2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "intel_batchbuffer.h"
37 #include "intel_buffers.h"
39 static const struct brw_tracked_state *gen4_atoms[] =
42 &brw_vs_prog, /* must do before GS prog, state base address. */
43 &brw_gs_prog, /* must do before state base address */
44 &brw_clip_prog, /* must do before state base address */
45 &brw_sf_prog, /* must do before state base address */
46 &brw_wm_prog, /* must do before state base address */
48 /* Once all the programs are done, we know how large urb entry
49 * sizes need to be and can decide if we need to change the urb
53 &brw_recalculate_urb_fence,
58 /* Surface state setup. Must come before the VS/WM unit. The binding
59 * table upload must be last.
61 &brw_vs_pull_constants,
62 &brw_wm_pull_constants,
63 &brw_renderbuffer_surfaces,
64 &brw_texture_surfaces,
65 &brw_vs_binding_table,
66 &brw_wm_binding_table,
70 /* These set up state for brw_psp_urb_cbs */
74 &brw_vs_unit, /* always required, enabled or not */
81 &brw_state_base_address,
83 &brw_binding_table_pointers,
84 &brw_blend_constant_color,
89 &brw_polygon_stipple_offset,
92 &brw_aa_line_parameters,
104 static const struct brw_tracked_state *gen6_atoms[] =
107 &brw_vs_prog, /* must do before state base address */
108 &brw_gs_prog, /* must do before state base address */
109 &brw_wm_prog, /* must do before state base address */
114 /* Command packets: */
115 &brw_invariant_state,
117 /* must do before binding table pointers, cc state ptrs */
118 &brw_state_base_address,
121 &gen6_viewport_state, /* must do after *_vp stages */
124 &gen6_blend_state, /* must do before cc unit */
125 &gen6_color_calc_state, /* must do before cc unit */
126 &gen6_depth_stencil_state, /* must do before cc unit */
127 &gen6_cc_state_pointers,
129 &gen6_vs_push_constants, /* Before vs_state */
130 &gen6_wm_push_constants, /* Before wm_state */
132 /* Surface state setup. Must come before the VS/WM unit. The binding
133 * table upload must be last.
135 &brw_vs_pull_constants,
136 &brw_vs_ubo_surfaces,
137 &brw_wm_pull_constants,
138 &brw_wm_ubo_surfaces,
139 &gen6_renderbuffer_surfaces,
140 &brw_texture_surfaces,
142 &brw_vs_binding_table,
143 &gen6_gs_binding_table,
144 &brw_wm_binding_table,
148 &gen6_multisample_state,
158 &gen6_binding_table_pointers,
162 &brw_polygon_stipple,
163 &brw_polygon_stipple_offset,
166 &brw_aa_line_parameters,
176 static const struct brw_tracked_state *gen7_atoms[] =
182 /* Command packets: */
183 &brw_invariant_state,
184 &gen7_push_constant_alloc,
186 /* must do before binding table pointers, cc state ptrs */
187 &brw_state_base_address,
190 &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
191 &gen7_sf_clip_viewport,
194 &gen6_blend_state, /* must do before cc unit */
195 &gen6_color_calc_state, /* must do before cc unit */
196 &gen6_depth_stencil_state, /* must do before cc unit */
197 &gen7_blend_state_pointer,
198 &gen7_cc_state_pointer,
199 &gen7_depth_stencil_state_pointer,
201 &gen6_vs_push_constants, /* Before vs_state */
202 &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
204 /* Surface state setup. Must come before the VS/WM unit. The binding
205 * table upload must be last.
207 &brw_vs_pull_constants,
208 &brw_vs_ubo_surfaces,
209 &brw_wm_pull_constants,
210 &brw_wm_ubo_surfaces,
211 &gen6_renderbuffer_surfaces,
212 &brw_texture_surfaces,
213 &brw_vs_binding_table,
214 &brw_wm_binding_table,
217 &gen6_multisample_state,
219 &gen7_disable_stages,
232 &brw_polygon_stipple,
233 &brw_polygon_stipple_offset,
236 &brw_aa_line_parameters,
248 void brw_init_state( struct brw_context *brw )
250 const struct brw_tracked_state **atoms;
253 brw_init_caches(brw);
255 if (brw->intel.gen >= 7) {
257 num_atoms = ARRAY_SIZE(gen7_atoms);
258 } else if (brw->intel.gen == 6) {
260 num_atoms = ARRAY_SIZE(gen6_atoms);
263 num_atoms = ARRAY_SIZE(gen4_atoms);
267 brw->num_atoms = num_atoms;
269 while (num_atoms--) {
270 assert((*atoms)->dirty.mesa |
271 (*atoms)->dirty.brw |
272 (*atoms)->dirty.cache);
273 assert((*atoms)->emit);
279 void brw_destroy_state( struct brw_context *brw )
281 brw_destroy_caches(brw);
284 /***********************************************************************
287 static GLuint check_state( const struct brw_state_flags *a,
288 const struct brw_state_flags *b )
290 return ((a->mesa & b->mesa) |
292 (a->cache & b->cache)) != 0;
295 static void accumulate_state( struct brw_state_flags *a,
296 const struct brw_state_flags *b )
300 a->cache |= b->cache;
304 static void xor_states( struct brw_state_flags *result,
305 const struct brw_state_flags *a,
306 const struct brw_state_flags *b )
308 result->mesa = a->mesa ^ b->mesa;
309 result->brw = a->brw ^ b->brw;
310 result->cache = a->cache ^ b->cache;
313 struct dirty_bit_map {
319 #define DEFINE_BIT(name) {name, #name, 0}
321 static struct dirty_bit_map mesa_bits[] = {
322 DEFINE_BIT(_NEW_MODELVIEW),
323 DEFINE_BIT(_NEW_PROJECTION),
324 DEFINE_BIT(_NEW_TEXTURE_MATRIX),
325 DEFINE_BIT(_NEW_COLOR),
326 DEFINE_BIT(_NEW_DEPTH),
327 DEFINE_BIT(_NEW_EVAL),
328 DEFINE_BIT(_NEW_FOG),
329 DEFINE_BIT(_NEW_HINT),
330 DEFINE_BIT(_NEW_LIGHT),
331 DEFINE_BIT(_NEW_LINE),
332 DEFINE_BIT(_NEW_PIXEL),
333 DEFINE_BIT(_NEW_POINT),
334 DEFINE_BIT(_NEW_POLYGON),
335 DEFINE_BIT(_NEW_POLYGONSTIPPLE),
336 DEFINE_BIT(_NEW_SCISSOR),
337 DEFINE_BIT(_NEW_STENCIL),
338 DEFINE_BIT(_NEW_TEXTURE),
339 DEFINE_BIT(_NEW_TRANSFORM),
340 DEFINE_BIT(_NEW_VIEWPORT),
341 DEFINE_BIT(_NEW_PACKUNPACK),
342 DEFINE_BIT(_NEW_ARRAY),
343 DEFINE_BIT(_NEW_RENDERMODE),
344 DEFINE_BIT(_NEW_BUFFERS),
345 DEFINE_BIT(_NEW_MULTISAMPLE),
346 DEFINE_BIT(_NEW_TRACK_MATRIX),
347 DEFINE_BIT(_NEW_PROGRAM),
348 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
352 static struct dirty_bit_map brw_bits[] = {
353 DEFINE_BIT(BRW_NEW_URB_FENCE),
354 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
355 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
356 DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
357 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
358 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
359 DEFINE_BIT(BRW_NEW_PRIMITIVE),
360 DEFINE_BIT(BRW_NEW_CONTEXT),
361 DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
362 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
363 DEFINE_BIT(BRW_NEW_PSP),
364 DEFINE_BIT(BRW_NEW_SURFACES),
365 DEFINE_BIT(BRW_NEW_INDICES),
366 DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
367 DEFINE_BIT(BRW_NEW_VERTICES),
368 DEFINE_BIT(BRW_NEW_BATCH),
369 DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
370 DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
371 DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
372 DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
373 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
377 static struct dirty_bit_map cache_bits[] = {
378 DEFINE_BIT(CACHE_NEW_BLEND_STATE),
379 DEFINE_BIT(CACHE_NEW_CC_VP),
380 DEFINE_BIT(CACHE_NEW_CC_UNIT),
381 DEFINE_BIT(CACHE_NEW_WM_PROG),
382 DEFINE_BIT(CACHE_NEW_SAMPLER),
383 DEFINE_BIT(CACHE_NEW_WM_UNIT),
384 DEFINE_BIT(CACHE_NEW_SF_PROG),
385 DEFINE_BIT(CACHE_NEW_SF_VP),
386 DEFINE_BIT(CACHE_NEW_SF_UNIT),
387 DEFINE_BIT(CACHE_NEW_VS_UNIT),
388 DEFINE_BIT(CACHE_NEW_VS_PROG),
389 DEFINE_BIT(CACHE_NEW_GS_UNIT),
390 DEFINE_BIT(CACHE_NEW_GS_PROG),
391 DEFINE_BIT(CACHE_NEW_CLIP_VP),
392 DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
393 DEFINE_BIT(CACHE_NEW_CLIP_PROG),
399 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
403 for (i = 0; i < 32; i++) {
404 if (bit_map[i].bit == 0)
407 if (bit_map[i].bit & bits)
413 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
417 for (i = 0; i < 32; i++) {
418 if (bit_map[i].bit == 0)
421 fprintf(stderr, "0x%08x: %12d (%s)\n",
422 bit_map[i].bit, bit_map[i].count, bit_map[i].name);
426 /***********************************************************************
429 void brw_upload_state(struct brw_context *brw)
431 struct gl_context *ctx = &brw->intel.ctx;
432 struct intel_context *intel = &brw->intel;
433 struct brw_state_flags *state = &brw->state.dirty;
435 static int dirty_count = 0;
437 state->mesa |= brw->intel.NewGLState;
438 brw->intel.NewGLState = 0;
440 if (brw->emit_state_always) {
446 if (brw->fragment_program != ctx->FragmentProgram._Current) {
447 brw->fragment_program = ctx->FragmentProgram._Current;
448 brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
451 if (brw->vertex_program != ctx->VertexProgram._Current) {
452 brw->vertex_program = ctx->VertexProgram._Current;
453 brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
456 if ((state->mesa | state->cache | state->brw) == 0)
459 intel_check_front_buffer_rendering(intel);
461 if (unlikely(INTEL_DEBUG)) {
462 /* Debug version which enforces various sanity checks on the
463 * state flags which are generated and checked to help ensure
464 * state atoms are ordered correctly in the list.
466 struct brw_state_flags examined, prev;
467 memset(&examined, 0, sizeof(examined));
470 for (i = 0; i < brw->num_atoms; i++) {
471 const struct brw_tracked_state *atom = brw->atoms[i];
472 struct brw_state_flags generated;
474 if (check_state(state, &atom->dirty)) {
478 accumulate_state(&examined, &atom->dirty);
480 /* generated = (prev ^ state)
481 * if (examined & generated)
484 xor_states(&generated, &prev, state);
485 assert(!check_state(&examined, &generated));
490 for (i = 0; i < brw->num_atoms; i++) {
491 const struct brw_tracked_state *atom = brw->atoms[i];
493 if (check_state(state, &atom->dirty)) {
499 if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
500 brw_update_dirty_count(mesa_bits, state->mesa);
501 brw_update_dirty_count(brw_bits, state->brw);
502 brw_update_dirty_count(cache_bits, state->cache);
503 if (dirty_count++ % 1000 == 0) {
504 brw_print_dirty_count(mesa_bits, state->mesa);
505 brw_print_dirty_count(brw_bits, state->brw);
506 brw_print_dirty_count(cache_bits, state->cache);
507 fprintf(stderr, "\n");
511 memset(state, 0, sizeof(*state));