2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "intel_batchbuffer.h"
37 #include "intel_buffers.h"
39 /* This is used to initialize brw->state.atoms[]. We could use this
40 * list directly except for a single atom, brw_constant_buffer, which
41 * has a .dirty value which changes according to the parameters of the
42 * current fragment and vertex programs, and so cannot be a static
45 static const struct brw_tracked_state *gen4_atoms[] =
56 /* Once all the programs are done, we know how large urb entry
57 * sizes need to be and can decide if we need to change the urb
61 &brw_recalculate_urb_fence,
65 &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
66 &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
68 &brw_vs_surfaces, /* must do before unit */
69 &brw_wm_constant_surface, /* must do before wm surfaces/bind bo */
70 &brw_wm_surfaces, /* must do before samplers and unit */
71 &brw_wm_binding_table,
77 &brw_vs_unit, /* always required, enabled or not */
84 &brw_state_base_address,
86 &brw_binding_table_pointers,
87 &brw_blend_constant_color,
92 &brw_polygon_stipple_offset,
95 &brw_aa_line_parameters,
107 const struct brw_tracked_state *gen6_atoms[] =
119 /* Command packets: */
120 &brw_invarient_state,
122 &gen6_viewport_state, /* must do after *_vp stages */
125 &gen6_blend_state, /* must do before cc unit */
126 &gen6_color_calc_state, /* must do before cc unit */
127 &gen6_depth_stencil_state, /* must do before cc unit */
128 &gen6_cc_state_pointers,
130 &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
131 &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
132 &gen6_wm_constants, /* Before wm_state */
134 &brw_vs_surfaces, /* must do before unit */
135 &brw_wm_constant_surface, /* must do before wm surfaces/bind bo */
136 &brw_wm_surfaces, /* must do before samplers and unit */
137 &brw_wm_binding_table,
149 &gen6_scissor_state_pointers,
151 &brw_state_base_address,
153 &gen6_binding_table_pointers,
157 &brw_polygon_stipple,
158 &brw_polygon_stipple_offset,
161 &brw_aa_line_parameters,
170 void brw_init_state( struct brw_context *brw )
172 brw_init_caches(brw);
176 void brw_destroy_state( struct brw_context *brw )
178 brw_destroy_caches(brw);
179 brw_destroy_batch_cache(brw);
182 /***********************************************************************
185 static GLboolean check_state( const struct brw_state_flags *a,
186 const struct brw_state_flags *b )
188 return ((a->mesa & b->mesa) ||
190 (a->cache & b->cache));
193 static void accumulate_state( struct brw_state_flags *a,
194 const struct brw_state_flags *b )
198 a->cache |= b->cache;
202 static void xor_states( struct brw_state_flags *result,
203 const struct brw_state_flags *a,
204 const struct brw_state_flags *b )
206 result->mesa = a->mesa ^ b->mesa;
207 result->brw = a->brw ^ b->brw;
208 result->cache = a->cache ^ b->cache;
212 brw_clear_validated_bos(struct brw_context *brw)
216 /* Clear the last round of validated bos */
217 for (i = 0; i < brw->state.validated_bo_count; i++) {
218 drm_intel_bo_unreference(brw->state.validated_bos[i]);
219 brw->state.validated_bos[i] = NULL;
221 brw->state.validated_bo_count = 0;
224 struct dirty_bit_map {
230 #define DEFINE_BIT(name) {name, #name, 0}
232 static struct dirty_bit_map mesa_bits[] = {
233 DEFINE_BIT(_NEW_MODELVIEW),
234 DEFINE_BIT(_NEW_PROJECTION),
235 DEFINE_BIT(_NEW_TEXTURE_MATRIX),
236 DEFINE_BIT(_NEW_ACCUM),
237 DEFINE_BIT(_NEW_COLOR),
238 DEFINE_BIT(_NEW_DEPTH),
239 DEFINE_BIT(_NEW_EVAL),
240 DEFINE_BIT(_NEW_FOG),
241 DEFINE_BIT(_NEW_HINT),
242 DEFINE_BIT(_NEW_LIGHT),
243 DEFINE_BIT(_NEW_LINE),
244 DEFINE_BIT(_NEW_PIXEL),
245 DEFINE_BIT(_NEW_POINT),
246 DEFINE_BIT(_NEW_POLYGON),
247 DEFINE_BIT(_NEW_POLYGONSTIPPLE),
248 DEFINE_BIT(_NEW_SCISSOR),
249 DEFINE_BIT(_NEW_STENCIL),
250 DEFINE_BIT(_NEW_TEXTURE),
251 DEFINE_BIT(_NEW_TRANSFORM),
252 DEFINE_BIT(_NEW_VIEWPORT),
253 DEFINE_BIT(_NEW_PACKUNPACK),
254 DEFINE_BIT(_NEW_ARRAY),
255 DEFINE_BIT(_NEW_RENDERMODE),
256 DEFINE_BIT(_NEW_BUFFERS),
257 DEFINE_BIT(_NEW_MULTISAMPLE),
258 DEFINE_BIT(_NEW_TRACK_MATRIX),
259 DEFINE_BIT(_NEW_PROGRAM),
260 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
264 static struct dirty_bit_map brw_bits[] = {
265 DEFINE_BIT(BRW_NEW_URB_FENCE),
266 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
267 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
268 DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
269 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
270 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
271 DEFINE_BIT(BRW_NEW_PRIMITIVE),
272 DEFINE_BIT(BRW_NEW_CONTEXT),
273 DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
274 DEFINE_BIT(BRW_NEW_PSP),
275 DEFINE_BIT(BRW_NEW_WM_SURFACES),
276 DEFINE_BIT(BRW_NEW_BINDING_TABLE),
277 DEFINE_BIT(BRW_NEW_INDICES),
278 DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
279 DEFINE_BIT(BRW_NEW_VERTICES),
280 DEFINE_BIT(BRW_NEW_BATCH),
281 DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
285 static struct dirty_bit_map cache_bits[] = {
286 DEFINE_BIT(CACHE_NEW_BLEND_STATE),
287 DEFINE_BIT(CACHE_NEW_CC_VP),
288 DEFINE_BIT(CACHE_NEW_CC_UNIT),
289 DEFINE_BIT(CACHE_NEW_WM_PROG),
290 DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR),
291 DEFINE_BIT(CACHE_NEW_SAMPLER),
292 DEFINE_BIT(CACHE_NEW_WM_UNIT),
293 DEFINE_BIT(CACHE_NEW_SF_PROG),
294 DEFINE_BIT(CACHE_NEW_SF_VP),
295 DEFINE_BIT(CACHE_NEW_SF_UNIT),
296 DEFINE_BIT(CACHE_NEW_VS_UNIT),
297 DEFINE_BIT(CACHE_NEW_VS_PROG),
298 DEFINE_BIT(CACHE_NEW_GS_UNIT),
299 DEFINE_BIT(CACHE_NEW_GS_PROG),
300 DEFINE_BIT(CACHE_NEW_CLIP_VP),
301 DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
302 DEFINE_BIT(CACHE_NEW_CLIP_PROG),
308 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
312 for (i = 0; i < 32; i++) {
313 if (bit_map[i].bit == 0)
316 if (bit_map[i].bit & bits)
322 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
326 for (i = 0; i < 32; i++) {
327 if (bit_map[i].bit == 0)
330 fprintf(stderr, "0x%08x: %12d (%s)\n",
331 bit_map[i].bit, bit_map[i].count, bit_map[i].name);
335 /***********************************************************************
338 void brw_validate_state( struct brw_context *brw )
340 struct gl_context *ctx = &brw->intel.ctx;
341 struct intel_context *intel = &brw->intel;
342 struct brw_state_flags *state = &brw->state.dirty;
344 const struct brw_tracked_state **atoms;
347 brw_clear_validated_bos(brw);
349 state->mesa |= brw->intel.NewGLState;
350 brw->intel.NewGLState = 0;
352 brw_add_validated_bo(brw, intel->batch->buf);
354 if (intel->gen >= 6) {
356 num_atoms = ARRAY_SIZE(gen6_atoms);
359 num_atoms = ARRAY_SIZE(gen4_atoms);
362 if (brw->emit_state_always) {
368 if (brw->fragment_program != ctx->FragmentProgram._Current) {
369 brw->fragment_program = ctx->FragmentProgram._Current;
370 brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
373 if (brw->vertex_program != ctx->VertexProgram._Current) {
374 brw->vertex_program = ctx->VertexProgram._Current;
375 brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
378 if (state->mesa == 0 &&
383 if (brw->state.dirty.brw & BRW_NEW_CONTEXT)
384 brw_clear_batch_cache(brw);
386 brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
388 /* do prepare stage for all atoms */
389 for (i = 0; i < num_atoms; i++) {
390 const struct brw_tracked_state *atom = atoms[i];
392 if (brw->intel.Fallback)
395 if (check_state(state, &atom->dirty)) {
402 intel_check_front_buffer_rendering(intel);
404 /* Make sure that the textures which are referenced by the current
405 * brw fragment program are actually present/valid.
406 * If this fails, we can experience GPU lock-ups.
409 const struct brw_fragment_program *fp;
410 fp = brw_fragment_program_const(brw->fragment_program);
412 assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
413 == fp->tex_units_used);
419 void brw_upload_state(struct brw_context *brw)
421 struct intel_context *intel = &brw->intel;
422 struct brw_state_flags *state = &brw->state.dirty;
424 static int dirty_count = 0;
425 const struct brw_tracked_state **atoms;
428 if (intel->gen >= 6) {
430 num_atoms = ARRAY_SIZE(gen6_atoms);
433 num_atoms = ARRAY_SIZE(gen4_atoms);
436 brw_clear_validated_bos(brw);
438 if (unlikely(INTEL_DEBUG)) {
439 /* Debug version which enforces various sanity checks on the
440 * state flags which are generated and checked to help ensure
441 * state atoms are ordered correctly in the list.
443 struct brw_state_flags examined, prev;
444 memset(&examined, 0, sizeof(examined));
447 for (i = 0; i < num_atoms; i++) {
448 const struct brw_tracked_state *atom = atoms[i];
449 struct brw_state_flags generated;
451 assert(atom->dirty.mesa ||
455 if (brw->intel.Fallback)
458 if (check_state(state, &atom->dirty)) {
464 accumulate_state(&examined, &atom->dirty);
466 /* generated = (prev ^ state)
467 * if (examined & generated)
470 xor_states(&generated, &prev, state);
471 assert(!check_state(&examined, &generated));
476 for (i = 0; i < num_atoms; i++) {
477 const struct brw_tracked_state *atom = atoms[i];
479 if (brw->intel.Fallback)
482 if (check_state(state, &atom->dirty)) {
490 if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
491 brw_update_dirty_count(mesa_bits, state->mesa);
492 brw_update_dirty_count(brw_bits, state->brw);
493 brw_update_dirty_count(cache_bits, state->cache);
494 if (dirty_count++ % 1000 == 0) {
495 brw_print_dirty_count(mesa_bits, state->mesa);
496 brw_print_dirty_count(brw_bits, state->brw);
497 brw_print_dirty_count(cache_bits, state->cache);
498 fprintf(stderr, "\n");
502 if (!brw->intel.Fallback)
503 memset(state, 0, sizeof(*state));