src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 static const struct brw_tracked_state *gen4_atoms[] =
  40 {
  41    &brw_wm_input_sizes,
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_gs_prog, /* must do before state base address */
  44    &brw_clip_prog, /* must do before state base address */
  45    &brw_sf_prog, /* must do before state base address */
  46    &brw_wm_prog, /* must do before state base address */
  47
  48    /* Once all the programs are done, we know how large urb entry
  49     * sizes need to be and can decide if we need to change the urb
  50     * layout.
  51     */
  52    &brw_curbe_offsets,
  53    &brw_recalculate_urb_fence,
  54
  55    &brw_cc_vp,
  56    &brw_cc_unit,
  57
  58    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  59     * table upload must be last.
  60     */
  61    &brw_vs_pull_constants,
  62    &brw_wm_pull_constants,
  63    &brw_renderbuffer_surfaces,
  64    &brw_texture_surfaces,
  65    &brw_vs_binding_table,
  66    &brw_wm_binding_table,
  67
  68    &brw_samplers,
  69
  70    /* These set up state for brw_psp_urb_cbs */
  71    &brw_wm_unit,
  72    &brw_sf_vp,
  73    &brw_sf_unit,
  74    &brw_vs_unit,                /* always required, enabled or not */
  75    &brw_clip_unit,
  76    &brw_gs_unit,
  77
  78    /* Command packets:
  79     */
  80    &brw_invariant_state,
  81    &brw_state_base_address,
  82
  83    &brw_binding_table_pointers,
  84    &brw_blend_constant_color,
  85
  86    &brw_depthbuffer,
  87
  88    &brw_polygon_stipple,
  89    &brw_polygon_stipple_offset,
  90
  91    &brw_line_stipple,
  92    &brw_aa_line_parameters,
  93
  94    &brw_psp_urb_cbs,
  95
  96    &brw_drawing_rect,
  97    &brw_indices,
  98    &brw_index_buffer,
  99    &brw_vertices,
 100
 101    &brw_constant_buffer
 102 };
 103
 104 static const struct brw_tracked_state *gen6_atoms[] =
 105 {
 106    &brw_wm_input_sizes,
 107    &brw_vs_prog, /* must do before state base address */
 108    &brw_gs_prog, /* must do before state base address */
 109    &brw_wm_prog, /* must do before state base address */
 110
 111    &gen6_clip_vp,
 112    &gen6_sf_vp,
 113
 114    /* Command packets: */
 115    &brw_invariant_state,
 116
 117    /* must do before binding table pointers, cc state ptrs */
 118    &brw_state_base_address,
 119
 120    &brw_cc_vp,
 121    &gen6_viewport_state,        /* must do after *_vp stages */
 122
 123    &gen6_urb,
 124    &gen6_blend_state,           /* must do before cc unit */
 125    &gen6_color_calc_state,      /* must do before cc unit */
 126    &gen6_depth_stencil_state,   /* must do before cc unit */
 127    &gen6_cc_state_pointers,
 128
 129    &gen6_vs_push_constants, /* Before vs_state */
 130    &gen6_wm_push_constants, /* Before wm_state */
 131
 132    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 133     * table upload must be last.
 134     */
 135    &brw_vs_pull_constants,
 136    &brw_vs_ubo_surfaces,
 137    &brw_wm_pull_constants,
 138    &brw_wm_ubo_surfaces,
 139    &gen6_renderbuffer_surfaces,
 140    &brw_texture_surfaces,
 141    &gen6_sol_surface,
 142    &brw_vs_binding_table,
 143    &gen6_gs_binding_table,
 144    &brw_wm_binding_table,
 145
 146    &brw_samplers,
 147    &gen6_sampler_state,
 148    &gen6_multisample_state,
 149
 150    &gen6_vs_state,
 151    &gen6_gs_state,
 152    &gen6_clip_state,
 153    &gen6_sf_state,
 154    &gen6_wm_state,
 155
 156    &gen6_scissor_state,
 157
 158    &gen6_binding_table_pointers,
 159
 160    &brw_depthbuffer,
 161
 162    &brw_polygon_stipple,
 163    &brw_polygon_stipple_offset,
 164
 165    &brw_line_stipple,
 166    &brw_aa_line_parameters,
 167
 168    &brw_drawing_rect,
 169
 170    &gen6_sol_indices,
 171    &brw_indices,
 172    &brw_index_buffer,
 173    &brw_vertices,
 174 };
 175
 176 static const struct brw_tracked_state *gen7_atoms[] =
 177 {
 178    &brw_wm_input_sizes,
 179    &brw_vs_prog,
 180    &brw_wm_prog,
 181
 182    /* Command packets: */
 183    &brw_invariant_state,
 184    &gen7_push_constant_alloc,
 185
 186    /* must do before binding table pointers, cc state ptrs */
 187    &brw_state_base_address,
 188
 189    &brw_cc_vp,
 190    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 191    &gen7_sf_clip_viewport,
 192
 193    &gen7_urb,
 194    &gen6_blend_state,           /* must do before cc unit */
 195    &gen6_color_calc_state,      /* must do before cc unit */
 196    &gen6_depth_stencil_state,   /* must do before cc unit */
 197    &gen7_blend_state_pointer,
 198    &gen7_cc_state_pointer,
 199    &gen7_depth_stencil_state_pointer,
 200
 201    &gen6_vs_push_constants, /* Before vs_state */
 202    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 203
 204    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 205     * table upload must be last.
 206     */
 207    &brw_vs_pull_constants,
 208    &brw_vs_ubo_surfaces,
 209    &brw_wm_pull_constants,
 210    &brw_wm_ubo_surfaces,
 211    &gen6_renderbuffer_surfaces,
 212    &brw_texture_surfaces,
 213    &brw_vs_binding_table,
 214    &brw_wm_binding_table,
 215
 216    &gen7_samplers,
 217    &gen6_multisample_state,
 218
 219    &gen7_disable_stages,
 220    &gen7_vs_state,
 221    &gen7_sol_state,
 222    &gen7_clip_state,
 223    &gen7_sbe_state,
 224    &gen7_sf_state,
 225    &gen7_wm_state,
 226    &gen7_ps_state,
 227
 228    &gen6_scissor_state,
 229
 230    &gen7_depthbuffer,
 231
 232    &brw_polygon_stipple,
 233    &brw_polygon_stipple_offset,
 234
 235    &brw_line_stipple,
 236    &brw_aa_line_parameters,
 237
 238    &brw_drawing_rect,
 239
 240    &brw_indices,
 241    &brw_index_buffer,
 242    &brw_vertices,
 243
 244    &haswell_cut_index,
 245 };
 246
 247
 248 void brw_init_state( struct brw_context *brw )
 249 {
 250    const struct brw_tracked_state **atoms;
 251    int num_atoms;
 252
 253    brw_init_caches(brw);
 254
 255    if (brw->intel.gen >= 7) {
 256       atoms = gen7_atoms;
 257       num_atoms = ARRAY_SIZE(gen7_atoms);
 258    } else if (brw->intel.gen == 6) {
 259       atoms = gen6_atoms;
 260       num_atoms = ARRAY_SIZE(gen6_atoms);
 261    } else {
 262       atoms = gen4_atoms;
 263       num_atoms = ARRAY_SIZE(gen4_atoms);
 264    }
 265
 266    brw->atoms = atoms;
 267    brw->num_atoms = num_atoms;
 268
 269    while (num_atoms--) {
 270       assert((*atoms)->dirty.mesa |
 271              (*atoms)->dirty.brw |
 272              (*atoms)->dirty.cache);
 273       assert((*atoms)->emit);
 274       atoms++;
 275    }
 276 }
 277
 278
 279 void brw_destroy_state( struct brw_context *brw )
 280 {
 281    brw_destroy_caches(brw);
 282 }
 283
 284 /***********************************************************************
 285  */
 286
 287 static GLuint check_state( const struct brw_state_flags *a,
 288                            const struct brw_state_flags *b )
 289 {
 290    return ((a->mesa & b->mesa) |
 291            (a->brw & b->brw) |
 292            (a->cache & b->cache)) != 0;
 293 }
 294
 295 static void accumulate_state( struct brw_state_flags *a,
 296                               const struct brw_state_flags *b )
 297 {
 298    a->mesa |= b->mesa;
 299    a->brw |= b->brw;
 300    a->cache |= b->cache;
 301 }
 302
 303
 304 static void xor_states( struct brw_state_flags *result,
 305                              const struct brw_state_flags *a,
 306                               const struct brw_state_flags *b )
 307 {
 308    result->mesa = a->mesa ^ b->mesa;
 309    result->brw = a->brw ^ b->brw;
 310    result->cache = a->cache ^ b->cache;
 311 }
 312
 313 struct dirty_bit_map {
 314    uint32_t bit;
 315    char *name;
 316    uint32_t count;
 317 };
 318
 319 #define DEFINE_BIT(name) {name, #name, 0}
 320
 321 static struct dirty_bit_map mesa_bits[] = {
 322    DEFINE_BIT(_NEW_MODELVIEW),
 323    DEFINE_BIT(_NEW_PROJECTION),
 324    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 325    DEFINE_BIT(_NEW_COLOR),
 326    DEFINE_BIT(_NEW_DEPTH),
 327    DEFINE_BIT(_NEW_EVAL),
 328    DEFINE_BIT(_NEW_FOG),
 329    DEFINE_BIT(_NEW_HINT),
 330    DEFINE_BIT(_NEW_LIGHT),
 331    DEFINE_BIT(_NEW_LINE),
 332    DEFINE_BIT(_NEW_PIXEL),
 333    DEFINE_BIT(_NEW_POINT),
 334    DEFINE_BIT(_NEW_POLYGON),
 335    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 336    DEFINE_BIT(_NEW_SCISSOR),
 337    DEFINE_BIT(_NEW_STENCIL),
 338    DEFINE_BIT(_NEW_TEXTURE),
 339    DEFINE_BIT(_NEW_TRANSFORM),
 340    DEFINE_BIT(_NEW_VIEWPORT),
 341    DEFINE_BIT(_NEW_PACKUNPACK),
 342    DEFINE_BIT(_NEW_ARRAY),
 343    DEFINE_BIT(_NEW_RENDERMODE),
 344    DEFINE_BIT(_NEW_BUFFERS),
 345    DEFINE_BIT(_NEW_MULTISAMPLE),
 346    DEFINE_BIT(_NEW_TRACK_MATRIX),
 347    DEFINE_BIT(_NEW_PROGRAM),
 348    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 349    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 350    DEFINE_BIT(_NEW_FRAG_CLAMP),
 351    DEFINE_BIT(_NEW_TRANSFORM_FEEDBACK),
 352    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 353    {0, 0, 0}
 354 };
 355
 356 static struct dirty_bit_map brw_bits[] = {
 357    DEFINE_BIT(BRW_NEW_URB_FENCE),
 358    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 359    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 360    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 361    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 362    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 363    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 364    DEFINE_BIT(BRW_NEW_CONTEXT),
 365    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 366    DEFINE_BIT(BRW_NEW_PSP),
 367    DEFINE_BIT(BRW_NEW_SURFACES),
 368    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 369    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 370    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 371    DEFINE_BIT(BRW_NEW_INDICES),
 372    DEFINE_BIT(BRW_NEW_VERTICES),
 373    DEFINE_BIT(BRW_NEW_BATCH),
 374    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 375    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 376    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 377    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 378    DEFINE_BIT(BRW_NEW_SOL_INDICES),
 379    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 380    {0, 0, 0}
 381 };
 382
 383 static struct dirty_bit_map cache_bits[] = {
 384    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 385    DEFINE_BIT(CACHE_NEW_DEPTH_STENCIL_STATE),
 386    DEFINE_BIT(CACHE_NEW_COLOR_CALC_STATE),
 387    DEFINE_BIT(CACHE_NEW_CC_VP),
 388    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 389    DEFINE_BIT(CACHE_NEW_WM_PROG),
 390    DEFINE_BIT(CACHE_NEW_SAMPLER),
 391    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 392    DEFINE_BIT(CACHE_NEW_SF_PROG),
 393    DEFINE_BIT(CACHE_NEW_SF_VP),
 394    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 395    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 396    DEFINE_BIT(CACHE_NEW_VS_PROG),
 397    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 398    DEFINE_BIT(CACHE_NEW_GS_PROG),
 399    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 400    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 401    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 402    {0, 0, 0}
 403 };
 404
 405
 406 static void
 407 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 408 {
 409    int i;
 410
 411    for (i = 0; i < 32; i++) {
 412       if (bit_map[i].bit == 0)
 413          return;
 414
 415       if (bit_map[i].bit & bits)
 416          bit_map[i].count++;
 417    }
 418 }
 419
 420 static void
 421 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 422 {
 423    int i;
 424
 425    for (i = 0; i < 32; i++) {
 426       if (bit_map[i].bit == 0)
 427          return;
 428
 429       fprintf(stderr, "0x%08x: %12d (%s)\n",
 430               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 431    }
 432 }
 433
 434 /***********************************************************************
 435  * Emit all state:
 436  */
 437 void brw_upload_state(struct brw_context *brw)
 438 {
 439    struct gl_context *ctx = &brw->intel.ctx;
 440    struct intel_context *intel = &brw->intel;
 441    struct brw_state_flags *state = &brw->state.dirty;
 442    int i;
 443    static int dirty_count = 0;
 444
 445    state->mesa |= brw->intel.NewGLState;
 446    brw->intel.NewGLState = 0;
 447
 448    if (brw->emit_state_always) {
 449       state->mesa |= ~0;
 450       state->brw |= ~0;
 451       state->cache |= ~0;
 452    }
 453
 454    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 455       brw->fragment_program = ctx->FragmentProgram._Current;
 456       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 457    }
 458
 459    if (brw->vertex_program != ctx->VertexProgram._Current) {
 460       brw->vertex_program = ctx->VertexProgram._Current;
 461       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 462    }
 463
 464    if ((state->mesa | state->cache | state->brw) == 0)
 465       return;
 466
 467    intel_check_front_buffer_rendering(intel);
 468
 469    if (unlikely(INTEL_DEBUG)) {
 470       /* Debug version which enforces various sanity checks on the
 471        * state flags which are generated and checked to help ensure
 472        * state atoms are ordered correctly in the list.
 473        */
 474       struct brw_state_flags examined, prev;
 475       memset(&examined, 0, sizeof(examined));
 476       prev = *state;
 477
 478       for (i = 0; i < brw->num_atoms; i++) {
 479          const struct brw_tracked_state *atom = brw->atoms[i];
 480          struct brw_state_flags generated;
 481
 482          if (check_state(state, &atom->dirty)) {
 483             atom->emit(brw);
 484          }
 485
 486          accumulate_state(&examined, &atom->dirty);
 487
 488          /* generated = (prev ^ state)
 489           * if (examined & generated)
 490           *     fail;
 491           */
 492          xor_states(&generated, &prev, state);
 493          assert(!check_state(&examined, &generated));
 494          prev = *state;
 495       }
 496    }
 497    else {
 498       for (i = 0; i < brw->num_atoms; i++) {
 499          const struct brw_tracked_state *atom = brw->atoms[i];
 500
 501          if (check_state(state, &atom->dirty)) {
 502             atom->emit(brw);
 503          }
 504       }
 505    }
 506
 507    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 508       brw_update_dirty_count(mesa_bits, state->mesa);
 509       brw_update_dirty_count(brw_bits, state->brw);
 510       brw_update_dirty_count(cache_bits, state->cache);
 511       if (dirty_count++ % 1000 == 0) {
 512          brw_print_dirty_count(mesa_bits, state->mesa);
 513          brw_print_dirty_count(brw_bits, state->brw);
 514          brw_print_dirty_count(cache_bits, state->cache);
 515          fprintf(stderr, "\n");
 516       }
 517    }
 518
 519    memset(state, 0, sizeof(*state));
 520 }