source/src/vm/mc6801.cpp

   1 /*
   2         Skelton for retropc emulator
   3
   4         Origin : MAME 0.142
   5         Author : Takeda.Toshiya
   6         Date  : 2011.04.23-
   7
   8         [ MC6801 ]
   9 */
  10 #if defined(_MSC_VER) && (_MSC_VER >= 1400)
  11 #pragma warning( disable : 4996 )
  12 #endif
  13
  14 #include "mc6801.h"
  15 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  16 #include "../fifo.h"
  17 //#endif
  18 //#ifdef USE_DEBUGGER
  19 #include "debugger.h"
  20 #include "mc6800_consts.h"
  21 #include "mc6801_consts.h"
  22 //#endif
  23 /****************************************************************************/
  24 /* memory                                                                   */
  25 /****************************************************************************/
  26
  27 uint32_t MC6801::RM(uint32_t Addr)
  28 {
  29 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  30         if(Addr < 0x20) {
  31                 return mc6801_io_r(Addr);
  32         } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
  33                 return ram[Addr & 0x7f];
  34         }
  35 //#endif
  36         return d_mem->read_data8(Addr);
  37 }
  38
  39 void MC6801::WM(uint32_t Addr, uint32_t Value)
  40 {
  41 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  42         if(Addr < 0x20) {
  43                 mc6801_io_w(Addr, Value);
  44         } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
  45                 ram[Addr & 0x7f] = Value;
  46         } else
  47 //#endif
  48         d_mem->write_data8(Addr, Value);
  49 }
  50 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  51
  52 uint32_t MC6801::mc6801_io_r(uint32_t offset)
  53 {
  54         switch (offset) {
  55         case 0x00:
  56                 // port1 data direction register
  57                 return port[0].ddr;
  58         case 0x01:
  59                 // port2 data direction register
  60                 return port[1].ddr;
  61         case 0x02:
  62                 // port1 data register
  63                 return (port[0].rreg & ~port[0].ddr) | (port[0].wreg & port[0].ddr);
  64         case 0x03:
  65                 // port2 data register
  66                 return (port[1].rreg & ~port[1].ddr) | (port[1].wreg & port[1].ddr);
  67         case 0x04:
  68                 // port3 data direction register (write only???)
  69                 return port[2].ddr;
  70         case 0x05:
  71                 // port4 data direction register
  72                 return port[3].ddr;
  73         case 0x06:
  74                 // port3 data register
  75                 if(p3csr_is3_flag_read) {
  76                         p3csr_is3_flag_read = false;
  77                         p3csr &= ~P3CSR_IS3_FLAG;
  78                 }
  79                 if(port[2].latched) {
  80                         port[2].latched = false;
  81                         return (port[2].latched_data & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
  82                 }
  83                 return (port[2].rreg & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
  84         case 0x07:
  85                 // port4 data register
  86                 return (port[3].rreg & ~port[3].ddr) | (port[3].wreg & port[3].ddr);
  87         case 0x08:
  88                 // timer control register
  89                 pending_tcsr = 0;
  90                 return tcsr;
  91         case 0x09:
  92                 // free running counter (msb)
  93                 if(!(pending_tcsr & TCSR_TOF)) {
  94                         tcsr &= ~TCSR_TOF;
  95                 }
  96                 return counter.b.h;
  97         case 0x0a:
  98                 // free running counter (lsb)
  99                 return counter.b.l;
 100         case 0x0b:
 101                 // output compare register (msb)
 102                 if(!(pending_tcsr & TCSR_OCF)) {
 103                         tcsr &= ~TCSR_OCF;
 104                 }
 105                 return output_compare.b.h;
 106         case 0x0c:
 107                 // output compare register (lsb)
 108                 if(!(pending_tcsr & TCSR_OCF)) {
 109                         tcsr &= ~TCSR_OCF;
 110                 }
 111                 return output_compare.b.l;
 112         case 0x0d:
 113                 // input capture register (msb)
 114                 if(!(pending_tcsr & TCSR_ICF)) {
 115                         tcsr &= ~TCSR_ICF;
 116                 }
 117                 return (input_capture >> 0) & 0xff;
 118         case 0x0e:
 119                 // input capture register (lsb)
 120                 return (input_capture >> 8) & 0xff;
 121         case 0x0f:
 122                 // port3 control/status register
 123                 p3csr_is3_flag_read = true;
 124                 return p3csr;
 125         case 0x10:
 126                 // rate and mode control register
 127                 return rmcr;
 128         case 0x11:
 129                 if(trcsr & TRCSR_TDRE) {
 130                         trcsr_read_tdre = true;
 131                 }
 132                 if(trcsr & TRCSR_ORFE) {
 133                         trcsr_read_orfe = true;
 134                 }
 135                 if(trcsr & TRCSR_RDRF) {
 136                         trcsr_read_rdrf = true;
 137                 }
 138                 return trcsr;
 139         case 0x12:
 140                 // receive data register
 141                 if(trcsr_read_orfe) {
 142                         trcsr_read_orfe = false;
 143                         trcsr &= ~TRCSR_ORFE;
 144                 }
 145                 if(trcsr_read_rdrf) {
 146                         trcsr_read_rdrf = false;
 147                         trcsr &= ~TRCSR_RDRF;
 148                 }
 149                 return rdr;
 150         case 0x13:
 151                 // transmit data register
 152                 return tdr;
 153         case 0x14:
 154                 // ram control register
 155                 return (ram_ctrl & 0x40) | 0x3f;
 156         }
 157         return 0;
 158 }
 159
 160 void MC6801::mc6801_io_w(uint32_t offset, uint32_t data)
 161 {
 162         switch(offset) {
 163         case 0x00:
 164                 // port1 data direction register
 165                 port[0].ddr = data;
 166                 break;
 167         case 0x01:
 168                 // port2 data direction register
 169                 port[1].ddr = data;
 170                 break;
 171         case 0x02:
 172                 // port1 data register
 173                 if(port[0].wreg != data || port[0].first_write) {
 174                         write_signals(&port[0].outputs, data);
 175                         port[0].wreg = data;
 176                         port[0].first_write = false;
 177                 }
 178                 break;
 179         case 0x03:
 180                 // port2 data register
 181                 if(port[1].wreg != data || port[1].first_write) {
 182                         write_signals(&port[1].outputs, data);
 183                         port[1].wreg = data;
 184                         port[1].first_write = false;
 185                 }
 186                 break;
 187         case 0x04:
 188                 // port3 data direction register
 189                 port[2].ddr = data;
 190                 break;
 191         case 0x05:
 192                 // port4 data direction register
 193                 port[3].ddr = data;
 194                 break;
 195         case 0x06:
 196                 // port3 data register
 197                 if(p3csr_is3_flag_read) {
 198                         p3csr_is3_flag_read = false;
 199                         p3csr &= ~P3CSR_IS3_FLAG;
 200                 }
 201                 if(port[2].wreg != data || port[2].first_write) {
 202                         write_signals(&port[2].outputs, data);
 203                         port[2].wreg = data;
 204                         port[2].first_write = false;
 205                 }
 206                 break;
 207         case 0x07:
 208                 // port4 data register
 209                 if(port[3].wreg != data || port[3].first_write) {
 210                         write_signals(&port[3].outputs, data);
 211                         port[3].wreg = data;
 212                         port[3].first_write = false;
 213                 }
 214                 break;
 215         case 0x08:
 216                 // timer control/status register
 217                 tcsr = data;
 218                 pending_tcsr &= tcsr;
 219                 break;
 220         case 0x09:
 221                 // free running counter (msb)
 222 //#ifdef HAS_HD6301
 223 //              latch09 = data & 0xff;
 224 //#endif
 225                 CT = 0xfff8;
 226                 TOH = CTH;
 227                 MODIFIED_counters;
 228                 break;
 229 //#ifdef HAS_HD6301
 230 //      case 0x0a:
 231 //              // free running counter (lsb)
 232 //              CT = (latch09 << 8) | (data & 0xff);
 233 //              TOH = CTH;
 234 //              MODIFIED_counters;
 235 ///             break;
 236 //#endif
 237         case 0x0b:
 238                 // output compare register (msb)
 239                 if(output_compare.b.h != data) {
 240                         output_compare.b.h = data;
 241                         MODIFIED_counters;
 242                 }
 243         tcsr &=~TCSR_OCF;
 244                 break;
 245         case 0x0c:
 246                 // output compare register (lsb)
 247                 if(output_compare.b.l != data) {
 248                         output_compare.b.l = data;
 249                         MODIFIED_counters;
 250                 }
 251         tcsr &=~TCSR_OCF;
 252                 break;
 253         case 0x0f:
 254                 // port3 control/status register
 255                 p3csr = (p3csr & P3CSR_IS3_FLAG) | (data & ~P3CSR_IS3_FLAG);
 256                 break;
 257         case 0x10:
 258                 // rate and mode control register
 259                 rmcr = data;
 260                 break;
 261         case 0x11:
 262                 // transmit/receive control/status register
 263                 trcsr = (trcsr & 0xe0) | (data & 0x1f);
 264                 break;
 265         case 0x13:
 266                 // transmit data register
 267                 if(trcsr_read_tdre) {
 268                         trcsr_read_tdre = false;
 269                         trcsr &= ~TRCSR_TDRE;
 270                 }
 271                 tdr = data;
 272                 break;
 273         case 0x14:
 274                 // ram control register
 275                 ram_ctrl = data;
 276                 break;
 277         }
 278 }
 279
 280 void MC6801::increment_counter(int amount)
 281 {
 282         total_icount += amount;
 283         icount -= amount;
 284
 285         // timer
 286         if((CTD += amount) >= timer_next) {
 287                 /* OCI */
 288                 if( CTD >= OCD) {
 289                         OCH++;  // next IRQ point
 290                         tcsr |= TCSR_OCF;
 291                         pending_tcsr |= TCSR_OCF;
 292                 }
 293                 /* TOI */
 294                 if( CTD >= TOD) {
 295                         TOH++;  // next IRQ point
 296                         tcsr |= TCSR_TOF;
 297                         pending_tcsr |= TCSR_TOF;
 298                 }
 299                 /* set next event */
 300                 SET_TIMER_EVENT;
 301         }
 302
 303         // serial i/o
 304         if((sio_counter -= amount) <= 0) {
 305                 if((trcsr & TRCSR_TE) && !(trcsr & TRCSR_TDRE)) {
 306                         write_signals(&outputs_sio, tdr);
 307                         trcsr |= TRCSR_TDRE;
 308                 }
 309                 if((trcsr & TRCSR_RE) && !recv_buffer->empty()) {
 310                         if(trcsr & TRCSR_WU) {
 311                                 // skip 10 bits
 312                                 trcsr &= ~TRCSR_WU;
 313                                 recv_buffer->read();
 314                         } else if(!(trcsr & TRCSR_RDRF)) {
 315                                 // note: wait reveived data is read by cpu, so overrun framing error never occurs
 316                                 rdr = recv_buffer->read();
 317                                 trcsr |= TRCSR_RDRF;
 318                         }
 319                 }
 320                 sio_counter += RMCR_SS[rmcr & 3];
 321         }
 322 }
 323 //#else
 324
 325
 326 void MC6801::initialize()
 327 {
 328         MC6800::initialize();
 329
 330 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 331         recv_buffer = new FIFO(0x10000);
 332         ram_ctrl = 0xc0;
 333 //#endif
 334 //#ifdef USE_DEBUGGER
 335         if(__USE_DEBUGGER) {
 336                 d_mem_stored = d_mem;
 337                 d_debugger->set_context_mem(d_mem);
 338         }
 339 //#endif
 340 }
 341 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 342 void MC6801::release()
 343 {
 344         recv_buffer->release();
 345         delete recv_buffer;
 346 }
 347 //#endif
 348
 349 void MC6801::reset()
 350 {
 351         CC = 0xc0;
 352         SEI; /* IRQ disabled */
 353         PCD = RM16(0xfffe);
 354         S = X = D = EA = 0;
 355
 356         wai_state = 0;
 357         int_state = 0;
 358
 359         icount = 0;
 360
 361 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 362         for(int i = 0; i < 4; i++) {
 363                 port[i].ddr = 0x00;
 364                 port[i].first_write = true;
 365                 port[i].latched = false;
 366         }
 367         p3csr = 0x00;
 368         p3csr_is3_flag_read = false;
 369         sc1_state = sc2_state = false;
 370
 371         tcsr = pending_tcsr = 0x00;
 372         CTD = 0x0000;
 373         OCD = 0xffff;
 374         TOD = 0xffff;
 375
 376         recv_buffer->clear();
 377         trcsr = TRCSR_TDRE;
 378         trcsr_read_tdre = trcsr_read_orfe = trcsr_read_rdrf = false;
 379         rmcr = 0x00;
 380         sio_counter = RMCR_SS[rmcr & 3];
 381
 382         ram_ctrl |= 0x40;
 383 //#endif
 384 }
 385
 386 void MC6801::write_signal(int id, uint32_t data, uint32_t mask)
 387 {
 388         switch(id) {
 389         case SIG_CPU_IRQ:
 390                 if(data & mask) {
 391                         int_state |= INT_REQ_BIT;
 392                 } else {
 393                         int_state &= ~INT_REQ_BIT;
 394                 }
 395                 break;
 396         case SIG_CPU_NMI:
 397                 if(data & mask) {
 398                         int_state |= NMI_REQ_BIT;
 399                 } else {
 400                         int_state &= ~NMI_REQ_BIT;
 401                 }
 402                 break;
 403 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 404         case SIG_MC6801_PORT_1:
 405                 port[0].rreg = (port[0].rreg & ~mask) | (data & mask);
 406                 break;
 407         case SIG_MC6801_PORT_2:
 408                 if((mask & 1) && (port[1].rreg & 1) != (data & 1) && (tcsr & 2) == ((data << 1) & 2)) {
 409                         // active TIN edge in
 410                         tcsr |= TCSR_ICF;
 411                         pending_tcsr |= TCSR_ICF;
 412                         input_capture = CT;
 413                 }
 414                 port[1].rreg = (port[1].rreg & ~mask) | (data & mask);
 415                 break;
 416         case SIG_MC6801_PORT_3:
 417                 port[2].rreg = (port[2].rreg & ~mask) | (data & mask);
 418                 break;
 419         case SIG_MC6801_PORT_4:
 420                 port[3].rreg = (port[3].rreg & ~mask) | (data & mask);
 421                 break;
 422         case SIG_MC6801_PORT_3_SC1:
 423                 if(sc1_state && !(data & mask)) {
 424                         // SC1: H -> L
 425                         if(!port[2].latched && (p3csr & P3CSR_LE)) {
 426                                 port[2].latched_data = port[2].rreg;
 427                                 port[2].latched = true;
 428                                 p3csr |= P3CSR_IS3_FLAG;
 429                         }
 430                 }
 431                 sc1_state = ((data & mask) != 0);
 432                 break;
 433         case SIG_MC6801_PORT_3_SC2:
 434                 sc2_state = ((data & mask) != 0);
 435                 break;
 436         case SIG_MC6801_SIO_RECV:
 437                 recv_buffer->write(data & mask);
 438                 break;
 439 //#endif
 440         }
 441 }
 442
 443 int MC6801::run(int clock)
 444 {
 445         // run cpu
 446         if(clock == -1) {
 447                 // run only one opcode
 448
 449                 CLEANUP_COUNTERS();
 450
 451                 icount = 0;
 452                 run_one_opecode();
 453                 return -icount;
 454         } else {
 455                 /* run cpu while given clocks */
 456
 457                 CLEANUP_COUNTERS();
 458
 459                 icount += clock;
 460                 int first_icount = icount;
 461
 462                 while(icount > 0) {
 463                         run_one_opecode();
 464                 }
 465                 return first_icount - icount;
 466         }
 467 }
 468
 469 void MC6801::run_one_opecode()
 470 {
 471         if(wai_state & (MC6800_WAI | HD6301_SLP)) {
 472                 increment_counter(1);
 473         } else {
 474                 do {
 475                         one_more_insn = false;
 476                         if(__USE_DEBUGGER) {
 477                                 bool now_debugging = d_debugger->now_debugging;
 478                                 if(now_debugging) {
 479                                         d_debugger->check_break_points(PC);
 480                                         if(d_debugger->now_suspended) {
 481                                                 d_debugger->now_waiting = true;
 482                                                 emu->start_waiting_in_debugger();
 483                                                 while(d_debugger->now_debugging && d_debugger->now_suspended) {
 484                                                         emu->process_waiting_in_debugger();
 485                                                 }
 486                                                 emu->finish_waiting_in_debugger();
 487                                                 d_debugger->now_waiting = false;
 488                                         }
 489                                         if(d_debugger->now_debugging) {
 490                                                 d_mem = d_debugger;
 491                                         } else {
 492                                                 now_debugging = false;
 493                                         }
 494
 495                                         d_debugger->add_cpu_trace(PC);
 496                                         uint8_t ireg = M_RDOP(PCD);
 497                                         prevpc = PC;
 498                                         PC++;
 499                                         insn(ireg);
 500                                         increment_counter(cycles[ireg]);
 501
 502                                         if(now_debugging) {
 503                                                 if(!d_debugger->now_going) {
 504                                                         d_debugger->now_suspended = true;
 505                                                 }
 506                                                 d_mem = d_mem_stored;
 507                                         }
 508                                 } else {
 509                                         if(__USE_DEBUGGER) d_debugger->add_cpu_trace(PC);
 510                                         uint8_t ireg = M_RDOP(PCD);
 511                                         prevpc = PC;
 512                                         PC++;
 513                                         insn(ireg);
 514                                         increment_counter(cycles[ireg]);
 515                                 }
 516                         } else {
 517                                 uint8_t ireg = M_RDOP(PCD);
 518                                 prevpc = PC;
 519                                 PC++;
 520                                 insn(ireg);
 521                                 increment_counter(cycles[ireg]);
 522                         }
 523                 } while(one_more_insn);
 524         }
 525
 526         // check interrupt
 527         if(int_state & NMI_REQ_BIT) {
 528                 wai_state &= ~HD6301_SLP;
 529                 int_state &= ~NMI_REQ_BIT;
 530                 enter_interrupt(0xfffc);
 531         } else if(int_state & INT_REQ_BIT) {
 532                 wai_state &= ~HD6301_SLP;
 533                 if(!(CC & 0x10)) {
 534                         int_state &= ~INT_REQ_BIT;
 535                         enter_interrupt(0xfff8);
 536                 }
 537 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 538         } else if((tcsr & (TCSR_EICI | TCSR_ICF)) == (TCSR_EICI | TCSR_ICF)) {
 539                 wai_state &= ~HD6301_SLP;
 540                 if(!(CC & 0x10)) {
 541                         TAKE_ICI;
 542                 }
 543         } else if((tcsr & (TCSR_EOCI | TCSR_OCF)) == (TCSR_EOCI | TCSR_OCF)) {
 544                 wai_state &= ~HD6301_SLP;
 545                 if(!(CC & 0x10)) {
 546                         TAKE_OCI;
 547                 }
 548         } else if((tcsr & (TCSR_ETOI | TCSR_TOF)) == (TCSR_ETOI | TCSR_TOF)) {
 549                 wai_state &= ~HD6301_SLP;
 550                 if(!(CC & 0x10)) {
 551                         TAKE_TOI;
 552                 }
 553         } else if(((trcsr & (TRCSR_RIE | TRCSR_RDRF)) == (TRCSR_RIE | TRCSR_RDRF)) ||
 554                   ((trcsr & (TRCSR_RIE | TRCSR_ORFE)) == (TRCSR_RIE | TRCSR_ORFE)) ||
 555                   ((trcsr & (TRCSR_TIE | TRCSR_TDRE)) == (TRCSR_TIE | TRCSR_TDRE))) {
 556                 wai_state &= ~HD6301_SLP;
 557                 if(!(CC & 0x10)) {
 558                         TAKE_SCI;
 559                 }
 560 //#endif
 561         }
 562 }
 563
 564 int MC6801::debug_dasm_with_userdata(uint32_t pc, _TCHAR *buffer, size_t buffer_len, uint32_t userdata)
 565 {
 566         uint8_t ops[4];
 567         for(int i = 0; i < 4; i++) {
 568                 int wait;
 569                 ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
 570         }
 571         return Dasm680x(6801, buffer, pc, ops, ops, d_debugger->first_symbol);
 572         return 0;
 573 }
 574
 575 void MC6801::insn(uint8_t code)
 576 {
 577         switch(code) {
 578         case 0x00: illegal(); break;
 579         case 0x01: nop(); break;
 580         case 0x02: illegal(); break;
 581         case 0x03: illegal(); break;
 582 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 583         case 0x04: lsrd(); break;
 584         case 0x05: asld(); break;
 585 //#else
 586 //      case 0x04: illegal(); break;
 587 //      case 0x05: illegal(); break;
 588 //#endif
 589         case 0x06: tap(); break;
 590         case 0x07: tpa(); break;
 591         case 0x08: inx(); break;
 592         case 0x09: dex(); break;
 593         case 0x0a: clv(); break;
 594         case 0x0b: sev(); break;
 595         case 0x0c: clc(); break;
 596         case 0x0d: sec(); break;
 597         case 0x0e: cli(); break;
 598         case 0x0f: sei(); break;
 599         case 0x10: sba(); break;
 600         case 0x11: cba(); break;
 601 //#if defined(HAS_HD6301)
 602 //      case 0x12: undoc1(); break;
 603 //      case 0x13: undoc2(); break;
 604 //#else
 605         case 0x12: illegal(); break;
 606         case 0x13: illegal(); break;
 607 //#endif
 608         case 0x14: illegal(); break;
 609         case 0x15: illegal(); break;
 610         case 0x16: tab(); break;
 611         case 0x17: tba(); break;
 612 //#if defined(HAS_HD6301)
 613 //      case 0x18: xgdx(); break;
 614 //#else
 615         case 0x18: illegal(); break;
 616 //#endif
 617         case 0x19: daa(); break;
 618 //#if defined(HAS_HD6301)
 619 //      case 0x1a: slp(); break;
 620 //#else
 621         case 0x1a: illegal(); break;
 622 //#endif
 623         case 0x1b: aba(); break;
 624         case 0x1c: illegal(); break;
 625         case 0x1d: illegal(); break;
 626         case 0x1e: illegal(); break;
 627         case 0x1f: illegal(); break;
 628         case 0x20: bra(); break;
 629         case 0x21: brn(); break;
 630         case 0x22: bhi(); break;
 631         case 0x23: bls(); break;
 632         case 0x24: bcc(); break;
 633         case 0x25: bcs(); break;
 634         case 0x26: bne(); break;
 635         case 0x27: beq(); break;
 636         case 0x28: bvc(); break;
 637         case 0x29: bvs(); break;
 638         case 0x2a: bpl(); break;
 639         case 0x2b: bmi(); break;
 640         case 0x2c: bge(); break;
 641         case 0x2d: blt(); break;
 642         case 0x2e: bgt(); break;
 643         case 0x2f: ble(); break;
 644         case 0x30: tsx(); break;
 645         case 0x31: ins(); break;
 646         case 0x32: pula(); break;
 647         case 0x33: pulb(); break;
 648         case 0x34: des(); break;
 649         case 0x35: txs(); break;
 650         case 0x36: psha(); break;
 651         case 0x37: pshb(); break;
 652 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 653         case 0x38: pulx(); break;
 654 //#else
 655 //      case 0x38: illegal(); break;
 656 //#endif
 657         case 0x39: rts(); break;
 658 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 659         case 0x3a: abx(); break;
 660 //#else
 661 //      case 0x3a: illegal(); break;
 662 //#endif
 663         case 0x3b: rti(); break;
 664 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 665         case 0x3c: pshx(); break;
 666         case 0x3d: mul(); break;
 667 //#else
 668 //      case 0x3c: illegal(); break;
 669 //      case 0x3d: illegal(); break;
 670 //#endif
 671         case 0x3e: wai(); break;
 672         case 0x3f: swi(); break;
 673         case 0x40: nega(); break;
 674         case 0x41: illegal(); break;
 675         case 0x42: illegal(); break;
 676         case 0x43: coma(); break;
 677         case 0x44: lsra(); break;
 678         case 0x45: illegal(); break;
 679         case 0x46: rora(); break;
 680         case 0x47: asra(); break;
 681         case 0x48: asla(); break;
 682         case 0x49: rola(); break;
 683         case 0x4a: deca(); break;
 684         case 0x4b: illegal(); break;
 685         case 0x4c: inca(); break;
 686         case 0x4d: tsta(); break;
 687         case 0x4e: illegal(); break;
 688         case 0x4f: clra(); break;
 689         case 0x50: negb(); break;
 690         case 0x51: illegal(); break;
 691         case 0x52: illegal(); break;
 692         case 0x53: comb(); break;
 693         case 0x54: lsrb(); break;
 694         case 0x55: illegal(); break;
 695         case 0x56: rorb(); break;
 696         case 0x57: asrb(); break;
 697         case 0x58: aslb(); break;
 698         case 0x59: rolb(); break;
 699         case 0x5a: decb(); break;
 700         case 0x5b: illegal(); break;
 701         case 0x5c: incb(); break;
 702         case 0x5d: tstb(); break;
 703         case 0x5e: illegal(); break;
 704         case 0x5f: clrb(); break;
 705         case 0x60: neg_ix(); break;
 706 //#if defined(HAS_HD6301)
 707 //      case 0x61: aim_ix(); break;
 708 //      case 0x62: oim_ix(); break;
 709 //#else
 710         case 0x61: illegal(); break;
 711         case 0x62: illegal(); break;
 712 //#endif
 713         case 0x63: com_ix(); break;
 714         case 0x64: lsr_ix(); break;
 715 //#if defined(HAS_HD6301)
 716 //      case 0x65: eim_ix(); break;
 717 //#else
 718         case 0x65: illegal(); break;
 719 //#endif
 720         case 0x66: ror_ix(); break;
 721         case 0x67: asr_ix(); break;
 722         case 0x68: asl_ix(); break;
 723         case 0x69: rol_ix(); break;
 724         case 0x6a: dec_ix(); break;
 725 //#if defined(HAS_HD6301)
 726 //      case 0x6b: tim_ix(); break;
 727 //#else
 728         case 0x6b: illegal(); break;
 729 //#endif
 730         case 0x6c: inc_ix(); break;
 731         case 0x6d: tst_ix(); break;
 732         case 0x6e: jmp_ix(); break;
 733         case 0x6f: clr_ix(); break;
 734         case 0x70: neg_ex(); break;
 735 //#if defined(HAS_HD6301)
 736 //      case 0x71: aim_di(); break;
 737 //      case 0x72: oim_di(); break;
 738 //#elif defined(HAS_MB8861)
 739 //      case 0x71: nim_ix(); break;
 740 //      case 0x72: oim_ix_mb8861(); break;
 741 //#else
 742         case 0x71: illegal(); break;
 743         case 0x72: illegal(); break;
 744 //#endif
 745         case 0x73: com_ex(); break;
 746         case 0x74: lsr_ex(); break;
 747 //#if defined(HAS_HD6301)
 748 //      case 0x75: eim_di(); break;
 749 //#elif defined(HAS_MB8861)
 750 //      case 0x75: xim_ix(); break;
 751 //#else
 752         case 0x75: illegal(); break;
 753 //#endif
 754         case 0x76: ror_ex(); break;
 755         case 0x77: asr_ex(); break;
 756         case 0x78: asl_ex(); break;
 757         case 0x79: rol_ex(); break;
 758         case 0x7a: dec_ex(); break;
 759 //#if defined(HAS_HD6301)
 760 //      case 0x7b: tim_di(); break;
 761 //#elif defined(HAS_MB8861)
 762 //      case 0x7b: tmm_ix(); break;
 763 //#else
 764         case 0x7b: illegal(); break;
 765 //#endif
 766         case 0x7c: inc_ex(); break;
 767         case 0x7d: tst_ex(); break;
 768         case 0x7e: jmp_ex(); break;
 769         case 0x7f: clr_ex(); break;
 770         case 0x80: suba_im(); break;
 771         case 0x81: cmpa_im(); break;
 772         case 0x82: sbca_im(); break;
 773 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 774         case 0x83: subd_im(); break;
 775 //#else
 776 //      case 0x83: illegal(); break;
 777 //#endif
 778         case 0x84: anda_im(); break;
 779         case 0x85: bita_im(); break;
 780         case 0x86: lda_im(); break;
 781         case 0x87: sta_im(); break;
 782         case 0x88: eora_im(); break;
 783         case 0x89: adca_im(); break;
 784         case 0x8a: ora_im(); break;
 785         case 0x8b: adda_im(); break;
 786 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 787         case 0x8c: cpx_im (); break;
 788 //#else
 789 //      case 0x8c: cmpx_im(); break;
 790 //#endif
 791         case 0x8d: bsr(); break;
 792         case 0x8e: lds_im(); break;
 793         case 0x8f: sts_im(); break;
 794         case 0x90: suba_di(); break;
 795         case 0x91: cmpa_di(); break;
 796         case 0x92: sbca_di(); break;
 797 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 798         case 0x93: subd_di(); break;
 799 //#else
 800 //      case 0x93: illegal(); break;
 801 //#endif
 802         case 0x94: anda_di(); break;
 803         case 0x95: bita_di(); break;
 804         case 0x96: lda_di(); break;
 805         case 0x97: sta_di(); break;
 806         case 0x98: eora_di(); break;
 807         case 0x99: adca_di(); break;
 808         case 0x9a: ora_di(); break;
 809         case 0x9b: adda_di(); break;
 810 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 811         case 0x9c: cpx_di (); break;
 812 //#else
 813 //      case 0x9c: cmpx_di(); break;
 814 //#endif
 815         case 0x9d: jsr_di(); break;
 816         case 0x9e: lds_di(); break;
 817         case 0x9f: sts_di(); break;
 818         case 0xa0: suba_ix(); break;
 819         case 0xa1: cmpa_ix(); break;
 820         case 0xa2: sbca_ix(); break;
 821 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 822         case 0xa3: subd_ix(); break;
 823 //#else
 824 //      case 0xa3: illegal(); break;
 825 //#endif
 826         case 0xa4: anda_ix(); break;
 827         case 0xa5: bita_ix(); break;
 828         case 0xa6: lda_ix(); break;
 829         case 0xa7: sta_ix(); break;
 830         case 0xa8: eora_ix(); break;
 831         case 0xa9: adca_ix(); break;
 832         case 0xaa: ora_ix(); break;
 833         case 0xab: adda_ix(); break;
 834 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 835         case 0xac: cpx_ix (); break;
 836 //#else
 837 //      case 0xac: cmpx_ix(); break;
 838 //#endif
 839         case 0xad: jsr_ix(); break;
 840         case 0xae: lds_ix(); break;
 841         case 0xaf: sts_ix(); break;
 842         case 0xb0: suba_ex(); break;
 843         case 0xb1: cmpa_ex(); break;
 844         case 0xb2: sbca_ex(); break;
 845 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 846         case 0xb3: subd_ex(); break;
 847 //#else
 848 //      case 0xb3: illegal(); break;
 849 //#endif
 850         case 0xb4: anda_ex(); break;
 851         case 0xb5: bita_ex(); break;
 852         case 0xb6: lda_ex(); break;
 853         case 0xb7: sta_ex(); break;
 854         case 0xb8: eora_ex(); break;
 855         case 0xb9: adca_ex(); break;
 856         case 0xba: ora_ex(); break;
 857         case 0xbb: adda_ex(); break;
 858 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 859         case 0xbc: cpx_ex (); break;
 860 //#else
 861 //      case 0xbc: cmpx_ex(); break;
 862 //#endif
 863         case 0xbd: jsr_ex(); break;
 864         case 0xbe: lds_ex(); break;
 865         case 0xbf: sts_ex(); break;
 866         case 0xc0: subb_im(); break;
 867         case 0xc1: cmpb_im(); break;
 868         case 0xc2: sbcb_im(); break;
 869 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 870         case 0xc3: addd_im(); break;
 871 //#else
 872 //      case 0xc3: illegal(); break;
 873 //#endif
 874         case 0xc4: andb_im(); break;
 875         case 0xc5: bitb_im(); break;
 876         case 0xc6: ldb_im(); break;
 877         case 0xc7: stb_im(); break;
 878         case 0xc8: eorb_im(); break;
 879         case 0xc9: adcb_im(); break;
 880         case 0xca: orb_im(); break;
 881         case 0xcb: addb_im(); break;
 882 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 883         case 0xcc: ldd_im(); break;
 884         case 0xcd: std_im(); break;
 885 //#else
 886 //      case 0xcc: illegal(); break;
 887 //      case 0xcd: illegal(); break;
 888 //#endif
 889         case 0xce: ldx_im(); break;
 890         case 0xcf: stx_im(); break;
 891         case 0xd0: subb_di(); break;
 892         case 0xd1: cmpb_di(); break;
 893         case 0xd2: sbcb_di(); break;
 894 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 895         case 0xd3: addd_di(); break;
 896 //#else
 897 //      case 0xd3: illegal(); break;
 898 //#endif
 899         case 0xd4: andb_di(); break;
 900         case 0xd5: bitb_di(); break;
 901         case 0xd6: ldb_di(); break;
 902         case 0xd7: stb_di(); break;
 903         case 0xd8: eorb_di(); break;
 904         case 0xd9: adcb_di(); break;
 905         case 0xda: orb_di(); break;
 906         case 0xdb: addb_di(); break;
 907 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 908         case 0xdc: ldd_di(); break;
 909         case 0xdd: std_di(); break;
 910 //#else
 911 //      case 0xdc: illegal(); break;
 912 //      case 0xdd: illegal(); break;
 913 //#endif
 914         case 0xde: ldx_di(); break;
 915         case 0xdf: stx_di(); break;
 916         case 0xe0: subb_ix(); break;
 917         case 0xe1: cmpb_ix(); break;
 918         case 0xe2: sbcb_ix(); break;
 919 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 920         case 0xe3: addd_ix(); break;
 921 //#else
 922 //      case 0xe3: illegal(); break;
 923 //#endif
 924         case 0xe4: andb_ix(); break;
 925         case 0xe5: bitb_ix(); break;
 926         case 0xe6: ldb_ix(); break;
 927         case 0xe7: stb_ix(); break;
 928         case 0xe8: eorb_ix(); break;
 929         case 0xe9: adcb_ix(); break;
 930         case 0xea: orb_ix(); break;
 931         case 0xeb: addb_ix(); break;
 932 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 933         case 0xec: ldd_ix(); break;
 934         case 0xed: std_ix(); break;
 935 //#elif defined(HAS_MB8861)
 936 //      case 0xec: adx_im(); break;
 937 //      case 0xed: illegal(); break;
 938 //#else
 939 //      case 0xec: illegal(); break;
 940 //      case 0xed: illegal(); break;
 941 //#endif
 942         case 0xee: ldx_ix(); break;
 943         case 0xef: stx_ix(); break;
 944         case 0xf0: subb_ex(); break;
 945         case 0xf1: cmpb_ex(); break;
 946         case 0xf2: sbcb_ex(); break;
 947 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 948         case 0xf3: addd_ex(); break;
 949 //#else
 950 //      case 0xf3: illegal(); break;
 951 //#endif
 952         case 0xf4: andb_ex(); break;
 953         case 0xf5: bitb_ex(); break;
 954         case 0xf6: ldb_ex(); break;
 955         case 0xf7: stb_ex(); break;
 956         case 0xf8: eorb_ex(); break;
 957         case 0xf9: adcb_ex(); break;
 958         case 0xfa: orb_ex(); break;
 959         case 0xfb: addb_ex(); break;
 960 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 961         case 0xfc: ldd_ex(); break;
 962         case 0xfd: std_ex(); break;
 963 //#elif defined(HAS_MB8861)
 964 //      case 0xfc: adx_ex(); break;
 965 //      case 0xfd: illegal(); break;
 966 //#else
 967 //      case 0xfc: illegal(); break;
 968 //      case 0xfd: illegal(); break;
 969 //#endif
 970         case 0xfe: ldx_ex(); break;
 971         case 0xff: stx_ex(); break;
 972 #if defined(_MSC_VER) && (_MSC_VER >= 1200)
 973         default: __assume(0);
 974 #endif
 975         }
 976 }
 977
 978 /* $04 LSRD inherent -0*-* */
 979 void MC6801::lsrd()
 980 {
 981         uint16_t t;
 982         CLR_NZC;
 983         t = D;
 984         CC |= (t & 0x0001);
 985         t >>= 1;
 986         SET_Z16(t);
 987         D = t;
 988 }
 989
 990 /* $05 ASLD inherent ?**** */
 991 void MC6801::asld()
 992 {
 993         int r;
 994         uint16_t t;
 995         t = D;
 996         r = t << 1;
 997         CLR_NZVC;
 998         SET_FLAGS16(t, t, r);
 999         D = r;
1000 }
1001 /* $38 PULX inherent ----- */
1002 void MC6801::pulx()
1003 {
1004         PULLWORD(pX);
1005 }
1006
1007 /* $3a ABX inherent ----- */
1008 void MC6801::abx()
1009 {
1010         X += B;
1011 }
1012 /* $3c PSHX inherent ----- */
1013 void MC6801::pshx()
1014 {
1015         PUSHWORD(pX);
1016 }
1017
1018 /* $3d MUL inherent --*-@ */
1019 void MC6801::mul()
1020 {
1021         uint16_t t;
1022         t = A*B;
1023         CLR_C;
1024         if(t & 0x80) SEC;
1025         D = t;
1026 }
1027 /* $83 SUBD immediate -**** */
1028 void MC6801::subd_im()
1029 {
1030         uint32_t r, d;
1031         pair32_t b;
1032         IMMWORD(b);
1033         d = D;
1034         r = d - b.d;
1035         CLR_NZVC;
1036         SET_FLAGS16(d, b.d, r);
1037         D = r;
1038 }
1039
1040 /* $8c CPX immediate -**** (6801) */
1041 void MC6801::cpx_im()
1042 {
1043         uint32_t r, d;
1044         pair32_t b;
1045         IMMWORD(b);
1046         d = X;
1047         r = d - b.d;
1048         CLR_NZVC;
1049         SET_FLAGS16(d, b.d, r);
1050 }
1051
1052 /* $93 SUBD direct -**** */
1053 void MC6801::subd_di()
1054 {
1055         uint32_t r, d;
1056         pair32_t b;
1057         DIRWORD(b);
1058         d = D;
1059         r = d - b.d;
1060         CLR_NZVC;
1061         SET_FLAGS16(d, b.d, r);
1062         D = r;
1063 }
1064
1065 /* $9c CPX direct -**** (6801) */
1066 void MC6801::cpx_di()
1067 {
1068         uint32_t r, d;
1069         pair32_t b;
1070         DIRWORD(b);
1071         d = X;
1072         r = d - b.d;
1073         CLR_NZVC;
1074         SET_FLAGS16(d, b.d, r);
1075 }
1076 /* $a3 SUBD indexed -**** */
1077 void MC6801::subd_ix()
1078 {
1079         uint32_t r, d;
1080         pair32_t b;
1081         IDXWORD(b);
1082         d = D;
1083         r = d - b.d;
1084         CLR_NZVC;
1085         SET_FLAGS16(d, b.d, r);
1086         D = r;
1087 }
1088
1089 /* $ac CPX indexed -**** (6801)*/
1090 void MC6801::cpx_ix()
1091 {
1092         uint32_t r, d;
1093         pair32_t b;
1094         IDXWORD(b);
1095         d = X;
1096         r = d - b.d;
1097         CLR_NZVC;
1098         SET_FLAGS16(d, b.d, r);
1099 }
1100
1101 /* $b3 SUBD extended -**** */
1102 void MC6801::subd_ex()
1103 {
1104         uint32_t r, d;
1105         pair32_t b;
1106         EXTWORD(b);
1107         d = D;
1108         r = d - b.d;
1109         CLR_NZVC;
1110         SET_FLAGS16(d, b.d, r);
1111         D = r;
1112 }
1113
1114 /* $bc CPX extended -**** (6801) */
1115 void MC6801::cpx_ex()
1116 {
1117         uint32_t r, d;
1118         pair32_t b;
1119         EXTWORD(b);
1120         d = X;
1121         r = d - b.d;
1122         CLR_NZVC;
1123         SET_FLAGS16(d, b.d, r);
1124 }
1125
1126 /* $c3 ADDD immediate -**** */
1127 void MC6801::addd_im()
1128 {
1129         uint32_t r, d;
1130         pair32_t b;
1131         IMMWORD(b);
1132         d = D;
1133         r = d + b.d;
1134         CLR_NZVC;
1135         SET_FLAGS16(d, b.d, r);
1136         D = r;
1137 }
1138
1139 /* $CC LDD immediate -**0- */
1140 void MC6801::ldd_im()
1141 {
1142         IMMWORD(pD);
1143         CLR_NZV;
1144         SET_NZ16(D);
1145 }
1146
1147 /* is this a legal instruction? */
1148 /* $cd STD immediate -**0- */
1149 void MC6801::std_im()
1150 {
1151         IMM16;
1152         CLR_NZV;
1153         SET_NZ16(D);
1154         WM16(EAD, &pD);
1155 }
1156
1157 /* $d3 ADDD direct -**** */
1158 void MC6801::addd_di()
1159 {
1160         uint32_t r, d;
1161         pair32_t b;
1162         DIRWORD(b);
1163         d = D;
1164         r = d + b.d;
1165         CLR_NZVC;
1166         SET_FLAGS16(d, b.d, r);
1167         D = r;
1168 }
1169
1170 /* $dc LDD direct -**0- */
1171 void MC6801::ldd_di()
1172 {
1173         DIRWORD(pD);
1174         CLR_NZV;
1175         SET_NZ16(D);
1176 }
1177
1178 /* $dd STD direct -**0- */
1179 void MC6801::std_di()
1180 {
1181         DIRECT;
1182         CLR_NZV;
1183         SET_NZ16(D);
1184         WM16(EAD, &pD);
1185 }
1186
1187 /* $e3 ADDD indexed -**** */
1188 void MC6801::addd_ix()
1189 {
1190         uint32_t r, d;
1191         pair32_t b;
1192         IDXWORD(b);
1193         d = D;
1194         r = d + b.d;
1195         CLR_NZVC;
1196         SET_FLAGS16(d, b.d, r);
1197         D = r;
1198 }
1199
1200 /* $ec LDD indexed -**0- */
1201 void MC6801::ldd_ix()
1202 {
1203         IDXWORD(pD);
1204         CLR_NZV;
1205         SET_NZ16(D);
1206 }
1207
1208 /* $ed STD indexed -**0- */
1209 void MC6801::std_ix()
1210 {
1211         INDEXED;
1212         CLR_NZV;
1213         SET_NZ16(D);
1214         WM16(EAD, &pD);
1215 }
1216
1217 /* $f3 ADDD extended -**** */
1218 void MC6801::addd_ex()
1219 {
1220         uint32_t r, d;
1221         pair32_t b;
1222         EXTWORD(b);
1223         d = D;
1224         r = d + b.d;
1225         CLR_NZVC;
1226         SET_FLAGS16(d, b.d, r);
1227         D = r;
1228 }
1229
1230 /* $fc LDD extended -**0- */
1231 void MC6801::ldd_ex()
1232 {
1233         EXTWORD(pD);
1234         CLR_NZV;
1235         SET_NZ16(D);
1236 }
1237
1238 /* $fd STD extended -**0- */
1239 void MC6801::std_ex()
1240 {
1241         EXTENDED;
1242         CLR_NZV;
1243         SET_NZ16(D);
1244         WM16(EAD, &pD);
1245 }
1246
1247 #define STATE_VERSION   2
1248
1249 bool MC6801::process_state(FILEIO* state_fio, bool loading)
1250 {
1251         if(!state_fio->StateCheckUint32(STATE_VERSION)) {
1252                 return false;
1253         }
1254         if(!state_fio->StateCheckInt32(this_device_id)) {
1255                 return false;
1256         }
1257         state_fio->StateValue(pc.d);
1258         state_fio->StateValue(prevpc);
1259         state_fio->StateValue(sp.d);
1260         state_fio->StateValue(ix.d);
1261         state_fio->StateValue(acc_d.d);
1262         state_fio->StateValue(ea.d);
1263         state_fio->StateValue(cc);
1264         state_fio->StateValue(wai_state);
1265         state_fio->StateValue(int_state);
1266         if(__USE_DEBUGGER) {
1267                 state_fio->StateValue(total_icount);
1268         }
1269         state_fio->StateValue(icount);
1270 // #if defined(HAS_MC6801) || defined(HAS_HD6301)
1271         for(int i = 0; i < 4; i++) {
1272                 state_fio->StateValue(port[i].wreg);
1273                 state_fio->StateValue(port[i].rreg);
1274                 state_fio->StateValue(port[i].ddr);
1275                 state_fio->StateValue(port[i].latched_data);
1276                 state_fio->StateValue(port[i].latched);
1277                 state_fio->StateValue(port[i].first_write);
1278         }
1279         state_fio->StateValue(p3csr);
1280         state_fio->StateValue(p3csr_is3_flag_read);
1281         state_fio->StateValue(sc1_state);
1282         state_fio->StateValue(sc2_state);
1283         state_fio->StateValue(counter.d);
1284         state_fio->StateValue(output_compare.d);
1285         state_fio->StateValue(timer_over.d);
1286         state_fio->StateValue(tcsr);
1287         state_fio->StateValue(pending_tcsr);
1288         state_fio->StateValue(input_capture);
1289         state_fio->StateValue(timer_next);
1290         if(!recv_buffer->process_state((void *)state_fio, loading)) {
1291                 return false;
1292         }
1293         state_fio->StateValue(trcsr);
1294         state_fio->StateValue(rdr);
1295         state_fio->StateValue(tdr);
1296         state_fio->StateValue(trcsr_read_tdre);
1297         state_fio->StateValue(trcsr_read_orfe);
1298         state_fio->StateValue(trcsr_read_rdrf);
1299         state_fio->StateValue(rmcr);
1300         state_fio->StateValue(sio_counter);
1301         state_fio->StateValue(ram_ctrl);
1302         state_fio->StateArray(ram, sizeof(ram), 1);
1303 //#endif
1304
1305         // post process
1306         if(__USE_DEBUGGER) {
1307                 if(loading) {
1308                         prev_total_icount = total_icount;
1309                 }
1310         }
1311         return true;
1312 }
1313