5 The PC16550D contains independent serial input and output ports that perform
6 byte-at-a-time I/O. The 16550 is distinguished from its predecessor, the
7 16450, by two 16-byte FIFOs. The FIFOs allow the CPU to buffer data to
8 reduce the frequency of interrupts. The 16550 also supports model-control
9 functions DMA hand-shaking, and have a loop-back mode for testing.
11 Pins: Sin, Sout, INTR, TxRDY, RxRDY, RTS, DTR, OUT1, OUT2, CTS, DSR, DCD, RI,
14 Attributes: timeout sio-framing? in-fifo-length out-fifo-length "tk tty"
15 RBR IER IIR LCR MCR LSR MSR SCR DLL DLM THR FCR Sin Sout Reset INTR
16 TxRDY RxRDY RTS DTR OUT1 OUT2 CTS DSR RI DCD state-snapshot
18 Symbol name: uart_component_library
22 The Uart model is somewhat abstracted from its hardware counterpart:
24 * The Sin and Sout pins carry a character at a time, including the parity
25 bit, if enabled. Normally, a character is 7-bits wide, so the model
26 transmits and receives one byte at a time. However, the chip supports
27 character widths of 5 to 8 bits, so up to 9 bits (8 data + parity) may
28 be transmitted. Stop bits are not modeled. If the "sio-framing?"
29 attribute is off, then only the raw data bits are passed on the pins.
30 The "in-fifo-length" attribute may be used to simulate an arbitrarily
31 large input FIFO. The "out-fifo-length" attribute is the converse,
32 though is just a placebo since there is no output FIFO processing at
35 * The preceding point suggests that the model uses an infinite baud rate,
36 since all the bits in a character are transmitted in a single event.
39 - The timing pins (XIN, XOUT, RCLK, BAUDOUT) are not simulated.
40 - Break functionality cannot be modeled.
41 - Framing errors cannot occur.
42 - The Divisor Latch is modeled but its values are ignored.
43 - To handle Character Timeouts, the UART model relies on callbacks
48 * This is a functional component
49 * It has state save/restore support
50 * It has not been explicitly made reentrant
51 * Pins and registers are both accessible from the Target View Manager
56 * Besides the CPU bus, the UART typically connects to both a
57 serial source and a serial sink component. The sink/source may be
58 combined, as with a modem component. More advanced designs will use
59 the TxRDY/RxRDY pins to communicate with a DMA controller.
61 If the UART is run using interrupts (versus polling) it should also be
62 connected to the scheduler so that transmit/receive timeouts are
65 Because the UART will be programmed to use a specific line discipline,
66 you must take care to match this discipline in both the sink and source.
68 * The following configuration file segment shows how to connect the
69 UART to a keyboard and console for interrupt-driven operation:
71 # components involved - cpu and bus are assumed
72 new hw-uart-ns16550 uart
73 new hw-keyboard keyboard
74 new hw-console console
75 new sid-sched-sim target-sched
76 set target-sched num-clients 2
77 # connect uart to bus at memory-mapped address 0x800000
78 connect-bus bus [0x800000-0x800008,4,1] uart Bus
80 connect-pin uart INTR -> cpu intr
81 connect-pin uart Sout -> console SIN
82 connect-pin keyboard SOUT -> uart Sin
83 connect-pin target-sched 0-event -> uart rx-timeout-event
84 connect-pin target-sched 1-event -> uart tx-timeout-event
85 # use 7-bits even-parity as the line discipline
86 set console line-disc "bits=7 parity=even"
87 set keyboard line-disc "bits=7 parity=even"
89 * SID interface reference
94 - Sin | input | data + parity | Serial input
95 - Sout | output | data + parity | Serial output
96 - INTR | output | 0,1 | active high interrupt pin
97 - TxRdy | output | 0,1 | active low Transmitter Ready (DMA control)
98 - RxRdy | output | 0,1 | active low Receiver Ready (DMA control)
99 - RTS | output | 0,1 | active low Request to Send (modem control)
100 - DTR | output | 0,1 | active low Data Transmit Ready (modem control)
101 - OUT1 | output | 0,1 | active low User Output (modem control)
102 - OUT2 | output | 0,1 | active low User Output (modem control)
103 - CTS | input | 0,1 | active low Clear To Send (modem control)
104 - DSR | input | 0,1 | active low Data Set Ready (modem control)
105 - RI | input | 0,1 | active low Ring Indicator (modem control
106 - DCD | input | 0,1 | active low Data Carrier Detect (modem control)
107 - Reset | input | any | Master Reset
110 - Bus | 0x0-0x7 | read/write, bytes only | access to registers
111 Although there are only 8 addresses, there are 12 registers
114 - timeout | write | positive integers | 10 | Sets the time to wait
115 (in wall-clock ms?) before a channel is considered to have timed-out
116 - sio-framing? | setting | "1" or "0" | "1" | Sin/Sout control
117 - in-fifo-length | setting | 1-65535 | 16 | Sin/Sout control
118 - out-fifo-length | setting | 1-65535 | 16 | Sin/Sout control
119 - "tk tty" | gui | n/a | "hw-visual-tty" | component gui
120 - state-snapshot | state | opaque string | none | state save/restore
123 National Semiconductor PC16550 data sheet, dated June 1995.
124 Obtained from <http://www.national.com/pf/PC/PC16550D.html>
125 This page has links to the data sheet and application notes (in PDF)