sid/component/testsuite/sidcomp.cfgroot/wrongOrd.badconf

   1 ## This conf file contains commands with arguments in incorrect order
   2
   3 # configuration logging
   4 set main verbose? 0
   5
   6 # component libraries
   7 load cgen_component_library libcgencpu.la       #incorrect order
   8 load libcgencpu.la cgen_component_library
   9 load libconsoles.la console_component_library
  10 load libgloss.la gloss_component_library
  11 load interrupt_component_library libinterrupt.la        #incorrect order
  12 load libinterrupt.la interrupt_component_library
  13 load libloader.la loader_component_library
  14 load libmapper.la mapper_component_library
  15 load libmemory.la mem_component_library
  16 load libmmu.la mmu_component_library
  17 load libsched.la sched_component_library
  18 load libtimers.la timer_component_library
  19
  20 # Components
  21
  22 new hw-cpu-arm7t cpu
  23 new loader sw-load-elf                  # incorrect order
  24 new sw-load-elf loader
  25 new sid-io-stdio stdio
  26 new sw-gloss-arm/angel angel
  27 new intctrl hw-interrupt-arm/ref        # incorrect order
  28 new hw-interrupt-arm/ref intctrl
  29 new hw-mapper-basic bus
  30 new hw-remap/pause-arm/ref remapper
  31 new sid-sched-host host-sched
  32 new sid-sched-sim target-sched
  33 new hw-memory-ram/rom-basic mem
  34 new hw-timer-arm/ref-sched timer1
  35 new timer2 hw-timer-arm/ref-sched       # incorrect order
  36 new hw-timer-arm/ref-sched timer2
  37
  38 # Scheduler
  39
  40 set 1 target-sched enabled?             # incorrect order
  41 set target-sched enabled? 1
  42 set target-sched num-clients 2
  43
  44 set host-sched enabled? 1
  45 set num-clients 1 host-sched            # incorrect order
  46 set host-sched 0-regular? 1
  47 set host-sched 0-time 50
  48
  49 connect-pin target-sched 0-control <- timer1 divided-clock-control
  50 connect-pin target-sched 1-control <- timer2 divided-clock-control
  51 connect-pin target-sched 0-event -> timer1 divided-clock-event
  52 connect-pin target-sched 1-event -> timer2 divided-clock-event
  53 connect-pin host-sched 0-event -> stdio poll
  54
  55 # Component relationships
  56 relate angel cpu cpu
  57
  58 # Main pin connections
  59 connect-pin main perform-activity -> host-sched advance
  60 connect-pin main perform-activity -> target-sched advance
  61 connect-pin main starting -> loader load!
  62 connect-pin main perform-activity -> cpu step!
  63
  64 # ELF loader
  65 connect-pin loader start-pc-set -> cpu start-pc-set!
  66 connect-pin loader endian-set -> cpu endian-set!
  67 connect-bus loader load-accessor bus access-port
  68
  69 # Gloss support
  70 connect-pin cpu trap <-> angel trap
  71 connect-pin cpu trap-code -> angel trap-code
  72 connect-pin angel process-signal -> main stop!
  73 connect-pin process-signal angel main -> stop!                  # incorrect order
  74 connect-pin angel debug-tx -> stdio stdout
  75 connect-pin angel debug-rx <- stdio stdin
  76
  77 # Interrupts from reference peripherals
  78 connect-pin timer1 interrupt intctrl interrupt-source-4 ->      # incorrect order
  79 connect-pin timer2 interrupt -> intctrl interrupt-source-5
  80 connect-pin -> intctrl interrupt cpu nirq                       # incorrect order
  81 connect-pin intctrl fast-interrupt -> cpu nfiq
  82
  83 # Alter this attribute to get more available system RAM.
  84 set mem size 8388608
  85
  86 # Attributes
  87 set loader file hello
  88 set cpu engine-type scache
  89 set step-insn-count 1000 cpu                                    # incorrect order
  90
  91 # Bus connections
  92 connect-bus remapper all bus access-port
  93 connect-bus cpu insn-memory remapper access-port
  94 connect-bus cpu data-memory remapper access-port
  95 connect-bus angel target-memory remapper access-port
  96 connect-bus mem bus [0,0x7fffff] read-write-port                # incorrect order
  97 connect-bus bus [0xA000000,0xA000013] intctrl irq-registers
  98 connect-bus bus [0xA000100,0xA00010F] intctrl fiq-registers
  99 connect-bus bus [0xA800000,0xA80000F] timer1 registers
 100 connect-bus bus [0xA800020,0xA80002F] timer2 registers
 101 connect-bus [0xB000000,0xB000037] bus registers remapper        # incorrect order
 102