1 # This conf file contains multiple connect-bus command on the same bus and
2 # connect bus command with bus and accessor switched.
4 # configuration logging
8 load libcgencpu.la cgen_component_library
9 load libconsoles.la console_component_library
10 load libgloss.la gloss_component_library
11 load libinterrupt.la interrupt_component_library
12 load libloader.la loader_component_library
13 load libmapper.la mapper_component_library
14 load libmemory.la mem_component_library
15 load libmmu.la mmu_component_library
16 load libsched.la sched_component_library
17 load libtimers.la timer_component_library
22 new sw-load-elf loader
23 new sid-io-stdio stdio
24 new sw-gloss-arm/angel angel
25 new hw-interrupt-arm/ref intctrl
26 new hw-mapper-basic bus
27 new hw-remap/pause-arm/ref remapper
28 new sid-sched-host host-sched
29 new sid-sched-sim target-sched
30 new hw-memory-ram/rom-basic mem
31 new hw-timer-arm/ref-sched timer1
32 new hw-timer-arm/ref-sched timer2
36 set target-sched enabled? 1
37 set target-sched num-clients 2
39 set host-sched enabled? 1
40 set host-sched num-clients 1
41 set host-sched 0-regular? 1
42 set host-sched 0-time 50
44 connect-pin target-sched 0-control <- timer1 divided-clock-control
45 connect-pin target-sched 1-control <- timer2 divided-clock-control
46 connect-pin target-sched 0-event -> timer1 divided-clock-event
47 connect-pin target-sched 1-event -> timer2 divided-clock-event
48 connect-pin host-sched 0-event -> stdio poll
50 # Component relationships
53 # Main pin connections
54 connect-pin main perform-activity -> host-sched advance
55 connect-pin main perform-activity -> target-sched advance
56 connect-pin main starting -> loader load!
57 connect-pin main perform-activity -> cpu step!
60 connect-pin loader start-pc-set -> cpu start-pc-set!
61 connect-pin loader endian-set -> cpu endian-set!
62 connect-bus loader load-accessor bus access-port
63 connect-bus loader load-accessor bus access-port # another connect-bus command
64 connect-bus bus access-port loader load-accessor # another connect-bus command in the opposite direction
67 connect-pin cpu trap <-> angel trap
68 connect-pin cpu trap-code -> angel trap-code
69 connect-pin angel process-signal -> main stop!
70 connect-pin angel debug-tx -> stdio stdout
71 connect-pin angel debug-rx <- stdio stdin
73 # Interrupts from reference peripherals
74 connect-pin timer1 interrupt -> intctrl interrupt-source-4
75 connect-pin timer2 interrupt -> intctrl interrupt-source-5
76 connect-pin intctrl interrupt -> cpu nirq
77 connect-pin intctrl fast-interrupt -> cpu nfiq
79 # Alter this attribute to get more available system RAM.
84 set cpu engine-type scache
85 set cpu step-insn-count 1000
88 connect-bus remapper all bus access-port
89 connect-bus bus access-port remapper all # reverse the bus connection
90 connect-bus cpu insn-memory remapper access-port
91 connect-bus cpu data-memory remapper access-port
92 connect-bus angel target-memory remapper access-port
93 connect-bus bus [0,0x7fffff] mem read-write-port
94 connect-bus bus [0,0x7fffff] mem read-write-port # duplicate of previous connect-bus command
95 connect-bus bus [0xA000000,0xA000013] intctrl irq-registers
96 connect-bus bus [0xA000100,0xA00010F] intctrl fiq-registers
97 connect-bus bus [0xA800000,0xA80000F] timer1 registers
98 connect-bus bus [0xA800020,0xA80002F] timer2 registers # duplicate of previous connect-bus command
99 connect-bus bus [0xB000000,0xB000037] remapper registers