1 * Copyright (C) 1999 Red Hat
4 hw-lcd-t6963c-0101 hw-lcd-t6963c-0201
7 Simulates the Toshiba T6963C LCD controller. The controller supports display
8 sizes from 32 to 80 columns and from 2 to 32 lines. The fonts may also be
9 varied from 5X8 dots to 8X8 dots. The chip supports an external display RAM
10 of up to 64 Kbytes. This RAM may be arbitrarily configured between text and
11 graphics, and attributes such as blink and reverse can be specified on a per
12 character basis. The chip comes with a 128 character ROM of predefined fonts.
13 Two ROMS are available: hw-lcd-t6963c-0101 specifies the European standard
14 font; hw-lcd-t6963c-0201 is the Japanese standard font.
17 Accessor: external-ram
19 Attributes: refresh-period-msec display-width display-height font-width
22 Symbol name: t6963c_component_library
26 The LCD controller model is somewhat abstracted from the physical device:
28 o All commands in the model are executed instantaneously, while the real
29 device requires significant time to execute a command. As a result, the
30 status flag in the model always shows "ready".
32 o The real device has a number of shift/latch pins that are used to drive
33 the display. These are replaced by 2 pins in the model. The FR (frame)
34 pin is driven to 1 to identify that a new frame is starting, and driven
35 to 0 when the frame is finished. The row-col pin is driven once for each
36 "on" pixel in the display, and the value on the pin is the [X,Y] co-
37 ordinates of the pixel, encoded as two adjacent 16-bit values in the
40 With these two pins, a display refresh cycle starts when the FR pin is
41 asserted; the [X,Y] co-ordinates of all the "on" pixels are then
42 transmitted on the row-col pin; and the FR pin is de-asserted to end
45 o The physical device uses an external crystal to set the duty cycle.
46 The model uses the refresh-period-msec attribute to communicate with
47 the scheduler to set the refresh rate.
49 To reduce system overhead, the model tries to reduce its interaction
50 with the scheduler and display. Specifically, a single refresh cycle is
51 initiated if there is a write to the component, to capture any internal
52 state changes that may affect the display. Because several writes are
53 often required to effect a meaningful change, the refresh is delayed to
54 occur refresh-period-msec milliseconds after the first write. As well,
55 the refresh is continued periodically if blink is enabled.
57 o The physical device uses a number of pins to set the display geometry
58 (MDS, MD0-3) and font width (FS0-1). The model uses the display-width,
59 display-height, and font-width attributes to set these parameters.
61 o Screen Peek and Screen Copy are not (currently) supported.
63 o Dual-Scan is not (currently) supported.
68 refresh-period-msec: used specify the refresh period (in milliseconds)
69 for continuous update modes such as blink.
71 display-width: specifies the number of columns in pixels. Legal values
72 are those that can be represented by the MD2-MD3 pins on the real chip.
74 display-height: specifies the number of rows in characters (each
75 each character is 8 pixels high). Legal values correspond to the
76 single-scan (ie. non-DUAL mode) values that can be represented by the
77 MDS, MD0, and MD11 pins on the real chip.
79 font-width: specifies the width of each character in pixels.
80 Corresponds to the values specifiable by the FS0-1 pins on the real chip.
84 See discussion of the FR and row-col pins in Modeling section above
87 * This is a functional component
88 * Save/restore is supported via the state-snapshot attribute
89 * Trigger point support is available on the following registers:
90 SR, X-ADRS, Y-ADRS, Offset, ADP, TH, GH, TA, and GA.
94 * The T6963C requires an external memory for its display RAM. This RAM
95 can be any size up to 64KBytes. Besides the memory (and CPU bus), the
96 LCD controller is usually connected to a display of some kind. Clearly,
97 the display component must be aware of the refresh protocol used by the
98 T6963C model. Finally, the scheduler is typically used to set up the
99 time between refreshes of the display.
101 * The following configuration file segment shows how the LCD controller
102 can be connected to 64K external RAM, the tcl based display, and the
105 new hw-lcd-t6963c-0101 lcd # Standard European font
106 new hw-visual-lcd display # The display is implemented in Tcl
107 new sid-sched-host sched # Use the real-time scheduler
109 # scheduling (must appear before pin assignments)
110 set sched num-clients 1
111 set sched 0-regular? 1
112 set sched 0-time 500 # in msec
114 # display size is in pixels - ie. font-width*display-height
115 set display width 160 # 20 chars X 8 pixels per char
116 set display height 48 # 6 lines of 8 pixels per line
118 # lcd geometry values must match allowed pin settings
119 set lcd display-width 32 # 32 chars (closest to 20)
120 set lcd display-height 6 # 6 rows/lines
122 # connect the LCD to the scheduler
123 connect-pin sched 0-event -> lcd refresh-sync-event
124 connect-pin sched 0-control <- lcd refresh-sync-control
125 # connect the LCD to the display
126 connect-pin lcd row-col -> display row-col
127 connect-pin lcd FR -> display FR
129 # connect external display ram
130 new hw-memory-ram/rom-basic d-ram
132 connect-bus lcd external-ram d-ram read-write-port
135 * SID interface reference
138 - FR | output | binary | display
139 - row-col | output | 2 shorts as a 32-bit value | display
142 - bus | 0 to 1 | byte-wide access
145 - external-ram | 0 to 0xffff | byte-wide read/write
148 - refresh-period-msec | setting | any positive value | 500 | configuration
149 - display-width | setting | 32, 40, 64, 80 | 80 | configuration
150 - display-height | setting | 2, 4, 6, ... 16 | 16 | configuration
151 - font-width | setting | 5, 6, 7, 8 | 8 | configuration
154 T6963C Dot Matrix LCD Control LSI (from the Toshiba web site)