1 * Copyright (C) 1999 Red Hat
4 hw-lcd-hd44780u-a00 hw-lcd-hd44780u-a02
7 Simulates the Hitachi HD44780U LCD controller. The controller supports
8 1 or 2 lines of 8 5X8 dots with cursor, or 1 line of 8 5X10 dots with cursor.
9 The chip includes an 80 character display RAM, a 64 byte character generator
10 RAM, and a 240 character ROM of predefined fonts. Two ROMS are available:
11 hw-lcd-hd44780u-a00 specifies the Japanese standard font; hw-lcd-hd44780u-a02
12 is the European standard font.
16 Attributes: refresh-period-msec verbose?
18 Library: libhd44780u.la
19 Symbol name: hd44780u_component_library
23 The LCD controller model is somewhat abstracted from the physical device:
25 o All commands in the model are executed instantaneously, while the real
26 device requires significant time to execute a command. As a result, the
27 busy flag in the model is never set.
29 o The real device has 40 segment driver pins, 16 common driver pins, and
30 6 more pins related to data and clock. These are replaced by 2(!) pins
31 in the model. The FR (frame) pin is driven to 1 to identify that a new
32 frame is starting, and driven to 0 when the frame is finished. The
33 row-col pin incorporates all the functionality of the row and column
34 drivers on the real chip. This pin is driven once for each "on" pixel
35 in the display, and the value on the pin is the [X,Y] co-ordinates of
36 the pixel, encoded as two adjacent 16-bit values in the 32-bit pin value.
38 With these two pins, a display refresh cycle starts when the FR pin is
39 asserted; the [X,Y] co-ordinates of all the "on" pixels are then
40 transmitted on the row-col pin; and the FR pin is de-asserted to end
43 o The physical device uses an external crystal to set the duty cycle.
44 The model uses the refresh-period-msec attribute to communicate with
45 the scheduler to set the refresh rate.
47 To reduce system overhead, the model tries to reduce its interaction
48 with the scheduler and display. Specifically, a single refresh cycle is
49 initiated if there is a write to the component, to capture any internal
50 state changes that may affect the display. Because several writes are
51 often required to effect a meaningful change, the refresh is delayed to
52 occur refresh-period-msec milliseconds after the first write. As well,
53 the refresh is continued periodically if blink is enabled.
57 The refresh-period-msec attribute is used specify the refresh period
58 (in milliseconds) for continuous update modes such as blink.
61 The boolean verbose? attribute can be used to track internal operations
64 See discussion of the FR and row-col pins in Modeling section above
67 * This is a functional component
68 * Save/restore is supported via the state-snapshot attribute
69 * Trigger point support is available on the IR, DR, and AC registers.
73 * Besides the CPU bus, the LCD controller is typically connected to a
74 display of some kind. Clearly, the display component must be aware of the
75 refresh protocol used by the HD44780U model. As well, the scheduler is
76 typically used to set up the time between refreshes of the display.
78 * The following configuration file segment shows how the LCD controller
79 can be connected to the lcd.tcl display and host-time scheduler:
81 new hw-lcd-hd44780u-a00 lcd # Standard Japanese font
82 new hw-visual-lcd display # The display is implemented in Tcl
83 new sid-sched-host sched # Use the real-time scheduler
85 # scheduling (must appear before pin assignments)
86 set sched num-clients 1
87 set sched 0-regular? 1
88 set sched 0-time 500 # in msec
90 # display size is in pixels - ie. font-width*display-height
91 set display width 40 # 8 chars X 5 pixels per char
92 set display height 8 # single line of 8 pixels
94 # connect the LCD to the scheduler
95 connect-pin sched 0-event -> lcd refresh-sync-event
96 connect-pin sched 0-control <- lcd refresh-sync-control
97 # connect the LCD to the display
98 connect-pin lcd row-col -> display row-col
99 connect-pin lcd FR -> display FR
101 * SID interface reference
104 - FR | output | binary | display
105 - row-col | output | 2 shorts as a 32-bit value | display
108 - bus | 0 to 1 | byte-wide access
111 - refresh-period-msec | setting | any positive value | 500 | configuration
112 - verbose? | setting | boolean | false | debug
115 HD44780U (LCD-II) Dot Matrix Liquid Crystal Display Controller Driver
116 (from the Hitachi web site)