2 hw-interrupt-cogent/cma222
5 This component simulates the interrupt controller on the Cogent
6 CMA222 ARM710T CPU model.
8 Pins: interrupt interrupt-source-0..interrupt-source-7
10 Attributes: interrupt irq-raw-status irq-enable-register
12 Library: libinterrupt.la
13 Symbol name: interrupt_component_library
19 * The interrupt controller model features 8 interrupt sources
20 for the follow services: reset, serial port A, serial port B,
21 timer, motherboard ethernet (CMA101) or parallel port (CMA102
22 and CMA110), and 3 interrupt lines for motherboard slots.
28 When the "interrupt-source-0" input pin is driven, this component
29 is reset to the hardware's normal power-up state.
33 When the "irq-registers" bus is accessed, the appropriate 8-bit control
34 register is read or written. Available registers are as follows:
35 ISR (Interrupt Source Register), Clear ISR, IMR (Interrupt Mask
36 Register), and 3 Interrupt Acknowledge slot registers. These
37 registers are mapped at base address 0xF000000, and the following
41 0xF600000 ISR (reserved)
42 0xF600008 (reserved) Clear ISR
43 0xF600010 IMR (reserved)
44 0xF600018 (reserved) IMR
45 0xF600020 IRQAckSlot1 (reserved)
46 0xF600028 IRQAckSlot2 (reserved)
47 0xF600030 IRQAckSlot3 (reserved)
49 Several registers are also available as watchable attributes.
51 * Interrupt processing
53 When any interrupt source is signalled, or interrupt-enabled
54 masks are modified, pending interrupts are processed. There is
55 only one interrupt source: the "interrupt-source-N" input pins.
56 Subject to the then-current interrupt-enabling registers, the
57 "interrupt" output pin may be driven.
59 The polarity for the input interrupt source pins is positive,
60 meaning that non-zero values are interpreted as "asserted". On
61 the other hand, the polarity for the output interrupt pins is
62 negative, meaning that zero values are to be interpreted as
65 Similarly named attributes may be used to generate/monitor pin
70 * This is a functional component.
71 * This component supports state save/restore and triggerpoints.
76 The interrupt controller sits between the ARM710T CPU on the CMA222
77 CPU board, and the other components on this board or the CMA motherboard.
78 The following configuration file fragment shows all the onboard devices
79 of the CMA110 motherboard connected to the interrupt controller.
82 new hw-timer-arm/ref-nosched timer
83 new hw-interrupt-cogent/cma222 intcontrl
84 new hw-uart-ns16550 uart1
85 new hw-uart-ns16550 uart2
86 connect-pin uart2 INTR -> intctrl interrupt-source-1
87 connect-pin uart1 INTR -> intctrl interrupt-source-2
88 connect-pin timer interrupt -> intcontrl interrupt-source-3
89 connect-pin parport INTP -> intctrl interrupt-source-4
90 connect-pin intcontrl interrupt -> cpu nirq
92 * SID interface reference
96 - interrupt-source-[0,7] | input | any | interrupt handling
97 - interrupt | output | 0,1 | interrupt handling
100 - irq-registers | 0x0 - 0x37F | read/write | register access
103 - interrupt | pin watchable | numeric | n/a | interrupt handling
104 - irq-raw-status | register watchable | numeric | n/a | register access
105 - irq-enable-register | register watchable | numeric | n/a | register access
108 <http://www.cogcomp.com/data_sheets/>