1 /* Misc. entries in the ms1 description file.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2005 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
19 /* Enum declaration for msys enums. */
20 typedef enum insn_msys {
24 /* Enum declaration for opc enums. */
25 typedef enum insn_opc {
26 OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3
27 , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10
28 , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
29 , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
30 , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
31 , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LDW = 32, OPC_STW = 33
32 , OPC_EI = 48, OPC_DI = 49, OPC_SI = 50, OPC_RETI = 51
33 , OPC_BREAK = 52, OPC_IFLUSH = 53
36 /* Enum declaration for msopc enums. */
37 typedef enum insn_msopc {
38 MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB
39 , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI
40 , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI
41 , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB
42 , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB
43 , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR
44 , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR
45 , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS
48 /* Enum declaration for imm enums. */
49 typedef enum insn_imm {
53 /* Enum declaration for . */
54 typedef enum msys_syms {
55 H_NIL_DUP = 1, H_NIL_XX = 0
58 // Insn attribute indices.
60 /* Enum declaration for cgen_insn attrs. */
61 typedef enum cgen_insn_attr {
62 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
63 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
64 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
65 , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_USES_FRDR
66 , CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA
67 , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
70 /* Number of non-boolean elements in cgen_insn_attr. */
71 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
75 /* Enum declaration for machine type selection. */
76 typedef enum mach_attr {
77 MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MAX
80 /* Enum declaration for instruction set selection. */
81 typedef enum isa_attr {
87 struct ms1_insn_attr {
90 inline unsigned int get_mach_attr () { return mach; }
91 inline int get_alias_attr () { return (bools & (1<<CGEN_INSN_ALIAS)) != 0; }
92 inline int get_virtual_attr () { return (bools & (1<<CGEN_INSN_VIRTUAL)) != 0; }
93 inline int get_uncond_cti_attr () { return (bools & (1<<CGEN_INSN_UNCOND_CTI)) != 0; }
94 inline int get_cond_cti_attr () { return (bools & (1<<CGEN_INSN_COND_CTI)) != 0; }
95 inline int get_skip_cti_attr () { return (bools & (1<<CGEN_INSN_SKIP_CTI)) != 0; }
96 inline int get_delay_slot_attr () { return (bools & (1<<CGEN_INSN_DELAY_SLOT)) != 0; }
97 inline int get_relaxable_attr () { return (bools & (1<<CGEN_INSN_RELAXABLE)) != 0; }
98 inline int get_relaxed_attr () { return (bools & (1<<CGEN_INSN_RELAXED)) != 0; }
99 inline int get_no_dis_attr () { return (bools & (1<<CGEN_INSN_NO_DIS)) != 0; }
100 inline int get_pbb_attr () { return (bools & (1<<CGEN_INSN_PBB)) != 0; }
101 inline int get_load_delay_attr () { return (bools & (1<<CGEN_INSN_LOAD_DELAY)) != 0; }
102 inline int get_memory_access_attr () { return (bools & (1<<CGEN_INSN_MEMORY_ACCESS)) != 0; }
103 inline int get_al_insn_attr () { return (bools & (1<<CGEN_INSN_AL_INSN)) != 0; }
104 inline int get_io_insn_attr () { return (bools & (1<<CGEN_INSN_IO_INSN)) != 0; }
105 inline int get_br_insn_attr () { return (bools & (1<<CGEN_INSN_BR_INSN)) != 0; }
106 inline int get_uses_frdr_attr () { return (bools & (1<<CGEN_INSN_USES_FRDR)) != 0; }
107 inline int get_uses_frdrrr_attr () { return (bools & (1<<CGEN_INSN_USES_FRDRRR)) != 0; }
108 inline int get_uses_frsr1_attr () { return (bools & (1<<CGEN_INSN_USES_FRSR1)) != 0; }
109 inline int get_uses_frsr2_attr () { return (bools & (1<<CGEN_INSN_USES_FRSR2)) != 0; }
110 inline int get_skipa_attr () { return (bools & (1<<CGEN_INSN_SKIPA)) != 0; }
113 #define MACH_MS1_003_INSN_CHUNK_BITSIZE 0
115 } // end ms1 namespace
117 #endif /* DESC_MS1_H */