1 /* CPU class elements for arm.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000 Red Hat, Inc.
7 This file is part of the Cygnus Simulators.
12 // This file is included in the middle of the cpu class struct.
16 // CPU state information.
20 /* ARM program counter (h-gr reg 15) */
22 /* General purpose registers */
24 /* user/system mode r8-r14 holding buffer */
26 /* fiq mode r8-r14 regs */
28 /* supervisor mode r13-r14 regs */
30 /* abort mode r13-r14 regs */
32 /* irq mode r13-r14 regs */
34 /* undefined mode r13-r14 regs */
52 /* Saved Process Status Register during FIQ */
54 /* Saved Process Status Register during SVC */
56 /* Saved Process Status Register during Abort */
58 /* Saved Process Status Register during IRQ */
60 /* Saved Process Status Register during Undefined */
64 // C++ register access function templates
65 #define current_cpu this
67 inline USI h_pc_get () const { return this->hardware.h_pc; }
68 inline void h_pc_set (USI newval) { if (current_cpu->hardware.h_tbit) {
69 current_cpu->hardware.h_pc = ANDSI (newval, -2);
71 current_cpu->hardware.h_pc = ANDSI (newval, -4);
75 inline SI h_gr_get (UINT regno) const { return this->hardware.h_gr[regno]; }
76 inline void h_gr_set (UINT regno, SI newval) { this->hardware.h_gr[regno] = newval; }
78 inline SI h_gr_usr_get (UINT regno) const { return this->hardware.h_gr_usr[regno]; }
79 inline void h_gr_usr_set (UINT regno, SI newval) { this->hardware.h_gr_usr[regno] = newval; }
81 inline SI h_gr_fiq_get (UINT regno) const { return this->hardware.h_gr_fiq[regno]; }
82 inline void h_gr_fiq_set (UINT regno, SI newval) { this->hardware.h_gr_fiq[regno] = newval; }
84 inline SI h_gr_svc_get (UINT regno) const { return this->hardware.h_gr_svc[regno]; }
85 inline void h_gr_svc_set (UINT regno, SI newval) { this->hardware.h_gr_svc[regno] = newval; }
87 inline SI h_gr_abt_get (UINT regno) const { return this->hardware.h_gr_abt[regno]; }
88 inline void h_gr_abt_set (UINT regno, SI newval) { this->hardware.h_gr_abt[regno] = newval; }
90 inline SI h_gr_irq_get (UINT regno) const { return this->hardware.h_gr_irq[regno]; }
91 inline void h_gr_irq_set (UINT regno, SI newval) { this->hardware.h_gr_irq[regno] = newval; }
93 inline SI h_gr_und_get (UINT regno) const { return this->hardware.h_gr_und[regno]; }
94 inline void h_gr_und_set (UINT regno, SI newval) { this->hardware.h_gr_und[regno] = newval; }
96 inline BI h_cbit_get () const { return this->hardware.h_cbit; }
97 inline void h_cbit_set (BI newval) { this->hardware.h_cbit = newval; }
99 inline BI h_nbit_get () const { return this->hardware.h_nbit; }
100 inline void h_nbit_set (BI newval) { this->hardware.h_nbit = newval; }
102 inline BI h_vbit_get () const { return this->hardware.h_vbit; }
103 inline void h_vbit_set (BI newval) { this->hardware.h_vbit = newval; }
105 inline BI h_zbit_get () const { return this->hardware.h_zbit; }
106 inline void h_zbit_set (BI newval) { this->hardware.h_zbit = newval; }
108 inline BI h_ibit_get () const { return this->hardware.h_ibit; }
109 inline void h_ibit_set (BI newval) { this->hardware.h_ibit = newval; }
111 inline BI h_fbit_get () const { return this->hardware.h_fbit; }
112 inline void h_fbit_set (BI newval) { this->hardware.h_fbit = newval; }
114 inline BI h_tbit_get () const { return this->hardware.h_tbit; }
115 inline void h_tbit_set (BI newval) { {
116 current_cpu->arm_tbit_set (newval);
120 inline UINT h_mbits_get () const { return this->hardware.h_mbits; }
121 inline void h_mbits_set (UINT newval) { {
124 case ARM_MODE_USER : case ARM_MODE_FIQ : case ARM_MODE_IRQ : case ARM_MODE_SUPERVISOR : case ARM_MODE_ABORT : case ARM_MODE_UNDEFINED : case ARM_MODE_SYSTEM : {
129 current_cpu->cgen_rtx_error ("bad value for M4-M0");
133 current_cpu->arm_mbits_set (newval);
137 inline SI h_cpsr_get () const { return ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_nbit), 31), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_zbit), 30), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_cbit), 29), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_vbit), 28), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_ibit), 7), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_fbit), 6), ORSI (SLLSI (ZEXTBISI (current_cpu->hardware.h_tbit), 5), current_cpu->hardware.h_mbits))))))); }
138 inline void h_cpsr_set (SI newval) { {
139 current_cpu->hardware.h_nbit = NESI (ANDSI (newval, 0x80000000), 0);
140 current_cpu->hardware.h_zbit = NESI (ANDSI (newval, 1073741824), 0);
141 current_cpu->hardware.h_cbit = NESI (ANDSI (newval, 536870912), 0);
142 current_cpu->hardware.h_vbit = NESI (ANDSI (newval, 268435456), 0);
143 current_cpu->hardware.h_ibit = NESI (ANDSI (newval, 128), 0);
144 current_cpu->hardware.h_fbit = NESI (ANDSI (newval, 64), 0);
145 current_cpu->h_tbit_set (NESI (ANDSI (newval, 32), 0));
146 current_cpu->h_mbits_set (ANDSI (newval, 31));
150 inline SI h_spsr_fiq_get () const { return this->hardware.h_spsr_fiq; }
151 inline void h_spsr_fiq_set (SI newval) { this->hardware.h_spsr_fiq = newval; }
153 inline SI h_spsr_svc_get () const { return this->hardware.h_spsr_svc; }
154 inline void h_spsr_svc_set (SI newval) { this->hardware.h_spsr_svc = newval; }
156 inline SI h_spsr_abt_get () const { return this->hardware.h_spsr_abt; }
157 inline void h_spsr_abt_set (SI newval) { this->hardware.h_spsr_abt = newval; }
159 inline SI h_spsr_irq_get () const { return this->hardware.h_spsr_irq; }
160 inline void h_spsr_irq_set (SI newval) { this->hardware.h_spsr_irq = newval; }
162 inline SI h_spsr_und_get () const { return this->hardware.h_spsr_und; }
163 inline void h_spsr_und_set (SI newval) { this->hardware.h_spsr_und = newval; }
165 inline SI h_spsr_get () const { return (current_cpu->hardware.h_mbits == ARM_MODE_USER) ? ((current_cpu->cgen_rtx_error ("can't read spsr in user mode"), 0)) : (current_cpu->hardware.h_mbits == ARM_MODE_FIQ) ? (current_cpu->hardware.h_spsr_fiq) : (current_cpu->hardware.h_mbits == ARM_MODE_IRQ) ? (current_cpu->hardware.h_spsr_irq) : (current_cpu->hardware.h_mbits == ARM_MODE_SUPERVISOR) ? (current_cpu->hardware.h_spsr_svc) : (current_cpu->hardware.h_mbits == ARM_MODE_ABORT) ? (current_cpu->hardware.h_spsr_abt) : (current_cpu->hardware.h_mbits == ARM_MODE_UNDEFINED) ? (current_cpu->hardware.h_spsr_und) : (current_cpu->hardware.h_mbits == ARM_MODE_SYSTEM) ? ((current_cpu->cgen_rtx_error ("can't read spsr in system mode"), 0)) : ((current_cpu->cgen_rtx_error ("can't read spsr, invalid mode"), 0)); }
166 inline void h_spsr_set (SI newval) { switch (current_cpu->hardware.h_mbits)
168 case ARM_MODE_USER : {
169 current_cpu->cgen_rtx_error ("can't set spsr in user mode");
172 case ARM_MODE_FIQ : {
173 current_cpu->hardware.h_spsr_fiq = newval;
176 case ARM_MODE_IRQ : {
177 current_cpu->hardware.h_spsr_irq = newval;
180 case ARM_MODE_SUPERVISOR : {
181 current_cpu->hardware.h_spsr_svc = newval;
184 case ARM_MODE_ABORT : {
185 current_cpu->hardware.h_spsr_abt = newval;
188 case ARM_MODE_UNDEFINED : {
189 current_cpu->hardware.h_spsr_und = newval;
192 case ARM_MODE_SYSTEM : {
193 current_cpu->cgen_rtx_error ("can't set spsr in system mode");
197 current_cpu->cgen_rtx_error ("can't set spsr, invalid mode");
203 inline SI thumb_h_gr_t_get (UINT regno) const { return current_cpu->hardware.h_gr[regno]; }
204 inline void thumb_h_gr_t_set (UINT regno, SI newval) { current_cpu->hardware.h_gr[regno] = newval;
207 inline SI thumb_h_lr_t_get () const { return current_cpu->hardware.h_gr[((UINT) 14)]; }
208 inline void thumb_h_lr_t_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 14)] = newval;
211 inline SI thumb_h_sp_t_get () const { return current_cpu->hardware.h_gr[((UINT) 13)]; }
212 inline void thumb_h_sp_t_set (SI newval) { current_cpu->hardware.h_gr[((UINT) 13)] = newval;
215 inline SI thumb_h_hiregs_get (UINT regno) const { return current_cpu->hardware.h_gr[((regno) + (8))]; }
216 inline void thumb_h_hiregs_set (UINT regno, SI newval) { current_cpu->hardware.h_gr[((regno) + (8))] = newval;