1 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
5 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
7 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
9 2005-01-10 Andreas Schwab <schwab@suse.de>
11 * disassemble.c (disassemble_init_for_target) <case
12 bfd_arch_ia64>: Set skip_zeroes to 16.
13 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
15 2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
17 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
19 2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
21 * avr-dis.c: Prettyprint. Added printing of symbol names in all
22 memory references. Convert avr_operand() to C90 formatting.
24 2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
26 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
28 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
30 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
31 (no_op_insn): Initialize array with instructions that have no
33 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
35 2004-11-29 Richard Earnshaw <rearnsha@arm.com>
37 * arm-dis.c: Correct top-level comment.
39 2004-11-27 Richard Earnshaw <rearnsha@arm.com>
41 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
42 architecuture defining the insn.
43 (arm_opcodes, thumb_opcodes): Delete. Move to ...
44 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
46 Also include opcode/arm.h.
47 * Makefile.am (arm-dis.lo): Update dependency list.
48 * Makefile.in: Regenerate.
50 2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
52 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
53 reflect the change to the short immediate syntax.
55 2004-11-19 Alan Modra <amodra@bigpond.net.au>
57 * or32-opc.c (debug): Warning fix.
58 * po/POTFILES.in: Regenerate.
60 * maxq-dis.c: Formatting.
61 (print_insn): Warning fix.
63 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
65 * arm-dis.c (WORD_ADDRESS): Define.
66 (print_insn): Use it. Correct big-endian end-of-section handling.
68 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
69 Vineet Sharma <vineets@noida.hcltech.com>
71 * maxq-dis.c: New file.
72 * disassemble.c (ARCH_maxq): Define.
73 (disassembler): Add 'print_insn_maxq_little' for handling maxq
75 * configure.in: Add case for bfd_maxq_arch.
76 * configure: Regenerate.
77 * Makefile.am: Add support for maxq-dis.c
78 * Makefile.in: Regenerate.
79 * aclocal.m4: Regenerate.
81 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
83 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
85 * crx-dis.c: Likewise.
87 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
89 Generally, handle CRISv32.
90 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
91 (struct cris_disasm_data): New type.
92 (format_reg, format_hex, cris_constraint, print_flags)
93 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
95 (format_sup_reg, print_insn_crisv32_with_register_prefix)
96 (print_insn_crisv32_without_register_prefix)
97 (print_insn_crisv10_v32_with_register_prefix)
98 (print_insn_crisv10_v32_without_register_prefix)
99 (cris_parse_disassembler_options): New functions.
100 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
101 parameter. All callers changed.
102 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
104 (cris_constraint) <case 'Y', 'U'>: New cases.
105 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
107 (print_with_operands) <case 'Y'>: New case.
108 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
109 <case 'N', 'Y', 'Q'>: New cases.
110 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
111 (print_insn_cris_with_register_prefix)
112 (print_insn_cris_without_register_prefix): Call
113 cris_parse_disassembler_options.
114 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
115 for CRISv32 and the size of immediate operands. New v32-only
116 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
117 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
118 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
119 Change brp to be v3..v10.
120 (cris_support_regs): New vector.
121 (cris_opcodes): Update head comment. New format characters '[',
122 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
123 Add new opcodes for v32 and adjust existing opcodes to accommodate
124 differences to earlier variants.
125 (cris_cond15s): New vector.
127 2004-11-04 Jan Beulich <jbeulich@novell.com>
129 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
131 (Mp): Use f_mode rather than none at all.
132 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
133 replaces what previously was x_mode; x_mode now means 128-bit SSE
135 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
136 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
137 pinsrw's second operand is Edqw.
138 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
139 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
140 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
141 mode when an operand size override is present or always suffixing.
142 More instructions will need to be added to this group.
143 (putop): Handle new macro chars 'C' (short/long suffix selector),
144 'I' (Intel mode override for following macro char), and 'J' (for
145 adding the 'l' prefix to far branches in AT&T mode). When an
146 alternative was specified in the template, honor macro character when
147 specified for Intel mode.
148 (OP_E): Handle new *_mode values. Correct pointer specifications for
149 memory operands. Consolidate output of index register.
150 (OP_G): Handle new *_mode values.
151 (OP_I): Handle const_1_mode.
152 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
153 respective opcode prefix bits have been consumed.
154 (OP_EM, OP_EX): Provide some default handling for generating pointer
157 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
159 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
162 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
164 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
165 (getregliststring): Support HI/LO and user registers.
166 * crx-opc.c (crx_instruction): Update data structure according to the
167 rearrangement done in CRX opcode header file.
168 (crx_regtab): Likewise.
169 (crx_optab): Likewise.
170 (crx_instruction): Reorder load/stor instructions, remove unsupported
172 support new Co-Processor instruction 'cpi'.
174 2004-10-27 Nick Clifton <nickc@redhat.com>
176 * opcodes/iq2000-asm.c: Regenerate.
177 * opcodes/iq2000-desc.c: Regenerate.
178 * opcodes/iq2000-desc.h: Regenerate.
179 * opcodes/iq2000-dis.c: Regenerate.
180 * opcodes/iq2000-ibld.c: Regenerate.
181 * opcodes/iq2000-opc.c: Regenerate.
182 * opcodes/iq2000-opc.h: Regenerate.
184 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
186 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
187 us4, us5 (respectively).
188 Remove unsupported 'popa' instruction.
189 Reverse operands order in store co-processor instructions.
191 2004-10-15 Alan Modra <amodra@bigpond.net.au>
193 * Makefile.am: Run "make dep-am"
194 * Makefile.in: Regenerate.
196 2004-10-12 Bob Wilson <bob.wilson@acm.org>
198 * xtensa-dis.c: Use ISO C90 formatting.
200 2004-10-09 Alan Modra <amodra@bigpond.net.au>
202 * ppc-opc.c: Revert 2004-09-09 change.
204 2004-10-07 Bob Wilson <bob.wilson@acm.org>
206 * xtensa-dis.c (state_names): Delete.
207 (fetch_data): Use xtensa_isa_maxlength.
208 (print_xtensa_operand): Replace operand parameter with opcode/operand
209 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
210 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
211 instruction bundles. Use xmalloc instead of malloc.
213 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
215 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
218 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
220 * crx-opc.c (crx_instruction): Support Co-processor insns.
221 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
222 (getregliststring): Change function to use the above enum.
223 (print_arg): Handle CO-Processor insns.
224 (crx_cinvs): Add 'b' option to invalidate the branch-target
227 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
229 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
230 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
231 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
232 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
233 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
235 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
237 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
240 2004-09-30 Paul Brook <paul@codesourcery.com>
242 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
243 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
245 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
247 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
248 (CONFIG_STATUS_DEPENDENCIES): New.
250 (config.status): Likewise.
251 * Makefile.in: Regenerated.
253 2004-09-17 Alan Modra <amodra@bigpond.net.au>
255 * Makefile.am: Run "make dep-am".
256 * Makefile.in: Regenerate.
257 * aclocal.m4: Regenerate.
258 * configure: Regenerate.
259 * po/POTFILES.in: Regenerate.
260 * po/opcodes.pot: Regenerate.
262 2004-09-11 Andreas Schwab <schwab@suse.de>
264 * configure: Rebuild.
266 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
268 * ppc-opc.c (L): Make this field not optional.
270 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
272 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
273 Fix parameter to 'm[t|f]csr' insns.
275 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
277 * configure.in: Autoupdate to autoconf 2.59.
278 * aclocal.m4: Rebuild with aclocal 1.4p6.
279 * configure: Rebuild with autoconf 2.59.
280 * Makefile.in: Rebuild with automake 1.4p6 (picking up
281 bfd changes for autoconf 2.59 on the way).
282 * config.in: Rebuild with autoheader 2.59.
284 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
286 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
288 2004-07-30 Michal Ludvig <mludvig@suse.cz>
290 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
291 (GRPPADLCK2): New define.
292 (twobyte_has_modrm): True for 0xA6.
293 (grps): GRPPADLCK2 for opcode 0xA6.
295 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
297 Introduce SH2a support.
298 * sh-opc.h (arch_sh2a_base): Renumber.
299 (arch_sh2a_nofpu_base): Remove.
300 (arch_sh_base_mask): Adjust.
301 (arch_opann_mask): New.
302 (arch_sh2a, arch_sh2a_nofpu): Adjust.
303 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
304 (sh_table): Adjust whitespace.
305 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
306 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
307 instruction list throughout.
308 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
309 of arch_sh2a in instruction list throughout.
310 (arch_sh2e_up): Accomodate above changes.
311 (arch_sh2_up): Ditto.
312 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
313 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
314 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
315 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
316 * sh-opc.h (arch_sh2a_nofpu): New.
317 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
318 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
320 2004-01-20 DJ Delorie <dj@redhat.com>
321 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
322 2003-12-29 DJ Delorie <dj@redhat.com>
323 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
324 sh_opcode_info, sh_table): Add sh2a support.
325 (arch_op32): New, to tag 32-bit opcodes.
326 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
327 2003-12-02 Michael Snyder <msnyder@redhat.com>
328 * sh-opc.h (arch_sh2a): Add.
329 * sh-dis.c (arch_sh2a): Handle.
330 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
332 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
334 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
336 2004-07-22 Nick Clifton <nickc@redhat.com>
339 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
340 insns - this is done by objdump itself.
341 * h8500-dis.c (print_insn_h8500): Likewise.
343 2004-07-21 Jan Beulich <jbeulich@novell.com>
345 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
346 regardless of address size prefix in effect.
347 (ptr_reg): Size or address registers does not depend on rex64, but
348 on the presence of an address size override.
349 (OP_MMX): Use rex.x only for xmm registers.
350 (OP_EM): Use rex.z only for xmm registers.
352 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
354 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
355 move/branch operations to the bottom so that VR5400 multimedia
356 instructions take precedence in disassembly.
358 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
360 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
361 ISA-specific "break" encoding.
363 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
365 * arm-opc.h: Fix typo in comment.
367 2004-07-11 Andreas Schwab <schwab@suse.de>
369 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
371 2004-07-09 Andreas Schwab <schwab@suse.de>
373 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
375 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
377 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
378 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
379 (crx-dis.lo): New target.
380 (crx-opc.lo): Likewise.
381 * Makefile.in: Regenerate.
382 * configure.in: Handle bfd_crx_arch.
383 * configure: Regenerate.
384 * crx-dis.c: New file.
385 * crx-opc.c: New file.
386 * disassemble.c (ARCH_crx): Define.
387 (disassembler): Handle ARCH_crx.
389 2004-06-29 James E Wilson <wilson@specifixinc.com>
391 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
392 * ia64-asmtab.c: Regnerate.
394 2004-06-28 Alan Modra <amodra@bigpond.net.au>
396 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
397 (extract_fxm): Don't test dialect.
398 (XFXFXM_MASK): Include the power4 bit.
399 (XFXM): Add p4 param.
400 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
402 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
404 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
405 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
407 2004-06-26 Alan Modra <amodra@bigpond.net.au>
409 * ppc-opc.c (BH, XLBH_MASK): Define.
410 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
412 2004-06-24 Alan Modra <amodra@bigpond.net.au>
414 * i386-dis.c (x_mode): Comment.
415 (two_source_ops): File scope.
416 (float_mem): Correct fisttpll and fistpll.
417 (float_mem_mode): New table.
419 (OP_E): Correct intel mode PTR output.
420 (ptr_reg): Use open_char and close_char.
421 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
422 operands. Set two_source_ops.
424 2004-06-15 Alan Modra <amodra@bigpond.net.au>
426 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
427 instead of _raw_size.
429 2004-06-08 Jakub Jelinek <jakub@redhat.com>
431 * ia64-gen.c (in_iclass): Handle more postinc st
433 * ia64-asmtab.c: Rebuilt.
435 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
437 * s390-opc.txt: Correct architecture mask for some opcodes.
438 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
439 in the esa mode as well.
441 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
443 * sh-dis.c (target_arch): Make unsigned.
444 (print_insn_sh): Replace (most of) switch with a call to
445 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
446 * sh-opc.h: Redefine architecture flags values.
447 Add sh3-nommu architecture.
448 Reorganise <arch>_up macros so they make more visual sense.
449 (SH_MERGE_ARCH_SET): Define new macro.
450 (SH_VALID_BASE_ARCH_SET): Likewise.
451 (SH_VALID_MMU_ARCH_SET): Likewise.
452 (SH_VALID_CO_ARCH_SET): Likewise.
453 (SH_VALID_ARCH_SET): Likewise.
454 (SH_MERGE_ARCH_SET_VALID): Likewise.
455 (SH_ARCH_SET_HAS_FPU): Likewise.
456 (SH_ARCH_SET_HAS_DSP): Likewise.
457 (SH_ARCH_UNKNOWN_ARCH): Likewise.
458 (sh_get_arch_from_bfd_mach): Add prototype.
459 (sh_get_arch_up_from_bfd_mach): Likewise.
460 (sh_get_bfd_mach_from_arch_set): Likewise.
461 (sh_merge_bfd_arc): Likewise.
463 2004-05-24 Peter Barada <peter@the-baradas.com>
465 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
466 into new match_insn_m68k function. Loop over canidate
467 matches and select first that completely matches.
468 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
469 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
470 to verify addressing for MAC/EMAC.
471 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
472 reigster halves since 'fpu' and 'spl' look misleading.
473 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
474 * m68k-opc.c: Rearragne mac/emac cases to use longest for
475 first, tighten up match masks.
476 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
477 'size' from special case code in print_insn_m68k to
478 determine decode size of insns.
480 2004-05-19 Alan Modra <amodra@bigpond.net.au>
482 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
483 well as when -mpower4.
485 2004-05-13 Nick Clifton <nickc@redhat.com>
487 * po/fr.po: Updated French translation.
489 2004-05-05 Peter Barada <peter@the-baradas.com>
491 * m68k-dis.c(print_insn_m68k): Add new chips, use core
492 variants in arch_mask. Only set m68881/68851 for 68k chips.
493 * m68k-op.c: Switch from ColdFire chips to core variants.
495 2004-05-05 Alan Modra <amodra@bigpond.net.au>
498 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
500 2004-04-29 Ben Elliston <bje@au.ibm.com>
502 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
503 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
505 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
507 * sh-dis.c (print_insn_sh): Print the value in constant pool
508 as a symbol if it looks like a symbol.
510 2004-04-22 Peter Barada <peter@the-baradas.com>
512 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
513 appropriate ColdFire architectures.
514 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
516 Add EMAC instructions, fix MAC instructions. Remove
517 macmw/macml/msacmw/msacml instructions since mask addressing now
520 2004-04-20 Jakub Jelinek <jakub@redhat.com>
522 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
523 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
524 suffix. Use fmov*x macros, create all 3 fpsize variants in one
525 macro. Adjust all users.
527 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
529 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
532 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
534 * m32r-asm.c: Regenerate.
536 2004-03-29 Stan Shebs <shebs@apple.com>
538 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
541 2004-03-19 Alan Modra <amodra@bigpond.net.au>
543 * aclocal.m4: Regenerate.
544 * config.in: Regenerate.
545 * configure: Regenerate.
546 * po/POTFILES.in: Regenerate.
547 * po/opcodes.pot: Regenerate.
549 2004-03-16 Alan Modra <amodra@bigpond.net.au>
551 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
553 * ppc-opc.c (RA0): Define.
554 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
555 (RAOPT): Rename from RAO. Update all uses.
556 (powerpc_opcodes): Use RA0 as appropriate.
558 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
560 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
562 2004-03-15 Alan Modra <amodra@bigpond.net.au>
564 * sparc-dis.c (print_insn_sparc): Update getword prototype.
566 2004-03-12 Michal Ludvig <mludvig@suse.cz>
568 * i386-dis.c (GRPPLOCK): Delete.
569 (grps): Delete GRPPLOCK entry.
571 2004-03-12 Alan Modra <amodra@bigpond.net.au>
573 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
575 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
577 (dis386): Use NOP_Fixup on "nop".
578 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
579 (twobyte_has_modrm): Set for 0xa7.
580 (padlock_table): Delete. Move to..
581 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
583 (print_insn): Revert PADLOCK_SPECIAL code.
584 (OP_E): Delete sfence, lfence, mfence checks.
586 2004-03-12 Jakub Jelinek <jakub@redhat.com>
588 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
589 (INVLPG_Fixup): New function.
590 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
592 2004-03-12 Michal Ludvig <mludvig@suse.cz>
594 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
595 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
596 (padlock_table): New struct with PadLock instructions.
597 (print_insn): Handle PADLOCK_SPECIAL.
599 2004-03-12 Alan Modra <amodra@bigpond.net.au>
601 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
602 (OP_E): Twiddle clflush to sfence here.
604 2004-03-08 Nick Clifton <nickc@redhat.com>
606 * po/de.po: Updated German translation.
608 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
610 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
611 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
612 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
615 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
617 * frv-asm.c: Regenerate.
618 * frv-desc.c: Regenerate.
619 * frv-desc.h: Regenerate.
620 * frv-dis.c: Regenerate.
621 * frv-ibld.c: Regenerate.
622 * frv-opc.c: Regenerate.
623 * frv-opc.h: Regenerate.
625 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
627 * frv-desc.c, frv-opc.c: Regenerate.
629 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
631 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
633 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
635 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
636 Also correct mistake in the comment.
638 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
640 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
641 ensure that double registers have even numbers.
642 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
643 that reserved instruction 0xfffd does not decode the same
645 * sh-opc.h: Add REG_N_D nibble type and use it whereever
646 REG_N refers to a double register.
647 Add REG_N_B01 nibble type and use it instead of REG_NM
649 Adjust the bit patterns in a few comments.
651 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
653 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
655 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
657 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
659 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
661 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
663 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
665 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
666 mtivor32, mtivor33, mtivor34.
668 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
670 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
672 2004-02-10 Petko Manolov <petkan@nucleusys.com>
674 * arm-opc.h Maverick accumulator register opcode fixes.
676 2004-02-13 Ben Elliston <bje@wasabisystems.com>
678 * m32r-dis.c: Regenerate.
680 2004-01-27 Michael Snyder <msnyder@redhat.com>
682 * sh-opc.h (sh_table): "fsrra", not "fssra".
684 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
686 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
689 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
691 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
693 2004-01-19 Alan Modra <amodra@bigpond.net.au>
695 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
696 1. Don't print scale factor on AT&T mode when index missing.
698 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
700 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
701 when loaded into XR registers.
703 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
705 * frv-desc.h: Regenerate.
706 * frv-desc.c: Regenerate.
707 * frv-opc.c: Regenerate.
709 2004-01-13 Michael Snyder <msnyder@redhat.com>
711 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
713 2004-01-09 Paul Brook <paul@codesourcery.com>
715 * arm-opc.h (arm_opcodes): Move generic mcrr after known
718 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
720 * Makefile.am (libopcodes_la_DEPENDENCIES)
721 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
722 comment about the problem.
723 * Makefile.in: Regenerate.
725 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
727 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
728 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
729 cut&paste errors in shifting/truncating numerical operands.
730 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
731 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
732 (parse_uslo16): Likewise.
733 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
734 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
735 (parse_s12): Likewise.
736 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
737 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
738 (parse_uslo16): Likewise.
739 (parse_uhi16): Parse gothi and gotfuncdeschi.
740 (parse_d12): Parse got12 and gotfuncdesc12.
741 (parse_s12): Likewise.
743 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
745 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
746 instruction which looks similar to an 'rla' instruction.
748 For older changes see ChangeLog-0203
754 version-control: never