OSDN Git Service

(root) / nxt-jsp / etrobo-atk.git / blob
? search:


457442732587e27cc699cf8947c9a602151fec1c
[nxt-jsp/etrobo-atk.git] / nxtOSEK / toppers_jsp / pdic / simple_sio / upd72001.c
1 /*
2  *  TOPPERS/JSP Kernel
3  *      Toyohashi Open Platform for Embedded Real-Time Systems/
4  *      Just Standard Profile Kernel
5  * 
6  *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
7  *                              Toyohashi Univ. of Technology, JAPAN
8  * 
9  *  ¾åµ­Ãøºî¸¢¼Ô¤Ï¡¤°Ê²¼¤Î (1)¡Á(4) ¤Î¾ò·ï¤«¡¤Free Software Foundation 
10  *  ¤Ë¤è¤Ã¤Æ¸øɽ¤µ¤ì¤Æ¤¤¤ë GNU General Public License ¤Î Version 2 ¤Ëµ­
11  *  ½Ò¤µ¤ì¤Æ¤¤¤ë¾ò·ï¤òËþ¤¿¤¹¾ì¹ç¤Ë¸Â¤ê¡¤ËÜ¥½¥Õ¥È¥¦¥§¥¢¡ÊËÜ¥½¥Õ¥È¥¦¥§¥¢
12  *  ¤ò²þÊѤ·¤¿¤â¤Î¤ò´Þ¤à¡¥°Ê²¼Æ±¤¸¡Ë¤ò»ÈÍÑ¡¦Ê£À½¡¦²þÊÑ¡¦ºÆÇÛÉۡʰʲ¼¡¤
13  *  ÍøÍѤȸƤ֡ˤ¹¤ë¤³¤È¤ò̵½þ¤ÇµöÂú¤¹¤ë¡¥
14  *  (1) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ò¥½¡¼¥¹¥³¡¼¥É¤Î·Á¤ÇÍøÍѤ¹¤ë¾ì¹ç¤Ë¤Ï¡¤¾åµ­¤ÎÃøºî
15  *      ¸¢É½¼¨¡¤¤³¤ÎÍøÍѾò·ï¤ª¤è¤Ó²¼µ­¤Î̵Êݾڵ¬Ä꤬¡¤¤½¤Î¤Þ¤Þ¤Î·Á¤Ç¥½¡¼
16  *      ¥¹¥³¡¼¥ÉÃæ¤Ë´Þ¤Þ¤ì¤Æ¤¤¤ë¤³¤È¡¥
17  *  (2) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ò¡¤¥é¥¤¥Ö¥é¥ê·Á¼°¤Ê¤É¡¤Â¾¤Î¥½¥Õ¥È¥¦¥§¥¢³«È¯¤Ë»È
18  *      ÍѤǤ­¤ë·Á¤ÇºÆÇÛÉÛ¤¹¤ë¾ì¹ç¤Ë¤Ï¡¤ºÆÇÛÉÛ¤Ëȼ¤¦¥É¥­¥å¥á¥ó¥È¡ÊÍøÍÑ
19  *      ¼Ô¥Þ¥Ë¥å¥¢¥ë¤Ê¤É¡Ë¤Ë¡¤¾åµ­¤ÎÃøºî¸¢É½¼¨¡¤¤³¤ÎÍøÍѾò·ï¤ª¤è¤Ó²¼µ­
20  *      ¤Î̵Êݾڵ¬Äê¤ò·ÇºÜ¤¹¤ë¤³¤È¡¥
21  *  (3) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ò¡¤µ¡´ï¤ËÁȤ߹þ¤à¤Ê¤É¡¤Â¾¤Î¥½¥Õ¥È¥¦¥§¥¢³«È¯¤Ë»È
22  *      ÍѤǤ­¤Ê¤¤·Á¤ÇºÆÇÛÉÛ¤¹¤ë¾ì¹ç¤Ë¤Ï¡¤¼¡¤Î¤¤¤º¤ì¤«¤Î¾ò·ï¤òËþ¤¿¤¹¤³
23  *      ¤È¡¥
24  *    (a) ºÆÇÛÉÛ¤Ëȼ¤¦¥É¥­¥å¥á¥ó¥È¡ÊÍøÍѼԥޥ˥奢¥ë¤Ê¤É¡Ë¤Ë¡¤¾åµ­¤ÎÃø
25  *        ºî¸¢É½¼¨¡¤¤³¤ÎÍøÍѾò·ï¤ª¤è¤Ó²¼µ­¤Î̵Êݾڵ¬Äê¤ò·ÇºÜ¤¹¤ë¤³¤È¡¥
26  *    (b) ºÆÇÛÉۤηÁÂÖ¤ò¡¤Ê̤ËÄê¤á¤ëÊýË¡¤Ë¤è¤Ã¤Æ¡¤TOPPERS¥×¥í¥¸¥§¥¯¥È¤Ë
27  *        Êó¹ð¤¹¤ë¤³¤È¡¥
28  *  (4) ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ÎÍøÍѤˤè¤êľÀÜŪ¤Þ¤¿¤Ï´ÖÀÜŪ¤ËÀ¸¤¸¤ë¤¤¤«¤Ê¤ë»
29  *      ³²¤«¤é¤â¡¤¾åµ­Ãøºî¸¢¼Ô¤ª¤è¤ÓTOPPERS¥×¥í¥¸¥§¥¯¥È¤òÌÈÀÕ¤¹¤ë¤³¤È¡¥
30  * 
31  *  ËÜ¥½¥Õ¥È¥¦¥§¥¢¤Ï¡¤ÌµÊݾڤÇÄ󶡤µ¤ì¤Æ¤¤¤ë¤â¤Î¤Ç¤¢¤ë¡¥¾åµ­Ãøºî¸¢¼Ô¤ª
32  *  ¤è¤ÓTOPPERS¥×¥í¥¸¥§¥¯¥È¤Ï¡¤ËÜ¥½¥Õ¥È¥¦¥§¥¢¤Ë´Ø¤·¤Æ¡¤¤½¤ÎŬÍѲÄǽÀ­¤â
33  *  ´Þ¤á¤Æ¡¤¤¤¤«¤Ê¤ëÊݾڤâ¹Ô¤ï¤Ê¤¤¡¥¤Þ¤¿¡¤ËÜ¥½¥Õ¥È¥¦¥§¥¢¤ÎÍøÍѤˤè¤êľ
34  *  ÀÜŪ¤Þ¤¿¤Ï´ÖÀÜŪ¤ËÀ¸¤¸¤¿¤¤¤«¤Ê¤ë»³²¤Ë´Ø¤·¤Æ¤â¡¤¤½¤ÎÀÕǤ¤òÉé¤ï¤Ê¤¤¡¥
35  * 
36  *  @(#) $Id: upd72001.c,v 1.4 2003/12/13 06:21:49 hiro Exp $
37  */
38
39 /*
40  *      ¦ÌPD72001ÍÑ ´Ê°×SIO¥É¥é¥¤¥Ð
41  */
42
43 #include <s_services.h>
44 #include <upd72001.h>
45
46 /*
47  *  ¥Ç¥Ð¥¤¥¹¥ì¥¸¥¹¥¿¤Î¥¢¥¯¥»¥¹´Ö³Ö»þ´Ö¡Ênsecñ°Ì¡Ë
48  *
49  *  200¤È¤¤¤¦Ãͤˤ¢¤Þ¤êº¬µò¤Ï¤Ê¤¤¡¥
50  */
51 #define UPD72001_DELAY  200
52
53 /*
54  *  ¦ÌPD72001¤Î¥ì¥¸¥¹¥¿¤ÎÈÖ¹æ
55  */
56 #define UPD72001_CR0    0x00u           /* ¥³¥ó¥È¥í¡¼¥ë¥ì¥¸¥¹¥¿ */
57 #define UPD72001_CR1    0x01u
58 #define UPD72001_CR2    0x02u
59 #define UPD72001_CR3    0x03u
60 #define UPD72001_CR4    0x04u
61 #define UPD72001_CR5    0x05u
62 #define UPD72001_CR10   0x0au
63 #define UPD72001_CR12   0x0cu
64 #define UPD72001_CR14   0x0eu
65 #define UPD72001_CR15   0x0fu
66
67 #define UPD72001_SR0    0x00u           /* ¥¹¥Æ¡¼¥¿¥¹¥ì¥¸¥¹¥¿ */
68
69 /*
70  *  ¥³¥ó¥È¥í¡¼¥ë¥ì¥¸¥¹¥¿¤ÎÀßÄêÃÍ
71  */
72 #define CR_RESET        0x18u           /* ¥Ý¡¼¥È¥ê¥»¥Ã¥È¥³¥Þ¥ó¥É */
73
74 #define CR0_EOI         0x38u           /* EOI¡ÊEnd of Interrupt¡Ë*/
75
76 #define CR1_DOWN        0x00u           /* Á´³ä¹þ¤ß¤ò¶Ø»ß */
77 #define CR1_RECV        0x10u           /* ¼õ¿®³ä¹þ¤ßµö²Ä¥Ó¥Ã¥È */
78 #define CR1_SEND        0x02u           /* Á÷¿®³ä¹þ¤ßµö²Ä¥Ó¥Ã¥È */
79
80 #define CR3_DEF         0xc1u           /* ¥Ç¡¼¥¿ 8bit¡¤¼õ¿®¥¤¥Í¡¼¥Ö¥ë */
81 #define CR4_DEF         0x44u           /* ¥¹¥È¥Ã¥×¥Ó¥Ã¥È 1bit¡¤¥Ñ¥ê¥Æ¥£¤Ê¤· */
82 #define CR5_DEF         0xeau           /* ¥Ç¡¼¥¿ 8bit¡¤Á÷¿®¥¤¥Í¡¼¥Ö¥ë */
83
84 #define CR10_DEF        0x00u           /* NRZ */
85 #define CR14_DEF        0x07u           /* ¥Ü¡¼¥ì¡¼¥È¥¸¥§¥Í¥ì¡¼¥¿¥¤¥Í¡¼¥Ö¥ë */
86 #define CR15_DEF        0x56u           /* ¥Ü¡¼¥ì¡¼¥È¥¸¥§¥Í¥ì¡¼¥¿»ÈÍÑ */
87
88 #define SR0_RECV        0x01u           /* ¼õ¿®ÄÌÃΥӥåȠ*/
89 #define SR0_SEND        0x04u           /* Á÷¿®²Äǽ¥Ó¥Ã¥È */
90
91 /*
92  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È½é´ü²½¥Ö¥í¥Ã¥¯¤ÎÄêµÁ
93  */
94 typedef struct sio_port_initialization_block {
95         VP      data;           /* ¥Ç¡¼¥¿¥ì¥¸¥¹¥¿¤ÎÈÖÃÏ */
96         VP      ctrl;           /* ¥³¥ó¥È¥í¡¼¥ë¥ì¥¸¥¹¥¿¤ÎÈÖÃÏ */
97
98         UB      cr3_def;        /* CR3¤ÎÀßÄêÃ͡ʼõ¿®¥Ó¥Ã¥È¿ô¡Ë*/
99         UB      cr4_def;        /* CR4¤ÎÀßÄêÃÍ¡Ê¥¹¥È¥Ã¥×¥Ó¥Ã¥È¡¤¥Ñ¥ê¥Æ¥£¡Ë*/
100         UB      cr5_def;        /* CR5¤ÎÀßÄêÃÍ¡ÊÁ÷¿®¥Ó¥Ã¥È¿ô¡Ë*/
101         UB      brg1_def;       /* ¥Ü¡¼¥ì¡¼¥È¾å°Ì¤ÎÀßÄêÃÍ */
102         UB      brg2_def;       /* ¥Ü¡¼¥ì¡¼¥È²¼°Ì¤ÎÀßÄêÃÍ */
103 } SIOPINIB;
104
105 /*
106  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯¤ÎÄêµÁ
107  */
108 struct sio_port_control_block {
109         const SIOPINIB  *siopinib;      /* ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È½é´ü²½¥Ö¥í¥Ã¥¯ */
110         VP_INT          exinf;          /* ³ÈÄ¥¾ðÊó */
111         BOOL            openflag;       /* ¥ª¡¼¥×¥óºÑ¤ß¥Õ¥é¥° */
112         UB              cr1;            /* CR1¤ÎÀßÄêÃ͡ʳä¹þ¤ßµö²Ä¡Ë*/
113         BOOL            getready;       /* Ê¸»ú¤ò¼õ¿®¤·¤¿¾õÂÖ */
114         BOOL            putready;       /* Ê¸»ú¤òÁ÷¿®¤Ç¤­¤ë¾õÂÖ */
115 };
116
117 /*
118  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È½é´ü²½¥Ö¥í¥Ã¥¯
119  *
120  *  ID = 1 ¤ò¥Ý¡¼¥ÈB¡¤ID = 2 ¤ò¥Ý¡¼¥ÈA¤ËÂбþ¤µ¤»¤Æ¤¤¤ë¡¥
121  */
122 const SIOPINIB siopinib_table[TNUM_SIOP] = {
123         { (VP) TADR_UPD72001_DATAB, (VP) TADR_UPD72001_CTRLB,
124                 CR3_DEF, CR4_DEF, CR5_DEF, BRG1_DEF, BRG2_DEF },
125 #if TNUM_SIOP >= 2
126         { (VP) TADR_UPD72001_DATAA, (VP) TADR_UPD72001_CTRLA,
127                 CR3_DEF, CR4_DEF, CR5_DEF, BRG1_DEF, BRG2_DEF },
128 #endif /* TNUM_SIOP >= 2 */
129 };
130
131 /*
132  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯¤Î¥¨¥ê¥¢
133  */
134 SIOPCB  siopcb_table[TNUM_SIOP];
135
136 /*
137  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥ÈID¤«¤é´ÉÍý¥Ö¥í¥Ã¥¯¤ò¼è¤ê½Ð¤¹¤¿¤á¤Î¥Þ¥¯¥í
138  */
139 #define INDEX_SIOP(siopid)      ((UINT)((siopid) - 1))
140 #define get_siopcb(siopid)      (&(siopcb_table[INDEX_SIOP(siopid)]))
141
142 /*
143  *  ¥Ç¥Ð¥¤¥¹¥ì¥¸¥¹¥¿¤Ø¤Î¥¢¥¯¥»¥¹´Ø¿ô
144  */
145 Inline UB
146 upd72001_read_reg(VP addr)
147 {
148         UB      val;
149
150         val = (UB) upd72001_reb_reg(addr);
151         sil_dly_nse(UPD72001_DELAY);
152         return(val);
153 }
154
155 Inline void
156 upd72001_write_reg(VP addr, UB val)
157 {
158         upd72001_wrb_reg(addr, (VB) val);
159         sil_dly_nse(UPD72001_DELAY);
160 }
161
162 Inline UB
163 upd72001_read_ctrl(VP addr, UB reg)
164 {
165         upd72001_write_reg(addr, reg);
166         return(upd72001_read_reg(addr));
167 }
168
169 Inline void
170 upd72001_write_ctrl(VP addr, UB reg, UB val)
171 {
172         upd72001_write_reg(addr, reg);
173         upd72001_write_reg(addr, val);
174 }
175
176 Inline void
177 upd72001_write_brg(VP addr, UB reg, UB val, UB brg2, UB brg1)
178 {
179         upd72001_write_reg(addr, reg);
180         upd72001_write_reg(addr, val);
181         upd72001_write_reg(addr, brg2);
182         upd72001_write_reg(addr, brg1);
183         (void) upd72001_read_reg(addr);         /* ¥À¥ß¡¼¥ê¡¼¥É */
184 }
185
186 /*
187  *  ¾õÂÖ¤ÎÆɽФ·¡ÊSR0¤ÎÆɽФ·¡Ë
188  *
189  *  ¦ÌPD72001¤Ï¡¤¾õÂÖ¡ÊSR0¡Ë¤ò°ìÅÙÆɤà¤È¼õ¿®ÄÌÃΥӥåȤ¬Íî¤Á¤Æ¤·¤Þ¤¦¤¿
190  *  ¤á¡¤¾õÂÖ¤òÆɤ߽Ф¹´Ø¿ô¤òÀߤ±¡¤¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯Ãæ¤Î
191  *  getready ¤Ë¼õ¿®ÄÌÃξõÂÖ¡¤putready ¤ËÁ÷¿®²Äǽ¾õÂÖ¤òÊݸ¤·¤Æ¤¤¤ë¡ÊÁ÷
192  *  ¿®²Äǽ¾õÂÖ¤ÎÊݸ¤ÏÉÔÍפ«¤â¤·¤ì¤Ê¤¤¡Ë¡¥
193  *  ¾õÂ֥쥸¥¹¥¿¤òÆɤó¤Ç¤â¼õ¿®ÄÌÃΥӥåȤ¬Íî¤Á¤Ê¤¤¥Ç¥Ð¥¤¥¹¡Ê¤³¤Á¤é¤¬Éá
194  *  Ä̤Ȼפï¤ì¤ë¡Ë¤Ç¤Ï¡¤¤³¤Î´Ø¿ô¤ÏɬÍפʤ¤¡¥
195  */
196 static void
197 upd72001_get_stat(SIOPCB *siopcb)
198 {
199         UB      sr0;
200
201         sr0 = upd72001_read_ctrl(siopcb->siopinib->ctrl, UPD72001_SR0);
202         if ((sr0 & SR0_RECV) != 0) {
203                 siopcb->getready = TRUE;
204         }
205         if ((sr0 & SR0_SEND) != 0) {
206                 siopcb->putready = TRUE;
207         }
208 }
209
210 /*
211  *  Ê¸»ú¤ò¼õ¿®¤Ç¤­¤ë¤«¡©
212  */
213 Inline BOOL
214 upd72001_getready(SIOPCB *siopcb)
215 {
216         upd72001_get_stat(siopcb);
217         return(siopcb->getready);
218 }
219
220 /*
221  *  Ê¸»ú¤òÁ÷¿®¤Ç¤­¤ë¤«¡©
222  */
223 Inline BOOL
224 upd72001_putready(SIOPCB *siopcb)
225 {
226         upd72001_get_stat(siopcb);
227         return(siopcb->putready);
228 }
229
230 /*
231  *  ¼õ¿®¤·¤¿Ê¸»ú¤Î¼è½Ð¤·
232  */
233 Inline char
234 upd72001_getchar(SIOPCB *siopcb)
235 {
236         siopcb->getready = FALSE;
237         return((char) upd72001_read_reg(siopcb->siopinib->data));
238 }
239
240 /*
241  *  Á÷¿®¤¹¤ëʸ»ú¤Î½ñ¹þ¤ß
242  */
243 Inline void
244 upd72001_putchar(SIOPCB *siopcb, char c)
245 {
246         siopcb->putready = FALSE;
247         upd72001_write_reg(siopcb->siopinib->data, (UB) c);
248 }
249
250 /*
251  *  EOI¡ÊEnd Of Interrupt¡Ëȯ¹Ô
252  */
253 Inline void
254 upd72001_eoi()
255 {
256         upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA, UPD72001_CR0, CR0_EOI);
257 }
258
259 /*
260  *  SIO¥É¥é¥¤¥Ð¤Î½é´ü²½¥ë¡¼¥Á¥ó
261  */
262 void
263 upd72001_initialize()
264 {
265         SIOPCB  *siopcb;
266         UINT    i;
267
268         /*
269          *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È´ÉÍý¥Ö¥í¥Ã¥¯¤Î½é´ü²½
270          */
271         for (siopcb = siopcb_table, i = 0; i < TNUM_SIOP; siopcb++, i++) {
272                 siopcb->siopinib = &(siopinib_table[i]);
273                 siopcb->openflag = FALSE;
274         }
275 }
276
277 /*
278  *  ¥ª¡¼¥×¥ó¤·¤Æ¤¤¤ë¥Ý¡¼¥È¤¬¤¢¤ë¤«¡©
279  */
280 BOOL
281 upd72001_openflag(void)
282 {
283 #if TNUM_SIOP < 2
284         return(siopcb_table[0].openflag);
285 #else /* TNUM_SIOP < 2 */
286         return(siopcb_table[0].openflag || siopcb_table[1].openflag);
287 #endif /* TNUM_SIOP < 2 */
288 }
289
290 /*
291  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤Î¥ª¡¼¥×¥ó
292  */
293 SIOPCB *
294 upd72001_opn_por(ID siopid, VP_INT exinf)
295 {
296         SIOPCB          *siopcb;
297         const SIOPINIB  *siopinib;
298
299         siopcb = get_siopcb(siopid);
300         siopinib = siopcb->siopinib;
301
302         upd72001_write_reg(siopinib->ctrl, CR_RESET);
303         if (!upd72001_openflag()) {
304                 upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA,
305                                                 UPD72001_CR2, 0x18);
306                 upd72001_write_ctrl((VP) TADR_UPD72001_CTRLB,
307                                                 UPD72001_CR2, 0x00);
308         }
309         siopcb->cr1 = CR1_DOWN;
310         upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
311         upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR4, siopinib->cr4_def);
312         upd72001_write_brg(siopinib->ctrl, UPD72001_CR12, 
313                                 0x01, siopinib->brg2_def, siopinib->brg1_def);
314         upd72001_write_brg(siopinib->ctrl, UPD72001_CR12,
315                                 0x02, siopinib->brg2_def, siopinib->brg1_def);
316         upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR15, CR15_DEF);
317         upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR14, CR14_DEF);
318         upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR10, CR10_DEF);
319         upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR3, siopinib->cr3_def);
320         upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR5, siopinib->cr5_def);
321         siopcb->exinf = exinf;
322         siopcb->getready = siopcb->putready = FALSE;
323         siopcb->openflag = TRUE;
324         return(siopcb);
325 }
326
327 /*
328  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤Î¥¯¥í¡¼¥º
329  */
330 void
331 upd72001_cls_por(SIOPCB *siopcb)
332 {
333         upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, CR1_DOWN);
334         siopcb->openflag = FALSE;
335 }
336
337 /*
338  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤Ø¤Îʸ»úÁ÷¿®
339  */
340 BOOL
341 upd72001_snd_chr(SIOPCB *siopcb, char c)
342 {
343         if (upd72001_putready(siopcb)) {
344                 upd72001_putchar(siopcb, c);
345                 return(TRUE);
346         }
347         return(FALSE);
348 }
349
350 /*
351  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤«¤é¤Îʸ»ú¼õ¿®
352  */
353 INT
354 upd72001_rcv_chr(SIOPCB *siopcb)
355 {
356         if (upd72001_getready(siopcb)) {
357                 return((INT)(UB) upd72001_getchar(siopcb));
358         }
359         return(-1);
360 }
361
362 /*
363  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤«¤é¤Î¥³¡¼¥ë¥Ð¥Ã¥¯¤Îµö²Ä
364  */
365 void
366 upd72001_ena_cbr(SIOPCB *siopcb, UINT cbrtn)
367 {
368         UB      cr1_bit = 0;
369
370         switch (cbrtn) {
371         case SIO_ERDY_SND:
372                 cr1_bit = CR1_SEND;
373                 break;
374         case SIO_ERDY_RCV:
375                 cr1_bit = CR1_RECV;
376                 break;
377         }
378         siopcb->cr1 |= cr1_bit;
379         upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
380 }
381
382 /*
383  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤«¤é¤Î¥³¡¼¥ë¥Ð¥Ã¥¯¤Î¶Ø»ß
384  */
385 void
386 upd72001_dis_cbr(SIOPCB *siopcb, UINT cbrtn)
387 {
388         UB      cr1_bit = 0;
389
390         switch (cbrtn) {
391         case SIO_ERDY_SND:
392                 cr1_bit = CR1_SEND;
393                 break;
394         case SIO_ERDY_RCV:
395                 cr1_bit = CR1_RECV;
396                 break;
397         }
398         siopcb->cr1 &= ~cr1_bit;
399         upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
400 }
401
402 /*
403  *  ¥·¥ê¥¢¥ëI/O¥Ý¡¼¥È¤ËÂФ¹¤ë³ä¹þ¤ß½èÍý
404  */
405 static void
406 upd72001_isr_siop(SIOPCB *siopcb)
407 {
408         if ((siopcb->cr1 & CR1_RECV) != 0 && upd72001_getready(siopcb)) {
409                 /*
410                  *  ¼õ¿®ÄÌÃÎ¥³¡¼¥ë¥Ð¥Ã¥¯¥ë¡¼¥Á¥ó¤ò¸Æ¤Ó½Ð¤¹¡¥
411                  */
412                 upd72001_ierdy_rcv(siopcb->exinf);
413         }
414         if ((siopcb->cr1 & CR1_SEND) != 0 && upd72001_putready(siopcb)) {
415                 /*
416                  *  Á÷¿®²Äǽ¥³¡¼¥ë¥Ð¥Ã¥¯¥ë¡¼¥Á¥ó¤ò¸Æ¤Ó½Ð¤¹¡¥
417                  */
418                 upd72001_ierdy_snd(siopcb->exinf);
419         }
420 }
421
422 /*
423  *  SIO¤Î³ä¹þ¤ß¥µ¡¼¥Ó¥¹¥ë¡¼¥Á¥ó
424  */
425 void
426 upd72001_isr()
427 {
428         if (siopcb_table[0].openflag) {
429                 upd72001_isr_siop(&(siopcb_table[0]));
430         }
431 #if TNUM_SIOP >= 2
432         if (siopcb_table[1].openflag) {
433                 upd72001_isr_siop(&(siopcb_table[1]));
434         }
435 #endif /* TNUM_SIOP >= 2 */
436         upd72001_eoi();
437 }
ETロボコン用ATKパッケージ (非公式)
About OSDN
Find Software
Develop Software
Help