1 #define _FP_W_TYPE_SIZE 32
2 #define _FP_W_TYPE unsigned int
3 #define _FP_WS_TYPE signed int
6 /* The type of the result of a floating point comparison. This must
7 match `__libgcc_cmp_return__' in GCC for the target. */
8 typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
9 #define CMPtype __gcc_CMPtype
11 #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
12 __asm__ ("add{l} {%11,%3|%3,%11}\n\t" \
13 "adc{l} {%9,%2|%2,%9}\n\t" \
14 "adc{l} {%7,%1|%1,%7}\n\t" \
15 "adc{l} {%5,%0|%0,%5}" \
16 : "=r" ((USItype) (r3)), \
17 "=&r" ((USItype) (r2)), \
18 "=&r" ((USItype) (r1)), \
19 "=&r" ((USItype) (r0)) \
20 : "%0" ((USItype) (x3)), \
21 "g" ((USItype) (y3)), \
22 "%1" ((USItype) (x2)), \
23 "g" ((USItype) (y2)), \
24 "%2" ((USItype) (x1)), \
25 "g" ((USItype) (y1)), \
26 "%3" ((USItype) (x0)), \
29 #define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
30 __asm__ ("add{l} {%8,%2|%2,%8}\n\t" \
31 "adc{l} {%6,%1|%1,%6}\n\t" \
32 "adc{l} {%4,%0|%0,%4}" \
33 : "=r" ((USItype) (r2)), \
34 "=&r" ((USItype) (r1)), \
35 "=&r" ((USItype) (r0)) \
36 : "%0" ((USItype) (x2)), \
37 "g" ((USItype) (y2)), \
38 "%1" ((USItype) (x1)), \
39 "g" ((USItype) (y1)), \
40 "%2" ((USItype) (x0)), \
43 /* FIXME: The last constraint should be "g" instead of "im" if reload
45 #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
46 __asm__ ("sub{l} {%11,%3|%3,%11}\n\t" \
47 "sbb{l} {%9,%2|%2,%9}\n\t" \
48 "sbb{l} {%7,%1|%1,%7}\n\t" \
49 "sbb{l} {%5,%0|%0,%5}" \
50 : "=r" ((USItype) (r3)), \
51 "=&r" ((USItype) (r2)), \
52 "=&r" ((USItype) (r1)), \
53 "=&r" ((USItype) (r0)) \
54 : "0" ((USItype) (x3)), \
55 "g" ((USItype) (y3)), \
56 "1" ((USItype) (x2)), \
57 "g" ((USItype) (y2)), \
58 "2" ((USItype) (x1)), \
59 "g" ((USItype) (y1)), \
60 "3" ((USItype) (x0)), \
61 "im" ((USItype) (y0)))
63 #define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
64 __asm__ ("sub{l} {%8,%2|%2,%8}\n\t" \
65 "sbb{l} {%6,%1|%1,%6}\n\t" \
66 "sbb{l} {%4,%0|%0,%4}" \
67 : "=r" ((USItype) (r2)), \
68 "=&r" ((USItype) (r1)), \
69 "=&r" ((USItype) (r0)) \
70 : "0" ((USItype) (x2)), \
71 "g" ((USItype) (y2)), \
72 "1" ((USItype) (x1)), \
73 "g" ((USItype) (y1)), \
74 "2" ((USItype) (x0)), \
78 #define _FP_MUL_MEAT_S(R,X,Y) \
79 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
80 #define _FP_MUL_MEAT_D(R,X,Y) \
81 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
82 #define _FP_MUL_MEAT_Q(R,X,Y) \
83 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
85 #define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
86 #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
87 #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
89 #define _FP_NANFRAC_S _FP_QNANBIT_S
90 #define _FP_NANFRAC_D _FP_QNANBIT_D, 0
91 /* Even if XFmode is 12byte, we have to pad it to 16byte since soft-fp
92 emulation is done in 16byte. */
93 #define _FP_NANFRAC_E _FP_QNANBIT_E, 0, 0, 0
94 #define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
95 #define _FP_NANSIGN_S 1
96 #define _FP_NANSIGN_D 1
97 #define _FP_NANSIGN_E 1
98 #define _FP_NANSIGN_Q 1
100 #define _FP_KEEPNANFRACP 1
102 /* Here is something Intel misdesigned: the specs don't define
103 the case where we have two NaNs with same mantissas, but
104 different sign. Different operations pick up different NaNs. */
105 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
107 if (_FP_FRAC_GT_##wc(X, Y) \
108 || (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
111 _FP_FRAC_COPY_##wc(R,X); \
116 _FP_FRAC_COPY_##wc(R,Y); \
118 R##_c = FP_CLS_NAN; \
121 #define FP_EX_INVALID 0x01
122 #define FP_EX_DENORM 0x02
123 #define FP_EX_DIVZERO 0x04
124 #define FP_EX_OVERFLOW 0x08
125 #define FP_EX_UNDERFLOW 0x10
126 #define FP_EX_INEXACT 0x20
130 unsigned short int __control_word;
131 unsigned short int __unused1;
132 unsigned short int __status_word;
133 unsigned short int __unused2;
134 unsigned short int __tags;
135 unsigned short int __unused3;
137 unsigned short int __cs_selector;
138 unsigned int __opcode:11;
139 unsigned int __unused4:5;
140 unsigned int __data_offset;
141 unsigned short int __data_selector;
142 unsigned short int __unused5;
145 #define FP_HANDLE_EXCEPTIONS \
147 if (_fex & FP_EX_INVALID) \
150 __asm__ __volatile__ ("fdiv %0" : "+t" (f)); \
151 __asm__ __volatile__ ("fwait"); \
153 if (_fex & FP_EX_DIVZERO) \
155 float f = 1.0, g = 0.0; \
156 __asm__ __volatile__ ("fdivp" : "=t" (f) \
159 __asm__ __volatile__ ("fwait"); \
161 if (_fex & FP_EX_OVERFLOW) \
164 __asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
165 temp.__status_word |= FP_EX_OVERFLOW; \
166 __asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
167 __asm__ __volatile__ ("fwait"); \
169 if (_fex & FP_EX_UNDERFLOW) \
172 __asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
173 temp.__status_word |= FP_EX_UNDERFLOW; \
174 __asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
175 __asm__ __volatile__ ("fwait"); \
177 if (_fex & FP_EX_INEXACT) \
180 __asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
181 temp.__status_word |= FP_EX_INEXACT; \
182 __asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
183 __asm__ __volatile__ ("fwait"); \
187 #define FP_RND_NEAREST 0
188 #define FP_RND_ZERO 0xc00
189 #define FP_RND_PINF 0x800
190 #define FP_RND_MINF 0x400
192 #define _FP_DECL_EX \
193 unsigned short _fcw __attribute__ ((unused)) = FP_RND_NEAREST
195 #define FP_INIT_ROUNDMODE \
197 __asm__ ("fnstcw %0" : "=m" (_fcw)); \
200 #define FP_ROUNDMODE (_fcw & 0xc00)
202 #define __LITTLE_ENDIAN 1234
203 #define __BIG_ENDIAN 4321
205 #define __BYTE_ORDER __LITTLE_ENDIAN
207 /* Define ALIASNAME as a strong alias for NAME. */
209 /* Mach-O doesn't support aliasing. If these functions ever return
210 anything but CMPtype we need to revisit this... */
211 #define strong_alias(name, aliasname) \
212 CMPtype aliasname (TFtype a, TFtype b) { return name(a, b); }
214 # define strong_alias(name, aliasname) _strong_alias(name, aliasname)
215 # define _strong_alias(name, aliasname) \
216 extern __typeof (name) aliasname __attribute__ ((alias (#name)));