1 /* Test MIPS32 DSP REV 2 instructions */
3 /* { dg-options "-mdspr2 -O2" } */
5 typedef signed char v4q7 __attribute__ ((vector_size(4)));
6 typedef signed char v4i8 __attribute__ ((vector_size(4)));
7 typedef short v2q15 __attribute__ ((vector_size(4)));
8 typedef short v2i16 __attribute__ ((vector_size(4)));
11 typedef unsigned int ui32;
12 typedef long long a64;
16 NOMIPS16 void test_MIPS_DSPR2 (void);
22 union { long long ll; int i[2]; } endianness_test;
23 endianness_test.ll = 1;
24 little_endian = endianness_test.i[0];
31 NOMIPS16 void test_MIPS_DSPR2 ()
33 v4q7 v4q7_a,v4q7_b,v4q7_c,v4q7_r,v4q7_s;
34 v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
35 v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
36 v2i16 v2i16_a,v2i16_b,v2i16_c,v2i16_r,v2i16_s;
37 q31 q31_a,q31_b,q31_c,q31_r,q31_s;
38 i32 i32_a,i32_b,i32_c,i32_r,i32_s;
39 ui32 ui32_a,ui32_b,ui32_c,ui32_r,ui32_s;
40 a64 a64_a,a64_b,a64_c,a64_r,a64_s;
44 v4q7_a = (v4i8) {0x81, 0xff, 0x80, 0x23};
45 v4q7_s = (v4i8) {0x7f, 0x01, 0x7f, 0x23};
46 v4q7_r = __builtin_mips_absq_s_qb (v4q7_a);
52 v2i16_a = (v2i16) {0xffff, 0x2468};
53 v2i16_b = (v2i16) {0x1234, 0x1111};
54 v2i16_s = (v2i16) {0x1233, 0x3579};
55 v2i16_r = __builtin_mips_addu_ph (v2i16_a, v2i16_b);
61 v2i16_a = (v2i16) {0xffff, 0x2468};
62 v2i16_b = (v2i16) {0x1234, 0x1111};
63 v2i16_s = (v2i16) {0xffff, 0x3579};
64 v2i16_r = __builtin_mips_addu_s_ph (v2i16_a, v2i16_b);
70 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
71 v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
72 v4i8_s = (v4i8) {0x11, 0x2a, 0x66, 0xff};
73 v4i8_r = __builtin_mips_adduh_qb (v4i8_a, v4i8_b);
79 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
80 v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
81 v4i8_s = (v4i8) {0x11, 0x2b, 0x66, 0xff};
82 v4i8_r = __builtin_mips_adduh_r_qb (v4i8_a, v4i8_b);
91 i32_r = __builtin_mips_append (i32_a, i32_b, 16);
98 i32_r = __builtin_mips_balign (i32_a, i32_b, 3);
102 __builtin_mips_wrdsp (0, 63);
103 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
104 v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
109 i32_r = __builtin_mips_cmpgdu_eq_qb (v4i8_a, v4i8_b);
112 i32_r = __builtin_mips_rddsp (16);
120 __builtin_mips_wrdsp (0, 63);
121 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
122 v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
127 i32_r = __builtin_mips_cmpgdu_lt_qb (v4i8_a, v4i8_b);
130 i32_r = __builtin_mips_rddsp (16);
138 __builtin_mips_wrdsp (0, 63);
139 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x54};
140 v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
145 i32_r = __builtin_mips_cmpgdu_le_qb (v4i8_a, v4i8_b);
148 i32_r = __builtin_mips_rddsp (16);
158 v2i16_b = (v2i16) {0xffff, 0x1555};
159 v2i16_c = (v2i16) {0x1234, 0x3322};
161 a64_r = __builtin_mips_dpa_w_ph (a64_a, v2i16_b, v2i16_c);
168 v2i16_b = (v2i16) {0xffff, 0x1555};
169 v2i16_c = (v2i16) {0x1234, 0x3322};
171 a64_r = __builtin_mips_dps_w_ph (a64_a, v2i16_b, v2i16_c);
180 a64_s = 0xF7776EEF12345678LL;
181 a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
190 a64_s = 0x0888911112345678LL;
191 a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
200 a64_s = 0x0888911112345678LL;
201 a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
210 a64_s = 0xF7776EEF12345678LL;
211 a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
216 v2i16_a = (v2i16) {0xffff, 0x2468};
217 v2i16_b = (v2i16) {0x1234, 0x1111};
218 v2i16_s = (v2i16) {0xedcc, 0x52e8};
219 v2i16_r = __builtin_mips_mul_ph (v2i16_a, v2i16_b);
225 v2i16_a = (v2i16) {0x8000, 0x7fff};
226 v2i16_b = (v2i16) {0x1234, 0x1111};
227 v2i16_s = (v2i16) {0x8000, 0x7fff};
228 v2i16_r = __builtin_mips_mul_s_ph (v2i16_a, v2i16_b);
237 q31_r = __builtin_mips_mulq_rs_w (q31_a, q31_b);
241 v2q15_a = (v2q15) {0xffff, 0x8000};
242 v2q15_b = (v2q15) {0x1111, 0x8000};
243 v2q15_s = (v2q15) {0xffff, 0x7fff};
244 v2q15_r = __builtin_mips_mulq_s_ph (v2q15_a, v2q15_b);
253 q31_r = __builtin_mips_mulq_s_w (q31_a, q31_b);
259 v2i16_b = (v2i16) {0xffff, 0x8000};
260 v2i16_c = (v2i16) {0x1111, 0x8000};
264 a64_s = 0xffffffffd9847308LL;
265 a64_r = __builtin_mips_mulsa_w_ph (a64_a, v2i16_b, v2i16_c);
273 a64_s = 0xF7776EEF00000000LL;
274 a64_r = __builtin_mips_mult (i32_a, i32_b);
282 a64_s = 0x888911100000000LL;
283 a64_r = __builtin_mips_multu (ui32_a, ui32_b);
288 v2i16_a = (v2i16) {0x1234, 0x5678};
289 v2i16_b = (v2i16) {0x2233, 0x5566};
291 v4i8_s = (v4i8) {0x33, 0x66, 0x34, 0x78};
293 v4i8_s = (v4i8) {0x34, 0x78, 0x33, 0x66};
294 v4i8_r = __builtin_mips_precr_qb_ph (v2i16_a, v2i16_b);
303 v2i16_s = (v2i16) {0x3444, 0x4567};
305 v2i16_s = (v2i16) {0x4567, 0x3444};
306 v2i16_r = __builtin_mips_precr_sra_ph_w (i32_a, i32_b, 4);
315 v2i16_s = (v2i16) {0x3444, 0x4568};
317 v2i16_s = (v2i16) {0x4568, 0x3444};
318 v2i16_r = __builtin_mips_precr_sra_r_ph_w (i32_a, i32_b, 4);
327 i32_r = __builtin_mips_prepend (i32_a, i32_b, 16);
331 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
332 v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
333 v4i8_r = __builtin_mips_shra_qb (v4i8_a, 1);
339 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
340 v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
341 v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, 1);
348 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
349 v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
350 v4i8_r = __builtin_mips_shra_qb (v4i8_a, i32_b);
357 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
358 v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
359 v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, i32_b);
365 v2i16_a = (v2i16) {0x1357, 0x2468};
366 v2i16_s = (v2i16) {0x0135, 0x0246};
367 v2i16_r = __builtin_mips_shrl_ph (v2i16_a, 4);
374 v2i16_a = (v2i16) {0x1357, 0x2468};
375 v2i16_s = (v2i16) {0x0013, 0x0024};
376 v2i16_r = __builtin_mips_shrl_ph (v2i16_a, i32_b);
382 v2i16_a = (v2i16) {0x1357, 0x4455};
383 v2i16_b = (v2i16) {0x3333, 0x4444};
384 v2i16_s = (v2i16) {0xe024, 0x0011};
385 v2i16_r = __builtin_mips_subu_ph (v2i16_a, v2i16_b);
391 v2i16_a = (v2i16) {0x1357, 0x4455};
392 v2i16_b = (v2i16) {0x3333, 0x4444};
393 v2i16_s = (v2i16) {0x0000, 0x0011};
394 v2i16_r = __builtin_mips_subu_s_ph (v2i16_a, v2i16_b);
400 v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
401 v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
402 v4i8_s = (v4i8) {0xcd ,0x17, 0xe8, 0xb3};
403 v4i8_r = __builtin_mips_subuh_qb (v4i8_a, v4i8_b);
409 v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
410 v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
411 v4i8_s = (v4i8) {0xcd ,0x18, 0xe8, 0xb4};
412 v4i8_r = __builtin_mips_subuh_r_qb (v4i8_a, v4i8_b);
418 v2q15_a = (v2q15) {0x3334, 0x4444};
419 v2q15_b = (v2q15) {0x1111, 0x2222};
420 v2q15_s = (v2q15) {0x2222, 0x3333};
421 v2q15_r = __builtin_mips_addqh_ph (v2q15_a, v2q15_b);
427 v2q15_a = (v2q15) {0x3334, 0x4444};
428 v2q15_b = (v2q15) {0x1111, 0x2222};
429 v2q15_s = (v2q15) {0x2223, 0x3333};
430 v2q15_r = __builtin_mips_addqh_r_ph (v2q15_a, v2q15_b);
439 q31_r = __builtin_mips_addqh_w (q31_a, q31_b);
446 q31_r = __builtin_mips_addqh_r_w (q31_a, q31_b);
450 v2q15_a = (v2q15) {0x3334, 0x4444};
451 v2q15_b = (v2q15) {0x1111, 0x2222};
452 v2q15_s = (v2q15) {0x1111, 0x1111};
453 v2q15_r = __builtin_mips_subqh_ph (v2q15_a, v2q15_b);
459 v2q15_a = (v2q15) {0x3334, 0x4444};
460 v2q15_b = (v2q15) {0x1111, 0x2222};
461 v2q15_s = (v2q15) {0x1112, 0x1111};
462 v2q15_r = __builtin_mips_subqh_r_ph (v2q15_a, v2q15_b);
471 q31_r = __builtin_mips_subqh_w (q31_a, q31_b);
478 q31_r = __builtin_mips_subqh_r_w (q31_a, q31_b);
483 a64_a = 0x1111222212345678LL;
484 v2i16_b = (v2i16) {0x1, 0x2};
485 v2i16_c = (v2i16) {0x3, 0x4};
486 a64_s = 0x1111222212345682LL;
487 a64_r = __builtin_mips_dpax_w_ph (a64_a, v2i16_b, v2i16_c);
493 a64_a = 0x9999111112345678LL;
494 v2i16_b = (v2i16) {0x1, 0x2};
495 v2i16_c = (v2i16) {0x3, 0x4};
496 a64_s = 0x999911111234566eLL;
497 a64_r = __builtin_mips_dpsx_w_ph (a64_a, v2i16_b, v2i16_c);
504 v2q15_b = (v2q15) {0x4000, 0x2000};
505 v2q15_c = (v2q15) {0x2000, 0x4000};
507 a64_r = __builtin_mips_dpaqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
514 v2q15_b = (v2q15) {0x4000, 0x2000};
515 v2q15_c = (v2q15) {0x2000, 0x4000};
517 a64_r = __builtin_mips_dpaqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);
524 v2q15_b = (v2q15) {0x4000, 0x2000};
525 v2q15_c = (v2q15) {0x2000, 0x4000};
527 a64_r = __builtin_mips_dpsqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
533 a64_a = 0xFFFFFFFF80000000LL;
534 v2q15_b = (v2q15) {0x4000, 0x2000};
535 v2q15_c = (v2q15) {0x2000, 0x4000};
536 a64_s = 0xFFFFFFFF80000000LL;
537 a64_r = __builtin_mips_dpsqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);