1 /* Test MIPS32 DSP instructions */
2 /* { dg-do compile } */
3 /* { dg-options "-mgp32 -mdsp" } */
4 /* { dg-final { scan-assembler "addq.ph" } } */
5 /* { dg-final { scan-assembler "addq_s.ph" } } */
6 /* { dg-final { scan-assembler "addq_s.w" } } */
7 /* { dg-final { scan-assembler "addu.qb" } } */
8 /* { dg-final { scan-assembler "addu_s.qb" } } */
9 /* { dg-final { scan-assembler "subq.ph" } } */
10 /* { dg-final { scan-assembler "subq_s.ph" } } */
11 /* { dg-final { scan-assembler "subq_s.w" } } */
12 /* { dg-final { scan-assembler "subu.qb" } } */
13 /* { dg-final { scan-assembler "subu_s.qb" } } */
14 /* { dg-final { scan-assembler "addsc" } } */
15 /* { dg-final { scan-assembler "addwc" } } */
16 /* { dg-final { scan-assembler "modsub" } } */
17 /* { dg-final { scan-assembler "raddu.w.qb" } } */
18 /* { dg-final { scan-assembler "absq_s.ph" } } */
19 /* { dg-final { scan-assembler "absq_s.w" } } */
20 /* { dg-final { scan-assembler "precrq.qb.ph" } } */
21 /* { dg-final { scan-assembler "precrq.ph.w" } } */
22 /* { dg-final { scan-assembler "precrq_rs.ph.w" } } */
23 /* { dg-final { scan-assembler "precrqu_s.qb.ph" } } */
24 /* { dg-final { scan-assembler "preceq.w.phl" } } */
25 /* { dg-final { scan-assembler "preceq.w.phr" } } */
26 /* { dg-final { scan-assembler "precequ.ph.qbl" } } */
27 /* { dg-final { scan-assembler "precequ.ph.qbr" } } */
28 /* { dg-final { scan-assembler "precequ.ph.qbla" } } */
29 /* { dg-final { scan-assembler "precequ.ph.qbra" } } */
30 /* { dg-final { scan-assembler "preceu.ph.qbl" } } */
31 /* { dg-final { scan-assembler "preceu.ph.qbr" } } */
32 /* { dg-final { scan-assembler "preceu.ph.qbla" } } */
33 /* { dg-final { scan-assembler "preceu.ph.qbra" } } */
34 /* { dg-final { scan-assembler "shllv?.qb" } } */
35 /* { dg-final { scan-assembler "shllv?.ph" } } */
36 /* { dg-final { scan-assembler "shllv?_s.ph" } } */
37 /* { dg-final { scan-assembler "shllv?_s.w" } } */
38 /* { dg-final { scan-assembler "shrlv?.qb" } } */
39 /* { dg-final { scan-assembler "shrav?.ph" } } */
40 /* { dg-final { scan-assembler "shrav?_r.ph" } } */
41 /* { dg-final { scan-assembler "shrav?_r.w" } } */
42 /* { dg-final { scan-assembler "muleu_s.ph.qbl" } } */
43 /* { dg-final { scan-assembler "muleu_s.ph.qbr" } } */
44 /* { dg-final { scan-assembler "mulq_rs.ph" } } */
45 /* { dg-final { scan-assembler "muleq_s.w.phl" } } */
46 /* { dg-final { scan-assembler "muleq_s.w.phr" } } */
47 /* { dg-final { scan-assembler "dpau.h.qbl" } } */
48 /* { dg-final { scan-assembler "dpau.h.qbr" } } */
49 /* { dg-final { scan-assembler "dpsu.h.qbl" } } */
50 /* { dg-final { scan-assembler "dpsu.h.qbr" } } */
51 /* { dg-final { scan-assembler "dpaq_s.w.ph" } } */
52 /* { dg-final { scan-assembler "dpsq_s.w.ph" } } */
53 /* { dg-final { scan-assembler "mulsaq_s.w.ph" } } */
54 /* { dg-final { scan-assembler "dpaq_sa.l.w" } } */
55 /* { dg-final { scan-assembler "dpsq_sa.l.w" } } */
56 /* { dg-final { scan-assembler "maq_s.w.phl" } } */
57 /* { dg-final { scan-assembler "maq_s.w.phr" } } */
58 /* { dg-final { scan-assembler "maq_sa.w.phl" } } */
59 /* { dg-final { scan-assembler "maq_sa.w.phr" } } */
60 /* { dg-final { scan-assembler "bitrev" } } */
61 /* { dg-final { scan-assembler "insv" } } */
62 /* { dg-final { scan-assembler "replv?.qb" } } */
63 /* { dg-final { scan-assembler "repl.ph" } } */
64 /* { dg-final { scan-assembler "replv.ph" } } */
65 /* { dg-final { scan-assembler "cmpu.eq.qb" } } */
66 /* { dg-final { scan-assembler "cmpu.lt.qb" } } */
67 /* { dg-final { scan-assembler "cmpu.le.qb" } } */
68 /* { dg-final { scan-assembler "cmpgu.eq.qb" } } */
69 /* { dg-final { scan-assembler "cmpgu.lt.qb" } } */
70 /* { dg-final { scan-assembler "cmpgu.le.qb" } } */
71 /* { dg-final { scan-assembler "cmp.eq.ph" } } */
72 /* { dg-final { scan-assembler "cmp.lt.ph" } } */
73 /* { dg-final { scan-assembler "cmp.le.ph" } } */
74 /* { dg-final { scan-assembler "pick.qb" } } */
75 /* { dg-final { scan-assembler "pick.ph" } } */
76 /* { dg-final { scan-assembler "packrl.ph" } } */
77 /* { dg-final { scan-assembler "extrv?.w" } } */
78 /* { dg-final { scan-assembler "extrv?_s.h" } } */
79 /* { dg-final { scan-assembler "extrv?_r.w" } } */
80 /* { dg-final { scan-assembler "extrv?_rs.w" } } */
81 /* { dg-final { scan-assembler "extpv?" } } */
82 /* { dg-final { scan-assembler "extpdpv?" } } */
83 /* { dg-final { scan-assembler "shilov?" } } */
84 /* { dg-final { scan-assembler "mthlip" } } */
85 /* { dg-final { scan-assembler "mfhi" } } */
86 /* { dg-final { scan-assembler "mflo" } } */
87 /* { dg-final { scan-assembler "mthi" } } */
88 /* { dg-final { scan-assembler "mtlo" } } */
89 /* { dg-final { scan-assembler "wrdsp" } } */
90 /* { dg-final { scan-assembler "rddsp" } } */
91 /* { dg-final { scan-assembler "lbux?" } } */
92 /* { dg-final { scan-assembler "lhx?" } } */
93 /* { dg-final { scan-assembler "lwx?" } } */
94 /* { dg-final { scan-assembler "bposge32" } } */
95 /* { dg-final { scan-assembler "madd" } } */
96 /* { dg-final { scan-assembler "maddu" } } */
97 /* { dg-final { scan-assembler "msub" } } */
98 /* { dg-final { scan-assembler "msubu" } } */
99 /* { dg-final { scan-assembler "mult" } } */
100 /* { dg-final { scan-assembler "multu" } } */
105 typedef signed char v4i8 __attribute__ ((vector_size(4)));
106 typedef short v2q15 __attribute__ ((vector_size(4)));
110 typedef unsigned int ui32;
111 typedef long long a64;
113 NOMIPS16 void test_MIPS_DSP (void);
122 union { long long ll; int i[2]; } endianness_test;
123 endianness_test.ll = 1;
124 little_endian = endianness_test.i[0];
126 for (i = 0; i < 100; i++)
134 NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
136 return __builtin_mips_addq_ph (a, b);
139 NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
141 return __builtin_mips_addu_qb (a, b);
144 NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
146 return __builtin_mips_subq_ph (a, b);
149 NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
151 return __builtin_mips_subu_qb (a, b);
154 NOMIPS16 void test_MIPS_DSP ()
156 v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
157 v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
158 q31 q31_a,q31_b,q31_c,q31_r,q31_s;
159 i32 i32_a,i32_b,i32_c,i32_r,i32_s;
160 ui32 ui32_a,ui32_b,ui32_c;
161 a64 a64_a,a64_b,a64_c,a64_r,a64_s;
167 v2q15_a = (v2q15) {0x1234, 0x5678};
168 v2q15_b = (v2q15) {0x6f89, 0x1111};
169 v2q15_s = (v2q15) {0x81bd, 0x6789};
170 v2q15_r = add_v2q15 (v2q15_a, v2q15_b);
176 v2q15_a = (v2q15) {0x1234, 0x5678};
177 v2q15_b = (v2q15) {0x6f89, 0x1111};
178 v2q15_s = (v2q15) {0x7fff, 0x6789};
179 v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b);
188 q31_r = __builtin_mips_addq_s_w (q31_a, q31_b);
192 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
193 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
194 v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89};
195 v4i8_r = add_v4i8 (v4i8_a, v4i8_b);
201 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
202 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
203 v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89};
204 v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b);
210 v2q15_a = (v2q15) {0x1234, 0x5678};
211 v2q15_b = (v2q15) {0x6f89, 0x1111};
212 v2q15_s = (v2q15) {0xa2ab, 0x4567};
213 v2q15_r = sub_v2q15 (v2q15_a, v2q15_b);
219 v2q15_a = (v2q15) {0x8000, 0x5678};
220 v2q15_b = (v2q15) {0x6f89, 0x1111};
221 v2q15_s = (v2q15) {0x8000, 0x4567};
222 v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b);
231 q31_r = __builtin_mips_subq_s_w (q31_a, q31_b);
235 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
236 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
237 v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67};
238 v4i8_r = sub_v4i8 (v4i8_a, v4i8_b);
244 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
245 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
246 v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67};
247 v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b);
256 i32_r = __builtin_mips_addsc (i32_a, i32_b);
263 i32_r = __builtin_mips_addwc (i32_a, i32_b);
270 i32_r = __builtin_mips_modsub (i32_a, i32_b);
274 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
276 i32_r = __builtin_mips_raddu_w_qb (v4i8_a);
280 v2q15_a = (v2q15) {0x8000, 0x8134};
281 v2q15_s = (v2q15) {0x7fff, 0x7ecc};
282 v2q15_r = __builtin_mips_absq_s_ph (v2q15_a);
288 q31_a = (q31) 0x80000000;
289 q31_s = (q31) 0x7fffffff;
290 q31_r = __builtin_mips_absq_s_w (q31_a);
294 v2q15_a = (v2q15) {0x9999, 0x5612};
295 v2q15_b = (v2q15) {0x5612, 0x3333};
297 v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56};
299 v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33};
300 v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b);
309 v2q15_s = (v2q15) {0x4444, 0x1234};
311 v2q15_s = (v2q15) {0x1234, 0x4444};
312 v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b);
321 v2q15_s = (v2q15) {0x4444, 0x1235};
323 v2q15_s = (v2q15) {0x1235, 0x4444};
324 v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b);
330 v2q15_a = (v2q15) {0x9999, 0x5612};
331 v2q15_b = (v2q15) {0x5612, 0x3333};
333 v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac};
335 v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66};
336 v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b);
342 v2q15_a = (v2q15) {0x3589, 0x4444};
347 q31_r = __builtin_mips_preceq_w_phl (v2q15_a);
351 v2q15_a = (v2q15) {0x3589, 0x4444};
356 q31_r = __builtin_mips_preceq_w_phr (v2q15_a);
360 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
362 v2q15_s = (v2q15) {0x2b00, 0x1980};
364 v2q15_s = (v2q15) {0x0900, 0x2b00};
365 v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a);
371 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
373 v2q15_s = (v2q15) {0x0900, 0x2b00};
375 v2q15_s = (v2q15) {0x2b00, 0x1980};
376 v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a);
382 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
384 v2q15_s = (v2q15) {0x2b00, 0x1980};
386 v2q15_s = (v2q15) {0x0900, 0x2b00};
387 v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a);
393 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
395 v2q15_s = (v2q15) {0x0900, 0x2b00};
397 v2q15_s = (v2q15) {0x2b00, 0x1980};
398 v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a);
404 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
406 v2q15_s = (v2q15) {0x56, 0x33};
408 v2q15_s = (v2q15) {0x12, 0x56};
409 v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a);
415 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
417 v2q15_s = (v2q15) {0x12, 0x56};
419 v2q15_s = (v2q15) {0x56, 0x33};
420 v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a);
426 v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
428 v2q15_s = (v2q15) {0x99, 0x33};
430 v2q15_s = (v2q15) {0x12, 0x56};
431 v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a);
437 v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
439 v2q15_s = (v2q15) {0x12, 0x56};
441 v2q15_s = (v2q15) {0x99, 0x33};
442 v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a);
448 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
449 v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0};
450 v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2);
456 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
458 v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0};
459 v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b);
465 v2q15_a = (v2q15) {0x1234, 0x5678};
466 v2q15_s = (v2q15) {0x48d0, 0x59e0};
467 v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2);
473 v2q15_a = (v2q15) {0x1234, 0x5678};
475 v2q15_s = (v2q15) {0x2468, 0xacf0};
476 v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b);
482 v2q15_a = (v2q15) {0x1234, 0x5678};
483 v2q15_s = (v2q15) {0x48d0, 0x7fff};
484 v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2);
490 v2q15_a = (v2q15) {0x1234, 0x5678};
492 v2q15_s = (v2q15) {0x2468, 0x7fff};
493 v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
501 q31_r = __builtin_mips_shll_s_w (q31_a, 2);
508 q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
512 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
513 v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e};
514 v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2);
520 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
522 v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c};
523 v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b);
529 v2q15_a = (v2q15) {0x1234, 0x5678};
530 v2q15_s = (v2q15) {0x48d, 0x159e};
531 v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2);
537 v2q15_a = (v2q15) {0x1234, 0x5678};
539 v2q15_s = (v2q15) {0x91a, 0x2b3c};
540 v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b);
546 v2q15_a = (v2q15) {0x1234, 0x5678};
547 v2q15_s = (v2q15) {0x48d, 0x159e};
548 v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2);
554 v2q15_a = (v2q15) {0x1234, 0x5678};
556 v2q15_s = (v2q15) {0x247, 0xacf};
557 v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b);
565 q31_r = __builtin_mips_shra_r_w (q31_a, 2);
572 q31_r = __builtin_mips_shra_r_w (q31_a, i32_b);
576 v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
577 v2q15_b = (v2q15) {0x6f89, 0x1111};
579 v2q15_s = (v2q15) {0xffff, 0x4444};
581 v2q15_s = (v2q15) {0x6f89, 0x2222};
582 v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b);
588 v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
589 v2q15_b = (v2q15) {0x6f89, 0x1111};
591 v2q15_s = (v2q15) {0x6f89, 0x2222};
593 v2q15_s = (v2q15) {0xffff, 0x4444};
594 v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b);
600 v2q15_a = (v2q15) {0x1234, 0x5678};
601 v2q15_b = (v2q15) {0x6f89, 0x1111};
602 v2q15_s = (v2q15) {0x0fdd, 0x0b87};
603 v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b);
609 v2q15_a = (v2q15) {0x8000, 0x8000};
610 v2q15_b = (v2q15) {0x8000, 0x8000};
612 q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b);
616 v2q15_a = (v2q15) {0x8000, 0x8000};
617 v2q15_b = (v2q15) {0x8000, 0x8000};
619 q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b);
625 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
626 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
631 a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c);
636 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
637 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
642 a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c);
647 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
648 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
653 a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c);
658 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
659 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
664 a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c);
669 v2q15_b = (v2q15) {0x8000, 0x5678};
670 v2q15_c = (v2q15) {0x8000, 0x1111};
672 a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
677 v2q15_b = (v2q15) {0x8000, 0x5678};
678 v2q15_c = (v2q15) {0x8000, 0x1111};
679 a64_s = 0xffffffff7478a522LL;
680 a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c);
685 v2q15_b = (v2q15) {0x8000, 0x5678};
686 v2q15_c = (v2q15) {0x8000, 0x1111};
688 a64_s = 0xffffffff8b877d02LL;
691 a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
698 a64_s = 0x7fffffffffffffffLL;
699 a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c);
706 a64_s = 0x8000000000001112LL;
707 a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c);
712 v2q15_b = (v2q15) {0x8000, 0x1};
713 v2q15_c = (v2q15) {0x8000, 0x2};
718 a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c);
723 v2q15_b = (v2q15) {0x8000, 0x1};
724 v2q15_c = (v2q15) {0x8000, 0x2};
729 a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c);
734 v2q15_b = (v2q15) {0x8000, 0x1};
735 v2q15_c = (v2q15) {0x8000, 0x2};
740 a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c);
745 v2q15_b = (v2q15) {0x8000, 0x1};
746 v2q15_c = (v2q15) {0x8000, 0x2};
751 a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c);
758 i32_r = __builtin_mips_bitrev (i32_a);
762 i32_a = 0x00000208; // pos is 8, size is 4
763 __builtin_mips_wrdsp (i32_a, 31);
767 i32_r = __builtin_mips_insv (i32_a, i32_b);
771 v4i8_s = (v4i8) {1, 1, 1, 1};
772 v4i8_r = __builtin_mips_repl_qb (1);
779 v4i8_s = (v4i8) {99, 99, 99, 99};
780 v4i8_r = __builtin_mips_repl_qb (i32_a);
786 v2q15_s = (v2q15) {30, 30};
787 v2q15_r = __builtin_mips_repl_ph (30);
794 v2q15_s = (v2q15) {0x5612, 0x5612};
795 v2q15_r = __builtin_mips_repl_ph (i32_a);
801 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
802 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
807 __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b);
808 i32_r = __builtin_mips_rddsp (16);
812 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
813 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
818 __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b);
819 i32_r = __builtin_mips_rddsp (16);
823 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
824 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
829 __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b);
830 i32_r = __builtin_mips_rddsp (16);
834 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
835 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
840 i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b);
844 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
845 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
850 i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b);
854 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
855 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
860 i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b);
864 __builtin_mips_wrdsp (0,31); // Clear all condition code bits.
865 v2q15_a = (v2q15) {0x1234, 0x5678};
866 v2q15_b = (v2q15) {0x1234, 0x7856};
871 __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b);
872 i32_r = __builtin_mips_rddsp (16);
876 v2q15_a = (v2q15) {0x1234, 0x5678};
877 v2q15_b = (v2q15) {0x1234, 0x7856};
882 __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b);
883 i32_r = __builtin_mips_rddsp (16);
887 v2q15_a = (v2q15) {0x1234, 0x5678};
888 v2q15_b = (v2q15) {0x1234, 0x7856};
890 __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b);
891 i32_r = __builtin_mips_rddsp (16);
895 i32_a = 0x0a000000; // cc: 0000 1010
896 __builtin_mips_wrdsp (i32_a, 31);
897 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
898 v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87};
900 v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78};
902 v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87};
903 v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b);
909 i32_a = 0x02000000; // cc: 0000 0010
910 __builtin_mips_wrdsp (i32_a, 31);
911 v2q15_a = (v2q15) {0x1234, 0x5678};
912 v2q15_b = (v2q15) {0x2143, 0x6587};
914 v2q15_s = (v2q15) {0x2143, 0x5678};
916 v2q15_s = (v2q15) {0x1234, 0x6587};
917 v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b);
923 v2q15_a = (v2q15) {0x1234, 0x5678};
924 v2q15_b = (v2q15) {0x1234, 0x7856};
926 v2q15_s = (v2q15) {0x7856, 0x1234};
928 v2q15_s = (v2q15) {0x5678, 0x1234};
929 v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b);
936 a64_a = 0x1234567887654321LL;
938 i32_r = __builtin_mips_extr_w (a64_a, 4);
942 a64_a = 0x1234567887658321LL;
944 i32_r = __builtin_mips_extr_r_w (a64_a, 16);
948 a64_a = 0x12345677fffffff8LL;
950 i32_r = __builtin_mips_extr_rs_w (a64_a, 4);
954 a64_a = 0x1234567887658321LL;
956 i32_r = __builtin_mips_extr_s_h (a64_a, 16);
960 a64_a = 0x0000007887658321LL;
963 i32_r = __builtin_mips_extr_s_h (a64_a, i32_b);
967 a64_a = 0x1234567887654321LL;
970 i32_r = __builtin_mips_extr_w (a64_a, i32_b);
974 a64_a = 0x1234567887658321LL;
977 i32_r = __builtin_mips_extr_r_w (a64_a, i32_b);
981 a64_a = 0x12345677fffffff8LL;
984 i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b);
988 i32_a = 0x0000021f; // pos is 31
989 __builtin_mips_wrdsp (i32_a, 31);
990 a64_a = 0x1234567887654321LL;
992 i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits
996 i32_a = 0x0000021f; // pos is 31
997 __builtin_mips_wrdsp (i32_a, 31);
998 a64_a = 0x1234567887654321LL;
999 i32_b = 7; // size is 8. NOTE!! we should use 7
1001 i32_r = __builtin_mips_extp (a64_a, i32_b);
1005 i32_a = 0x0000021f; // pos is 31
1006 __builtin_mips_wrdsp (i32_a, 31);
1007 a64_a = 0x1234567887654321LL;
1009 i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits
1013 i32_s = 0x0000021b; // pos is 27
1014 i32_r = __builtin_mips_rddsp (31);
1018 i32_a = 0x0000021f; // pos is 31
1019 __builtin_mips_wrdsp (i32_a, 31);
1020 a64_a = 0x1234567887654321LL;
1021 i32_b = 11; // size is 12. NOTE!!! We should use 11
1023 i32_r = __builtin_mips_extpdp (a64_a, i32_b);
1027 i32_s = 0x00000213; // pos is 19
1028 i32_r = __builtin_mips_rddsp (31);
1032 a64_a = 0x1234567887654321LL;
1033 a64_s = 0x0012345678876543LL;
1034 a64_r = __builtin_mips_shilo (a64_a, 8);
1038 a64_a = 0x1234567887654321LL;
1040 a64_s = 0x5678876543210000LL;
1041 a64_r = __builtin_mips_shilo (a64_a, i32_b);
1046 __builtin_mips_wrdsp (i32_a, 31);
1047 a64_a = 0x1234567887654321LL;
1049 a64_s = 0x8765432111112222LL;
1050 a64_r = __builtin_mips_mthlip (a64_a, i32_b);
1054 i32_r = __builtin_mips_rddsp (31);
1060 __builtin_mips_wrdsp (i32_a, 63);
1062 i32_r = __builtin_mips_rddsp (63);
1069 i32_r = __builtin_mips_lbux (ptr_a, i32_b);
1079 i32_r = __builtin_mips_lhx (ptr_a, i32_b);
1089 i32_r = __builtin_mips_lwx (ptr_a, i32_b);
1093 i32_a = 0x00000220; // pos is 32, size is 4
1094 __builtin_mips_wrdsp (i32_a, 63);
1096 i32_r = __builtin_mips_bposge32 ();
1104 a64_s = 0xF7776EEF12345678LL;
1105 a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
1112 ui32_b = 0x80000000;
1113 ui32_c = 0x11112222;
1114 a64_s = 0x0888911112345678LL;
1115 a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
1124 a64_s = 0x0888911112345678LL;
1125 a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
1132 ui32_b = 0x80000000;
1133 ui32_c = 0x11112222;
1134 a64_s = 0xF7776EEF12345678LL;
1135 a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
1143 a64_s = 0xF7776EEF00000000LL;
1144 a64_r = __builtin_mips_mult (i32_a, i32_b);
1150 ui32_a = 0x80000000;
1151 ui32_b = 0x11112222;
1152 a64_s = 0x888911100000000LL;
1153 a64_r = __builtin_mips_multu (ui32_a, ui32_b);