1 /* Test MIPS32 DSP instructions */
3 /* { dg-options "-mdsp -O2" } */
8 typedef signed char v4i8 __attribute__ ((vector_size(4)));
9 typedef short v2q15 __attribute__ ((vector_size(4)));
13 typedef unsigned int ui32;
14 typedef long long a64;
16 NOMIPS16 void test_MIPS_DSP (void);
25 union { long long ll; int i[2]; } endianness_test;
26 endianness_test.ll = 1;
27 little_endian = endianness_test.i[0];
29 for (i = 0; i < 100; i++)
37 NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
39 return __builtin_mips_addq_ph (a, b);
42 NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
44 return __builtin_mips_addu_qb (a, b);
47 NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
49 return __builtin_mips_subq_ph (a, b);
52 NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
54 return __builtin_mips_subu_qb (a, b);
57 NOMIPS16 void test_MIPS_DSP ()
59 v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
60 v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
61 q31 q31_a,q31_b,q31_c,q31_r,q31_s;
62 i32 i32_a,i32_b,i32_c,i32_r,i32_s;
63 ui32 ui32_a,ui32_b,ui32_c;
64 a64 a64_a,a64_b,a64_c,a64_r,a64_s;
70 v2q15_a = (v2q15) {0x1234, 0x5678};
71 v2q15_b = (v2q15) {0x6f89, 0x1111};
72 v2q15_s = (v2q15) {0x81bd, 0x6789};
73 v2q15_r = add_v2q15 (v2q15_a, v2q15_b);
79 v2q15_a = (v2q15) {0x1234, 0x5678};
80 v2q15_b = (v2q15) {0x6f89, 0x1111};
81 v2q15_s = (v2q15) {0x7fff, 0x6789};
82 v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b);
91 q31_r = __builtin_mips_addq_s_w (q31_a, q31_b);
95 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
96 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
97 v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89};
98 v4i8_r = add_v4i8 (v4i8_a, v4i8_b);
104 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
105 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
106 v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89};
107 v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b);
113 v2q15_a = (v2q15) {0x1234, 0x5678};
114 v2q15_b = (v2q15) {0x6f89, 0x1111};
115 v2q15_s = (v2q15) {0xa2ab, 0x4567};
116 v2q15_r = sub_v2q15 (v2q15_a, v2q15_b);
122 v2q15_a = (v2q15) {0x8000, 0x5678};
123 v2q15_b = (v2q15) {0x6f89, 0x1111};
124 v2q15_s = (v2q15) {0x8000, 0x4567};
125 v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b);
134 q31_r = __builtin_mips_subq_s_w (q31_a, q31_b);
138 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
139 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
140 v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67};
141 v4i8_r = sub_v4i8 (v4i8_a, v4i8_b);
147 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
148 v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
149 v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67};
150 v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b);
159 i32_r = __builtin_mips_addsc (i32_a, i32_b);
166 i32_r = __builtin_mips_addwc (i32_a, i32_b);
173 i32_r = __builtin_mips_modsub (i32_a, i32_b);
177 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
179 i32_r = __builtin_mips_raddu_w_qb (v4i8_a);
183 v2q15_a = (v2q15) {0x8000, 0x8134};
184 v2q15_s = (v2q15) {0x7fff, 0x7ecc};
185 v2q15_r = __builtin_mips_absq_s_ph (v2q15_a);
191 q31_a = (q31) 0x80000000;
192 q31_s = (q31) 0x7fffffff;
193 q31_r = __builtin_mips_absq_s_w (q31_a);
197 v2q15_a = (v2q15) {0x9999, 0x5612};
198 v2q15_b = (v2q15) {0x5612, 0x3333};
200 v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56};
202 v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33};
203 v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b);
212 v2q15_s = (v2q15) {0x4444, 0x1234};
214 v2q15_s = (v2q15) {0x1234, 0x4444};
215 v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b);
224 v2q15_s = (v2q15) {0x4444, 0x1235};
226 v2q15_s = (v2q15) {0x1235, 0x4444};
227 v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b);
233 v2q15_a = (v2q15) {0x9999, 0x5612};
234 v2q15_b = (v2q15) {0x5612, 0x3333};
236 v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac};
238 v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66};
239 v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b);
245 v2q15_a = (v2q15) {0x3589, 0x4444};
250 q31_r = __builtin_mips_preceq_w_phl (v2q15_a);
254 v2q15_a = (v2q15) {0x3589, 0x4444};
259 q31_r = __builtin_mips_preceq_w_phr (v2q15_a);
263 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
265 v2q15_s = (v2q15) {0x2b00, 0x1980};
267 v2q15_s = (v2q15) {0x0900, 0x2b00};
268 v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a);
274 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
276 v2q15_s = (v2q15) {0x0900, 0x2b00};
278 v2q15_s = (v2q15) {0x2b00, 0x1980};
279 v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a);
285 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
287 v2q15_s = (v2q15) {0x2b00, 0x1980};
289 v2q15_s = (v2q15) {0x0900, 0x2b00};
290 v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a);
296 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
298 v2q15_s = (v2q15) {0x0900, 0x2b00};
300 v2q15_s = (v2q15) {0x2b00, 0x1980};
301 v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a);
307 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
309 v2q15_s = (v2q15) {0x56, 0x33};
311 v2q15_s = (v2q15) {0x12, 0x56};
312 v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a);
318 v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
320 v2q15_s = (v2q15) {0x12, 0x56};
322 v2q15_s = (v2q15) {0x56, 0x33};
323 v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a);
329 v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
331 v2q15_s = (v2q15) {0x99, 0x33};
333 v2q15_s = (v2q15) {0x12, 0x56};
334 v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a);
340 v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
342 v2q15_s = (v2q15) {0x12, 0x56};
344 v2q15_s = (v2q15) {0x99, 0x33};
345 v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a);
351 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
352 v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0};
353 v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2);
359 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
361 v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0};
362 v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b);
368 v2q15_a = (v2q15) {0x1234, 0x5678};
369 v2q15_s = (v2q15) {0x48d0, 0x59e0};
370 v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2);
376 v2q15_a = (v2q15) {0x1234, 0x5678};
378 v2q15_s = (v2q15) {0x2468, 0xacf0};
379 v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b);
385 v2q15_a = (v2q15) {0x1234, 0x5678};
386 v2q15_s = (v2q15) {0x48d0, 0x7fff};
387 v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2);
393 v2q15_a = (v2q15) {0x1234, 0x5678};
395 v2q15_s = (v2q15) {0x2468, 0x7fff};
396 v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
404 q31_r = __builtin_mips_shll_s_w (q31_a, 2);
411 q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
415 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
416 v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e};
417 v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2);
423 v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
425 v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c};
426 v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b);
432 v2q15_a = (v2q15) {0x1234, 0x5678};
433 v2q15_s = (v2q15) {0x48d, 0x159e};
434 v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2);
440 v2q15_a = (v2q15) {0x1234, 0x5678};
442 v2q15_s = (v2q15) {0x91a, 0x2b3c};
443 v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b);
449 v2q15_a = (v2q15) {0x1234, 0x5678};
450 v2q15_s = (v2q15) {0x48d, 0x159e};
451 v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2);
457 v2q15_a = (v2q15) {0x1234, 0x5678};
459 v2q15_s = (v2q15) {0x247, 0xacf};
460 v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b);
468 q31_r = __builtin_mips_shra_r_w (q31_a, 2);
475 q31_r = __builtin_mips_shra_r_w (q31_a, i32_b);
479 v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
480 v2q15_b = (v2q15) {0x6f89, 0x1111};
482 v2q15_s = (v2q15) {0xffff, 0x4444};
484 v2q15_s = (v2q15) {0x6f89, 0x2222};
485 v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b);
491 v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
492 v2q15_b = (v2q15) {0x6f89, 0x1111};
494 v2q15_s = (v2q15) {0x6f89, 0x2222};
496 v2q15_s = (v2q15) {0xffff, 0x4444};
497 v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b);
503 v2q15_a = (v2q15) {0x1234, 0x5678};
504 v2q15_b = (v2q15) {0x6f89, 0x1111};
505 v2q15_s = (v2q15) {0x0fdd, 0x0b87};
506 v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b);
512 v2q15_a = (v2q15) {0x8000, 0x8000};
513 v2q15_b = (v2q15) {0x8000, 0x8000};
515 q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b);
519 v2q15_a = (v2q15) {0x8000, 0x8000};
520 v2q15_b = (v2q15) {0x8000, 0x8000};
522 q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b);
528 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
529 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
534 a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c);
539 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
540 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
545 a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c);
550 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
551 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
556 a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c);
561 v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
562 v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
567 a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c);
572 v2q15_b = (v2q15) {0x8000, 0x5678};
573 v2q15_c = (v2q15) {0x8000, 0x1111};
575 a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
580 v2q15_b = (v2q15) {0x8000, 0x5678};
581 v2q15_c = (v2q15) {0x8000, 0x1111};
582 a64_s = 0xffffffff7478a522LL;
583 a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c);
588 v2q15_b = (v2q15) {0x8000, 0x5678};
589 v2q15_c = (v2q15) {0x8000, 0x1111};
591 a64_s = 0xffffffff8b877d02LL;
594 a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
601 a64_s = 0x7fffffffffffffffLL;
602 a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c);
609 a64_s = 0x8000000000001112LL;
610 a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c);
615 v2q15_b = (v2q15) {0x8000, 0x1};
616 v2q15_c = (v2q15) {0x8000, 0x2};
621 a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c);
626 v2q15_b = (v2q15) {0x8000, 0x1};
627 v2q15_c = (v2q15) {0x8000, 0x2};
632 a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c);
637 v2q15_b = (v2q15) {0x8000, 0x1};
638 v2q15_c = (v2q15) {0x8000, 0x2};
643 a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c);
648 v2q15_b = (v2q15) {0x8000, 0x1};
649 v2q15_c = (v2q15) {0x8000, 0x2};
654 a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c);
661 i32_r = __builtin_mips_bitrev (i32_a);
665 i32_a = 0x00000208; // pos is 8, size is 4
666 __builtin_mips_wrdsp (i32_a, 31);
670 i32_r = __builtin_mips_insv (i32_a, i32_b);
674 v4i8_s = (v4i8) {1, 1, 1, 1};
675 v4i8_r = __builtin_mips_repl_qb (1);
682 v4i8_s = (v4i8) {99, 99, 99, 99};
683 v4i8_r = __builtin_mips_repl_qb (i32_a);
689 v2q15_s = (v2q15) {30, 30};
690 v2q15_r = __builtin_mips_repl_ph (30);
697 v2q15_s = (v2q15) {0x5612, 0x5612};
698 v2q15_r = __builtin_mips_repl_ph (i32_a);
704 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
705 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
710 __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b);
711 i32_r = __builtin_mips_rddsp (16);
715 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
716 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
721 __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b);
722 i32_r = __builtin_mips_rddsp (16);
726 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
727 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
732 __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b);
733 i32_r = __builtin_mips_rddsp (16);
737 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
738 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
743 i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b);
747 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
748 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
753 i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b);
757 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
758 v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
763 i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b);
767 __builtin_mips_wrdsp (0,31); // Clear all condition code bits.
768 v2q15_a = (v2q15) {0x1234, 0x5678};
769 v2q15_b = (v2q15) {0x1234, 0x7856};
774 __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b);
775 i32_r = __builtin_mips_rddsp (16);
779 v2q15_a = (v2q15) {0x1234, 0x5678};
780 v2q15_b = (v2q15) {0x1234, 0x7856};
785 __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b);
786 i32_r = __builtin_mips_rddsp (16);
790 v2q15_a = (v2q15) {0x1234, 0x5678};
791 v2q15_b = (v2q15) {0x1234, 0x7856};
793 __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b);
794 i32_r = __builtin_mips_rddsp (16);
798 i32_a = 0x0a000000; // cc: 0000 1010
799 __builtin_mips_wrdsp (i32_a, 31);
800 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
801 v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87};
803 v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78};
805 v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87};
806 v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b);
812 i32_a = 0x02000000; // cc: 0000 0010
813 __builtin_mips_wrdsp (i32_a, 31);
814 v2q15_a = (v2q15) {0x1234, 0x5678};
815 v2q15_b = (v2q15) {0x2143, 0x6587};
817 v2q15_s = (v2q15) {0x2143, 0x5678};
819 v2q15_s = (v2q15) {0x1234, 0x6587};
820 v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b);
826 v2q15_a = (v2q15) {0x1234, 0x5678};
827 v2q15_b = (v2q15) {0x1234, 0x7856};
829 v2q15_s = (v2q15) {0x7856, 0x1234};
831 v2q15_s = (v2q15) {0x5678, 0x1234};
832 v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b);
839 a64_a = 0x1234567887654321LL;
841 i32_r = __builtin_mips_extr_w (a64_a, 4);
845 a64_a = 0x1234567887658321LL;
847 i32_r = __builtin_mips_extr_r_w (a64_a, 16);
851 a64_a = 0x12345677fffffff8LL;
853 i32_r = __builtin_mips_extr_rs_w (a64_a, 4);
857 a64_a = 0x1234567887658321LL;
859 i32_r = __builtin_mips_extr_s_h (a64_a, 16);
863 a64_a = 0x0000007887658321LL;
866 i32_r = __builtin_mips_extr_s_h (a64_a, i32_b);
870 a64_a = 0x1234567887654321LL;
873 i32_r = __builtin_mips_extr_w (a64_a, i32_b);
877 a64_a = 0x1234567887658321LL;
880 i32_r = __builtin_mips_extr_r_w (a64_a, i32_b);
884 a64_a = 0x12345677fffffff8LL;
887 i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b);
891 i32_a = 0x0000021f; // pos is 31
892 __builtin_mips_wrdsp (i32_a, 31);
893 a64_a = 0x1234567887654321LL;
895 i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits
899 i32_a = 0x0000021f; // pos is 31
900 __builtin_mips_wrdsp (i32_a, 31);
901 a64_a = 0x1234567887654321LL;
902 i32_b = 7; // size is 8. NOTE!! we should use 7
904 i32_r = __builtin_mips_extp (a64_a, i32_b);
908 i32_a = 0x0000021f; // pos is 31
909 __builtin_mips_wrdsp (i32_a, 31);
910 a64_a = 0x1234567887654321LL;
912 i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits
916 i32_s = 0x0000021b; // pos is 27
917 i32_r = __builtin_mips_rddsp (31);
921 i32_a = 0x0000021f; // pos is 31
922 __builtin_mips_wrdsp (i32_a, 31);
923 a64_a = 0x1234567887654321LL;
924 i32_b = 11; // size is 12. NOTE!!! We should use 11
926 i32_r = __builtin_mips_extpdp (a64_a, i32_b);
930 i32_s = 0x00000213; // pos is 19
931 i32_r = __builtin_mips_rddsp (31);
935 a64_a = 0x1234567887654321LL;
936 a64_s = 0x0012345678876543LL;
937 a64_r = __builtin_mips_shilo (a64_a, 8);
941 a64_a = 0x1234567887654321LL;
943 a64_s = 0x5678876543210000LL;
944 a64_r = __builtin_mips_shilo (a64_a, i32_b);
949 __builtin_mips_wrdsp (i32_a, 31);
950 a64_a = 0x1234567887654321LL;
952 a64_s = 0x8765432111112222LL;
953 a64_r = __builtin_mips_mthlip (a64_a, i32_b);
957 i32_r = __builtin_mips_rddsp (31);
963 __builtin_mips_wrdsp (i32_a, 63);
965 i32_r = __builtin_mips_rddsp (63);
972 i32_r = __builtin_mips_lbux (ptr_a, i32_b);
982 i32_r = __builtin_mips_lhx (ptr_a, i32_b);
992 i32_r = __builtin_mips_lwx (ptr_a, i32_b);
996 i32_a = 0x00000220; // pos is 32, size is 4
997 __builtin_mips_wrdsp (i32_a, 63);
999 i32_r = __builtin_mips_bposge32 ();
1007 a64_s = 0xF7776EEF12345678LL;
1008 a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
1015 ui32_b = 0x80000000;
1016 ui32_c = 0x11112222;
1017 a64_s = 0x0888911112345678LL;
1018 a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
1027 a64_s = 0x0888911112345678LL;
1028 a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
1035 ui32_b = 0x80000000;
1036 ui32_c = 0x11112222;
1037 a64_s = 0xF7776EEF12345678LL;
1038 a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
1046 a64_s = 0xF7776EEF00000000LL;
1047 a64_r = __builtin_mips_mult (i32_a, i32_b);
1053 ui32_a = 0x80000000;
1054 ui32_b = 0x11112222;
1055 a64_s = 0x888911100000000LL;
1056 a64_r = __builtin_mips_multu (ui32_a, ui32_b);