1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "hard-reg-set.h"
32 #include "insn-config.h"
40 /* Simplification and canonicalization of RTL. */
42 /* Nonzero if X has the form (PLUS frame-pointer integer). We check for
43 virtual regs here because the simplify_*_operation routines are called
44 by integrate.c, which is called before virtual register instantiation.
46 ?!? NONZERO_BASE_PLUS_P needs to move into
47 a header file so that their definitions can be shared with the
48 simplification routines in simplify-rtx.c. Until then, do not
49 change this macro without also changing the copy in simplify-rtx.c. */
51 /* Allows reference to the stack pointer.
53 This used to include FIXED_BASE_PLUS_P, however, we can't assume that
54 arg_pointer_rtx by itself is nonzero, because on at least one machine,
55 the i960, the arg pointer is zero when it is unused. */
57 #define NONZERO_BASE_PLUS_P(X) \
58 ((X) == frame_pointer_rtx || (X) == hard_frame_pointer_rtx \
59 || (X) == virtual_stack_vars_rtx \
60 || (X) == virtual_incoming_args_rtx \
61 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == CONST_INT \
62 && (XEXP (X, 0) == frame_pointer_rtx \
63 || XEXP (X, 0) == hard_frame_pointer_rtx \
64 || ((X) == arg_pointer_rtx \
65 && fixed_regs[ARG_POINTER_REGNUM]) \
66 || XEXP (X, 0) == virtual_stack_vars_rtx \
67 || XEXP (X, 0) == virtual_incoming_args_rtx)) \
68 || (X) == stack_pointer_rtx \
69 || (X) == virtual_stack_dynamic_rtx \
70 || (X) == virtual_outgoing_args_rtx \
71 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == CONST_INT \
72 && (XEXP (X, 0) == stack_pointer_rtx \
73 || XEXP (X, 0) == virtual_stack_dynamic_rtx \
74 || XEXP (X, 0) == virtual_outgoing_args_rtx)) \
75 || GET_CODE (X) == ADDRESSOF)
77 /* Much code operates on (low, high) pairs; the low value is an
78 unsigned wide int, the high value a signed wide int. We
79 occasionally need to sign extend from low to high as if low were a
81 #define HWI_SIGN_EXTEND(low) \
82 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
84 static rtx neg_const_int PARAMS ((enum machine_mode, rtx));
85 static int simplify_plus_minus_op_data_cmp PARAMS ((const void *,
87 static rtx simplify_plus_minus PARAMS ((enum rtx_code,
88 enum machine_mode, rtx,
91 /* Negate a CONST_INT rtx, truncating (because a conversion from a
92 maximally negative number can overflow). */
94 neg_const_int (mode, i)
95 enum machine_mode mode;
98 return gen_int_mode (- INTVAL (i), mode);
102 /* Make a binary operation by properly ordering the operands and
103 seeing if the expression folds. */
106 simplify_gen_binary (code, mode, op0, op1)
108 enum machine_mode mode;
113 /* Put complex operands first and constants second if commutative. */
114 if (GET_RTX_CLASS (code) == 'c'
115 && swap_commutative_operands_p (op0, op1))
116 tem = op0, op0 = op1, op1 = tem;
118 /* If this simplifies, do it. */
119 tem = simplify_binary_operation (code, mode, op0, op1);
123 /* Handle addition and subtraction specially. Otherwise, just form
126 if (code == PLUS || code == MINUS)
128 tem = simplify_plus_minus (code, mode, op0, op1, 1);
133 return gen_rtx_fmt_ee (code, mode, op0, op1);
136 /* If X is a MEM referencing the constant pool, return the real value.
137 Otherwise return X. */
139 avoid_constant_pool_reference (x)
143 enum machine_mode cmode;
145 if (GET_CODE (x) != MEM)
149 if (GET_CODE (addr) == LO_SUM)
150 addr = XEXP (addr, 1);
152 if (GET_CODE (addr) != SYMBOL_REF
153 || ! CONSTANT_POOL_ADDRESS_P (addr))
156 c = get_pool_constant (addr);
157 cmode = get_pool_mode (addr);
159 /* If we're accessing the constant in a different mode than it was
160 originally stored, attempt to fix that up via subreg simplifications.
161 If that fails we have no choice but to return the original memory. */
162 if (cmode != GET_MODE (x))
164 c = simplify_subreg (GET_MODE (x), c, cmode, 0);
171 /* Make a unary operation by first seeing if it folds and otherwise making
172 the specified operation. */
175 simplify_gen_unary (code, mode, op, op_mode)
177 enum machine_mode mode;
179 enum machine_mode op_mode;
183 /* If this simplifies, use it. */
184 if ((tem = simplify_unary_operation (code, mode, op, op_mode)) != 0)
187 return gen_rtx_fmt_e (code, mode, op);
190 /* Likewise for ternary operations. */
193 simplify_gen_ternary (code, mode, op0_mode, op0, op1, op2)
195 enum machine_mode mode, op0_mode;
200 /* If this simplifies, use it. */
201 if (0 != (tem = simplify_ternary_operation (code, mode, op0_mode,
205 return gen_rtx_fmt_eee (code, mode, op0, op1, op2);
208 /* Likewise, for relational operations.
209 CMP_MODE specifies mode comparison is done in.
213 simplify_gen_relational (code, mode, cmp_mode, op0, op1)
215 enum machine_mode mode;
216 enum machine_mode cmp_mode;
221 if ((tem = simplify_relational_operation (code, cmp_mode, op0, op1)) != 0)
224 /* For the following tests, ensure const0_rtx is op1. */
225 if (op0 == const0_rtx && swap_commutative_operands_p (op0, op1))
226 tem = op0, op0 = op1, op1 = tem, code = swap_condition (code);
228 /* If op0 is a compare, extract the comparison arguments from it. */
229 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
230 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
232 /* If op0 is a comparison, extract the comparison arguments form it. */
233 if (code == NE && op1 == const0_rtx
234 && GET_RTX_CLASS (GET_CODE (op0)) == '<')
236 else if (code == EQ && op1 == const0_rtx)
238 /* The following tests GET_RTX_CLASS (GET_CODE (op0)) == '<'. */
239 enum rtx_code new = reversed_comparison_code (op0, NULL_RTX);
249 /* Put complex operands first and constants second. */
250 if (swap_commutative_operands_p (op0, op1))
251 tem = op0, op0 = op1, op1 = tem, code = swap_condition (code);
253 return gen_rtx_fmt_ee (code, mode, op0, op1);
256 /* Replace all occurrences of OLD in X with NEW and try to simplify the
257 resulting RTX. Return a new RTX which is as simplified as possible. */
260 simplify_replace_rtx (x, old, new)
265 enum rtx_code code = GET_CODE (x);
266 enum machine_mode mode = GET_MODE (x);
268 /* If X is OLD, return NEW. Otherwise, if this is an expression, try
269 to build a new expression substituting recursively. If we can't do
270 anything, return our input. */
275 switch (GET_RTX_CLASS (code))
279 enum machine_mode op_mode = GET_MODE (XEXP (x, 0));
280 rtx op = (XEXP (x, 0) == old
281 ? new : simplify_replace_rtx (XEXP (x, 0), old, new));
283 return simplify_gen_unary (code, mode, op, op_mode);
289 simplify_gen_binary (code, mode,
290 simplify_replace_rtx (XEXP (x, 0), old, new),
291 simplify_replace_rtx (XEXP (x, 1), old, new));
294 enum machine_mode op_mode = (GET_MODE (XEXP (x, 0)) != VOIDmode
295 ? GET_MODE (XEXP (x, 0))
296 : GET_MODE (XEXP (x, 1)));
297 rtx op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
298 rtx op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
301 simplify_gen_relational (code, mode,
304 : GET_MODE (op0) != VOIDmode
313 enum machine_mode op_mode = GET_MODE (XEXP (x, 0));
314 rtx op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
317 simplify_gen_ternary (code, mode,
322 simplify_replace_rtx (XEXP (x, 1), old, new),
323 simplify_replace_rtx (XEXP (x, 2), old, new));
327 /* The only case we try to handle is a SUBREG. */
331 exp = simplify_gen_subreg (GET_MODE (x),
332 simplify_replace_rtx (SUBREG_REG (x),
334 GET_MODE (SUBREG_REG (x)),
343 return replace_equiv_address_nv (x,
344 simplify_replace_rtx (XEXP (x, 0),
346 else if (code == LO_SUM)
348 rtx op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
349 rtx op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
351 /* (lo_sum (high x) x) -> x */
352 if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1))
355 return gen_rtx_LO_SUM (mode, op0, op1);
357 else if (code == REG)
359 if (REG_P (old) && REGNO (x) == REGNO (old))
371 /* Try to simplify a unary operation CODE whose output mode is to be
372 MODE with input operand OP whose mode was originally OP_MODE.
373 Return zero if no simplification can be made. */
375 simplify_unary_operation (code, mode, op, op_mode)
377 enum machine_mode mode;
379 enum machine_mode op_mode;
381 unsigned int width = GET_MODE_BITSIZE (mode);
382 rtx trueop = avoid_constant_pool_reference (op);
384 /* The order of these tests is critical so that, for example, we don't
385 check the wrong mode (input vs. output) for a conversion operation,
386 such as FIX. At some point, this should be simplified. */
388 if (code == FLOAT && GET_MODE (trueop) == VOIDmode
389 && (GET_CODE (trueop) == CONST_DOUBLE || GET_CODE (trueop) == CONST_INT))
391 HOST_WIDE_INT hv, lv;
394 if (GET_CODE (trueop) == CONST_INT)
395 lv = INTVAL (trueop), hv = HWI_SIGN_EXTEND (lv);
397 lv = CONST_DOUBLE_LOW (trueop), hv = CONST_DOUBLE_HIGH (trueop);
399 REAL_VALUE_FROM_INT (d, lv, hv, mode);
400 d = real_value_truncate (mode, d);
401 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
403 else if (code == UNSIGNED_FLOAT && GET_MODE (trueop) == VOIDmode
404 && (GET_CODE (trueop) == CONST_DOUBLE
405 || GET_CODE (trueop) == CONST_INT))
407 HOST_WIDE_INT hv, lv;
410 if (GET_CODE (trueop) == CONST_INT)
411 lv = INTVAL (trueop), hv = HWI_SIGN_EXTEND (lv);
413 lv = CONST_DOUBLE_LOW (trueop), hv = CONST_DOUBLE_HIGH (trueop);
415 if (op_mode == VOIDmode)
417 /* We don't know how to interpret negative-looking numbers in
418 this case, so don't try to fold those. */
422 else if (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT * 2)
425 hv = 0, lv &= GET_MODE_MASK (op_mode);
427 REAL_VALUE_FROM_UNSIGNED_INT (d, lv, hv, mode);
428 d = real_value_truncate (mode, d);
429 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
432 if (GET_CODE (trueop) == CONST_INT
433 && width <= HOST_BITS_PER_WIDE_INT && width > 0)
435 HOST_WIDE_INT arg0 = INTVAL (trueop);
449 val = (arg0 >= 0 ? arg0 : - arg0);
453 /* Don't use ffs here. Instead, get low order bit and then its
454 number. If arg0 is zero, this will return 0, as desired. */
455 arg0 &= GET_MODE_MASK (mode);
456 val = exact_log2 (arg0 & (- arg0)) + 1;
464 /* When zero-extending a CONST_INT, we need to know its
466 if (op_mode == VOIDmode)
468 if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT)
470 /* If we were really extending the mode,
471 we would have to distinguish between zero-extension
472 and sign-extension. */
473 if (width != GET_MODE_BITSIZE (op_mode))
477 else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
478 val = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
484 if (op_mode == VOIDmode)
486 if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT)
488 /* If we were really extending the mode,
489 we would have to distinguish between zero-extension
490 and sign-extension. */
491 if (width != GET_MODE_BITSIZE (op_mode))
495 else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
498 = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
500 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (op_mode) - 1)))
501 val -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
518 val = trunc_int_for_mode (val, mode);
520 return GEN_INT (val);
523 /* We can do some operations on integer CONST_DOUBLEs. Also allow
524 for a DImode operation on a CONST_INT. */
525 else if (GET_MODE (trueop) == VOIDmode
526 && width <= HOST_BITS_PER_WIDE_INT * 2
527 && (GET_CODE (trueop) == CONST_DOUBLE
528 || GET_CODE (trueop) == CONST_INT))
530 unsigned HOST_WIDE_INT l1, lv;
531 HOST_WIDE_INT h1, hv;
533 if (GET_CODE (trueop) == CONST_DOUBLE)
534 l1 = CONST_DOUBLE_LOW (trueop), h1 = CONST_DOUBLE_HIGH (trueop);
536 l1 = INTVAL (trueop), h1 = HWI_SIGN_EXTEND (l1);
546 neg_double (l1, h1, &lv, &hv);
551 neg_double (l1, h1, &lv, &hv);
559 lv = HOST_BITS_PER_WIDE_INT + exact_log2 (h1 & (-h1)) + 1;
561 lv = exact_log2 (l1 & (-l1)) + 1;
565 /* This is just a change-of-mode, so do nothing. */
570 if (op_mode == VOIDmode)
573 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT)
577 lv = l1 & GET_MODE_MASK (op_mode);
581 if (op_mode == VOIDmode
582 || GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT)
586 lv = l1 & GET_MODE_MASK (op_mode);
587 if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT
588 && (lv & ((HOST_WIDE_INT) 1
589 << (GET_MODE_BITSIZE (op_mode) - 1))) != 0)
590 lv -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
592 hv = HWI_SIGN_EXTEND (lv);
603 return immed_double_const (lv, hv, mode);
606 else if (GET_CODE (trueop) == CONST_DOUBLE
607 && GET_MODE_CLASS (mode) == MODE_FLOAT)
610 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop);
615 /* We don't attempt to optimize this. */
619 d = REAL_VALUE_ABS (d);
622 d = REAL_VALUE_NEGATE (d);
625 d = real_value_truncate (mode, d);
628 /* All this does is change the mode. */
631 real_arithmetic (&d, FIX_TRUNC_EXPR, &d, NULL);
637 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
640 else if (GET_CODE (trueop) == CONST_DOUBLE
641 && GET_MODE_CLASS (GET_MODE (trueop)) == MODE_FLOAT
642 && GET_MODE_CLASS (mode) == MODE_INT
643 && width <= HOST_BITS_PER_WIDE_INT && width > 0)
647 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop);
650 case FIX: i = REAL_VALUE_FIX (d); break;
651 case UNSIGNED_FIX: i = REAL_VALUE_UNSIGNED_FIX (d); break;
655 return gen_int_mode (i, mode);
658 /* This was formerly used only for non-IEEE float.
659 eggert@twinsun.com says it is safe for IEEE also. */
662 enum rtx_code reversed;
663 /* There are some simplifications we can do even if the operands
668 /* (not (not X)) == X. */
669 if (GET_CODE (op) == NOT)
672 /* (not (eq X Y)) == (ne X Y), etc. */
673 if (mode == BImode && GET_RTX_CLASS (GET_CODE (op)) == '<'
674 && ((reversed = reversed_comparison_code (op, NULL_RTX))
676 return gen_rtx_fmt_ee (reversed,
677 op_mode, XEXP (op, 0), XEXP (op, 1));
681 /* (neg (neg X)) == X. */
682 if (GET_CODE (op) == NEG)
687 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
688 becomes just the MINUS if its mode is MODE. This allows
689 folding switch statements on machines using casesi (such as
691 if (GET_CODE (op) == TRUNCATE
692 && GET_MODE (XEXP (op, 0)) == mode
693 && GET_CODE (XEXP (op, 0)) == MINUS
694 && GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF
695 && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
698 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
699 if (! POINTERS_EXTEND_UNSIGNED
700 && mode == Pmode && GET_MODE (op) == ptr_mode
702 || (GET_CODE (op) == SUBREG
703 && GET_CODE (SUBREG_REG (op)) == REG
704 && REG_POINTER (SUBREG_REG (op))
705 && GET_MODE (SUBREG_REG (op)) == Pmode)))
706 return convert_memory_address (Pmode, op);
710 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
712 if (POINTERS_EXTEND_UNSIGNED > 0
713 && mode == Pmode && GET_MODE (op) == ptr_mode
715 || (GET_CODE (op) == SUBREG
716 && GET_CODE (SUBREG_REG (op)) == REG
717 && REG_POINTER (SUBREG_REG (op))
718 && GET_MODE (SUBREG_REG (op)) == Pmode)))
719 return convert_memory_address (Pmode, op);
731 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
732 and OP1. Return 0 if no simplification is possible.
734 Don't use this for relational operations such as EQ or LT.
735 Use simplify_relational_operation instead. */
737 simplify_binary_operation (code, mode, op0, op1)
739 enum machine_mode mode;
742 HOST_WIDE_INT arg0, arg1, arg0s, arg1s;
744 unsigned int width = GET_MODE_BITSIZE (mode);
746 rtx trueop0 = avoid_constant_pool_reference (op0);
747 rtx trueop1 = avoid_constant_pool_reference (op1);
749 /* Relational operations don't work here. We must know the mode
750 of the operands in order to do the comparison correctly.
751 Assuming a full word can give incorrect results.
752 Consider comparing 128 with -128 in QImode. */
754 if (GET_RTX_CLASS (code) == '<')
757 /* Make sure the constant is second. */
758 if (GET_RTX_CLASS (code) == 'c'
759 && swap_commutative_operands_p (trueop0, trueop1))
761 tem = op0, op0 = op1, op1 = tem;
762 tem = trueop0, trueop0 = trueop1, trueop1 = tem;
765 if (GET_MODE_CLASS (mode) == MODE_FLOAT
766 && GET_CODE (trueop0) == CONST_DOUBLE
767 && GET_CODE (trueop1) == CONST_DOUBLE
768 && mode == GET_MODE (op0) && mode == GET_MODE (op1))
770 REAL_VALUE_TYPE f0, f1, value;
772 REAL_VALUE_FROM_CONST_DOUBLE (f0, trueop0);
773 REAL_VALUE_FROM_CONST_DOUBLE (f1, trueop1);
774 f0 = real_value_truncate (mode, f0);
775 f1 = real_value_truncate (mode, f1);
778 && !MODE_HAS_INFINITIES (mode)
779 && REAL_VALUES_EQUAL (f1, dconst0))
782 REAL_ARITHMETIC (value, rtx_to_tree_code (code), f0, f1);
784 value = real_value_truncate (mode, value);
785 return CONST_DOUBLE_FROM_REAL_VALUE (value, mode);
788 /* We can fold some multi-word operations. */
789 if (GET_MODE_CLASS (mode) == MODE_INT
790 && width == HOST_BITS_PER_WIDE_INT * 2
791 && (GET_CODE (trueop0) == CONST_DOUBLE
792 || GET_CODE (trueop0) == CONST_INT)
793 && (GET_CODE (trueop1) == CONST_DOUBLE
794 || GET_CODE (trueop1) == CONST_INT))
796 unsigned HOST_WIDE_INT l1, l2, lv;
797 HOST_WIDE_INT h1, h2, hv;
799 if (GET_CODE (trueop0) == CONST_DOUBLE)
800 l1 = CONST_DOUBLE_LOW (trueop0), h1 = CONST_DOUBLE_HIGH (trueop0);
802 l1 = INTVAL (trueop0), h1 = HWI_SIGN_EXTEND (l1);
804 if (GET_CODE (trueop1) == CONST_DOUBLE)
805 l2 = CONST_DOUBLE_LOW (trueop1), h2 = CONST_DOUBLE_HIGH (trueop1);
807 l2 = INTVAL (trueop1), h2 = HWI_SIGN_EXTEND (l2);
812 /* A - B == A + (-B). */
813 neg_double (l2, h2, &lv, &hv);
816 /* .. fall through ... */
819 add_double (l1, h1, l2, h2, &lv, &hv);
823 mul_double (l1, h1, l2, h2, &lv, &hv);
826 case DIV: case MOD: case UDIV: case UMOD:
827 /* We'd need to include tree.h to do this and it doesn't seem worth
832 lv = l1 & l2, hv = h1 & h2;
836 lv = l1 | l2, hv = h1 | h2;
840 lv = l1 ^ l2, hv = h1 ^ h2;
846 && ((unsigned HOST_WIDE_INT) l1
847 < (unsigned HOST_WIDE_INT) l2)))
856 && ((unsigned HOST_WIDE_INT) l1
857 > (unsigned HOST_WIDE_INT) l2)))
864 if ((unsigned HOST_WIDE_INT) h1 < (unsigned HOST_WIDE_INT) h2
866 && ((unsigned HOST_WIDE_INT) l1
867 < (unsigned HOST_WIDE_INT) l2)))
874 if ((unsigned HOST_WIDE_INT) h1 > (unsigned HOST_WIDE_INT) h2
876 && ((unsigned HOST_WIDE_INT) l1
877 > (unsigned HOST_WIDE_INT) l2)))
883 case LSHIFTRT: case ASHIFTRT:
885 case ROTATE: case ROTATERT:
886 #ifdef SHIFT_COUNT_TRUNCATED
887 if (SHIFT_COUNT_TRUNCATED)
888 l2 &= (GET_MODE_BITSIZE (mode) - 1), h2 = 0;
891 if (h2 != 0 || l2 >= GET_MODE_BITSIZE (mode))
894 if (code == LSHIFTRT || code == ASHIFTRT)
895 rshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv,
897 else if (code == ASHIFT)
898 lshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv, 1);
899 else if (code == ROTATE)
900 lrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv);
901 else /* code == ROTATERT */
902 rrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv);
909 return immed_double_const (lv, hv, mode);
912 if (GET_CODE (op0) != CONST_INT || GET_CODE (op1) != CONST_INT
913 || width > HOST_BITS_PER_WIDE_INT || width == 0)
915 /* Even if we can't compute a constant result,
916 there are some cases worth simplifying. */
921 /* Maybe simplify x + 0 to x. The two expressions are equivalent
922 when x is NaN, infinite, or finite and nonzero. They aren't
923 when x is -0 and the rounding mode is not towards -infinity,
924 since (-0) + 0 is then 0. */
925 if (!HONOR_SIGNED_ZEROS (mode) && trueop1 == CONST0_RTX (mode))
928 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
929 transformations are safe even for IEEE. */
930 if (GET_CODE (op0) == NEG)
931 return simplify_gen_binary (MINUS, mode, op1, XEXP (op0, 0));
932 else if (GET_CODE (op1) == NEG)
933 return simplify_gen_binary (MINUS, mode, op0, XEXP (op1, 0));
936 if (INTEGRAL_MODE_P (mode)
937 && GET_CODE (op0) == NOT
938 && trueop1 == const1_rtx)
939 return gen_rtx_NEG (mode, XEXP (op0, 0));
941 /* Handle both-operands-constant cases. We can only add
942 CONST_INTs to constants since the sum of relocatable symbols
943 can't be handled by most assemblers. Don't add CONST_INT
944 to CONST_INT since overflow won't be computed properly if wider
945 than HOST_BITS_PER_WIDE_INT. */
947 if (CONSTANT_P (op0) && GET_MODE (op0) != VOIDmode
948 && GET_CODE (op1) == CONST_INT)
949 return plus_constant (op0, INTVAL (op1));
950 else if (CONSTANT_P (op1) && GET_MODE (op1) != VOIDmode
951 && GET_CODE (op0) == CONST_INT)
952 return plus_constant (op1, INTVAL (op0));
954 /* See if this is something like X * C - X or vice versa or
955 if the multiplication is written as a shift. If so, we can
956 distribute and make a new multiply, shift, or maybe just
957 have X (if C is 2 in the example above). But don't make
958 real multiply if we didn't have one before. */
960 if (! FLOAT_MODE_P (mode))
962 HOST_WIDE_INT coeff0 = 1, coeff1 = 1;
963 rtx lhs = op0, rhs = op1;
966 if (GET_CODE (lhs) == NEG)
967 coeff0 = -1, lhs = XEXP (lhs, 0);
968 else if (GET_CODE (lhs) == MULT
969 && GET_CODE (XEXP (lhs, 1)) == CONST_INT)
971 coeff0 = INTVAL (XEXP (lhs, 1)), lhs = XEXP (lhs, 0);
974 else if (GET_CODE (lhs) == ASHIFT
975 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
976 && INTVAL (XEXP (lhs, 1)) >= 0
977 && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
979 coeff0 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (lhs, 1));
983 if (GET_CODE (rhs) == NEG)
984 coeff1 = -1, rhs = XEXP (rhs, 0);
985 else if (GET_CODE (rhs) == MULT
986 && GET_CODE (XEXP (rhs, 1)) == CONST_INT)
988 coeff1 = INTVAL (XEXP (rhs, 1)), rhs = XEXP (rhs, 0);
991 else if (GET_CODE (rhs) == ASHIFT
992 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
993 && INTVAL (XEXP (rhs, 1)) >= 0
994 && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
996 coeff1 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (rhs, 1));
1000 if (rtx_equal_p (lhs, rhs))
1002 tem = simplify_gen_binary (MULT, mode, lhs,
1003 GEN_INT (coeff0 + coeff1));
1004 return (GET_CODE (tem) == MULT && ! had_mult) ? 0 : tem;
1008 /* If one of the operands is a PLUS or a MINUS, see if we can
1009 simplify this by the associative law.
1010 Don't use the associative law for floating point.
1011 The inaccuracy makes it nonassociative,
1012 and subtle programs can break if operations are associated. */
1014 if (INTEGRAL_MODE_P (mode)
1015 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
1016 || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS
1017 || (GET_CODE (op0) == CONST
1018 && GET_CODE (XEXP (op0, 0)) == PLUS)
1019 || (GET_CODE (op1) == CONST
1020 && GET_CODE (XEXP (op1, 0)) == PLUS))
1021 && (tem = simplify_plus_minus (code, mode, op0, op1, 0)) != 0)
1027 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
1028 using cc0, in which case we want to leave it as a COMPARE
1029 so we can distinguish it from a register-register-copy.
1031 In IEEE floating point, x-0 is not the same as x. */
1033 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
1034 || ! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
1035 && trueop1 == CONST0_RTX (mode))
1039 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
1040 if (((GET_CODE (op0) == GT && GET_CODE (op1) == LT)
1041 || (GET_CODE (op0) == GTU && GET_CODE (op1) == LTU))
1042 && XEXP (op0, 1) == const0_rtx && XEXP (op1, 1) == const0_rtx)
1044 rtx xop00 = XEXP (op0, 0);
1045 rtx xop10 = XEXP (op1, 0);
1048 if (GET_CODE (xop00) == CC0 && GET_CODE (xop10) == CC0)
1050 if (GET_CODE (xop00) == REG && GET_CODE (xop10) == REG
1051 && GET_MODE (xop00) == GET_MODE (xop10)
1052 && REGNO (xop00) == REGNO (xop10)
1053 && GET_MODE_CLASS (GET_MODE (xop00)) == MODE_CC
1054 && GET_MODE_CLASS (GET_MODE (xop10)) == MODE_CC)
1061 /* We can't assume x-x is 0 even with non-IEEE floating point,
1062 but since it is zero except in very strange circumstances, we
1063 will treat it as zero with -funsafe-math-optimizations. */
1064 if (rtx_equal_p (trueop0, trueop1)
1065 && ! side_effects_p (op0)
1066 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations))
1067 return CONST0_RTX (mode);
1069 /* Change subtraction from zero into negation. (0 - x) is the
1070 same as -x when x is NaN, infinite, or finite and nonzero.
1071 But if the mode has signed zeros, and does not round towards
1072 -infinity, then 0 - 0 is 0, not -0. */
1073 if (!HONOR_SIGNED_ZEROS (mode) && trueop0 == CONST0_RTX (mode))
1074 return gen_rtx_NEG (mode, op1);
1076 /* (-1 - a) is ~a. */
1077 if (trueop0 == constm1_rtx)
1078 return gen_rtx_NOT (mode, op1);
1080 /* Subtracting 0 has no effect unless the mode has signed zeros
1081 and supports rounding towards -infinity. In such a case,
1083 if (!(HONOR_SIGNED_ZEROS (mode)
1084 && HONOR_SIGN_DEPENDENT_ROUNDING (mode))
1085 && trueop1 == CONST0_RTX (mode))
1088 /* See if this is something like X * C - X or vice versa or
1089 if the multiplication is written as a shift. If so, we can
1090 distribute and make a new multiply, shift, or maybe just
1091 have X (if C is 2 in the example above). But don't make
1092 real multiply if we didn't have one before. */
1094 if (! FLOAT_MODE_P (mode))
1096 HOST_WIDE_INT coeff0 = 1, coeff1 = 1;
1097 rtx lhs = op0, rhs = op1;
1100 if (GET_CODE (lhs) == NEG)
1101 coeff0 = -1, lhs = XEXP (lhs, 0);
1102 else if (GET_CODE (lhs) == MULT
1103 && GET_CODE (XEXP (lhs, 1)) == CONST_INT)
1105 coeff0 = INTVAL (XEXP (lhs, 1)), lhs = XEXP (lhs, 0);
1108 else if (GET_CODE (lhs) == ASHIFT
1109 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
1110 && INTVAL (XEXP (lhs, 1)) >= 0
1111 && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
1113 coeff0 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (lhs, 1));
1114 lhs = XEXP (lhs, 0);
1117 if (GET_CODE (rhs) == NEG)
1118 coeff1 = - 1, rhs = XEXP (rhs, 0);
1119 else if (GET_CODE (rhs) == MULT
1120 && GET_CODE (XEXP (rhs, 1)) == CONST_INT)
1122 coeff1 = INTVAL (XEXP (rhs, 1)), rhs = XEXP (rhs, 0);
1125 else if (GET_CODE (rhs) == ASHIFT
1126 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
1127 && INTVAL (XEXP (rhs, 1)) >= 0
1128 && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
1130 coeff1 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (rhs, 1));
1131 rhs = XEXP (rhs, 0);
1134 if (rtx_equal_p (lhs, rhs))
1136 tem = simplify_gen_binary (MULT, mode, lhs,
1137 GEN_INT (coeff0 - coeff1));
1138 return (GET_CODE (tem) == MULT && ! had_mult) ? 0 : tem;
1142 /* (a - (-b)) -> (a + b). True even for IEEE. */
1143 if (GET_CODE (op1) == NEG)
1144 return simplify_gen_binary (PLUS, mode, op0, XEXP (op1, 0));
1146 /* If one of the operands is a PLUS or a MINUS, see if we can
1147 simplify this by the associative law.
1148 Don't use the associative law for floating point.
1149 The inaccuracy makes it nonassociative,
1150 and subtle programs can break if operations are associated. */
1152 if (INTEGRAL_MODE_P (mode)
1153 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
1154 || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS
1155 || (GET_CODE (op0) == CONST
1156 && GET_CODE (XEXP (op0, 0)) == PLUS)
1157 || (GET_CODE (op1) == CONST
1158 && GET_CODE (XEXP (op1, 0)) == PLUS))
1159 && (tem = simplify_plus_minus (code, mode, op0, op1, 0)) != 0)
1162 /* Don't let a relocatable value get a negative coeff. */
1163 if (GET_CODE (op1) == CONST_INT && GET_MODE (op0) != VOIDmode)
1164 return simplify_gen_binary (PLUS, mode,
1166 neg_const_int (mode, op1));
1168 /* (x - (x & y)) -> (x & ~y) */
1169 if (GET_CODE (op1) == AND)
1171 if (rtx_equal_p (op0, XEXP (op1, 0)))
1172 return simplify_gen_binary (AND, mode, op0,
1173 gen_rtx_NOT (mode, XEXP (op1, 1)));
1174 if (rtx_equal_p (op0, XEXP (op1, 1)))
1175 return simplify_gen_binary (AND, mode, op0,
1176 gen_rtx_NOT (mode, XEXP (op1, 0)));
1181 if (trueop1 == constm1_rtx)
1183 tem = simplify_unary_operation (NEG, mode, op0, mode);
1185 return tem ? tem : gen_rtx_NEG (mode, op0);
1188 /* Maybe simplify x * 0 to 0. The reduction is not valid if
1189 x is NaN, since x * 0 is then also NaN. Nor is it valid
1190 when the mode has signed zeros, since multiplying a negative
1191 number by 0 will give -0, not 0. */
1192 if (!HONOR_NANS (mode)
1193 && !HONOR_SIGNED_ZEROS (mode)
1194 && trueop1 == CONST0_RTX (mode)
1195 && ! side_effects_p (op0))
1198 /* In IEEE floating point, x*1 is not equivalent to x for
1200 if (!HONOR_SNANS (mode)
1201 && trueop1 == CONST1_RTX (mode))
1204 /* Convert multiply by constant power of two into shift unless
1205 we are still generating RTL. This test is a kludge. */
1206 if (GET_CODE (trueop1) == CONST_INT
1207 && (val = exact_log2 (INTVAL (trueop1))) >= 0
1208 /* If the mode is larger than the host word size, and the
1209 uppermost bit is set, then this isn't a power of two due
1210 to implicit sign extension. */
1211 && (width <= HOST_BITS_PER_WIDE_INT
1212 || val != HOST_BITS_PER_WIDE_INT - 1)
1213 && ! rtx_equal_function_value_matters)
1214 return gen_rtx_ASHIFT (mode, op0, GEN_INT (val));
1216 /* x*2 is x+x and x*(-1) is -x */
1217 if (GET_CODE (trueop1) == CONST_DOUBLE
1218 && GET_MODE_CLASS (GET_MODE (trueop1)) == MODE_FLOAT
1219 && GET_MODE (op0) == mode)
1222 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
1224 if (REAL_VALUES_EQUAL (d, dconst2))
1225 return gen_rtx_PLUS (mode, op0, copy_rtx (op0));
1227 if (REAL_VALUES_EQUAL (d, dconstm1))
1228 return gen_rtx_NEG (mode, op0);
1233 if (trueop1 == const0_rtx)
1235 if (GET_CODE (trueop1) == CONST_INT
1236 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1237 == GET_MODE_MASK (mode)))
1239 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1241 /* A | (~A) -> -1 */
1242 if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
1243 || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
1244 && ! side_effects_p (op0)
1245 && GET_MODE_CLASS (mode) != MODE_CC)
1250 if (trueop1 == const0_rtx)
1252 if (GET_CODE (trueop1) == CONST_INT
1253 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1254 == GET_MODE_MASK (mode)))
1255 return gen_rtx_NOT (mode, op0);
1256 if (trueop0 == trueop1 && ! side_effects_p (op0)
1257 && GET_MODE_CLASS (mode) != MODE_CC)
1262 if (trueop1 == const0_rtx && ! side_effects_p (op0))
1264 if (GET_CODE (trueop1) == CONST_INT
1265 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1266 == GET_MODE_MASK (mode)))
1268 if (trueop0 == trueop1 && ! side_effects_p (op0)
1269 && GET_MODE_CLASS (mode) != MODE_CC)
1272 if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
1273 || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
1274 && ! side_effects_p (op0)
1275 && GET_MODE_CLASS (mode) != MODE_CC)
1280 /* Convert divide by power of two into shift (divide by 1 handled
1282 if (GET_CODE (trueop1) == CONST_INT
1283 && (arg1 = exact_log2 (INTVAL (trueop1))) > 0)
1284 return gen_rtx_LSHIFTRT (mode, op0, GEN_INT (arg1));
1286 /* ... fall through ... */
1289 if (trueop1 == CONST1_RTX (mode))
1291 /* On some platforms DIV uses narrower mode than its
1293 rtx x = gen_lowpart_common (mode, op0);
1296 else if (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
1297 return gen_lowpart_SUBREG (mode, op0);
1302 /* Maybe change 0 / x to 0. This transformation isn't safe for
1303 modes with NaNs, since 0 / 0 will then be NaN rather than 0.
1304 Nor is it safe for modes with signed zeros, since dividing
1305 0 by a negative number gives -0, not 0. */
1306 if (!HONOR_NANS (mode)
1307 && !HONOR_SIGNED_ZEROS (mode)
1308 && trueop0 == CONST0_RTX (mode)
1309 && ! side_effects_p (op1))
1312 /* Change division by a constant into multiplication. Only do
1313 this with -funsafe-math-optimizations. */
1314 else if (GET_CODE (trueop1) == CONST_DOUBLE
1315 && GET_MODE_CLASS (GET_MODE (trueop1)) == MODE_FLOAT
1316 && trueop1 != CONST0_RTX (mode)
1317 && flag_unsafe_math_optimizations)
1320 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
1322 if (! REAL_VALUES_EQUAL (d, dconst0))
1324 REAL_ARITHMETIC (d, rtx_to_tree_code (DIV), dconst1, d);
1325 return gen_rtx_MULT (mode, op0,
1326 CONST_DOUBLE_FROM_REAL_VALUE (d, mode));
1332 /* Handle modulus by power of two (mod with 1 handled below). */
1333 if (GET_CODE (trueop1) == CONST_INT
1334 && exact_log2 (INTVAL (trueop1)) > 0)
1335 return gen_rtx_AND (mode, op0, GEN_INT (INTVAL (op1) - 1));
1337 /* ... fall through ... */
1340 if ((trueop0 == const0_rtx || trueop1 == const1_rtx)
1341 && ! side_effects_p (op0) && ! side_effects_p (op1))
1347 /* Rotating ~0 always results in ~0. */
1348 if (GET_CODE (trueop0) == CONST_INT && width <= HOST_BITS_PER_WIDE_INT
1349 && (unsigned HOST_WIDE_INT) INTVAL (trueop0) == GET_MODE_MASK (mode)
1350 && ! side_effects_p (op1))
1353 /* ... fall through ... */
1358 if (trueop1 == const0_rtx)
1360 if (trueop0 == const0_rtx && ! side_effects_p (op1))
1365 if (width <= HOST_BITS_PER_WIDE_INT && GET_CODE (trueop1) == CONST_INT
1366 && INTVAL (trueop1) == (HOST_WIDE_INT) 1 << (width -1)
1367 && ! side_effects_p (op0))
1369 else if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1374 if (width <= HOST_BITS_PER_WIDE_INT && GET_CODE (trueop1) == CONST_INT
1375 && ((unsigned HOST_WIDE_INT) INTVAL (trueop1)
1376 == (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode) >> 1)
1377 && ! side_effects_p (op0))
1379 else if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1384 if (trueop1 == const0_rtx && ! side_effects_p (op0))
1386 else if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1391 if (trueop1 == constm1_rtx && ! side_effects_p (op0))
1393 else if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1401 /* ??? There are simplifications that can be done. */
1411 /* Get the integer argument values in two forms:
1412 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
1414 arg0 = INTVAL (trueop0);
1415 arg1 = INTVAL (trueop1);
1417 if (width < HOST_BITS_PER_WIDE_INT)
1419 arg0 &= ((HOST_WIDE_INT) 1 << width) - 1;
1420 arg1 &= ((HOST_WIDE_INT) 1 << width) - 1;
1423 if (arg0s & ((HOST_WIDE_INT) 1 << (width - 1)))
1424 arg0s |= ((HOST_WIDE_INT) (-1) << width);
1427 if (arg1s & ((HOST_WIDE_INT) 1 << (width - 1)))
1428 arg1s |= ((HOST_WIDE_INT) (-1) << width);
1436 /* Compute the value of the arithmetic. */
1441 val = arg0s + arg1s;
1445 val = arg0s - arg1s;
1449 val = arg0s * arg1s;
1454 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
1457 val = arg0s / arg1s;
1462 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
1465 val = arg0s % arg1s;
1470 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
1473 val = (unsigned HOST_WIDE_INT) arg0 / arg1;
1478 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
1481 val = (unsigned HOST_WIDE_INT) arg0 % arg1;
1497 /* If shift count is undefined, don't fold it; let the machine do
1498 what it wants. But truncate it if the machine will do that. */
1502 #ifdef SHIFT_COUNT_TRUNCATED
1503 if (SHIFT_COUNT_TRUNCATED)
1507 val = ((unsigned HOST_WIDE_INT) arg0) >> arg1;
1514 #ifdef SHIFT_COUNT_TRUNCATED
1515 if (SHIFT_COUNT_TRUNCATED)
1519 val = ((unsigned HOST_WIDE_INT) arg0) << arg1;
1526 #ifdef SHIFT_COUNT_TRUNCATED
1527 if (SHIFT_COUNT_TRUNCATED)
1531 val = arg0s >> arg1;
1533 /* Bootstrap compiler may not have sign extended the right shift.
1534 Manually extend the sign to insure bootstrap cc matches gcc. */
1535 if (arg0s < 0 && arg1 > 0)
1536 val |= ((HOST_WIDE_INT) -1) << (HOST_BITS_PER_WIDE_INT - arg1);
1545 val = ((((unsigned HOST_WIDE_INT) arg0) << (width - arg1))
1546 | (((unsigned HOST_WIDE_INT) arg0) >> arg1));
1554 val = ((((unsigned HOST_WIDE_INT) arg0) << arg1)
1555 | (((unsigned HOST_WIDE_INT) arg0) >> (width - arg1)));
1559 /* Do nothing here. */
1563 val = arg0s <= arg1s ? arg0s : arg1s;
1567 val = ((unsigned HOST_WIDE_INT) arg0
1568 <= (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
1572 val = arg0s > arg1s ? arg0s : arg1s;
1576 val = ((unsigned HOST_WIDE_INT) arg0
1577 > (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
1584 val = trunc_int_for_mode (val, mode);
1586 return GEN_INT (val);
1589 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
1592 Rather than test for specific case, we do this by a brute-force method
1593 and do all possible simplifications until no more changes occur. Then
1594 we rebuild the operation.
1596 If FORCE is true, then always generate the rtx. This is used to
1597 canonicalize stuff emitted from simplify_gen_binary. Note that this
1598 can still fail if the rtx is too complex. It won't fail just because
1599 the result is not 'simpler' than the input, however. */
1601 struct simplify_plus_minus_op_data
1608 simplify_plus_minus_op_data_cmp (p1, p2)
1612 const struct simplify_plus_minus_op_data *d1 = p1;
1613 const struct simplify_plus_minus_op_data *d2 = p2;
1615 return (commutative_operand_precedence (d2->op)
1616 - commutative_operand_precedence (d1->op));
1620 simplify_plus_minus (code, mode, op0, op1, force)
1622 enum machine_mode mode;
1626 struct simplify_plus_minus_op_data ops[8];
1628 int n_ops = 2, input_ops = 2, input_consts = 0, n_consts;
1629 int first, negate, changed;
1632 memset ((char *) ops, 0, sizeof ops);
1634 /* Set up the two operands and then expand them until nothing has been
1635 changed. If we run out of room in our array, give up; this should
1636 almost never happen. */
1641 ops[1].neg = (code == MINUS);
1647 for (i = 0; i < n_ops; i++)
1649 rtx this_op = ops[i].op;
1650 int this_neg = ops[i].neg;
1651 enum rtx_code this_code = GET_CODE (this_op);
1660 ops[n_ops].op = XEXP (this_op, 1);
1661 ops[n_ops].neg = (this_code == MINUS) ^ this_neg;
1664 ops[i].op = XEXP (this_op, 0);
1670 ops[i].op = XEXP (this_op, 0);
1671 ops[i].neg = ! this_neg;
1677 && GET_CODE (XEXP (this_op, 0)) == PLUS
1678 && CONSTANT_P (XEXP (XEXP (this_op, 0), 0))
1679 && CONSTANT_P (XEXP (XEXP (this_op, 0), 1)))
1681 ops[i].op = XEXP (XEXP (this_op, 0), 0);
1682 ops[n_ops].op = XEXP (XEXP (this_op, 0), 1);
1683 ops[n_ops].neg = this_neg;
1691 /* ~a -> (-a - 1) */
1694 ops[n_ops].op = constm1_rtx;
1695 ops[n_ops++].neg = this_neg;
1696 ops[i].op = XEXP (this_op, 0);
1697 ops[i].neg = !this_neg;
1705 ops[i].op = neg_const_int (mode, this_op);
1718 /* If we only have two operands, we can't do anything. */
1719 if (n_ops <= 2 && !force)
1722 /* Count the number of CONSTs we didn't split above. */
1723 for (i = 0; i < n_ops; i++)
1724 if (GET_CODE (ops[i].op) == CONST)
1727 /* Now simplify each pair of operands until nothing changes. The first
1728 time through just simplify constants against each other. */
1735 for (i = 0; i < n_ops - 1; i++)
1736 for (j = i + 1; j < n_ops; j++)
1738 rtx lhs = ops[i].op, rhs = ops[j].op;
1739 int lneg = ops[i].neg, rneg = ops[j].neg;
1741 if (lhs != 0 && rhs != 0
1742 && (! first || (CONSTANT_P (lhs) && CONSTANT_P (rhs))))
1744 enum rtx_code ncode = PLUS;
1750 tem = lhs, lhs = rhs, rhs = tem;
1752 else if (swap_commutative_operands_p (lhs, rhs))
1753 tem = lhs, lhs = rhs, rhs = tem;
1755 tem = simplify_binary_operation (ncode, mode, lhs, rhs);
1757 /* Reject "simplifications" that just wrap the two
1758 arguments in a CONST. Failure to do so can result
1759 in infinite recursion with simplify_binary_operation
1760 when it calls us to simplify CONST operations. */
1762 && ! (GET_CODE (tem) == CONST
1763 && GET_CODE (XEXP (tem, 0)) == ncode
1764 && XEXP (XEXP (tem, 0), 0) == lhs
1765 && XEXP (XEXP (tem, 0), 1) == rhs)
1766 /* Don't allow -x + -1 -> ~x simplifications in the
1767 first pass. This allows us the chance to combine
1768 the -1 with other constants. */
1770 && GET_CODE (tem) == NOT
1771 && XEXP (tem, 0) == rhs))
1774 if (GET_CODE (tem) == NEG)
1775 tem = XEXP (tem, 0), lneg = !lneg;
1776 if (GET_CODE (tem) == CONST_INT && lneg)
1777 tem = neg_const_int (mode, tem), lneg = 0;
1781 ops[j].op = NULL_RTX;
1791 /* Pack all the operands to the lower-numbered entries. */
1792 for (i = 0, j = 0; j < n_ops; j++)
1797 /* Sort the operations based on swap_commutative_operands_p. */
1798 qsort (ops, n_ops, sizeof (*ops), simplify_plus_minus_op_data_cmp);
1800 /* We suppressed creation of trivial CONST expressions in the
1801 combination loop to avoid recursion. Create one manually now.
1802 The combination loop should have ensured that there is exactly
1803 one CONST_INT, and the sort will have ensured that it is last
1804 in the array and that any other constant will be next-to-last. */
1807 && GET_CODE (ops[n_ops - 1].op) == CONST_INT
1808 && CONSTANT_P (ops[n_ops - 2].op))
1810 rtx value = ops[n_ops - 1].op;
1811 if (ops[n_ops - 1].neg ^ ops[n_ops - 2].neg)
1812 value = neg_const_int (mode, value);
1813 ops[n_ops - 2].op = plus_constant (ops[n_ops - 2].op, INTVAL (value));
1817 /* Count the number of CONSTs that we generated. */
1819 for (i = 0; i < n_ops; i++)
1820 if (GET_CODE (ops[i].op) == CONST)
1823 /* Give up if we didn't reduce the number of operands we had. Make
1824 sure we count a CONST as two operands. If we have the same
1825 number of operands, but have made more CONSTs than before, this
1826 is also an improvement, so accept it. */
1828 && (n_ops + n_consts > input_ops
1829 || (n_ops + n_consts == input_ops && n_consts <= input_consts)))
1832 /* Put a non-negated operand first. If there aren't any, make all
1833 operands positive and negate the whole thing later. */
1836 for (i = 0; i < n_ops && ops[i].neg; i++)
1840 for (i = 0; i < n_ops; i++)
1852 /* Now make the result by performing the requested operations. */
1854 for (i = 1; i < n_ops; i++)
1855 result = gen_rtx_fmt_ee (ops[i].neg ? MINUS : PLUS,
1856 mode, result, ops[i].op);
1858 return negate ? gen_rtx_NEG (mode, result) : result;
1861 /* Like simplify_binary_operation except used for relational operators.
1862 MODE is the mode of the operands, not that of the result. If MODE
1863 is VOIDmode, both operands must also be VOIDmode and we compare the
1864 operands in "infinite precision".
1866 If no simplification is possible, this function returns zero. Otherwise,
1867 it returns either const_true_rtx or const0_rtx. */
1870 simplify_relational_operation (code, mode, op0, op1)
1872 enum machine_mode mode;
1875 int equal, op0lt, op0ltu, op1lt, op1ltu;
1880 if (mode == VOIDmode
1881 && (GET_MODE (op0) != VOIDmode
1882 || GET_MODE (op1) != VOIDmode))
1885 /* If op0 is a compare, extract the comparison arguments from it. */
1886 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
1887 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
1889 trueop0 = avoid_constant_pool_reference (op0);
1890 trueop1 = avoid_constant_pool_reference (op1);
1892 /* We can't simplify MODE_CC values since we don't know what the
1893 actual comparison is. */
1894 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC
1901 /* Make sure the constant is second. */
1902 if (swap_commutative_operands_p (trueop0, trueop1))
1904 tem = op0, op0 = op1, op1 = tem;
1905 tem = trueop0, trueop0 = trueop1, trueop1 = tem;
1906 code = swap_condition (code);
1909 /* For integer comparisons of A and B maybe we can simplify A - B and can
1910 then simplify a comparison of that with zero. If A and B are both either
1911 a register or a CONST_INT, this can't help; testing for these cases will
1912 prevent infinite recursion here and speed things up.
1914 If CODE is an unsigned comparison, then we can never do this optimization,
1915 because it gives an incorrect result if the subtraction wraps around zero.
1916 ANSI C defines unsigned operations such that they never overflow, and
1917 thus such cases can not be ignored. */
1919 if (INTEGRAL_MODE_P (mode) && trueop1 != const0_rtx
1920 && ! ((GET_CODE (op0) == REG || GET_CODE (trueop0) == CONST_INT)
1921 && (GET_CODE (op1) == REG || GET_CODE (trueop1) == CONST_INT))
1922 && 0 != (tem = simplify_binary_operation (MINUS, mode, op0, op1))
1923 && code != GTU && code != GEU && code != LTU && code != LEU)
1924 return simplify_relational_operation (signed_condition (code),
1925 mode, tem, const0_rtx);
1927 if (flag_unsafe_math_optimizations && code == ORDERED)
1928 return const_true_rtx;
1930 if (flag_unsafe_math_optimizations && code == UNORDERED)
1933 /* For modes without NaNs, if the two operands are equal, we know the
1935 if (!HONOR_NANS (GET_MODE (trueop0)) && rtx_equal_p (trueop0, trueop1))
1936 equal = 1, op0lt = 0, op0ltu = 0, op1lt = 0, op1ltu = 0;
1938 /* If the operands are floating-point constants, see if we can fold
1940 else if (GET_CODE (trueop0) == CONST_DOUBLE
1941 && GET_CODE (trueop1) == CONST_DOUBLE
1942 && GET_MODE_CLASS (GET_MODE (trueop0)) == MODE_FLOAT)
1944 REAL_VALUE_TYPE d0, d1;
1946 REAL_VALUE_FROM_CONST_DOUBLE (d0, trueop0);
1947 REAL_VALUE_FROM_CONST_DOUBLE (d1, trueop1);
1949 /* Comparisons are unordered iff at least one of the values is NaN. */
1950 if (REAL_VALUE_ISNAN (d0) || REAL_VALUE_ISNAN (d1))
1960 return const_true_rtx;
1973 equal = REAL_VALUES_EQUAL (d0, d1);
1974 op0lt = op0ltu = REAL_VALUES_LESS (d0, d1);
1975 op1lt = op1ltu = REAL_VALUES_LESS (d1, d0);
1978 /* Otherwise, see if the operands are both integers. */
1979 else if ((GET_MODE_CLASS (mode) == MODE_INT || mode == VOIDmode)
1980 && (GET_CODE (trueop0) == CONST_DOUBLE
1981 || GET_CODE (trueop0) == CONST_INT)
1982 && (GET_CODE (trueop1) == CONST_DOUBLE
1983 || GET_CODE (trueop1) == CONST_INT))
1985 int width = GET_MODE_BITSIZE (mode);
1986 HOST_WIDE_INT l0s, h0s, l1s, h1s;
1987 unsigned HOST_WIDE_INT l0u, h0u, l1u, h1u;
1989 /* Get the two words comprising each integer constant. */
1990 if (GET_CODE (trueop0) == CONST_DOUBLE)
1992 l0u = l0s = CONST_DOUBLE_LOW (trueop0);
1993 h0u = h0s = CONST_DOUBLE_HIGH (trueop0);
1997 l0u = l0s = INTVAL (trueop0);
1998 h0u = h0s = HWI_SIGN_EXTEND (l0s);
2001 if (GET_CODE (trueop1) == CONST_DOUBLE)
2003 l1u = l1s = CONST_DOUBLE_LOW (trueop1);
2004 h1u = h1s = CONST_DOUBLE_HIGH (trueop1);
2008 l1u = l1s = INTVAL (trueop1);
2009 h1u = h1s = HWI_SIGN_EXTEND (l1s);
2012 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
2013 we have to sign or zero-extend the values. */
2014 if (width != 0 && width < HOST_BITS_PER_WIDE_INT)
2016 l0u &= ((HOST_WIDE_INT) 1 << width) - 1;
2017 l1u &= ((HOST_WIDE_INT) 1 << width) - 1;
2019 if (l0s & ((HOST_WIDE_INT) 1 << (width - 1)))
2020 l0s |= ((HOST_WIDE_INT) (-1) << width);
2022 if (l1s & ((HOST_WIDE_INT) 1 << (width - 1)))
2023 l1s |= ((HOST_WIDE_INT) (-1) << width);
2025 if (width != 0 && width <= HOST_BITS_PER_WIDE_INT)
2026 h0u = h1u = 0, h0s = HWI_SIGN_EXTEND (l0s), h1s = HWI_SIGN_EXTEND (l1s);
2028 equal = (h0u == h1u && l0u == l1u);
2029 op0lt = (h0s < h1s || (h0s == h1s && l0u < l1u));
2030 op1lt = (h1s < h0s || (h1s == h0s && l1u < l0u));
2031 op0ltu = (h0u < h1u || (h0u == h1u && l0u < l1u));
2032 op1ltu = (h1u < h0u || (h1u == h0u && l1u < l0u));
2035 /* Otherwise, there are some code-specific tests we can make. */
2041 /* References to the frame plus a constant or labels cannot
2042 be zero, but a SYMBOL_REF can due to #pragma weak. */
2043 if (((NONZERO_BASE_PLUS_P (op0) && trueop1 == const0_rtx)
2044 || GET_CODE (trueop0) == LABEL_REF)
2045 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2046 /* On some machines, the ap reg can be 0 sometimes. */
2047 && op0 != arg_pointer_rtx
2054 if (((NONZERO_BASE_PLUS_P (op0) && trueop1 == const0_rtx)
2055 || GET_CODE (trueop0) == LABEL_REF)
2056 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2057 && op0 != arg_pointer_rtx
2060 return const_true_rtx;
2064 /* Unsigned values are never negative. */
2065 if (trueop1 == const0_rtx)
2066 return const_true_rtx;
2070 if (trueop1 == const0_rtx)
2075 /* Unsigned values are never greater than the largest
2077 if (GET_CODE (trueop1) == CONST_INT
2078 && (unsigned HOST_WIDE_INT) INTVAL (trueop1) == GET_MODE_MASK (mode)
2079 && INTEGRAL_MODE_P (mode))
2080 return const_true_rtx;
2084 if (GET_CODE (trueop1) == CONST_INT
2085 && (unsigned HOST_WIDE_INT) INTVAL (trueop1) == GET_MODE_MASK (mode)
2086 && INTEGRAL_MODE_P (mode))
2091 /* Optimize abs(x) < 0.0. */
2092 if (trueop1 == CONST0_RTX (mode) && !HONOR_SNANS (mode))
2094 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
2096 if (GET_CODE (tem) == ABS)
2102 /* Optimize abs(x) >= 0.0. */
2103 if (trueop1 == CONST0_RTX (mode) && !HONOR_NANS (mode))
2105 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
2107 if (GET_CODE (tem) == ABS)
2119 /* If we reach here, EQUAL, OP0LT, OP0LTU, OP1LT, and OP1LTU are set
2125 return equal ? const_true_rtx : const0_rtx;
2128 return ! equal ? const_true_rtx : const0_rtx;
2131 return op0lt ? const_true_rtx : const0_rtx;
2134 return op1lt ? const_true_rtx : const0_rtx;
2136 return op0ltu ? const_true_rtx : const0_rtx;
2138 return op1ltu ? const_true_rtx : const0_rtx;
2141 return equal || op0lt ? const_true_rtx : const0_rtx;
2144 return equal || op1lt ? const_true_rtx : const0_rtx;
2146 return equal || op0ltu ? const_true_rtx : const0_rtx;
2148 return equal || op1ltu ? const_true_rtx : const0_rtx;
2150 return const_true_rtx;
2158 /* Simplify CODE, an operation with result mode MODE and three operands,
2159 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
2160 a constant. Return 0 if no simplifications is possible. */
2163 simplify_ternary_operation (code, mode, op0_mode, op0, op1, op2)
2165 enum machine_mode mode, op0_mode;
2168 unsigned int width = GET_MODE_BITSIZE (mode);
2170 /* VOIDmode means "infinite" precision. */
2172 width = HOST_BITS_PER_WIDE_INT;
2178 if (GET_CODE (op0) == CONST_INT
2179 && GET_CODE (op1) == CONST_INT
2180 && GET_CODE (op2) == CONST_INT
2181 && ((unsigned) INTVAL (op1) + (unsigned) INTVAL (op2) <= width)
2182 && width <= (unsigned) HOST_BITS_PER_WIDE_INT)
2184 /* Extracting a bit-field from a constant */
2185 HOST_WIDE_INT val = INTVAL (op0);
2187 if (BITS_BIG_ENDIAN)
2188 val >>= (GET_MODE_BITSIZE (op0_mode)
2189 - INTVAL (op2) - INTVAL (op1));
2191 val >>= INTVAL (op2);
2193 if (HOST_BITS_PER_WIDE_INT != INTVAL (op1))
2195 /* First zero-extend. */
2196 val &= ((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1;
2197 /* If desired, propagate sign bit. */
2198 if (code == SIGN_EXTRACT
2199 && (val & ((HOST_WIDE_INT) 1 << (INTVAL (op1) - 1))))
2200 val |= ~ (((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1);
2203 /* Clear the bits that don't belong in our mode,
2204 unless they and our sign bit are all one.
2205 So we get either a reasonable negative value or a reasonable
2206 unsigned value for this mode. */
2207 if (width < HOST_BITS_PER_WIDE_INT
2208 && ((val & ((HOST_WIDE_INT) (-1) << (width - 1)))
2209 != ((HOST_WIDE_INT) (-1) << (width - 1))))
2210 val &= ((HOST_WIDE_INT) 1 << width) - 1;
2212 return GEN_INT (val);
2217 if (GET_CODE (op0) == CONST_INT)
2218 return op0 != const0_rtx ? op1 : op2;
2220 /* Convert a == b ? b : a to "a". */
2221 if (GET_CODE (op0) == NE && ! side_effects_p (op0)
2222 && !HONOR_NANS (mode)
2223 && rtx_equal_p (XEXP (op0, 0), op1)
2224 && rtx_equal_p (XEXP (op0, 1), op2))
2226 else if (GET_CODE (op0) == EQ && ! side_effects_p (op0)
2227 && !HONOR_NANS (mode)
2228 && rtx_equal_p (XEXP (op0, 1), op1)
2229 && rtx_equal_p (XEXP (op0, 0), op2))
2231 else if (GET_RTX_CLASS (GET_CODE (op0)) == '<' && ! side_effects_p (op0))
2233 enum machine_mode cmp_mode = (GET_MODE (XEXP (op0, 0)) == VOIDmode
2234 ? GET_MODE (XEXP (op0, 1))
2235 : GET_MODE (XEXP (op0, 0)));
2237 if (cmp_mode == VOIDmode)
2238 cmp_mode = op0_mode;
2239 temp = simplify_relational_operation (GET_CODE (op0), cmp_mode,
2240 XEXP (op0, 0), XEXP (op0, 1));
2242 /* See if any simplifications were possible. */
2243 if (temp == const0_rtx)
2245 else if (temp == const1_rtx)
2250 /* Look for happy constants in op1 and op2. */
2251 if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
2253 HOST_WIDE_INT t = INTVAL (op1);
2254 HOST_WIDE_INT f = INTVAL (op2);
2256 if (t == STORE_FLAG_VALUE && f == 0)
2257 code = GET_CODE (op0);
2258 else if (t == 0 && f == STORE_FLAG_VALUE)
2261 tmp = reversed_comparison_code (op0, NULL_RTX);
2269 return gen_rtx_fmt_ee (code, mode, XEXP (op0, 0), XEXP (op0, 1));
2281 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
2282 Return 0 if no simplifications is possible. */
2284 simplify_subreg (outermode, op, innermode, byte)
2287 enum machine_mode outermode, innermode;
2289 /* Little bit of sanity checking. */
2290 if (innermode == VOIDmode || outermode == VOIDmode
2291 || innermode == BLKmode || outermode == BLKmode)
2294 if (GET_MODE (op) != innermode
2295 && GET_MODE (op) != VOIDmode)
2298 if (byte % GET_MODE_SIZE (outermode)
2299 || byte >= GET_MODE_SIZE (innermode))
2302 if (outermode == innermode && !byte)
2305 /* Simplify subregs of vector constants. */
2306 if (GET_CODE (op) == CONST_VECTOR)
2308 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (innermode));
2309 const unsigned int offset = byte / elt_size;
2312 if (GET_MODE_INNER (innermode) == outermode)
2314 elt = CONST_VECTOR_ELT (op, offset);
2316 /* ?? We probably don't need this copy_rtx because constants
2317 can be shared. ?? */
2319 return copy_rtx (elt);
2321 else if (GET_MODE_INNER (innermode) == GET_MODE_INNER (outermode)
2322 && GET_MODE_SIZE (innermode) > GET_MODE_SIZE (outermode))
2324 return (gen_rtx_CONST_VECTOR
2326 gen_rtvec_v (GET_MODE_NUNITS (outermode),
2327 &CONST_VECTOR_ELT (op, offset))));
2329 else if (GET_MODE_CLASS (outermode) == MODE_INT
2330 && (GET_MODE_SIZE (outermode) % elt_size == 0))
2332 /* This happens when the target register size is smaller then
2333 the vector mode, and we synthesize operations with vectors
2334 of elements that are smaller than the register size. */
2335 HOST_WIDE_INT sum = 0, high = 0;
2336 unsigned n_elts = (GET_MODE_SIZE (outermode) / elt_size);
2337 unsigned i = BYTES_BIG_ENDIAN ? offset : offset + n_elts - 1;
2338 unsigned step = BYTES_BIG_ENDIAN ? 1 : -1;
2339 int shift = BITS_PER_UNIT * elt_size;
2341 for (; n_elts--; i += step)
2343 elt = CONST_VECTOR_ELT (op, i);
2344 if (GET_CODE (elt) == CONST_DOUBLE
2345 && GET_MODE_CLASS (GET_MODE (elt)) == MODE_FLOAT)
2347 elt = gen_lowpart_common (int_mode_for_mode (GET_MODE (elt)),
2352 if (GET_CODE (elt) != CONST_INT)
2354 high = high << shift | sum >> (HOST_BITS_PER_WIDE_INT - shift);
2355 sum = (sum << shift) + INTVAL (elt);
2357 if (GET_MODE_BITSIZE (outermode) <= HOST_BITS_PER_WIDE_INT)
2358 return GEN_INT (trunc_int_for_mode (sum, outermode));
2359 else if (GET_MODE_BITSIZE (outermode) == 2* HOST_BITS_PER_WIDE_INT)
2360 return immed_double_const (high, sum, outermode);
2364 else if (GET_MODE_CLASS (outermode) == MODE_INT
2365 && (elt_size % GET_MODE_SIZE (outermode) == 0))
2367 enum machine_mode new_mode
2368 = int_mode_for_mode (GET_MODE_INNER (innermode));
2369 int subbyte = byte % elt_size;
2371 op = simplify_subreg (new_mode, op, innermode, byte - subbyte);
2374 return simplify_subreg (outermode, op, new_mode, subbyte);
2376 else if (GET_MODE_CLASS (outermode) == MODE_INT)
2377 /* This shouldn't happen, but let's not do anything stupid. */
2381 /* Attempt to simplify constant to non-SUBREG expression. */
2382 if (CONSTANT_P (op))
2385 unsigned HOST_WIDE_INT val = 0;
2387 if (GET_MODE_CLASS (outermode) == MODE_VECTOR_INT
2388 || GET_MODE_CLASS (outermode) == MODE_VECTOR_FLOAT)
2390 /* Construct a CONST_VECTOR from individual subregs. */
2391 enum machine_mode submode = GET_MODE_INNER (outermode);
2392 int subsize = GET_MODE_UNIT_SIZE (outermode);
2393 int i, elts = GET_MODE_NUNITS (outermode);
2394 rtvec v = rtvec_alloc (elts);
2397 for (i = 0; i < elts; i++, byte += subsize)
2399 /* This might fail, e.g. if taking a subreg from a SYMBOL_REF. */
2400 /* ??? It would be nice if we could actually make such subregs
2401 on targets that allow such relocations. */
2402 if (byte >= GET_MODE_UNIT_SIZE (innermode))
2403 elt = CONST0_RTX (submode);
2405 elt = simplify_subreg (submode, op, innermode, byte);
2408 RTVEC_ELT (v, i) = elt;
2410 return gen_rtx_CONST_VECTOR (outermode, v);
2413 /* ??? This code is partly redundant with code below, but can handle
2414 the subregs of floats and similar corner cases.
2415 Later it we should move all simplification code here and rewrite
2416 GEN_LOWPART_IF_POSSIBLE, GEN_HIGHPART, OPERAND_SUBWORD and friends
2417 using SIMPLIFY_SUBREG. */
2418 if (subreg_lowpart_offset (outermode, innermode) == byte
2419 && GET_CODE (op) != CONST_VECTOR)
2421 rtx new = gen_lowpart_if_possible (outermode, op);
2426 /* Similar comment as above apply here. */
2427 if (GET_MODE_SIZE (outermode) == UNITS_PER_WORD
2428 && GET_MODE_SIZE (innermode) > UNITS_PER_WORD
2429 && GET_MODE_CLASS (outermode) == MODE_INT)
2431 rtx new = constant_subword (op,
2432 (byte / UNITS_PER_WORD),
2438 if (GET_MODE_CLASS (outermode) != MODE_INT
2439 && GET_MODE_CLASS (outermode) != MODE_CC)
2441 enum machine_mode new_mode = int_mode_for_mode (outermode);
2443 if (new_mode != innermode || byte != 0)
2445 op = simplify_subreg (new_mode, op, innermode, byte);
2448 return simplify_subreg (outermode, op, new_mode, 0);
2452 offset = byte * BITS_PER_UNIT;
2453 switch (GET_CODE (op))
2456 if (GET_MODE (op) != VOIDmode)
2459 /* We can't handle this case yet. */
2460 if (GET_MODE_BITSIZE (outermode) >= HOST_BITS_PER_WIDE_INT)
2463 part = offset >= HOST_BITS_PER_WIDE_INT;
2464 if ((BITS_PER_WORD > HOST_BITS_PER_WIDE_INT
2465 && BYTES_BIG_ENDIAN)
2466 || (BITS_PER_WORD <= HOST_BITS_PER_WIDE_INT
2467 && WORDS_BIG_ENDIAN))
2469 val = part ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op);
2470 offset %= HOST_BITS_PER_WIDE_INT;
2472 /* We've already picked the word we want from a double, so
2473 pretend this is actually an integer. */
2474 innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
2478 if (GET_CODE (op) == CONST_INT)
2481 /* We don't handle synthetizing of non-integral constants yet. */
2482 if (GET_MODE_CLASS (outermode) != MODE_INT)
2485 if (BYTES_BIG_ENDIAN || WORDS_BIG_ENDIAN)
2487 if (WORDS_BIG_ENDIAN)
2488 offset = (GET_MODE_BITSIZE (innermode)
2489 - GET_MODE_BITSIZE (outermode) - offset);
2490 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN
2491 && GET_MODE_SIZE (outermode) < UNITS_PER_WORD)
2492 offset = (offset + BITS_PER_WORD - GET_MODE_BITSIZE (outermode)
2493 - 2 * (offset % BITS_PER_WORD));
2496 if (offset >= HOST_BITS_PER_WIDE_INT)
2497 return ((HOST_WIDE_INT) val < 0) ? constm1_rtx : const0_rtx;
2501 if (GET_MODE_BITSIZE (outermode) < HOST_BITS_PER_WIDE_INT)
2502 val = trunc_int_for_mode (val, outermode);
2503 return GEN_INT (val);
2510 /* Changing mode twice with SUBREG => just change it once,
2511 or not at all if changing back op starting mode. */
2512 if (GET_CODE (op) == SUBREG)
2514 enum machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
2515 int final_offset = byte + SUBREG_BYTE (op);
2518 if (outermode == innermostmode
2519 && byte == 0 && SUBREG_BYTE (op) == 0)
2520 return SUBREG_REG (op);
2522 /* The SUBREG_BYTE represents offset, as if the value were stored
2523 in memory. Irritating exception is paradoxical subreg, where
2524 we define SUBREG_BYTE to be 0. On big endian machines, this
2525 value should be negative. For a moment, undo this exception. */
2526 if (byte == 0 && GET_MODE_SIZE (innermode) < GET_MODE_SIZE (outermode))
2528 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
2529 if (WORDS_BIG_ENDIAN)
2530 final_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
2531 if (BYTES_BIG_ENDIAN)
2532 final_offset += difference % UNITS_PER_WORD;
2534 if (SUBREG_BYTE (op) == 0
2535 && GET_MODE_SIZE (innermostmode) < GET_MODE_SIZE (innermode))
2537 int difference = (GET_MODE_SIZE (innermostmode) - GET_MODE_SIZE (innermode));
2538 if (WORDS_BIG_ENDIAN)
2539 final_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
2540 if (BYTES_BIG_ENDIAN)
2541 final_offset += difference % UNITS_PER_WORD;
2544 /* See whether resulting subreg will be paradoxical. */
2545 if (GET_MODE_SIZE (innermostmode) > GET_MODE_SIZE (outermode))
2547 /* In nonparadoxical subregs we can't handle negative offsets. */
2548 if (final_offset < 0)
2550 /* Bail out in case resulting subreg would be incorrect. */
2551 if (final_offset % GET_MODE_SIZE (outermode)
2552 || (unsigned) final_offset >= GET_MODE_SIZE (innermostmode))
2558 int difference = (GET_MODE_SIZE (innermostmode) - GET_MODE_SIZE (outermode));
2560 /* In paradoxical subreg, see if we are still looking on lower part.
2561 If so, our SUBREG_BYTE will be 0. */
2562 if (WORDS_BIG_ENDIAN)
2563 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
2564 if (BYTES_BIG_ENDIAN)
2565 offset += difference % UNITS_PER_WORD;
2566 if (offset == final_offset)
2572 /* Recurse for futher possible simplifications. */
2573 new = simplify_subreg (outermode, SUBREG_REG (op),
2574 GET_MODE (SUBREG_REG (op)),
2578 return gen_rtx_SUBREG (outermode, SUBREG_REG (op), final_offset);
2581 /* SUBREG of a hard register => just change the register number
2582 and/or mode. If the hard register is not valid in that mode,
2583 suppress this simplification. If the hard register is the stack,
2584 frame, or argument pointer, leave this as a SUBREG. */
2587 && (! REG_FUNCTION_VALUE_P (op)
2588 || ! rtx_equal_function_value_matters)
2589 && REGNO (op) < FIRST_PSEUDO_REGISTER
2590 #ifdef CANNOT_CHANGE_MODE_CLASS
2591 && ! (REG_CANNOT_CHANGE_MODE_P (REGNO (op), outermode, innermode)
2592 && GET_MODE_CLASS (innermode) != MODE_COMPLEX_INT
2593 && GET_MODE_CLASS (innermode) != MODE_COMPLEX_FLOAT)
2595 && ((reload_completed && !frame_pointer_needed)
2596 || (REGNO (op) != FRAME_POINTER_REGNUM
2597 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2598 && REGNO (op) != HARD_FRAME_POINTER_REGNUM
2601 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2602 && REGNO (op) != ARG_POINTER_REGNUM
2604 && REGNO (op) != STACK_POINTER_REGNUM)
2606 int final_regno = subreg_hard_regno (gen_rtx_SUBREG (outermode, op, byte),
2609 /* ??? We do allow it if the current REG is not valid for
2610 its mode. This is a kludge to work around how float/complex
2611 arguments are passed on 32-bit SPARC and should be fixed. */
2612 if (HARD_REGNO_MODE_OK (final_regno, outermode)
2613 || ! HARD_REGNO_MODE_OK (REGNO (op), innermode))
2615 rtx x = gen_rtx_REG (outermode, final_regno);
2617 /* Propagate original regno. We don't have any way to specify
2618 the offset inside orignal regno, so do so only for lowpart.
2619 The information is used only by alias analysis that can not
2620 grog partial register anyway. */
2622 if (subreg_lowpart_offset (outermode, innermode) == byte)
2623 ORIGINAL_REGNO (x) = ORIGINAL_REGNO (op);
2628 /* If we have a SUBREG of a register that we are replacing and we are
2629 replacing it with a MEM, make a new MEM and try replacing the
2630 SUBREG with it. Don't do this if the MEM has a mode-dependent address
2631 or if we would be widening it. */
2633 if (GET_CODE (op) == MEM
2634 && ! mode_dependent_address_p (XEXP (op, 0))
2635 /* Allow splitting of volatile memory references in case we don't
2636 have instruction to move the whole thing. */
2637 && (! MEM_VOLATILE_P (op)
2638 || ! have_insn_for (SET, innermode))
2639 && GET_MODE_SIZE (outermode) <= GET_MODE_SIZE (GET_MODE (op)))
2640 return adjust_address_nv (op, outermode, byte);
2642 /* Handle complex values represented as CONCAT
2643 of real and imaginary part. */
2644 if (GET_CODE (op) == CONCAT)
2646 int is_realpart = byte < GET_MODE_UNIT_SIZE (innermode);
2647 rtx part = is_realpart ? XEXP (op, 0) : XEXP (op, 1);
2648 unsigned int final_offset;
2651 final_offset = byte % (GET_MODE_UNIT_SIZE (innermode));
2652 res = simplify_subreg (outermode, part, GET_MODE (part), final_offset);
2655 /* We can at least simplify it by referring directly to the relevant part. */
2656 return gen_rtx_SUBREG (outermode, part, final_offset);
2661 /* Make a SUBREG operation or equivalent if it folds. */
2664 simplify_gen_subreg (outermode, op, innermode, byte)
2667 enum machine_mode outermode, innermode;
2670 /* Little bit of sanity checking. */
2671 if (innermode == VOIDmode || outermode == VOIDmode
2672 || innermode == BLKmode || outermode == BLKmode)
2675 if (GET_MODE (op) != innermode
2676 && GET_MODE (op) != VOIDmode)
2679 if (byte % GET_MODE_SIZE (outermode)
2680 || byte >= GET_MODE_SIZE (innermode))
2683 if (GET_CODE (op) == QUEUED)
2686 new = simplify_subreg (outermode, op, innermode, byte);
2690 if (GET_CODE (op) == SUBREG || GET_MODE (op) == VOIDmode)
2693 return gen_rtx_SUBREG (outermode, op, byte);
2695 /* Simplify X, an rtx expression.
2697 Return the simplified expression or NULL if no simplifications
2700 This is the preferred entry point into the simplification routines;
2701 however, we still allow passes to call the more specific routines.
2703 Right now GCC has three (yes, three) major bodies of RTL simplficiation
2704 code that need to be unified.
2706 1. fold_rtx in cse.c. This code uses various CSE specific
2707 information to aid in RTL simplification.
2709 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
2710 it uses combine specific information to aid in RTL
2713 3. The routines in this file.
2716 Long term we want to only have one body of simplification code; to
2717 get to that state I recommend the following steps:
2719 1. Pour over fold_rtx & simplify_rtx and move any simplifications
2720 which are not pass dependent state into these routines.
2722 2. As code is moved by #1, change fold_rtx & simplify_rtx to
2723 use this routine whenever possible.
2725 3. Allow for pass dependent state to be provided to these
2726 routines and add simplifications based on the pass dependent
2727 state. Remove code from cse.c & combine.c that becomes
2730 It will take time, but ultimately the compiler will be easier to
2731 maintain and improve. It's totally silly that when we add a
2732 simplification that it needs to be added to 4 places (3 for RTL
2733 simplification and 1 for tree simplification. */
2739 enum rtx_code code = GET_CODE (x);
2740 enum machine_mode mode = GET_MODE (x);
2742 switch (GET_RTX_CLASS (code))
2745 return simplify_unary_operation (code, mode,
2746 XEXP (x, 0), GET_MODE (XEXP (x, 0)));
2748 if (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
2753 XEXP (x, 0) = XEXP (x, 1);
2755 return simplify_binary_operation (code, mode,
2756 XEXP (x, 0), XEXP (x, 1));
2760 return simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2764 return simplify_ternary_operation (code, mode, GET_MODE (XEXP (x, 0)),
2765 XEXP (x, 0), XEXP (x, 1),
2769 return simplify_relational_operation (code,
2770 ((GET_MODE (XEXP (x, 0))
2772 ? GET_MODE (XEXP (x, 0))
2773 : GET_MODE (XEXP (x, 1))),
2774 XEXP (x, 0), XEXP (x, 1));
2776 /* The only case we try to handle is a SUBREG. */
2778 return simplify_gen_subreg (mode, SUBREG_REG (x),
2779 GET_MODE (SUBREG_REG (x)),