1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
34 #include "insn-config.h"
43 /* Simplification and canonicalization of RTL. */
45 /* Much code operates on (low, high) pairs; the low value is an
46 unsigned wide int, the high value a signed wide int. We
47 occasionally need to sign extend from low to high as if low were a
49 #define HWI_SIGN_EXTEND(low) \
50 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
52 static rtx neg_const_int (enum machine_mode, rtx);
53 static bool mode_signbit_p (enum machine_mode, rtx);
54 static int simplify_plus_minus_op_data_cmp (const void *, const void *);
55 static rtx simplify_plus_minus (enum rtx_code, enum machine_mode, rtx,
57 static rtx simplify_immed_subreg (enum machine_mode, rtx, enum machine_mode,
59 static rtx simplify_associative_operation (enum rtx_code, enum machine_mode,
61 static rtx simplify_relational_operation_1 (enum rtx_code, enum machine_mode,
62 enum machine_mode, rtx, rtx);
64 /* Negate a CONST_INT rtx, truncating (because a conversion from a
65 maximally negative number can overflow). */
67 neg_const_int (enum machine_mode mode, rtx i)
69 return gen_int_mode (- INTVAL (i), mode);
72 /* Test whether expression, X, is an immediate constant that represents
73 the most significant bit of machine mode MODE. */
76 mode_signbit_p (enum machine_mode mode, rtx x)
78 unsigned HOST_WIDE_INT val;
81 if (GET_MODE_CLASS (mode) != MODE_INT)
84 width = GET_MODE_BITSIZE (mode);
88 if (width <= HOST_BITS_PER_WIDE_INT
89 && GET_CODE (x) == CONST_INT)
91 else if (width <= 2 * HOST_BITS_PER_WIDE_INT
92 && GET_CODE (x) == CONST_DOUBLE
93 && CONST_DOUBLE_LOW (x) == 0)
95 val = CONST_DOUBLE_HIGH (x);
96 width -= HOST_BITS_PER_WIDE_INT;
101 if (width < HOST_BITS_PER_WIDE_INT)
102 val &= ((unsigned HOST_WIDE_INT) 1 << width) - 1;
103 return val == ((unsigned HOST_WIDE_INT) 1 << (width - 1));
106 /* Make a binary operation by properly ordering the operands and
107 seeing if the expression folds. */
110 simplify_gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0,
115 /* Put complex operands first and constants second if commutative. */
116 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
117 && swap_commutative_operands_p (op0, op1))
118 tem = op0, op0 = op1, op1 = tem;
120 /* If this simplifies, do it. */
121 tem = simplify_binary_operation (code, mode, op0, op1);
125 /* Handle addition and subtraction specially. Otherwise, just form
128 if (code == PLUS || code == MINUS)
130 tem = simplify_plus_minus (code, mode, op0, op1, 1);
135 return gen_rtx_fmt_ee (code, mode, op0, op1);
138 /* If X is a MEM referencing the constant pool, return the real value.
139 Otherwise return X. */
141 avoid_constant_pool_reference (rtx x)
144 enum machine_mode cmode;
146 switch (GET_CODE (x))
152 /* Handle float extensions of constant pool references. */
154 c = avoid_constant_pool_reference (tmp);
155 if (c != tmp && GET_CODE (c) == CONST_DOUBLE)
159 REAL_VALUE_FROM_CONST_DOUBLE (d, c);
160 return CONST_DOUBLE_FROM_REAL_VALUE (d, GET_MODE (x));
170 /* Call target hook to avoid the effects of -fpic etc.... */
171 addr = targetm.delegitimize_address (addr);
173 if (GET_CODE (addr) == LO_SUM)
174 addr = XEXP (addr, 1);
176 if (GET_CODE (addr) != SYMBOL_REF
177 || ! CONSTANT_POOL_ADDRESS_P (addr))
180 c = get_pool_constant (addr);
181 cmode = get_pool_mode (addr);
183 /* If we're accessing the constant in a different mode than it was
184 originally stored, attempt to fix that up via subreg simplifications.
185 If that fails we have no choice but to return the original memory. */
186 if (cmode != GET_MODE (x))
188 c = simplify_subreg (GET_MODE (x), c, cmode, 0);
195 /* Make a unary operation by first seeing if it folds and otherwise making
196 the specified operation. */
199 simplify_gen_unary (enum rtx_code code, enum machine_mode mode, rtx op,
200 enum machine_mode op_mode)
204 /* If this simplifies, use it. */
205 if ((tem = simplify_unary_operation (code, mode, op, op_mode)) != 0)
208 return gen_rtx_fmt_e (code, mode, op);
211 /* Likewise for ternary operations. */
214 simplify_gen_ternary (enum rtx_code code, enum machine_mode mode,
215 enum machine_mode op0_mode, rtx op0, rtx op1, rtx op2)
219 /* If this simplifies, use it. */
220 if (0 != (tem = simplify_ternary_operation (code, mode, op0_mode,
224 return gen_rtx_fmt_eee (code, mode, op0, op1, op2);
227 /* Likewise, for relational operations.
228 CMP_MODE specifies mode comparison is done in. */
231 simplify_gen_relational (enum rtx_code code, enum machine_mode mode,
232 enum machine_mode cmp_mode, rtx op0, rtx op1)
236 if (0 != (tem = simplify_relational_operation (code, mode, cmp_mode,
240 return gen_rtx_fmt_ee (code, mode, op0, op1);
243 /* Replace all occurrences of OLD in X with NEW and try to simplify the
244 resulting RTX. Return a new RTX which is as simplified as possible. */
247 simplify_replace_rtx (rtx x, rtx old, rtx new)
249 enum rtx_code code = GET_CODE (x);
250 enum machine_mode mode = GET_MODE (x);
251 enum machine_mode op_mode;
254 /* If X is OLD, return NEW. Otherwise, if this is an expression, try
255 to build a new expression substituting recursively. If we can't do
256 anything, return our input. */
261 switch (GET_RTX_CLASS (code))
265 op_mode = GET_MODE (op0);
266 op0 = simplify_replace_rtx (op0, old, new);
267 if (op0 == XEXP (x, 0))
269 return simplify_gen_unary (code, mode, op0, op_mode);
273 op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
274 op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
275 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
277 return simplify_gen_binary (code, mode, op0, op1);
280 case RTX_COMM_COMPARE:
283 op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
284 op0 = simplify_replace_rtx (op0, old, new);
285 op1 = simplify_replace_rtx (op1, old, new);
286 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
288 return simplify_gen_relational (code, mode, op_mode, op0, op1);
291 case RTX_BITFIELD_OPS:
293 op_mode = GET_MODE (op0);
294 op0 = simplify_replace_rtx (op0, old, new);
295 op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
296 op2 = simplify_replace_rtx (XEXP (x, 2), old, new);
297 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2))
299 if (op_mode == VOIDmode)
300 op_mode = GET_MODE (op0);
301 return simplify_gen_ternary (code, mode, op_mode, op0, op1, op2);
304 /* The only case we try to handle is a SUBREG. */
307 op0 = simplify_replace_rtx (SUBREG_REG (x), old, new);
308 if (op0 == SUBREG_REG (x))
310 op0 = simplify_gen_subreg (GET_MODE (x), op0,
311 GET_MODE (SUBREG_REG (x)),
313 return op0 ? op0 : x;
320 op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
321 if (op0 == XEXP (x, 0))
323 return replace_equiv_address_nv (x, op0);
325 else if (code == LO_SUM)
327 op0 = simplify_replace_rtx (XEXP (x, 0), old, new);
328 op1 = simplify_replace_rtx (XEXP (x, 1), old, new);
330 /* (lo_sum (high x) x) -> x */
331 if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1))
334 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
336 return gen_rtx_LO_SUM (mode, op0, op1);
338 else if (code == REG)
340 if (REG_P (old) && REGNO (x) == REGNO (old))
351 /* Try to simplify a unary operation CODE whose output mode is to be
352 MODE with input operand OP whose mode was originally OP_MODE.
353 Return zero if no simplification can be made. */
355 simplify_unary_operation (enum rtx_code code, enum machine_mode mode,
356 rtx op, enum machine_mode op_mode)
358 unsigned int width = GET_MODE_BITSIZE (mode);
359 rtx trueop = avoid_constant_pool_reference (op);
361 if (code == VEC_DUPLICATE)
363 if (!VECTOR_MODE_P (mode))
365 if (GET_MODE (trueop) != VOIDmode
366 && !VECTOR_MODE_P (GET_MODE (trueop))
367 && GET_MODE_INNER (mode) != GET_MODE (trueop))
369 if (GET_MODE (trueop) != VOIDmode
370 && VECTOR_MODE_P (GET_MODE (trueop))
371 && GET_MODE_INNER (mode) != GET_MODE_INNER (GET_MODE (trueop)))
373 if (GET_CODE (trueop) == CONST_INT || GET_CODE (trueop) == CONST_DOUBLE
374 || GET_CODE (trueop) == CONST_VECTOR)
376 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
377 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
378 rtvec v = rtvec_alloc (n_elts);
381 if (GET_CODE (trueop) != CONST_VECTOR)
382 for (i = 0; i < n_elts; i++)
383 RTVEC_ELT (v, i) = trueop;
386 enum machine_mode inmode = GET_MODE (trueop);
387 int in_elt_size = GET_MODE_SIZE (GET_MODE_INNER (inmode));
388 unsigned in_n_elts = (GET_MODE_SIZE (inmode) / in_elt_size);
390 if (in_n_elts >= n_elts || n_elts % in_n_elts)
392 for (i = 0; i < n_elts; i++)
393 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop, i % in_n_elts);
395 return gen_rtx_CONST_VECTOR (mode, v);
398 else if (GET_CODE (op) == CONST)
399 return simplify_unary_operation (code, mode, XEXP (op, 0), op_mode);
401 if (VECTOR_MODE_P (mode) && GET_CODE (trueop) == CONST_VECTOR)
403 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
404 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
405 enum machine_mode opmode = GET_MODE (trueop);
406 int op_elt_size = GET_MODE_SIZE (GET_MODE_INNER (opmode));
407 unsigned op_n_elts = (GET_MODE_SIZE (opmode) / op_elt_size);
408 rtvec v = rtvec_alloc (n_elts);
411 if (op_n_elts != n_elts)
414 for (i = 0; i < n_elts; i++)
416 rtx x = simplify_unary_operation (code, GET_MODE_INNER (mode),
417 CONST_VECTOR_ELT (trueop, i),
418 GET_MODE_INNER (opmode));
421 RTVEC_ELT (v, i) = x;
423 return gen_rtx_CONST_VECTOR (mode, v);
426 /* The order of these tests is critical so that, for example, we don't
427 check the wrong mode (input vs. output) for a conversion operation,
428 such as FIX. At some point, this should be simplified. */
430 if (code == FLOAT && GET_MODE (trueop) == VOIDmode
431 && (GET_CODE (trueop) == CONST_DOUBLE || GET_CODE (trueop) == CONST_INT))
433 HOST_WIDE_INT hv, lv;
436 if (GET_CODE (trueop) == CONST_INT)
437 lv = INTVAL (trueop), hv = HWI_SIGN_EXTEND (lv);
439 lv = CONST_DOUBLE_LOW (trueop), hv = CONST_DOUBLE_HIGH (trueop);
441 REAL_VALUE_FROM_INT (d, lv, hv, mode);
442 d = real_value_truncate (mode, d);
443 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
445 else if (code == UNSIGNED_FLOAT && GET_MODE (trueop) == VOIDmode
446 && (GET_CODE (trueop) == CONST_DOUBLE
447 || GET_CODE (trueop) == CONST_INT))
449 HOST_WIDE_INT hv, lv;
452 if (GET_CODE (trueop) == CONST_INT)
453 lv = INTVAL (trueop), hv = HWI_SIGN_EXTEND (lv);
455 lv = CONST_DOUBLE_LOW (trueop), hv = CONST_DOUBLE_HIGH (trueop);
457 if (op_mode == VOIDmode)
459 /* We don't know how to interpret negative-looking numbers in
460 this case, so don't try to fold those. */
464 else if (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT * 2)
467 hv = 0, lv &= GET_MODE_MASK (op_mode);
469 REAL_VALUE_FROM_UNSIGNED_INT (d, lv, hv, mode);
470 d = real_value_truncate (mode, d);
471 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
474 if (GET_CODE (trueop) == CONST_INT
475 && width <= HOST_BITS_PER_WIDE_INT && width > 0)
477 HOST_WIDE_INT arg0 = INTVAL (trueop);
491 val = (arg0 >= 0 ? arg0 : - arg0);
495 /* Don't use ffs here. Instead, get low order bit and then its
496 number. If arg0 is zero, this will return 0, as desired. */
497 arg0 &= GET_MODE_MASK (mode);
498 val = exact_log2 (arg0 & (- arg0)) + 1;
502 arg0 &= GET_MODE_MASK (mode);
503 if (arg0 == 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode, val))
506 val = GET_MODE_BITSIZE (mode) - floor_log2 (arg0) - 1;
510 arg0 &= GET_MODE_MASK (mode);
513 /* Even if the value at zero is undefined, we have to come
514 up with some replacement. Seems good enough. */
515 if (! CTZ_DEFINED_VALUE_AT_ZERO (mode, val))
516 val = GET_MODE_BITSIZE (mode);
519 val = exact_log2 (arg0 & -arg0);
523 arg0 &= GET_MODE_MASK (mode);
526 val++, arg0 &= arg0 - 1;
530 arg0 &= GET_MODE_MASK (mode);
533 val++, arg0 &= arg0 - 1;
542 /* When zero-extending a CONST_INT, we need to know its
544 if (op_mode == VOIDmode)
546 if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT)
548 /* If we were really extending the mode,
549 we would have to distinguish between zero-extension
550 and sign-extension. */
551 if (width != GET_MODE_BITSIZE (op_mode))
555 else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
556 val = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
562 if (op_mode == VOIDmode)
564 if (GET_MODE_BITSIZE (op_mode) == HOST_BITS_PER_WIDE_INT)
566 /* If we were really extending the mode,
567 we would have to distinguish between zero-extension
568 and sign-extension. */
569 if (width != GET_MODE_BITSIZE (op_mode))
573 else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
576 = arg0 & ~((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (op_mode));
578 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (op_mode) - 1)))
579 val -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
596 val = trunc_int_for_mode (val, mode);
598 return GEN_INT (val);
601 /* We can do some operations on integer CONST_DOUBLEs. Also allow
602 for a DImode operation on a CONST_INT. */
603 else if (GET_MODE (trueop) == VOIDmode
604 && width <= HOST_BITS_PER_WIDE_INT * 2
605 && (GET_CODE (trueop) == CONST_DOUBLE
606 || GET_CODE (trueop) == CONST_INT))
608 unsigned HOST_WIDE_INT l1, lv;
609 HOST_WIDE_INT h1, hv;
611 if (GET_CODE (trueop) == CONST_DOUBLE)
612 l1 = CONST_DOUBLE_LOW (trueop), h1 = CONST_DOUBLE_HIGH (trueop);
614 l1 = INTVAL (trueop), h1 = HWI_SIGN_EXTEND (l1);
624 neg_double (l1, h1, &lv, &hv);
629 neg_double (l1, h1, &lv, &hv);
641 lv = HOST_BITS_PER_WIDE_INT + exact_log2 (h1 & -h1) + 1;
644 lv = exact_log2 (l1 & -l1) + 1;
650 lv = GET_MODE_BITSIZE (mode) - floor_log2 (h1) - 1
651 - HOST_BITS_PER_WIDE_INT;
653 lv = GET_MODE_BITSIZE (mode) - floor_log2 (l1) - 1;
654 else if (! CLZ_DEFINED_VALUE_AT_ZERO (mode, lv))
655 lv = GET_MODE_BITSIZE (mode);
661 lv = exact_log2 (l1 & -l1);
663 lv = HOST_BITS_PER_WIDE_INT + exact_log2 (h1 & -h1);
664 else if (! CTZ_DEFINED_VALUE_AT_ZERO (mode, lv))
665 lv = GET_MODE_BITSIZE (mode);
688 /* This is just a change-of-mode, so do nothing. */
693 if (op_mode == VOIDmode)
696 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT)
700 lv = l1 & GET_MODE_MASK (op_mode);
704 if (op_mode == VOIDmode
705 || GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT)
709 lv = l1 & GET_MODE_MASK (op_mode);
710 if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT
711 && (lv & ((HOST_WIDE_INT) 1
712 << (GET_MODE_BITSIZE (op_mode) - 1))) != 0)
713 lv -= (HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (op_mode);
715 hv = HWI_SIGN_EXTEND (lv);
726 return immed_double_const (lv, hv, mode);
729 else if (GET_CODE (trueop) == CONST_DOUBLE
730 && GET_MODE_CLASS (mode) == MODE_FLOAT)
732 REAL_VALUE_TYPE d, t;
733 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop);
738 if (HONOR_SNANS (mode) && real_isnan (&d))
740 real_sqrt (&t, mode, &d);
744 d = REAL_VALUE_ABS (d);
747 d = REAL_VALUE_NEGATE (d);
750 d = real_value_truncate (mode, d);
753 /* All this does is change the mode. */
756 real_arithmetic (&d, FIX_TRUNC_EXPR, &d, NULL);
763 real_to_target (tmp, &d, GET_MODE (trueop));
764 for (i = 0; i < 4; i++)
766 real_from_target (&d, tmp, mode);
771 return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
774 else if (GET_CODE (trueop) == CONST_DOUBLE
775 && GET_MODE_CLASS (GET_MODE (trueop)) == MODE_FLOAT
776 && GET_MODE_CLASS (mode) == MODE_INT
777 && width <= 2*HOST_BITS_PER_WIDE_INT && width > 0)
779 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
780 operators are intentionally left unspecified (to ease implementation
781 by target backends), for consistency, this routine implements the
782 same semantics for constant folding as used by the middle-end. */
784 HOST_WIDE_INT xh, xl, th, tl;
785 REAL_VALUE_TYPE x, t;
786 REAL_VALUE_FROM_CONST_DOUBLE (x, trueop);
790 if (REAL_VALUE_ISNAN (x))
793 /* Test against the signed upper bound. */
794 if (width > HOST_BITS_PER_WIDE_INT)
796 th = ((unsigned HOST_WIDE_INT) 1
797 << (width - HOST_BITS_PER_WIDE_INT - 1)) - 1;
803 tl = ((unsigned HOST_WIDE_INT) 1 << (width - 1)) - 1;
805 real_from_integer (&t, VOIDmode, tl, th, 0);
806 if (REAL_VALUES_LESS (t, x))
813 /* Test against the signed lower bound. */
814 if (width > HOST_BITS_PER_WIDE_INT)
816 th = (HOST_WIDE_INT) -1 << (width - HOST_BITS_PER_WIDE_INT - 1);
822 tl = (HOST_WIDE_INT) -1 << (width - 1);
824 real_from_integer (&t, VOIDmode, tl, th, 0);
825 if (REAL_VALUES_LESS (x, t))
831 REAL_VALUE_TO_INT (&xl, &xh, x);
835 if (REAL_VALUE_ISNAN (x) || REAL_VALUE_NEGATIVE (x))
838 /* Test against the unsigned upper bound. */
839 if (width == 2*HOST_BITS_PER_WIDE_INT)
844 else if (width >= HOST_BITS_PER_WIDE_INT)
846 th = ((unsigned HOST_WIDE_INT) 1
847 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
853 tl = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
855 real_from_integer (&t, VOIDmode, tl, th, 1);
856 if (REAL_VALUES_LESS (t, x))
863 REAL_VALUE_TO_INT (&xl, &xh, x);
869 return immed_double_const (xl, xh, mode);
872 /* This was formerly used only for non-IEEE float.
873 eggert@twinsun.com says it is safe for IEEE also. */
876 enum rtx_code reversed;
879 /* There are some simplifications we can do even if the operands
884 /* (not (not X)) == X. */
885 if (GET_CODE (op) == NOT)
888 /* (not (eq X Y)) == (ne X Y), etc. */
889 if (COMPARISON_P (op)
890 && (mode == BImode || STORE_FLAG_VALUE == -1)
891 && ((reversed = reversed_comparison_code (op, NULL_RTX))
893 return simplify_gen_relational (reversed, mode, VOIDmode,
894 XEXP (op, 0), XEXP (op, 1));
896 /* (not (plus X -1)) can become (neg X). */
897 if (GET_CODE (op) == PLUS
898 && XEXP (op, 1) == constm1_rtx)
899 return simplify_gen_unary (NEG, mode, XEXP (op, 0), mode);
901 /* Similarly, (not (neg X)) is (plus X -1). */
902 if (GET_CODE (op) == NEG)
903 return plus_constant (XEXP (op, 0), -1);
905 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
906 if (GET_CODE (op) == XOR
907 && GET_CODE (XEXP (op, 1)) == CONST_INT
908 && (temp = simplify_unary_operation (NOT, mode,
911 return simplify_gen_binary (XOR, mode, XEXP (op, 0), temp);
913 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
914 if (GET_CODE (op) == PLUS
915 && GET_CODE (XEXP (op, 1)) == CONST_INT
916 && mode_signbit_p (mode, XEXP (op, 1))
917 && (temp = simplify_unary_operation (NOT, mode,
920 return simplify_gen_binary (XOR, mode, XEXP (op, 0), temp);
924 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
925 operands other than 1, but that is not valid. We could do a
926 similar simplification for (not (lshiftrt C X)) where C is
927 just the sign bit, but this doesn't seem common enough to
929 if (GET_CODE (op) == ASHIFT
930 && XEXP (op, 0) == const1_rtx)
932 temp = simplify_gen_unary (NOT, mode, const1_rtx, mode);
933 return simplify_gen_binary (ROTATE, mode, temp, XEXP (op, 1));
936 /* If STORE_FLAG_VALUE is -1, (not (comparison X Y)) can be done
937 by reversing the comparison code if valid. */
938 if (STORE_FLAG_VALUE == -1
940 && (reversed = reversed_comparison_code (op, NULL_RTX))
942 return simplify_gen_relational (reversed, mode, VOIDmode,
943 XEXP (op, 0), XEXP (op, 1));
945 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
946 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
947 so we can perform the above simplification. */
949 if (STORE_FLAG_VALUE == -1
950 && GET_CODE (op) == ASHIFTRT
951 && GET_CODE (XEXP (op, 1)) == CONST_INT
952 && INTVAL (XEXP (op, 1)) == GET_MODE_BITSIZE (mode) - 1)
953 return simplify_gen_relational (GE, mode, VOIDmode,
954 XEXP (op, 0), const0_rtx);
959 /* (neg (neg X)) == X. */
960 if (GET_CODE (op) == NEG)
963 /* (neg (plus X 1)) can become (not X). */
964 if (GET_CODE (op) == PLUS
965 && XEXP (op, 1) == const1_rtx)
966 return simplify_gen_unary (NOT, mode, XEXP (op, 0), mode);
968 /* Similarly, (neg (not X)) is (plus X 1). */
969 if (GET_CODE (op) == NOT)
970 return plus_constant (XEXP (op, 0), 1);
972 /* (neg (minus X Y)) can become (minus Y X). This transformation
973 isn't safe for modes with signed zeros, since if X and Y are
974 both +0, (minus Y X) is the same as (minus X Y). If the
975 rounding mode is towards +infinity (or -infinity) then the two
976 expressions will be rounded differently. */
977 if (GET_CODE (op) == MINUS
978 && !HONOR_SIGNED_ZEROS (mode)
979 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
980 return simplify_gen_binary (MINUS, mode, XEXP (op, 1),
983 if (GET_CODE (op) == PLUS
984 && !HONOR_SIGNED_ZEROS (mode)
985 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
987 /* (neg (plus A C)) is simplified to (minus -C A). */
988 if (GET_CODE (XEXP (op, 1)) == CONST_INT
989 || GET_CODE (XEXP (op, 1)) == CONST_DOUBLE)
991 temp = simplify_unary_operation (NEG, mode, XEXP (op, 1),
994 return simplify_gen_binary (MINUS, mode, temp,
998 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
999 temp = simplify_gen_unary (NEG, mode, XEXP (op, 0), mode);
1000 return simplify_gen_binary (MINUS, mode, temp, XEXP (op, 1));
1003 /* (neg (mult A B)) becomes (mult (neg A) B).
1004 This works even for floating-point values. */
1005 if (GET_CODE (op) == MULT
1006 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
1008 temp = simplify_gen_unary (NEG, mode, XEXP (op, 0), mode);
1009 return simplify_gen_binary (MULT, mode, temp, XEXP (op, 1));
1012 /* NEG commutes with ASHIFT since it is multiplication. Only do
1013 this if we can then eliminate the NEG (e.g., if the operand
1015 if (GET_CODE (op) == ASHIFT)
1017 temp = simplify_unary_operation (NEG, mode, XEXP (op, 0),
1020 return simplify_gen_binary (ASHIFT, mode, temp,
1024 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
1025 C is equal to the width of MODE minus 1. */
1026 if (GET_CODE (op) == ASHIFTRT
1027 && GET_CODE (XEXP (op, 1)) == CONST_INT
1028 && INTVAL (XEXP (op, 1)) == GET_MODE_BITSIZE (mode) - 1)
1029 return simplify_gen_binary (LSHIFTRT, mode,
1030 XEXP (op, 0), XEXP (op, 1));
1032 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
1033 C is equal to the width of MODE minus 1. */
1034 if (GET_CODE (op) == LSHIFTRT
1035 && GET_CODE (XEXP (op, 1)) == CONST_INT
1036 && INTVAL (XEXP (op, 1)) == GET_MODE_BITSIZE (mode) - 1)
1037 return simplify_gen_binary (ASHIFTRT, mode,
1038 XEXP (op, 0), XEXP (op, 1));
1043 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1044 becomes just the MINUS if its mode is MODE. This allows
1045 folding switch statements on machines using casesi (such as
1047 if (GET_CODE (op) == TRUNCATE
1048 && GET_MODE (XEXP (op, 0)) == mode
1049 && GET_CODE (XEXP (op, 0)) == MINUS
1050 && GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF
1051 && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
1052 return XEXP (op, 0);
1054 /* Check for a sign extension of a subreg of a promoted
1055 variable, where the promotion is sign-extended, and the
1056 target mode is the same as the variable's promotion. */
1057 if (GET_CODE (op) == SUBREG
1058 && SUBREG_PROMOTED_VAR_P (op)
1059 && ! SUBREG_PROMOTED_UNSIGNED_P (op)
1060 && GET_MODE (XEXP (op, 0)) == mode)
1061 return XEXP (op, 0);
1063 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1064 if (! POINTERS_EXTEND_UNSIGNED
1065 && mode == Pmode && GET_MODE (op) == ptr_mode
1067 || (GET_CODE (op) == SUBREG
1068 && REG_P (SUBREG_REG (op))
1069 && REG_POINTER (SUBREG_REG (op))
1070 && GET_MODE (SUBREG_REG (op)) == Pmode)))
1071 return convert_memory_address (Pmode, op);
1076 /* Check for a zero extension of a subreg of a promoted
1077 variable, where the promotion is zero-extended, and the
1078 target mode is the same as the variable's promotion. */
1079 if (GET_CODE (op) == SUBREG
1080 && SUBREG_PROMOTED_VAR_P (op)
1081 && SUBREG_PROMOTED_UNSIGNED_P (op)
1082 && GET_MODE (XEXP (op, 0)) == mode)
1083 return XEXP (op, 0);
1085 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1086 if (POINTERS_EXTEND_UNSIGNED > 0
1087 && mode == Pmode && GET_MODE (op) == ptr_mode
1089 || (GET_CODE (op) == SUBREG
1090 && REG_P (SUBREG_REG (op))
1091 && REG_POINTER (SUBREG_REG (op))
1092 && GET_MODE (SUBREG_REG (op)) == Pmode)))
1093 return convert_memory_address (Pmode, op);
1105 /* Subroutine of simplify_binary_operation to simplify a commutative,
1106 associative binary operation CODE with result mode MODE, operating
1107 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
1108 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
1109 canonicalization is possible. */
1112 simplify_associative_operation (enum rtx_code code, enum machine_mode mode,
1117 /* Linearize the operator to the left. */
1118 if (GET_CODE (op1) == code)
1120 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
1121 if (GET_CODE (op0) == code)
1123 tem = simplify_gen_binary (code, mode, op0, XEXP (op1, 0));
1124 return simplify_gen_binary (code, mode, tem, XEXP (op1, 1));
1127 /* "a op (b op c)" becomes "(b op c) op a". */
1128 if (! swap_commutative_operands_p (op1, op0))
1129 return simplify_gen_binary (code, mode, op1, op0);
1136 if (GET_CODE (op0) == code)
1138 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
1139 if (swap_commutative_operands_p (XEXP (op0, 1), op1))
1141 tem = simplify_gen_binary (code, mode, XEXP (op0, 0), op1);
1142 return simplify_gen_binary (code, mode, tem, XEXP (op0, 1));
1145 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
1146 tem = swap_commutative_operands_p (XEXP (op0, 1), op1)
1147 ? simplify_binary_operation (code, mode, op1, XEXP (op0, 1))
1148 : simplify_binary_operation (code, mode, XEXP (op0, 1), op1);
1150 return simplify_gen_binary (code, mode, XEXP (op0, 0), tem);
1152 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
1153 tem = swap_commutative_operands_p (XEXP (op0, 0), op1)
1154 ? simplify_binary_operation (code, mode, op1, XEXP (op0, 0))
1155 : simplify_binary_operation (code, mode, XEXP (op0, 0), op1);
1157 return simplify_gen_binary (code, mode, tem, XEXP (op0, 1));
1163 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
1164 and OP1. Return 0 if no simplification is possible.
1166 Don't use this for relational operations such as EQ or LT.
1167 Use simplify_relational_operation instead. */
1169 simplify_binary_operation (enum rtx_code code, enum machine_mode mode,
1172 HOST_WIDE_INT arg0, arg1, arg0s, arg1s;
1174 unsigned int width = GET_MODE_BITSIZE (mode);
1175 rtx trueop0, trueop1;
1178 #ifdef ENABLE_CHECKING
1179 /* Relational operations don't work here. We must know the mode
1180 of the operands in order to do the comparison correctly.
1181 Assuming a full word can give incorrect results.
1182 Consider comparing 128 with -128 in QImode. */
1184 if (GET_RTX_CLASS (code) == RTX_COMPARE
1185 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
1189 /* Make sure the constant is second. */
1190 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
1191 && swap_commutative_operands_p (op0, op1))
1193 tem = op0, op0 = op1, op1 = tem;
1196 trueop0 = avoid_constant_pool_reference (op0);
1197 trueop1 = avoid_constant_pool_reference (op1);
1199 if (VECTOR_MODE_P (mode)
1200 && GET_CODE (trueop0) == CONST_VECTOR
1201 && GET_CODE (trueop1) == CONST_VECTOR)
1203 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
1204 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
1205 enum machine_mode op0mode = GET_MODE (trueop0);
1206 int op0_elt_size = GET_MODE_SIZE (GET_MODE_INNER (op0mode));
1207 unsigned op0_n_elts = (GET_MODE_SIZE (op0mode) / op0_elt_size);
1208 enum machine_mode op1mode = GET_MODE (trueop1);
1209 int op1_elt_size = GET_MODE_SIZE (GET_MODE_INNER (op1mode));
1210 unsigned op1_n_elts = (GET_MODE_SIZE (op1mode) / op1_elt_size);
1211 rtvec v = rtvec_alloc (n_elts);
1214 if (op0_n_elts != n_elts || op1_n_elts != n_elts)
1217 for (i = 0; i < n_elts; i++)
1219 rtx x = simplify_binary_operation (code, GET_MODE_INNER (mode),
1220 CONST_VECTOR_ELT (trueop0, i),
1221 CONST_VECTOR_ELT (trueop1, i));
1224 RTVEC_ELT (v, i) = x;
1227 return gen_rtx_CONST_VECTOR (mode, v);
1230 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1231 && GET_CODE (trueop0) == CONST_DOUBLE
1232 && GET_CODE (trueop1) == CONST_DOUBLE
1233 && mode == GET_MODE (op0) && mode == GET_MODE (op1))
1244 real_to_target (tmp0, CONST_DOUBLE_REAL_VALUE (op0),
1246 real_to_target (tmp1, CONST_DOUBLE_REAL_VALUE (op1),
1248 for (i = 0; i < 4; i++)
1252 else if (code == IOR)
1254 else if (code == XOR)
1259 real_from_target (&r, tmp0, mode);
1260 return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
1264 REAL_VALUE_TYPE f0, f1, value;
1266 REAL_VALUE_FROM_CONST_DOUBLE (f0, trueop0);
1267 REAL_VALUE_FROM_CONST_DOUBLE (f1, trueop1);
1268 f0 = real_value_truncate (mode, f0);
1269 f1 = real_value_truncate (mode, f1);
1271 if (HONOR_SNANS (mode)
1272 && (REAL_VALUE_ISNAN (f0) || REAL_VALUE_ISNAN (f1)))
1276 && REAL_VALUES_EQUAL (f1, dconst0)
1277 && (flag_trapping_math || ! MODE_HAS_INFINITIES (mode)))
1280 if (MODE_HAS_INFINITIES (mode) && HONOR_NANS (mode)
1281 && flag_trapping_math
1282 && REAL_VALUE_ISINF (f0) && REAL_VALUE_ISINF (f1))
1284 int s0 = REAL_VALUE_NEGATIVE (f0);
1285 int s1 = REAL_VALUE_NEGATIVE (f1);
1290 /* Inf + -Inf = NaN plus exception. */
1295 /* Inf - Inf = NaN plus exception. */
1300 /* Inf / Inf = NaN plus exception. */
1307 if (code == MULT && MODE_HAS_INFINITIES (mode) && HONOR_NANS (mode)
1308 && flag_trapping_math
1309 && ((REAL_VALUE_ISINF (f0) && REAL_VALUES_EQUAL (f1, dconst0))
1310 || (REAL_VALUE_ISINF (f1)
1311 && REAL_VALUES_EQUAL (f0, dconst0))))
1312 /* Inf * 0 = NaN plus exception. */
1315 REAL_ARITHMETIC (value, rtx_to_tree_code (code), f0, f1);
1317 value = real_value_truncate (mode, value);
1318 return CONST_DOUBLE_FROM_REAL_VALUE (value, mode);
1322 /* We can fold some multi-word operations. */
1323 if (GET_MODE_CLASS (mode) == MODE_INT
1324 && width == HOST_BITS_PER_WIDE_INT * 2
1325 && (GET_CODE (trueop0) == CONST_DOUBLE
1326 || GET_CODE (trueop0) == CONST_INT)
1327 && (GET_CODE (trueop1) == CONST_DOUBLE
1328 || GET_CODE (trueop1) == CONST_INT))
1330 unsigned HOST_WIDE_INT l1, l2, lv, lt;
1331 HOST_WIDE_INT h1, h2, hv, ht;
1333 if (GET_CODE (trueop0) == CONST_DOUBLE)
1334 l1 = CONST_DOUBLE_LOW (trueop0), h1 = CONST_DOUBLE_HIGH (trueop0);
1336 l1 = INTVAL (trueop0), h1 = HWI_SIGN_EXTEND (l1);
1338 if (GET_CODE (trueop1) == CONST_DOUBLE)
1339 l2 = CONST_DOUBLE_LOW (trueop1), h2 = CONST_DOUBLE_HIGH (trueop1);
1341 l2 = INTVAL (trueop1), h2 = HWI_SIGN_EXTEND (l2);
1346 /* A - B == A + (-B). */
1347 neg_double (l2, h2, &lv, &hv);
1350 /* Fall through.... */
1353 add_double (l1, h1, l2, h2, &lv, &hv);
1357 mul_double (l1, h1, l2, h2, &lv, &hv);
1361 if (div_and_round_double (TRUNC_DIV_EXPR, 0, l1, h1, l2, h2,
1362 &lv, &hv, <, &ht))
1367 if (div_and_round_double (TRUNC_DIV_EXPR, 0, l1, h1, l2, h2,
1368 <, &ht, &lv, &hv))
1373 if (div_and_round_double (TRUNC_DIV_EXPR, 1, l1, h1, l2, h2,
1374 &lv, &hv, <, &ht))
1379 if (div_and_round_double (TRUNC_DIV_EXPR, 1, l1, h1, l2, h2,
1380 <, &ht, &lv, &hv))
1385 lv = l1 & l2, hv = h1 & h2;
1389 lv = l1 | l2, hv = h1 | h2;
1393 lv = l1 ^ l2, hv = h1 ^ h2;
1399 && ((unsigned HOST_WIDE_INT) l1
1400 < (unsigned HOST_WIDE_INT) l2)))
1409 && ((unsigned HOST_WIDE_INT) l1
1410 > (unsigned HOST_WIDE_INT) l2)))
1417 if ((unsigned HOST_WIDE_INT) h1 < (unsigned HOST_WIDE_INT) h2
1419 && ((unsigned HOST_WIDE_INT) l1
1420 < (unsigned HOST_WIDE_INT) l2)))
1427 if ((unsigned HOST_WIDE_INT) h1 > (unsigned HOST_WIDE_INT) h2
1429 && ((unsigned HOST_WIDE_INT) l1
1430 > (unsigned HOST_WIDE_INT) l2)))
1436 case LSHIFTRT: case ASHIFTRT:
1438 case ROTATE: case ROTATERT:
1439 if (SHIFT_COUNT_TRUNCATED)
1440 l2 &= (GET_MODE_BITSIZE (mode) - 1), h2 = 0;
1442 if (h2 != 0 || l2 >= GET_MODE_BITSIZE (mode))
1445 if (code == LSHIFTRT || code == ASHIFTRT)
1446 rshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv,
1448 else if (code == ASHIFT)
1449 lshift_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv, 1);
1450 else if (code == ROTATE)
1451 lrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv);
1452 else /* code == ROTATERT */
1453 rrotate_double (l1, h1, l2, GET_MODE_BITSIZE (mode), &lv, &hv);
1460 return immed_double_const (lv, hv, mode);
1463 if (GET_CODE (op0) != CONST_INT || GET_CODE (op1) != CONST_INT
1464 || width > HOST_BITS_PER_WIDE_INT || width == 0)
1466 /* Even if we can't compute a constant result,
1467 there are some cases worth simplifying. */
1472 /* Maybe simplify x + 0 to x. The two expressions are equivalent
1473 when x is NaN, infinite, or finite and nonzero. They aren't
1474 when x is -0 and the rounding mode is not towards -infinity,
1475 since (-0) + 0 is then 0. */
1476 if (!HONOR_SIGNED_ZEROS (mode) && trueop1 == CONST0_RTX (mode))
1479 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
1480 transformations are safe even for IEEE. */
1481 if (GET_CODE (op0) == NEG)
1482 return simplify_gen_binary (MINUS, mode, op1, XEXP (op0, 0));
1483 else if (GET_CODE (op1) == NEG)
1484 return simplify_gen_binary (MINUS, mode, op0, XEXP (op1, 0));
1486 /* (~a) + 1 -> -a */
1487 if (INTEGRAL_MODE_P (mode)
1488 && GET_CODE (op0) == NOT
1489 && trueop1 == const1_rtx)
1490 return simplify_gen_unary (NEG, mode, XEXP (op0, 0), mode);
1492 /* Handle both-operands-constant cases. We can only add
1493 CONST_INTs to constants since the sum of relocatable symbols
1494 can't be handled by most assemblers. Don't add CONST_INT
1495 to CONST_INT since overflow won't be computed properly if wider
1496 than HOST_BITS_PER_WIDE_INT. */
1498 if (CONSTANT_P (op0) && GET_MODE (op0) != VOIDmode
1499 && GET_CODE (op1) == CONST_INT)
1500 return plus_constant (op0, INTVAL (op1));
1501 else if (CONSTANT_P (op1) && GET_MODE (op1) != VOIDmode
1502 && GET_CODE (op0) == CONST_INT)
1503 return plus_constant (op1, INTVAL (op0));
1505 /* See if this is something like X * C - X or vice versa or
1506 if the multiplication is written as a shift. If so, we can
1507 distribute and make a new multiply, shift, or maybe just
1508 have X (if C is 2 in the example above). But don't make
1509 real multiply if we didn't have one before. */
1511 if (! FLOAT_MODE_P (mode))
1513 HOST_WIDE_INT coeff0 = 1, coeff1 = 1;
1514 rtx lhs = op0, rhs = op1;
1517 if (GET_CODE (lhs) == NEG)
1518 coeff0 = -1, lhs = XEXP (lhs, 0);
1519 else if (GET_CODE (lhs) == MULT
1520 && GET_CODE (XEXP (lhs, 1)) == CONST_INT)
1522 coeff0 = INTVAL (XEXP (lhs, 1)), lhs = XEXP (lhs, 0);
1525 else if (GET_CODE (lhs) == ASHIFT
1526 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
1527 && INTVAL (XEXP (lhs, 1)) >= 0
1528 && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
1530 coeff0 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (lhs, 1));
1531 lhs = XEXP (lhs, 0);
1534 if (GET_CODE (rhs) == NEG)
1535 coeff1 = -1, rhs = XEXP (rhs, 0);
1536 else if (GET_CODE (rhs) == MULT
1537 && GET_CODE (XEXP (rhs, 1)) == CONST_INT)
1539 coeff1 = INTVAL (XEXP (rhs, 1)), rhs = XEXP (rhs, 0);
1542 else if (GET_CODE (rhs) == ASHIFT
1543 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
1544 && INTVAL (XEXP (rhs, 1)) >= 0
1545 && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
1547 coeff1 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (rhs, 1));
1548 rhs = XEXP (rhs, 0);
1551 if (rtx_equal_p (lhs, rhs))
1553 tem = simplify_gen_binary (MULT, mode, lhs,
1554 GEN_INT (coeff0 + coeff1));
1555 return (GET_CODE (tem) == MULT && ! had_mult) ? 0 : tem;
1559 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
1560 if ((GET_CODE (op1) == CONST_INT
1561 || GET_CODE (op1) == CONST_DOUBLE)
1562 && GET_CODE (op0) == XOR
1563 && (GET_CODE (XEXP (op0, 1)) == CONST_INT
1564 || GET_CODE (XEXP (op0, 1)) == CONST_DOUBLE)
1565 && mode_signbit_p (mode, op1))
1566 return simplify_gen_binary (XOR, mode, XEXP (op0, 0),
1567 simplify_gen_binary (XOR, mode, op1,
1570 /* If one of the operands is a PLUS or a MINUS, see if we can
1571 simplify this by the associative law.
1572 Don't use the associative law for floating point.
1573 The inaccuracy makes it nonassociative,
1574 and subtle programs can break if operations are associated. */
1576 if (INTEGRAL_MODE_P (mode)
1577 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
1578 || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS
1579 || (GET_CODE (op0) == CONST
1580 && GET_CODE (XEXP (op0, 0)) == PLUS)
1581 || (GET_CODE (op1) == CONST
1582 && GET_CODE (XEXP (op1, 0)) == PLUS))
1583 && (tem = simplify_plus_minus (code, mode, op0, op1, 0)) != 0)
1586 /* Reassociate floating point addition only when the user
1587 specifies unsafe math optimizations. */
1588 if (FLOAT_MODE_P (mode)
1589 && flag_unsafe_math_optimizations)
1591 tem = simplify_associative_operation (code, mode, op0, op1);
1599 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
1600 using cc0, in which case we want to leave it as a COMPARE
1601 so we can distinguish it from a register-register-copy.
1603 In IEEE floating point, x-0 is not the same as x. */
1605 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
1606 || ! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
1607 && trueop1 == CONST0_RTX (mode))
1611 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
1612 if (((GET_CODE (op0) == GT && GET_CODE (op1) == LT)
1613 || (GET_CODE (op0) == GTU && GET_CODE (op1) == LTU))
1614 && XEXP (op0, 1) == const0_rtx && XEXP (op1, 1) == const0_rtx)
1616 rtx xop00 = XEXP (op0, 0);
1617 rtx xop10 = XEXP (op1, 0);
1620 if (GET_CODE (xop00) == CC0 && GET_CODE (xop10) == CC0)
1622 if (REG_P (xop00) && REG_P (xop10)
1623 && GET_MODE (xop00) == GET_MODE (xop10)
1624 && REGNO (xop00) == REGNO (xop10)
1625 && GET_MODE_CLASS (GET_MODE (xop00)) == MODE_CC
1626 && GET_MODE_CLASS (GET_MODE (xop10)) == MODE_CC)
1633 /* We can't assume x-x is 0 even with non-IEEE floating point,
1634 but since it is zero except in very strange circumstances, we
1635 will treat it as zero with -funsafe-math-optimizations. */
1636 if (rtx_equal_p (trueop0, trueop1)
1637 && ! side_effects_p (op0)
1638 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations))
1639 return CONST0_RTX (mode);
1641 /* Change subtraction from zero into negation. (0 - x) is the
1642 same as -x when x is NaN, infinite, or finite and nonzero.
1643 But if the mode has signed zeros, and does not round towards
1644 -infinity, then 0 - 0 is 0, not -0. */
1645 if (!HONOR_SIGNED_ZEROS (mode) && trueop0 == CONST0_RTX (mode))
1646 return simplify_gen_unary (NEG, mode, op1, mode);
1648 /* (-1 - a) is ~a. */
1649 if (trueop0 == constm1_rtx)
1650 return simplify_gen_unary (NOT, mode, op1, mode);
1652 /* Subtracting 0 has no effect unless the mode has signed zeros
1653 and supports rounding towards -infinity. In such a case,
1655 if (!(HONOR_SIGNED_ZEROS (mode)
1656 && HONOR_SIGN_DEPENDENT_ROUNDING (mode))
1657 && trueop1 == CONST0_RTX (mode))
1660 /* See if this is something like X * C - X or vice versa or
1661 if the multiplication is written as a shift. If so, we can
1662 distribute and make a new multiply, shift, or maybe just
1663 have X (if C is 2 in the example above). But don't make
1664 real multiply if we didn't have one before. */
1666 if (! FLOAT_MODE_P (mode))
1668 HOST_WIDE_INT coeff0 = 1, coeff1 = 1;
1669 rtx lhs = op0, rhs = op1;
1672 if (GET_CODE (lhs) == NEG)
1673 coeff0 = -1, lhs = XEXP (lhs, 0);
1674 else if (GET_CODE (lhs) == MULT
1675 && GET_CODE (XEXP (lhs, 1)) == CONST_INT)
1677 coeff0 = INTVAL (XEXP (lhs, 1)), lhs = XEXP (lhs, 0);
1680 else if (GET_CODE (lhs) == ASHIFT
1681 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
1682 && INTVAL (XEXP (lhs, 1)) >= 0
1683 && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
1685 coeff0 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (lhs, 1));
1686 lhs = XEXP (lhs, 0);
1689 if (GET_CODE (rhs) == NEG)
1690 coeff1 = - 1, rhs = XEXP (rhs, 0);
1691 else if (GET_CODE (rhs) == MULT
1692 && GET_CODE (XEXP (rhs, 1)) == CONST_INT)
1694 coeff1 = INTVAL (XEXP (rhs, 1)), rhs = XEXP (rhs, 0);
1697 else if (GET_CODE (rhs) == ASHIFT
1698 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
1699 && INTVAL (XEXP (rhs, 1)) >= 0
1700 && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
1702 coeff1 = ((HOST_WIDE_INT) 1) << INTVAL (XEXP (rhs, 1));
1703 rhs = XEXP (rhs, 0);
1706 if (rtx_equal_p (lhs, rhs))
1708 tem = simplify_gen_binary (MULT, mode, lhs,
1709 GEN_INT (coeff0 - coeff1));
1710 return (GET_CODE (tem) == MULT && ! had_mult) ? 0 : tem;
1714 /* (a - (-b)) -> (a + b). True even for IEEE. */
1715 if (GET_CODE (op1) == NEG)
1716 return simplify_gen_binary (PLUS, mode, op0, XEXP (op1, 0));
1718 /* (-x - c) may be simplified as (-c - x). */
1719 if (GET_CODE (op0) == NEG
1720 && (GET_CODE (op1) == CONST_INT
1721 || GET_CODE (op1) == CONST_DOUBLE))
1723 tem = simplify_unary_operation (NEG, mode, op1, mode);
1725 return simplify_gen_binary (MINUS, mode, tem, XEXP (op0, 0));
1728 /* If one of the operands is a PLUS or a MINUS, see if we can
1729 simplify this by the associative law.
1730 Don't use the associative law for floating point.
1731 The inaccuracy makes it nonassociative,
1732 and subtle programs can break if operations are associated. */
1734 if (INTEGRAL_MODE_P (mode)
1735 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
1736 || GET_CODE (op1) == PLUS || GET_CODE (op1) == MINUS
1737 || (GET_CODE (op0) == CONST
1738 && GET_CODE (XEXP (op0, 0)) == PLUS)
1739 || (GET_CODE (op1) == CONST
1740 && GET_CODE (XEXP (op1, 0)) == PLUS))
1741 && (tem = simplify_plus_minus (code, mode, op0, op1, 0)) != 0)
1744 /* Don't let a relocatable value get a negative coeff. */
1745 if (GET_CODE (op1) == CONST_INT && GET_MODE (op0) != VOIDmode)
1746 return simplify_gen_binary (PLUS, mode,
1748 neg_const_int (mode, op1));
1750 /* (x - (x & y)) -> (x & ~y) */
1751 if (GET_CODE (op1) == AND)
1753 if (rtx_equal_p (op0, XEXP (op1, 0)))
1755 tem = simplify_gen_unary (NOT, mode, XEXP (op1, 1),
1756 GET_MODE (XEXP (op1, 1)));
1757 return simplify_gen_binary (AND, mode, op0, tem);
1759 if (rtx_equal_p (op0, XEXP (op1, 1)))
1761 tem = simplify_gen_unary (NOT, mode, XEXP (op1, 0),
1762 GET_MODE (XEXP (op1, 0)));
1763 return simplify_gen_binary (AND, mode, op0, tem);
1769 if (trueop1 == constm1_rtx)
1770 return simplify_gen_unary (NEG, mode, op0, mode);
1772 /* Maybe simplify x * 0 to 0. The reduction is not valid if
1773 x is NaN, since x * 0 is then also NaN. Nor is it valid
1774 when the mode has signed zeros, since multiplying a negative
1775 number by 0 will give -0, not 0. */
1776 if (!HONOR_NANS (mode)
1777 && !HONOR_SIGNED_ZEROS (mode)
1778 && trueop1 == CONST0_RTX (mode)
1779 && ! side_effects_p (op0))
1782 /* In IEEE floating point, x*1 is not equivalent to x for
1784 if (!HONOR_SNANS (mode)
1785 && trueop1 == CONST1_RTX (mode))
1788 /* Convert multiply by constant power of two into shift unless
1789 we are still generating RTL. This test is a kludge. */
1790 if (GET_CODE (trueop1) == CONST_INT
1791 && (val = exact_log2 (INTVAL (trueop1))) >= 0
1792 /* If the mode is larger than the host word size, and the
1793 uppermost bit is set, then this isn't a power of two due
1794 to implicit sign extension. */
1795 && (width <= HOST_BITS_PER_WIDE_INT
1796 || val != HOST_BITS_PER_WIDE_INT - 1)
1797 && ! rtx_equal_function_value_matters)
1798 return simplify_gen_binary (ASHIFT, mode, op0, GEN_INT (val));
1800 /* x*2 is x+x and x*(-1) is -x */
1801 if (GET_CODE (trueop1) == CONST_DOUBLE
1802 && GET_MODE_CLASS (GET_MODE (trueop1)) == MODE_FLOAT
1803 && GET_MODE (op0) == mode)
1806 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
1808 if (REAL_VALUES_EQUAL (d, dconst2))
1809 return simplify_gen_binary (PLUS, mode, op0, copy_rtx (op0));
1811 if (REAL_VALUES_EQUAL (d, dconstm1))
1812 return simplify_gen_unary (NEG, mode, op0, mode);
1815 /* Reassociate multiplication, but for floating point MULTs
1816 only when the user specifies unsafe math optimizations. */
1817 if (! FLOAT_MODE_P (mode)
1818 || flag_unsafe_math_optimizations)
1820 tem = simplify_associative_operation (code, mode, op0, op1);
1827 if (trueop1 == const0_rtx)
1829 if (GET_CODE (trueop1) == CONST_INT
1830 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1831 == GET_MODE_MASK (mode)))
1833 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
1835 /* A | (~A) -> -1 */
1836 if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
1837 || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
1838 && ! side_effects_p (op0)
1839 && GET_MODE_CLASS (mode) != MODE_CC)
1841 tem = simplify_associative_operation (code, mode, op0, op1);
1847 if (trueop1 == const0_rtx)
1849 if (GET_CODE (trueop1) == CONST_INT
1850 && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
1851 == GET_MODE_MASK (mode)))
1852 return simplify_gen_unary (NOT, mode, op0, mode);
1853 if (trueop0 == trueop1
1854 && ! side_effects_p (op0)
1855 && GET_MODE_CLASS (mode) != MODE_CC)
1858 /* Canonicalize XOR of the most significant bit to PLUS. */
1859 if ((GET_CODE (op1) == CONST_INT
1860 || GET_CODE (op1) == CONST_DOUBLE)
1861 && mode_signbit_p (mode, op1))
1862 return simplify_gen_binary (PLUS, mode, op0, op1);
1863 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
1864 if ((GET_CODE (op1) == CONST_INT
1865 || GET_CODE (op1) == CONST_DOUBLE)
1866 && GET_CODE (op0) == PLUS
1867 && (GET_CODE (XEXP (op0, 1)) == CONST_INT
1868 || GET_CODE (XEXP (op0, 1)) == CONST_DOUBLE)
1869 && mode_signbit_p (mode, XEXP (op0, 1)))
1870 return simplify_gen_binary (XOR, mode, XEXP (op0, 0),
1871 simplify_gen_binary (XOR, mode, op1,
1874 tem = simplify_associative_operation (code, mode, op0, op1);
1880 if (trueop1 == const0_rtx && ! side_effects_p (op0))
1882 /* If we are turning off bits already known off in OP0, we need
1884 if (GET_CODE (trueop1) == CONST_INT
1885 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1886 && (nonzero_bits (trueop0, mode) & ~INTVAL (trueop1)) == 0)
1888 if (trueop0 == trueop1 && ! side_effects_p (op0)
1889 && GET_MODE_CLASS (mode) != MODE_CC)
1892 if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
1893 || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
1894 && ! side_effects_p (op0)
1895 && GET_MODE_CLASS (mode) != MODE_CC)
1897 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
1898 ((A & N) + B) & M -> (A + B) & M
1899 Similarly if (N & M) == 0,
1900 ((A | N) + B) & M -> (A + B) & M
1901 and for - instead of + and/or ^ instead of |. */
1902 if (GET_CODE (trueop1) == CONST_INT
1903 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1904 && ~INTVAL (trueop1)
1905 && (INTVAL (trueop1) & (INTVAL (trueop1) + 1)) == 0
1906 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS))
1911 pmop[0] = XEXP (op0, 0);
1912 pmop[1] = XEXP (op0, 1);
1914 for (which = 0; which < 2; which++)
1917 switch (GET_CODE (tem))
1920 if (GET_CODE (XEXP (tem, 1)) == CONST_INT
1921 && (INTVAL (XEXP (tem, 1)) & INTVAL (trueop1))
1922 == INTVAL (trueop1))
1923 pmop[which] = XEXP (tem, 0);
1927 if (GET_CODE (XEXP (tem, 1)) == CONST_INT
1928 && (INTVAL (XEXP (tem, 1)) & INTVAL (trueop1)) == 0)
1929 pmop[which] = XEXP (tem, 0);
1936 if (pmop[0] != XEXP (op0, 0) || pmop[1] != XEXP (op0, 1))
1938 tem = simplify_gen_binary (GET_CODE (op0), mode,
1940 return simplify_gen_binary (code, mode, tem, op1);
1943 tem = simplify_associative_operation (code, mode, op0, op1);
1949 /* 0/x is 0 (or x&0 if x has side-effects). */
1950 if (trueop0 == const0_rtx)
1951 return side_effects_p (op1)
1952 ? simplify_gen_binary (AND, mode, op1, const0_rtx)
1955 if (trueop1 == const1_rtx)
1957 /* Handle narrowing UDIV. */
1958 rtx x = gen_lowpart_common (mode, op0);
1961 if (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
1962 return gen_lowpart_SUBREG (mode, op0);
1965 /* Convert divide by power of two into shift. */
1966 if (GET_CODE (trueop1) == CONST_INT
1967 && (arg1 = exact_log2 (INTVAL (trueop1))) > 0)
1968 return simplify_gen_binary (LSHIFTRT, mode, op0, GEN_INT (arg1));
1972 /* Handle floating point and integers separately. */
1973 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1975 /* Maybe change 0.0 / x to 0.0. This transformation isn't
1976 safe for modes with NaNs, since 0.0 / 0.0 will then be
1977 NaN rather than 0.0. Nor is it safe for modes with signed
1978 zeros, since dividing 0 by a negative number gives -0.0 */
1979 if (trueop0 == CONST0_RTX (mode)
1980 && !HONOR_NANS (mode)
1981 && !HONOR_SIGNED_ZEROS (mode)
1982 && ! side_effects_p (op1))
1985 if (trueop1 == CONST1_RTX (mode)
1986 && !HONOR_SNANS (mode))
1989 if (GET_CODE (trueop1) == CONST_DOUBLE
1990 && trueop1 != CONST0_RTX (mode))
1993 REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);
1996 if (REAL_VALUES_EQUAL (d, dconstm1)
1997 && !HONOR_SNANS (mode))
1998 return simplify_gen_unary (NEG, mode, op0, mode);
2000 /* Change FP division by a constant into multiplication.
2001 Only do this with -funsafe-math-optimizations. */
2002 if (flag_unsafe_math_optimizations
2003 && !REAL_VALUES_EQUAL (d, dconst0))
2005 REAL_ARITHMETIC (d, RDIV_EXPR, dconst1, d);
2006 tem = CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
2007 return simplify_gen_binary (MULT, mode, op0, tem);
2013 /* 0/x is 0 (or x&0 if x has side-effects). */
2014 if (trueop0 == const0_rtx)
2015 return side_effects_p (op1)
2016 ? simplify_gen_binary (AND, mode, op1, const0_rtx)
2019 if (trueop1 == const1_rtx)
2021 /* Handle narrowing DIV. */
2022 rtx x = gen_lowpart_common (mode, op0);
2025 if (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
2026 return gen_lowpart_SUBREG (mode, op0);
2030 if (trueop1 == constm1_rtx)
2032 rtx x = gen_lowpart_common (mode, op0);
2034 x = (mode != GET_MODE (op0) && GET_MODE (op0) != VOIDmode)
2035 ? gen_lowpart_SUBREG (mode, op0) : op0;
2036 return simplify_gen_unary (NEG, mode, x, mode);
2042 /* 0%x is 0 (or x&0 if x has side-effects). */
2043 if (trueop0 == const0_rtx)
2044 return side_effects_p (op1)
2045 ? simplify_gen_binary (AND, mode, op1, const0_rtx)
2047 /* x%1 is 0 (of x&0 if x has side-effects). */
2048 if (trueop1 == const1_rtx)
2049 return side_effects_p (op0)
2050 ? simplify_gen_binary (AND, mode, op0, const0_rtx)
2052 /* Implement modulus by power of two as AND. */
2053 if (GET_CODE (trueop1) == CONST_INT
2054 && exact_log2 (INTVAL (trueop1)) > 0)
2055 return simplify_gen_binary (AND, mode, op0,
2056 GEN_INT (INTVAL (op1) - 1));
2060 /* 0%x is 0 (or x&0 if x has side-effects). */
2061 if (trueop0 == const0_rtx)
2062 return side_effects_p (op1)
2063 ? simplify_gen_binary (AND, mode, op1, const0_rtx)
2065 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
2066 if (trueop1 == const1_rtx || trueop1 == constm1_rtx)
2067 return side_effects_p (op0)
2068 ? simplify_gen_binary (AND, mode, op0, const0_rtx)
2075 /* Rotating ~0 always results in ~0. */
2076 if (GET_CODE (trueop0) == CONST_INT && width <= HOST_BITS_PER_WIDE_INT
2077 && (unsigned HOST_WIDE_INT) INTVAL (trueop0) == GET_MODE_MASK (mode)
2078 && ! side_effects_p (op1))
2081 /* Fall through.... */
2085 if (trueop1 == const0_rtx)
2087 if (trueop0 == const0_rtx && ! side_effects_p (op1))
2092 if (width <= HOST_BITS_PER_WIDE_INT
2093 && GET_CODE (trueop1) == CONST_INT
2094 && INTVAL (trueop1) == (HOST_WIDE_INT) 1 << (width -1)
2095 && ! side_effects_p (op0))
2097 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
2099 tem = simplify_associative_operation (code, mode, op0, op1);
2105 if (width <= HOST_BITS_PER_WIDE_INT
2106 && GET_CODE (trueop1) == CONST_INT
2107 && ((unsigned HOST_WIDE_INT) INTVAL (trueop1)
2108 == (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode) >> 1)
2109 && ! side_effects_p (op0))
2111 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
2113 tem = simplify_associative_operation (code, mode, op0, op1);
2119 if (trueop1 == const0_rtx && ! side_effects_p (op0))
2121 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
2123 tem = simplify_associative_operation (code, mode, op0, op1);
2129 if (trueop1 == constm1_rtx && ! side_effects_p (op0))
2131 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
2133 tem = simplify_associative_operation (code, mode, op0, op1);
2142 /* ??? There are simplifications that can be done. */
2146 if (!VECTOR_MODE_P (mode))
2148 if (!VECTOR_MODE_P (GET_MODE (trueop0))
2150 != GET_MODE_INNER (GET_MODE (trueop0)))
2151 || GET_CODE (trueop1) != PARALLEL
2152 || XVECLEN (trueop1, 0) != 1
2153 || GET_CODE (XVECEXP (trueop1, 0, 0)) != CONST_INT)
2156 if (GET_CODE (trueop0) == CONST_VECTOR)
2157 return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP (trueop1, 0, 0)));
2161 if (!VECTOR_MODE_P (GET_MODE (trueop0))
2162 || (GET_MODE_INNER (mode)
2163 != GET_MODE_INNER (GET_MODE (trueop0)))
2164 || GET_CODE (trueop1) != PARALLEL)
2167 if (GET_CODE (trueop0) == CONST_VECTOR)
2169 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
2170 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
2171 rtvec v = rtvec_alloc (n_elts);
2174 if (XVECLEN (trueop1, 0) != (int) n_elts)
2176 for (i = 0; i < n_elts; i++)
2178 rtx x = XVECEXP (trueop1, 0, i);
2180 if (GET_CODE (x) != CONST_INT)
2182 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop0, INTVAL (x));
2185 return gen_rtx_CONST_VECTOR (mode, v);
2191 enum machine_mode op0_mode = (GET_MODE (trueop0) != VOIDmode
2192 ? GET_MODE (trueop0)
2193 : GET_MODE_INNER (mode));
2194 enum machine_mode op1_mode = (GET_MODE (trueop1) != VOIDmode
2195 ? GET_MODE (trueop1)
2196 : GET_MODE_INNER (mode));
2198 if (!VECTOR_MODE_P (mode)
2199 || (GET_MODE_SIZE (op0_mode) + GET_MODE_SIZE (op1_mode)
2200 != GET_MODE_SIZE (mode)))
2203 if ((VECTOR_MODE_P (op0_mode)
2204 && (GET_MODE_INNER (mode)
2205 != GET_MODE_INNER (op0_mode)))
2206 || (!VECTOR_MODE_P (op0_mode)
2207 && GET_MODE_INNER (mode) != op0_mode))
2210 if ((VECTOR_MODE_P (op1_mode)
2211 && (GET_MODE_INNER (mode)
2212 != GET_MODE_INNER (op1_mode)))
2213 || (!VECTOR_MODE_P (op1_mode)
2214 && GET_MODE_INNER (mode) != op1_mode))
2217 if ((GET_CODE (trueop0) == CONST_VECTOR
2218 || GET_CODE (trueop0) == CONST_INT
2219 || GET_CODE (trueop0) == CONST_DOUBLE)
2220 && (GET_CODE (trueop1) == CONST_VECTOR
2221 || GET_CODE (trueop1) == CONST_INT
2222 || GET_CODE (trueop1) == CONST_DOUBLE))
2224 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
2225 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
2226 rtvec v = rtvec_alloc (n_elts);
2228 unsigned in_n_elts = 1;
2230 if (VECTOR_MODE_P (op0_mode))
2231 in_n_elts = (GET_MODE_SIZE (op0_mode) / elt_size);
2232 for (i = 0; i < n_elts; i++)
2236 if (!VECTOR_MODE_P (op0_mode))
2237 RTVEC_ELT (v, i) = trueop0;
2239 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop0, i);
2243 if (!VECTOR_MODE_P (op1_mode))
2244 RTVEC_ELT (v, i) = trueop1;
2246 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop1,
2251 return gen_rtx_CONST_VECTOR (mode, v);
2263 /* Get the integer argument values in two forms:
2264 zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
2266 arg0 = INTVAL (trueop0);
2267 arg1 = INTVAL (trueop1);
2269 if (width < HOST_BITS_PER_WIDE_INT)
2271 arg0 &= ((HOST_WIDE_INT) 1 << width) - 1;
2272 arg1 &= ((HOST_WIDE_INT) 1 << width) - 1;
2275 if (arg0s & ((HOST_WIDE_INT) 1 << (width - 1)))
2276 arg0s |= ((HOST_WIDE_INT) (-1) << width);
2279 if (arg1s & ((HOST_WIDE_INT) 1 << (width - 1)))
2280 arg1s |= ((HOST_WIDE_INT) (-1) << width);
2288 /* Compute the value of the arithmetic. */
2293 val = arg0s + arg1s;
2297 val = arg0s - arg1s;
2301 val = arg0s * arg1s;
2306 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2309 val = arg0s / arg1s;
2314 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2317 val = arg0s % arg1s;
2322 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2325 val = (unsigned HOST_WIDE_INT) arg0 / arg1;
2330 || (arg0s == (HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
2333 val = (unsigned HOST_WIDE_INT) arg0 % arg1;
2349 /* If shift count is undefined, don't fold it; let the machine do
2350 what it wants. But truncate it if the machine will do that. */
2354 if (SHIFT_COUNT_TRUNCATED)
2357 val = ((unsigned HOST_WIDE_INT) arg0) >> arg1;
2364 if (SHIFT_COUNT_TRUNCATED)
2367 val = ((unsigned HOST_WIDE_INT) arg0) << arg1;
2374 if (SHIFT_COUNT_TRUNCATED)
2377 val = arg0s >> arg1;
2379 /* Bootstrap compiler may not have sign extended the right shift.
2380 Manually extend the sign to insure bootstrap cc matches gcc. */
2381 if (arg0s < 0 && arg1 > 0)
2382 val |= ((HOST_WIDE_INT) -1) << (HOST_BITS_PER_WIDE_INT - arg1);
2391 val = ((((unsigned HOST_WIDE_INT) arg0) << (width - arg1))
2392 | (((unsigned HOST_WIDE_INT) arg0) >> arg1));
2400 val = ((((unsigned HOST_WIDE_INT) arg0) << arg1)
2401 | (((unsigned HOST_WIDE_INT) arg0) >> (width - arg1)));
2405 /* Do nothing here. */
2409 val = arg0s <= arg1s ? arg0s : arg1s;
2413 val = ((unsigned HOST_WIDE_INT) arg0
2414 <= (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
2418 val = arg0s > arg1s ? arg0s : arg1s;
2422 val = ((unsigned HOST_WIDE_INT) arg0
2423 > (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
2430 /* ??? There are simplifications that can be done. */
2437 val = trunc_int_for_mode (val, mode);
2439 return GEN_INT (val);
2442 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
2445 Rather than test for specific case, we do this by a brute-force method
2446 and do all possible simplifications until no more changes occur. Then
2447 we rebuild the operation.
2449 If FORCE is true, then always generate the rtx. This is used to
2450 canonicalize stuff emitted from simplify_gen_binary. Note that this
2451 can still fail if the rtx is too complex. It won't fail just because
2452 the result is not 'simpler' than the input, however. */
2454 struct simplify_plus_minus_op_data
2461 simplify_plus_minus_op_data_cmp (const void *p1, const void *p2)
2463 const struct simplify_plus_minus_op_data *d1 = p1;
2464 const struct simplify_plus_minus_op_data *d2 = p2;
2466 return (commutative_operand_precedence (d2->op)
2467 - commutative_operand_precedence (d1->op));
2471 simplify_plus_minus (enum rtx_code code, enum machine_mode mode, rtx op0,
2474 struct simplify_plus_minus_op_data ops[8];
2476 int n_ops = 2, input_ops = 2, input_consts = 0, n_consts;
2480 memset (ops, 0, sizeof ops);
2482 /* Set up the two operands and then expand them until nothing has been
2483 changed. If we run out of room in our array, give up; this should
2484 almost never happen. */
2489 ops[1].neg = (code == MINUS);
2495 for (i = 0; i < n_ops; i++)
2497 rtx this_op = ops[i].op;
2498 int this_neg = ops[i].neg;
2499 enum rtx_code this_code = GET_CODE (this_op);
2508 ops[n_ops].op = XEXP (this_op, 1);
2509 ops[n_ops].neg = (this_code == MINUS) ^ this_neg;
2512 ops[i].op = XEXP (this_op, 0);
2518 ops[i].op = XEXP (this_op, 0);
2519 ops[i].neg = ! this_neg;
2525 && GET_CODE (XEXP (this_op, 0)) == PLUS
2526 && CONSTANT_P (XEXP (XEXP (this_op, 0), 0))
2527 && CONSTANT_P (XEXP (XEXP (this_op, 0), 1)))
2529 ops[i].op = XEXP (XEXP (this_op, 0), 0);
2530 ops[n_ops].op = XEXP (XEXP (this_op, 0), 1);
2531 ops[n_ops].neg = this_neg;
2539 /* ~a -> (-a - 1) */
2542 ops[n_ops].op = constm1_rtx;
2543 ops[n_ops++].neg = this_neg;
2544 ops[i].op = XEXP (this_op, 0);
2545 ops[i].neg = !this_neg;
2553 ops[i].op = neg_const_int (mode, this_op);
2566 /* If we only have two operands, we can't do anything. */
2567 if (n_ops <= 2 && !force)
2570 /* Count the number of CONSTs we didn't split above. */
2571 for (i = 0; i < n_ops; i++)
2572 if (GET_CODE (ops[i].op) == CONST)
2575 /* Now simplify each pair of operands until nothing changes. The first
2576 time through just simplify constants against each other. */
2583 for (i = 0; i < n_ops - 1; i++)
2584 for (j = i + 1; j < n_ops; j++)
2586 rtx lhs = ops[i].op, rhs = ops[j].op;
2587 int lneg = ops[i].neg, rneg = ops[j].neg;
2589 if (lhs != 0 && rhs != 0
2590 && (! first || (CONSTANT_P (lhs) && CONSTANT_P (rhs))))
2592 enum rtx_code ncode = PLUS;
2598 tem = lhs, lhs = rhs, rhs = tem;
2600 else if (swap_commutative_operands_p (lhs, rhs))
2601 tem = lhs, lhs = rhs, rhs = tem;
2603 tem = simplify_binary_operation (ncode, mode, lhs, rhs);
2605 /* Reject "simplifications" that just wrap the two
2606 arguments in a CONST. Failure to do so can result
2607 in infinite recursion with simplify_binary_operation
2608 when it calls us to simplify CONST operations. */
2610 && ! (GET_CODE (tem) == CONST
2611 && GET_CODE (XEXP (tem, 0)) == ncode
2612 && XEXP (XEXP (tem, 0), 0) == lhs
2613 && XEXP (XEXP (tem, 0), 1) == rhs)
2614 /* Don't allow -x + -1 -> ~x simplifications in the
2615 first pass. This allows us the chance to combine
2616 the -1 with other constants. */
2618 && GET_CODE (tem) == NOT
2619 && XEXP (tem, 0) == rhs))
2622 if (GET_CODE (tem) == NEG)
2623 tem = XEXP (tem, 0), lneg = !lneg;
2624 if (GET_CODE (tem) == CONST_INT && lneg)
2625 tem = neg_const_int (mode, tem), lneg = 0;
2629 ops[j].op = NULL_RTX;
2639 /* Pack all the operands to the lower-numbered entries. */
2640 for (i = 0, j = 0; j < n_ops; j++)
2645 /* Sort the operations based on swap_commutative_operands_p. */
2646 qsort (ops, n_ops, sizeof (*ops), simplify_plus_minus_op_data_cmp);
2648 /* Create (minus -C X) instead of (neg (const (plus X C))). */
2650 && GET_CODE (ops[1].op) == CONST_INT
2651 && CONSTANT_P (ops[0].op)
2653 return gen_rtx_fmt_ee (MINUS, mode, ops[1].op, ops[0].op);
2655 /* We suppressed creation of trivial CONST expressions in the
2656 combination loop to avoid recursion. Create one manually now.
2657 The combination loop should have ensured that there is exactly
2658 one CONST_INT, and the sort will have ensured that it is last
2659 in the array and that any other constant will be next-to-last. */
2662 && GET_CODE (ops[n_ops - 1].op) == CONST_INT
2663 && CONSTANT_P (ops[n_ops - 2].op))
2665 rtx value = ops[n_ops - 1].op;
2666 if (ops[n_ops - 1].neg ^ ops[n_ops - 2].neg)
2667 value = neg_const_int (mode, value);
2668 ops[n_ops - 2].op = plus_constant (ops[n_ops - 2].op, INTVAL (value));
2672 /* Count the number of CONSTs that we generated. */
2674 for (i = 0; i < n_ops; i++)
2675 if (GET_CODE (ops[i].op) == CONST)
2678 /* Give up if we didn't reduce the number of operands we had. Make
2679 sure we count a CONST as two operands. If we have the same
2680 number of operands, but have made more CONSTs than before, this
2681 is also an improvement, so accept it. */
2683 && (n_ops + n_consts > input_ops
2684 || (n_ops + n_consts == input_ops && n_consts <= input_consts)))
2687 /* Put a non-negated operand first, if possible. */
2689 for (i = 0; i < n_ops && ops[i].neg; i++)
2692 ops[0].op = gen_rtx_NEG (mode, ops[0].op);
2701 /* Now make the result by performing the requested operations. */
2703 for (i = 1; i < n_ops; i++)
2704 result = gen_rtx_fmt_ee (ops[i].neg ? MINUS : PLUS,
2705 mode, result, ops[i].op);
2710 /* Like simplify_binary_operation except used for relational operators.
2711 MODE is the mode of the result. If MODE is VOIDmode, both operands must
2714 CMP_MODE specifies in which mode the comparison is done in, so it is
2715 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
2716 the operands or, if both are VOIDmode, the operands are compared in
2717 "infinite precision". */
2719 simplify_relational_operation (enum rtx_code code, enum machine_mode mode,
2720 enum machine_mode cmp_mode, rtx op0, rtx op1)
2722 rtx tem, trueop0, trueop1;
2724 if (cmp_mode == VOIDmode)
2725 cmp_mode = GET_MODE (op0);
2726 if (cmp_mode == VOIDmode)
2727 cmp_mode = GET_MODE (op1);
2729 tem = simplify_const_relational_operation (code, cmp_mode, op0, op1);
2732 #ifdef FLOAT_STORE_FLAG_VALUE
2733 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2735 if (tem == const0_rtx)
2736 return CONST0_RTX (mode);
2737 else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2739 REAL_VALUE_TYPE val;
2740 val = FLOAT_STORE_FLAG_VALUE (mode);
2741 return CONST_DOUBLE_FROM_REAL_VALUE (val, mode);
2749 /* For the following tests, ensure const0_rtx is op1. */
2750 if (swap_commutative_operands_p (op0, op1)
2751 || (op0 == const0_rtx && op1 != const0_rtx))
2752 tem = op0, op0 = op1, op1 = tem, code = swap_condition (code);
2754 /* If op0 is a compare, extract the comparison arguments from it. */
2755 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
2756 return simplify_relational_operation (code, mode, VOIDmode,
2757 XEXP (op0, 0), XEXP (op0, 1));
2759 if (mode == VOIDmode
2760 || GET_MODE_CLASS (cmp_mode) == MODE_CC
2764 trueop0 = avoid_constant_pool_reference (op0);
2765 trueop1 = avoid_constant_pool_reference (op1);
2766 return simplify_relational_operation_1 (code, mode, cmp_mode,
2770 /* This part of simplify_relational_operation is only used when CMP_MODE
2771 is not in class MODE_CC (i.e. it is a real comparison).
2773 MODE is the mode of the result, while CMP_MODE specifies in which
2774 mode the comparison is done in, so it is the mode of the operands. */
2776 simplify_relational_operation_1 (enum rtx_code code, enum machine_mode mode,
2777 enum machine_mode cmp_mode, rtx op0, rtx op1)
2779 if (GET_CODE (op1) == CONST_INT)
2781 if (INTVAL (op1) == 0 && COMPARISON_P (op0))
2783 /* If op0 is a comparison, extract the comparison arguments form it. */
2786 if (GET_MODE (op0) == cmp_mode)
2787 return simplify_rtx (op0);
2789 return simplify_gen_relational (GET_CODE (op0), mode, VOIDmode,
2790 XEXP (op0, 0), XEXP (op0, 1));
2792 else if (code == EQ)
2794 enum rtx_code new = reversed_comparison_code (op0, NULL_RTX);
2796 return simplify_gen_relational (new, mode, VOIDmode,
2797 XEXP (op0, 0), XEXP (op0, 1));
2805 /* Check if the given comparison (done in the given MODE) is actually a
2806 tautology or a contradiction.
2807 If no simplification is possible, this function returns zero.
2808 Otherwise, it returns either const_true_rtx or const0_rtx. */
2811 simplify_const_relational_operation (enum rtx_code code,
2812 enum machine_mode mode,
2815 int equal, op0lt, op0ltu, op1lt, op1ltu;
2820 if (mode == VOIDmode
2821 && (GET_MODE (op0) != VOIDmode
2822 || GET_MODE (op1) != VOIDmode))
2825 /* If op0 is a compare, extract the comparison arguments from it. */
2826 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
2827 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
2829 /* We can't simplify MODE_CC values since we don't know what the
2830 actual comparison is. */
2831 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC || CC0_P (op0))
2834 /* Make sure the constant is second. */
2835 if (swap_commutative_operands_p (op0, op1))
2837 tem = op0, op0 = op1, op1 = tem;
2838 code = swap_condition (code);
2841 trueop0 = avoid_constant_pool_reference (op0);
2842 trueop1 = avoid_constant_pool_reference (op1);
2844 /* For integer comparisons of A and B maybe we can simplify A - B and can
2845 then simplify a comparison of that with zero. If A and B are both either
2846 a register or a CONST_INT, this can't help; testing for these cases will
2847 prevent infinite recursion here and speed things up.
2849 If CODE is an unsigned comparison, then we can never do this optimization,
2850 because it gives an incorrect result if the subtraction wraps around zero.
2851 ANSI C defines unsigned operations such that they never overflow, and
2852 thus such cases can not be ignored; but we cannot do it even for
2853 signed comparisons for languages such as Java, so test flag_wrapv. */
2855 if (!flag_wrapv && INTEGRAL_MODE_P (mode) && trueop1 != const0_rtx
2856 && ! ((REG_P (op0) || GET_CODE (trueop0) == CONST_INT)
2857 && (REG_P (op1) || GET_CODE (trueop1) == CONST_INT))
2858 && 0 != (tem = simplify_binary_operation (MINUS, mode, op0, op1))
2859 /* We cannot do this for == or != if tem is a nonzero address. */
2860 && ((code != EQ && code != NE) || ! nonzero_address_p (tem))
2861 && code != GTU && code != GEU && code != LTU && code != LEU)
2862 return simplify_const_relational_operation (signed_condition (code),
2863 mode, tem, const0_rtx);
2865 if (flag_unsafe_math_optimizations && code == ORDERED)
2866 return const_true_rtx;
2868 if (flag_unsafe_math_optimizations && code == UNORDERED)
2871 /* For modes without NaNs, if the two operands are equal, we know the
2872 result except if they have side-effects. */
2873 if (! HONOR_NANS (GET_MODE (trueop0))
2874 && rtx_equal_p (trueop0, trueop1)
2875 && ! side_effects_p (trueop0))
2876 equal = 1, op0lt = 0, op0ltu = 0, op1lt = 0, op1ltu = 0;
2878 /* If the operands are floating-point constants, see if we can fold
2880 else if (GET_CODE (trueop0) == CONST_DOUBLE
2881 && GET_CODE (trueop1) == CONST_DOUBLE
2882 && GET_MODE_CLASS (GET_MODE (trueop0)) == MODE_FLOAT)
2884 REAL_VALUE_TYPE d0, d1;
2886 REAL_VALUE_FROM_CONST_DOUBLE (d0, trueop0);
2887 REAL_VALUE_FROM_CONST_DOUBLE (d1, trueop1);
2889 /* Comparisons are unordered iff at least one of the values is NaN. */
2890 if (REAL_VALUE_ISNAN (d0) || REAL_VALUE_ISNAN (d1))
2900 return const_true_rtx;
2913 equal = REAL_VALUES_EQUAL (d0, d1);
2914 op0lt = op0ltu = REAL_VALUES_LESS (d0, d1);
2915 op1lt = op1ltu = REAL_VALUES_LESS (d1, d0);
2918 /* Otherwise, see if the operands are both integers. */
2919 else if ((GET_MODE_CLASS (mode) == MODE_INT || mode == VOIDmode)
2920 && (GET_CODE (trueop0) == CONST_DOUBLE
2921 || GET_CODE (trueop0) == CONST_INT)
2922 && (GET_CODE (trueop1) == CONST_DOUBLE
2923 || GET_CODE (trueop1) == CONST_INT))
2925 int width = GET_MODE_BITSIZE (mode);
2926 HOST_WIDE_INT l0s, h0s, l1s, h1s;
2927 unsigned HOST_WIDE_INT l0u, h0u, l1u, h1u;
2929 /* Get the two words comprising each integer constant. */
2930 if (GET_CODE (trueop0) == CONST_DOUBLE)
2932 l0u = l0s = CONST_DOUBLE_LOW (trueop0);
2933 h0u = h0s = CONST_DOUBLE_HIGH (trueop0);
2937 l0u = l0s = INTVAL (trueop0);
2938 h0u = h0s = HWI_SIGN_EXTEND (l0s);
2941 if (GET_CODE (trueop1) == CONST_DOUBLE)
2943 l1u = l1s = CONST_DOUBLE_LOW (trueop1);
2944 h1u = h1s = CONST_DOUBLE_HIGH (trueop1);
2948 l1u = l1s = INTVAL (trueop1);
2949 h1u = h1s = HWI_SIGN_EXTEND (l1s);
2952 /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
2953 we have to sign or zero-extend the values. */
2954 if (width != 0 && width < HOST_BITS_PER_WIDE_INT)
2956 l0u &= ((HOST_WIDE_INT) 1 << width) - 1;
2957 l1u &= ((HOST_WIDE_INT) 1 << width) - 1;
2959 if (l0s & ((HOST_WIDE_INT) 1 << (width - 1)))
2960 l0s |= ((HOST_WIDE_INT) (-1) << width);
2962 if (l1s & ((HOST_WIDE_INT) 1 << (width - 1)))
2963 l1s |= ((HOST_WIDE_INT) (-1) << width);
2965 if (width != 0 && width <= HOST_BITS_PER_WIDE_INT)
2966 h0u = h1u = 0, h0s = HWI_SIGN_EXTEND (l0s), h1s = HWI_SIGN_EXTEND (l1s);
2968 equal = (h0u == h1u && l0u == l1u);
2969 op0lt = (h0s < h1s || (h0s == h1s && l0u < l1u));
2970 op1lt = (h1s < h0s || (h1s == h0s && l1u < l0u));
2971 op0ltu = (h0u < h1u || (h0u == h1u && l0u < l1u));
2972 op1ltu = (h1u < h0u || (h1u == h0u && l1u < l0u));
2975 /* Otherwise, there are some code-specific tests we can make. */
2978 /* Optimize comparisons with upper and lower bounds. */
2979 if (INTEGRAL_MODE_P (mode)
2980 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2993 get_mode_bounds (mode, sign, mode, &mmin, &mmax);
3000 /* x >= min is always true. */
3001 if (rtx_equal_p (trueop1, mmin))
3002 tem = const_true_rtx;
3008 /* x <= max is always true. */
3009 if (rtx_equal_p (trueop1, mmax))
3010 tem = const_true_rtx;
3015 /* x > max is always false. */
3016 if (rtx_equal_p (trueop1, mmax))
3022 /* x < min is always false. */
3023 if (rtx_equal_p (trueop1, mmin))
3030 if (tem == const0_rtx
3031 || tem == const_true_rtx)
3038 if (trueop1 == const0_rtx && nonzero_address_p (op0))
3043 if (trueop1 == const0_rtx && nonzero_address_p (op0))
3044 return const_true_rtx;
3048 /* Optimize abs(x) < 0.0. */
3049 if (trueop1 == CONST0_RTX (mode) && !HONOR_SNANS (mode))
3051 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
3053 if (GET_CODE (tem) == ABS)
3059 /* Optimize abs(x) >= 0.0. */
3060 if (trueop1 == CONST0_RTX (mode) && !HONOR_NANS (mode))
3062 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
3064 if (GET_CODE (tem) == ABS)
3065 return const_true_rtx;
3070 /* Optimize ! (abs(x) < 0.0). */
3071 if (trueop1 == CONST0_RTX (mode))
3073 tem = GET_CODE (trueop0) == FLOAT_EXTEND ? XEXP (trueop0, 0)
3075 if (GET_CODE (tem) == ABS)
3076 return const_true_rtx;
3087 /* If we reach here, EQUAL, OP0LT, OP0LTU, OP1LT, and OP1LTU are set
3093 return equal ? const_true_rtx : const0_rtx;
3096 return ! equal ? const_true_rtx : const0_rtx;
3099 return op0lt ? const_true_rtx : const0_rtx;
3102 return op1lt ? const_true_rtx : const0_rtx;
3104 return op0ltu ? const_true_rtx : const0_rtx;
3106 return op1ltu ? const_true_rtx : const0_rtx;
3109 return equal || op0lt ? const_true_rtx : const0_rtx;
3112 return equal || op1lt ? const_true_rtx : const0_rtx;
3114 return equal || op0ltu ? const_true_rtx : const0_rtx;
3116 return equal || op1ltu ? const_true_rtx : const0_rtx;
3118 return const_true_rtx;
3126 /* Simplify CODE, an operation with result mode MODE and three operands,
3127 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
3128 a constant. Return 0 if no simplifications is possible. */
3131 simplify_ternary_operation (enum rtx_code code, enum machine_mode mode,
3132 enum machine_mode op0_mode, rtx op0, rtx op1,
3135 unsigned int width = GET_MODE_BITSIZE (mode);
3137 /* VOIDmode means "infinite" precision. */
3139 width = HOST_BITS_PER_WIDE_INT;
3145 if (GET_CODE (op0) == CONST_INT
3146 && GET_CODE (op1) == CONST_INT
3147 && GET_CODE (op2) == CONST_INT
3148 && ((unsigned) INTVAL (op1) + (unsigned) INTVAL (op2) <= width)
3149 && width <= (unsigned) HOST_BITS_PER_WIDE_INT)
3151 /* Extracting a bit-field from a constant */
3152 HOST_WIDE_INT val = INTVAL (op0);
3154 if (BITS_BIG_ENDIAN)
3155 val >>= (GET_MODE_BITSIZE (op0_mode)
3156 - INTVAL (op2) - INTVAL (op1));
3158 val >>= INTVAL (op2);
3160 if (HOST_BITS_PER_WIDE_INT != INTVAL (op1))
3162 /* First zero-extend. */
3163 val &= ((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1;
3164 /* If desired, propagate sign bit. */
3165 if (code == SIGN_EXTRACT
3166 && (val & ((HOST_WIDE_INT) 1 << (INTVAL (op1) - 1))))
3167 val |= ~ (((HOST_WIDE_INT) 1 << INTVAL (op1)) - 1);
3170 /* Clear the bits that don't belong in our mode,
3171 unless they and our sign bit are all one.
3172 So we get either a reasonable negative value or a reasonable
3173 unsigned value for this mode. */
3174 if (width < HOST_BITS_PER_WIDE_INT
3175 && ((val & ((HOST_WIDE_INT) (-1) << (width - 1)))
3176 != ((HOST_WIDE_INT) (-1) << (width - 1))))
3177 val &= ((HOST_WIDE_INT) 1 << width) - 1;
3179 return GEN_INT (val);
3184 if (GET_CODE (op0) == CONST_INT)
3185 return op0 != const0_rtx ? op1 : op2;
3187 /* Convert c ? a : a into "a". */
3188 if (rtx_equal_p (op1, op2) && ! side_effects_p (op0))
3191 /* Convert a != b ? a : b into "a". */
3192 if (GET_CODE (op0) == NE
3193 && ! side_effects_p (op0)
3194 && ! HONOR_NANS (mode)
3195 && ! HONOR_SIGNED_ZEROS (mode)
3196 && ((rtx_equal_p (XEXP (op0, 0), op1)
3197 && rtx_equal_p (XEXP (op0, 1), op2))
3198 || (rtx_equal_p (XEXP (op0, 0), op2)
3199 && rtx_equal_p (XEXP (op0, 1), op1))))
3202 /* Convert a == b ? a : b into "b". */
3203 if (GET_CODE (op0) == EQ
3204 && ! side_effects_p (op0)
3205 && ! HONOR_NANS (mode)
3206 && ! HONOR_SIGNED_ZEROS (mode)
3207 && ((rtx_equal_p (XEXP (op0, 0), op1)
3208 && rtx_equal_p (XEXP (op0, 1), op2))
3209 || (rtx_equal_p (XEXP (op0, 0), op2)
3210 && rtx_equal_p (XEXP (op0, 1), op1))))
3213 if (COMPARISON_P (op0) && ! side_effects_p (op0))
3215 enum machine_mode cmp_mode = (GET_MODE (XEXP (op0, 0)) == VOIDmode
3216 ? GET_MODE (XEXP (op0, 1))
3217 : GET_MODE (XEXP (op0, 0)));
3220 /* Look for happy constants in op1 and op2. */
3221 if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
3223 HOST_WIDE_INT t = INTVAL (op1);
3224 HOST_WIDE_INT f = INTVAL (op2);
3226 if (t == STORE_FLAG_VALUE && f == 0)
3227 code = GET_CODE (op0);
3228 else if (t == 0 && f == STORE_FLAG_VALUE)
3231 tmp = reversed_comparison_code (op0, NULL_RTX);
3239 return simplify_gen_relational (code, mode, cmp_mode,
3240 XEXP (op0, 0), XEXP (op0, 1));
3243 if (cmp_mode == VOIDmode)
3244 cmp_mode = op0_mode;
3245 temp = simplify_relational_operation (GET_CODE (op0), op0_mode,
3246 cmp_mode, XEXP (op0, 0),
3249 /* See if any simplifications were possible. */
3252 if (GET_CODE (temp) == CONST_INT)
3253 return temp == const0_rtx ? op2 : op1;
3255 return gen_rtx_IF_THEN_ELSE (mode, temp, op1, op2);
3261 if (GET_MODE (op0) != mode
3262 || GET_MODE (op1) != mode
3263 || !VECTOR_MODE_P (mode))
3265 op2 = avoid_constant_pool_reference (op2);
3266 if (GET_CODE (op2) == CONST_INT)
3268 int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
3269 unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
3270 int mask = (1 << n_elts) - 1;
3272 if (!(INTVAL (op2) & mask))
3274 if ((INTVAL (op2) & mask) == mask)
3277 op0 = avoid_constant_pool_reference (op0);
3278 op1 = avoid_constant_pool_reference (op1);
3279 if (GET_CODE (op0) == CONST_VECTOR
3280 && GET_CODE (op1) == CONST_VECTOR)
3282 rtvec v = rtvec_alloc (n_elts);
3285 for (i = 0; i < n_elts; i++)
3286 RTVEC_ELT (v, i) = (INTVAL (op2) & (1 << i)
3287 ? CONST_VECTOR_ELT (op0, i)
3288 : CONST_VECTOR_ELT (op1, i));
3289 return gen_rtx_CONST_VECTOR (mode, v);
3301 /* Evaluate a SUBREG of a CONST_INT or CONST_DOUBLE or CONST_VECTOR,
3302 returning another CONST_INT or CONST_DOUBLE or CONST_VECTOR.
3304 Works by unpacking OP into a collection of 8-bit values
3305 represented as a little-endian array of 'unsigned char', selecting by BYTE,
3306 and then repacking them again for OUTERMODE. */
3309 simplify_immed_subreg (enum machine_mode outermode, rtx op,
3310 enum machine_mode innermode, unsigned int byte)
3312 /* We support up to 512-bit values (for V8DFmode). */
3316 value_mask = (1 << value_bit) - 1
3318 unsigned char value[max_bitsize / value_bit];
3327 rtvec result_v = NULL;
3328 enum mode_class outer_class;
3329 enum machine_mode outer_submode;
3331 /* Some ports misuse CCmode. */
3332 if (GET_MODE_CLASS (outermode) == MODE_CC && GET_CODE (op) == CONST_INT)
3335 /* Unpack the value. */
3337 if (GET_CODE (op) == CONST_VECTOR)
3339 num_elem = CONST_VECTOR_NUNITS (op);
3340 elems = &CONST_VECTOR_ELT (op, 0);
3341 elem_bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (innermode));
3347 elem_bitsize = max_bitsize;
3350 if (BITS_PER_UNIT % value_bit != 0)
3351 abort (); /* Too complicated; reducing value_bit may help. */
3352 if (elem_bitsize % BITS_PER_UNIT != 0)
3353 abort (); /* I don't know how to handle endianness of sub-units. */
3355 for (elem = 0; elem < num_elem; elem++)
3358 rtx el = elems[elem];
3360 /* Vectors are kept in target memory order. (This is probably
3363 unsigned byte = (elem * elem_bitsize) / BITS_PER_UNIT;
3364 unsigned ibyte = (((num_elem - 1 - elem) * elem_bitsize)
3366 unsigned word_byte = WORDS_BIG_ENDIAN ? ibyte : byte;
3367 unsigned subword_byte = BYTES_BIG_ENDIAN ? ibyte : byte;
3368 unsigned bytele = (subword_byte % UNITS_PER_WORD
3369 + (word_byte / UNITS_PER_WORD) * UNITS_PER_WORD);
3370 vp = value + (bytele * BITS_PER_UNIT) / value_bit;
3373 switch (GET_CODE (el))
3377 i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize;
3379 *vp++ = INTVAL (el) >> i;
3380 /* CONST_INTs are always logically sign-extended. */
3381 for (; i < elem_bitsize; i += value_bit)
3382 *vp++ = INTVAL (el) < 0 ? -1 : 0;
3386 if (GET_MODE (el) == VOIDmode)
3388 /* If this triggers, someone should have generated a
3389 CONST_INT instead. */
3390 if (elem_bitsize <= HOST_BITS_PER_WIDE_INT)
3393 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i += value_bit)
3394 *vp++ = CONST_DOUBLE_LOW (el) >> i;
3395 while (i < HOST_BITS_PER_WIDE_INT * 2 && i < elem_bitsize)
3398 = CONST_DOUBLE_HIGH (el) >> (i - HOST_BITS_PER_WIDE_INT);
3401 /* It shouldn't matter what's done here, so fill it with
3403 for (; i < max_bitsize; i += value_bit)
3406 else if (GET_MODE_CLASS (GET_MODE (el)) == MODE_FLOAT)
3408 long tmp[max_bitsize / 32];
3409 int bitsize = GET_MODE_BITSIZE (GET_MODE (el));
3411 if (bitsize > elem_bitsize)
3413 if (bitsize % value_bit != 0)
3416 real_to_target (tmp, CONST_DOUBLE_REAL_VALUE (el),
3419 /* real_to_target produces its result in words affected by
3420 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
3421 and use WORDS_BIG_ENDIAN instead; see the documentation
3422 of SUBREG in rtl.texi. */
3423 for (i = 0; i < bitsize; i += value_bit)
3426 if (WORDS_BIG_ENDIAN)
3427 ibase = bitsize - 1 - i;
3430 *vp++ = tmp[ibase / 32] >> i % 32;
3433 /* It shouldn't matter what's done here, so fill it with
3435 for (; i < elem_bitsize; i += value_bit)
3447 /* Now, pick the right byte to start with. */
3448 /* Renumber BYTE so that the least-significant byte is byte 0. A special
3449 case is paradoxical SUBREGs, which shouldn't be adjusted since they
3450 will already have offset 0. */
3451 if (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode))
3453 unsigned ibyte = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)
3455 unsigned word_byte = WORDS_BIG_ENDIAN ? ibyte : byte;
3456 unsigned subword_byte = BYTES_BIG_ENDIAN ? ibyte : byte;
3457 byte = (subword_byte % UNITS_PER_WORD
3458 + (word_byte / UNITS_PER_WORD) * UNITS_PER_WORD);
3461 /* BYTE should still be inside OP. (Note that BYTE is unsigned,
3462 so if it's become negative it will instead be very large.) */
3463 if (byte >= GET_MODE_SIZE (innermode))
3466 /* Convert from bytes to chunks of size value_bit. */
3467 value_start = byte * (BITS_PER_UNIT / value_bit);
3469 /* Re-pack the value. */
3471 if (VECTOR_MODE_P (outermode))
3473 num_elem = GET_MODE_NUNITS (outermode);
3474 result_v = rtvec_alloc (num_elem);
3475 elems = &RTVEC_ELT (result_v, 0);
3476 outer_submode = GET_MODE_INNER (outermode);
3482 outer_submode = outermode;
3485 outer_class = GET_MODE_CLASS (outer_submode);
3486 elem_bitsize = GET_MODE_BITSIZE (outer_submode);
3488 if (elem_bitsize % value_bit != 0)
3490 if (elem_bitsize + value_start * value_bit > max_bitsize)
3493 for (elem = 0; elem < num_elem; elem++)
3497 /* Vectors are stored in target memory order. (This is probably
3500 unsigned byte = (elem * elem_bitsize) / BITS_PER_UNIT;
3501 unsigned ibyte = (((num_elem - 1 - elem) * elem_bitsize)
3503 unsigned word_byte = WORDS_BIG_ENDIAN ? ibyte : byte;
3504 unsigned subword_byte = BYTES_BIG_ENDIAN ? ibyte : byte;
3505 unsigned bytele = (subword_byte % UNITS_PER_WORD
3506 + (word_byte / UNITS_PER_WORD) * UNITS_PER_WORD);
3507 vp = value + value_start + (bytele * BITS_PER_UNIT) / value_bit;
3510 switch (outer_class)
3513 case MODE_PARTIAL_INT:
3515 unsigned HOST_WIDE_INT hi = 0, lo = 0;
3518 i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize;
3520 lo |= (HOST_WIDE_INT)(*vp++ & value_mask) << i;
3521 for (; i < elem_bitsize; i += value_bit)
3522 hi |= ((HOST_WIDE_INT)(*vp++ & value_mask)
3523 << (i - HOST_BITS_PER_WIDE_INT));
3525 /* immed_double_const doesn't call trunc_int_for_mode. I don't
3527 if (elem_bitsize <= HOST_BITS_PER_WIDE_INT)
3528 elems[elem] = gen_int_mode (lo, outer_submode);
3530 elems[elem] = immed_double_const (lo, hi, outer_submode);
3537 long tmp[max_bitsize / 32];
3539 /* real_from_target wants its input in words affected by
3540 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
3541 and use WORDS_BIG_ENDIAN instead; see the documentation
3542 of SUBREG in rtl.texi. */
3543 for (i = 0; i < max_bitsize / 32; i++)
3545 for (i = 0; i < elem_bitsize; i += value_bit)
3548 if (WORDS_BIG_ENDIAN)
3549 ibase = elem_bitsize - 1 - i;
3552 tmp[ibase / 32] |= (*vp++ & value_mask) << i % 32;
3555 real_from_target (&r, tmp, outer_submode);
3556 elems[elem] = CONST_DOUBLE_FROM_REAL_VALUE (r, outer_submode);
3564 if (VECTOR_MODE_P (outermode))
3565 return gen_rtx_CONST_VECTOR (outermode, result_v);
3570 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
3571 Return 0 if no simplifications are possible. */
3573 simplify_subreg (enum machine_mode outermode, rtx op,
3574 enum machine_mode innermode, unsigned int byte)
3576 /* Little bit of sanity checking. */
3577 if (innermode == VOIDmode || outermode == VOIDmode
3578 || innermode == BLKmode || outermode == BLKmode)
3581 if (GET_MODE (op) != innermode
3582 && GET_MODE (op) != VOIDmode)
3585 if (byte % GET_MODE_SIZE (outermode)
3586 || byte >= GET_MODE_SIZE (innermode))
3589 if (outermode == innermode && !byte)
3592 if (GET_CODE (op) == CONST_INT
3593 || GET_CODE (op) == CONST_DOUBLE
3594 || GET_CODE (op) == CONST_VECTOR)
3595 return simplify_immed_subreg (outermode, op, innermode, byte);
3597 /* Changing mode twice with SUBREG => just change it once,
3598 or not at all if changing back op starting mode. */
3599 if (GET_CODE (op) == SUBREG)
3601 enum machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
3602 int final_offset = byte + SUBREG_BYTE (op);
3605 if (outermode == innermostmode
3606 && byte == 0 && SUBREG_BYTE (op) == 0)
3607 return SUBREG_REG (op);
3609 /* The SUBREG_BYTE represents offset, as if the value were stored
3610 in memory. Irritating exception is paradoxical subreg, where
3611 we define SUBREG_BYTE to be 0. On big endian machines, this
3612 value should be negative. For a moment, undo this exception. */
3613 if (byte == 0 && GET_MODE_SIZE (innermode) < GET_MODE_SIZE (outermode))
3615 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
3616 if (WORDS_BIG_ENDIAN)
3617 final_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
3618 if (BYTES_BIG_ENDIAN)
3619 final_offset += difference % UNITS_PER_WORD;
3621 if (SUBREG_BYTE (op) == 0
3622 && GET_MODE_SIZE (innermostmode) < GET_MODE_SIZE (innermode))
3624 int difference = (GET_MODE_SIZE (innermostmode) - GET_MODE_SIZE (innermode));
3625 if (WORDS_BIG_ENDIAN)
3626 final_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
3627 if (BYTES_BIG_ENDIAN)
3628 final_offset += difference % UNITS_PER_WORD;
3631 /* See whether resulting subreg will be paradoxical. */
3632 if (GET_MODE_SIZE (innermostmode) > GET_MODE_SIZE (outermode))
3634 /* In nonparadoxical subregs we can't handle negative offsets. */
3635 if (final_offset < 0)
3637 /* Bail out in case resulting subreg would be incorrect. */
3638 if (final_offset % GET_MODE_SIZE (outermode)
3639 || (unsigned) final_offset >= GET_MODE_SIZE (innermostmode))
3645 int difference = (GET_MODE_SIZE (innermostmode) - GET_MODE_SIZE (outermode));
3647 /* In paradoxical subreg, see if we are still looking on lower part.
3648 If so, our SUBREG_BYTE will be 0. */
3649 if (WORDS_BIG_ENDIAN)
3650 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
3651 if (BYTES_BIG_ENDIAN)
3652 offset += difference % UNITS_PER_WORD;
3653 if (offset == final_offset)
3659 /* Recurse for further possible simplifications. */
3660 new = simplify_subreg (outermode, SUBREG_REG (op),
3661 GET_MODE (SUBREG_REG (op)),
3665 return gen_rtx_SUBREG (outermode, SUBREG_REG (op), final_offset);
3668 /* SUBREG of a hard register => just change the register number
3669 and/or mode. If the hard register is not valid in that mode,
3670 suppress this simplification. If the hard register is the stack,
3671 frame, or argument pointer, leave this as a SUBREG. */
3674 && (! REG_FUNCTION_VALUE_P (op)
3675 || ! rtx_equal_function_value_matters)
3676 && REGNO (op) < FIRST_PSEUDO_REGISTER
3677 #ifdef CANNOT_CHANGE_MODE_CLASS
3678 && ! (REG_CANNOT_CHANGE_MODE_P (REGNO (op), innermode, outermode)
3679 && GET_MODE_CLASS (innermode) != MODE_COMPLEX_INT
3680 && GET_MODE_CLASS (innermode) != MODE_COMPLEX_FLOAT)
3682 && ((reload_completed && !frame_pointer_needed)
3683 || (REGNO (op) != FRAME_POINTER_REGNUM
3684 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3685 && REGNO (op) != HARD_FRAME_POINTER_REGNUM
3688 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3689 && REGNO (op) != ARG_POINTER_REGNUM
3691 && REGNO (op) != STACK_POINTER_REGNUM
3692 && subreg_offset_representable_p (REGNO (op), innermode,
3695 rtx tem = gen_rtx_SUBREG (outermode, op, byte);
3696 int final_regno = subreg_hard_regno (tem, 0);
3698 /* ??? We do allow it if the current REG is not valid for
3699 its mode. This is a kludge to work around how float/complex
3700 arguments are passed on 32-bit SPARC and should be fixed. */
3701 if (HARD_REGNO_MODE_OK (final_regno, outermode)
3702 || ! HARD_REGNO_MODE_OK (REGNO (op), innermode))
3704 rtx x = gen_rtx_REG_offset (op, outermode, final_regno, byte);
3706 /* Propagate original regno. We don't have any way to specify
3707 the offset inside original regno, so do so only for lowpart.
3708 The information is used only by alias analysis that can not
3709 grog partial register anyway. */
3711 if (subreg_lowpart_offset (outermode, innermode) == byte)
3712 ORIGINAL_REGNO (x) = ORIGINAL_REGNO (op);
3717 /* If we have a SUBREG of a register that we are replacing and we are
3718 replacing it with a MEM, make a new MEM and try replacing the
3719 SUBREG with it. Don't do this if the MEM has a mode-dependent address
3720 or if we would be widening it. */
3722 if (GET_CODE (op) == MEM
3723 && ! mode_dependent_address_p (XEXP (op, 0))
3724 /* Allow splitting of volatile memory references in case we don't
3725 have instruction to move the whole thing. */
3726 && (! MEM_VOLATILE_P (op)
3727 || ! have_insn_for (SET, innermode))
3728 && GET_MODE_SIZE (outermode) <= GET_MODE_SIZE (GET_MODE (op)))
3729 return adjust_address_nv (op, outermode, byte);
3731 /* Handle complex values represented as CONCAT
3732 of real and imaginary part. */
3733 if (GET_CODE (op) == CONCAT)
3735 int is_realpart = byte < (unsigned int) GET_MODE_UNIT_SIZE (innermode);
3736 rtx part = is_realpart ? XEXP (op, 0) : XEXP (op, 1);
3737 unsigned int final_offset;
3740 final_offset = byte % (GET_MODE_UNIT_SIZE (innermode));
3741 res = simplify_subreg (outermode, part, GET_MODE (part), final_offset);
3744 /* We can at least simplify it by referring directly to the
3746 return gen_rtx_SUBREG (outermode, part, final_offset);
3749 /* Optimize SUBREG truncations of zero and sign extended values. */
3750 if ((GET_CODE (op) == ZERO_EXTEND
3751 || GET_CODE (op) == SIGN_EXTEND)
3752 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode))
3754 unsigned int bitpos = subreg_lsb_1 (outermode, innermode, byte);
3756 /* If we're requesting the lowpart of a zero or sign extension,
3757 there are three possibilities. If the outermode is the same
3758 as the origmode, we can omit both the extension and the subreg.
3759 If the outermode is not larger than the origmode, we can apply
3760 the truncation without the extension. Finally, if the outermode
3761 is larger than the origmode, but both are integer modes, we
3762 can just extend to the appropriate mode. */
3765 enum machine_mode origmode = GET_MODE (XEXP (op, 0));
3766 if (outermode == origmode)
3767 return XEXP (op, 0);
3768 if (GET_MODE_BITSIZE (outermode) <= GET_MODE_BITSIZE (origmode))
3769 return simplify_gen_subreg (outermode, XEXP (op, 0), origmode,
3770 subreg_lowpart_offset (outermode,
3772 if (SCALAR_INT_MODE_P (outermode))
3773 return simplify_gen_unary (GET_CODE (op), outermode,
3774 XEXP (op, 0), origmode);
3777 /* A SUBREG resulting from a zero extension may fold to zero if
3778 it extracts higher bits that the ZERO_EXTEND's source bits. */
3779 if (GET_CODE (op) == ZERO_EXTEND
3780 && bitpos >= GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))))
3781 return CONST0_RTX (outermode);
3787 /* Make a SUBREG operation or equivalent if it folds. */
3790 simplify_gen_subreg (enum machine_mode outermode, rtx op,
3791 enum machine_mode innermode, unsigned int byte)
3794 /* Little bit of sanity checking. */
3795 if (innermode == VOIDmode || outermode == VOIDmode
3796 || innermode == BLKmode || outermode == BLKmode)
3799 if (GET_MODE (op) != innermode
3800 && GET_MODE (op) != VOIDmode)
3803 if (byte % GET_MODE_SIZE (outermode)
3804 || byte >= GET_MODE_SIZE (innermode))
3807 if (GET_CODE (op) == QUEUED)
3810 new = simplify_subreg (outermode, op, innermode, byte);
3814 if (GET_CODE (op) == SUBREG || GET_MODE (op) == VOIDmode)
3817 return gen_rtx_SUBREG (outermode, op, byte);
3819 /* Simplify X, an rtx expression.
3821 Return the simplified expression or NULL if no simplifications
3824 This is the preferred entry point into the simplification routines;
3825 however, we still allow passes to call the more specific routines.
3827 Right now GCC has three (yes, three) major bodies of RTL simplification
3828 code that need to be unified.
3830 1. fold_rtx in cse.c. This code uses various CSE specific
3831 information to aid in RTL simplification.
3833 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
3834 it uses combine specific information to aid in RTL
3837 3. The routines in this file.
3840 Long term we want to only have one body of simplification code; to
3841 get to that state I recommend the following steps:
3843 1. Pour over fold_rtx & simplify_rtx and move any simplifications
3844 which are not pass dependent state into these routines.
3846 2. As code is moved by #1, change fold_rtx & simplify_rtx to
3847 use this routine whenever possible.
3849 3. Allow for pass dependent state to be provided to these
3850 routines and add simplifications based on the pass dependent
3851 state. Remove code from cse.c & combine.c that becomes
3854 It will take time, but ultimately the compiler will be easier to
3855 maintain and improve. It's totally silly that when we add a
3856 simplification that it needs to be added to 4 places (3 for RTL
3857 simplification and 1 for tree simplification. */
3860 simplify_rtx (rtx x)
3862 enum rtx_code code = GET_CODE (x);
3863 enum machine_mode mode = GET_MODE (x);
3865 switch (GET_RTX_CLASS (code))
3868 return simplify_unary_operation (code, mode,
3869 XEXP (x, 0), GET_MODE (XEXP (x, 0)));
3870 case RTX_COMM_ARITH:
3871 if (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3872 return simplify_gen_binary (code, mode, XEXP (x, 1), XEXP (x, 0));
3874 /* Fall through.... */
3877 return simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3880 case RTX_BITFIELD_OPS:
3881 return simplify_ternary_operation (code, mode, GET_MODE (XEXP (x, 0)),
3882 XEXP (x, 0), XEXP (x, 1),
3886 case RTX_COMM_COMPARE:
3887 return simplify_relational_operation (code, mode,
3888 ((GET_MODE (XEXP (x, 0))
3890 ? GET_MODE (XEXP (x, 0))
3891 : GET_MODE (XEXP (x, 1))),
3897 return simplify_gen_subreg (mode, SUBREG_REG (x),
3898 GET_MODE (SUBREG_REG (x)),
3905 /* Convert (lo_sum (high FOO) FOO) to FOO. */
3906 if (GET_CODE (XEXP (x, 0)) == HIGH
3907 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))