1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
40 #include "tree-pass.h"
41 #include "sched-int.h"
45 #include "langhooks.h"
46 #include "rtlhooks-def.h"
49 #ifdef INSN_SCHEDULING
50 #include "sel-sched-ir.h"
51 #include "sel-sched-dump.h"
52 #include "sel-sched.h"
55 /* Implementation of selective scheduling approach.
56 The below implementation follows the original approach with the following
59 o the scheduler works after register allocation (but can be also tuned
61 o some instructions are not copied or register renamed;
62 o conditional jumps are not moved with code duplication;
63 o several jumps in one parallel group are not supported;
64 o when pipelining outer loops, code motion through inner loops
66 o control and data speculation are supported;
67 o some improvements for better compile time/performance were made.
72 A vinsn, or virtual insn, is an insn with additional data characterizing
73 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
74 Vinsns also act as smart pointers to save memory by reusing them in
75 different expressions. A vinsn is described by vinsn_t type.
77 An expression is a vinsn with additional data characterizing its properties
78 at some point in the control flow graph. The data may be its usefulness,
79 priority, speculative status, whether it was renamed/subsituted, etc.
80 An expression is described by expr_t type.
82 Availability set (av_set) is a set of expressions at a given control flow
83 point. It is represented as av_set_t. The expressions in av sets are kept
84 sorted in the terms of expr_greater_p function. It allows to truncate
85 the set while leaving the best expressions.
87 A fence is a point through which code motion is prohibited. On each step,
88 we gather a parallel group of insns at a fence. It is possible to have
89 multiple fences. A fence is represented via fence_t.
91 A boundary is the border between the fence group and the rest of the code.
92 Currently, we never have more than one boundary per fence, as we finalize
93 the fence group when a jump is scheduled. A boundary is represented
99 The scheduler finds regions to schedule, schedules each one, and finalizes.
100 The regions are formed starting from innermost loops, so that when the inner
101 loop is pipelined, its prologue can be scheduled together with yet unprocessed
102 outer loop. The rest of acyclic regions are found using extend_rgns:
103 the blocks that are not yet allocated to any regions are traversed in top-down
104 order, and a block is added to a region to which all its predecessors belong;
105 otherwise, the block starts its own region.
107 The main scheduling loop (sel_sched_region_2) consists of just
108 scheduling on each fence and updating fences. For each fence,
109 we fill a parallel group of insns (fill_insns) until some insns can be added.
110 First, we compute available exprs (av-set) at the boundary of the current
111 group. Second, we choose the best expression from it. If the stall is
112 required to schedule any of the expressions, we advance the current cycle
113 appropriately. So, the final group does not exactly correspond to a VLIW
114 word. Third, we move the chosen expression to the boundary (move_op)
115 and update the intermediate av sets and liveness sets. We quit fill_insns
116 when either no insns left for scheduling or we have scheduled enough insns
117 so we feel like advancing a scheduling point.
119 Computing available expressions
120 ===============================
122 The computation (compute_av_set) is a bottom-up traversal. At each insn,
123 we're moving the union of its successors' sets through it via
124 moveup_expr_set. The dependent expressions are removed. Local
125 transformations (substitution, speculation) are applied to move more
126 exprs. Then the expr corresponding to the current insn is added.
127 The result is saved on each basic block header.
129 When traversing the CFG, we're moving down for no more than max_ws insns.
130 Also, we do not move down to ineligible successors (is_ineligible_successor),
131 which include moving along a back-edge, moving to already scheduled code,
132 and moving to another fence. The first two restrictions are lifted during
133 pipelining, which allows us to move insns along a back-edge. We always have
134 an acyclic region for scheduling because we forbid motion through fences.
136 Choosing the best expression
137 ============================
139 We sort the final availability set via sel_rank_for_schedule, then we remove
140 expressions which are not yet ready (tick_check_p) or which dest registers
141 cannot be used. For some of them, we choose another register via
142 find_best_reg. To do this, we run find_used_regs to calculate the set of
143 registers which cannot be used. The find_used_regs function performs
144 a traversal of code motion paths for an expr. We consider for renaming
145 only registers which are from the same regclass as the original one and
146 using which does not interfere with any live ranges. Finally, we convert
147 the resulting set to the ready list format and use max_issue and reorder*
148 hooks similarly to the Haifa scheduler.
150 Scheduling the best expression
151 ==============================
153 We run the move_op routine to perform the same type of code motion paths
154 traversal as in find_used_regs. (These are working via the same driver,
155 code_motion_path_driver.) When moving down the CFG, we look for original
156 instruction that gave birth to a chosen expression. We undo
157 the transformations performed on an expression via the history saved in it.
158 When found, we remove the instruction or leave a reg-reg copy/speculation
159 check if needed. On a way up, we insert bookkeeping copies at each join
160 point. If a copy is not needed, it will be removed later during this
161 traversal. We update the saved av sets and liveness sets on the way up, too.
163 Finalizing the schedule
164 =======================
166 When pipelining, we reschedule the blocks from which insns were pipelined
167 to get a tighter schedule. On Itanium, we also perform bundling via
168 the same routine from ia64.c.
170 Dependence analysis changes
171 ===========================
173 We augmented the sched-deps.c with hooks that get called when a particular
174 dependence is found in a particular part of an insn. Using these hooks, we
175 can do several actions such as: determine whether an insn can be moved through
176 another (has_dependence_p, moveup_expr); find out whether an insn can be
177 scheduled on the current cycle (tick_check_p); find out registers that
178 are set/used/clobbered by an insn and find out all the strange stuff that
179 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
180 init_global_and_expr_for_insn).
182 Initialization changes
183 ======================
185 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
186 reused in all of the schedulers. We have split up the initialization of data
187 of such parts into different functions prefixed with scheduler type and
188 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
189 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
190 The same splitting is done with current_sched_info structure:
191 dependence-related parts are in sched_deps_info, common part is in
192 common_sched_info, and haifa/sel/etc part is in current_sched_info.
197 As we now have multiple-point scheduling, this would not work with backends
198 which save some of the scheduler state to use it in the target hooks.
199 For this purpose, we introduce a concept of target contexts, which
200 encapsulate such information. The backend should implement simple routines
201 of allocating/freeing/setting such a context. The scheduler calls these
202 as target hooks and handles the target context as an opaque pointer (similar
203 to the DFA state type, state_t).
208 As the correct data dependence graph is not supported during scheduling (which
209 is to be changed in mid-term), we cache as much of the dependence analysis
210 results as possible to avoid reanalyzing. This includes: bitmap caches on
211 each insn in stream of the region saying yes/no for a query with a pair of
212 UIDs; hashtables with the previously done transformations on each insn in
213 stream; a vector keeping a history of transformations on each expr.
215 Also, we try to minimize the dependence context used on each fence to check
216 whether the given expression is ready for scheduling by removing from it
217 insns that are definitely completed the execution. The results of
218 tick_check_p checks are also cached in a vector on each fence.
220 We keep a valid liveness set on each insn in a region to avoid the high
221 cost of recomputation on large basic blocks.
223 Finally, we try to minimize the number of needed updates to the availability
224 sets. The updates happen in two cases: when fill_insns terminates,
225 we advance all fences and increase the stage number to show that the region
226 has changed and the sets are to be recomputed; and when the next iteration
227 of a loop in fill_insns happens (but this one reuses the saved av sets
228 on bb headers.) Thus, we try to break the fill_insns loop only when
229 "significant" number of insns from the current scheduling window was
230 scheduled. This should be made a target param.
233 TODO: correctly support the data dependence graph at all stages and get rid
234 of all caches. This should speed up the scheduler.
235 TODO: implement moving cond jumps with bookkeeping copies on both targets.
236 TODO: tune the scheduler before RA so it does not create too much pseudos.
240 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
241 selective scheduling and software pipelining.
242 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
244 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
245 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
246 for GCC. In Proceedings of GCC Developers' Summit 2006.
248 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
249 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
250 http://rogue.colorado.edu/EPIC7/.
254 /* True when pipelining is enabled. */
257 /* True if bookkeeping is enabled. */
260 /* Maximum number of insns that are eligible for renaming. */
261 int max_insns_to_rename;
264 /* Definitions of local types and macros. */
266 /* Represents possible outcomes of moving an expression through an insn. */
267 enum MOVEUP_EXPR_CODE
269 /* The expression is not changed. */
272 /* Not changed, but requires a new destination register. */
275 /* Cannot be moved. */
278 /* Changed (substituted or speculated). */
282 /* The container to be passed into rtx search & replace functions. */
283 struct rtx_search_arg
285 /* What we are searching for. */
288 /* The occurence counter. */
292 typedef struct rtx_search_arg *rtx_search_arg_p;
294 /* This struct contains precomputed hard reg sets that are needed when
295 computing registers available for renaming. */
296 struct hard_regs_data
298 /* For every mode, this stores registers available for use with
300 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
302 /* True when regs_for_mode[mode] is initialized. */
303 bool regs_for_mode_ok[NUM_MACHINE_MODES];
305 /* For every register, it has regs that are ok to rename into it.
306 The register in question is always set. If not, this means
307 that the whole set is not computed yet. */
308 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
310 /* For every mode, this stores registers not available due to
312 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
314 /* All registers that are used or call used. */
315 HARD_REG_SET regs_ever_used;
318 /* Stack registers. */
319 HARD_REG_SET stack_regs;
323 /* Holds the results of computation of available for renaming and
324 unavailable hard registers. */
327 /* These are unavailable due to calls crossing, globalness, etc. */
328 HARD_REG_SET unavailable_hard_regs;
330 /* These are *available* for renaming. */
331 HARD_REG_SET available_for_renaming;
333 /* Whether this code motion path crosses a call. */
337 /* A global structure that contains the needed information about harg
339 static struct hard_regs_data sel_hrd;
342 /* This structure holds local data used in code_motion_path_driver hooks on
343 the same or adjacent levels of recursion. Here we keep those parameters
344 that are not used in code_motion_path_driver routine itself, but only in
345 its hooks. Moreover, all parameters that can be modified in hooks are
346 in this structure, so all other parameters passed explicitly to hooks are
348 struct cmpd_local_params
350 /* Local params used in move_op_* functions. */
352 /* Edges for bookkeeping generation. */
355 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
356 expr_t c_expr_merged, c_expr_local;
358 /* Local params used in fur_* functions. */
359 /* Copy of the ORIGINAL_INSN list, stores the original insns already
360 found before entering the current level of code_motion_path_driver. */
361 def_list_t old_original_insns;
363 /* Local params used in move_op_* functions. */
364 /* True when we have removed last insn in the block which was
365 also a boundary. Do not update anything or create bookkeeping copies. */
366 BOOL_BITFIELD removed_last_insn : 1;
369 /* Stores the static parameters for move_op_* calls. */
370 struct moveop_static_params
372 /* Destination register. */
375 /* Current C_EXPR. */
378 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
379 they are to be removed. */
382 #ifdef ENABLE_CHECKING
383 /* This is initialized to the insn on which the driver stopped its traversal. */
387 /* True if we scheduled an insn with different register. */
391 /* Stores the static parameters for fur_* calls. */
392 struct fur_static_params
394 /* Set of registers unavailable on the code motion path. */
397 /* Pointer to the list of original insns definitions. */
398 def_list_t *original_insns;
400 /* True if a code motion path contains a CALL insn. */
404 typedef struct fur_static_params *fur_static_params_p;
405 typedef struct cmpd_local_params *cmpd_local_params_p;
406 typedef struct moveop_static_params *moveop_static_params_p;
408 /* Set of hooks and parameters that determine behaviour specific to
409 move_op or find_used_regs functions. */
410 struct code_motion_path_driver_info_def
412 /* Called on enter to the basic block. */
413 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
415 /* Called when original expr is found. */
416 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
418 /* Called while descending current basic block if current insn is not
419 the original EXPR we're searching for. */
420 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
422 /* Function to merge C_EXPRes from different successors. */
423 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
425 /* Function to finalize merge from different successors and possibly
426 deallocate temporary data structures used for merging. */
427 void (*after_merge_succs) (cmpd_local_params_p, void *);
429 /* Called on the backward stage of recursion to do moveup_expr.
430 Used only with move_op_*. */
431 void (*ascend) (insn_t, void *);
433 /* Called on the ascending pass, before returning from the current basic
434 block or from the whole traversal. */
435 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
437 /* When processing successors in move_op we need only descend into
438 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
441 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
442 const char *routine_name;
445 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
447 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
449 /* Set of hooks for performing move_op and find_used_regs routines with
450 code_motion_path_driver. */
451 extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
453 /* True if/when we want to emulate Haifa scheduler in the common code.
454 This is used in sched_rgn_local_init and in various places in
456 int sched_emulate_haifa_p;
458 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
459 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
460 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
461 scheduling window. */
464 /* Current fences. */
467 /* True when separable insns should be scheduled as RHSes. */
468 static bool enable_schedule_as_rhs_p;
470 /* Used in verify_target_availability to assert that target reg is reported
471 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
472 we haven't scheduled anything on the previous fence.
473 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
474 have more conservative value than the one returned by the
475 find_used_regs, thus we shouldn't assert that these values are equal. */
476 static bool scheduled_something_on_previous_fence;
478 /* All newly emitted insns will have their uids greater than this value. */
479 static int first_emitted_uid;
481 /* Set of basic blocks that are forced to start new ebbs. This is a subset
482 of all the ebb heads. */
483 static bitmap_head _forced_ebb_heads;
484 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
486 /* Blocks that need to be rescheduled after pipelining. */
487 bitmap blocks_to_reschedule = NULL;
489 /* True when the first lv set should be ignored when updating liveness. */
490 static bool ignore_first = false;
492 /* Number of insns max_issue has initialized data structures for. */
493 static int max_issue_size = 0;
495 /* Whether we can issue more instructions. */
496 static int can_issue_more;
498 /* Maximum software lookahead window size, reduced when rescheduling after
502 /* Number of insns scheduled in current region. */
503 static int num_insns_scheduled;
505 /* A vector of expressions is used to be able to sort them. */
507 DEF_VEC_ALLOC_P(expr_t,heap);
508 static VEC(expr_t, heap) *vec_av_set = NULL;
510 /* A vector of vinsns is used to hold temporary lists of vinsns. */
512 DEF_VEC_ALLOC_P(vinsn_t,heap);
513 typedef VEC(vinsn_t, heap) *vinsn_vec_t;
515 /* This vector has the exprs which may still present in av_sets, but actually
516 can't be moved up due to bookkeeping created during code motion to another
517 fence. See comment near the call to update_and_record_unavailable_insns
518 for the detailed explanations. */
519 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = NULL;
521 /* This vector has vinsns which are scheduled with renaming on the first fence
522 and then seen on the second. For expressions with such vinsns, target
523 availability information may be wrong. */
524 static vinsn_vec_t vec_target_unavailable_vinsns = NULL;
526 /* Vector to store temporary nops inserted in move_op to prevent removal
529 DEF_VEC_ALLOC_P(insn_t,heap);
530 static VEC(insn_t, heap) *vec_temp_moveop_nops = NULL;
532 /* These bitmaps record original instructions scheduled on the current
533 iteration and bookkeeping copies created by them. */
534 static bitmap current_originators = NULL;
535 static bitmap current_copies = NULL;
537 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
538 visit them afterwards. */
539 static bitmap code_motion_visited_blocks = NULL;
541 /* Variables to accumulate different statistics. */
543 /* The number of bookkeeping copies created. */
544 static int stat_bookkeeping_copies;
546 /* The number of insns that required bookkeeiping for their scheduling. */
547 static int stat_insns_needed_bookkeeping;
549 /* The number of insns that got renamed. */
550 static int stat_renamed_scheduled;
552 /* The number of substitutions made during scheduling. */
553 static int stat_substitutions_total;
556 /* Forward declarations of static functions. */
557 static bool rtx_ok_for_substitution_p (rtx, rtx);
558 static int sel_rank_for_schedule (const void *, const void *);
559 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
560 static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax);
562 static rtx get_dest_from_orig_ops (av_set_t);
563 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
564 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
566 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
567 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
568 cmpd_local_params_p, void *);
569 static void sel_sched_region_1 (void);
570 static void sel_sched_region_2 (int);
571 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
573 static void debug_state (state_t);
576 /* Functions that work with fences. */
578 /* Advance one cycle on FENCE. */
580 advance_one_cycle (fence_t fence)
586 advance_state (FENCE_STATE (fence));
587 cycle = ++FENCE_CYCLE (fence);
588 FENCE_ISSUED_INSNS (fence) = 0;
589 FENCE_STARTS_CYCLE_P (fence) = 1;
590 can_issue_more = issue_rate;
591 FENCE_ISSUE_MORE (fence) = can_issue_more;
593 for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); )
595 if (INSN_READY_CYCLE (insn) < cycle)
597 remove_from_deps (FENCE_DC (fence), insn);
598 VEC_unordered_remove (rtx, FENCE_EXECUTING_INSNS (fence), i);
603 if (sched_verbose >= 2)
605 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
606 debug_state (FENCE_STATE (fence));
610 /* Returns true when SUCC in a fallthru bb of INSN, possibly
611 skipping empty basic blocks. */
613 in_fallthru_bb_p (rtx insn, rtx succ)
615 basic_block bb = BLOCK_FOR_INSN (insn);
617 if (bb == BLOCK_FOR_INSN (succ))
620 if (find_fallthru_edge (bb))
621 bb = find_fallthru_edge (bb)->dest;
625 while (sel_bb_empty_p (bb))
628 return bb == BLOCK_FOR_INSN (succ);
631 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
632 When a successor will continue a ebb, transfer all parameters of a fence
633 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
634 of scheduling helping to distinguish between the old and the new code. */
636 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
639 bool was_here_p = false;
640 insn_t insn = NULL_RTX;
644 fence_t fence = FLIST_FENCE (old_fences);
647 /* Get the only element of FENCE_BNDS (fence). */
648 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
650 gcc_assert (!was_here_p);
653 gcc_assert (was_here_p && insn != NULL_RTX);
655 /* When in the "middle" of the block, just move this fence
657 bb = BLOCK_FOR_INSN (insn);
658 if (! sel_bb_end_p (insn)
659 || (single_succ_p (bb)
660 && single_pred_p (single_succ (bb))))
664 succ = (sel_bb_end_p (insn)
665 ? sel_bb_head (single_succ (bb))
668 if (INSN_SEQNO (succ) > 0
669 && INSN_SEQNO (succ) <= orig_max_seqno
670 && INSN_SCHED_TIMES (succ) <= 0)
672 FENCE_INSN (fence) = succ;
673 move_fence_to_fences (old_fences, new_fences);
675 if (sched_verbose >= 1)
676 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
677 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
682 /* Otherwise copy fence's structures to (possibly) multiple successors. */
683 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
685 int seqno = INSN_SEQNO (succ);
687 if (0 < seqno && seqno <= orig_max_seqno
688 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
690 bool b = (in_same_ebb_p (insn, succ)
691 || in_fallthru_bb_p (insn, succ));
693 if (sched_verbose >= 1)
694 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
695 INSN_UID (insn), INSN_UID (succ),
696 BLOCK_NUM (succ), b ? "continue" : "reset");
699 add_dirty_fence_to_fences (new_fences, succ, fence);
702 /* Mark block of the SUCC as head of the new ebb. */
703 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
704 add_clean_fence_to_fences (new_fences, succ, fence);
711 /* Functions to support substitution. */
713 /* Returns whether INSN with dependence status DS is eligible for
714 substitution, i.e. it's a copy operation x := y, and RHS that is
715 moved up through this insn should be substituted. */
717 can_substitute_through_p (insn_t insn, ds_t ds)
719 /* We can substitute only true dependencies. */
720 if ((ds & DEP_OUTPUT)
723 || ! INSN_LHS (insn))
726 /* Now we just need to make sure the INSN_RHS consists of only one
728 if (REG_P (INSN_LHS (insn))
729 && REG_P (INSN_RHS (insn)))
734 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
735 source (if INSN is eligible for substitution). Returns TRUE if
736 substitution was actually performed, FALSE otherwise. Substitution might
737 be not performed because it's either EXPR' vinsn doesn't contain INSN's
738 destination or the resulting insn is invalid for the target machine.
739 When UNDO is true, perform unsubstitution instead (the difference is in
740 the part of rtx on which validate_replace_rtx is called). */
742 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
746 vinsn_t *vi = &EXPR_VINSN (expr);
747 bool has_rhs = VINSN_RHS (*vi) != NULL;
750 /* Do not try to replace in SET_DEST. Although we'll choose new
751 register for the RHS, we don't want to change RHS' original reg.
752 If the insn is not SET, we may still be able to substitute something
753 in it, and if we're here (don't have deps), it doesn't write INSN's
757 : &PATTERN (VINSN_INSN_RTX (*vi)));
758 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
760 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
761 if (rtx_ok_for_substitution_p (old, *where))
766 /* We should copy these rtxes before substitution. */
767 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
768 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
770 /* Where we'll replace.
771 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
772 used instead of SET_SRC. */
773 where_replace = (has_rhs
774 ? &SET_SRC (PATTERN (new_insn))
775 : &PATTERN (new_insn));
778 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
781 /* ??? Actually, constrain_operands result depends upon choice of
782 destination register. E.g. if we allow single register to be an rhs,
783 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
784 in invalid insn dx=dx, so we'll loose this rhs here.
785 Just can't come up with significant testcase for this, so just
786 leaving it for now. */
789 change_vinsn_in_expr (expr,
790 create_vinsn_from_insn_rtx (new_insn, false));
792 /* Do not allow clobbering the address register of speculative
794 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
795 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr)),
796 expr_dest_regno (expr)))
797 EXPR_TARGET_AVAILABLE (expr) = false;
808 /* Helper function for count_occurences_equiv. */
810 count_occurrences_1 (rtx *cur_rtx, void *arg)
812 rtx_search_arg_p p = (rtx_search_arg_p) arg;
814 /* The last param FOR_GCSE is true, because otherwise it performs excessive
818 for the last insn it presumes r33 equivalent to r8, so it changes it to
819 r33. Actually, there's no change, but it spoils debugging. */
820 if (exp_equiv_p (*cur_rtx, p->x, 0, true))
822 /* Bail out if we occupy more than one register. */
824 && HARD_REGISTER_P (*cur_rtx)
825 && hard_regno_nregs[REGNO(*cur_rtx)][GET_MODE (*cur_rtx)] > 1)
833 /* Do not traverse subexprs. */
837 if (GET_CODE (*cur_rtx) == SUBREG
839 && REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x))
841 /* ??? Do not support substituting regs inside subregs. In that case,
842 simplify_subreg will be called by validate_replace_rtx, and
843 unsubstitution will fail later. */
848 /* Continue search. */
852 /* Return the number of places WHAT appears within WHERE.
853 Bail out when we found a reference occupying several hard registers. */
855 count_occurrences_equiv (rtx what, rtx where)
857 struct rtx_search_arg arg;
862 for_each_rtx (&where, &count_occurrences_1, (void *) &arg);
867 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
869 rtx_ok_for_substitution_p (rtx what, rtx where)
871 return (count_occurrences_equiv (what, where) > 0);
875 /* Functions to support register renaming. */
877 /* Substitute VI's set source with REGNO. Returns newly created pattern
878 that has REGNO as its source. */
880 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
886 lhs_rtx = copy_rtx (VINSN_LHS (vi));
888 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
889 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
894 /* Returns whether INSN's src can be replaced with register number
895 NEW_SRC_REG. E.g. the following insn is valid for i386:
897 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
898 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
899 (reg:SI 0 ax [orig:770 c1 ] [770]))
900 (const_int 288 [0x120])) [0 str S1 A8])
901 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
904 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
905 because of operand constraints:
907 (define_insn "*movqi_1"
908 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
909 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
912 So do constrain_operands here, before choosing NEW_SRC_REG as best
916 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
918 vinsn_t vi = INSN_VINSN (insn);
919 enum machine_mode mode;
923 gcc_assert (VINSN_SEPARABLE_P (vi));
925 get_dest_and_mode (insn, &dst_loc, &mode);
926 gcc_assert (mode == GET_MODE (new_src_reg));
928 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
931 /* See whether SET_SRC can be replaced with this register. */
932 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
933 res = verify_changes (0);
939 /* Returns whether INSN still be valid after replacing it's DEST with
942 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
944 vinsn_t vi = INSN_VINSN (insn);
947 /* We should deal here only with separable insns. */
948 gcc_assert (VINSN_SEPARABLE_P (vi));
949 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
951 /* See whether SET_DEST can be replaced with this register. */
952 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
953 res = verify_changes (0);
959 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
961 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
967 rhs_rtx = copy_rtx (VINSN_RHS (vi));
969 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
970 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
975 /* Substitute lhs in the given expression EXPR for the register with number
976 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
978 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
983 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
984 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
986 change_vinsn_in_expr (expr, vinsn);
987 EXPR_WAS_RENAMED (expr) = 1;
988 EXPR_TARGET_AVAILABLE (expr) = 1;
991 /* Returns whether VI writes either one of the USED_REGS registers or,
992 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
994 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
995 HARD_REG_SET unavailable_hard_regs)
998 reg_set_iterator rsi;
1000 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
1002 if (REGNO_REG_SET_P (used_regs, regno))
1004 if (HARD_REGISTER_NUM_P (regno)
1005 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1009 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
1011 if (REGNO_REG_SET_P (used_regs, regno))
1013 if (HARD_REGISTER_NUM_P (regno)
1014 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1021 /* Returns register class of the output register in INSN.
1022 Returns NO_REGS for call insns because some targets have constraints on
1023 destination register of a call insn.
1025 Code adopted from regrename.c::build_def_use. */
1026 static enum reg_class
1027 get_reg_class (rtx insn)
1031 extract_insn (insn);
1032 if (! constrain_operands (1))
1033 fatal_insn_not_found (insn);
1034 preprocess_constraints ();
1035 alt = which_alternative;
1036 n_ops = recog_data.n_operands;
1038 for (i = 0; i < n_ops; ++i)
1040 int matches = recog_op_alt[i][alt].matches;
1042 recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;
1045 if (asm_noperands (PATTERN (insn)) > 0)
1047 for (i = 0; i < n_ops; i++)
1048 if (recog_data.operand_type[i] == OP_OUT)
1050 rtx *loc = recog_data.operand_loc[i];
1052 enum reg_class cl = recog_op_alt[i][alt].cl;
1055 && REGNO (op) == ORIGINAL_REGNO (op))
1061 else if (!CALL_P (insn))
1063 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1065 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1066 enum reg_class cl = recog_op_alt[opn][alt].cl;
1068 if (recog_data.operand_type[opn] == OP_OUT ||
1069 recog_data.operand_type[opn] == OP_INOUT)
1075 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1076 may result in returning NO_REGS, cause flags is written implicitly through
1077 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1081 #ifdef HARD_REGNO_RENAME_OK
1082 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1084 init_hard_regno_rename (int regno)
1088 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1090 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1092 /* We are not interested in renaming in other regs. */
1093 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1096 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1097 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1102 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1105 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1107 #ifdef HARD_REGNO_RENAME_OK
1108 /* Check whether this is all calculated. */
1109 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1110 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1112 init_hard_regno_rename (from);
1114 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1120 /* Calculate set of registers that are capable of holding MODE. */
1122 init_regs_for_mode (enum machine_mode mode)
1126 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1127 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1129 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1131 int nregs = hard_regno_nregs[cur_reg][mode];
1134 for (i = nregs - 1; i >= 0; --i)
1135 if (fixed_regs[cur_reg + i]
1136 || global_regs[cur_reg + i]
1137 /* Can't use regs which aren't saved by
1139 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1140 #ifdef LEAF_REGISTERS
1141 /* We can't use a non-leaf register if we're in a
1143 || (current_function_is_leaf
1144 && !LEAF_REGISTERS[cur_reg + i])
1152 /* See whether it accepts all modes that occur in
1154 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1157 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1158 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1161 /* If the CUR_REG passed all the checks above,
1163 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1166 sel_hrd.regs_for_mode_ok[mode] = true;
1169 /* Init all register sets gathered in HRD. */
1171 init_hard_regs_data (void)
1176 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1177 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1178 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1179 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1181 /* Initialize registers that are valid based on mode when this is
1183 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1184 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1186 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1187 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1188 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1191 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1193 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1194 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1198 /* Mark hardware regs in REG_RENAME_P that are not suitable
1199 for renaming rhs in INSN due to hardware restrictions (register class,
1200 modes compatibility etc). This doesn't affect original insn's dest reg,
1201 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1202 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1203 Registers that are in used_regs are always marked in
1204 unavailable_hard_regs as well. */
1207 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1208 regset used_regs ATTRIBUTE_UNUSED)
1210 enum machine_mode mode;
1211 enum reg_class cl = NO_REGS;
1213 unsigned cur_reg, regno;
1214 hard_reg_set_iterator hrsi;
1216 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1217 gcc_assert (reg_rename_p);
1219 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1221 /* We have decided not to rename 'mem = something;' insns, as 'something'
1222 is usually a register. */
1223 if (!REG_P (orig_dest))
1226 regno = REGNO (orig_dest);
1228 /* If before reload, don't try to work with pseudos. */
1229 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1232 if (reload_completed)
1233 cl = get_reg_class (def->orig_insn);
1235 /* Stop if the original register is one of the fixed_regs, global_regs or
1236 frame pointer, or we could not discover its class. */
1237 if (fixed_regs[regno]
1238 || global_regs[regno]
1239 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1240 || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
1242 || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
1244 || (reload_completed && cl == NO_REGS))
1246 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1248 /* Give a chance for original register, if it isn't in used_regs. */
1249 if (!def->crosses_call)
1250 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1255 /* If something allocated on stack in this function, mark frame pointer
1256 register unavailable, considering also modes.
1257 FIXME: it is enough to do this once per all original defs. */
1258 if (frame_pointer_needed)
1262 for (i = hard_regno_nregs[FRAME_POINTER_REGNUM][Pmode]; i--;)
1263 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1264 FRAME_POINTER_REGNUM + i);
1266 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1267 for (i = hard_regno_nregs[HARD_FRAME_POINTER_REGNUM][Pmode]; i--;)
1268 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1269 HARD_FRAME_POINTER_REGNUM + i);
1274 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1275 is equivalent to as if all stack regs were in this set.
1276 I.e. no stack register can be renamed, and even if it's an original
1277 register here we make sure it won't be lifted over it's previous def
1278 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1279 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1280 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1281 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1282 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1283 sel_hrd.stack_regs);
1286 /* If there's a call on this path, make regs from call_used_reg_set
1288 if (def->crosses_call)
1289 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1292 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1293 but not register classes. */
1294 if (!reload_completed)
1297 /* Leave regs as 'available' only from the current
1299 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1300 reg_class_contents[cl]);
1302 mode = GET_MODE (orig_dest);
1304 /* Leave only registers available for this mode. */
1305 if (!sel_hrd.regs_for_mode_ok[mode])
1306 init_regs_for_mode (mode);
1307 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1308 sel_hrd.regs_for_mode[mode]);
1310 /* Exclude registers that are partially call clobbered. */
1311 if (def->crosses_call
1312 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1313 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1314 sel_hrd.regs_for_call_clobbered[mode]);
1316 /* Leave only those that are ok to rename. */
1317 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1323 nregs = hard_regno_nregs[cur_reg][mode];
1324 gcc_assert (nregs > 0);
1326 for (i = nregs - 1; i >= 0; --i)
1327 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1331 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1335 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1336 reg_rename_p->unavailable_hard_regs);
1338 /* Regno is always ok from the renaming part of view, but it really
1339 could be in *unavailable_hard_regs already, so set it here instead
1341 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1344 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1345 best register more recently than REG2. */
1346 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1348 /* Indicates the number of times renaming happened before the current one. */
1349 static int reg_rename_this_tick;
1351 /* Choose the register among free, that is suitable for storing
1354 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1355 originally appears. There could be multiple original operations
1356 for single rhs since we moving it up and merging along different
1359 Some code is adapted from regrename.c (regrename_optimize).
1360 If original register is available, function returns it.
1361 Otherwise it performs the checks, so the new register should
1362 comply with the following:
1363 - it should not violate any live ranges (such registers are in
1364 REG_RENAME_P->available_for_renaming set);
1365 - it should not be in the HARD_REGS_USED regset;
1366 - it should be in the class compatible with original uses;
1367 - it should not be clobbered through reference with different mode;
1368 - if we're in the leaf function, then the new register should
1369 not be in the LEAF_REGISTERS;
1372 If several registers meet the conditions, the register with smallest
1373 tick is returned to achieve more even register allocation.
1375 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1377 If no register satisfies the above conditions, NULL_RTX is returned. */
1379 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1380 struct reg_rename *reg_rename_p,
1381 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1385 enum machine_mode mode = VOIDmode;
1386 unsigned regno, i, n;
1387 hard_reg_set_iterator hrsi;
1388 def_list_iterator di;
1391 /* If original register is available, return it. */
1392 *is_orig_reg_p_ptr = true;
1394 FOR_EACH_DEF (def, di, original_insns)
1396 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1398 gcc_assert (REG_P (orig_dest));
1400 /* Check that all original operations have the same mode.
1401 This is done for the next loop; if we'd return from this
1402 loop, we'd check only part of them, but in this case
1403 it doesn't matter. */
1404 if (mode == VOIDmode)
1405 mode = GET_MODE (orig_dest);
1406 gcc_assert (mode == GET_MODE (orig_dest));
1408 regno = REGNO (orig_dest);
1409 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1410 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1413 /* All hard registers are available. */
1416 gcc_assert (mode != VOIDmode);
1418 /* Hard registers should not be shared. */
1419 return gen_rtx_REG (mode, regno);
1423 *is_orig_reg_p_ptr = false;
1426 /* Among all available regs choose the register that was
1427 allocated earliest. */
1428 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1430 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1432 /* All hard registers are available. */
1433 if (best_new_reg < 0
1434 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1436 best_new_reg = cur_reg;
1438 /* Return immediately when we know there's no better reg. */
1439 if (! reg_rename_tick[best_new_reg])
1444 if (best_new_reg >= 0)
1446 /* Use the check from the above loop. */
1447 gcc_assert (mode != VOIDmode);
1448 return gen_rtx_REG (mode, best_new_reg);
1454 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1455 assumptions about available registers in the function. */
1457 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1458 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1460 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1461 original_insns, is_orig_reg_p_ptr);
1463 gcc_assert (best_reg == NULL_RTX
1464 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1469 /* Choose the pseudo register for storing rhs value. As this is supposed
1470 to work before reload, we return either the original register or make
1471 the new one. The parameters are the same that in choose_nest_reg_1
1472 functions, except that USED_REGS may contain pseudos.
1473 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1475 TODO: take into account register pressure while doing this. Up to this
1476 moment, this function would never return NULL for pseudos, but we should
1477 not rely on this. */
1479 choose_best_pseudo_reg (regset used_regs,
1480 struct reg_rename *reg_rename_p,
1481 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1483 def_list_iterator i;
1485 enum machine_mode mode = VOIDmode;
1486 bool bad_hard_regs = false;
1488 /* We should not use this after reload. */
1489 gcc_assert (!reload_completed);
1491 /* If original register is available, return it. */
1492 *is_orig_reg_p_ptr = true;
1494 FOR_EACH_DEF (def, i, original_insns)
1496 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1499 gcc_assert (REG_P (dest));
1501 /* Check that all original operations have the same mode. */
1502 if (mode == VOIDmode)
1503 mode = GET_MODE (dest);
1505 gcc_assert (mode == GET_MODE (dest));
1506 orig_regno = REGNO (dest);
1508 if (!REGNO_REG_SET_P (used_regs, orig_regno))
1510 if (orig_regno < FIRST_PSEUDO_REGISTER)
1512 gcc_assert (df_regs_ever_live_p (orig_regno));
1514 /* For hard registers, we have to check hardware imposed
1515 limitations (frame/stack registers, calls crossed). */
1516 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1519 /* Don't let register cross a call if it doesn't already
1520 cross one. This condition is written in accordance with
1521 that in sched-deps.c sched_analyze_reg(). */
1522 if (!reg_rename_p->crosses_call
1523 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1524 return gen_rtx_REG (mode, orig_regno);
1527 bad_hard_regs = true;
1534 *is_orig_reg_p_ptr = false;
1536 /* We had some original hard registers that couldn't be used.
1537 Those were likely special. Don't try to create a pseudo. */
1541 /* We haven't found a register from original operations. Get a new one.
1542 FIXME: control register pressure somehow. */
1544 rtx new_reg = gen_reg_rtx (mode);
1546 gcc_assert (mode != VOIDmode);
1548 max_regno = max_reg_num ();
1549 maybe_extend_reg_info_p ();
1550 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1556 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1557 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1559 verify_target_availability (expr_t expr, regset used_regs,
1560 struct reg_rename *reg_rename_p)
1562 unsigned n, i, regno;
1563 enum machine_mode mode;
1564 bool target_available, live_available, hard_available;
1566 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1569 regno = expr_dest_regno (expr);
1570 mode = GET_MODE (EXPR_LHS (expr));
1571 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1572 n = reload_completed ? hard_regno_nregs[regno][mode] : 1;
1574 live_available = hard_available = true;
1575 for (i = 0; i < n; i++)
1577 if (bitmap_bit_p (used_regs, regno + i))
1578 live_available = false;
1579 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1580 hard_available = false;
1583 /* When target is not available, it may be due to hard register
1584 restrictions, e.g. crosses calls, so we check hard_available too. */
1585 if (target_available)
1586 gcc_assert (live_available);
1588 /* Check only if we haven't scheduled something on the previous fence,
1589 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1590 and having more than one fence, we may end having targ_un in a block
1591 in which successors target register is actually available.
1593 The last condition handles the case when a dependence from a call insn
1594 was created in sched-deps.c for insns with destination registers that
1595 never crossed a call before, but do cross one after our code motion.
1597 FIXME: in the latter case, we just uselessly called find_used_regs,
1598 because we can't move this expression with any other register
1600 gcc_assert (scheduled_something_on_previous_fence || !live_available
1602 || (!reload_completed && reg_rename_p->crosses_call
1603 && REG_N_CALLS_CROSSED (regno) == 0));
1606 /* Collect unavailable registers due to liveness for EXPR from BNDS
1607 into USED_REGS. Save additional information about available
1608 registers and unavailable due to hardware restriction registers
1609 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1612 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1613 struct reg_rename *reg_rename_p,
1614 def_list_t *original_insns)
1616 for (; bnds; bnds = BLIST_NEXT (bnds))
1619 av_set_t orig_ops = NULL;
1620 bnd_t bnd = BLIST_BND (bnds);
1622 /* If the chosen best expr doesn't belong to current boundary,
1624 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1627 /* Put in ORIG_OPS all exprs from this boundary that became
1629 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1631 /* Compute used regs and OR it into the USED_REGS. */
1632 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1633 reg_rename_p, original_insns);
1635 /* FIXME: the assert is true until we'd have several boundaries. */
1637 av_set_clear (&orig_ops);
1641 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1642 If BEST_REG is valid, replace LHS of EXPR with it. */
1644 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1646 /* Try whether we'll be able to generate the insn
1647 'dest := best_reg' at the place of the original operation. */
1648 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1650 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1652 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1654 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1655 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1656 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1660 /* Make sure that EXPR has the right destination
1662 if (expr_dest_regno (expr) != REGNO (best_reg))
1663 replace_dest_with_reg_in_expr (expr, best_reg);
1665 EXPR_TARGET_AVAILABLE (expr) = 1;
1670 /* Select and assign best register to EXPR searching from BNDS.
1671 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1672 Return FALSE if no register can be chosen, which could happen when:
1673 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1674 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1675 that are used on the moving path. */
1677 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1679 static struct reg_rename reg_rename_data;
1682 def_list_t original_insns = NULL;
1685 *is_orig_reg_p = false;
1687 /* Don't bother to do anything if this insn doesn't set any registers. */
1688 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1689 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1692 used_regs = get_clear_regset_from_pool ();
1693 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1695 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data,
1698 #ifdef ENABLE_CHECKING
1699 /* If after reload, make sure we're working with hard regs here. */
1700 if (reload_completed)
1702 reg_set_iterator rsi;
1705 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1710 if (EXPR_SEPARABLE_P (expr))
1712 rtx best_reg = NULL_RTX;
1713 /* Check that we have computed availability of a target register
1715 verify_target_availability (expr, used_regs, ®_rename_data);
1717 /* Turn everything in hard regs after reload. */
1718 if (reload_completed)
1720 HARD_REG_SET hard_regs_used;
1721 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1723 /* Join hard registers unavailable due to register class
1724 restrictions and live range intersection. */
1725 IOR_HARD_REG_SET (hard_regs_used,
1726 reg_rename_data.unavailable_hard_regs);
1728 best_reg = choose_best_reg (hard_regs_used, ®_rename_data,
1729 original_insns, is_orig_reg_p);
1732 best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data,
1733 original_insns, is_orig_reg_p);
1737 else if (*is_orig_reg_p)
1739 /* In case of unification BEST_REG may be different from EXPR's LHS
1740 when EXPR's LHS is unavailable, and there is another LHS among
1742 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1746 /* Forbid renaming of low-cost insns. */
1747 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1750 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1755 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1756 any of the HARD_REGS_USED set. */
1757 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1758 reg_rename_data.unavailable_hard_regs))
1761 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1766 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1770 ilist_clear (&original_insns);
1771 return_regset_to_pool (used_regs);
1777 /* Return true if dependence described by DS can be overcomed. */
1779 can_speculate_dep_p (ds_t ds)
1781 if (spec_info == NULL)
1784 /* Leave only speculative data. */
1791 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1792 that we can overcome. */
1793 ds_t spec_mask = spec_info->mask;
1795 if ((ds & spec_mask) != ds)
1799 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1805 /* Get a speculation check instruction.
1806 C_EXPR is a speculative expression,
1807 CHECK_DS describes speculations that should be checked,
1808 ORIG_INSN is the original non-speculative insn in the stream. */
1810 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1815 basic_block recovery_block;
1818 /* Create a recovery block if target is going to emit branchy check, or if
1819 ORIG_INSN was speculative already. */
1820 if (targetm.sched.needs_block_p (check_ds)
1821 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1823 recovery_block = sel_create_recovery_block (orig_insn);
1824 label = BB_HEAD (recovery_block);
1828 recovery_block = NULL;
1832 /* Get pattern of the check. */
1833 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1836 gcc_assert (check_pattern != NULL);
1839 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1841 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1842 INSN_SEQNO (orig_insn), orig_insn);
1844 /* Make check to be non-speculative. */
1845 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1846 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1848 /* Decrease priority of check by difference of load/check instruction
1850 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1851 - sel_vinsn_cost (INSN_VINSN (insn)));
1853 /* Emit copy of original insn (though with replaced target register,
1854 if needed) to the recovery block. */
1855 if (recovery_block != NULL)
1860 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1861 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1862 twin = sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1863 INSN_EXPR (orig_insn),
1865 bb_note (recovery_block));
1868 /* If we've generated a data speculation check, make sure
1869 that all the bookkeeping instruction we'll create during
1870 this move_op () will allocate an ALAT entry so that the
1872 In case of control speculation we must convert C_EXPR to control
1873 speculative mode, because failing to do so will bring us an exception
1874 thrown by the non-control-speculative load. */
1875 check_ds = ds_get_max_dep_weak (check_ds);
1876 speculate_expr (c_expr, check_ds);
1881 /* True when INSN is a "regN = regN" copy. */
1883 identical_copy_p (rtx insn)
1887 pat = PATTERN (insn);
1889 if (GET_CODE (pat) != SET)
1892 lhs = SET_DEST (pat);
1896 rhs = SET_SRC (pat);
1900 return REGNO (lhs) == REGNO (rhs);
1903 /* Undo all transformations on *AV_PTR that were done when
1904 moving through INSN. */
1906 undo_transformations (av_set_t *av_ptr, rtx insn)
1908 av_set_iterator av_iter;
1910 av_set_t new_set = NULL;
1912 /* First, kill any EXPR that uses registers set by an insn. This is
1913 required for correctness. */
1914 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1915 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1916 && bitmap_intersect_p (INSN_REG_SETS (insn),
1917 VINSN_REG_USES (EXPR_VINSN (expr)))
1918 /* When an insn looks like 'r1 = r1', we could substitute through
1919 it, but the above condition will still hold. This happened with
1920 gcc.c-torture/execute/961125-1.c. */
1921 && !identical_copy_p (insn))
1923 if (sched_verbose >= 6)
1924 sel_print ("Expr %d removed due to use/set conflict\n",
1925 INSN_UID (EXPR_INSN_RTX (expr)));
1926 av_set_iter_remove (&av_iter);
1929 /* Undo transformations looking at the history vector. */
1930 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1932 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1933 insn, EXPR_VINSN (expr), true);
1937 expr_history_def *phist;
1939 phist = VEC_index (expr_history_def,
1940 EXPR_HISTORY_OF_CHANGES (expr),
1943 switch (phist->type)
1945 case TRANS_SPECULATION:
1947 ds_t old_ds, new_ds;
1949 /* Compute the difference between old and new speculative
1950 statuses: that's what we need to check.
1951 Earlier we used to assert that the status will really
1952 change. This no longer works because only the probability
1953 bits in the status may have changed during compute_av_set,
1954 and in the case of merging different probabilities of the
1955 same speculative status along different paths we do not
1956 record this in the history vector. */
1957 old_ds = phist->spec_ds;
1958 new_ds = EXPR_SPEC_DONE_DS (expr);
1960 old_ds &= SPECULATIVE;
1961 new_ds &= SPECULATIVE;
1964 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1967 case TRANS_SUBSTITUTION:
1969 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1973 new_vi = phist->old_expr_vinsn;
1975 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1976 == EXPR_SEPARABLE_P (expr));
1977 copy_expr (tmp_expr, expr);
1979 if (vinsn_equal_p (phist->new_expr_vinsn,
1980 EXPR_VINSN (tmp_expr)))
1981 change_vinsn_in_expr (tmp_expr, new_vi);
1983 /* This happens when we're unsubstituting on a bookkeeping
1984 copy, which was in turn substituted. The history is wrong
1985 in this case. Do it the hard way. */
1986 add = substitute_reg_in_expr (tmp_expr, insn, true);
1988 av_set_add (&new_set, tmp_expr);
1989 clear_expr (tmp_expr);
1999 av_set_union_and_clear (av_ptr, &new_set, NULL);
2003 /* Moveup_* helpers for code motion and computing av sets. */
2005 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2006 The difference from the below function is that only substitution is
2008 static enum MOVEUP_EXPR_CODE
2009 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
2011 vinsn_t vi = EXPR_VINSN (expr);
2015 /* Do this only inside insn group. */
2016 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
2018 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2020 return MOVEUP_EXPR_SAME;
2022 /* Substitution is the possible choice in this case. */
2023 if (has_dep_p[DEPS_IN_RHS])
2025 /* Can't substitute UNIQUE VINSNs. */
2026 gcc_assert (!VINSN_UNIQUE_P (vi));
2028 if (can_substitute_through_p (through_insn,
2029 has_dep_p[DEPS_IN_RHS])
2030 && substitute_reg_in_expr (expr, through_insn, false))
2032 EXPR_WAS_SUBSTITUTED (expr) = true;
2033 return MOVEUP_EXPR_CHANGED;
2036 /* Don't care about this, as even true dependencies may be allowed
2037 in an insn group. */
2038 return MOVEUP_EXPR_SAME;
2041 /* This can catch output dependencies in COND_EXECs. */
2042 if (has_dep_p[DEPS_IN_INSN])
2043 return MOVEUP_EXPR_NULL;
2045 /* This is either an output or an anti dependence, which usually have
2046 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2048 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2049 return MOVEUP_EXPR_AS_RHS;
2052 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2053 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2054 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2055 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2056 && !sel_insn_is_speculation_check (through_insn))
2058 /* True when a conflict on a target register was found during moveup_expr. */
2059 static bool was_target_conflict = false;
2061 /* Return true when moving a debug INSN across THROUGH_INSN will
2062 create a bookkeeping block. We don't want to create such blocks,
2063 for they would cause codegen differences between compilations with
2064 and without debug info. */
2067 moving_insn_creates_bookkeeping_block_p (insn_t insn,
2068 insn_t through_insn)
2070 basic_block bbi, bbt;
2072 edge_iterator ei1, ei2;
2074 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn))
2076 if (sched_verbose >= 9)
2077 sel_print ("no bookkeeping required: ");
2081 bbi = BLOCK_FOR_INSN (insn);
2083 if (EDGE_COUNT (bbi->preds) == 1)
2085 if (sched_verbose >= 9)
2086 sel_print ("only one pred edge: ");
2090 bbt = BLOCK_FOR_INSN (through_insn);
2092 FOR_EACH_EDGE (e1, ei1, bbt->succs)
2094 FOR_EACH_EDGE (e2, ei2, bbi->preds)
2096 if (find_block_for_bookkeeping (e1, e2, TRUE))
2098 if (sched_verbose >= 9)
2099 sel_print ("found existing block: ");
2105 if (sched_verbose >= 9)
2106 sel_print ("would create bookkeeping block: ");
2111 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2112 performing necessary transformations. Record the type of transformation
2113 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2114 permit all dependencies except true ones, and try to remove those
2115 too via forward substitution. All cases when a non-eliminable
2116 non-zero cost dependency exists inside an insn group will be fixed
2117 in tick_check_p instead. */
2118 static enum MOVEUP_EXPR_CODE
2119 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2120 enum local_trans_type *ptrans_type)
2122 vinsn_t vi = EXPR_VINSN (expr);
2123 insn_t insn = VINSN_INSN_RTX (vi);
2124 bool was_changed = false;
2125 bool as_rhs = false;
2129 /* When inside_insn_group, delegate to the helper. */
2130 if (inside_insn_group)
2131 return moveup_expr_inside_insn_group (expr, through_insn);
2133 /* Deal with unique insns and control dependencies. */
2134 if (VINSN_UNIQUE_P (vi))
2136 /* We can move jumps without side-effects or jumps that are
2137 mutually exclusive with instruction THROUGH_INSN (all in cases
2138 dependencies allow to do so and jump is not speculative). */
2139 if (control_flow_insn_p (insn))
2141 basic_block fallthru_bb;
2143 /* Do not move checks and do not move jumps through other
2145 if (control_flow_insn_p (through_insn)
2146 || sel_insn_is_speculation_check (insn))
2147 return MOVEUP_EXPR_NULL;
2149 /* Don't move jumps through CFG joins. */
2150 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2151 return MOVEUP_EXPR_NULL;
2153 /* The jump should have a clear fallthru block, and
2154 this block should be in the current region. */
2155 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2156 || ! in_current_region_p (fallthru_bb))
2157 return MOVEUP_EXPR_NULL;
2159 /* And it should be mutually exclusive with through_insn, or
2160 be an unconditional jump. */
2161 if (! any_uncondjump_p (insn)
2162 && ! sched_insns_conditions_mutex_p (insn, through_insn)
2163 && ! DEBUG_INSN_P (through_insn))
2164 return MOVEUP_EXPR_NULL;
2167 /* Don't move what we can't move. */
2168 if (EXPR_CANT_MOVE (expr)
2169 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2170 return MOVEUP_EXPR_NULL;
2172 /* Don't move SCHED_GROUP instruction through anything.
2173 If we don't force this, then it will be possible to start
2174 scheduling a sched_group before all its dependencies are
2176 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2177 as late as possible through rank_for_schedule. */
2178 if (SCHED_GROUP_P (insn))
2179 return MOVEUP_EXPR_NULL;
2182 gcc_assert (!control_flow_insn_p (insn));
2184 /* Don't move debug insns if this would require bookkeeping. */
2185 if (DEBUG_INSN_P (insn)
2186 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)
2187 && moving_insn_creates_bookkeeping_block_p (insn, through_insn))
2188 return MOVEUP_EXPR_NULL;
2190 /* Deal with data dependencies. */
2191 was_target_conflict = false;
2192 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2195 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2196 return MOVEUP_EXPR_SAME;
2200 /* We can move UNIQUE insn up only as a whole and unchanged,
2201 so it shouldn't have any dependencies. */
2202 if (VINSN_UNIQUE_P (vi))
2203 return MOVEUP_EXPR_NULL;
2206 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2210 res = speculate_expr (expr, full_ds);
2213 /* Speculation was successful. */
2215 was_changed = (res > 0);
2217 was_target_conflict = true;
2219 *ptrans_type = TRANS_SPECULATION;
2220 sel_clear_has_dependence ();
2224 if (has_dep_p[DEPS_IN_INSN])
2225 /* We have some dependency that cannot be discarded. */
2226 return MOVEUP_EXPR_NULL;
2228 if (has_dep_p[DEPS_IN_LHS])
2230 /* Only separable insns can be moved up with the new register.
2231 Anyways, we should mark that the original register is
2233 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2234 return MOVEUP_EXPR_NULL;
2236 EXPR_TARGET_AVAILABLE (expr) = false;
2237 was_target_conflict = true;
2241 /* At this point we have either separable insns, that will be lifted
2242 up only as RHSes, or non-separable insns with no dependency in lhs.
2243 If dependency is in RHS, then try to perform substitution and move up
2250 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2251 moved above y=x assignment as z=x*2.
2253 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2254 side can be moved because of the output dependency. The operation was
2255 cropped to its rhs above. */
2256 if (has_dep_p[DEPS_IN_RHS])
2258 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2260 /* Can't substitute UNIQUE VINSNs. */
2261 gcc_assert (!VINSN_UNIQUE_P (vi));
2263 if (can_speculate_dep_p (*rhs_dsp))
2267 res = speculate_expr (expr, *rhs_dsp);
2270 /* Speculation was successful. */
2272 was_changed = (res > 0);
2274 was_target_conflict = true;
2276 *ptrans_type = TRANS_SPECULATION;
2279 return MOVEUP_EXPR_NULL;
2281 else if (can_substitute_through_p (through_insn,
2283 && substitute_reg_in_expr (expr, through_insn, false))
2285 /* ??? We cannot perform substitution AND speculation on the same
2287 gcc_assert (!was_changed);
2290 *ptrans_type = TRANS_SUBSTITUTION;
2291 EXPR_WAS_SUBSTITUTED (expr) = true;
2294 return MOVEUP_EXPR_NULL;
2297 /* Don't move trapping insns through jumps.
2298 This check should be at the end to give a chance to control speculation
2299 to perform its duties. */
2300 if (CANT_MOVE_TRAPPING (expr, through_insn))
2301 return MOVEUP_EXPR_NULL;
2304 ? MOVEUP_EXPR_CHANGED
2306 ? MOVEUP_EXPR_AS_RHS
2307 : MOVEUP_EXPR_SAME));
2310 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2311 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2312 that can exist within a parallel group. Write to RES the resulting
2313 code for moveup_expr. */
2315 try_bitmap_cache (expr_t expr, insn_t insn,
2316 bool inside_insn_group,
2317 enum MOVEUP_EXPR_CODE *res)
2319 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2321 /* First check whether we've analyzed this situation already. */
2322 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2324 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2326 if (sched_verbose >= 6)
2327 sel_print ("removed (cached)\n");
2328 *res = MOVEUP_EXPR_NULL;
2333 if (sched_verbose >= 6)
2334 sel_print ("unchanged (cached)\n");
2335 *res = MOVEUP_EXPR_SAME;
2339 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2341 if (inside_insn_group)
2343 if (sched_verbose >= 6)
2344 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2345 *res = MOVEUP_EXPR_SAME;
2350 EXPR_TARGET_AVAILABLE (expr) = false;
2352 /* This is the only case when propagation result can change over time,
2353 as we can dynamically switch off scheduling as RHS. In this case,
2354 just check the flag to reach the correct decision. */
2355 if (enable_schedule_as_rhs_p)
2357 if (sched_verbose >= 6)
2358 sel_print ("unchanged (as RHS, cached)\n");
2359 *res = MOVEUP_EXPR_AS_RHS;
2364 if (sched_verbose >= 6)
2365 sel_print ("removed (cached as RHS, but renaming"
2366 " is now disabled)\n");
2367 *res = MOVEUP_EXPR_NULL;
2375 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2376 if successful. Write to RES the resulting code for moveup_expr. */
2378 try_transformation_cache (expr_t expr, insn_t insn,
2379 enum MOVEUP_EXPR_CODE *res)
2381 struct transformed_insns *pti
2382 = (struct transformed_insns *)
2383 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2385 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2388 /* This EXPR was already moved through this insn and was
2389 changed as a result. Fetch the proper data from
2391 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2392 INSN_UID (insn), pti->type,
2393 pti->vinsn_old, pti->vinsn_new,
2394 EXPR_SPEC_DONE_DS (expr));
2396 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2397 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2398 change_vinsn_in_expr (expr, pti->vinsn_new);
2399 if (pti->was_target_conflict)
2400 EXPR_TARGET_AVAILABLE (expr) = false;
2401 if (pti->type == TRANS_SPECULATION)
2405 ds = EXPR_SPEC_DONE_DS (expr);
2407 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2408 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2411 if (sched_verbose >= 6)
2413 sel_print ("changed (cached): ");
2418 *res = MOVEUP_EXPR_CHANGED;
2425 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2427 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2428 enum MOVEUP_EXPR_CODE res)
2430 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2432 /* Do not cache result of propagating jumps through an insn group,
2433 as it is always true, which is not useful outside the group. */
2434 if (inside_insn_group)
2437 if (res == MOVEUP_EXPR_NULL)
2439 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2440 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2442 else if (res == MOVEUP_EXPR_SAME)
2444 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2445 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2447 else if (res == MOVEUP_EXPR_AS_RHS)
2449 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2450 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2456 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2457 and transformation type TRANS_TYPE. */
2459 update_transformation_cache (expr_t expr, insn_t insn,
2460 bool inside_insn_group,
2461 enum local_trans_type trans_type,
2462 vinsn_t expr_old_vinsn)
2464 struct transformed_insns *pti;
2466 if (inside_insn_group)
2469 pti = XNEW (struct transformed_insns);
2470 pti->vinsn_old = expr_old_vinsn;
2471 pti->vinsn_new = EXPR_VINSN (expr);
2472 pti->type = trans_type;
2473 pti->was_target_conflict = was_target_conflict;
2474 pti->ds = EXPR_SPEC_DONE_DS (expr);
2475 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2476 vinsn_attach (pti->vinsn_old);
2477 vinsn_attach (pti->vinsn_new);
2478 *((struct transformed_insns **)
2479 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2480 pti, VINSN_HASH_RTX (expr_old_vinsn),
2484 /* Same as moveup_expr, but first looks up the result of
2485 transformation in caches. */
2486 static enum MOVEUP_EXPR_CODE
2487 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2489 enum MOVEUP_EXPR_CODE res;
2490 bool got_answer = false;
2492 if (sched_verbose >= 6)
2494 sel_print ("Moving ");
2496 sel_print (" through %d: ", INSN_UID (insn));
2499 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr))
2500 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr)))
2501 == EXPR_INSN_RTX (expr)))
2502 /* Don't use cached information for debug insns that are heads of
2504 else if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2505 /* When inside insn group, we do not want remove stores conflicting
2506 with previosly issued loads. */
2507 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2508 else if (try_transformation_cache (expr, insn, &res))
2513 /* Invoke moveup_expr and record the results. */
2514 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2515 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2516 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2517 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2518 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2520 /* ??? Invent something better than this. We can't allow old_vinsn
2521 to go, we need it for the history vector. */
2522 vinsn_attach (expr_old_vinsn);
2524 res = moveup_expr (expr, insn, inside_insn_group,
2528 case MOVEUP_EXPR_NULL:
2529 update_bitmap_cache (expr, insn, inside_insn_group, res);
2530 if (sched_verbose >= 6)
2531 sel_print ("removed\n");
2534 case MOVEUP_EXPR_SAME:
2535 update_bitmap_cache (expr, insn, inside_insn_group, res);
2536 if (sched_verbose >= 6)
2537 sel_print ("unchanged\n");
2540 case MOVEUP_EXPR_AS_RHS:
2541 gcc_assert (!unique_p || inside_insn_group);
2542 update_bitmap_cache (expr, insn, inside_insn_group, res);
2543 if (sched_verbose >= 6)
2544 sel_print ("unchanged (as RHS)\n");
2547 case MOVEUP_EXPR_CHANGED:
2548 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2549 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2550 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2551 INSN_UID (insn), trans_type,
2552 expr_old_vinsn, EXPR_VINSN (expr),
2554 update_transformation_cache (expr, insn, inside_insn_group,
2555 trans_type, expr_old_vinsn);
2556 if (sched_verbose >= 6)
2558 sel_print ("changed: ");
2567 vinsn_detach (expr_old_vinsn);
2573 /* Moves an av set AVP up through INSN, performing necessary
2576 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2581 FOR_EACH_EXPR_1 (expr, i, avp)
2584 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2586 case MOVEUP_EXPR_SAME:
2587 case MOVEUP_EXPR_AS_RHS:
2590 case MOVEUP_EXPR_NULL:
2591 av_set_iter_remove (&i);
2594 case MOVEUP_EXPR_CHANGED:
2595 expr = merge_with_other_exprs (avp, &i, expr);
2604 /* Moves AVP set along PATH. */
2606 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2610 if (sched_verbose >= 6)
2611 sel_print ("Moving expressions up in the insn group...\n");
2614 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2616 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2618 moveup_set_expr (avp, ILIST_INSN (path), true);
2619 path = ILIST_NEXT (path);
2623 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2625 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2627 expr_def _tmp, *tmp = &_tmp;
2631 copy_expr_onside (tmp, expr);
2632 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2635 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2637 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2638 != MOVEUP_EXPR_NULL);
2639 path = ILIST_NEXT (path);
2644 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2645 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2647 if (tmp_vinsn != expr_vliw_vinsn)
2648 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2656 /* Functions that compute av and lv sets. */
2658 /* Returns true if INSN is not a downward continuation of the given path P in
2659 the current stage. */
2661 is_ineligible_successor (insn_t insn, ilist_t p)
2665 /* Check if insn is not deleted. */
2666 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2668 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2671 /* If it's the first insn visited, then the successor is ok. */
2675 prev_insn = ILIST_INSN (p);
2677 if (/* a backward edge. */
2678 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2679 /* is already visited. */
2680 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2681 && (ilist_is_in_p (p, insn)
2682 /* We can reach another fence here and still seqno of insn
2683 would be equal to seqno of prev_insn. This is possible
2684 when prev_insn is a previously created bookkeeping copy.
2685 In that case it'd get a seqno of insn. Thus, check here
2686 whether insn is in current fence too. */
2687 || IN_CURRENT_FENCE_P (insn)))
2688 /* Was already scheduled on this round. */
2689 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2690 && IN_CURRENT_FENCE_P (insn))
2691 /* An insn from another fence could also be
2692 scheduled earlier even if this insn is not in
2693 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2695 && INSN_SCHED_TIMES (insn) > 0))
2701 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2702 of handling multiple successors and properly merging its av_sets. P is
2703 the current path traversed. WS is the size of lookahead window.
2704 Return the av set computed. */
2706 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2708 struct succs_info *sinfo;
2709 av_set_t expr_in_all_succ_branches = NULL;
2711 insn_t succ, zero_succ = NULL;
2712 av_set_t av1 = NULL;
2714 gcc_assert (sel_bb_end_p (insn));
2716 /* Find different kind of successors needed for correct computing of
2717 SPEC and TARGET_AVAILABLE attributes. */
2718 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2721 if (sched_verbose >= 6)
2723 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2724 dump_insn_vector (sinfo->succs_ok);
2726 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2727 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2730 /* Add insn to to the tail of current path. */
2731 ilist_add (&p, insn);
2733 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2737 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2738 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2740 av_set_split_usefulness (succ_set,
2741 VEC_index (int, sinfo->probs_ok, is),
2744 if (sinfo->all_succs_n > 1
2745 && sinfo->all_succs_n == sinfo->succs_ok_n)
2747 /* Find EXPR'es that came from *all* successors and save them
2748 into expr_in_all_succ_branches. This set will be used later
2749 for calculating speculation attributes of EXPR'es. */
2752 expr_in_all_succ_branches = av_set_copy (succ_set);
2754 /* Remember the first successor for later. */
2762 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2763 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2764 av_set_iter_remove (&i);
2768 /* Union the av_sets. Check liveness restrictions on target registers
2769 in special case of two successors. */
2770 if (sinfo->succs_ok_n == 2 && is == 1)
2772 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2773 basic_block bb1 = BLOCK_FOR_INSN (succ);
2775 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2776 av_set_union_and_live (&av1, &succ_set,
2782 av_set_union_and_clear (&av1, &succ_set, insn);
2785 /* Check liveness restrictions via hard way when there are more than
2787 if (sinfo->succs_ok_n > 2)
2788 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2790 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2792 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2793 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2794 BB_LV_SET (succ_bb));
2797 /* Finally, check liveness restrictions on paths leaving the region. */
2798 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2799 for (is = 0; VEC_iterate (rtx, sinfo->succs_other, is, succ); is++)
2800 mark_unavailable_targets
2801 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2803 if (sinfo->all_succs_n > 1)
2808 /* Increase the spec attribute of all EXPR'es that didn't come
2809 from all successors. */
2810 FOR_EACH_EXPR (expr, i, av1)
2811 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2814 av_set_clear (&expr_in_all_succ_branches);
2816 /* Do not move conditional branches through other
2817 conditional branches. So, remove all conditional
2818 branches from av_set if current operator is a conditional
2820 av_set_substract_cond_branches (&av1);
2824 free_succs_info (sinfo);
2826 if (sched_verbose >= 6)
2828 sel_print ("av_succs (%d): ", INSN_UID (insn));
2836 /* This function computes av_set for the FIRST_INSN by dragging valid
2837 av_set through all basic block insns either from the end of basic block
2838 (computed using compute_av_set_at_bb_end) or from the insn on which
2839 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2840 below the basic block and handling conditional branches.
2841 FIRST_INSN - the basic block head, P - path consisting of the insns
2842 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2843 and bb ends are added to the path), WS - current window size,
2844 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2846 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2851 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2852 insn_t after_bb_end = NEXT_INSN (bb_end);
2855 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2857 /* Return NULL if insn is not on the legitimate downward path. */
2858 if (is_ineligible_successor (first_insn, p))
2860 if (sched_verbose >= 6)
2861 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2866 /* If insn already has valid av(insn) computed, just return it. */
2867 if (AV_SET_VALID_P (first_insn))
2871 if (sel_bb_head_p (first_insn))
2872 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2876 if (sched_verbose >= 6)
2878 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2879 dump_av_set (av_set);
2883 return need_copy_p ? av_set_copy (av_set) : av_set;
2886 ilist_add (&p, first_insn);
2888 /* As the result after this loop have completed, in LAST_INSN we'll
2889 have the insn which has valid av_set to start backward computation
2890 from: it either will be NULL because on it the window size was exceeded
2891 or other valid av_set as returned by compute_av_set for the last insn
2892 of the basic block. */
2893 for (last_insn = first_insn; last_insn != after_bb_end;
2894 last_insn = NEXT_INSN (last_insn))
2896 /* We may encounter valid av_set not only on bb_head, but also on
2897 those insns on which previously MAX_WS was exceeded. */
2898 if (AV_SET_VALID_P (last_insn))
2900 if (sched_verbose >= 6)
2901 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2905 /* The special case: the last insn of the BB may be an
2906 ineligible_successor due to its SEQ_NO that was set on
2907 it as a bookkeeping. */
2908 if (last_insn != first_insn
2909 && is_ineligible_successor (last_insn, p))
2911 if (sched_verbose >= 6)
2912 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
2916 if (DEBUG_INSN_P (last_insn))
2919 if (end_ws > max_ws)
2921 /* We can reach max lookahead size at bb_header, so clean av_set
2923 INSN_WS_LEVEL (last_insn) = global_level;
2925 if (sched_verbose >= 6)
2926 sel_print ("Insn %d is beyond the software lookahead window size\n",
2927 INSN_UID (last_insn));
2934 /* Get the valid av_set into AV above the LAST_INSN to start backward
2935 computation from. It either will be empty av_set or av_set computed from
2936 the successors on the last insn of the current bb. */
2937 if (last_insn != after_bb_end)
2941 /* This is needed only to obtain av_sets that are identical to
2942 those computed by the old compute_av_set version. */
2943 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
2944 av_set_add (&av, INSN_EXPR (last_insn));
2947 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2948 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
2950 /* Compute av_set in AV starting from below the LAST_INSN up to
2951 location above the FIRST_INSN. */
2952 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
2953 cur_insn = PREV_INSN (cur_insn))
2954 if (!INSN_NOP_P (cur_insn))
2958 moveup_set_expr (&av, cur_insn, false);
2960 /* If the expression for CUR_INSN is already in the set,
2961 replace it by the new one. */
2962 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
2966 copy_expr (expr, INSN_EXPR (cur_insn));
2969 av_set_add (&av, INSN_EXPR (cur_insn));
2972 /* Clear stale bb_av_set. */
2973 if (sel_bb_head_p (first_insn))
2975 av_set_clear (&BB_AV_SET (cur_bb));
2976 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
2977 BB_AV_LEVEL (cur_bb) = global_level;
2980 if (sched_verbose >= 6)
2982 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
2991 /* Compute av set before INSN.
2992 INSN - the current operation (actual rtx INSN)
2993 P - the current path, which is list of insns visited so far
2994 WS - software lookahead window size.
2995 UNIQUE_P - TRUE, if returned av_set will be changed, hence
2996 if we want to save computed av_set in s_i_d, we should make a copy of it.
2998 In the resulting set we will have only expressions that don't have delay
2999 stalls and nonsubstitutable dependences. */
3001 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
3003 return compute_av_set_inside_bb (insn, p, ws, unique_p);
3006 /* Propagate a liveness set LV through INSN. */
3008 propagate_lv_set (regset lv, insn_t insn)
3010 gcc_assert (INSN_P (insn));
3012 if (INSN_NOP_P (insn))
3015 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
3018 /* Return livness set at the end of BB. */
3020 compute_live_after_bb (basic_block bb)
3024 regset lv = get_clear_regset_from_pool ();
3026 gcc_assert (!ignore_first);
3028 FOR_EACH_EDGE (e, ei, bb->succs)
3029 if (sel_bb_empty_p (e->dest))
3031 if (! BB_LV_SET_VALID_P (e->dest))
3034 gcc_assert (BB_LV_SET (e->dest) == NULL);
3035 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
3036 BB_LV_SET_VALID_P (e->dest) = true;
3038 IOR_REG_SET (lv, BB_LV_SET (e->dest));
3041 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
3046 /* Compute the set of all live registers at the point before INSN and save
3047 it at INSN if INSN is bb header. */
3049 compute_live (insn_t insn)
3051 basic_block bb = BLOCK_FOR_INSN (insn);
3055 /* Return the valid set if we're already on it. */
3060 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3061 src = BB_LV_SET (bb);
3064 gcc_assert (in_current_region_p (bb));
3065 if (INSN_LIVE_VALID_P (insn))
3066 src = INSN_LIVE (insn);
3071 lv = get_regset_from_pool ();
3072 COPY_REG_SET (lv, src);
3074 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3076 COPY_REG_SET (BB_LV_SET (bb), lv);
3077 BB_LV_SET_VALID_P (bb) = true;
3080 return_regset_to_pool (lv);
3085 /* We've skipped the wrong lv_set. Don't skip the right one. */
3086 ignore_first = false;
3087 gcc_assert (in_current_region_p (bb));
3089 /* Find a valid LV set in this block or below, if needed.
3090 Start searching from the next insn: either ignore_first is true, or
3091 INSN doesn't have a correct live set. */
3092 temp = NEXT_INSN (insn);
3093 final = NEXT_INSN (BB_END (bb));
3094 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3095 temp = NEXT_INSN (temp);
3098 lv = compute_live_after_bb (bb);
3099 temp = PREV_INSN (temp);
3103 lv = get_regset_from_pool ();
3104 COPY_REG_SET (lv, INSN_LIVE (temp));
3107 /* Put correct lv sets on the insns which have bad sets. */
3108 final = PREV_INSN (insn);
3109 while (temp != final)
3111 propagate_lv_set (lv, temp);
3112 COPY_REG_SET (INSN_LIVE (temp), lv);
3113 INSN_LIVE_VALID_P (temp) = true;
3114 temp = PREV_INSN (temp);
3117 /* Also put it in a BB. */
3118 if (sel_bb_head_p (insn))
3120 basic_block bb = BLOCK_FOR_INSN (insn);
3122 COPY_REG_SET (BB_LV_SET (bb), lv);
3123 BB_LV_SET_VALID_P (bb) = true;
3126 /* We return LV to the pool, but will not clear it there. Thus we can
3127 legimatelly use LV till the next use of regset_pool_get (). */
3128 return_regset_to_pool (lv);
3132 /* Update liveness sets for INSN. */
3134 update_liveness_on_insn (rtx insn)
3136 ignore_first = true;
3137 compute_live (insn);
3140 /* Compute liveness below INSN and write it into REGS. */
3142 compute_live_below_insn (rtx insn, regset regs)
3147 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3148 IOR_REG_SET (regs, compute_live (succ));
3151 /* Update the data gathered in av and lv sets starting from INSN. */
3153 update_data_sets (rtx insn)
3155 update_liveness_on_insn (insn);
3156 if (sel_bb_head_p (insn))
3158 gcc_assert (AV_LEVEL (insn) != 0);
3159 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3160 compute_av_set (insn, NULL, 0, 0);
3165 /* Helper for move_op () and find_used_regs ().
3166 Return speculation type for which a check should be created on the place
3167 of INSN. EXPR is one of the original ops we are searching for. */
3169 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3172 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3174 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3176 if (targetm.sched.get_insn_checked_ds)
3177 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3179 if (spec_info != NULL
3180 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3181 already_checked_ds |= BEGIN_CONTROL;
3183 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3185 to_check_ds &= ~already_checked_ds;
3190 /* Find the set of registers that are unavailable for storing expres
3191 while moving ORIG_OPS up on the path starting from INSN due to
3192 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3194 All the original operations found during the traversal are saved in the
3195 ORIGINAL_INSNS list.
3197 REG_RENAME_P denotes the set of hardware registers that
3198 can not be used with renaming due to the register class restrictions,
3199 mode restrictions and other (the register we'll choose should be
3200 compatible class with the original uses, shouldn't be in call_used_regs,
3201 should be HARD_REGNO_RENAME_OK etc).
3203 Returns TRUE if we've found all original insns, FALSE otherwise.
3205 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3206 to traverse the code motion paths. This helper function finds registers
3207 that are not available for storing expres while moving ORIG_OPS up on the
3208 path starting from INSN. A register considered as used on the moving path,
3209 if one of the following conditions is not satisfied:
3211 (1) a register not set or read on any path from xi to an instance of
3212 the original operation,
3213 (2) not among the live registers of the point immediately following the
3214 first original operation on a given downward path, except for the
3215 original target register of the operation,
3216 (3) not live on the other path of any conditional branch that is passed
3217 by the operation, in case original operations are not present on
3218 both paths of the conditional branch.
3220 All the original operations found during the traversal are saved in the
3221 ORIGINAL_INSNS list.
3223 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3224 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3225 to unavailable hard regs at the point original operation is found. */
3228 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3229 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3231 def_list_iterator i;
3234 bool needs_spec_check_p = false;
3236 av_set_iterator expr_iter;
3237 struct fur_static_params sparams;
3238 struct cmpd_local_params lparams;
3240 /* We haven't visited any blocks yet. */
3241 bitmap_clear (code_motion_visited_blocks);
3243 /* Init parameters for code_motion_path_driver. */
3244 sparams.crosses_call = false;
3245 sparams.original_insns = original_insns;
3246 sparams.used_regs = used_regs;
3248 /* Set the appropriate hooks and data. */
3249 code_motion_path_driver_info = &fur_hooks;
3251 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3253 reg_rename_p->crosses_call |= sparams.crosses_call;
3255 gcc_assert (res == 1);
3256 gcc_assert (original_insns && *original_insns);
3258 /* ??? We calculate whether an expression needs a check when computing
3259 av sets. This information is not as precise as it could be due to
3260 merging this bit in merge_expr. We can do better in find_used_regs,
3261 but we want to avoid multiple traversals of the same code motion
3263 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3264 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3266 /* Mark hardware regs in REG_RENAME_P that are not suitable
3267 for renaming expr in INSN due to hardware restrictions (register class,
3268 modes compatibility etc). */
3269 FOR_EACH_DEF (def, i, *original_insns)
3271 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3273 if (VINSN_SEPARABLE_P (vinsn))
3274 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3276 /* Do not allow clobbering of ld.[sa] address in case some of the
3277 original operations need a check. */
3278 if (needs_spec_check_p)
3279 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3286 /* Functions to choose the best insn from available ones. */
3288 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3290 sel_target_adjust_priority (expr_t expr)
3292 int priority = EXPR_PRIORITY (expr);
3295 if (targetm.sched.adjust_priority)
3296 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3298 new_priority = priority;
3300 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3301 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3303 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3305 if (sched_verbose >= 4)
3306 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3307 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3308 EXPR_PRIORITY_ADJ (expr), new_priority);
3310 return new_priority;
3313 /* Rank two available exprs for schedule. Never return 0 here. */
3315 sel_rank_for_schedule (const void *x, const void *y)
3317 expr_t tmp = *(const expr_t *) y;
3318 expr_t tmp2 = *(const expr_t *) x;
3319 insn_t tmp_insn, tmp2_insn;
3320 vinsn_t tmp_vinsn, tmp2_vinsn;
3323 tmp_vinsn = EXPR_VINSN (tmp);
3324 tmp2_vinsn = EXPR_VINSN (tmp2);
3325 tmp_insn = EXPR_INSN_RTX (tmp);
3326 tmp2_insn = EXPR_INSN_RTX (tmp2);
3328 /* Schedule debug insns as early as possible. */
3329 if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn))
3331 else if (DEBUG_INSN_P (tmp2_insn))
3334 /* Prefer SCHED_GROUP_P insns to any others. */
3335 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3337 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3338 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3340 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3341 cannot be cloned. */
3342 if (VINSN_UNIQUE_P (tmp2_vinsn))
3347 /* Discourage scheduling of speculative checks. */
3348 val = (sel_insn_is_speculation_check (tmp_insn)
3349 - sel_insn_is_speculation_check (tmp2_insn));
3353 /* Prefer not scheduled insn over scheduled one. */
3354 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3356 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3361 /* Prefer jump over non-jump instruction. */
3362 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3364 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3367 /* Prefer an expr with greater priority. */
3368 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3370 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3371 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3373 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3376 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3377 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3381 if (spec_info != NULL && spec_info->mask != 0)
3382 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3388 ds1 = EXPR_SPEC_DONE_DS (tmp);
3390 dw1 = ds_weak (ds1);
3394 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3396 dw2 = ds_weak (ds2);
3401 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3405 /* Prefer an old insn to a bookkeeping insn. */
3406 if (INSN_UID (tmp_insn) < first_emitted_uid
3407 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3409 if (INSN_UID (tmp_insn) >= first_emitted_uid
3410 && INSN_UID (tmp2_insn) < first_emitted_uid)
3413 /* Prefer an insn with smaller UID, as a last resort.
3414 We can't safely use INSN_LUID as it is defined only for those insns
3415 that are in the stream. */
3416 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3419 /* Filter out expressions from av set pointed to by AV_PTR
3420 that are pipelined too many times. */
3422 process_pipelined_exprs (av_set_t *av_ptr)
3427 /* Don't pipeline already pipelined code as that would increase
3428 number of unnecessary register moves. */
3429 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3431 if (EXPR_SCHED_TIMES (expr)
3432 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3433 av_set_iter_remove (&si);
3437 /* Filter speculative insns from AV_PTR if we don't want them. */
3439 process_spec_exprs (av_set_t *av_ptr)
3441 bool try_data_p = true;
3442 bool try_control_p = true;
3446 if (spec_info == NULL)
3449 /* Scan *AV_PTR to find out if we want to consider speculative
3450 instructions for scheduling. */
3451 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3455 ds = EXPR_SPEC_DONE_DS (expr);
3457 /* The probability of a success is too low - don't speculate. */
3458 if ((ds & SPECULATIVE)
3459 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3460 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3461 || (pipelining_p && false
3463 && (ds & CONTROL_SPEC))))
3465 av_set_iter_remove (&si);
3469 if ((spec_info->flags & PREFER_NON_DATA_SPEC)
3470 && !(ds & BEGIN_DATA))
3473 if ((spec_info->flags & PREFER_NON_CONTROL_SPEC)
3474 && !(ds & BEGIN_CONTROL))
3475 try_control_p = false;
3478 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3482 ds = EXPR_SPEC_DONE_DS (expr);
3484 if (ds & SPECULATIVE)
3486 if ((ds & BEGIN_DATA) && !try_data_p)
3487 /* We don't want any data speculative instructions right
3489 av_set_iter_remove (&si);
3491 if ((ds & BEGIN_CONTROL) && !try_control_p)
3492 /* We don't want any control speculative instructions right
3494 av_set_iter_remove (&si);
3499 /* Search for any use-like insns in AV_PTR and decide on scheduling
3500 them. Return one when found, and NULL otherwise.
3501 Note that we check here whether a USE could be scheduled to avoid
3502 an infinite loop later. */
3504 process_use_exprs (av_set_t *av_ptr)
3508 bool uses_present_p = false;
3509 bool try_uses_p = true;
3511 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3513 /* This will also initialize INSN_CODE for later use. */
3514 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3516 /* If we have a USE in *AV_PTR that was not scheduled yet,
3517 do so because it will do good only. */
3518 if (EXPR_SCHED_TIMES (expr) <= 0)
3520 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3523 av_set_iter_remove (&si);
3527 gcc_assert (pipelining_p);
3529 uses_present_p = true;
3538 /* If we don't want to schedule any USEs right now and we have some
3539 in *AV_PTR, remove them, else just return the first one found. */
3542 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3543 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3544 av_set_iter_remove (&si);
3548 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3550 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3552 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3555 av_set_iter_remove (&si);
3563 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3565 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3570 for (n = 0; VEC_iterate (vinsn_t, vinsn_vec, n, vinsn); n++)
3571 if (VINSN_SEPARABLE_P (vinsn))
3573 if (vinsn_equal_p (vinsn, EXPR_VINSN (expr)))
3578 /* For non-separable instructions, the blocking insn can have
3579 another pattern due to substitution, and we can't choose
3580 different register as in the above case. Check all registers
3581 being written instead. */
3582 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3583 VINSN_REG_SETS (EXPR_VINSN (expr))))
3590 #ifdef ENABLE_CHECKING
3591 /* Return true if either of expressions from ORIG_OPS can be blocked
3592 by previously created bookkeeping code. STATIC_PARAMS points to static
3593 parameters of move_op. */
3595 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3598 av_set_iterator iter;
3599 moveop_static_params_p sparams;
3601 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3602 created while scheduling on another fence. */
3603 FOR_EACH_EXPR (expr, iter, orig_ops)
3604 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3607 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3608 sparams = (moveop_static_params_p) static_params;
3610 /* Expressions can be also blocked by bookkeeping created during current
3612 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3613 FOR_EACH_EXPR (expr, iter, orig_ops)
3614 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3617 /* Expressions in ORIG_OPS may have wrong destination register due to
3618 renaming. Check with the right register instead. */
3619 if (sparams->dest && REG_P (sparams->dest))
3621 unsigned regno = REGNO (sparams->dest);
3622 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3624 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn), regno)
3625 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn), regno)
3626 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn), regno))
3634 /* Clear VINSN_VEC and detach vinsns. */
3636 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3638 unsigned len = VEC_length (vinsn_t, *vinsn_vec);
3644 for (n = 0; VEC_iterate (vinsn_t, *vinsn_vec, n, vinsn); n++)
3645 vinsn_detach (vinsn);
3646 VEC_block_remove (vinsn_t, *vinsn_vec, 0, len);
3650 /* Add the vinsn of EXPR to the VINSN_VEC. */
3652 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3654 vinsn_attach (EXPR_VINSN (expr));
3655 VEC_safe_push (vinsn_t, heap, *vinsn_vec, EXPR_VINSN (expr));
3658 /* Free the vector representing blocked expressions. */
3660 vinsn_vec_free (vinsn_vec_t *vinsn_vec)
3663 VEC_free (vinsn_t, heap, *vinsn_vec);
3666 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3668 void sel_add_to_insn_priority (rtx insn, int amount)
3670 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3672 if (sched_verbose >= 2)
3673 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3674 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3675 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3678 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3679 true if there is something to schedule. BNDS and FENCE are current
3680 boundaries and fence, respectively. If we need to stall for some cycles
3681 before an expr from AV would become available, write this number to
3684 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3689 int sched_next_worked = 0, stalled, n;
3690 static int av_max_prio, est_ticks_till_branch;
3691 int min_need_stall = -1;
3692 deps_t dc = BND_DC (BLIST_BND (bnds));
3694 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3695 already scheduled. */
3699 /* Empty vector from the previous stuff. */
3700 if (VEC_length (expr_t, vec_av_set) > 0)
3701 VEC_block_remove (expr_t, vec_av_set, 0, VEC_length (expr_t, vec_av_set));
3703 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3705 gcc_assert (VEC_empty (expr_t, vec_av_set));
3706 FOR_EACH_EXPR (expr, si, av)
3708 VEC_safe_push (expr_t, heap, vec_av_set, expr);
3710 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3712 /* Adjust priority using target backend hook. */
3713 sel_target_adjust_priority (expr);
3716 /* Sort the vector. */
3717 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3718 sizeof (expr_t), sel_rank_for_schedule);
3720 /* We record maximal priority of insns in av set for current instruction
3722 if (FENCE_STARTS_CYCLE_P (fence))
3723 av_max_prio = est_ticks_till_branch = INT_MIN;
3725 /* Filter out inappropriate expressions. Loop's direction is reversed to
3726 visit "best" instructions first. We assume that VEC_unordered_remove
3727 moves last element in place of one being deleted. */
3728 for (n = VEC_length (expr_t, vec_av_set) - 1, stalled = 0; n >= 0; n--)
3730 expr_t expr = VEC_index (expr_t, vec_av_set, n);
3731 insn_t insn = EXPR_INSN_RTX (expr);
3732 char target_available;
3733 bool is_orig_reg_p = true;
3734 int need_cycles, new_prio;
3736 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3737 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3739 VEC_unordered_remove (expr_t, vec_av_set, n);
3743 /* Set number of sched_next insns (just in case there
3744 could be several). */
3745 if (FENCE_SCHED_NEXT (fence))
3746 sched_next_worked++;
3748 /* Check all liveness requirements and try renaming.
3749 FIXME: try to minimize calls to this. */
3750 target_available = EXPR_TARGET_AVAILABLE (expr);
3752 /* If insn was already scheduled on the current fence,
3753 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3754 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr))
3755 target_available = -1;
3757 /* If the availability of the EXPR is invalidated by the insertion of
3758 bookkeeping earlier, make sure that we won't choose this expr for
3759 scheduling if it's not separable, and if it is separable, then
3760 we have to recompute the set of available registers for it. */
3761 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3763 VEC_unordered_remove (expr_t, vec_av_set, n);
3764 if (sched_verbose >= 4)
3765 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3770 if (target_available == true)
3772 /* Do nothing -- we can use an existing register. */
3773 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3775 else if (/* Non-separable instruction will never
3776 get another register. */
3777 (target_available == false
3778 && !EXPR_SEPARABLE_P (expr))
3779 /* Don't try to find a register for low-priority expression. */
3780 || (int) VEC_length (expr_t, vec_av_set) - 1 - n >= max_insns_to_rename
3781 /* ??? FIXME: Don't try to rename data speculation. */
3782 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3783 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3785 VEC_unordered_remove (expr_t, vec_av_set, n);
3786 if (sched_verbose >= 4)
3787 sel_print ("Expr %d has no suitable target register\n",
3792 /* Filter expressions that need to be renamed or speculated when
3793 pipelining, because compensating register copies or speculation
3794 checks are likely to be placed near the beginning of the loop,
3796 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3797 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3799 /* Estimation of number of cycles until loop branch for
3800 renaming/speculation to be successful. */
3801 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3803 if ((int) current_loop_nest->ninsns < 9)
3805 VEC_unordered_remove (expr_t, vec_av_set, n);
3806 if (sched_verbose >= 4)
3807 sel_print ("Pipelining expr %d will likely cause stall\n",
3812 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3813 < need_n_ticks_till_branch * issue_rate / 2
3814 && est_ticks_till_branch < need_n_ticks_till_branch)
3816 VEC_unordered_remove (expr_t, vec_av_set, n);
3817 if (sched_verbose >= 4)
3818 sel_print ("Pipelining expr %d will likely cause stall\n",
3824 /* We want to schedule speculation checks as late as possible. Discard
3825 them from av set if there are instructions with higher priority. */
3826 if (sel_insn_is_speculation_check (insn)
3827 && EXPR_PRIORITY (expr) < av_max_prio)
3830 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3831 VEC_unordered_remove (expr_t, vec_av_set, n);
3832 if (sched_verbose >= 4)
3833 sel_print ("Delaying speculation check %d until its first use\n",
3838 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3839 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3840 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3842 /* Don't allow any insns whose data is not yet ready.
3843 Check first whether we've already tried them and failed. */
3844 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3846 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3847 - FENCE_CYCLE (fence));
3848 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3849 est_ticks_till_branch = MAX (est_ticks_till_branch,
3850 EXPR_PRIORITY (expr) + need_cycles);
3852 if (need_cycles > 0)
3855 min_need_stall = (min_need_stall < 0
3857 : MIN (min_need_stall, need_cycles));
3858 VEC_unordered_remove (expr_t, vec_av_set, n);
3860 if (sched_verbose >= 4)
3861 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3863 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3868 /* Now resort to dependence analysis to find whether EXPR might be
3869 stalled due to dependencies from FENCE's context. */
3870 need_cycles = tick_check_p (expr, dc, fence);
3871 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3873 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3874 est_ticks_till_branch = MAX (est_ticks_till_branch,
3877 if (need_cycles > 0)
3879 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3881 int new_size = INSN_UID (insn) * 3 / 2;
3883 FENCE_READY_TICKS (fence)
3884 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3885 new_size, FENCE_READY_TICKS_SIZE (fence),
3888 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3889 = FENCE_CYCLE (fence) + need_cycles;
3892 min_need_stall = (min_need_stall < 0
3894 : MIN (min_need_stall, need_cycles));
3896 VEC_unordered_remove (expr_t, vec_av_set, n);
3898 if (sched_verbose >= 4)
3899 sel_print ("Expr %d is not ready yet until cycle %d\n",
3901 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3905 if (sched_verbose >= 4)
3906 sel_print ("Expr %d is ok\n", INSN_UID (insn));
3910 /* Clear SCHED_NEXT. */
3911 if (FENCE_SCHED_NEXT (fence))
3913 gcc_assert (sched_next_worked == 1);
3914 FENCE_SCHED_NEXT (fence) = NULL_RTX;
3917 /* No need to stall if this variable was not initialized. */
3918 if (min_need_stall < 0)
3921 if (VEC_empty (expr_t, vec_av_set))
3923 /* We need to set *pneed_stall here, because later we skip this code
3924 when ready list is empty. */
3925 *pneed_stall = min_need_stall;
3929 gcc_assert (min_need_stall == 0);
3931 /* Sort the vector. */
3932 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3933 sizeof (expr_t), sel_rank_for_schedule);
3935 if (sched_verbose >= 4)
3937 sel_print ("Total ready exprs: %d, stalled: %d\n",
3938 VEC_length (expr_t, vec_av_set), stalled);
3939 sel_print ("Sorted av set (%d): ", VEC_length (expr_t, vec_av_set));
3940 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3949 /* Convert a vectored and sorted av set to the ready list that
3950 the rest of the backend wants to see. */
3952 convert_vec_av_set_to_ready (void)
3957 /* Allocate and fill the ready list from the sorted vector. */
3958 ready.n_ready = VEC_length (expr_t, vec_av_set);
3959 ready.first = ready.n_ready - 1;
3961 gcc_assert (ready.n_ready > 0);
3963 if (ready.n_ready > max_issue_size)
3965 max_issue_size = ready.n_ready;
3966 sched_extend_ready_list (ready.n_ready);
3969 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3971 vinsn_t vi = EXPR_VINSN (expr);
3972 insn_t insn = VINSN_INSN_RTX (vi);
3975 ready.vec[n] = insn;
3979 /* Initialize ready list from *AV_PTR for the max_issue () call.
3980 If any unrecognizable insn found in *AV_PTR, return it (and skip
3981 max_issue). BND and FENCE are current boundary and fence,
3982 respectively. If we need to stall for some cycles before an expr
3983 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3985 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
3990 /* We do not support multiple boundaries per fence. */
3991 gcc_assert (BLIST_NEXT (bnds) == NULL);
3993 /* Process expressions required special handling, i.e. pipelined,
3994 speculative and recog() < 0 expressions first. */
3995 process_pipelined_exprs (av_ptr);
3996 process_spec_exprs (av_ptr);
3998 /* A USE could be scheduled immediately. */
3999 expr = process_use_exprs (av_ptr);
4006 /* Turn the av set to a vector for sorting. */
4007 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
4013 /* Build the final ready list. */
4014 convert_vec_av_set_to_ready ();
4018 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4020 sel_dfa_new_cycle (insn_t insn, fence_t fence)
4022 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
4023 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
4024 : FENCE_CYCLE (fence) - 1;
4028 if (!targetm.sched.dfa_new_cycle)
4031 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4033 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
4034 insn, last_scheduled_cycle,
4035 FENCE_CYCLE (fence), &sort_p))
4037 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4038 advance_one_cycle (fence);
4039 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4046 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4047 we can issue. FENCE is the current fence. */
4049 invoke_reorder_hooks (fence_t fence)
4052 bool ran_hook = false;
4054 /* Call the reorder hook at the beginning of the cycle, and call
4055 the reorder2 hook in the middle of the cycle. */
4056 if (FENCE_ISSUED_INSNS (fence) == 0)
4058 if (targetm.sched.reorder
4059 && !SCHED_GROUP_P (ready_element (&ready, 0))
4060 && ready.n_ready > 1)
4062 /* Don't give reorder the most prioritized insn as it can break
4068 = targetm.sched.reorder (sched_dump, sched_verbose,
4069 ready_lastpos (&ready),
4070 &ready.n_ready, FENCE_CYCLE (fence));
4078 /* Initialize can_issue_more for variable_issue. */
4079 issue_more = issue_rate;
4081 else if (targetm.sched.reorder2
4082 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4084 if (ready.n_ready == 1)
4086 targetm.sched.reorder2 (sched_dump, sched_verbose,
4087 ready_lastpos (&ready),
4088 &ready.n_ready, FENCE_CYCLE (fence));
4095 targetm.sched.reorder2 (sched_dump, sched_verbose,
4097 ? ready_lastpos (&ready) : NULL,
4098 &ready.n_ready, FENCE_CYCLE (fence));
4107 issue_more = FENCE_ISSUE_MORE (fence);
4109 /* Ensure that ready list and vec_av_set are in line with each other,
4110 i.e. vec_av_set[i] == ready_element (&ready, i). */
4111 if (issue_more && ran_hook)
4114 rtx *arr = ready.vec;
4115 expr_t *vec = VEC_address (expr_t, vec_av_set);
4117 for (i = 0, n = ready.n_ready; i < n; i++)
4118 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4122 for (j = i; j < n; j++)
4123 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4136 /* Return an EXPR correponding to INDEX element of ready list, if
4137 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4138 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4139 ready.vec otherwise. */
4140 static inline expr_t
4141 find_expr_for_ready (int index, bool follow_ready_element)
4146 real_index = follow_ready_element ? ready.first - index : index;
4148 expr = VEC_index (expr_t, vec_av_set, real_index);
4149 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4154 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4155 of such insns found. */
4157 invoke_dfa_lookahead_guard (void)
4161 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4163 if (sched_verbose >= 2)
4164 sel_print ("ready after reorder: ");
4166 for (i = 0, n = 0; i < ready.n_ready; i++)
4172 /* In this loop insn is Ith element of the ready list given by
4173 ready_element, not Ith element of ready.vec. */
4174 insn = ready_element (&ready, i);
4176 if (! have_hook || i == 0)
4179 r = !targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn);
4181 gcc_assert (INSN_CODE (insn) >= 0);
4183 /* Only insns with ready_try = 0 can get here
4184 from fill_ready_list. */
4185 gcc_assert (ready_try [i] == 0);
4190 expr = find_expr_for_ready (i, true);
4192 if (sched_verbose >= 2)
4194 dump_vinsn (EXPR_VINSN (expr));
4195 sel_print (":%d; ", ready_try[i]);
4199 if (sched_verbose >= 2)
4204 /* Calculate the number of privileged insns and return it. */
4206 calculate_privileged_insns (void)
4208 expr_t cur_expr, min_spec_expr = NULL;
4209 insn_t cur_insn, min_spec_insn;
4210 int privileged_n = 0, i;
4212 for (i = 0; i < ready.n_ready; i++)
4217 if (! min_spec_expr)
4219 min_spec_insn = ready_element (&ready, i);
4220 min_spec_expr = find_expr_for_ready (i, true);
4223 cur_insn = ready_element (&ready, i);
4224 cur_expr = find_expr_for_ready (i, true);
4226 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4232 if (i == ready.n_ready)
4235 if (sched_verbose >= 2)
4236 sel_print ("privileged_n: %d insns with SPEC %d\n",
4237 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4238 return privileged_n;
4241 /* Call the rest of the hooks after the choice was made. Return
4242 the number of insns that still can be issued given that the current
4243 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4244 and the insn chosen for scheduling, respectively. */
4246 invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more)
4248 gcc_assert (INSN_P (best_insn));
4250 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4251 sel_dfa_new_cycle (best_insn, fence);
4253 if (targetm.sched.variable_issue)
4255 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4257 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4259 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4261 else if (GET_CODE (PATTERN (best_insn)) != USE
4262 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4268 /* Estimate the cost of issuing INSN on DFA state STATE. */
4270 estimate_insn_cost (rtx insn, state_t state)
4272 static state_t temp = NULL;
4276 temp = xmalloc (dfa_state_size);
4278 memcpy (temp, state, dfa_state_size);
4279 cost = state_transition (temp, insn);
4288 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4289 This function properly handles ASMs, USEs etc. */
4291 get_expr_cost (expr_t expr, fence_t fence)
4293 rtx insn = EXPR_INSN_RTX (expr);
4295 if (recog_memoized (insn) < 0)
4297 if (!FENCE_STARTS_CYCLE_P (fence)
4298 && INSN_ASM_P (insn))
4299 /* This is asm insn which is tryed to be issued on the
4300 cycle not first. Issue it on the next cycle. */
4303 /* A USE insn, or something else we don't need to
4304 understand. We can't pass these directly to
4305 state_transition because it will trigger a
4306 fatal error for unrecognizable insns. */
4310 return estimate_insn_cost (insn, FENCE_STATE (fence));
4313 /* Find the best insn for scheduling, either via max_issue or just take
4314 the most prioritized available. */
4316 choose_best_insn (fence_t fence, int privileged_n, int *index)
4320 if (dfa_lookahead > 0)
4322 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4323 can_issue = max_issue (&ready, privileged_n,
4324 FENCE_STATE (fence), index);
4325 if (sched_verbose >= 2)
4326 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4327 can_issue, FENCE_ISSUED_INSNS (fence));
4331 /* We can't use max_issue; just return the first available element. */
4334 for (i = 0; i < ready.n_ready; i++)
4336 expr_t expr = find_expr_for_ready (i, true);
4338 if (get_expr_cost (expr, fence) < 1)
4340 can_issue = can_issue_more;
4343 if (sched_verbose >= 2)
4344 sel_print ("using %dth insn from the ready list\n", i + 1);
4350 if (i == ready.n_ready)
4360 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4361 BNDS and FENCE are current boundaries and scheduling fence respectively.
4362 Return the expr found and NULL if nothing can be issued atm.
4363 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4365 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4370 /* Choose the best insn for scheduling via:
4371 1) sorting the ready list based on priority;
4372 2) calling the reorder hook;
4373 3) calling max_issue. */
4374 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4375 if (best == NULL && ready.n_ready > 0)
4377 int privileged_n, index, avail_n;
4379 can_issue_more = invoke_reorder_hooks (fence);
4380 if (can_issue_more > 0)
4382 /* Try choosing the best insn until we find one that is could be
4383 scheduled due to liveness restrictions on its destination register.
4384 In the future, we'd like to choose once and then just probe insns
4385 in the order of their priority. */
4386 avail_n = invoke_dfa_lookahead_guard ();
4387 privileged_n = calculate_privileged_insns ();
4388 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4390 best = find_expr_for_ready (index, true);
4392 /* We had some available insns, so if we can't issue them,
4394 if (can_issue_more == 0)
4403 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4405 if (can_issue_more == 0)
4409 if (sched_verbose >= 2)
4413 sel_print ("Best expression (vliw form): ");
4415 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4418 sel_print ("No best expr found!\n");
4425 /* Functions that implement the core of the scheduler. */
4428 /* Emit an instruction from EXPR with SEQNO and VINSN after
4431 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4432 insn_t place_to_insert)
4434 /* This assert fails when we have identical instructions
4435 one of which dominates the other. In this case move_op ()
4436 finds the first instruction and doesn't search for second one.
4437 The solution would be to compute av_set after the first found
4438 insn and, if insn present in that set, continue searching.
4439 For now we workaround this issue in move_op. */
4440 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4442 if (EXPR_WAS_RENAMED (expr))
4444 unsigned regno = expr_dest_regno (expr);
4446 if (HARD_REGISTER_NUM_P (regno))
4448 df_set_regs_ever_live (regno, true);
4449 reg_rename_tick[regno] = ++reg_rename_this_tick;
4453 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4457 /* Return TRUE if BB can hold bookkeeping code. */
4459 block_valid_for_bookkeeping_p (basic_block bb)
4461 insn_t bb_end = BB_END (bb);
4463 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4466 if (INSN_P (bb_end))
4468 if (INSN_SCHED_TIMES (bb_end) > 0)
4472 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4477 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4478 into E2->dest, except from E1->src (there may be a sequence of empty basic
4479 blocks between E1->src and E2->dest). Return found block, or NULL if new
4480 one must be created. If LAX holds, don't assume there is a simple path
4481 from E1->src to E2->dest. */
4483 find_block_for_bookkeeping (edge e1, edge e2, bool lax)
4485 basic_block candidate_block = NULL;
4488 /* Loop over edges from E1 to E2, inclusive. */
4489 for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR; e = EDGE_SUCC (e->dest, 0))
4491 if (EDGE_COUNT (e->dest->preds) == 2)
4493 if (candidate_block == NULL)
4494 candidate_block = (EDGE_PRED (e->dest, 0) == e
4495 ? EDGE_PRED (e->dest, 1)->src
4496 : EDGE_PRED (e->dest, 0)->src);
4498 /* Found additional edge leading to path from e1 to e2
4502 else if (EDGE_COUNT (e->dest->preds) > 2)
4503 /* Several edges leading to path from e1 to e2 from aside. */
4507 return ((!lax || candidate_block)
4508 && block_valid_for_bookkeeping_p (candidate_block)
4512 if (lax && EDGE_COUNT (e->dest->succs) != 1)
4522 /* Create new basic block for bookkeeping code for path(s) incoming into
4523 E2->dest, except from E1->src. Return created block. */
4525 create_block_for_bookkeeping (edge e1, edge e2)
4527 basic_block new_bb, bb = e2->dest;
4529 /* Check that we don't spoil the loop structure. */
4530 if (current_loop_nest)
4532 basic_block latch = current_loop_nest->latch;
4534 /* We do not split header. */
4535 gcc_assert (e2->dest != current_loop_nest->header);
4537 /* We do not redirect the only edge to the latch block. */
4538 gcc_assert (e1->dest != latch
4539 || !single_pred_p (latch)
4540 || e1 != single_pred_edge (latch));
4543 /* Split BB to insert BOOK_INSN there. */
4544 new_bb = sched_split_block (bb, NULL);
4546 /* Move note_list from the upper bb. */
4547 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4548 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4549 BB_NOTE_LIST (bb) = NULL_RTX;
4551 gcc_assert (e2->dest == bb);
4553 /* Skip block for bookkeeping copy when leaving E1->src. */
4554 if (e1->flags & EDGE_FALLTHRU)
4555 sel_redirect_edge_and_branch_force (e1, new_bb);
4557 sel_redirect_edge_and_branch (e1, new_bb);
4559 gcc_assert (e1->dest == new_bb);
4560 gcc_assert (sel_bb_empty_p (bb));
4562 /* To keep basic block numbers in sync between debug and non-debug
4563 compilations, we have to rotate blocks here. Consider that we
4564 started from (a,b)->d, (c,d)->e, and d contained only debug
4565 insns. It would have been removed before if the debug insns
4566 weren't there, so we'd have split e rather than d. So what we do
4567 now is to swap the block numbers of new_bb and
4568 single_succ(new_bb) == e, so that the insns that were in e before
4569 get the new block number. */
4571 if (MAY_HAVE_DEBUG_INSNS)
4574 insn_t insn = sel_bb_head (new_bb);
4577 if (DEBUG_INSN_P (insn)
4578 && single_succ_p (new_bb)
4579 && (succ = single_succ (new_bb))
4580 && succ != EXIT_BLOCK_PTR
4581 && DEBUG_INSN_P ((last = sel_bb_end (new_bb))))
4583 while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4584 insn = NEXT_INSN (insn);
4588 sel_global_bb_info_def gbi;
4589 sel_region_bb_info_def rbi;
4592 if (sched_verbose >= 2)
4593 sel_print ("Swapping block ids %i and %i\n",
4594 new_bb->index, succ->index);
4597 new_bb->index = succ->index;
4600 SET_BASIC_BLOCK (new_bb->index, new_bb);
4601 SET_BASIC_BLOCK (succ->index, succ);
4603 memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi));
4604 memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ),
4606 memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi));
4608 memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi));
4609 memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ),
4611 memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi));
4613 i = BLOCK_TO_BB (new_bb->index);
4614 BLOCK_TO_BB (new_bb->index) = BLOCK_TO_BB (succ->index);
4615 BLOCK_TO_BB (succ->index) = i;
4617 i = CONTAINING_RGN (new_bb->index);
4618 CONTAINING_RGN (new_bb->index) = CONTAINING_RGN (succ->index);
4619 CONTAINING_RGN (succ->index) = i;
4621 for (i = 0; i < current_nr_blocks; i++)
4622 if (BB_TO_BLOCK (i) == succ->index)
4623 BB_TO_BLOCK (i) = new_bb->index;
4624 else if (BB_TO_BLOCK (i) == new_bb->index)
4625 BB_TO_BLOCK (i) = succ->index;
4627 FOR_BB_INSNS (new_bb, insn)
4629 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index;
4631 FOR_BB_INSNS (succ, insn)
4633 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index;
4635 if (bitmap_bit_p (code_motion_visited_blocks, new_bb->index))
4637 bitmap_set_bit (code_motion_visited_blocks, succ->index);
4638 bitmap_clear_bit (code_motion_visited_blocks, new_bb->index);
4641 gcc_assert (LABEL_P (BB_HEAD (new_bb))
4642 && LABEL_P (BB_HEAD (succ)));
4644 if (sched_verbose >= 4)
4645 sel_print ("Swapping code labels %i and %i\n",
4646 CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4647 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4649 i = CODE_LABEL_NUMBER (BB_HEAD (new_bb));
4650 CODE_LABEL_NUMBER (BB_HEAD (new_bb))
4651 = CODE_LABEL_NUMBER (BB_HEAD (succ));
4652 CODE_LABEL_NUMBER (BB_HEAD (succ)) = i;
4660 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4661 into E2->dest, except from E1->src. */
4663 find_place_for_bookkeeping (edge e1, edge e2)
4665 insn_t place_to_insert;
4666 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4667 create new basic block, but insert bookkeeping there. */
4668 basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE);
4672 place_to_insert = BB_END (book_block);
4674 /* Don't use a block containing only debug insns for
4675 bookkeeping, this causes scheduling differences between debug
4676 and non-debug compilations, for the block would have been
4678 if (DEBUG_INSN_P (place_to_insert))
4680 rtx insn = sel_bb_head (book_block);
4682 while (insn != place_to_insert &&
4683 (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4684 insn = NEXT_INSN (insn);
4686 if (insn == place_to_insert)
4693 book_block = create_block_for_bookkeeping (e1, e2);
4694 place_to_insert = BB_END (book_block);
4695 if (sched_verbose >= 9)
4696 sel_print ("New block is %i, split from bookkeeping block %i\n",
4697 EDGE_SUCC (book_block, 0)->dest->index, book_block->index);
4701 if (sched_verbose >= 9)
4702 sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index);
4705 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4706 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4707 place_to_insert = PREV_INSN (place_to_insert);
4709 return place_to_insert;
4712 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4715 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4720 /* Check if we are about to insert bookkeeping copy before a jump, and use
4721 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4722 next = NEXT_INSN (place_to_insert);
4725 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4727 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4728 seqno = INSN_SEQNO (next);
4730 else if (INSN_SEQNO (join_point) > 0)
4731 seqno = INSN_SEQNO (join_point);
4734 seqno = get_seqno_by_preds (place_to_insert);
4736 /* Sometimes the fences can move in such a way that there will be
4737 no instructions with positive seqno around this bookkeeping.
4738 This means that there will be no way to get to it by a regular
4739 fence movement. Never mind because we pick up such pieces for
4740 rescheduling anyways, so any positive value will do for now. */
4743 gcc_assert (pipelining_p);
4748 gcc_assert (seqno > 0);
4752 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4753 NEW_SEQNO to it. Return created insn. */
4755 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4757 rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4760 = create_vinsn_from_insn_rtx (new_insn_rtx,
4761 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4763 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4766 INSN_SCHED_TIMES (new_insn) = 0;
4767 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4772 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4773 E2->dest, except from E1->src (there may be a sequence of empty blocks
4774 between E1->src and E2->dest). Return block containing the copy.
4775 All scheduler data is initialized for the newly created insn. */
4777 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4779 insn_t join_point, place_to_insert, new_insn;
4781 bool need_to_exchange_data_sets;
4783 if (sched_verbose >= 4)
4784 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4787 join_point = sel_bb_head (e2->dest);
4788 place_to_insert = find_place_for_bookkeeping (e1, e2);
4789 if (!place_to_insert)
4791 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4792 need_to_exchange_data_sets
4793 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4795 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4797 /* When inserting bookkeeping insn in new block, av sets should be
4798 following: old basic block (that now holds bookkeeping) data sets are
4799 the same as was before generation of bookkeeping, and new basic block
4800 (that now hold all other insns of old basic block) data sets are
4801 invalid. So exchange data sets for these basic blocks as sel_split_block
4802 mistakenly exchanges them in this case. Cannot do it earlier because
4803 when single instruction is added to new basic block it should hold NULL
4805 if (need_to_exchange_data_sets)
4806 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4807 BLOCK_FOR_INSN (join_point));
4809 stat_bookkeeping_copies++;
4810 return BLOCK_FOR_INSN (new_insn);
4813 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4814 on FENCE, but we are unable to copy them. */
4816 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4821 /* An expression does not need bookkeeping if it is available on all paths
4822 from current block to original block and current block dominates
4823 original block. We check availability on all paths by examining
4824 EXPR_SPEC; this is not equivalent, because it may be positive even
4825 if expr is available on all paths (but if expr is not available on
4826 any path, EXPR_SPEC will be positive). */
4828 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4830 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4831 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4832 && (EXPR_SPEC (expr)
4833 || !EXPR_ORIG_BB_INDEX (expr)
4834 || !dominated_by_p (CDI_DOMINATORS,
4835 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr)),
4836 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4838 if (sched_verbose >= 4)
4839 sel_print ("Expr %d removed because it would need bookkeeping, which "
4840 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4841 av_set_iter_remove (&i);
4846 /* Moving conditional jump through some instructions.
4850 ... <- current scheduling point
4851 NOTE BASIC BLOCK: <- bb header
4852 (p8) add r14=r14+0x9;;
4858 We can schedule jump one cycle earlier, than mov, because they cannot be
4859 executed together as their predicates are mutually exclusive.
4861 This is done in this way: first, new fallthrough basic block is created
4862 after jump (it is always can be done, because there already should be a
4863 fallthrough block, where control flow goes in case of predicate being true -
4864 in our example; otherwise there should be a dependence between those
4865 instructions and jump and we cannot schedule jump right now);
4866 next, all instructions between jump and current scheduling point are moved
4867 to this new block. And the result is this:
4870 (!p8) jump L1 <- current scheduling point
4871 NOTE BASIC BLOCK: <- bb header
4872 (p8) add r14=r14+0x9;;
4878 move_cond_jump (rtx insn, bnd_t bnd)
4881 basic_block block_from, block_next, block_new;
4882 rtx next, prev, link;
4884 /* BLOCK_FROM holds basic block of the jump. */
4885 block_from = BLOCK_FOR_INSN (insn);
4887 /* Moving of jump should not cross any other jumps or
4888 beginnings of new basic blocks. */
4889 gcc_assert (block_from == BLOCK_FOR_INSN (BND_TO (bnd)));
4891 /* Jump is moved to the boundary. */
4892 prev = BND_TO (bnd);
4893 next = PREV_INSN (insn);
4894 BND_TO (bnd) = insn;
4896 ft_edge = find_fallthru_edge (block_from);
4897 block_next = ft_edge->dest;
4898 /* There must be a fallthrough block (or where should go
4899 control flow in case of false jump predicate otherwise?). */
4900 gcc_assert (block_next);
4902 /* Create new empty basic block after source block. */
4903 block_new = sel_split_edge (ft_edge);
4904 gcc_assert (block_new->next_bb == block_next
4905 && block_from->next_bb == block_new);
4907 gcc_assert (BB_END (block_from) == insn);
4909 /* Move all instructions except INSN from BLOCK_FROM to
4911 for (link = prev; link != insn; link = NEXT_INSN (link))
4913 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
4914 df_insn_change_bb (link, block_new);
4917 /* Set correct basic block and instructions properties. */
4918 BB_END (block_new) = PREV_INSN (insn);
4920 NEXT_INSN (PREV_INSN (prev)) = insn;
4921 PREV_INSN (insn) = PREV_INSN (prev);
4923 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4924 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
4925 PREV_INSN (prev) = BB_HEAD (block_new);
4926 NEXT_INSN (next) = NEXT_INSN (BB_HEAD (block_new));
4927 NEXT_INSN (BB_HEAD (block_new)) = prev;
4928 PREV_INSN (NEXT_INSN (next)) = next;
4930 gcc_assert (!sel_bb_empty_p (block_from)
4931 && !sel_bb_empty_p (block_new));
4933 /* Update data sets for BLOCK_NEW to represent that INSN and
4934 instructions from the other branch of INSN is no longer
4935 available at BLOCK_NEW. */
4936 BB_AV_LEVEL (block_new) = global_level;
4937 gcc_assert (BB_LV_SET (block_new) == NULL);
4938 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
4939 update_data_sets (sel_bb_head (block_new));
4941 /* INSN is a new basic block header - so prepare its data
4942 structures and update availability and liveness sets. */
4943 update_data_sets (insn);
4945 if (sched_verbose >= 4)
4946 sel_print ("Moving jump %d\n", INSN_UID (insn));
4949 /* Remove nops generated during move_op for preventing removal of empty
4952 remove_temp_moveop_nops (bool full_tidying)
4957 for (i = 0; VEC_iterate (insn_t, vec_temp_moveop_nops, i, insn); i++)
4959 gcc_assert (INSN_NOP_P (insn));
4960 return_nop_to_pool (insn, full_tidying);
4963 /* Empty the vector. */
4964 if (VEC_length (insn_t, vec_temp_moveop_nops) > 0)
4965 VEC_block_remove (insn_t, vec_temp_moveop_nops, 0,
4966 VEC_length (insn_t, vec_temp_moveop_nops));
4969 /* Records the maximal UID before moving up an instruction. Used for
4970 distinguishing between bookkeeping copies and original insns. */
4971 static int max_uid_before_move_op = 0;
4973 /* Remove from AV_VLIW_P all instructions but next when debug counter
4974 tells us so. Next instruction is fetched from BNDS. */
4976 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
4978 if (! dbg_cnt (sel_sched_insn_cnt))
4979 /* Leave only the next insn in av_vliw. */
4981 av_set_iterator av_it;
4983 bnd_t bnd = BLIST_BND (bnds);
4984 insn_t next = BND_TO (bnd);
4986 gcc_assert (BLIST_NEXT (bnds) == NULL);
4988 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
4989 if (EXPR_INSN_RTX (expr) != next)
4990 av_set_iter_remove (&av_it);
4994 /* Compute available instructions on BNDS. FENCE is the current fence. Write
4995 the computed set to *AV_VLIW_P. */
4997 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
4999 if (sched_verbose >= 2)
5001 sel_print ("Boundaries: ");
5006 for (; bnds; bnds = BLIST_NEXT (bnds))
5008 bnd_t bnd = BLIST_BND (bnds);
5010 insn_t bnd_to = BND_TO (bnd);
5012 /* Rewind BND->TO to the basic block header in case some bookkeeping
5013 instructions were inserted before BND->TO and it needs to be
5015 if (sel_bb_head_p (bnd_to))
5016 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
5018 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
5020 bnd_to = PREV_INSN (bnd_to);
5021 if (sel_bb_head_p (bnd_to))
5025 if (BND_TO (bnd) != bnd_to)
5027 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
5028 FENCE_INSN (fence) = bnd_to;
5029 BND_TO (bnd) = bnd_to;
5032 av_set_clear (&BND_AV (bnd));
5033 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
5035 av_set_clear (&BND_AV1 (bnd));
5036 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
5038 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
5040 av1_copy = av_set_copy (BND_AV1 (bnd));
5041 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
5044 if (sched_verbose >= 2)
5046 sel_print ("Available exprs (vliw form): ");
5047 dump_av_set (*av_vliw_p);
5052 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5053 expression. When FOR_MOVEOP is true, also replace the register of
5054 expressions found with the register from EXPR_VLIW. */
5056 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
5058 av_set_t expr_seq = NULL;
5062 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
5064 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
5068 /* The sequential expression has the right form to pass
5069 to move_op except when renaming happened. Put the
5070 correct register in EXPR then. */
5071 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
5073 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
5075 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
5076 stat_renamed_scheduled++;
5078 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5079 This is needed when renaming came up with original
5081 else if (EXPR_TARGET_AVAILABLE (expr)
5082 != EXPR_TARGET_AVAILABLE (expr_vliw))
5084 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
5085 EXPR_TARGET_AVAILABLE (expr) = 1;
5088 if (EXPR_WAS_SUBSTITUTED (expr))
5089 stat_substitutions_total++;
5092 av_set_add (&expr_seq, expr);
5094 /* With substitution inside insn group, it is possible
5095 that more than one expression in expr_seq will correspond
5096 to expr_vliw. In this case, choose one as the attempt to
5097 move both leads to miscompiles. */
5102 if (for_moveop && sched_verbose >= 2)
5104 sel_print ("Best expression(s) (sequential form): ");
5105 dump_av_set (expr_seq);
5113 /* Move nop to previous block. */
5114 static void ATTRIBUTE_UNUSED
5115 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
5117 insn_t prev_insn, next_insn, note;
5119 gcc_assert (sel_bb_head_p (nop)
5120 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
5121 note = bb_note (BLOCK_FOR_INSN (nop));
5122 prev_insn = sel_bb_end (prev_bb);
5123 next_insn = NEXT_INSN (nop);
5124 gcc_assert (prev_insn != NULL_RTX
5125 && PREV_INSN (note) == prev_insn);
5127 NEXT_INSN (prev_insn) = nop;
5128 PREV_INSN (nop) = prev_insn;
5130 PREV_INSN (note) = nop;
5131 NEXT_INSN (note) = next_insn;
5133 NEXT_INSN (nop) = note;
5134 PREV_INSN (next_insn) = note;
5136 BB_END (prev_bb) = nop;
5137 BLOCK_FOR_INSN (nop) = prev_bb;
5140 /* Prepare a place to insert the chosen expression on BND. */
5142 prepare_place_to_insert (bnd_t bnd)
5144 insn_t place_to_insert;
5146 /* Init place_to_insert before calling move_op, as the later
5147 can possibly remove BND_TO (bnd). */
5148 if (/* If this is not the first insn scheduled. */
5151 /* Add it after last scheduled. */
5152 place_to_insert = ILIST_INSN (BND_PTR (bnd));
5153 if (DEBUG_INSN_P (place_to_insert))
5155 ilist_t l = BND_PTR (bnd);
5156 while ((l = ILIST_NEXT (l)) &&
5157 DEBUG_INSN_P (ILIST_INSN (l)))
5160 place_to_insert = NULL;
5164 place_to_insert = NULL;
5166 if (!place_to_insert)
5168 /* Add it before BND_TO. The difference is in the
5169 basic block, where INSN will be added. */
5170 place_to_insert = get_nop_from_pool (BND_TO (bnd));
5171 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
5172 == BLOCK_FOR_INSN (BND_TO (bnd)));
5175 return place_to_insert;
5178 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5179 Return the expression to emit in C_EXPR. */
5181 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5182 av_set_t expr_seq, expr_t c_expr)
5184 bool b, should_move;
5187 int n_bookkeeping_copies_before_moveop;
5189 /* Make a move. This call will remove the original operation,
5190 insert all necessary bookkeeping instructions and update the
5191 data sets. After that all we have to do is add the operation
5192 at before BND_TO (BND). */
5193 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5194 max_uid_before_move_op = get_max_uid ();
5195 bitmap_clear (current_copies);
5196 bitmap_clear (current_originators);
5198 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5199 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5201 /* We should be able to find the expression we've chosen for
5205 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5206 stat_insns_needed_bookkeeping++;
5208 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5213 /* We allocate these bitmaps lazily. */
5214 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5215 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5217 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5218 current_originators);
5220 /* Transitively add all originators' originators. */
5221 EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi)
5222 if (INSN_ORIGINATORS_BY_UID (uid))
5223 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid),
5224 INSN_ORIGINATORS_BY_UID (uid));
5231 /* Debug a DFA state as an array of bytes. */
5233 debug_state (state_t state)
5236 unsigned int i, size = dfa_state_size;
5238 sel_print ("state (%u):", size);
5239 for (i = 0, p = (unsigned char *) state; i < size; i++)
5240 sel_print (" %d", p[i]);
5244 /* Advance state on FENCE with INSN. Return true if INSN is
5245 an ASM, and we should advance state once more. */
5247 advance_state_on_fence (fence_t fence, insn_t insn)
5251 if (recog_memoized (insn) >= 0)
5254 state_t temp_state = alloca (dfa_state_size);
5256 gcc_assert (!INSN_ASM_P (insn));
5259 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5260 res = state_transition (FENCE_STATE (fence), insn);
5261 gcc_assert (res < 0);
5263 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5265 FENCE_ISSUED_INSNS (fence)++;
5267 /* We should never issue more than issue_rate insns. */
5268 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5274 /* This could be an ASM insn which we'd like to schedule
5275 on the next cycle. */
5276 asm_p = INSN_ASM_P (insn);
5277 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5278 advance_one_cycle (fence);
5281 if (sched_verbose >= 2)
5282 debug_state (FENCE_STATE (fence));
5283 if (!DEBUG_INSN_P (insn))
5284 FENCE_STARTS_CYCLE_P (fence) = 0;
5285 FENCE_ISSUE_MORE (fence) = can_issue_more;
5289 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5290 is nonzero if we need to stall after issuing INSN. */
5292 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5296 /* First, reflect that something is scheduled on this fence. */
5297 asm_p = advance_state_on_fence (fence, insn);
5298 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5299 VEC_safe_push (rtx, gc, FENCE_EXECUTING_INSNS (fence), insn);
5300 if (SCHED_GROUP_P (insn))
5302 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5303 SCHED_GROUP_P (insn) = 0;
5306 FENCE_SCHED_NEXT (fence) = NULL_RTX;
5307 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5308 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5310 /* Set instruction scheduling info. This will be used in bundling,
5311 pipelining, tick computations etc. */
5312 ++INSN_SCHED_TIMES (insn);
5313 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5314 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5315 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5316 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5318 /* This does not account for adjust_cost hooks, just add the biggest
5319 constant the hook may add to the latency. TODO: make this
5320 a target dependent constant. */
5321 INSN_READY_CYCLE (insn)
5322 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5324 : maximal_insn_latency (insn) + 1);
5326 /* Change these fields last, as they're used above. */
5327 FENCE_AFTER_STALL_P (fence) = 0;
5328 if (asm_p || need_stall)
5329 advance_one_cycle (fence);
5331 /* Indicate that we've scheduled something on this fence. */
5332 FENCE_SCHEDULED_P (fence) = true;
5333 scheduled_something_on_previous_fence = true;
5335 /* Print debug information when insn's fields are updated. */
5336 if (sched_verbose >= 2)
5338 sel_print ("Scheduling insn: ");
5339 dump_insn_1 (insn, 1);
5344 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5345 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5348 update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp,
5349 blist_t *bnds_tailp)
5354 advance_deps_context (BND_DC (bnd), insn);
5355 FOR_EACH_SUCC_1 (succ, si, insn,
5356 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5358 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5360 ilist_add (&ptr, insn);
5362 if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn)
5363 && is_ineligible_successor (succ, ptr))
5369 if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn))
5371 if (sched_verbose >= 9)
5372 sel_print ("Updating fence insn from %i to %i\n",
5373 INSN_UID (insn), INSN_UID (succ));
5374 FENCE_INSN (fence) = succ;
5376 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5377 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5380 blist_remove (bndsp);
5384 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5386 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5389 expr_t c_expr = XALLOCA (expr_def);
5390 insn_t place_to_insert;
5394 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5396 /* In case of scheduling a jump skipping some other instructions,
5397 prepare CFG. After this, jump is at the boundary and can be
5398 scheduled as usual insn by MOVE_OP. */
5399 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5401 insn = EXPR_INSN_RTX (expr_vliw);
5403 /* Speculative jumps are not handled. */
5404 if (insn != BND_TO (bnd)
5405 && !sel_insn_is_speculation_check (insn))
5406 move_cond_jump (insn, bnd);
5409 /* Find a place for C_EXPR to schedule. */
5410 place_to_insert = prepare_place_to_insert (bnd);
5411 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5412 clear_expr (c_expr);
5414 /* Add the instruction. The corner case to care about is when
5415 the expr_seq set has more than one expr, and we chose the one that
5416 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5417 we can't use it. Generate the new vinsn. */
5418 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5422 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5423 change_vinsn_in_expr (expr_vliw, vinsn_new);
5424 should_move = false;
5427 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5429 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5432 /* Return the nops generated for preserving of data sets back
5434 if (INSN_NOP_P (place_to_insert))
5435 return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn));
5436 remove_temp_moveop_nops (!DEBUG_INSN_P (insn));
5438 av_set_clear (&expr_seq);
5440 /* Save the expression scheduled so to reset target availability if we'll
5441 meet it later on the same fence. */
5442 if (EXPR_WAS_RENAMED (expr_vliw))
5443 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5445 /* Check that the recent movement didn't destroyed loop
5447 gcc_assert (!pipelining_p
5448 || current_loop_nest == NULL
5449 || loop_latch_edge (current_loop_nest));
5453 /* Stall for N cycles on FENCE. */
5455 stall_for_cycles (fence_t fence, int n)
5459 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5461 advance_one_cycle (fence);
5463 FENCE_AFTER_STALL_P (fence) = 1;
5466 /* Gather a parallel group of insns at FENCE and assign their seqno
5467 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5468 list for later recalculation of seqnos. */
5470 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5472 blist_t bnds = NULL, *bnds_tailp;
5473 av_set_t av_vliw = NULL;
5474 insn_t insn = FENCE_INSN (fence);
5476 if (sched_verbose >= 2)
5477 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5478 INSN_UID (insn), FENCE_CYCLE (fence));
5480 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5481 bnds_tailp = &BLIST_NEXT (bnds);
5482 set_target_context (FENCE_TC (fence));
5483 can_issue_more = FENCE_ISSUE_MORE (fence);
5484 target_bb = INSN_BB (insn);
5486 /* Do while we can add any operation to the current group. */
5489 blist_t *bnds_tailp1, *bndsp;
5492 int was_stall = 0, scheduled_insns = 0, stall_iterations = 0;
5493 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5494 int max_stall = pipelining_p ? 1 : 3;
5495 bool last_insn_was_debug = false;
5496 bool was_debug_bb_end_p = false;
5498 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5499 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5500 remove_insns_for_debug (bnds, &av_vliw);
5502 /* Return early if we have nothing to schedule. */
5503 if (av_vliw == NULL)
5506 /* Choose the best expression and, if needed, destination register
5510 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5511 if (!expr_vliw && need_stall)
5513 /* All expressions required a stall. Do not recompute av sets
5514 as we'll get the same answer (modulo the insns between
5515 the fence and its boundary, which will not be available for
5517 gcc_assert (! expr_vliw && stall_iterations < 2);
5519 /* If we are going to stall for too long, break to recompute av
5520 sets and bring more insns for pipelining. */
5521 if (need_stall <= 3)
5522 stall_for_cycles (fence, need_stall);
5525 stall_for_cycles (fence, 1);
5530 while (! expr_vliw && need_stall);
5532 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5535 av_set_clear (&av_vliw);
5540 bnds_tailp1 = bnds_tailp;
5543 /* This code will be executed only once until we'd have several
5544 boundaries per fence. */
5546 bnd_t bnd = BLIST_BND (*bndsp);
5548 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5550 bndsp = &BLIST_NEXT (*bndsp);
5554 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5555 last_insn_was_debug = DEBUG_INSN_P (insn);
5556 if (last_insn_was_debug)
5557 was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn));
5558 update_fence_and_insn (fence, insn, need_stall);
5559 bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp);
5561 /* Add insn to the list of scheduled on this cycle instructions. */
5562 ilist_add (*scheduled_insns_tailpp, insn);
5563 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5565 while (*bndsp != *bnds_tailp1);
5567 av_set_clear (&av_vliw);
5568 if (!last_insn_was_debug)
5571 /* We currently support information about candidate blocks only for
5572 one 'target_bb' block. Hence we can't schedule after jump insn,
5573 as this will bring two boundaries and, hence, necessity to handle
5574 information for two or more blocks concurrently. */
5575 if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn))
5577 && (was_stall >= max_stall
5578 || scheduled_insns >= max_insns)))
5583 gcc_assert (!FENCE_BNDS (fence));
5585 /* Update boundaries of the FENCE. */
5588 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5592 insn = ILIST_INSN (ptr);
5594 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5595 ilist_add (&FENCE_BNDS (fence), insn);
5598 blist_remove (&bnds);
5601 /* Update target context on the fence. */
5602 reset_target_context (FENCE_TC (fence), false);
5605 /* All exprs in ORIG_OPS must have the same destination register or memory.
5606 Return that destination. */
5608 get_dest_from_orig_ops (av_set_t orig_ops)
5610 rtx dest = NULL_RTX;
5611 av_set_iterator av_it;
5613 bool first_p = true;
5615 FOR_EACH_EXPR (expr, av_it, orig_ops)
5617 rtx x = EXPR_LHS (expr);
5625 gcc_assert (dest == x
5626 || (dest != NULL_RTX && x != NULL_RTX
5627 && rtx_equal_p (dest, x)));
5633 /* Update data sets for the bookkeeping block and record those expressions
5634 which become no longer available after inserting this bookkeeping. */
5636 update_and_record_unavailable_insns (basic_block book_block)
5639 av_set_t old_av_set = NULL;
5641 rtx bb_end = sel_bb_end (book_block);
5643 /* First, get correct liveness in the bookkeeping block. The problem is
5644 the range between the bookeeping insn and the end of block. */
5645 update_liveness_on_insn (bb_end);
5646 if (control_flow_insn_p (bb_end))
5647 update_liveness_on_insn (PREV_INSN (bb_end));
5649 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5650 fence above, where we may choose to schedule an insn which is
5651 actually blocked from moving up with the bookkeeping we create here. */
5652 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5654 old_av_set = av_set_copy (BB_AV_SET (book_block));
5655 update_data_sets (sel_bb_head (book_block));
5657 /* Traverse all the expressions in the old av_set and check whether
5658 CUR_EXPR is in new AV_SET. */
5659 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5661 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5662 EXPR_VINSN (cur_expr));
5665 /* In this case, we can just turn off the E_T_A bit, but we can't
5666 represent this information with the current vector. */
5667 || EXPR_TARGET_AVAILABLE (new_expr)
5668 != EXPR_TARGET_AVAILABLE (cur_expr))
5669 /* Unfortunately, the below code could be also fired up on
5671 FIXME: add an example of how this could happen. */
5672 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5675 av_set_clear (&old_av_set);
5679 /* The main effect of this function is that sparams->c_expr is merged
5680 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5681 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5682 lparams->c_expr_merged is copied back to sparams->c_expr after all
5683 successors has been traversed. lparams->c_expr_local is an expr allocated
5684 on stack in the caller function, and is used if there is more than one
5687 SUCC is one of the SUCCS_NORMAL successors of INSN,
5688 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5689 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5691 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5692 insn_t succ ATTRIBUTE_UNUSED,
5693 int moveop_drv_call_res,
5694 cmpd_local_params_p lparams, void *static_params)
5696 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5698 /* Nothing to do, if original expr wasn't found below. */
5699 if (moveop_drv_call_res != 1)
5702 /* If this is a first successor. */
5703 if (!lparams->c_expr_merged)
5705 lparams->c_expr_merged = sparams->c_expr;
5706 sparams->c_expr = lparams->c_expr_local;
5710 /* We must merge all found expressions to get reasonable
5711 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5712 do so then we can first find the expr with epsilon
5713 speculation success probability and only then with the
5714 good probability. As a result the insn will get epsilon
5715 probability and will never be scheduled because of
5716 weakness_cutoff in find_best_expr.
5718 We call merge_expr_data here instead of merge_expr
5719 because due to speculation C_EXPR and X may have the
5720 same insns with different speculation types. And as of
5721 now such insns are considered non-equal.
5723 However, EXPR_SCHED_TIMES is different -- we must get
5724 SCHED_TIMES from a real insn, not a bookkeeping copy.
5725 We force this here. Instead, we may consider merging
5726 SCHED_TIMES to the maximum instead of minimum in the
5728 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5730 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5731 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5732 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5734 clear_expr (sparams->c_expr);
5738 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5740 SUCC is one of the SUCCS_NORMAL successors of INSN,
5741 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5742 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5743 STATIC_PARAMS contain USED_REGS set. */
5745 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5746 int moveop_drv_call_res,
5747 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5748 void *static_params)
5751 fur_static_params_p sparams = (fur_static_params_p) static_params;
5753 /* Here we compute live regsets only for branches that do not lie
5754 on the code motion paths. These branches correspond to value
5755 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5756 for such branches code_motion_path_driver is not called. */
5757 if (moveop_drv_call_res != 0)
5760 /* Mark all registers that do not meet the following condition:
5761 (3) not live on the other path of any conditional branch
5762 that is passed by the operation, in case original
5763 operations are not present on both paths of the
5764 conditional branch. */
5765 succ_live = compute_live (succ);
5766 IOR_REG_SET (sparams->used_regs, succ_live);
5769 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5772 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5774 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5776 sp->c_expr = lp->c_expr_merged;
5779 /* Track bookkeeping copies created, insns scheduled, and blocks for
5780 rescheduling when INSN is found by move_op. */
5782 track_scheduled_insns_and_blocks (rtx insn)
5784 /* Even if this insn can be a copy that will be removed during current move_op,
5785 we still need to count it as an originator. */
5786 bitmap_set_bit (current_originators, INSN_UID (insn));
5788 if (!bitmap_bit_p (current_copies, INSN_UID (insn)))
5790 /* Note that original block needs to be rescheduled, as we pulled an
5791 instruction out of it. */
5792 if (INSN_SCHED_TIMES (insn) > 0)
5793 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5794 else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn))
5795 num_insns_scheduled++;
5798 bitmap_clear_bit (current_copies, INSN_UID (insn));
5800 /* For instructions we must immediately remove insn from the
5801 stream, so subsequent update_data_sets () won't include this
5803 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5804 if (INSN_UID (insn) > max_uid_before_move_op)
5805 stat_bookkeeping_copies--;
5808 /* Emit a register-register copy for INSN if needed. Return true if
5809 emitted one. PARAMS is the move_op static parameters. */
5811 maybe_emit_renaming_copy (rtx insn,
5812 moveop_static_params_p params)
5814 bool insn_emitted = false;
5815 rtx cur_reg = expr_dest_reg (params->c_expr);
5817 gcc_assert (!cur_reg || (params->dest && REG_P (params->dest)));
5819 /* If original operation has expr and the register chosen for
5820 that expr is not original operation's dest reg, substitute
5821 operation's right hand side with the register chosen. */
5822 if (cur_reg != NULL_RTX && REGNO (params->dest) != REGNO (cur_reg))
5824 insn_t reg_move_insn, reg_move_insn_rtx;
5826 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5828 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5832 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5833 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5835 insn_emitted = true;
5836 params->was_renamed = true;
5839 return insn_emitted;
5842 /* Emit a speculative check for INSN speculated as EXPR if needed.
5843 Return true if we've emitted one. PARAMS is the move_op static
5846 maybe_emit_speculative_check (rtx insn, expr_t expr,
5847 moveop_static_params_p params)
5849 bool insn_emitted = false;
5853 check_ds = get_spec_check_type_for_insn (insn, expr);
5856 /* A speculation check should be inserted. */
5857 x = create_speculation_check (params->c_expr, check_ds, insn);
5858 insn_emitted = true;
5862 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5866 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5867 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5868 return insn_emitted;
5871 /* Handle transformations that leave an insn in place of original
5872 insn such as renaming/speculation. Return true if one of such
5873 transformations actually happened, and we have emitted this insn. */
5875 handle_emitting_transformations (rtx insn, expr_t expr,
5876 moveop_static_params_p params)
5878 bool insn_emitted = false;
5880 insn_emitted = maybe_emit_renaming_copy (insn, params);
5881 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5883 return insn_emitted;
5886 /* If INSN is the only insn in the basic block (not counting JUMP,
5887 which may be a jump to next insn, and DEBUG_INSNs), we want to
5888 leave a NOP there till the return to fill_insns. */
5891 need_nop_to_preserve_insn_bb (rtx insn)
5893 insn_t bb_head, bb_end, bb_next, in_next;
5894 basic_block bb = BLOCK_FOR_INSN (insn);
5896 bb_head = sel_bb_head (bb);
5897 bb_end = sel_bb_end (bb);
5899 if (bb_head == bb_end)
5902 while (bb_head != bb_end && DEBUG_INSN_P (bb_head))
5903 bb_head = NEXT_INSN (bb_head);
5905 if (bb_head == bb_end)
5908 while (bb_head != bb_end && DEBUG_INSN_P (bb_end))
5909 bb_end = PREV_INSN (bb_end);
5911 if (bb_head == bb_end)
5914 bb_next = NEXT_INSN (bb_head);
5915 while (bb_next != bb_end && DEBUG_INSN_P (bb_next))
5916 bb_next = NEXT_INSN (bb_next);
5918 if (bb_next == bb_end && JUMP_P (bb_end))
5921 in_next = NEXT_INSN (insn);
5922 while (DEBUG_INSN_P (in_next))
5923 in_next = NEXT_INSN (in_next);
5925 if (IN_CURRENT_FENCE_P (in_next))
5931 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5932 is not removed but reused when INSN is re-emitted. */
5934 remove_insn_from_stream (rtx insn, bool only_disconnect)
5936 /* If there's only one insn in the BB, make sure that a nop is
5937 inserted into it, so the basic block won't disappear when we'll
5938 delete INSN below with sel_remove_insn. It should also survive
5939 till the return to fill_insns. */
5940 if (need_nop_to_preserve_insn_bb (insn))
5942 insn_t nop = get_nop_from_pool (insn);
5943 gcc_assert (INSN_NOP_P (nop));
5944 VEC_safe_push (insn_t, heap, vec_temp_moveop_nops, nop);
5947 sel_remove_insn (insn, only_disconnect, false);
5950 /* This function is called when original expr is found.
5951 INSN - current insn traversed, EXPR - the corresponding expr found.
5952 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5953 is static parameters of move_op. */
5955 move_op_orig_expr_found (insn_t insn, expr_t expr,
5956 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5957 void *static_params)
5959 bool only_disconnect, insn_emitted;
5960 moveop_static_params_p params = (moveop_static_params_p) static_params;
5962 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
5963 track_scheduled_insns_and_blocks (insn);
5964 insn_emitted = handle_emitting_transformations (insn, expr, params);
5965 only_disconnect = (params->uid == INSN_UID (insn)
5966 && ! insn_emitted && ! EXPR_WAS_CHANGED (expr));
5968 /* Mark that we've disconnected an insn. */
5969 if (only_disconnect)
5971 remove_insn_from_stream (insn, only_disconnect);
5974 /* The function is called when original expr is found.
5975 INSN - current insn traversed, EXPR - the corresponding expr found,
5976 crosses_call and original_insns in STATIC_PARAMS are updated. */
5978 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
5979 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5980 void *static_params)
5982 fur_static_params_p params = (fur_static_params_p) static_params;
5986 params->crosses_call = true;
5988 def_list_add (params->original_insns, insn, params->crosses_call);
5990 /* Mark the registers that do not meet the following condition:
5991 (2) not among the live registers of the point
5992 immediately following the first original operation on
5993 a given downward path, except for the original target
5994 register of the operation. */
5995 tmp = get_clear_regset_from_pool ();
5996 compute_live_below_insn (insn, tmp);
5997 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
5998 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
5999 IOR_REG_SET (params->used_regs, tmp);
6000 return_regset_to_pool (tmp);
6002 /* (*1) We need to add to USED_REGS registers that are read by
6003 INSN's lhs. This may lead to choosing wrong src register.
6004 E.g. (scheduling const expr enabled):
6006 429: ax=0x0 <- Can't use AX for this expr (0x0)
6013 /* FIXME: see comment above and enable MEM_P
6014 in vinsn_separable_p. */
6015 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
6016 || !MEM_P (INSN_LHS (insn)));
6019 /* This function is called on the ascending pass, before returning from
6020 current basic block. */
6022 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
6023 void *static_params)
6025 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6026 basic_block book_block = NULL;
6028 /* When we have removed the boundary insn for scheduling, which also
6029 happened to be the end insn in its bb, we don't need to update sets. */
6030 if (!lparams->removed_last_insn
6032 && sel_bb_head_p (insn))
6034 /* We should generate bookkeeping code only if we are not at the
6035 top level of the move_op. */
6036 if (sel_num_cfg_preds_gt_1 (insn))
6037 book_block = generate_bookkeeping_insn (sparams->c_expr,
6038 lparams->e1, lparams->e2);
6039 /* Update data sets for the current insn. */
6040 update_data_sets (insn);
6043 /* If bookkeeping code was inserted, we need to update av sets of basic
6044 block that received bookkeeping. After generation of bookkeeping insn,
6045 bookkeeping block does not contain valid av set because we are not following
6046 the original algorithm in every detail with regards to e.g. renaming
6047 simple reg-reg copies. Consider example:
6049 bookkeeping block scheduling fence
6059 We try to schedule insn "r1 := r3" on the current
6060 scheduling fence. Also, note that av set of bookkeeping block
6061 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6062 been scheduled, the CFG is as follows:
6065 bookkeeping block scheduling fence
6075 Here, insn "r1 := r3" was scheduled at the current scheduling point
6076 and bookkeeping code was generated at the bookeeping block. This
6077 way insn "r1 := r2" is no longer available as a whole instruction
6078 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6079 This situation is handled by calling update_data_sets.
6081 Since update_data_sets is called only on the bookkeeping block, and
6082 it also may have predecessors with av_sets, containing instructions that
6083 are no longer available, we save all such expressions that become
6084 unavailable during data sets update on the bookkeeping block in
6085 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6086 expressions for scheduling. This allows us to avoid recomputation of
6087 av_sets outside the code motion path. */
6090 update_and_record_unavailable_insns (book_block);
6092 /* If INSN was previously marked for deletion, it's time to do it. */
6093 if (lparams->removed_last_insn)
6094 insn = PREV_INSN (insn);
6096 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6097 kill a block with a single nop in which the insn should be emitted. */
6099 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
6102 /* This function is called on the ascending pass, before returning from the
6103 current basic block. */
6105 fur_at_first_insn (insn_t insn,
6106 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6107 void *static_params ATTRIBUTE_UNUSED)
6109 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
6110 || AV_LEVEL (insn) == -1);
6113 /* Called on the backward stage of recursion to call moveup_expr for insn
6114 and sparams->c_expr. */
6116 move_op_ascend (insn_t insn, void *static_params)
6118 enum MOVEUP_EXPR_CODE res;
6119 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6121 if (! INSN_NOP_P (insn))
6123 res = moveup_expr_cached (sparams->c_expr, insn, false);
6124 gcc_assert (res != MOVEUP_EXPR_NULL);
6127 /* Update liveness for this insn as it was invalidated. */
6128 update_liveness_on_insn (insn);
6131 /* This function is called on enter to the basic block.
6132 Returns TRUE if this block already have been visited and
6133 code_motion_path_driver should return 1, FALSE otherwise. */
6135 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
6136 void *static_params, bool visited_p)
6138 fur_static_params_p sparams = (fur_static_params_p) static_params;
6142 /* If we have found something below this block, there should be at
6143 least one insn in ORIGINAL_INSNS. */
6144 gcc_assert (*sparams->original_insns);
6146 /* Adjust CROSSES_CALL, since we may have come to this block along
6148 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
6149 |= sparams->crosses_call;
6152 local_params->old_original_insns = *sparams->original_insns;
6157 /* Same as above but for move_op. */
6159 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
6160 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
6161 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
6168 /* This function is called while descending current basic block if current
6169 insn is not the original EXPR we're searching for.
6171 Return value: FALSE, if code_motion_path_driver should perform a local
6172 cleanup and return 0 itself;
6173 TRUE, if code_motion_path_driver should continue. */
6175 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
6176 void *static_params)
6178 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6180 #ifdef ENABLE_CHECKING
6181 sparams->failed_insn = insn;
6184 /* If we're scheduling separate expr, in order to generate correct code
6185 we need to stop the search at bookkeeping code generated with the
6186 same destination register or memory. */
6187 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
6192 /* This function is called while descending current basic block if current
6193 insn is not the original EXPR we're searching for.
6195 Return value: TRUE (code_motion_path_driver should continue). */
6197 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
6201 av_set_iterator avi;
6202 fur_static_params_p sparams = (fur_static_params_p) static_params;
6205 sparams->crosses_call = true;
6206 else if (DEBUG_INSN_P (insn))
6209 /* If current insn we are looking at cannot be executed together
6210 with original insn, then we can skip it safely.
6212 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6213 INSN = (!p6) r14 = r14 + 1;
6215 Here we can schedule ORIG_OP with lhs = r14, though only
6216 looking at the set of used and set registers of INSN we must
6217 forbid it. So, add set/used in INSN registers to the
6218 untouchable set only if there is an insn in ORIG_OPS that can
6221 FOR_EACH_EXPR (r, avi, orig_ops)
6222 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
6228 /* Mark all registers that do not meet the following condition:
6229 (1) Not set or read on any path from xi to an instance of the
6230 original operation. */
6233 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6234 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6235 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6241 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6242 struct code_motion_path_driver_info_def move_op_hooks = {
6244 move_op_orig_expr_found,
6245 move_op_orig_expr_not_found,
6246 move_op_merge_succs,
6247 move_op_after_merge_succs,
6249 move_op_at_first_insn,
6254 /* Hooks and data to perform find_used_regs operations
6255 with code_motion_path_driver. */
6256 struct code_motion_path_driver_info_def fur_hooks = {
6258 fur_orig_expr_found,
6259 fur_orig_expr_not_found,
6261 NULL, /* fur_after_merge_succs */
6262 NULL, /* fur_ascend */
6268 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6269 code_motion_path_driver is called recursively. Original operation
6270 was found at least on one path that is starting with one of INSN's
6271 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6272 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6273 of either move_op or find_used_regs depending on the caller.
6275 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6276 know for sure at this point. */
6278 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6279 ilist_t path, void *static_params)
6282 succ_iterator succ_i;
6288 struct cmpd_local_params lparams;
6291 lparams.c_expr_local = &_x;
6292 lparams.c_expr_merged = NULL;
6294 /* We need to process only NORMAL succs for move_op, and collect live
6295 registers from ALL branches (including those leading out of the
6296 region) for find_used_regs.
6298 In move_op, there can be a case when insn's bb number has changed
6299 due to created bookkeeping. This happens very rare, as we need to
6300 move expression from the beginning to the end of the same block.
6301 Rescan successors in this case. */
6304 bb = BLOCK_FOR_INSN (insn);
6305 old_index = bb->index;
6306 old_succs = EDGE_COUNT (bb->succs);
6308 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6312 lparams.e1 = succ_i.e1;
6313 lparams.e2 = succ_i.e2;
6315 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6317 if (succ_i.current_flags == SUCCS_NORMAL)
6318 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6323 /* Merge c_expres found or unify live register sets from different
6325 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6329 else if (b == -1 && res != 1)
6332 /* We have simplified the control flow below this point. In this case,
6333 the iterator becomes invalid. We need to try again. */
6334 if (BLOCK_FOR_INSN (insn)->index != old_index
6335 || EDGE_COUNT (bb->succs) != old_succs)
6339 #ifdef ENABLE_CHECKING
6340 /* Here, RES==1 if original expr was found at least for one of the
6341 successors. After the loop, RES may happen to have zero value
6342 only if at some point the expr searched is present in av_set, but is
6343 not found below. In most cases, this situation is an error.
6344 The exception is when the original operation is blocked by
6345 bookkeeping generated for another fence or for another path in current
6347 gcc_assert (res == 1
6349 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops,
6354 /* Merge data, clean up, etc. */
6355 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6356 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6362 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6363 is the pointer to the av set with expressions we were looking for,
6364 PATH_P is the pointer to the traversed path. */
6366 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6368 ilist_remove (path_p);
6369 av_set_clear (orig_ops_p);
6372 /* The driver function that implements move_op or find_used_regs
6373 functionality dependent whether code_motion_path_driver_INFO is set to
6374 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6375 of code (CFG traversal etc) that are shared among both functions. INSN
6376 is the insn we're starting the search from, ORIG_OPS are the expressions
6377 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6378 parameters of the driver, and STATIC_PARAMS are static parameters of
6381 Returns whether original instructions were found. Note that top-level
6382 code_motion_path_driver always returns true. */
6384 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6385 cmpd_local_params_p local_params_in,
6386 void *static_params)
6389 basic_block bb = BLOCK_FOR_INSN (insn);
6390 insn_t first_insn, bb_tail, before_first;
6391 bool removed_last_insn = false;
6393 if (sched_verbose >= 6)
6395 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6398 dump_av_set (orig_ops);
6402 gcc_assert (orig_ops);
6404 /* If no original operations exist below this insn, return immediately. */
6405 if (is_ineligible_successor (insn, path))
6407 if (sched_verbose >= 6)
6408 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6412 /* The block can have invalid av set, in which case it was created earlier
6413 during move_op. Return immediately. */
6414 if (sel_bb_head_p (insn))
6416 if (! AV_SET_VALID_P (insn))
6418 if (sched_verbose >= 6)
6419 sel_print ("Returned from block %d as it had invalid av set\n",
6424 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6426 /* We have already found an original operation on this branch, do not
6427 go any further and just return TRUE here. If we don't stop here,
6428 function can have exponential behaviour even on the small code
6429 with many different paths (e.g. with data speculation and
6430 recovery blocks). */
6431 if (sched_verbose >= 6)
6432 sel_print ("Block %d already visited in this traversal\n", bb->index);
6433 if (code_motion_path_driver_info->on_enter)
6434 return code_motion_path_driver_info->on_enter (insn,
6441 if (code_motion_path_driver_info->on_enter)
6442 code_motion_path_driver_info->on_enter (insn, local_params_in,
6443 static_params, false);
6444 orig_ops = av_set_copy (orig_ops);
6446 /* Filter the orig_ops set. */
6447 if (AV_SET_VALID_P (insn))
6448 av_set_intersect (&orig_ops, AV_SET (insn));
6450 /* If no more original ops, return immediately. */
6453 if (sched_verbose >= 6)
6454 sel_print ("No intersection with av set of block %d\n", bb->index);
6458 /* For non-speculative insns we have to leave only one form of the
6459 original operation, because if we don't, we may end up with
6460 different C_EXPRes and, consequently, with bookkeepings for different
6461 expression forms along the same code motion path. That may lead to
6462 generation of incorrect code. So for each code motion we stick to
6463 the single form of the instruction, except for speculative insns
6464 which we need to keep in different forms with all speculation
6466 av_set_leave_one_nonspec (&orig_ops);
6468 /* It is not possible that all ORIG_OPS are filtered out. */
6469 gcc_assert (orig_ops);
6471 /* It is enough to place only heads and tails of visited basic blocks into
6473 ilist_add (&path, insn);
6475 bb_tail = sel_bb_end (bb);
6477 /* Descend the basic block in search of the original expr; this part
6478 corresponds to the part of the original move_op procedure executed
6479 before the recursive call. */
6482 /* Look at the insn and decide if it could be an ancestor of currently
6483 scheduling operation. If it is so, then the insn "dest = op" could
6484 either be replaced with "dest = reg", because REG now holds the result
6485 of OP, or just removed, if we've scheduled the insn as a whole.
6487 If this insn doesn't contain currently scheduling OP, then proceed
6488 with searching and look at its successors. Operations we're searching
6489 for could have changed when moving up through this insn via
6490 substituting. In this case, perform unsubstitution on them first.
6492 When traversing the DAG below this insn is finished, insert
6493 bookkeeping code, if the insn is a joint point, and remove
6496 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6499 insn_t last_insn = PREV_INSN (insn);
6501 /* We have found the original operation. */
6502 if (sched_verbose >= 6)
6503 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6505 code_motion_path_driver_info->orig_expr_found
6506 (insn, expr, local_params_in, static_params);
6508 /* Step back, so on the way back we'll start traversing from the
6509 previous insn (or we'll see that it's bb_note and skip that
6511 if (insn == first_insn)
6513 first_insn = NEXT_INSN (last_insn);
6514 removed_last_insn = sel_bb_end_p (last_insn);
6521 /* We haven't found the original expr, continue descending the basic
6523 if (code_motion_path_driver_info->orig_expr_not_found
6524 (insn, orig_ops, static_params))
6526 /* Av set ops could have been changed when moving through this
6527 insn. To find them below it, we have to un-substitute them. */
6528 undo_transformations (&orig_ops, insn);
6532 /* Clean up and return, if the hook tells us to do so. It may
6533 happen if we've encountered the previously created
6535 code_motion_path_driver_cleanup (&orig_ops, &path);
6539 gcc_assert (orig_ops);
6542 /* Stop at insn if we got to the end of BB. */
6543 if (insn == bb_tail)
6546 insn = NEXT_INSN (insn);
6549 /* Here INSN either points to the insn before the original insn (may be
6550 bb_note, if original insn was a bb_head) or to the bb_end. */
6555 gcc_assert (insn == sel_bb_end (bb));
6557 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6558 it's already in PATH then). */
6559 if (insn != first_insn)
6560 ilist_add (&path, insn);
6562 /* Process_successors should be able to find at least one
6563 successor for which code_motion_path_driver returns TRUE. */
6564 res = code_motion_process_successors (insn, orig_ops,
6565 path, static_params);
6567 /* Remove bb tail from path. */
6568 if (insn != first_insn)
6569 ilist_remove (&path);
6573 /* This is the case when one of the original expr is no longer available
6574 due to bookkeeping created on this branch with the same register.
6575 In the original algorithm, which doesn't have update_data_sets call
6576 on a bookkeeping block, it would simply result in returning
6577 FALSE when we've encountered a previously generated bookkeeping
6578 insn in moveop_orig_expr_not_found. */
6579 code_motion_path_driver_cleanup (&orig_ops, &path);
6584 /* Don't need it any more. */
6585 av_set_clear (&orig_ops);
6587 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6588 the beginning of the basic block. */
6589 before_first = PREV_INSN (first_insn);
6590 while (insn != before_first)
6592 if (code_motion_path_driver_info->ascend)
6593 code_motion_path_driver_info->ascend (insn, static_params);
6595 insn = PREV_INSN (insn);
6598 /* Now we're at the bb head. */
6600 ilist_remove (&path);
6601 local_params_in->removed_last_insn = removed_last_insn;
6602 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6604 /* This should be the very last operation as at bb head we could change
6605 the numbering by creating bookkeeping blocks. */
6606 if (removed_last_insn)
6607 insn = PREV_INSN (insn);
6608 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6612 /* Move up the operations from ORIG_OPS set traversing the dag starting
6613 from INSN. PATH represents the edges traversed so far.
6614 DEST is the register chosen for scheduling the current expr. Insert
6615 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6616 C_EXPR is how it looks like at the given cfg point.
6617 Set *SHOULD_MOVE to indicate whether we have only disconnected
6618 one of the insns found.
6620 Returns whether original instructions were found, which is asserted
6621 to be true in the caller. */
6623 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6624 rtx dest, expr_t c_expr, bool *should_move)
6626 struct moveop_static_params sparams;
6627 struct cmpd_local_params lparams;
6630 /* Init params for code_motion_path_driver. */
6631 sparams.dest = dest;
6632 sparams.c_expr = c_expr;
6633 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6634 #ifdef ENABLE_CHECKING
6635 sparams.failed_insn = NULL;
6637 sparams.was_renamed = false;
6640 /* We haven't visited any blocks yet. */
6641 bitmap_clear (code_motion_visited_blocks);
6643 /* Set appropriate hooks and data. */
6644 code_motion_path_driver_info = &move_op_hooks;
6645 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6647 if (sparams.was_renamed)
6648 EXPR_WAS_RENAMED (expr_vliw) = true;
6650 *should_move = (sparams.uid == -1);
6656 /* Functions that work with regions. */
6658 /* Current number of seqno used in init_seqno and init_seqno_1. */
6659 static int cur_seqno;
6661 /* A helper for init_seqno. Traverse the region starting from BB and
6662 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6663 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6665 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6667 int bbi = BLOCK_TO_BB (bb->index);
6668 insn_t insn, note = bb_note (bb);
6672 SET_BIT (visited_bbs, bbi);
6673 if (blocks_to_reschedule)
6674 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6676 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6677 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6679 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6680 int succ_bbi = BLOCK_TO_BB (succ->index);
6682 gcc_assert (in_current_region_p (succ));
6684 if (!TEST_BIT (visited_bbs, succ_bbi))
6686 gcc_assert (succ_bbi > bbi);
6688 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6692 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6693 INSN_SEQNO (insn) = cur_seqno--;
6696 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6697 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6698 which we're rescheduling when pipelining, FROM is the block where
6699 traversing region begins (it may not be the head of the region when
6700 pipelining, but the head of the loop instead).
6702 Returns the maximal seqno found. */
6704 init_seqno (int number_of_insns, bitmap blocks_to_reschedule, basic_block from)
6706 sbitmap visited_bbs;
6710 visited_bbs = sbitmap_alloc (current_nr_blocks);
6712 if (blocks_to_reschedule)
6714 sbitmap_ones (visited_bbs);
6715 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6717 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6718 RESET_BIT (visited_bbs, BLOCK_TO_BB (bbi));
6723 sbitmap_zero (visited_bbs);
6724 from = EBB_FIRST_BB (0);
6727 cur_seqno = number_of_insns > 0 ? number_of_insns : sched_max_luid - 1;
6728 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6729 gcc_assert (cur_seqno == 0 || number_of_insns == 0);
6731 sbitmap_free (visited_bbs);
6732 return sched_max_luid - 1;
6735 /* Initialize scheduling parameters for current region. */
6737 sel_setup_region_sched_flags (void)
6739 enable_schedule_as_rhs_p = 1;
6741 pipelining_p = (bookkeeping_p
6742 && (flag_sel_sched_pipelining != 0)
6743 && current_loop_nest != NULL);
6744 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6748 /* Return true if all basic blocks of current region are empty. */
6750 current_region_empty_p (void)
6753 for (i = 0; i < current_nr_blocks; i++)
6754 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i))))
6760 /* Prepare and verify loop nest for pipelining. */
6762 setup_current_loop_nest (int rgn)
6764 current_loop_nest = get_loop_nest_for_rgn (rgn);
6766 if (!current_loop_nest)
6769 /* If this loop has any saved loop preheaders from nested loops,
6770 add these basic blocks to the current region. */
6771 sel_add_loop_preheaders ();
6773 /* Check that we're starting with a valid information. */
6774 gcc_assert (loop_latch_edge (current_loop_nest));
6775 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6778 /* Compute instruction priorities for current region. */
6780 sel_compute_priorities (int rgn)
6782 sched_rgn_compute_dependencies (rgn);
6784 /* Compute insn priorities in haifa style. Then free haifa style
6785 dependencies that we've calculated for this. */
6786 compute_priorities ();
6788 if (sched_verbose >= 5)
6789 debug_rgn_dependencies (0);
6794 /* Init scheduling data for RGN. Returns true when this region should not
6797 sel_region_init (int rgn)
6802 rgn_setup_region (rgn);
6804 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6805 do region initialization here so the region can be bundled correctly,
6806 but we'll skip the scheduling in sel_sched_region (). */
6807 if (current_region_empty_p ())
6810 if (flag_sel_sched_pipelining)
6811 setup_current_loop_nest (rgn);
6813 sel_setup_region_sched_flags ();
6815 bbs = VEC_alloc (basic_block, heap, current_nr_blocks);
6817 for (i = 0; i < current_nr_blocks; i++)
6818 VEC_quick_push (basic_block, bbs, BASIC_BLOCK (BB_TO_BLOCK (i)));
6820 sel_init_bbs (bbs, NULL);
6822 /* Initialize luids and dependence analysis which both sel-sched and haifa
6824 sched_init_luids (bbs, NULL, NULL, NULL);
6825 sched_deps_init (false);
6827 /* Initialize haifa data. */
6828 rgn_setup_sched_infos ();
6829 sel_set_sched_flags ();
6830 haifa_init_h_i_d (bbs, NULL, NULL, NULL);
6832 sel_compute_priorities (rgn);
6833 init_deps_global ();
6835 /* Main initialization. */
6836 sel_setup_sched_infos ();
6837 sel_init_global_and_expr (bbs);
6839 VEC_free (basic_block, heap, bbs);
6841 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6843 /* Init correct liveness sets on each instruction of a single-block loop.
6844 This is the only situation when we can't update liveness when calling
6845 compute_live for the first insn of the loop. */
6846 if (current_loop_nest)
6848 int header = (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6852 if (current_nr_blocks == header + 1)
6853 update_liveness_on_insn
6854 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header))));
6857 /* Set hooks so that no newly generated insn will go out unnoticed. */
6858 sel_register_cfg_hooks ();
6860 /* !!! We call target.sched.md_init () for the whole region, but we invoke
6861 targetm.sched.md_finish () for every ebb. */
6862 if (targetm.sched.md_init)
6863 /* None of the arguments are actually used in any target. */
6864 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6866 first_emitted_uid = get_max_uid () + 1;
6867 preheader_removed = false;
6869 /* Reset register allocation ticks array. */
6870 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6871 reg_rename_this_tick = 0;
6873 bitmap_initialize (forced_ebb_heads, 0);
6874 bitmap_clear (forced_ebb_heads);
6877 current_copies = BITMAP_ALLOC (NULL);
6878 current_originators = BITMAP_ALLOC (NULL);
6879 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
6884 /* Simplify insns after the scheduling. */
6886 simplify_changed_insns (void)
6890 for (i = 0; i < current_nr_blocks; i++)
6892 basic_block bb = BASIC_BLOCK (BB_TO_BLOCK (i));
6895 FOR_BB_INSNS (bb, insn)
6898 expr_t expr = INSN_EXPR (insn);
6900 if (EXPR_WAS_SUBSTITUTED (expr))
6901 validate_simplify_insn (insn);
6906 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6907 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6908 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6910 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
6913 basic_block bb1 = bb;
6914 if (sched_verbose >= 2)
6915 sel_print ("Finishing schedule in bbs: ");
6919 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
6921 if (sched_verbose >= 2)
6922 sel_print ("%d; ", bb1->index);
6924 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
6926 if (sched_verbose >= 2)
6929 get_ebb_head_tail (bb, bb1, &head, &tail);
6931 current_sched_info->head = head;
6932 current_sched_info->tail = tail;
6933 current_sched_info->prev_head = PREV_INSN (head);
6934 current_sched_info->next_tail = NEXT_INSN (tail);
6937 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6939 reset_sched_cycles_in_current_ebb (void)
6942 int haifa_last_clock = -1;
6943 int haifa_clock = 0;
6946 if (targetm.sched.md_init)
6948 /* None of the arguments are actually used in any target.
6949 NB: We should have md_reset () hook for cases like this. */
6950 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6953 state_reset (curr_state);
6954 advance_state (curr_state);
6956 for (insn = current_sched_info->head;
6957 insn != current_sched_info->next_tail;
6958 insn = NEXT_INSN (insn))
6960 int cost, haifa_cost;
6962 bool asm_p, real_insn, after_stall;
6969 real_insn = recog_memoized (insn) >= 0;
6970 clock = INSN_SCHED_CYCLE (insn);
6972 cost = clock - last_clock;
6974 /* Initialize HAIFA_COST. */
6977 asm_p = INSN_ASM_P (insn);
6980 /* This is asm insn which *had* to be scheduled first
6984 /* This is a use/clobber insn. It should not change
6989 haifa_cost = estimate_insn_cost (insn, curr_state);
6991 /* Stall for whatever cycles we've stalled before. */
6993 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
7003 while (haifa_cost--)
7005 advance_state (curr_state);
7008 if (sched_verbose >= 2)
7010 sel_print ("advance_state (state_transition)\n");
7011 debug_state (curr_state);
7014 /* The DFA may report that e.g. insn requires 2 cycles to be
7015 issued, but on the next cycle it says that insn is ready
7016 to go. Check this here. */
7020 && estimate_insn_cost (insn, curr_state) == 0)
7027 gcc_assert (haifa_cost == 0);
7029 if (sched_verbose >= 2)
7030 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
7032 if (targetm.sched.dfa_new_cycle)
7033 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
7034 haifa_last_clock, haifa_clock,
7037 advance_state (curr_state);
7039 if (sched_verbose >= 2)
7041 sel_print ("advance_state (dfa_new_cycle)\n");
7042 debug_state (curr_state);
7048 cost = state_transition (curr_state, insn);
7050 if (sched_verbose >= 2)
7051 debug_state (curr_state);
7053 gcc_assert (cost < 0);
7056 if (targetm.sched.variable_issue)
7057 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
7059 INSN_SCHED_CYCLE (insn) = haifa_clock;
7062 haifa_last_clock = haifa_clock;
7066 /* Put TImode markers on insns starting a new issue group. */
7070 int last_clock = -1;
7073 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
7074 insn = NEXT_INSN (insn))
7081 clock = INSN_SCHED_CYCLE (insn);
7082 cost = (last_clock == -1) ? 1 : clock - last_clock;
7084 gcc_assert (cost >= 0);
7087 && GET_CODE (PATTERN (insn)) != USE
7088 && GET_CODE (PATTERN (insn)) != CLOBBER)
7090 if (reload_completed && cost > 0)
7091 PUT_MODE (insn, TImode);
7096 if (sched_verbose >= 2)
7097 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
7101 /* Perform MD_FINISH on EBBs comprising current region. When
7102 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7103 to produce correct sched cycles on insns. */
7105 sel_region_target_finish (bool reset_sched_cycles_p)
7108 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
7110 for (i = 0; i < current_nr_blocks; i++)
7112 if (bitmap_bit_p (scheduled_blocks, i))
7115 /* While pipelining outer loops, skip bundling for loop
7116 preheaders. Those will be rescheduled in the outer loop. */
7117 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
7120 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
7122 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
7125 if (reset_sched_cycles_p)
7126 reset_sched_cycles_in_current_ebb ();
7128 if (targetm.sched.md_init)
7129 targetm.sched.md_init (sched_dump, sched_verbose, -1);
7133 if (targetm.sched.md_finish)
7135 targetm.sched.md_finish (sched_dump, sched_verbose);
7137 /* Extend luids so that insns generated by the target will
7139 sched_init_luids (NULL, NULL, NULL, NULL);
7143 BITMAP_FREE (scheduled_blocks);
7146 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7147 is true, make an additional pass emulating scheduler to get correct insn
7148 cycles for md_finish calls. */
7150 sel_region_finish (bool reset_sched_cycles_p)
7152 simplify_changed_insns ();
7153 sched_finish_ready_list ();
7156 /* Free the vectors. */
7158 VEC_free (expr_t, heap, vec_av_set);
7159 BITMAP_FREE (current_copies);
7160 BITMAP_FREE (current_originators);
7161 BITMAP_FREE (code_motion_visited_blocks);
7162 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns);
7163 vinsn_vec_free (&vec_target_unavailable_vinsns);
7165 /* If LV_SET of the region head should be updated, do it now because
7166 there will be no other chance. */
7171 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
7172 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
7174 basic_block bb = BLOCK_FOR_INSN (insn);
7176 if (!BB_LV_SET_VALID_P (bb))
7177 compute_live (insn);
7181 /* Emulate the Haifa scheduler for bundling. */
7182 if (reload_completed)
7183 sel_region_target_finish (reset_sched_cycles_p);
7185 sel_finish_global_and_expr ();
7187 bitmap_clear (forced_ebb_heads);
7191 finish_deps_global ();
7192 sched_finish_luids ();
7195 BITMAP_FREE (blocks_to_reschedule);
7197 sel_unregister_cfg_hooks ();
7203 /* Functions that implement the scheduler driver. */
7205 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7206 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7207 of insns scheduled -- these would be postprocessed later. */
7209 schedule_on_fences (flist_t fences, int max_seqno,
7210 ilist_t **scheduled_insns_tailpp)
7212 flist_t old_fences = fences;
7214 if (sched_verbose >= 1)
7216 sel_print ("\nScheduling on fences: ");
7217 dump_flist (fences);
7221 scheduled_something_on_previous_fence = false;
7222 for (; fences; fences = FLIST_NEXT (fences))
7224 fence_t fence = NULL;
7227 bool first_p = true;
7229 /* Choose the next fence group to schedule.
7230 The fact that insn can be scheduled only once
7231 on the cycle is guaranteed by two properties:
7232 1. seqnos of parallel groups decrease with each iteration.
7233 2. If is_ineligible_successor () sees the larger seqno, it
7234 checks if candidate insn is_in_current_fence_p (). */
7235 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7237 fence_t f = FLIST_FENCE (fences2);
7239 if (!FENCE_PROCESSED_P (f))
7241 int i = INSN_SEQNO (FENCE_INSN (f));
7243 if (first_p || i > seqno)
7250 /* ??? Seqnos of different groups should be different. */
7251 gcc_assert (1 || i != seqno);
7257 /* As FENCE is nonnull, SEQNO is initialized. */
7258 seqno -= max_seqno + 1;
7259 fill_insns (fence, seqno, scheduled_insns_tailpp);
7260 FENCE_PROCESSED_P (fence) = true;
7263 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7264 don't need to keep bookkeeping-invalidated and target-unavailable
7266 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7267 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7270 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7272 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7274 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7276 /* The first element is already processed. */
7277 while ((fences = FLIST_NEXT (fences)))
7279 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7281 if (*min_seqno > seqno)
7283 else if (*max_seqno < seqno)
7288 /* Calculate new fences from FENCES. */
7290 calculate_new_fences (flist_t fences, int orig_max_seqno)
7292 flist_t old_fences = fences;
7293 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7295 flist_tail_init (new_fences);
7296 for (; fences; fences = FLIST_NEXT (fences))
7298 fence_t fence = FLIST_FENCE (fences);
7301 if (!FENCE_BNDS (fence))
7303 /* This fence doesn't have any successors. */
7304 if (!FENCE_SCHEDULED_P (fence))
7306 /* Nothing was scheduled on this fence. */
7309 insn = FENCE_INSN (fence);
7310 seqno = INSN_SEQNO (insn);
7311 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7313 if (sched_verbose >= 1)
7314 sel_print ("Fence %d[%d] has not changed\n",
7317 move_fence_to_fences (fences, new_fences);
7321 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7324 flist_clear (&old_fences);
7325 return FLIST_TAIL_HEAD (new_fences);
7328 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7329 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7330 the highest seqno used in a region. Return the updated highest seqno. */
7332 update_seqnos_and_stage (int min_seqno, int max_seqno,
7333 int highest_seqno_in_use,
7334 ilist_t *pscheduled_insns)
7340 /* Actually, new_hs is the seqno of the instruction, that was
7341 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7342 if (*pscheduled_insns)
7344 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7345 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7346 gcc_assert (new_hs > highest_seqno_in_use);
7349 new_hs = highest_seqno_in_use;
7351 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7353 gcc_assert (INSN_SEQNO (insn) < 0);
7354 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7355 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7357 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7358 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7359 require > 1GB of memory e.g. on limit-fnargs.c. */
7361 free_data_for_scheduled_insn (insn);
7364 ilist_clear (pscheduled_insns);
7370 /* The main driver for scheduling a region. This function is responsible
7371 for correct propagation of fences (i.e. scheduling points) and creating
7372 a group of parallel insns at each of them. It also supports
7373 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7376 sel_sched_region_2 (int orig_max_seqno)
7378 int highest_seqno_in_use = orig_max_seqno;
7380 stat_bookkeeping_copies = 0;
7381 stat_insns_needed_bookkeeping = 0;
7382 stat_renamed_scheduled = 0;
7383 stat_substitutions_total = 0;
7384 num_insns_scheduled = 0;
7388 int min_seqno, max_seqno;
7389 ilist_t scheduled_insns = NULL;
7390 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7392 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7393 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7394 fences = calculate_new_fences (fences, orig_max_seqno);
7395 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7396 highest_seqno_in_use,
7400 if (sched_verbose >= 1)
7401 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7402 "bookkeeping, %d insns renamed, %d insns substituted\n",
7403 stat_bookkeeping_copies,
7404 stat_insns_needed_bookkeeping,
7405 stat_renamed_scheduled,
7406 stat_substitutions_total);
7409 /* Schedule a region. When pipelining, search for possibly never scheduled
7410 bookkeeping code and schedule it. Reschedule pipelined code without
7411 pipelining after. */
7413 sel_sched_region_1 (void)
7415 int number_of_insns;
7418 /* Remove empty blocks that might be in the region from the beginning.
7419 We need to do save sched_max_luid before that, as it actually shows
7420 the number of insns in the region, and purge_empty_blocks can
7422 number_of_insns = sched_max_luid - 1;
7423 purge_empty_blocks ();
7425 orig_max_seqno = init_seqno (number_of_insns, NULL, NULL);
7426 gcc_assert (orig_max_seqno >= 1);
7428 /* When pipelining outer loops, create fences on the loop header,
7431 if (current_loop_nest)
7432 init_fences (BB_END (EBB_FIRST_BB (0)));
7434 init_fences (bb_note (EBB_FIRST_BB (0)));
7437 sel_sched_region_2 (orig_max_seqno);
7439 gcc_assert (fences == NULL);
7445 struct flist_tail_def _new_fences;
7446 flist_tail_t new_fences = &_new_fences;
7449 pipelining_p = false;
7450 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7451 bookkeeping_p = false;
7452 enable_schedule_as_rhs_p = false;
7454 /* Schedule newly created code, that has not been scheduled yet. */
7461 for (i = 0; i < current_nr_blocks; i++)
7463 basic_block bb = EBB_FIRST_BB (i);
7465 if (sel_bb_empty_p (bb))
7467 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7471 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7473 clear_outdated_rtx_info (bb);
7474 if (sel_insn_is_speculation_check (BB_END (bb))
7475 && JUMP_P (BB_END (bb)))
7476 bitmap_set_bit (blocks_to_reschedule,
7477 BRANCH_EDGE (bb)->dest->index);
7479 else if (INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7480 bitmap_set_bit (blocks_to_reschedule, bb->index);
7483 for (i = 0; i < current_nr_blocks; i++)
7485 bb = EBB_FIRST_BB (i);
7487 /* While pipelining outer loops, skip bundling for loop
7488 preheaders. Those will be rescheduled in the outer
7490 if (sel_is_loop_preheader_p (bb))
7492 clear_outdated_rtx_info (bb);
7496 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7498 flist_tail_init (new_fences);
7500 orig_max_seqno = init_seqno (0, blocks_to_reschedule, bb);
7502 /* Mark BB as head of the new ebb. */
7503 bitmap_set_bit (forced_ebb_heads, bb->index);
7505 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7507 gcc_assert (fences == NULL);
7509 init_fences (bb_note (bb));
7511 sel_sched_region_2 (orig_max_seqno);
7521 /* Schedule the RGN region. */
7523 sel_sched_region (int rgn)
7526 bool reset_sched_cycles_p;
7528 if (sel_region_init (rgn))
7531 if (sched_verbose >= 1)
7532 sel_print ("Scheduling region %d\n", rgn);
7534 schedule_p = (!sched_is_disabled_for_current_region_p ()
7535 && dbg_cnt (sel_sched_region_cnt));
7536 reset_sched_cycles_p = pipelining_p;
7538 sel_sched_region_1 ();
7540 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7541 reset_sched_cycles_p = true;
7543 sel_region_finish (reset_sched_cycles_p);
7546 /* Perform global init for the scheduler. */
7548 sel_global_init (void)
7550 calculate_dominance_info (CDI_DOMINATORS);
7551 alloc_sched_pools ();
7553 /* Setup the infos for sched_init. */
7554 sel_setup_sched_infos ();
7555 setup_sched_dump ();
7557 sched_rgn_init (false);
7561 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7563 can_issue_more = issue_rate;
7565 sched_extend_target ();
7566 sched_deps_init (true);
7567 setup_nop_and_exit_insns ();
7568 sel_extend_global_bb_info ();
7570 init_hard_regs_data ();
7573 /* Free the global data of the scheduler. */
7575 sel_global_finish (void)
7577 free_bb_note_pool ();
7579 sel_finish_global_bb_info ();
7581 free_regset_pool ();
7582 free_nop_and_exit_insns ();
7584 sched_rgn_finish ();
7585 sched_deps_finish ();
7589 sel_finish_pipelining ();
7591 free_sched_pools ();
7592 free_dominance_info (CDI_DOMINATORS);
7595 /* Return true when we need to skip selective scheduling. Used for debugging. */
7597 maybe_skip_selective_scheduling (void)
7599 return ! dbg_cnt (sel_sched_cnt);
7602 /* The entry point. */
7604 run_selective_scheduling (void)
7608 if (n_basic_blocks == NUM_FIXED_BLOCKS)
7613 for (rgn = 0; rgn < nr_regions; rgn++)
7614 sel_sched_region (rgn);
7616 sel_global_finish ();