1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
40 #include "tree-pass.h"
41 #include "sched-int.h"
45 #include "langhooks.h"
46 #include "rtlhooks-def.h"
49 #ifdef INSN_SCHEDULING
50 #include "sel-sched-ir.h"
51 #include "sel-sched-dump.h"
52 #include "sel-sched.h"
55 /* Implementation of selective scheduling approach.
56 The below implementation follows the original approach with the following
59 o the scheduler works after register allocation (but can be also tuned
61 o some instructions are not copied or register renamed;
62 o conditional jumps are not moved with code duplication;
63 o several jumps in one parallel group are not supported;
64 o when pipelining outer loops, code motion through inner loops
66 o control and data speculation are supported;
67 o some improvements for better compile time/performance were made.
72 A vinsn, or virtual insn, is an insn with additional data characterizing
73 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
74 Vinsns also act as smart pointers to save memory by reusing them in
75 different expressions. A vinsn is described by vinsn_t type.
77 An expression is a vinsn with additional data characterizing its properties
78 at some point in the control flow graph. The data may be its usefulness,
79 priority, speculative status, whether it was renamed/subsituted, etc.
80 An expression is described by expr_t type.
82 Availability set (av_set) is a set of expressions at a given control flow
83 point. It is represented as av_set_t. The expressions in av sets are kept
84 sorted in the terms of expr_greater_p function. It allows to truncate
85 the set while leaving the best expressions.
87 A fence is a point through which code motion is prohibited. On each step,
88 we gather a parallel group of insns at a fence. It is possible to have
89 multiple fences. A fence is represented via fence_t.
91 A boundary is the border between the fence group and the rest of the code.
92 Currently, we never have more than one boundary per fence, as we finalize
93 the fence group when a jump is scheduled. A boundary is represented
99 The scheduler finds regions to schedule, schedules each one, and finalizes.
100 The regions are formed starting from innermost loops, so that when the inner
101 loop is pipelined, its prologue can be scheduled together with yet unprocessed
102 outer loop. The rest of acyclic regions are found using extend_rgns:
103 the blocks that are not yet allocated to any regions are traversed in top-down
104 order, and a block is added to a region to which all its predecessors belong;
105 otherwise, the block starts its own region.
107 The main scheduling loop (sel_sched_region_2) consists of just
108 scheduling on each fence and updating fences. For each fence,
109 we fill a parallel group of insns (fill_insns) until some insns can be added.
110 First, we compute available exprs (av-set) at the boundary of the current
111 group. Second, we choose the best expression from it. If the stall is
112 required to schedule any of the expressions, we advance the current cycle
113 appropriately. So, the final group does not exactly correspond to a VLIW
114 word. Third, we move the chosen expression to the boundary (move_op)
115 and update the intermediate av sets and liveness sets. We quit fill_insns
116 when either no insns left for scheduling or we have scheduled enough insns
117 so we feel like advancing a scheduling point.
119 Computing available expressions
120 ===============================
122 The computation (compute_av_set) is a bottom-up traversal. At each insn,
123 we're moving the union of its successors' sets through it via
124 moveup_expr_set. The dependent expressions are removed. Local
125 transformations (substitution, speculation) are applied to move more
126 exprs. Then the expr corresponding to the current insn is added.
127 The result is saved on each basic block header.
129 When traversing the CFG, we're moving down for no more than max_ws insns.
130 Also, we do not move down to ineligible successors (is_ineligible_successor),
131 which include moving along a back-edge, moving to already scheduled code,
132 and moving to another fence. The first two restrictions are lifted during
133 pipelining, which allows us to move insns along a back-edge. We always have
134 an acyclic region for scheduling because we forbid motion through fences.
136 Choosing the best expression
137 ============================
139 We sort the final availability set via sel_rank_for_schedule, then we remove
140 expressions which are not yet ready (tick_check_p) or which dest registers
141 cannot be used. For some of them, we choose another register via
142 find_best_reg. To do this, we run find_used_regs to calculate the set of
143 registers which cannot be used. The find_used_regs function performs
144 a traversal of code motion paths for an expr. We consider for renaming
145 only registers which are from the same regclass as the original one and
146 using which does not interfere with any live ranges. Finally, we convert
147 the resulting set to the ready list format and use max_issue and reorder*
148 hooks similarly to the Haifa scheduler.
150 Scheduling the best expression
151 ==============================
153 We run the move_op routine to perform the same type of code motion paths
154 traversal as in find_used_regs. (These are working via the same driver,
155 code_motion_path_driver.) When moving down the CFG, we look for original
156 instruction that gave birth to a chosen expression. We undo
157 the transformations performed on an expression via the history saved in it.
158 When found, we remove the instruction or leave a reg-reg copy/speculation
159 check if needed. On a way up, we insert bookkeeping copies at each join
160 point. If a copy is not needed, it will be removed later during this
161 traversal. We update the saved av sets and liveness sets on the way up, too.
163 Finalizing the schedule
164 =======================
166 When pipelining, we reschedule the blocks from which insns were pipelined
167 to get a tighter schedule. On Itanium, we also perform bundling via
168 the same routine from ia64.c.
170 Dependence analysis changes
171 ===========================
173 We augmented the sched-deps.c with hooks that get called when a particular
174 dependence is found in a particular part of an insn. Using these hooks, we
175 can do several actions such as: determine whether an insn can be moved through
176 another (has_dependence_p, moveup_expr); find out whether an insn can be
177 scheduled on the current cycle (tick_check_p); find out registers that
178 are set/used/clobbered by an insn and find out all the strange stuff that
179 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
180 init_global_and_expr_for_insn).
182 Initialization changes
183 ======================
185 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
186 reused in all of the schedulers. We have split up the initialization of data
187 of such parts into different functions prefixed with scheduler type and
188 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
189 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
190 The same splitting is done with current_sched_info structure:
191 dependence-related parts are in sched_deps_info, common part is in
192 common_sched_info, and haifa/sel/etc part is in current_sched_info.
197 As we now have multiple-point scheduling, this would not work with backends
198 which save some of the scheduler state to use it in the target hooks.
199 For this purpose, we introduce a concept of target contexts, which
200 encapsulate such information. The backend should implement simple routines
201 of allocating/freeing/setting such a context. The scheduler calls these
202 as target hooks and handles the target context as an opaque pointer (similar
203 to the DFA state type, state_t).
208 As the correct data dependence graph is not supported during scheduling (which
209 is to be changed in mid-term), we cache as much of the dependence analysis
210 results as possible to avoid reanalyzing. This includes: bitmap caches on
211 each insn in stream of the region saying yes/no for a query with a pair of
212 UIDs; hashtables with the previously done transformations on each insn in
213 stream; a vector keeping a history of transformations on each expr.
215 Also, we try to minimize the dependence context used on each fence to check
216 whether the given expression is ready for scheduling by removing from it
217 insns that are definitely completed the execution. The results of
218 tick_check_p checks are also cached in a vector on each fence.
220 We keep a valid liveness set on each insn in a region to avoid the high
221 cost of recomputation on large basic blocks.
223 Finally, we try to minimize the number of needed updates to the availability
224 sets. The updates happen in two cases: when fill_insns terminates,
225 we advance all fences and increase the stage number to show that the region
226 has changed and the sets are to be recomputed; and when the next iteration
227 of a loop in fill_insns happens (but this one reuses the saved av sets
228 on bb headers.) Thus, we try to break the fill_insns loop only when
229 "significant" number of insns from the current scheduling window was
230 scheduled. This should be made a target param.
233 TODO: correctly support the data dependence graph at all stages and get rid
234 of all caches. This should speed up the scheduler.
235 TODO: implement moving cond jumps with bookkeeping copies on both targets.
236 TODO: tune the scheduler before RA so it does not create too much pseudos.
240 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
241 selective scheduling and software pipelining.
242 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
244 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
245 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
246 for GCC. In Proceedings of GCC Developers' Summit 2006.
248 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
249 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
250 http://rogue.colorado.edu/EPIC7/.
254 /* True when pipelining is enabled. */
257 /* True if bookkeeping is enabled. */
260 /* Maximum number of insns that are eligible for renaming. */
261 int max_insns_to_rename;
264 /* Definitions of local types and macros. */
266 /* Represents possible outcomes of moving an expression through an insn. */
267 enum MOVEUP_EXPR_CODE
269 /* The expression is not changed. */
272 /* Not changed, but requires a new destination register. */
275 /* Cannot be moved. */
278 /* Changed (substituted or speculated). */
282 /* The container to be passed into rtx search & replace functions. */
283 struct rtx_search_arg
285 /* What we are searching for. */
288 /* The occurence counter. */
292 typedef struct rtx_search_arg *rtx_search_arg_p;
294 /* This struct contains precomputed hard reg sets that are needed when
295 computing registers available for renaming. */
296 struct hard_regs_data
298 /* For every mode, this stores registers available for use with
300 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
302 /* True when regs_for_mode[mode] is initialized. */
303 bool regs_for_mode_ok[NUM_MACHINE_MODES];
305 /* For every register, it has regs that are ok to rename into it.
306 The register in question is always set. If not, this means
307 that the whole set is not computed yet. */
308 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
310 /* For every mode, this stores registers not available due to
312 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
314 /* All registers that are used or call used. */
315 HARD_REG_SET regs_ever_used;
318 /* Stack registers. */
319 HARD_REG_SET stack_regs;
323 /* Holds the results of computation of available for renaming and
324 unavailable hard registers. */
327 /* These are unavailable due to calls crossing, globalness, etc. */
328 HARD_REG_SET unavailable_hard_regs;
330 /* These are *available* for renaming. */
331 HARD_REG_SET available_for_renaming;
333 /* Whether this code motion path crosses a call. */
337 /* A global structure that contains the needed information about harg
339 static struct hard_regs_data sel_hrd;
342 /* This structure holds local data used in code_motion_path_driver hooks on
343 the same or adjacent levels of recursion. Here we keep those parameters
344 that are not used in code_motion_path_driver routine itself, but only in
345 its hooks. Moreover, all parameters that can be modified in hooks are
346 in this structure, so all other parameters passed explicitly to hooks are
348 struct cmpd_local_params
350 /* Local params used in move_op_* functions. */
352 /* Edges for bookkeeping generation. */
355 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
356 expr_t c_expr_merged, c_expr_local;
358 /* Local params used in fur_* functions. */
359 /* Copy of the ORIGINAL_INSN list, stores the original insns already
360 found before entering the current level of code_motion_path_driver. */
361 def_list_t old_original_insns;
363 /* Local params used in move_op_* functions. */
364 /* True when we have removed last insn in the block which was
365 also a boundary. Do not update anything or create bookkeeping copies. */
366 BOOL_BITFIELD removed_last_insn : 1;
369 /* Stores the static parameters for move_op_* calls. */
370 struct moveop_static_params
372 /* Destination register. */
375 /* Current C_EXPR. */
378 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
379 they are to be removed. */
382 #ifdef ENABLE_CHECKING
383 /* This is initialized to the insn on which the driver stopped its traversal. */
387 /* True if we scheduled an insn with different register. */
391 /* Stores the static parameters for fur_* calls. */
392 struct fur_static_params
394 /* Set of registers unavailable on the code motion path. */
397 /* Pointer to the list of original insns definitions. */
398 def_list_t *original_insns;
400 /* True if a code motion path contains a CALL insn. */
404 typedef struct fur_static_params *fur_static_params_p;
405 typedef struct cmpd_local_params *cmpd_local_params_p;
406 typedef struct moveop_static_params *moveop_static_params_p;
408 /* Set of hooks and parameters that determine behaviour specific to
409 move_op or find_used_regs functions. */
410 struct code_motion_path_driver_info_def
412 /* Called on enter to the basic block. */
413 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
415 /* Called when original expr is found. */
416 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
418 /* Called while descending current basic block if current insn is not
419 the original EXPR we're searching for. */
420 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
422 /* Function to merge C_EXPRes from different successors. */
423 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
425 /* Function to finalize merge from different successors and possibly
426 deallocate temporary data structures used for merging. */
427 void (*after_merge_succs) (cmpd_local_params_p, void *);
429 /* Called on the backward stage of recursion to do moveup_expr.
430 Used only with move_op_*. */
431 void (*ascend) (insn_t, void *);
433 /* Called on the ascending pass, before returning from the current basic
434 block or from the whole traversal. */
435 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
437 /* When processing successors in move_op we need only descend into
438 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
441 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
442 const char *routine_name;
445 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
447 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
449 /* Set of hooks for performing move_op and find_used_regs routines with
450 code_motion_path_driver. */
451 extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
453 /* True if/when we want to emulate Haifa scheduler in the common code.
454 This is used in sched_rgn_local_init and in various places in
456 int sched_emulate_haifa_p;
458 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
459 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
460 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
461 scheduling window. */
464 /* Current fences. */
467 /* True when separable insns should be scheduled as RHSes. */
468 static bool enable_schedule_as_rhs_p;
470 /* Used in verify_target_availability to assert that target reg is reported
471 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
472 we haven't scheduled anything on the previous fence.
473 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
474 have more conservative value than the one returned by the
475 find_used_regs, thus we shouldn't assert that these values are equal. */
476 static bool scheduled_something_on_previous_fence;
478 /* All newly emitted insns will have their uids greater than this value. */
479 static int first_emitted_uid;
481 /* Set of basic blocks that are forced to start new ebbs. This is a subset
482 of all the ebb heads. */
483 static bitmap_head _forced_ebb_heads;
484 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
486 /* Blocks that need to be rescheduled after pipelining. */
487 bitmap blocks_to_reschedule = NULL;
489 /* True when the first lv set should be ignored when updating liveness. */
490 static bool ignore_first = false;
492 /* Number of insns max_issue has initialized data structures for. */
493 static int max_issue_size = 0;
495 /* Whether we can issue more instructions. */
496 static int can_issue_more;
498 /* Maximum software lookahead window size, reduced when rescheduling after
502 /* Number of insns scheduled in current region. */
503 static int num_insns_scheduled;
505 /* A vector of expressions is used to be able to sort them. */
507 DEF_VEC_ALLOC_P(expr_t,heap);
508 static VEC(expr_t, heap) *vec_av_set = NULL;
510 /* A vector of vinsns is used to hold temporary lists of vinsns. */
512 DEF_VEC_ALLOC_P(vinsn_t,heap);
513 typedef VEC(vinsn_t, heap) *vinsn_vec_t;
515 /* This vector has the exprs which may still present in av_sets, but actually
516 can't be moved up due to bookkeeping created during code motion to another
517 fence. See comment near the call to update_and_record_unavailable_insns
518 for the detailed explanations. */
519 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = NULL;
521 /* This vector has vinsns which are scheduled with renaming on the first fence
522 and then seen on the second. For expressions with such vinsns, target
523 availability information may be wrong. */
524 static vinsn_vec_t vec_target_unavailable_vinsns = NULL;
526 /* Vector to store temporary nops inserted in move_op to prevent removal
529 DEF_VEC_ALLOC_P(insn_t,heap);
530 static VEC(insn_t, heap) *vec_temp_moveop_nops = NULL;
532 /* These bitmaps record original instructions scheduled on the current
533 iteration and bookkeeping copies created by them. */
534 static bitmap current_originators = NULL;
535 static bitmap current_copies = NULL;
537 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
538 visit them afterwards. */
539 static bitmap code_motion_visited_blocks = NULL;
541 /* Variables to accumulate different statistics. */
543 /* The number of bookkeeping copies created. */
544 static int stat_bookkeeping_copies;
546 /* The number of insns that required bookkeeiping for their scheduling. */
547 static int stat_insns_needed_bookkeeping;
549 /* The number of insns that got renamed. */
550 static int stat_renamed_scheduled;
552 /* The number of substitutions made during scheduling. */
553 static int stat_substitutions_total;
556 /* Forward declarations of static functions. */
557 static bool rtx_ok_for_substitution_p (rtx, rtx);
558 static int sel_rank_for_schedule (const void *, const void *);
559 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
560 static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax);
562 static rtx get_dest_from_orig_ops (av_set_t);
563 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
564 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
566 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
567 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
568 cmpd_local_params_p, void *);
569 static void sel_sched_region_1 (void);
570 static void sel_sched_region_2 (int);
571 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
573 static void debug_state (state_t);
576 /* Functions that work with fences. */
578 /* Advance one cycle on FENCE. */
580 advance_one_cycle (fence_t fence)
586 advance_state (FENCE_STATE (fence));
587 cycle = ++FENCE_CYCLE (fence);
588 FENCE_ISSUED_INSNS (fence) = 0;
589 FENCE_STARTS_CYCLE_P (fence) = 1;
590 can_issue_more = issue_rate;
592 for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); )
594 if (INSN_READY_CYCLE (insn) < cycle)
596 remove_from_deps (FENCE_DC (fence), insn);
597 VEC_unordered_remove (rtx, FENCE_EXECUTING_INSNS (fence), i);
602 if (sched_verbose >= 2)
604 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
605 debug_state (FENCE_STATE (fence));
609 /* Returns true when SUCC in a fallthru bb of INSN, possibly
610 skipping empty basic blocks. */
612 in_fallthru_bb_p (rtx insn, rtx succ)
614 basic_block bb = BLOCK_FOR_INSN (insn);
616 if (bb == BLOCK_FOR_INSN (succ))
619 if (find_fallthru_edge (bb))
620 bb = find_fallthru_edge (bb)->dest;
624 while (sel_bb_empty_p (bb))
627 return bb == BLOCK_FOR_INSN (succ);
630 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
631 When a successor will continue a ebb, transfer all parameters of a fence
632 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
633 of scheduling helping to distinguish between the old and the new code. */
635 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
638 bool was_here_p = false;
639 insn_t insn = NULL_RTX;
643 fence_t fence = FLIST_FENCE (old_fences);
646 /* Get the only element of FENCE_BNDS (fence). */
647 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
649 gcc_assert (!was_here_p);
652 gcc_assert (was_here_p && insn != NULL_RTX);
654 /* When in the "middle" of the block, just move this fence
656 bb = BLOCK_FOR_INSN (insn);
657 if (! sel_bb_end_p (insn)
658 || (single_succ_p (bb)
659 && single_pred_p (single_succ (bb))))
663 succ = (sel_bb_end_p (insn)
664 ? sel_bb_head (single_succ (bb))
667 if (INSN_SEQNO (succ) > 0
668 && INSN_SEQNO (succ) <= orig_max_seqno
669 && INSN_SCHED_TIMES (succ) <= 0)
671 FENCE_INSN (fence) = succ;
672 move_fence_to_fences (old_fences, new_fences);
674 if (sched_verbose >= 1)
675 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
676 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
681 /* Otherwise copy fence's structures to (possibly) multiple successors. */
682 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
684 int seqno = INSN_SEQNO (succ);
686 if (0 < seqno && seqno <= orig_max_seqno
687 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
689 bool b = (in_same_ebb_p (insn, succ)
690 || in_fallthru_bb_p (insn, succ));
692 if (sched_verbose >= 1)
693 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
694 INSN_UID (insn), INSN_UID (succ),
695 BLOCK_NUM (succ), b ? "continue" : "reset");
698 add_dirty_fence_to_fences (new_fences, succ, fence);
701 /* Mark block of the SUCC as head of the new ebb. */
702 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
703 add_clean_fence_to_fences (new_fences, succ, fence);
710 /* Functions to support substitution. */
712 /* Returns whether INSN with dependence status DS is eligible for
713 substitution, i.e. it's a copy operation x := y, and RHS that is
714 moved up through this insn should be substituted. */
716 can_substitute_through_p (insn_t insn, ds_t ds)
718 /* We can substitute only true dependencies. */
719 if ((ds & DEP_OUTPUT)
722 || ! INSN_LHS (insn))
725 /* Now we just need to make sure the INSN_RHS consists of only one
727 if (REG_P (INSN_LHS (insn))
728 && REG_P (INSN_RHS (insn)))
733 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
734 source (if INSN is eligible for substitution). Returns TRUE if
735 substitution was actually performed, FALSE otherwise. Substitution might
736 be not performed because it's either EXPR' vinsn doesn't contain INSN's
737 destination or the resulting insn is invalid for the target machine.
738 When UNDO is true, perform unsubstitution instead (the difference is in
739 the part of rtx on which validate_replace_rtx is called). */
741 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
745 vinsn_t *vi = &EXPR_VINSN (expr);
746 bool has_rhs = VINSN_RHS (*vi) != NULL;
749 /* Do not try to replace in SET_DEST. Although we'll choose new
750 register for the RHS, we don't want to change RHS' original reg.
751 If the insn is not SET, we may still be able to substitute something
752 in it, and if we're here (don't have deps), it doesn't write INSN's
756 : &PATTERN (VINSN_INSN_RTX (*vi)));
757 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
759 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
760 if (rtx_ok_for_substitution_p (old, *where))
765 /* We should copy these rtxes before substitution. */
766 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
767 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
769 /* Where we'll replace.
770 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
771 used instead of SET_SRC. */
772 where_replace = (has_rhs
773 ? &SET_SRC (PATTERN (new_insn))
774 : &PATTERN (new_insn));
777 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
780 /* ??? Actually, constrain_operands result depends upon choice of
781 destination register. E.g. if we allow single register to be an rhs,
782 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
783 in invalid insn dx=dx, so we'll loose this rhs here.
784 Just can't come up with significant testcase for this, so just
785 leaving it for now. */
788 change_vinsn_in_expr (expr,
789 create_vinsn_from_insn_rtx (new_insn, false));
791 /* Do not allow clobbering the address register of speculative
793 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
794 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr)),
795 expr_dest_regno (expr)))
796 EXPR_TARGET_AVAILABLE (expr) = false;
807 /* Helper function for count_occurences_equiv. */
809 count_occurrences_1 (rtx *cur_rtx, void *arg)
811 rtx_search_arg_p p = (rtx_search_arg_p) arg;
813 /* The last param FOR_GCSE is true, because otherwise it performs excessive
817 for the last insn it presumes r33 equivalent to r8, so it changes it to
818 r33. Actually, there's no change, but it spoils debugging. */
819 if (exp_equiv_p (*cur_rtx, p->x, 0, true))
821 /* Bail out if we occupy more than one register. */
823 && HARD_REGISTER_P (*cur_rtx)
824 && hard_regno_nregs[REGNO(*cur_rtx)][GET_MODE (*cur_rtx)] > 1)
832 /* Do not traverse subexprs. */
836 if (GET_CODE (*cur_rtx) == SUBREG
838 && REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x))
840 /* ??? Do not support substituting regs inside subregs. In that case,
841 simplify_subreg will be called by validate_replace_rtx, and
842 unsubstitution will fail later. */
847 /* Continue search. */
851 /* Return the number of places WHAT appears within WHERE.
852 Bail out when we found a reference occupying several hard registers. */
854 count_occurrences_equiv (rtx what, rtx where)
856 struct rtx_search_arg arg;
861 for_each_rtx (&where, &count_occurrences_1, (void *) &arg);
866 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
868 rtx_ok_for_substitution_p (rtx what, rtx where)
870 return (count_occurrences_equiv (what, where) > 0);
874 /* Functions to support register renaming. */
876 /* Substitute VI's set source with REGNO. Returns newly created pattern
877 that has REGNO as its source. */
879 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
885 lhs_rtx = copy_rtx (VINSN_LHS (vi));
887 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
888 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
893 /* Returns whether INSN's src can be replaced with register number
894 NEW_SRC_REG. E.g. the following insn is valid for i386:
896 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
897 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
898 (reg:SI 0 ax [orig:770 c1 ] [770]))
899 (const_int 288 [0x120])) [0 str S1 A8])
900 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
903 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
904 because of operand constraints:
906 (define_insn "*movqi_1"
907 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
908 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
911 So do constrain_operands here, before choosing NEW_SRC_REG as best
915 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
917 vinsn_t vi = INSN_VINSN (insn);
918 enum machine_mode mode;
922 gcc_assert (VINSN_SEPARABLE_P (vi));
924 get_dest_and_mode (insn, &dst_loc, &mode);
925 gcc_assert (mode == GET_MODE (new_src_reg));
927 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
930 /* See whether SET_SRC can be replaced with this register. */
931 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
932 res = verify_changes (0);
938 /* Returns whether INSN still be valid after replacing it's DEST with
941 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
943 vinsn_t vi = INSN_VINSN (insn);
946 /* We should deal here only with separable insns. */
947 gcc_assert (VINSN_SEPARABLE_P (vi));
948 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
950 /* See whether SET_DEST can be replaced with this register. */
951 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
952 res = verify_changes (0);
958 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
960 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
966 rhs_rtx = copy_rtx (VINSN_RHS (vi));
968 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
969 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
974 /* Substitute lhs in the given expression EXPR for the register with number
975 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
977 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
982 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
983 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
985 change_vinsn_in_expr (expr, vinsn);
986 EXPR_WAS_RENAMED (expr) = 1;
987 EXPR_TARGET_AVAILABLE (expr) = 1;
990 /* Returns whether VI writes either one of the USED_REGS registers or,
991 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
993 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
994 HARD_REG_SET unavailable_hard_regs)
997 reg_set_iterator rsi;
999 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
1001 if (REGNO_REG_SET_P (used_regs, regno))
1003 if (HARD_REGISTER_NUM_P (regno)
1004 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1008 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
1010 if (REGNO_REG_SET_P (used_regs, regno))
1012 if (HARD_REGISTER_NUM_P (regno)
1013 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1020 /* Returns register class of the output register in INSN.
1021 Returns NO_REGS for call insns because some targets have constraints on
1022 destination register of a call insn.
1024 Code adopted from regrename.c::build_def_use. */
1025 static enum reg_class
1026 get_reg_class (rtx insn)
1030 extract_insn (insn);
1031 if (! constrain_operands (1))
1032 fatal_insn_not_found (insn);
1033 preprocess_constraints ();
1034 alt = which_alternative;
1035 n_ops = recog_data.n_operands;
1037 for (i = 0; i < n_ops; ++i)
1039 int matches = recog_op_alt[i][alt].matches;
1041 recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;
1044 if (asm_noperands (PATTERN (insn)) > 0)
1046 for (i = 0; i < n_ops; i++)
1047 if (recog_data.operand_type[i] == OP_OUT)
1049 rtx *loc = recog_data.operand_loc[i];
1051 enum reg_class cl = recog_op_alt[i][alt].cl;
1054 && REGNO (op) == ORIGINAL_REGNO (op))
1060 else if (!CALL_P (insn))
1062 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1064 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1065 enum reg_class cl = recog_op_alt[opn][alt].cl;
1067 if (recog_data.operand_type[opn] == OP_OUT ||
1068 recog_data.operand_type[opn] == OP_INOUT)
1074 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1075 may result in returning NO_REGS, cause flags is written implicitly through
1076 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1080 #ifdef HARD_REGNO_RENAME_OK
1081 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1083 init_hard_regno_rename (int regno)
1087 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1089 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1091 /* We are not interested in renaming in other regs. */
1092 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1095 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1096 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1101 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1104 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1106 #ifdef HARD_REGNO_RENAME_OK
1107 /* Check whether this is all calculated. */
1108 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1109 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1111 init_hard_regno_rename (from);
1113 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1119 /* Calculate set of registers that are capable of holding MODE. */
1121 init_regs_for_mode (enum machine_mode mode)
1125 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1126 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1128 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1130 int nregs = hard_regno_nregs[cur_reg][mode];
1133 for (i = nregs - 1; i >= 0; --i)
1134 if (fixed_regs[cur_reg + i]
1135 || global_regs[cur_reg + i]
1136 /* Can't use regs which aren't saved by
1138 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1139 #ifdef LEAF_REGISTERS
1140 /* We can't use a non-leaf register if we're in a
1142 || (current_function_is_leaf
1143 && !LEAF_REGISTERS[cur_reg + i])
1151 /* See whether it accepts all modes that occur in
1153 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1156 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1157 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1160 /* If the CUR_REG passed all the checks above,
1162 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1165 sel_hrd.regs_for_mode_ok[mode] = true;
1168 /* Init all register sets gathered in HRD. */
1170 init_hard_regs_data (void)
1175 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1176 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1177 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1178 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1180 /* Initialize registers that are valid based on mode when this is
1182 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1183 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1185 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1186 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1187 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1190 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1192 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1193 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1197 /* Mark hardware regs in REG_RENAME_P that are not suitable
1198 for renaming rhs in INSN due to hardware restrictions (register class,
1199 modes compatibility etc). This doesn't affect original insn's dest reg,
1200 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1201 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1202 Registers that are in used_regs are always marked in
1203 unavailable_hard_regs as well. */
1206 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1207 regset used_regs ATTRIBUTE_UNUSED)
1209 enum machine_mode mode;
1210 enum reg_class cl = NO_REGS;
1212 unsigned cur_reg, regno;
1213 hard_reg_set_iterator hrsi;
1215 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1216 gcc_assert (reg_rename_p);
1218 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1220 /* We have decided not to rename 'mem = something;' insns, as 'something'
1221 is usually a register. */
1222 if (!REG_P (orig_dest))
1225 regno = REGNO (orig_dest);
1227 /* If before reload, don't try to work with pseudos. */
1228 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1231 mode = GET_MODE (orig_dest);
1233 /* Stop when mode is not supported for renaming. Also can't proceed
1234 if the original register is one of the fixed_regs, global_regs or
1236 if (fixed_regs[regno]
1237 || global_regs[regno]
1238 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1239 || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
1241 || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
1245 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1247 /* Give a chance for original register, if it isn't in used_regs. */
1248 if (!def->crosses_call)
1249 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1254 /* If something allocated on stack in this function, mark frame pointer
1255 register unavailable, considering also modes.
1256 FIXME: it is enough to do this once per all original defs. */
1257 if (frame_pointer_needed)
1261 for (i = hard_regno_nregs[FRAME_POINTER_REGNUM][Pmode]; i--;)
1262 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1263 FRAME_POINTER_REGNUM + i);
1265 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1266 for (i = hard_regno_nregs[HARD_FRAME_POINTER_REGNUM][Pmode]; i--;)
1267 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1268 HARD_FRAME_POINTER_REGNUM + i);
1273 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1274 is equivalent to as if all stack regs were in this set.
1275 I.e. no stack register can be renamed, and even if it's an original
1276 register here we make sure it won't be lifted over it's previous def
1277 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1278 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1279 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1280 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1281 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1282 sel_hrd.stack_regs);
1285 /* If there's a call on this path, make regs from call_used_reg_set
1287 if (def->crosses_call)
1288 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1291 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1292 but not register classes. */
1293 if (!reload_completed)
1296 /* Leave regs as 'available' only from the current
1298 cl = get_reg_class (def->orig_insn);
1299 gcc_assert (cl != NO_REGS);
1300 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1301 reg_class_contents[cl]);
1303 /* Leave only registers available for this mode. */
1304 if (!sel_hrd.regs_for_mode_ok[mode])
1305 init_regs_for_mode (mode);
1306 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1307 sel_hrd.regs_for_mode[mode]);
1309 /* Exclude registers that are partially call clobbered. */
1310 if (def->crosses_call
1311 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1312 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1313 sel_hrd.regs_for_call_clobbered[mode]);
1315 /* Leave only those that are ok to rename. */
1316 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1322 nregs = hard_regno_nregs[cur_reg][mode];
1323 gcc_assert (nregs > 0);
1325 for (i = nregs - 1; i >= 0; --i)
1326 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1330 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1334 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1335 reg_rename_p->unavailable_hard_regs);
1337 /* Regno is always ok from the renaming part of view, but it really
1338 could be in *unavailable_hard_regs already, so set it here instead
1340 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1343 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1344 best register more recently than REG2. */
1345 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1347 /* Indicates the number of times renaming happened before the current one. */
1348 static int reg_rename_this_tick;
1350 /* Choose the register among free, that is suitable for storing
1353 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1354 originally appears. There could be multiple original operations
1355 for single rhs since we moving it up and merging along different
1358 Some code is adapted from regrename.c (regrename_optimize).
1359 If original register is available, function returns it.
1360 Otherwise it performs the checks, so the new register should
1361 comply with the following:
1362 - it should not violate any live ranges (such registers are in
1363 REG_RENAME_P->available_for_renaming set);
1364 - it should not be in the HARD_REGS_USED regset;
1365 - it should be in the class compatible with original uses;
1366 - it should not be clobbered through reference with different mode;
1367 - if we're in the leaf function, then the new register should
1368 not be in the LEAF_REGISTERS;
1371 If several registers meet the conditions, the register with smallest
1372 tick is returned to achieve more even register allocation.
1374 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1376 If no register satisfies the above conditions, NULL_RTX is returned. */
1378 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1379 struct reg_rename *reg_rename_p,
1380 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1384 enum machine_mode mode = VOIDmode;
1385 unsigned regno, i, n;
1386 hard_reg_set_iterator hrsi;
1387 def_list_iterator di;
1390 /* If original register is available, return it. */
1391 *is_orig_reg_p_ptr = true;
1393 FOR_EACH_DEF (def, di, original_insns)
1395 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1397 gcc_assert (REG_P (orig_dest));
1399 /* Check that all original operations have the same mode.
1400 This is done for the next loop; if we'd return from this
1401 loop, we'd check only part of them, but in this case
1402 it doesn't matter. */
1403 if (mode == VOIDmode)
1404 mode = GET_MODE (orig_dest);
1405 gcc_assert (mode == GET_MODE (orig_dest));
1407 regno = REGNO (orig_dest);
1408 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1409 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1412 /* All hard registers are available. */
1415 gcc_assert (mode != VOIDmode);
1417 /* Hard registers should not be shared. */
1418 return gen_rtx_REG (mode, regno);
1422 *is_orig_reg_p_ptr = false;
1425 /* Among all available regs choose the register that was
1426 allocated earliest. */
1427 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1429 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1431 /* All hard registers are available. */
1432 if (best_new_reg < 0
1433 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1435 best_new_reg = cur_reg;
1437 /* Return immediately when we know there's no better reg. */
1438 if (! reg_rename_tick[best_new_reg])
1443 if (best_new_reg >= 0)
1445 /* Use the check from the above loop. */
1446 gcc_assert (mode != VOIDmode);
1447 return gen_rtx_REG (mode, best_new_reg);
1453 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1454 assumptions about available registers in the function. */
1456 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1457 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1459 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1460 original_insns, is_orig_reg_p_ptr);
1462 gcc_assert (best_reg == NULL_RTX
1463 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1468 /* Choose the pseudo register for storing rhs value. As this is supposed
1469 to work before reload, we return either the original register or make
1470 the new one. The parameters are the same that in choose_nest_reg_1
1471 functions, except that USED_REGS may contain pseudos.
1472 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1474 TODO: take into account register pressure while doing this. Up to this
1475 moment, this function would never return NULL for pseudos, but we should
1476 not rely on this. */
1478 choose_best_pseudo_reg (regset used_regs,
1479 struct reg_rename *reg_rename_p,
1480 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1482 def_list_iterator i;
1484 enum machine_mode mode = VOIDmode;
1485 bool bad_hard_regs = false;
1487 /* We should not use this after reload. */
1488 gcc_assert (!reload_completed);
1490 /* If original register is available, return it. */
1491 *is_orig_reg_p_ptr = true;
1493 FOR_EACH_DEF (def, i, original_insns)
1495 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1498 gcc_assert (REG_P (dest));
1500 /* Check that all original operations have the same mode. */
1501 if (mode == VOIDmode)
1502 mode = GET_MODE (dest);
1504 gcc_assert (mode == GET_MODE (dest));
1505 orig_regno = REGNO (dest);
1507 if (!REGNO_REG_SET_P (used_regs, orig_regno))
1509 if (orig_regno < FIRST_PSEUDO_REGISTER)
1511 gcc_assert (df_regs_ever_live_p (orig_regno));
1513 /* For hard registers, we have to check hardware imposed
1514 limitations (frame/stack registers, calls crossed). */
1515 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1518 /* Don't let register cross a call if it doesn't already
1519 cross one. This condition is written in accordance with
1520 that in sched-deps.c sched_analyze_reg(). */
1521 if (!reg_rename_p->crosses_call
1522 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1523 return gen_rtx_REG (mode, orig_regno);
1526 bad_hard_regs = true;
1533 *is_orig_reg_p_ptr = false;
1535 /* We had some original hard registers that couldn't be used.
1536 Those were likely special. Don't try to create a pseudo. */
1540 /* We haven't found a register from original operations. Get a new one.
1541 FIXME: control register pressure somehow. */
1543 rtx new_reg = gen_reg_rtx (mode);
1545 gcc_assert (mode != VOIDmode);
1547 max_regno = max_reg_num ();
1548 maybe_extend_reg_info_p ();
1549 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1555 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1556 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1558 verify_target_availability (expr_t expr, regset used_regs,
1559 struct reg_rename *reg_rename_p)
1561 unsigned n, i, regno;
1562 enum machine_mode mode;
1563 bool target_available, live_available, hard_available;
1565 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1568 regno = expr_dest_regno (expr);
1569 mode = GET_MODE (EXPR_LHS (expr));
1570 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1571 n = reload_completed ? hard_regno_nregs[regno][mode] : 1;
1573 live_available = hard_available = true;
1574 for (i = 0; i < n; i++)
1576 if (bitmap_bit_p (used_regs, regno + i))
1577 live_available = false;
1578 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1579 hard_available = false;
1582 /* When target is not available, it may be due to hard register
1583 restrictions, e.g. crosses calls, so we check hard_available too. */
1584 if (target_available)
1585 gcc_assert (live_available);
1587 /* Check only if we haven't scheduled something on the previous fence,
1588 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1589 and having more than one fence, we may end having targ_un in a block
1590 in which successors target register is actually available.
1592 The last condition handles the case when a dependence from a call insn
1593 was created in sched-deps.c for insns with destination registers that
1594 never crossed a call before, but do cross one after our code motion.
1596 FIXME: in the latter case, we just uselessly called find_used_regs,
1597 because we can't move this expression with any other register
1599 gcc_assert (scheduled_something_on_previous_fence || !live_available
1601 || (!reload_completed && reg_rename_p->crosses_call
1602 && REG_N_CALLS_CROSSED (regno) == 0));
1605 /* Collect unavailable registers due to liveness for EXPR from BNDS
1606 into USED_REGS. Save additional information about available
1607 registers and unavailable due to hardware restriction registers
1608 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1611 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1612 struct reg_rename *reg_rename_p,
1613 def_list_t *original_insns)
1615 for (; bnds; bnds = BLIST_NEXT (bnds))
1618 av_set_t orig_ops = NULL;
1619 bnd_t bnd = BLIST_BND (bnds);
1621 /* If the chosen best expr doesn't belong to current boundary,
1623 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1626 /* Put in ORIG_OPS all exprs from this boundary that became
1628 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1630 /* Compute used regs and OR it into the USED_REGS. */
1631 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1632 reg_rename_p, original_insns);
1634 /* FIXME: the assert is true until we'd have several boundaries. */
1636 av_set_clear (&orig_ops);
1640 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1641 If BEST_REG is valid, replace LHS of EXPR with it. */
1643 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1645 /* Try whether we'll be able to generate the insn
1646 'dest := best_reg' at the place of the original operation. */
1647 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1649 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1651 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1653 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1654 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1655 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1659 /* Make sure that EXPR has the right destination
1661 if (expr_dest_regno (expr) != REGNO (best_reg))
1662 replace_dest_with_reg_in_expr (expr, best_reg);
1664 EXPR_TARGET_AVAILABLE (expr) = 1;
1669 /* Select and assign best register to EXPR searching from BNDS.
1670 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1671 Return FALSE if no register can be chosen, which could happen when:
1672 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1673 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1674 that are used on the moving path. */
1676 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1678 static struct reg_rename reg_rename_data;
1681 def_list_t original_insns = NULL;
1684 *is_orig_reg_p = false;
1686 /* Don't bother to do anything if this insn doesn't set any registers. */
1687 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1688 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1691 used_regs = get_clear_regset_from_pool ();
1692 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1694 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data,
1697 #ifdef ENABLE_CHECKING
1698 /* If after reload, make sure we're working with hard regs here. */
1699 if (reload_completed)
1701 reg_set_iterator rsi;
1704 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1709 if (EXPR_SEPARABLE_P (expr))
1711 rtx best_reg = NULL_RTX;
1712 /* Check that we have computed availability of a target register
1714 verify_target_availability (expr, used_regs, ®_rename_data);
1716 /* Turn everything in hard regs after reload. */
1717 if (reload_completed)
1719 HARD_REG_SET hard_regs_used;
1720 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1722 /* Join hard registers unavailable due to register class
1723 restrictions and live range intersection. */
1724 IOR_HARD_REG_SET (hard_regs_used,
1725 reg_rename_data.unavailable_hard_regs);
1727 best_reg = choose_best_reg (hard_regs_used, ®_rename_data,
1728 original_insns, is_orig_reg_p);
1731 best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data,
1732 original_insns, is_orig_reg_p);
1736 else if (*is_orig_reg_p)
1738 /* In case of unification BEST_REG may be different from EXPR's LHS
1739 when EXPR's LHS is unavailable, and there is another LHS among
1741 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1745 /* Forbid renaming of low-cost insns. */
1746 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1749 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1754 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1755 any of the HARD_REGS_USED set. */
1756 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1757 reg_rename_data.unavailable_hard_regs))
1760 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1765 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1769 ilist_clear (&original_insns);
1770 return_regset_to_pool (used_regs);
1776 /* Return true if dependence described by DS can be overcomed. */
1778 can_speculate_dep_p (ds_t ds)
1780 if (spec_info == NULL)
1783 /* Leave only speculative data. */
1790 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1791 that we can overcome. */
1792 ds_t spec_mask = spec_info->mask;
1794 if ((ds & spec_mask) != ds)
1798 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1804 /* Get a speculation check instruction.
1805 C_EXPR is a speculative expression,
1806 CHECK_DS describes speculations that should be checked,
1807 ORIG_INSN is the original non-speculative insn in the stream. */
1809 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1814 basic_block recovery_block;
1817 /* Create a recovery block if target is going to emit branchy check, or if
1818 ORIG_INSN was speculative already. */
1819 if (targetm.sched.needs_block_p (check_ds)
1820 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1822 recovery_block = sel_create_recovery_block (orig_insn);
1823 label = BB_HEAD (recovery_block);
1827 recovery_block = NULL;
1831 /* Get pattern of the check. */
1832 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1835 gcc_assert (check_pattern != NULL);
1838 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1840 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1841 INSN_SEQNO (orig_insn), orig_insn);
1843 /* Make check to be non-speculative. */
1844 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1845 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1847 /* Decrease priority of check by difference of load/check instruction
1849 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1850 - sel_vinsn_cost (INSN_VINSN (insn)));
1852 /* Emit copy of original insn (though with replaced target register,
1853 if needed) to the recovery block. */
1854 if (recovery_block != NULL)
1859 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1860 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1861 twin = sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1862 INSN_EXPR (orig_insn),
1864 bb_note (recovery_block));
1867 /* If we've generated a data speculation check, make sure
1868 that all the bookkeeping instruction we'll create during
1869 this move_op () will allocate an ALAT entry so that the
1871 In case of control speculation we must convert C_EXPR to control
1872 speculative mode, because failing to do so will bring us an exception
1873 thrown by the non-control-speculative load. */
1874 check_ds = ds_get_max_dep_weak (check_ds);
1875 speculate_expr (c_expr, check_ds);
1880 /* True when INSN is a "regN = regN" copy. */
1882 identical_copy_p (rtx insn)
1886 pat = PATTERN (insn);
1888 if (GET_CODE (pat) != SET)
1891 lhs = SET_DEST (pat);
1895 rhs = SET_SRC (pat);
1899 return REGNO (lhs) == REGNO (rhs);
1902 /* Undo all transformations on *AV_PTR that were done when
1903 moving through INSN. */
1905 undo_transformations (av_set_t *av_ptr, rtx insn)
1907 av_set_iterator av_iter;
1909 av_set_t new_set = NULL;
1911 /* First, kill any EXPR that uses registers set by an insn. This is
1912 required for correctness. */
1913 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1914 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1915 && bitmap_intersect_p (INSN_REG_SETS (insn),
1916 VINSN_REG_USES (EXPR_VINSN (expr)))
1917 /* When an insn looks like 'r1 = r1', we could substitute through
1918 it, but the above condition will still hold. This happened with
1919 gcc.c-torture/execute/961125-1.c. */
1920 && !identical_copy_p (insn))
1922 if (sched_verbose >= 6)
1923 sel_print ("Expr %d removed due to use/set conflict\n",
1924 INSN_UID (EXPR_INSN_RTX (expr)));
1925 av_set_iter_remove (&av_iter);
1928 /* Undo transformations looking at the history vector. */
1929 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1931 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1932 insn, EXPR_VINSN (expr), true);
1936 expr_history_def *phist;
1938 phist = VEC_index (expr_history_def,
1939 EXPR_HISTORY_OF_CHANGES (expr),
1942 switch (phist->type)
1944 case TRANS_SPECULATION:
1946 ds_t old_ds, new_ds;
1948 /* Compute the difference between old and new speculative
1949 statuses: that's what we need to check.
1950 Earlier we used to assert that the status will really
1951 change. This no longer works because only the probability
1952 bits in the status may have changed during compute_av_set,
1953 and in the case of merging different probabilities of the
1954 same speculative status along different paths we do not
1955 record this in the history vector. */
1956 old_ds = phist->spec_ds;
1957 new_ds = EXPR_SPEC_DONE_DS (expr);
1959 old_ds &= SPECULATIVE;
1960 new_ds &= SPECULATIVE;
1963 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1966 case TRANS_SUBSTITUTION:
1968 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1972 new_vi = phist->old_expr_vinsn;
1974 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1975 == EXPR_SEPARABLE_P (expr));
1976 copy_expr (tmp_expr, expr);
1978 if (vinsn_equal_p (phist->new_expr_vinsn,
1979 EXPR_VINSN (tmp_expr)))
1980 change_vinsn_in_expr (tmp_expr, new_vi);
1982 /* This happens when we're unsubstituting on a bookkeeping
1983 copy, which was in turn substituted. The history is wrong
1984 in this case. Do it the hard way. */
1985 add = substitute_reg_in_expr (tmp_expr, insn, true);
1987 av_set_add (&new_set, tmp_expr);
1988 clear_expr (tmp_expr);
1998 av_set_union_and_clear (av_ptr, &new_set, NULL);
2002 /* Moveup_* helpers for code motion and computing av sets. */
2004 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2005 The difference from the below function is that only substitution is
2007 static enum MOVEUP_EXPR_CODE
2008 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
2010 vinsn_t vi = EXPR_VINSN (expr);
2014 /* Do this only inside insn group. */
2015 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
2017 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2019 return MOVEUP_EXPR_SAME;
2021 /* Substitution is the possible choice in this case. */
2022 if (has_dep_p[DEPS_IN_RHS])
2024 /* Can't substitute UNIQUE VINSNs. */
2025 gcc_assert (!VINSN_UNIQUE_P (vi));
2027 if (can_substitute_through_p (through_insn,
2028 has_dep_p[DEPS_IN_RHS])
2029 && substitute_reg_in_expr (expr, through_insn, false))
2031 EXPR_WAS_SUBSTITUTED (expr) = true;
2032 return MOVEUP_EXPR_CHANGED;
2035 /* Don't care about this, as even true dependencies may be allowed
2036 in an insn group. */
2037 return MOVEUP_EXPR_SAME;
2040 /* This can catch output dependencies in COND_EXECs. */
2041 if (has_dep_p[DEPS_IN_INSN])
2042 return MOVEUP_EXPR_NULL;
2044 /* This is either an output or an anti dependence, which usually have
2045 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2047 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2048 return MOVEUP_EXPR_AS_RHS;
2051 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2052 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2053 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2054 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2055 && !sel_insn_is_speculation_check (through_insn))
2057 /* True when a conflict on a target register was found during moveup_expr. */
2058 static bool was_target_conflict = false;
2060 /* Return true when moving a debug INSN across THROUGH_INSN will
2061 create a bookkeeping block. We don't want to create such blocks,
2062 for they would cause codegen differences between compilations with
2063 and without debug info. */
2066 moving_insn_creates_bookkeeping_block_p (insn_t insn,
2067 insn_t through_insn)
2069 basic_block bbi, bbt;
2071 edge_iterator ei1, ei2;
2073 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn))
2075 if (sched_verbose >= 9)
2076 sel_print ("no bookkeeping required: ");
2080 bbi = BLOCK_FOR_INSN (insn);
2082 if (EDGE_COUNT (bbi->preds) == 1)
2084 if (sched_verbose >= 9)
2085 sel_print ("only one pred edge: ");
2089 bbt = BLOCK_FOR_INSN (through_insn);
2091 FOR_EACH_EDGE (e1, ei1, bbt->succs)
2093 FOR_EACH_EDGE (e2, ei2, bbi->preds)
2095 if (find_block_for_bookkeeping (e1, e2, TRUE))
2097 if (sched_verbose >= 9)
2098 sel_print ("found existing block: ");
2104 if (sched_verbose >= 9)
2105 sel_print ("would create bookkeeping block: ");
2110 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2111 performing necessary transformations. Record the type of transformation
2112 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2113 permit all dependencies except true ones, and try to remove those
2114 too via forward substitution. All cases when a non-eliminable
2115 non-zero cost dependency exists inside an insn group will be fixed
2116 in tick_check_p instead. */
2117 static enum MOVEUP_EXPR_CODE
2118 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2119 enum local_trans_type *ptrans_type)
2121 vinsn_t vi = EXPR_VINSN (expr);
2122 insn_t insn = VINSN_INSN_RTX (vi);
2123 bool was_changed = false;
2124 bool as_rhs = false;
2128 /* When inside_insn_group, delegate to the helper. */
2129 if (inside_insn_group)
2130 return moveup_expr_inside_insn_group (expr, through_insn);
2132 /* Deal with unique insns and control dependencies. */
2133 if (VINSN_UNIQUE_P (vi))
2135 /* We can move jumps without side-effects or jumps that are
2136 mutually exclusive with instruction THROUGH_INSN (all in cases
2137 dependencies allow to do so and jump is not speculative). */
2138 if (control_flow_insn_p (insn))
2140 basic_block fallthru_bb;
2142 /* Do not move checks and do not move jumps through other
2144 if (control_flow_insn_p (through_insn)
2145 || sel_insn_is_speculation_check (insn))
2146 return MOVEUP_EXPR_NULL;
2148 /* Don't move jumps through CFG joins. */
2149 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2150 return MOVEUP_EXPR_NULL;
2152 /* The jump should have a clear fallthru block, and
2153 this block should be in the current region. */
2154 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2155 || ! in_current_region_p (fallthru_bb))
2156 return MOVEUP_EXPR_NULL;
2158 /* And it should be mutually exclusive with through_insn, or
2159 be an unconditional jump. */
2160 if (! any_uncondjump_p (insn)
2161 && ! sched_insns_conditions_mutex_p (insn, through_insn)
2162 && ! DEBUG_INSN_P (through_insn))
2163 return MOVEUP_EXPR_NULL;
2166 /* Don't move what we can't move. */
2167 if (EXPR_CANT_MOVE (expr)
2168 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2169 return MOVEUP_EXPR_NULL;
2171 /* Don't move SCHED_GROUP instruction through anything.
2172 If we don't force this, then it will be possible to start
2173 scheduling a sched_group before all its dependencies are
2175 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2176 as late as possible through rank_for_schedule. */
2177 if (SCHED_GROUP_P (insn))
2178 return MOVEUP_EXPR_NULL;
2181 gcc_assert (!control_flow_insn_p (insn));
2183 /* Don't move debug insns if this would require bookkeeping. */
2184 if (DEBUG_INSN_P (insn)
2185 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)
2186 && moving_insn_creates_bookkeeping_block_p (insn, through_insn))
2187 return MOVEUP_EXPR_NULL;
2189 /* Deal with data dependencies. */
2190 was_target_conflict = false;
2191 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2194 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2195 return MOVEUP_EXPR_SAME;
2199 /* We can move UNIQUE insn up only as a whole and unchanged,
2200 so it shouldn't have any dependencies. */
2201 if (VINSN_UNIQUE_P (vi))
2202 return MOVEUP_EXPR_NULL;
2205 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2209 res = speculate_expr (expr, full_ds);
2212 /* Speculation was successful. */
2214 was_changed = (res > 0);
2216 was_target_conflict = true;
2218 *ptrans_type = TRANS_SPECULATION;
2219 sel_clear_has_dependence ();
2223 if (has_dep_p[DEPS_IN_INSN])
2224 /* We have some dependency that cannot be discarded. */
2225 return MOVEUP_EXPR_NULL;
2227 if (has_dep_p[DEPS_IN_LHS])
2229 /* Only separable insns can be moved up with the new register.
2230 Anyways, we should mark that the original register is
2232 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2233 return MOVEUP_EXPR_NULL;
2235 EXPR_TARGET_AVAILABLE (expr) = false;
2236 was_target_conflict = true;
2240 /* At this point we have either separable insns, that will be lifted
2241 up only as RHSes, or non-separable insns with no dependency in lhs.
2242 If dependency is in RHS, then try to perform substitution and move up
2249 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2250 moved above y=x assignment as z=x*2.
2252 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2253 side can be moved because of the output dependency. The operation was
2254 cropped to its rhs above. */
2255 if (has_dep_p[DEPS_IN_RHS])
2257 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2259 /* Can't substitute UNIQUE VINSNs. */
2260 gcc_assert (!VINSN_UNIQUE_P (vi));
2262 if (can_speculate_dep_p (*rhs_dsp))
2266 res = speculate_expr (expr, *rhs_dsp);
2269 /* Speculation was successful. */
2271 was_changed = (res > 0);
2273 was_target_conflict = true;
2275 *ptrans_type = TRANS_SPECULATION;
2278 return MOVEUP_EXPR_NULL;
2280 else if (can_substitute_through_p (through_insn,
2282 && substitute_reg_in_expr (expr, through_insn, false))
2284 /* ??? We cannot perform substitution AND speculation on the same
2286 gcc_assert (!was_changed);
2289 *ptrans_type = TRANS_SUBSTITUTION;
2290 EXPR_WAS_SUBSTITUTED (expr) = true;
2293 return MOVEUP_EXPR_NULL;
2296 /* Don't move trapping insns through jumps.
2297 This check should be at the end to give a chance to control speculation
2298 to perform its duties. */
2299 if (CANT_MOVE_TRAPPING (expr, through_insn))
2300 return MOVEUP_EXPR_NULL;
2303 ? MOVEUP_EXPR_CHANGED
2305 ? MOVEUP_EXPR_AS_RHS
2306 : MOVEUP_EXPR_SAME));
2309 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2310 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2311 that can exist within a parallel group. Write to RES the resulting
2312 code for moveup_expr. */
2314 try_bitmap_cache (expr_t expr, insn_t insn,
2315 bool inside_insn_group,
2316 enum MOVEUP_EXPR_CODE *res)
2318 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2320 /* First check whether we've analyzed this situation already. */
2321 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2323 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2325 if (sched_verbose >= 6)
2326 sel_print ("removed (cached)\n");
2327 *res = MOVEUP_EXPR_NULL;
2332 if (sched_verbose >= 6)
2333 sel_print ("unchanged (cached)\n");
2334 *res = MOVEUP_EXPR_SAME;
2338 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2340 if (inside_insn_group)
2342 if (sched_verbose >= 6)
2343 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2344 *res = MOVEUP_EXPR_SAME;
2349 EXPR_TARGET_AVAILABLE (expr) = false;
2351 /* This is the only case when propagation result can change over time,
2352 as we can dynamically switch off scheduling as RHS. In this case,
2353 just check the flag to reach the correct decision. */
2354 if (enable_schedule_as_rhs_p)
2356 if (sched_verbose >= 6)
2357 sel_print ("unchanged (as RHS, cached)\n");
2358 *res = MOVEUP_EXPR_AS_RHS;
2363 if (sched_verbose >= 6)
2364 sel_print ("removed (cached as RHS, but renaming"
2365 " is now disabled)\n");
2366 *res = MOVEUP_EXPR_NULL;
2374 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2375 if successful. Write to RES the resulting code for moveup_expr. */
2377 try_transformation_cache (expr_t expr, insn_t insn,
2378 enum MOVEUP_EXPR_CODE *res)
2380 struct transformed_insns *pti
2381 = (struct transformed_insns *)
2382 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2384 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2387 /* This EXPR was already moved through this insn and was
2388 changed as a result. Fetch the proper data from
2390 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2391 INSN_UID (insn), pti->type,
2392 pti->vinsn_old, pti->vinsn_new,
2393 EXPR_SPEC_DONE_DS (expr));
2395 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2396 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2397 change_vinsn_in_expr (expr, pti->vinsn_new);
2398 if (pti->was_target_conflict)
2399 EXPR_TARGET_AVAILABLE (expr) = false;
2400 if (pti->type == TRANS_SPECULATION)
2404 ds = EXPR_SPEC_DONE_DS (expr);
2406 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2407 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2410 if (sched_verbose >= 6)
2412 sel_print ("changed (cached): ");
2417 *res = MOVEUP_EXPR_CHANGED;
2424 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2426 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2427 enum MOVEUP_EXPR_CODE res)
2429 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2431 /* Do not cache result of propagating jumps through an insn group,
2432 as it is always true, which is not useful outside the group. */
2433 if (inside_insn_group)
2436 if (res == MOVEUP_EXPR_NULL)
2438 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2439 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2441 else if (res == MOVEUP_EXPR_SAME)
2443 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2444 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2446 else if (res == MOVEUP_EXPR_AS_RHS)
2448 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2449 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2455 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2456 and transformation type TRANS_TYPE. */
2458 update_transformation_cache (expr_t expr, insn_t insn,
2459 bool inside_insn_group,
2460 enum local_trans_type trans_type,
2461 vinsn_t expr_old_vinsn)
2463 struct transformed_insns *pti;
2465 if (inside_insn_group)
2468 pti = XNEW (struct transformed_insns);
2469 pti->vinsn_old = expr_old_vinsn;
2470 pti->vinsn_new = EXPR_VINSN (expr);
2471 pti->type = trans_type;
2472 pti->was_target_conflict = was_target_conflict;
2473 pti->ds = EXPR_SPEC_DONE_DS (expr);
2474 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2475 vinsn_attach (pti->vinsn_old);
2476 vinsn_attach (pti->vinsn_new);
2477 *((struct transformed_insns **)
2478 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2479 pti, VINSN_HASH_RTX (expr_old_vinsn),
2483 /* Same as moveup_expr, but first looks up the result of
2484 transformation in caches. */
2485 static enum MOVEUP_EXPR_CODE
2486 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2488 enum MOVEUP_EXPR_CODE res;
2489 bool got_answer = false;
2491 if (sched_verbose >= 6)
2493 sel_print ("Moving ");
2495 sel_print (" through %d: ", INSN_UID (insn));
2498 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr))
2499 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr)))
2500 == EXPR_INSN_RTX (expr)))
2501 /* Don't use cached information for debug insns that are heads of
2503 else if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2504 /* When inside insn group, we do not want remove stores conflicting
2505 with previosly issued loads. */
2506 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2507 else if (try_transformation_cache (expr, insn, &res))
2512 /* Invoke moveup_expr and record the results. */
2513 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2514 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2515 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2516 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2517 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2519 /* ??? Invent something better than this. We can't allow old_vinsn
2520 to go, we need it for the history vector. */
2521 vinsn_attach (expr_old_vinsn);
2523 res = moveup_expr (expr, insn, inside_insn_group,
2527 case MOVEUP_EXPR_NULL:
2528 update_bitmap_cache (expr, insn, inside_insn_group, res);
2529 if (sched_verbose >= 6)
2530 sel_print ("removed\n");
2533 case MOVEUP_EXPR_SAME:
2534 update_bitmap_cache (expr, insn, inside_insn_group, res);
2535 if (sched_verbose >= 6)
2536 sel_print ("unchanged\n");
2539 case MOVEUP_EXPR_AS_RHS:
2540 gcc_assert (!unique_p || inside_insn_group);
2541 update_bitmap_cache (expr, insn, inside_insn_group, res);
2542 if (sched_verbose >= 6)
2543 sel_print ("unchanged (as RHS)\n");
2546 case MOVEUP_EXPR_CHANGED:
2547 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2548 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2549 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2550 INSN_UID (insn), trans_type,
2551 expr_old_vinsn, EXPR_VINSN (expr),
2553 update_transformation_cache (expr, insn, inside_insn_group,
2554 trans_type, expr_old_vinsn);
2555 if (sched_verbose >= 6)
2557 sel_print ("changed: ");
2566 vinsn_detach (expr_old_vinsn);
2572 /* Moves an av set AVP up through INSN, performing necessary
2575 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2580 FOR_EACH_EXPR_1 (expr, i, avp)
2583 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2585 case MOVEUP_EXPR_SAME:
2586 case MOVEUP_EXPR_AS_RHS:
2589 case MOVEUP_EXPR_NULL:
2590 av_set_iter_remove (&i);
2593 case MOVEUP_EXPR_CHANGED:
2594 expr = merge_with_other_exprs (avp, &i, expr);
2603 /* Moves AVP set along PATH. */
2605 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2609 if (sched_verbose >= 6)
2610 sel_print ("Moving expressions up in the insn group...\n");
2613 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2615 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2617 moveup_set_expr (avp, ILIST_INSN (path), true);
2618 path = ILIST_NEXT (path);
2622 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2624 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2626 expr_def _tmp, *tmp = &_tmp;
2630 copy_expr_onside (tmp, expr);
2631 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2634 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2636 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2637 != MOVEUP_EXPR_NULL);
2638 path = ILIST_NEXT (path);
2643 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2644 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2646 if (tmp_vinsn != expr_vliw_vinsn)
2647 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2655 /* Functions that compute av and lv sets. */
2657 /* Returns true if INSN is not a downward continuation of the given path P in
2658 the current stage. */
2660 is_ineligible_successor (insn_t insn, ilist_t p)
2664 /* Check if insn is not deleted. */
2665 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2667 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2670 /* If it's the first insn visited, then the successor is ok. */
2674 prev_insn = ILIST_INSN (p);
2676 if (/* a backward edge. */
2677 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2678 /* is already visited. */
2679 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2680 && (ilist_is_in_p (p, insn)
2681 /* We can reach another fence here and still seqno of insn
2682 would be equal to seqno of prev_insn. This is possible
2683 when prev_insn is a previously created bookkeeping copy.
2684 In that case it'd get a seqno of insn. Thus, check here
2685 whether insn is in current fence too. */
2686 || IN_CURRENT_FENCE_P (insn)))
2687 /* Was already scheduled on this round. */
2688 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2689 && IN_CURRENT_FENCE_P (insn))
2690 /* An insn from another fence could also be
2691 scheduled earlier even if this insn is not in
2692 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2694 && INSN_SCHED_TIMES (insn) > 0))
2700 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2701 of handling multiple successors and properly merging its av_sets. P is
2702 the current path traversed. WS is the size of lookahead window.
2703 Return the av set computed. */
2705 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2707 struct succs_info *sinfo;
2708 av_set_t expr_in_all_succ_branches = NULL;
2710 insn_t succ, zero_succ = NULL;
2711 av_set_t av1 = NULL;
2713 gcc_assert (sel_bb_end_p (insn));
2715 /* Find different kind of successors needed for correct computing of
2716 SPEC and TARGET_AVAILABLE attributes. */
2717 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2720 if (sched_verbose >= 6)
2722 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2723 dump_insn_vector (sinfo->succs_ok);
2725 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2726 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2729 /* Add insn to to the tail of current path. */
2730 ilist_add (&p, insn);
2732 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2736 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2737 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2739 av_set_split_usefulness (succ_set,
2740 VEC_index (int, sinfo->probs_ok, is),
2743 if (sinfo->all_succs_n > 1
2744 && sinfo->all_succs_n == sinfo->succs_ok_n)
2746 /* Find EXPR'es that came from *all* successors and save them
2747 into expr_in_all_succ_branches. This set will be used later
2748 for calculating speculation attributes of EXPR'es. */
2751 expr_in_all_succ_branches = av_set_copy (succ_set);
2753 /* Remember the first successor for later. */
2761 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2762 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2763 av_set_iter_remove (&i);
2767 /* Union the av_sets. Check liveness restrictions on target registers
2768 in special case of two successors. */
2769 if (sinfo->succs_ok_n == 2 && is == 1)
2771 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2772 basic_block bb1 = BLOCK_FOR_INSN (succ);
2774 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2775 av_set_union_and_live (&av1, &succ_set,
2781 av_set_union_and_clear (&av1, &succ_set, insn);
2784 /* Check liveness restrictions via hard way when there are more than
2786 if (sinfo->succs_ok_n > 2)
2787 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2789 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2791 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2792 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2793 BB_LV_SET (succ_bb));
2796 /* Finally, check liveness restrictions on paths leaving the region. */
2797 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2798 for (is = 0; VEC_iterate (rtx, sinfo->succs_other, is, succ); is++)
2799 mark_unavailable_targets
2800 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2802 if (sinfo->all_succs_n > 1)
2807 /* Increase the spec attribute of all EXPR'es that didn't come
2808 from all successors. */
2809 FOR_EACH_EXPR (expr, i, av1)
2810 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2813 av_set_clear (&expr_in_all_succ_branches);
2815 /* Do not move conditional branches through other
2816 conditional branches. So, remove all conditional
2817 branches from av_set if current operator is a conditional
2819 av_set_substract_cond_branches (&av1);
2823 free_succs_info (sinfo);
2825 if (sched_verbose >= 6)
2827 sel_print ("av_succs (%d): ", INSN_UID (insn));
2835 /* This function computes av_set for the FIRST_INSN by dragging valid
2836 av_set through all basic block insns either from the end of basic block
2837 (computed using compute_av_set_at_bb_end) or from the insn on which
2838 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2839 below the basic block and handling conditional branches.
2840 FIRST_INSN - the basic block head, P - path consisting of the insns
2841 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2842 and bb ends are added to the path), WS - current window size,
2843 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2845 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2850 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2851 insn_t after_bb_end = NEXT_INSN (bb_end);
2854 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2856 /* Return NULL if insn is not on the legitimate downward path. */
2857 if (is_ineligible_successor (first_insn, p))
2859 if (sched_verbose >= 6)
2860 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2865 /* If insn already has valid av(insn) computed, just return it. */
2866 if (AV_SET_VALID_P (first_insn))
2870 if (sel_bb_head_p (first_insn))
2871 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2875 if (sched_verbose >= 6)
2877 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2878 dump_av_set (av_set);
2882 return need_copy_p ? av_set_copy (av_set) : av_set;
2885 ilist_add (&p, first_insn);
2887 /* As the result after this loop have completed, in LAST_INSN we'll
2888 have the insn which has valid av_set to start backward computation
2889 from: it either will be NULL because on it the window size was exceeded
2890 or other valid av_set as returned by compute_av_set for the last insn
2891 of the basic block. */
2892 for (last_insn = first_insn; last_insn != after_bb_end;
2893 last_insn = NEXT_INSN (last_insn))
2895 /* We may encounter valid av_set not only on bb_head, but also on
2896 those insns on which previously MAX_WS was exceeded. */
2897 if (AV_SET_VALID_P (last_insn))
2899 if (sched_verbose >= 6)
2900 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2904 /* The special case: the last insn of the BB may be an
2905 ineligible_successor due to its SEQ_NO that was set on
2906 it as a bookkeeping. */
2907 if (last_insn != first_insn
2908 && is_ineligible_successor (last_insn, p))
2910 if (sched_verbose >= 6)
2911 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
2915 if (DEBUG_INSN_P (last_insn))
2918 if (end_ws > max_ws)
2920 /* We can reach max lookahead size at bb_header, so clean av_set
2922 INSN_WS_LEVEL (last_insn) = global_level;
2924 if (sched_verbose >= 6)
2925 sel_print ("Insn %d is beyond the software lookahead window size\n",
2926 INSN_UID (last_insn));
2933 /* Get the valid av_set into AV above the LAST_INSN to start backward
2934 computation from. It either will be empty av_set or av_set computed from
2935 the successors on the last insn of the current bb. */
2936 if (last_insn != after_bb_end)
2940 /* This is needed only to obtain av_sets that are identical to
2941 those computed by the old compute_av_set version. */
2942 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
2943 av_set_add (&av, INSN_EXPR (last_insn));
2946 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2947 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
2949 /* Compute av_set in AV starting from below the LAST_INSN up to
2950 location above the FIRST_INSN. */
2951 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
2952 cur_insn = PREV_INSN (cur_insn))
2953 if (!INSN_NOP_P (cur_insn))
2957 moveup_set_expr (&av, cur_insn, false);
2959 /* If the expression for CUR_INSN is already in the set,
2960 replace it by the new one. */
2961 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
2965 copy_expr (expr, INSN_EXPR (cur_insn));
2968 av_set_add (&av, INSN_EXPR (cur_insn));
2971 /* Clear stale bb_av_set. */
2972 if (sel_bb_head_p (first_insn))
2974 av_set_clear (&BB_AV_SET (cur_bb));
2975 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
2976 BB_AV_LEVEL (cur_bb) = global_level;
2979 if (sched_verbose >= 6)
2981 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
2990 /* Compute av set before INSN.
2991 INSN - the current operation (actual rtx INSN)
2992 P - the current path, which is list of insns visited so far
2993 WS - software lookahead window size.
2994 UNIQUE_P - TRUE, if returned av_set will be changed, hence
2995 if we want to save computed av_set in s_i_d, we should make a copy of it.
2997 In the resulting set we will have only expressions that don't have delay
2998 stalls and nonsubstitutable dependences. */
3000 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
3002 return compute_av_set_inside_bb (insn, p, ws, unique_p);
3005 /* Propagate a liveness set LV through INSN. */
3007 propagate_lv_set (regset lv, insn_t insn)
3009 gcc_assert (INSN_P (insn));
3011 if (INSN_NOP_P (insn))
3014 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
3017 /* Return livness set at the end of BB. */
3019 compute_live_after_bb (basic_block bb)
3023 regset lv = get_clear_regset_from_pool ();
3025 gcc_assert (!ignore_first);
3027 FOR_EACH_EDGE (e, ei, bb->succs)
3028 if (sel_bb_empty_p (e->dest))
3030 if (! BB_LV_SET_VALID_P (e->dest))
3033 gcc_assert (BB_LV_SET (e->dest) == NULL);
3034 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
3035 BB_LV_SET_VALID_P (e->dest) = true;
3037 IOR_REG_SET (lv, BB_LV_SET (e->dest));
3040 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
3045 /* Compute the set of all live registers at the point before INSN and save
3046 it at INSN if INSN is bb header. */
3048 compute_live (insn_t insn)
3050 basic_block bb = BLOCK_FOR_INSN (insn);
3054 /* Return the valid set if we're already on it. */
3059 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3060 src = BB_LV_SET (bb);
3063 gcc_assert (in_current_region_p (bb));
3064 if (INSN_LIVE_VALID_P (insn))
3065 src = INSN_LIVE (insn);
3070 lv = get_regset_from_pool ();
3071 COPY_REG_SET (lv, src);
3073 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3075 COPY_REG_SET (BB_LV_SET (bb), lv);
3076 BB_LV_SET_VALID_P (bb) = true;
3079 return_regset_to_pool (lv);
3084 /* We've skipped the wrong lv_set. Don't skip the right one. */
3085 ignore_first = false;
3086 gcc_assert (in_current_region_p (bb));
3088 /* Find a valid LV set in this block or below, if needed.
3089 Start searching from the next insn: either ignore_first is true, or
3090 INSN doesn't have a correct live set. */
3091 temp = NEXT_INSN (insn);
3092 final = NEXT_INSN (BB_END (bb));
3093 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3094 temp = NEXT_INSN (temp);
3097 lv = compute_live_after_bb (bb);
3098 temp = PREV_INSN (temp);
3102 lv = get_regset_from_pool ();
3103 COPY_REG_SET (lv, INSN_LIVE (temp));
3106 /* Put correct lv sets on the insns which have bad sets. */
3107 final = PREV_INSN (insn);
3108 while (temp != final)
3110 propagate_lv_set (lv, temp);
3111 COPY_REG_SET (INSN_LIVE (temp), lv);
3112 INSN_LIVE_VALID_P (temp) = true;
3113 temp = PREV_INSN (temp);
3116 /* Also put it in a BB. */
3117 if (sel_bb_head_p (insn))
3119 basic_block bb = BLOCK_FOR_INSN (insn);
3121 COPY_REG_SET (BB_LV_SET (bb), lv);
3122 BB_LV_SET_VALID_P (bb) = true;
3125 /* We return LV to the pool, but will not clear it there. Thus we can
3126 legimatelly use LV till the next use of regset_pool_get (). */
3127 return_regset_to_pool (lv);
3131 /* Update liveness sets for INSN. */
3133 update_liveness_on_insn (rtx insn)
3135 ignore_first = true;
3136 compute_live (insn);
3139 /* Compute liveness below INSN and write it into REGS. */
3141 compute_live_below_insn (rtx insn, regset regs)
3146 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3147 IOR_REG_SET (regs, compute_live (succ));
3150 /* Update the data gathered in av and lv sets starting from INSN. */
3152 update_data_sets (rtx insn)
3154 update_liveness_on_insn (insn);
3155 if (sel_bb_head_p (insn))
3157 gcc_assert (AV_LEVEL (insn) != 0);
3158 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3159 compute_av_set (insn, NULL, 0, 0);
3164 /* Helper for move_op () and find_used_regs ().
3165 Return speculation type for which a check should be created on the place
3166 of INSN. EXPR is one of the original ops we are searching for. */
3168 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3171 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3173 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3175 if (targetm.sched.get_insn_checked_ds)
3176 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3178 if (spec_info != NULL
3179 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3180 already_checked_ds |= BEGIN_CONTROL;
3182 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3184 to_check_ds &= ~already_checked_ds;
3189 /* Find the set of registers that are unavailable for storing expres
3190 while moving ORIG_OPS up on the path starting from INSN due to
3191 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3193 All the original operations found during the traversal are saved in the
3194 ORIGINAL_INSNS list.
3196 REG_RENAME_P denotes the set of hardware registers that
3197 can not be used with renaming due to the register class restrictions,
3198 mode restrictions and other (the register we'll choose should be
3199 compatible class with the original uses, shouldn't be in call_used_regs,
3200 should be HARD_REGNO_RENAME_OK etc).
3202 Returns TRUE if we've found all original insns, FALSE otherwise.
3204 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3205 to traverse the code motion paths. This helper function finds registers
3206 that are not available for storing expres while moving ORIG_OPS up on the
3207 path starting from INSN. A register considered as used on the moving path,
3208 if one of the following conditions is not satisfied:
3210 (1) a register not set or read on any path from xi to an instance of
3211 the original operation,
3212 (2) not among the live registers of the point immediately following the
3213 first original operation on a given downward path, except for the
3214 original target register of the operation,
3215 (3) not live on the other path of any conditional branch that is passed
3216 by the operation, in case original operations are not present on
3217 both paths of the conditional branch.
3219 All the original operations found during the traversal are saved in the
3220 ORIGINAL_INSNS list.
3222 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3223 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3224 to unavailable hard regs at the point original operation is found. */
3227 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3228 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3230 def_list_iterator i;
3233 bool needs_spec_check_p = false;
3235 av_set_iterator expr_iter;
3236 struct fur_static_params sparams;
3237 struct cmpd_local_params lparams;
3239 /* We haven't visited any blocks yet. */
3240 bitmap_clear (code_motion_visited_blocks);
3242 /* Init parameters for code_motion_path_driver. */
3243 sparams.crosses_call = false;
3244 sparams.original_insns = original_insns;
3245 sparams.used_regs = used_regs;
3247 /* Set the appropriate hooks and data. */
3248 code_motion_path_driver_info = &fur_hooks;
3250 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3252 reg_rename_p->crosses_call |= sparams.crosses_call;
3254 gcc_assert (res == 1);
3255 gcc_assert (original_insns && *original_insns);
3257 /* ??? We calculate whether an expression needs a check when computing
3258 av sets. This information is not as precise as it could be due to
3259 merging this bit in merge_expr. We can do better in find_used_regs,
3260 but we want to avoid multiple traversals of the same code motion
3262 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3263 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3265 /* Mark hardware regs in REG_RENAME_P that are not suitable
3266 for renaming expr in INSN due to hardware restrictions (register class,
3267 modes compatibility etc). */
3268 FOR_EACH_DEF (def, i, *original_insns)
3270 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3272 if (VINSN_SEPARABLE_P (vinsn))
3273 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3275 /* Do not allow clobbering of ld.[sa] address in case some of the
3276 original operations need a check. */
3277 if (needs_spec_check_p)
3278 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3285 /* Functions to choose the best insn from available ones. */
3287 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3289 sel_target_adjust_priority (expr_t expr)
3291 int priority = EXPR_PRIORITY (expr);
3294 if (targetm.sched.adjust_priority)
3295 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3297 new_priority = priority;
3299 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3300 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3302 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3304 if (sched_verbose >= 2)
3305 sel_print ("sel_target_adjust_priority: insn %d, %d +%d = %d.\n",
3306 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3307 EXPR_PRIORITY_ADJ (expr), new_priority);
3309 return new_priority;
3312 /* Rank two available exprs for schedule. Never return 0 here. */
3314 sel_rank_for_schedule (const void *x, const void *y)
3316 expr_t tmp = *(const expr_t *) y;
3317 expr_t tmp2 = *(const expr_t *) x;
3318 insn_t tmp_insn, tmp2_insn;
3319 vinsn_t tmp_vinsn, tmp2_vinsn;
3322 tmp_vinsn = EXPR_VINSN (tmp);
3323 tmp2_vinsn = EXPR_VINSN (tmp2);
3324 tmp_insn = EXPR_INSN_RTX (tmp);
3325 tmp2_insn = EXPR_INSN_RTX (tmp2);
3327 /* Schedule debug insns as early as possible. */
3328 if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn))
3330 else if (DEBUG_INSN_P (tmp2_insn))
3333 /* Prefer SCHED_GROUP_P insns to any others. */
3334 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3336 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3337 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3339 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3340 cannot be cloned. */
3341 if (VINSN_UNIQUE_P (tmp2_vinsn))
3346 /* Discourage scheduling of speculative checks. */
3347 val = (sel_insn_is_speculation_check (tmp_insn)
3348 - sel_insn_is_speculation_check (tmp2_insn));
3352 /* Prefer not scheduled insn over scheduled one. */
3353 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3355 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3360 /* Prefer jump over non-jump instruction. */
3361 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3363 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3366 /* Prefer an expr with greater priority. */
3367 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3369 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3370 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3372 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3375 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3376 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3380 if (spec_info != NULL && spec_info->mask != 0)
3381 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3387 ds1 = EXPR_SPEC_DONE_DS (tmp);
3389 dw1 = ds_weak (ds1);
3393 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3395 dw2 = ds_weak (ds2);
3400 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3404 /* Prefer an old insn to a bookkeeping insn. */
3405 if (INSN_UID (tmp_insn) < first_emitted_uid
3406 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3408 if (INSN_UID (tmp_insn) >= first_emitted_uid
3409 && INSN_UID (tmp2_insn) < first_emitted_uid)
3412 /* Prefer an insn with smaller UID, as a last resort.
3413 We can't safely use INSN_LUID as it is defined only for those insns
3414 that are in the stream. */
3415 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3418 /* Filter out expressions from av set pointed to by AV_PTR
3419 that are pipelined too many times. */
3421 process_pipelined_exprs (av_set_t *av_ptr)
3426 /* Don't pipeline already pipelined code as that would increase
3427 number of unnecessary register moves. */
3428 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3430 if (EXPR_SCHED_TIMES (expr)
3431 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3432 av_set_iter_remove (&si);
3436 /* Filter speculative insns from AV_PTR if we don't want them. */
3438 process_spec_exprs (av_set_t *av_ptr)
3440 bool try_data_p = true;
3441 bool try_control_p = true;
3445 if (spec_info == NULL)
3448 /* Scan *AV_PTR to find out if we want to consider speculative
3449 instructions for scheduling. */
3450 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3454 ds = EXPR_SPEC_DONE_DS (expr);
3456 /* The probability of a success is too low - don't speculate. */
3457 if ((ds & SPECULATIVE)
3458 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3459 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3460 || (pipelining_p && false
3462 && (ds & CONTROL_SPEC))))
3464 av_set_iter_remove (&si);
3468 if ((spec_info->flags & PREFER_NON_DATA_SPEC)
3469 && !(ds & BEGIN_DATA))
3472 if ((spec_info->flags & PREFER_NON_CONTROL_SPEC)
3473 && !(ds & BEGIN_CONTROL))
3474 try_control_p = false;
3477 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3481 ds = EXPR_SPEC_DONE_DS (expr);
3483 if (ds & SPECULATIVE)
3485 if ((ds & BEGIN_DATA) && !try_data_p)
3486 /* We don't want any data speculative instructions right
3488 av_set_iter_remove (&si);
3490 if ((ds & BEGIN_CONTROL) && !try_control_p)
3491 /* We don't want any control speculative instructions right
3493 av_set_iter_remove (&si);
3498 /* Search for any use-like insns in AV_PTR and decide on scheduling
3499 them. Return one when found, and NULL otherwise.
3500 Note that we check here whether a USE could be scheduled to avoid
3501 an infinite loop later. */
3503 process_use_exprs (av_set_t *av_ptr)
3507 bool uses_present_p = false;
3508 bool try_uses_p = true;
3510 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3512 /* This will also initialize INSN_CODE for later use. */
3513 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3515 /* If we have a USE in *AV_PTR that was not scheduled yet,
3516 do so because it will do good only. */
3517 if (EXPR_SCHED_TIMES (expr) <= 0)
3519 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3522 av_set_iter_remove (&si);
3526 gcc_assert (pipelining_p);
3528 uses_present_p = true;
3537 /* If we don't want to schedule any USEs right now and we have some
3538 in *AV_PTR, remove them, else just return the first one found. */
3541 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3542 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3543 av_set_iter_remove (&si);
3547 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3549 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3551 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3554 av_set_iter_remove (&si);
3562 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3564 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3569 for (n = 0; VEC_iterate (vinsn_t, vinsn_vec, n, vinsn); n++)
3570 if (VINSN_SEPARABLE_P (vinsn))
3572 if (vinsn_equal_p (vinsn, EXPR_VINSN (expr)))
3577 /* For non-separable instructions, the blocking insn can have
3578 another pattern due to substitution, and we can't choose
3579 different register as in the above case. Check all registers
3580 being written instead. */
3581 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3582 VINSN_REG_SETS (EXPR_VINSN (expr))))
3589 #ifdef ENABLE_CHECKING
3590 /* Return true if either of expressions from ORIG_OPS can be blocked
3591 by previously created bookkeeping code. STATIC_PARAMS points to static
3592 parameters of move_op. */
3594 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3597 av_set_iterator iter;
3598 moveop_static_params_p sparams;
3600 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3601 created while scheduling on another fence. */
3602 FOR_EACH_EXPR (expr, iter, orig_ops)
3603 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3606 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3607 sparams = (moveop_static_params_p) static_params;
3609 /* Expressions can be also blocked by bookkeeping created during current
3611 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3612 FOR_EACH_EXPR (expr, iter, orig_ops)
3613 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3616 /* Expressions in ORIG_OPS may have wrong destination register due to
3617 renaming. Check with the right register instead. */
3618 if (sparams->dest && REG_P (sparams->dest))
3620 unsigned regno = REGNO (sparams->dest);
3621 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3623 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn), regno)
3624 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn), regno)
3625 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn), regno))
3633 /* Clear VINSN_VEC and detach vinsns. */
3635 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3637 unsigned len = VEC_length (vinsn_t, *vinsn_vec);
3643 for (n = 0; VEC_iterate (vinsn_t, *vinsn_vec, n, vinsn); n++)
3644 vinsn_detach (vinsn);
3645 VEC_block_remove (vinsn_t, *vinsn_vec, 0, len);
3649 /* Add the vinsn of EXPR to the VINSN_VEC. */
3651 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3653 vinsn_attach (EXPR_VINSN (expr));
3654 VEC_safe_push (vinsn_t, heap, *vinsn_vec, EXPR_VINSN (expr));
3657 /* Free the vector representing blocked expressions. */
3659 vinsn_vec_free (vinsn_vec_t *vinsn_vec)
3662 VEC_free (vinsn_t, heap, *vinsn_vec);
3665 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3667 void sel_add_to_insn_priority (rtx insn, int amount)
3669 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3671 if (sched_verbose >= 2)
3672 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3673 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3674 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3677 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3678 true if there is something to schedule. BNDS and FENCE are current
3679 boundaries and fence, respectively. If we need to stall for some cycles
3680 before an expr from AV would become available, write this number to
3683 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3688 int sched_next_worked = 0, stalled, n;
3689 static int av_max_prio, est_ticks_till_branch;
3690 int min_need_stall = -1;
3691 deps_t dc = BND_DC (BLIST_BND (bnds));
3693 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3694 already scheduled. */
3698 /* Empty vector from the previous stuff. */
3699 if (VEC_length (expr_t, vec_av_set) > 0)
3700 VEC_block_remove (expr_t, vec_av_set, 0, VEC_length (expr_t, vec_av_set));
3702 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3704 gcc_assert (VEC_empty (expr_t, vec_av_set));
3705 FOR_EACH_EXPR (expr, si, av)
3707 VEC_safe_push (expr_t, heap, vec_av_set, expr);
3709 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3711 /* Adjust priority using target backend hook. */
3712 sel_target_adjust_priority (expr);
3715 /* Sort the vector. */
3716 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3717 sizeof (expr_t), sel_rank_for_schedule);
3719 /* We record maximal priority of insns in av set for current instruction
3721 if (FENCE_STARTS_CYCLE_P (fence))
3722 av_max_prio = est_ticks_till_branch = INT_MIN;
3724 /* Filter out inappropriate expressions. Loop's direction is reversed to
3725 visit "best" instructions first. We assume that VEC_unordered_remove
3726 moves last element in place of one being deleted. */
3727 for (n = VEC_length (expr_t, vec_av_set) - 1, stalled = 0; n >= 0; n--)
3729 expr_t expr = VEC_index (expr_t, vec_av_set, n);
3730 insn_t insn = EXPR_INSN_RTX (expr);
3731 char target_available;
3732 bool is_orig_reg_p = true;
3733 int need_cycles, new_prio;
3735 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3736 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3738 VEC_unordered_remove (expr_t, vec_av_set, n);
3742 /* Set number of sched_next insns (just in case there
3743 could be several). */
3744 if (FENCE_SCHED_NEXT (fence))
3745 sched_next_worked++;
3747 /* Check all liveness requirements and try renaming.
3748 FIXME: try to minimize calls to this. */
3749 target_available = EXPR_TARGET_AVAILABLE (expr);
3751 /* If insn was already scheduled on the current fence,
3752 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3753 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr))
3754 target_available = -1;
3756 /* If the availability of the EXPR is invalidated by the insertion of
3757 bookkeeping earlier, make sure that we won't choose this expr for
3758 scheduling if it's not separable, and if it is separable, then
3759 we have to recompute the set of available registers for it. */
3760 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3762 VEC_unordered_remove (expr_t, vec_av_set, n);
3763 if (sched_verbose >= 4)
3764 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3769 if (target_available == true)
3771 /* Do nothing -- we can use an existing register. */
3772 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3774 else if (/* Non-separable instruction will never
3775 get another register. */
3776 (target_available == false
3777 && !EXPR_SEPARABLE_P (expr))
3778 /* Don't try to find a register for low-priority expression. */
3779 || (int) VEC_length (expr_t, vec_av_set) - 1 - n >= max_insns_to_rename
3780 /* ??? FIXME: Don't try to rename data speculation. */
3781 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3782 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3784 VEC_unordered_remove (expr_t, vec_av_set, n);
3785 if (sched_verbose >= 4)
3786 sel_print ("Expr %d has no suitable target register\n",
3791 /* Filter expressions that need to be renamed or speculated when
3792 pipelining, because compensating register copies or speculation
3793 checks are likely to be placed near the beginning of the loop,
3795 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3796 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3798 /* Estimation of number of cycles until loop branch for
3799 renaming/speculation to be successful. */
3800 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3802 if ((int) current_loop_nest->ninsns < 9)
3804 VEC_unordered_remove (expr_t, vec_av_set, n);
3805 if (sched_verbose >= 4)
3806 sel_print ("Pipelining expr %d will likely cause stall\n",
3811 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3812 < need_n_ticks_till_branch * issue_rate / 2
3813 && est_ticks_till_branch < need_n_ticks_till_branch)
3815 VEC_unordered_remove (expr_t, vec_av_set, n);
3816 if (sched_verbose >= 4)
3817 sel_print ("Pipelining expr %d will likely cause stall\n",
3823 /* We want to schedule speculation checks as late as possible. Discard
3824 them from av set if there are instructions with higher priority. */
3825 if (sel_insn_is_speculation_check (insn)
3826 && EXPR_PRIORITY (expr) < av_max_prio)
3829 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3830 VEC_unordered_remove (expr_t, vec_av_set, n);
3831 if (sched_verbose >= 4)
3832 sel_print ("Delaying speculation check %d until its first use\n",
3837 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3838 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3839 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3841 /* Don't allow any insns whose data is not yet ready.
3842 Check first whether we've already tried them and failed. */
3843 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3845 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3846 - FENCE_CYCLE (fence));
3847 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3848 est_ticks_till_branch = MAX (est_ticks_till_branch,
3849 EXPR_PRIORITY (expr) + need_cycles);
3851 if (need_cycles > 0)
3854 min_need_stall = (min_need_stall < 0
3856 : MIN (min_need_stall, need_cycles));
3857 VEC_unordered_remove (expr_t, vec_av_set, n);
3859 if (sched_verbose >= 4)
3860 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3862 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3867 /* Now resort to dependence analysis to find whether EXPR might be
3868 stalled due to dependencies from FENCE's context. */
3869 need_cycles = tick_check_p (expr, dc, fence);
3870 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3872 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3873 est_ticks_till_branch = MAX (est_ticks_till_branch,
3876 if (need_cycles > 0)
3878 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3880 int new_size = INSN_UID (insn) * 3 / 2;
3882 FENCE_READY_TICKS (fence)
3883 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3884 new_size, FENCE_READY_TICKS_SIZE (fence),
3887 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3888 = FENCE_CYCLE (fence) + need_cycles;
3891 min_need_stall = (min_need_stall < 0
3893 : MIN (min_need_stall, need_cycles));
3895 VEC_unordered_remove (expr_t, vec_av_set, n);
3897 if (sched_verbose >= 4)
3898 sel_print ("Expr %d is not ready yet until cycle %d\n",
3900 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3904 if (sched_verbose >= 4)
3905 sel_print ("Expr %d is ok\n", INSN_UID (insn));
3909 /* Clear SCHED_NEXT. */
3910 if (FENCE_SCHED_NEXT (fence))
3912 gcc_assert (sched_next_worked == 1);
3913 FENCE_SCHED_NEXT (fence) = NULL_RTX;
3916 /* No need to stall if this variable was not initialized. */
3917 if (min_need_stall < 0)
3920 if (VEC_empty (expr_t, vec_av_set))
3922 /* We need to set *pneed_stall here, because later we skip this code
3923 when ready list is empty. */
3924 *pneed_stall = min_need_stall;
3928 gcc_assert (min_need_stall == 0);
3930 /* Sort the vector. */
3931 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3932 sizeof (expr_t), sel_rank_for_schedule);
3934 if (sched_verbose >= 4)
3936 sel_print ("Total ready exprs: %d, stalled: %d\n",
3937 VEC_length (expr_t, vec_av_set), stalled);
3938 sel_print ("Sorted av set (%d): ", VEC_length (expr_t, vec_av_set));
3939 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3948 /* Convert a vectored and sorted av set to the ready list that
3949 the rest of the backend wants to see. */
3951 convert_vec_av_set_to_ready (void)
3956 /* Allocate and fill the ready list from the sorted vector. */
3957 ready.n_ready = VEC_length (expr_t, vec_av_set);
3958 ready.first = ready.n_ready - 1;
3960 gcc_assert (ready.n_ready > 0);
3962 if (ready.n_ready > max_issue_size)
3964 max_issue_size = ready.n_ready;
3965 sched_extend_ready_list (ready.n_ready);
3968 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3970 vinsn_t vi = EXPR_VINSN (expr);
3971 insn_t insn = VINSN_INSN_RTX (vi);
3974 ready.vec[n] = insn;
3978 /* Initialize ready list from *AV_PTR for the max_issue () call.
3979 If any unrecognizable insn found in *AV_PTR, return it (and skip
3980 max_issue). BND and FENCE are current boundary and fence,
3981 respectively. If we need to stall for some cycles before an expr
3982 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3984 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
3989 /* We do not support multiple boundaries per fence. */
3990 gcc_assert (BLIST_NEXT (bnds) == NULL);
3992 /* Process expressions required special handling, i.e. pipelined,
3993 speculative and recog() < 0 expressions first. */
3994 process_pipelined_exprs (av_ptr);
3995 process_spec_exprs (av_ptr);
3997 /* A USE could be scheduled immediately. */
3998 expr = process_use_exprs (av_ptr);
4005 /* Turn the av set to a vector for sorting. */
4006 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
4012 /* Build the final ready list. */
4013 convert_vec_av_set_to_ready ();
4017 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4019 sel_dfa_new_cycle (insn_t insn, fence_t fence)
4021 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
4022 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
4023 : FENCE_CYCLE (fence) - 1;
4027 if (!targetm.sched.dfa_new_cycle)
4030 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4032 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
4033 insn, last_scheduled_cycle,
4034 FENCE_CYCLE (fence), &sort_p))
4036 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4037 advance_one_cycle (fence);
4038 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4045 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4046 we can issue. FENCE is the current fence. */
4048 invoke_reorder_hooks (fence_t fence)
4051 bool ran_hook = false;
4053 /* Call the reorder hook at the beginning of the cycle, and call
4054 the reorder2 hook in the middle of the cycle. */
4055 if (FENCE_ISSUED_INSNS (fence) == 0)
4057 if (targetm.sched.reorder
4058 && !SCHED_GROUP_P (ready_element (&ready, 0))
4059 && ready.n_ready > 1)
4061 /* Don't give reorder the most prioritized insn as it can break
4067 = targetm.sched.reorder (sched_dump, sched_verbose,
4068 ready_lastpos (&ready),
4069 &ready.n_ready, FENCE_CYCLE (fence));
4077 /* Initialize can_issue_more for variable_issue. */
4078 issue_more = issue_rate;
4080 else if (targetm.sched.reorder2
4081 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4083 if (ready.n_ready == 1)
4085 targetm.sched.reorder2 (sched_dump, sched_verbose,
4086 ready_lastpos (&ready),
4087 &ready.n_ready, FENCE_CYCLE (fence));
4094 targetm.sched.reorder2 (sched_dump, sched_verbose,
4096 ? ready_lastpos (&ready) : NULL,
4097 &ready.n_ready, FENCE_CYCLE (fence));
4106 issue_more = issue_rate;
4108 /* Ensure that ready list and vec_av_set are in line with each other,
4109 i.e. vec_av_set[i] == ready_element (&ready, i). */
4110 if (issue_more && ran_hook)
4113 rtx *arr = ready.vec;
4114 expr_t *vec = VEC_address (expr_t, vec_av_set);
4116 for (i = 0, n = ready.n_ready; i < n; i++)
4117 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4121 for (j = i; j < n; j++)
4122 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4135 /* Return an EXPR correponding to INDEX element of ready list, if
4136 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4137 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4138 ready.vec otherwise. */
4139 static inline expr_t
4140 find_expr_for_ready (int index, bool follow_ready_element)
4145 real_index = follow_ready_element ? ready.first - index : index;
4147 expr = VEC_index (expr_t, vec_av_set, real_index);
4148 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4153 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4154 of such insns found. */
4156 invoke_dfa_lookahead_guard (void)
4160 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4162 if (sched_verbose >= 2)
4163 sel_print ("ready after reorder: ");
4165 for (i = 0, n = 0; i < ready.n_ready; i++)
4171 /* In this loop insn is Ith element of the ready list given by
4172 ready_element, not Ith element of ready.vec. */
4173 insn = ready_element (&ready, i);
4175 if (! have_hook || i == 0)
4178 r = !targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn);
4180 gcc_assert (INSN_CODE (insn) >= 0);
4182 /* Only insns with ready_try = 0 can get here
4183 from fill_ready_list. */
4184 gcc_assert (ready_try [i] == 0);
4189 expr = find_expr_for_ready (i, true);
4191 if (sched_verbose >= 2)
4193 dump_vinsn (EXPR_VINSN (expr));
4194 sel_print (":%d; ", ready_try[i]);
4198 if (sched_verbose >= 2)
4203 /* Calculate the number of privileged insns and return it. */
4205 calculate_privileged_insns (void)
4207 expr_t cur_expr, min_spec_expr = NULL;
4208 insn_t cur_insn, min_spec_insn;
4209 int privileged_n = 0, i;
4211 for (i = 0; i < ready.n_ready; i++)
4216 if (! min_spec_expr)
4218 min_spec_insn = ready_element (&ready, i);
4219 min_spec_expr = find_expr_for_ready (i, true);
4222 cur_insn = ready_element (&ready, i);
4223 cur_expr = find_expr_for_ready (i, true);
4225 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4231 if (i == ready.n_ready)
4234 if (sched_verbose >= 2)
4235 sel_print ("privileged_n: %d insns with SPEC %d\n",
4236 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4237 return privileged_n;
4240 /* Call the rest of the hooks after the choice was made. Return
4241 the number of insns that still can be issued given that the current
4242 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4243 and the insn chosen for scheduling, respectively. */
4245 invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more)
4247 gcc_assert (INSN_P (best_insn));
4249 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4250 sel_dfa_new_cycle (best_insn, fence);
4252 if (targetm.sched.variable_issue)
4254 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4256 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4258 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4260 else if (GET_CODE (PATTERN (best_insn)) != USE
4261 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4267 /* Estimate the cost of issuing INSN on DFA state STATE. */
4269 estimate_insn_cost (rtx insn, state_t state)
4271 static state_t temp = NULL;
4275 temp = xmalloc (dfa_state_size);
4277 memcpy (temp, state, dfa_state_size);
4278 cost = state_transition (temp, insn);
4287 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4288 This function properly handles ASMs, USEs etc. */
4290 get_expr_cost (expr_t expr, fence_t fence)
4292 rtx insn = EXPR_INSN_RTX (expr);
4294 if (recog_memoized (insn) < 0)
4296 if (!FENCE_STARTS_CYCLE_P (fence)
4297 /* FIXME: Is this condition necessary? */
4298 && VINSN_UNIQUE_P (EXPR_VINSN (expr))
4299 && INSN_ASM_P (insn))
4300 /* This is asm insn which is tryed to be issued on the
4301 cycle not first. Issue it on the next cycle. */
4304 /* A USE insn, or something else we don't need to
4305 understand. We can't pass these directly to
4306 state_transition because it will trigger a
4307 fatal error for unrecognizable insns. */
4311 return estimate_insn_cost (insn, FENCE_STATE (fence));
4314 /* Find the best insn for scheduling, either via max_issue or just take
4315 the most prioritized available. */
4317 choose_best_insn (fence_t fence, int privileged_n, int *index)
4321 if (dfa_lookahead > 0)
4323 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4324 can_issue = max_issue (&ready, privileged_n,
4325 FENCE_STATE (fence), index);
4326 if (sched_verbose >= 2)
4327 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4328 can_issue, FENCE_ISSUED_INSNS (fence));
4332 /* We can't use max_issue; just return the first available element. */
4335 for (i = 0; i < ready.n_ready; i++)
4337 expr_t expr = find_expr_for_ready (i, true);
4339 if (get_expr_cost (expr, fence) < 1)
4341 can_issue = can_issue_more;
4344 if (sched_verbose >= 2)
4345 sel_print ("using %dth insn from the ready list\n", i + 1);
4351 if (i == ready.n_ready)
4361 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4362 BNDS and FENCE are current boundaries and scheduling fence respectively.
4363 Return the expr found and NULL if nothing can be issued atm.
4364 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4366 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4371 /* Choose the best insn for scheduling via:
4372 1) sorting the ready list based on priority;
4373 2) calling the reorder hook;
4374 3) calling max_issue. */
4375 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4376 if (best == NULL && ready.n_ready > 0)
4378 int privileged_n, index, avail_n;
4380 can_issue_more = invoke_reorder_hooks (fence);
4381 if (can_issue_more > 0)
4383 /* Try choosing the best insn until we find one that is could be
4384 scheduled due to liveness restrictions on its destination register.
4385 In the future, we'd like to choose once and then just probe insns
4386 in the order of their priority. */
4387 avail_n = invoke_dfa_lookahead_guard ();
4388 privileged_n = calculate_privileged_insns ();
4389 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4391 best = find_expr_for_ready (index, true);
4393 /* We had some available insns, so if we can't issue them,
4395 if (can_issue_more == 0)
4404 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4406 if (can_issue_more == 0)
4410 if (sched_verbose >= 2)
4414 sel_print ("Best expression (vliw form): ");
4416 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4419 sel_print ("No best expr found!\n");
4426 /* Functions that implement the core of the scheduler. */
4429 /* Emit an instruction from EXPR with SEQNO and VINSN after
4432 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4433 insn_t place_to_insert)
4435 /* This assert fails when we have identical instructions
4436 one of which dominates the other. In this case move_op ()
4437 finds the first instruction and doesn't search for second one.
4438 The solution would be to compute av_set after the first found
4439 insn and, if insn present in that set, continue searching.
4440 For now we workaround this issue in move_op. */
4441 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4443 if (EXPR_WAS_RENAMED (expr))
4445 unsigned regno = expr_dest_regno (expr);
4447 if (HARD_REGISTER_NUM_P (regno))
4449 df_set_regs_ever_live (regno, true);
4450 reg_rename_tick[regno] = ++reg_rename_this_tick;
4454 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4458 /* Return TRUE if BB can hold bookkeeping code. */
4460 block_valid_for_bookkeeping_p (basic_block bb)
4462 insn_t bb_end = BB_END (bb);
4464 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4467 if (INSN_P (bb_end))
4469 if (INSN_SCHED_TIMES (bb_end) > 0)
4473 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4478 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4479 into E2->dest, except from E1->src (there may be a sequence of empty basic
4480 blocks between E1->src and E2->dest). Return found block, or NULL if new
4481 one must be created. If LAX holds, don't assume there is a simple path
4482 from E1->src to E2->dest. */
4484 find_block_for_bookkeeping (edge e1, edge e2, bool lax)
4486 basic_block candidate_block = NULL;
4489 /* Loop over edges from E1 to E2, inclusive. */
4490 for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR; e = EDGE_SUCC (e->dest, 0))
4492 if (EDGE_COUNT (e->dest->preds) == 2)
4494 if (candidate_block == NULL)
4495 candidate_block = (EDGE_PRED (e->dest, 0) == e
4496 ? EDGE_PRED (e->dest, 1)->src
4497 : EDGE_PRED (e->dest, 0)->src);
4499 /* Found additional edge leading to path from e1 to e2
4503 else if (EDGE_COUNT (e->dest->preds) > 2)
4504 /* Several edges leading to path from e1 to e2 from aside. */
4508 return ((!lax || candidate_block)
4509 && block_valid_for_bookkeeping_p (candidate_block)
4513 if (lax && EDGE_COUNT (e->dest->succs) != 1)
4523 /* Create new basic block for bookkeeping code for path(s) incoming into
4524 E2->dest, except from E1->src. Return created block. */
4526 create_block_for_bookkeeping (edge e1, edge e2)
4528 basic_block new_bb, bb = e2->dest;
4530 /* Check that we don't spoil the loop structure. */
4531 if (current_loop_nest)
4533 basic_block latch = current_loop_nest->latch;
4535 /* We do not split header. */
4536 gcc_assert (e2->dest != current_loop_nest->header);
4538 /* We do not redirect the only edge to the latch block. */
4539 gcc_assert (e1->dest != latch
4540 || !single_pred_p (latch)
4541 || e1 != single_pred_edge (latch));
4544 /* Split BB to insert BOOK_INSN there. */
4545 new_bb = sched_split_block (bb, NULL);
4547 /* Move note_list from the upper bb. */
4548 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4549 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4550 BB_NOTE_LIST (bb) = NULL_RTX;
4552 gcc_assert (e2->dest == bb);
4554 /* Skip block for bookkeeping copy when leaving E1->src. */
4555 if (e1->flags & EDGE_FALLTHRU)
4556 sel_redirect_edge_and_branch_force (e1, new_bb);
4558 sel_redirect_edge_and_branch (e1, new_bb);
4560 gcc_assert (e1->dest == new_bb);
4561 gcc_assert (sel_bb_empty_p (bb));
4563 /* To keep basic block numbers in sync between debug and non-debug
4564 compilations, we have to rotate blocks here. Consider that we
4565 started from (a,b)->d, (c,d)->e, and d contained only debug
4566 insns. It would have been removed before if the debug insns
4567 weren't there, so we'd have split e rather than d. So what we do
4568 now is to swap the block numbers of new_bb and
4569 single_succ(new_bb) == e, so that the insns that were in e before
4570 get the new block number. */
4572 if (MAY_HAVE_DEBUG_INSNS)
4575 insn_t insn = sel_bb_head (new_bb);
4578 if (DEBUG_INSN_P (insn)
4579 && single_succ_p (new_bb)
4580 && (succ = single_succ (new_bb))
4581 && succ != EXIT_BLOCK_PTR
4582 && DEBUG_INSN_P ((last = sel_bb_end (new_bb))))
4584 while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4585 insn = NEXT_INSN (insn);
4589 sel_global_bb_info_def gbi;
4590 sel_region_bb_info_def rbi;
4593 if (sched_verbose >= 2)
4594 sel_print ("Swapping block ids %i and %i\n",
4595 new_bb->index, succ->index);
4598 new_bb->index = succ->index;
4601 SET_BASIC_BLOCK (new_bb->index, new_bb);
4602 SET_BASIC_BLOCK (succ->index, succ);
4604 memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi));
4605 memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ),
4607 memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi));
4609 memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi));
4610 memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ),
4612 memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi));
4614 i = BLOCK_TO_BB (new_bb->index);
4615 BLOCK_TO_BB (new_bb->index) = BLOCK_TO_BB (succ->index);
4616 BLOCK_TO_BB (succ->index) = i;
4618 i = CONTAINING_RGN (new_bb->index);
4619 CONTAINING_RGN (new_bb->index) = CONTAINING_RGN (succ->index);
4620 CONTAINING_RGN (succ->index) = i;
4622 for (i = 0; i < current_nr_blocks; i++)
4623 if (BB_TO_BLOCK (i) == succ->index)
4624 BB_TO_BLOCK (i) = new_bb->index;
4625 else if (BB_TO_BLOCK (i) == new_bb->index)
4626 BB_TO_BLOCK (i) = succ->index;
4628 FOR_BB_INSNS (new_bb, insn)
4630 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index;
4632 FOR_BB_INSNS (succ, insn)
4634 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index;
4636 if (bitmap_bit_p (code_motion_visited_blocks, new_bb->index))
4638 bitmap_set_bit (code_motion_visited_blocks, succ->index);
4639 bitmap_clear_bit (code_motion_visited_blocks, new_bb->index);
4642 gcc_assert (LABEL_P (BB_HEAD (new_bb))
4643 && LABEL_P (BB_HEAD (succ)));
4645 if (sched_verbose >= 4)
4646 sel_print ("Swapping code labels %i and %i\n",
4647 CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4648 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4650 i = CODE_LABEL_NUMBER (BB_HEAD (new_bb));
4651 CODE_LABEL_NUMBER (BB_HEAD (new_bb))
4652 = CODE_LABEL_NUMBER (BB_HEAD (succ));
4653 CODE_LABEL_NUMBER (BB_HEAD (succ)) = i;
4661 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4662 into E2->dest, except from E1->src. */
4664 find_place_for_bookkeeping (edge e1, edge e2)
4666 insn_t place_to_insert;
4667 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4668 create new basic block, but insert bookkeeping there. */
4669 basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE);
4673 place_to_insert = BB_END (book_block);
4675 /* Don't use a block containing only debug insns for
4676 bookkeeping, this causes scheduling differences between debug
4677 and non-debug compilations, for the block would have been
4679 if (DEBUG_INSN_P (place_to_insert))
4681 rtx insn = sel_bb_head (book_block);
4683 while (insn != place_to_insert &&
4684 (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4685 insn = NEXT_INSN (insn);
4687 if (insn == place_to_insert)
4694 book_block = create_block_for_bookkeeping (e1, e2);
4695 place_to_insert = BB_END (book_block);
4696 if (sched_verbose >= 9)
4697 sel_print ("New block is %i, split from bookkeeping block %i\n",
4698 EDGE_SUCC (book_block, 0)->dest->index, book_block->index);
4702 if (sched_verbose >= 9)
4703 sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index);
4706 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4707 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4708 place_to_insert = PREV_INSN (place_to_insert);
4710 return place_to_insert;
4713 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4716 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4721 /* Check if we are about to insert bookkeeping copy before a jump, and use
4722 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4723 next = NEXT_INSN (place_to_insert);
4726 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4728 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4729 seqno = INSN_SEQNO (next);
4731 else if (INSN_SEQNO (join_point) > 0)
4732 seqno = INSN_SEQNO (join_point);
4735 seqno = get_seqno_by_preds (place_to_insert);
4737 /* Sometimes the fences can move in such a way that there will be
4738 no instructions with positive seqno around this bookkeeping.
4739 This means that there will be no way to get to it by a regular
4740 fence movement. Never mind because we pick up such pieces for
4741 rescheduling anyways, so any positive value will do for now. */
4744 gcc_assert (pipelining_p);
4749 gcc_assert (seqno > 0);
4753 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4754 NEW_SEQNO to it. Return created insn. */
4756 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4758 rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4761 = create_vinsn_from_insn_rtx (new_insn_rtx,
4762 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4764 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4767 INSN_SCHED_TIMES (new_insn) = 0;
4768 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4773 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4774 E2->dest, except from E1->src (there may be a sequence of empty blocks
4775 between E1->src and E2->dest). Return block containing the copy.
4776 All scheduler data is initialized for the newly created insn. */
4778 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4780 insn_t join_point, place_to_insert, new_insn;
4782 bool need_to_exchange_data_sets;
4784 if (sched_verbose >= 4)
4785 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4788 join_point = sel_bb_head (e2->dest);
4789 place_to_insert = find_place_for_bookkeeping (e1, e2);
4790 if (!place_to_insert)
4792 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4793 need_to_exchange_data_sets
4794 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4796 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4798 /* When inserting bookkeeping insn in new block, av sets should be
4799 following: old basic block (that now holds bookkeeping) data sets are
4800 the same as was before generation of bookkeeping, and new basic block
4801 (that now hold all other insns of old basic block) data sets are
4802 invalid. So exchange data sets for these basic blocks as sel_split_block
4803 mistakenly exchanges them in this case. Cannot do it earlier because
4804 when single instruction is added to new basic block it should hold NULL
4806 if (need_to_exchange_data_sets)
4807 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4808 BLOCK_FOR_INSN (join_point));
4810 stat_bookkeeping_copies++;
4811 return BLOCK_FOR_INSN (new_insn);
4814 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4815 on FENCE, but we are unable to copy them. */
4817 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4822 /* An expression does not need bookkeeping if it is available on all paths
4823 from current block to original block and current block dominates
4824 original block. We check availability on all paths by examining
4825 EXPR_SPEC; this is not equivalent, because it may be positive even
4826 if expr is available on all paths (but if expr is not available on
4827 any path, EXPR_SPEC will be positive). */
4829 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4831 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4832 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4833 && (EXPR_SPEC (expr)
4834 || !EXPR_ORIG_BB_INDEX (expr)
4835 || !dominated_by_p (CDI_DOMINATORS,
4836 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr)),
4837 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4839 if (sched_verbose >= 4)
4840 sel_print ("Expr %d removed because it would need bookkeeping, which "
4841 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4842 av_set_iter_remove (&i);
4847 /* Moving conditional jump through some instructions.
4851 ... <- current scheduling point
4852 NOTE BASIC BLOCK: <- bb header
4853 (p8) add r14=r14+0x9;;
4859 We can schedule jump one cycle earlier, than mov, because they cannot be
4860 executed together as their predicates are mutually exclusive.
4862 This is done in this way: first, new fallthrough basic block is created
4863 after jump (it is always can be done, because there already should be a
4864 fallthrough block, where control flow goes in case of predicate being true -
4865 in our example; otherwise there should be a dependence between those
4866 instructions and jump and we cannot schedule jump right now);
4867 next, all instructions between jump and current scheduling point are moved
4868 to this new block. And the result is this:
4871 (!p8) jump L1 <- current scheduling point
4872 NOTE BASIC BLOCK: <- bb header
4873 (p8) add r14=r14+0x9;;
4879 move_cond_jump (rtx insn, bnd_t bnd)
4882 basic_block block_from, block_next, block_new;
4883 rtx next, prev, link;
4885 /* BLOCK_FROM holds basic block of the jump. */
4886 block_from = BLOCK_FOR_INSN (insn);
4888 /* Moving of jump should not cross any other jumps or
4889 beginnings of new basic blocks. */
4890 gcc_assert (block_from == BLOCK_FOR_INSN (BND_TO (bnd)));
4892 /* Jump is moved to the boundary. */
4893 prev = BND_TO (bnd);
4894 next = PREV_INSN (insn);
4895 BND_TO (bnd) = insn;
4897 ft_edge = find_fallthru_edge (block_from);
4898 block_next = ft_edge->dest;
4899 /* There must be a fallthrough block (or where should go
4900 control flow in case of false jump predicate otherwise?). */
4901 gcc_assert (block_next);
4903 /* Create new empty basic block after source block. */
4904 block_new = sel_split_edge (ft_edge);
4905 gcc_assert (block_new->next_bb == block_next
4906 && block_from->next_bb == block_new);
4908 gcc_assert (BB_END (block_from) == insn);
4910 /* Move all instructions except INSN from BLOCK_FROM to
4912 for (link = prev; link != insn; link = NEXT_INSN (link))
4914 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
4915 df_insn_change_bb (link, block_new);
4918 /* Set correct basic block and instructions properties. */
4919 BB_END (block_new) = PREV_INSN (insn);
4921 NEXT_INSN (PREV_INSN (prev)) = insn;
4922 PREV_INSN (insn) = PREV_INSN (prev);
4924 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4925 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
4926 PREV_INSN (prev) = BB_HEAD (block_new);
4927 NEXT_INSN (next) = NEXT_INSN (BB_HEAD (block_new));
4928 NEXT_INSN (BB_HEAD (block_new)) = prev;
4929 PREV_INSN (NEXT_INSN (next)) = next;
4931 gcc_assert (!sel_bb_empty_p (block_from)
4932 && !sel_bb_empty_p (block_new));
4934 /* Update data sets for BLOCK_NEW to represent that INSN and
4935 instructions from the other branch of INSN is no longer
4936 available at BLOCK_NEW. */
4937 BB_AV_LEVEL (block_new) = global_level;
4938 gcc_assert (BB_LV_SET (block_new) == NULL);
4939 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
4940 update_data_sets (sel_bb_head (block_new));
4942 /* INSN is a new basic block header - so prepare its data
4943 structures and update availability and liveness sets. */
4944 update_data_sets (insn);
4946 if (sched_verbose >= 4)
4947 sel_print ("Moving jump %d\n", INSN_UID (insn));
4950 /* Remove nops generated during move_op for preventing removal of empty
4953 remove_temp_moveop_nops (bool full_tidying)
4958 for (i = 0; VEC_iterate (insn_t, vec_temp_moveop_nops, i, insn); i++)
4960 gcc_assert (INSN_NOP_P (insn));
4961 return_nop_to_pool (insn, full_tidying);
4964 /* Empty the vector. */
4965 if (VEC_length (insn_t, vec_temp_moveop_nops) > 0)
4966 VEC_block_remove (insn_t, vec_temp_moveop_nops, 0,
4967 VEC_length (insn_t, vec_temp_moveop_nops));
4970 /* Records the maximal UID before moving up an instruction. Used for
4971 distinguishing between bookkeeping copies and original insns. */
4972 static int max_uid_before_move_op = 0;
4974 /* Remove from AV_VLIW_P all instructions but next when debug counter
4975 tells us so. Next instruction is fetched from BNDS. */
4977 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
4979 if (! dbg_cnt (sel_sched_insn_cnt))
4980 /* Leave only the next insn in av_vliw. */
4982 av_set_iterator av_it;
4984 bnd_t bnd = BLIST_BND (bnds);
4985 insn_t next = BND_TO (bnd);
4987 gcc_assert (BLIST_NEXT (bnds) == NULL);
4989 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
4990 if (EXPR_INSN_RTX (expr) != next)
4991 av_set_iter_remove (&av_it);
4995 /* Compute available instructions on BNDS. FENCE is the current fence. Write
4996 the computed set to *AV_VLIW_P. */
4998 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
5000 if (sched_verbose >= 2)
5002 sel_print ("Boundaries: ");
5007 for (; bnds; bnds = BLIST_NEXT (bnds))
5009 bnd_t bnd = BLIST_BND (bnds);
5011 insn_t bnd_to = BND_TO (bnd);
5013 /* Rewind BND->TO to the basic block header in case some bookkeeping
5014 instructions were inserted before BND->TO and it needs to be
5016 if (sel_bb_head_p (bnd_to))
5017 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
5019 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
5021 bnd_to = PREV_INSN (bnd_to);
5022 if (sel_bb_head_p (bnd_to))
5026 if (BND_TO (bnd) != bnd_to)
5028 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
5029 FENCE_INSN (fence) = bnd_to;
5030 BND_TO (bnd) = bnd_to;
5033 av_set_clear (&BND_AV (bnd));
5034 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
5036 av_set_clear (&BND_AV1 (bnd));
5037 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
5039 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
5041 av1_copy = av_set_copy (BND_AV1 (bnd));
5042 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
5045 if (sched_verbose >= 2)
5047 sel_print ("Available exprs (vliw form): ");
5048 dump_av_set (*av_vliw_p);
5053 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5054 expression. When FOR_MOVEOP is true, also replace the register of
5055 expressions found with the register from EXPR_VLIW. */
5057 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
5059 av_set_t expr_seq = NULL;
5063 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
5065 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
5069 /* The sequential expression has the right form to pass
5070 to move_op except when renaming happened. Put the
5071 correct register in EXPR then. */
5072 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
5074 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
5076 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
5077 stat_renamed_scheduled++;
5079 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5080 This is needed when renaming came up with original
5082 else if (EXPR_TARGET_AVAILABLE (expr)
5083 != EXPR_TARGET_AVAILABLE (expr_vliw))
5085 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
5086 EXPR_TARGET_AVAILABLE (expr) = 1;
5089 if (EXPR_WAS_SUBSTITUTED (expr))
5090 stat_substitutions_total++;
5093 av_set_add (&expr_seq, expr);
5095 /* With substitution inside insn group, it is possible
5096 that more than one expression in expr_seq will correspond
5097 to expr_vliw. In this case, choose one as the attempt to
5098 move both leads to miscompiles. */
5103 if (for_moveop && sched_verbose >= 2)
5105 sel_print ("Best expression(s) (sequential form): ");
5106 dump_av_set (expr_seq);
5114 /* Move nop to previous block. */
5115 static void ATTRIBUTE_UNUSED
5116 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
5118 insn_t prev_insn, next_insn, note;
5120 gcc_assert (sel_bb_head_p (nop)
5121 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
5122 note = bb_note (BLOCK_FOR_INSN (nop));
5123 prev_insn = sel_bb_end (prev_bb);
5124 next_insn = NEXT_INSN (nop);
5125 gcc_assert (prev_insn != NULL_RTX
5126 && PREV_INSN (note) == prev_insn);
5128 NEXT_INSN (prev_insn) = nop;
5129 PREV_INSN (nop) = prev_insn;
5131 PREV_INSN (note) = nop;
5132 NEXT_INSN (note) = next_insn;
5134 NEXT_INSN (nop) = note;
5135 PREV_INSN (next_insn) = note;
5137 BB_END (prev_bb) = nop;
5138 BLOCK_FOR_INSN (nop) = prev_bb;
5141 /* Prepare a place to insert the chosen expression on BND. */
5143 prepare_place_to_insert (bnd_t bnd)
5145 insn_t place_to_insert;
5147 /* Init place_to_insert before calling move_op, as the later
5148 can possibly remove BND_TO (bnd). */
5149 if (/* If this is not the first insn scheduled. */
5152 /* Add it after last scheduled. */
5153 place_to_insert = ILIST_INSN (BND_PTR (bnd));
5154 if (DEBUG_INSN_P (place_to_insert))
5156 ilist_t l = BND_PTR (bnd);
5157 while ((l = ILIST_NEXT (l)) &&
5158 DEBUG_INSN_P (ILIST_INSN (l)))
5161 place_to_insert = NULL;
5165 place_to_insert = NULL;
5167 if (!place_to_insert)
5169 /* Add it before BND_TO. The difference is in the
5170 basic block, where INSN will be added. */
5171 place_to_insert = get_nop_from_pool (BND_TO (bnd));
5172 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
5173 == BLOCK_FOR_INSN (BND_TO (bnd)));
5176 return place_to_insert;
5179 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5180 Return the expression to emit in C_EXPR. */
5182 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5183 av_set_t expr_seq, expr_t c_expr)
5185 bool b, should_move;
5188 int n_bookkeeping_copies_before_moveop;
5190 /* Make a move. This call will remove the original operation,
5191 insert all necessary bookkeeping instructions and update the
5192 data sets. After that all we have to do is add the operation
5193 at before BND_TO (BND). */
5194 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5195 max_uid_before_move_op = get_max_uid ();
5196 bitmap_clear (current_copies);
5197 bitmap_clear (current_originators);
5199 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5200 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5202 /* We should be able to find the expression we've chosen for
5206 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5207 stat_insns_needed_bookkeeping++;
5209 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5211 /* We allocate these bitmaps lazily. */
5212 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5213 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5215 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5216 current_originators);
5223 /* Debug a DFA state as an array of bytes. */
5225 debug_state (state_t state)
5228 unsigned int i, size = dfa_state_size;
5230 sel_print ("state (%u):", size);
5231 for (i = 0, p = (unsigned char *) state; i < size; i++)
5232 sel_print (" %d", p[i]);
5236 /* Advance state on FENCE with INSN. Return true if INSN is
5237 an ASM, and we should advance state once more. */
5239 advance_state_on_fence (fence_t fence, insn_t insn)
5243 if (recog_memoized (insn) >= 0)
5246 state_t temp_state = alloca (dfa_state_size);
5248 gcc_assert (!INSN_ASM_P (insn));
5251 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5252 res = state_transition (FENCE_STATE (fence), insn);
5253 gcc_assert (res < 0);
5255 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5257 FENCE_ISSUED_INSNS (fence)++;
5259 /* We should never issue more than issue_rate insns. */
5260 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5266 /* This could be an ASM insn which we'd like to schedule
5267 on the next cycle. */
5268 asm_p = INSN_ASM_P (insn);
5269 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5270 advance_one_cycle (fence);
5273 if (sched_verbose >= 2)
5274 debug_state (FENCE_STATE (fence));
5275 if (!DEBUG_INSN_P (insn))
5276 FENCE_STARTS_CYCLE_P (fence) = 0;
5280 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5281 is nonzero if we need to stall after issuing INSN. */
5283 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5287 /* First, reflect that something is scheduled on this fence. */
5288 asm_p = advance_state_on_fence (fence, insn);
5289 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5290 VEC_safe_push (rtx, gc, FENCE_EXECUTING_INSNS (fence), insn);
5291 if (SCHED_GROUP_P (insn))
5293 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5294 SCHED_GROUP_P (insn) = 0;
5297 FENCE_SCHED_NEXT (fence) = NULL_RTX;
5298 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5299 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5301 /* Set instruction scheduling info. This will be used in bundling,
5302 pipelining, tick computations etc. */
5303 ++INSN_SCHED_TIMES (insn);
5304 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5305 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5306 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5307 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5309 /* This does not account for adjust_cost hooks, just add the biggest
5310 constant the hook may add to the latency. TODO: make this
5311 a target dependent constant. */
5312 INSN_READY_CYCLE (insn)
5313 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5315 : maximal_insn_latency (insn) + 1);
5317 /* Change these fields last, as they're used above. */
5318 FENCE_AFTER_STALL_P (fence) = 0;
5319 if (asm_p || need_stall)
5320 advance_one_cycle (fence);
5322 /* Indicate that we've scheduled something on this fence. */
5323 FENCE_SCHEDULED_P (fence) = true;
5324 scheduled_something_on_previous_fence = true;
5326 /* Print debug information when insn's fields are updated. */
5327 if (sched_verbose >= 2)
5329 sel_print ("Scheduling insn: ");
5330 dump_insn_1 (insn, 1);
5335 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5336 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5339 update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp,
5340 blist_t *bnds_tailp)
5345 advance_deps_context (BND_DC (bnd), insn);
5346 FOR_EACH_SUCC_1 (succ, si, insn,
5347 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5349 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5351 ilist_add (&ptr, insn);
5353 if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn)
5354 && is_ineligible_successor (succ, ptr))
5360 if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn))
5362 if (sched_verbose >= 9)
5363 sel_print ("Updating fence insn from %i to %i\n",
5364 INSN_UID (insn), INSN_UID (succ));
5365 FENCE_INSN (fence) = succ;
5367 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5368 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5371 blist_remove (bndsp);
5375 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5377 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5380 expr_t c_expr = XALLOCA (expr_def);
5381 insn_t place_to_insert;
5385 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5387 /* In case of scheduling a jump skipping some other instructions,
5388 prepare CFG. After this, jump is at the boundary and can be
5389 scheduled as usual insn by MOVE_OP. */
5390 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5392 insn = EXPR_INSN_RTX (expr_vliw);
5394 /* Speculative jumps are not handled. */
5395 if (insn != BND_TO (bnd)
5396 && !sel_insn_is_speculation_check (insn))
5397 move_cond_jump (insn, bnd);
5400 /* Find a place for C_EXPR to schedule. */
5401 place_to_insert = prepare_place_to_insert (bnd);
5402 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5403 clear_expr (c_expr);
5405 /* Add the instruction. The corner case to care about is when
5406 the expr_seq set has more than one expr, and we chose the one that
5407 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5408 we can't use it. Generate the new vinsn. */
5409 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5413 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5414 change_vinsn_in_expr (expr_vliw, vinsn_new);
5415 should_move = false;
5418 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5420 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5423 /* Return the nops generated for preserving of data sets back
5425 if (INSN_NOP_P (place_to_insert))
5426 return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn));
5427 remove_temp_moveop_nops (!DEBUG_INSN_P (insn));
5429 av_set_clear (&expr_seq);
5431 /* Save the expression scheduled so to reset target availability if we'll
5432 meet it later on the same fence. */
5433 if (EXPR_WAS_RENAMED (expr_vliw))
5434 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5436 /* Check that the recent movement didn't destroyed loop
5438 gcc_assert (!pipelining_p
5439 || current_loop_nest == NULL
5440 || loop_latch_edge (current_loop_nest));
5444 /* Stall for N cycles on FENCE. */
5446 stall_for_cycles (fence_t fence, int n)
5450 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5452 advance_one_cycle (fence);
5454 FENCE_AFTER_STALL_P (fence) = 1;
5457 /* Gather a parallel group of insns at FENCE and assign their seqno
5458 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5459 list for later recalculation of seqnos. */
5461 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5463 blist_t bnds = NULL, *bnds_tailp;
5464 av_set_t av_vliw = NULL;
5465 insn_t insn = FENCE_INSN (fence);
5467 if (sched_verbose >= 2)
5468 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5469 INSN_UID (insn), FENCE_CYCLE (fence));
5471 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5472 bnds_tailp = &BLIST_NEXT (bnds);
5473 set_target_context (FENCE_TC (fence));
5474 target_bb = INSN_BB (insn);
5476 /* Do while we can add any operation to the current group. */
5479 blist_t *bnds_tailp1, *bndsp;
5482 int was_stall = 0, scheduled_insns = 0, stall_iterations = 0;
5483 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5484 int max_stall = pipelining_p ? 1 : 3;
5485 bool last_insn_was_debug = false;
5486 bool was_debug_bb_end_p = false;
5488 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5489 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5490 remove_insns_for_debug (bnds, &av_vliw);
5492 /* Return early if we have nothing to schedule. */
5493 if (av_vliw == NULL)
5496 /* Choose the best expression and, if needed, destination register
5500 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5501 if (!expr_vliw && need_stall)
5503 /* All expressions required a stall. Do not recompute av sets
5504 as we'll get the same answer (modulo the insns between
5505 the fence and its boundary, which will not be available for
5507 gcc_assert (! expr_vliw && stall_iterations < 2);
5509 /* If we are going to stall for too long, break to recompute av
5510 sets and bring more insns for pipelining. */
5511 if (need_stall <= 3)
5512 stall_for_cycles (fence, need_stall);
5515 stall_for_cycles (fence, 1);
5520 while (! expr_vliw && need_stall);
5522 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5525 av_set_clear (&av_vliw);
5530 bnds_tailp1 = bnds_tailp;
5533 /* This code will be executed only once until we'd have several
5534 boundaries per fence. */
5536 bnd_t bnd = BLIST_BND (*bndsp);
5538 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5540 bndsp = &BLIST_NEXT (*bndsp);
5544 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5545 last_insn_was_debug = DEBUG_INSN_P (insn);
5546 if (last_insn_was_debug)
5547 was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn));
5548 update_fence_and_insn (fence, insn, need_stall);
5549 bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp);
5551 /* Add insn to the list of scheduled on this cycle instructions. */
5552 ilist_add (*scheduled_insns_tailpp, insn);
5553 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5555 while (*bndsp != *bnds_tailp1);
5557 av_set_clear (&av_vliw);
5558 if (!last_insn_was_debug)
5561 /* We currently support information about candidate blocks only for
5562 one 'target_bb' block. Hence we can't schedule after jump insn,
5563 as this will bring two boundaries and, hence, necessity to handle
5564 information for two or more blocks concurrently. */
5565 if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn))
5567 && (was_stall >= max_stall
5568 || scheduled_insns >= max_insns)))
5573 gcc_assert (!FENCE_BNDS (fence));
5575 /* Update boundaries of the FENCE. */
5578 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5582 insn = ILIST_INSN (ptr);
5584 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5585 ilist_add (&FENCE_BNDS (fence), insn);
5588 blist_remove (&bnds);
5591 /* Update target context on the fence. */
5592 reset_target_context (FENCE_TC (fence), false);
5595 /* All exprs in ORIG_OPS must have the same destination register or memory.
5596 Return that destination. */
5598 get_dest_from_orig_ops (av_set_t orig_ops)
5600 rtx dest = NULL_RTX;
5601 av_set_iterator av_it;
5603 bool first_p = true;
5605 FOR_EACH_EXPR (expr, av_it, orig_ops)
5607 rtx x = EXPR_LHS (expr);
5615 gcc_assert (dest == x
5616 || (dest != NULL_RTX && x != NULL_RTX
5617 && rtx_equal_p (dest, x)));
5623 /* Update data sets for the bookkeeping block and record those expressions
5624 which become no longer available after inserting this bookkeeping. */
5626 update_and_record_unavailable_insns (basic_block book_block)
5629 av_set_t old_av_set = NULL;
5631 rtx bb_end = sel_bb_end (book_block);
5633 /* First, get correct liveness in the bookkeeping block. The problem is
5634 the range between the bookeeping insn and the end of block. */
5635 update_liveness_on_insn (bb_end);
5636 if (control_flow_insn_p (bb_end))
5637 update_liveness_on_insn (PREV_INSN (bb_end));
5639 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5640 fence above, where we may choose to schedule an insn which is
5641 actually blocked from moving up with the bookkeeping we create here. */
5642 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5644 old_av_set = av_set_copy (BB_AV_SET (book_block));
5645 update_data_sets (sel_bb_head (book_block));
5647 /* Traverse all the expressions in the old av_set and check whether
5648 CUR_EXPR is in new AV_SET. */
5649 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5651 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5652 EXPR_VINSN (cur_expr));
5655 /* In this case, we can just turn off the E_T_A bit, but we can't
5656 represent this information with the current vector. */
5657 || EXPR_TARGET_AVAILABLE (new_expr)
5658 != EXPR_TARGET_AVAILABLE (cur_expr))
5659 /* Unfortunately, the below code could be also fired up on
5661 FIXME: add an example of how this could happen. */
5662 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5665 av_set_clear (&old_av_set);
5669 /* The main effect of this function is that sparams->c_expr is merged
5670 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5671 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5672 lparams->c_expr_merged is copied back to sparams->c_expr after all
5673 successors has been traversed. lparams->c_expr_local is an expr allocated
5674 on stack in the caller function, and is used if there is more than one
5677 SUCC is one of the SUCCS_NORMAL successors of INSN,
5678 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5679 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5681 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5682 insn_t succ ATTRIBUTE_UNUSED,
5683 int moveop_drv_call_res,
5684 cmpd_local_params_p lparams, void *static_params)
5686 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5688 /* Nothing to do, if original expr wasn't found below. */
5689 if (moveop_drv_call_res != 1)
5692 /* If this is a first successor. */
5693 if (!lparams->c_expr_merged)
5695 lparams->c_expr_merged = sparams->c_expr;
5696 sparams->c_expr = lparams->c_expr_local;
5700 /* We must merge all found expressions to get reasonable
5701 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5702 do so then we can first find the expr with epsilon
5703 speculation success probability and only then with the
5704 good probability. As a result the insn will get epsilon
5705 probability and will never be scheduled because of
5706 weakness_cutoff in find_best_expr.
5708 We call merge_expr_data here instead of merge_expr
5709 because due to speculation C_EXPR and X may have the
5710 same insns with different speculation types. And as of
5711 now such insns are considered non-equal.
5713 However, EXPR_SCHED_TIMES is different -- we must get
5714 SCHED_TIMES from a real insn, not a bookkeeping copy.
5715 We force this here. Instead, we may consider merging
5716 SCHED_TIMES to the maximum instead of minimum in the
5718 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5720 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5721 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5722 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5724 clear_expr (sparams->c_expr);
5728 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5730 SUCC is one of the SUCCS_NORMAL successors of INSN,
5731 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5732 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5733 STATIC_PARAMS contain USED_REGS set. */
5735 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5736 int moveop_drv_call_res,
5737 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5738 void *static_params)
5741 fur_static_params_p sparams = (fur_static_params_p) static_params;
5743 /* Here we compute live regsets only for branches that do not lie
5744 on the code motion paths. These branches correspond to value
5745 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5746 for such branches code_motion_path_driver is not called. */
5747 if (moveop_drv_call_res != 0)
5750 /* Mark all registers that do not meet the following condition:
5751 (3) not live on the other path of any conditional branch
5752 that is passed by the operation, in case original
5753 operations are not present on both paths of the
5754 conditional branch. */
5755 succ_live = compute_live (succ);
5756 IOR_REG_SET (sparams->used_regs, succ_live);
5759 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5762 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5764 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5766 sp->c_expr = lp->c_expr_merged;
5769 /* Track bookkeeping copies created, insns scheduled, and blocks for
5770 rescheduling when INSN is found by move_op. */
5772 track_scheduled_insns_and_blocks (rtx insn)
5774 /* Even if this insn can be a copy that will be removed during current move_op,
5775 we still need to count it as an originator. */
5776 bitmap_set_bit (current_originators, INSN_UID (insn));
5778 if (!bitmap_bit_p (current_copies, INSN_UID (insn)))
5780 /* Note that original block needs to be rescheduled, as we pulled an
5781 instruction out of it. */
5782 if (INSN_SCHED_TIMES (insn) > 0)
5783 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5784 else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn))
5785 num_insns_scheduled++;
5788 bitmap_clear_bit (current_copies, INSN_UID (insn));
5790 /* For instructions we must immediately remove insn from the
5791 stream, so subsequent update_data_sets () won't include this
5793 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5794 if (INSN_UID (insn) > max_uid_before_move_op)
5795 stat_bookkeeping_copies--;
5798 /* Emit a register-register copy for INSN if needed. Return true if
5799 emitted one. PARAMS is the move_op static parameters. */
5801 maybe_emit_renaming_copy (rtx insn,
5802 moveop_static_params_p params)
5804 bool insn_emitted = false;
5805 rtx cur_reg = expr_dest_reg (params->c_expr);
5807 gcc_assert (!cur_reg || (params->dest && REG_P (params->dest)));
5809 /* If original operation has expr and the register chosen for
5810 that expr is not original operation's dest reg, substitute
5811 operation's right hand side with the register chosen. */
5812 if (cur_reg != NULL_RTX && REGNO (params->dest) != REGNO (cur_reg))
5814 insn_t reg_move_insn, reg_move_insn_rtx;
5816 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5818 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5822 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5823 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5825 insn_emitted = true;
5826 params->was_renamed = true;
5829 return insn_emitted;
5832 /* Emit a speculative check for INSN speculated as EXPR if needed.
5833 Return true if we've emitted one. PARAMS is the move_op static
5836 maybe_emit_speculative_check (rtx insn, expr_t expr,
5837 moveop_static_params_p params)
5839 bool insn_emitted = false;
5843 check_ds = get_spec_check_type_for_insn (insn, expr);
5846 /* A speculation check should be inserted. */
5847 x = create_speculation_check (params->c_expr, check_ds, insn);
5848 insn_emitted = true;
5852 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5856 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5857 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5858 return insn_emitted;
5861 /* Handle transformations that leave an insn in place of original
5862 insn such as renaming/speculation. Return true if one of such
5863 transformations actually happened, and we have emitted this insn. */
5865 handle_emitting_transformations (rtx insn, expr_t expr,
5866 moveop_static_params_p params)
5868 bool insn_emitted = false;
5870 insn_emitted = maybe_emit_renaming_copy (insn, params);
5871 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5873 return insn_emitted;
5876 /* If INSN is the only insn in the basic block (not counting JUMP,
5877 which may be a jump to next insn, and DEBUG_INSNs), we want to
5878 leave a NOP there till the return to fill_insns. */
5881 need_nop_to_preserve_insn_bb (rtx insn)
5883 insn_t bb_head, bb_end, bb_next, in_next;
5884 basic_block bb = BLOCK_FOR_INSN (insn);
5886 bb_head = sel_bb_head (bb);
5887 bb_end = sel_bb_end (bb);
5889 if (bb_head == bb_end)
5892 while (bb_head != bb_end && DEBUG_INSN_P (bb_head))
5893 bb_head = NEXT_INSN (bb_head);
5895 if (bb_head == bb_end)
5898 while (bb_head != bb_end && DEBUG_INSN_P (bb_end))
5899 bb_end = PREV_INSN (bb_end);
5901 if (bb_head == bb_end)
5904 bb_next = NEXT_INSN (bb_head);
5905 while (bb_next != bb_end && DEBUG_INSN_P (bb_next))
5906 bb_next = NEXT_INSN (bb_next);
5908 if (bb_next == bb_end && JUMP_P (bb_end))
5911 in_next = NEXT_INSN (insn);
5912 while (DEBUG_INSN_P (in_next))
5913 in_next = NEXT_INSN (in_next);
5915 if (IN_CURRENT_FENCE_P (in_next))
5921 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5922 is not removed but reused when INSN is re-emitted. */
5924 remove_insn_from_stream (rtx insn, bool only_disconnect)
5926 /* If there's only one insn in the BB, make sure that a nop is
5927 inserted into it, so the basic block won't disappear when we'll
5928 delete INSN below with sel_remove_insn. It should also survive
5929 till the return to fill_insns. */
5930 if (need_nop_to_preserve_insn_bb (insn))
5932 insn_t nop = get_nop_from_pool (insn);
5933 gcc_assert (INSN_NOP_P (nop));
5934 VEC_safe_push (insn_t, heap, vec_temp_moveop_nops, nop);
5937 sel_remove_insn (insn, only_disconnect, false);
5940 /* This function is called when original expr is found.
5941 INSN - current insn traversed, EXPR - the corresponding expr found.
5942 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5943 is static parameters of move_op. */
5945 move_op_orig_expr_found (insn_t insn, expr_t expr,
5946 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5947 void *static_params)
5949 bool only_disconnect, insn_emitted;
5950 moveop_static_params_p params = (moveop_static_params_p) static_params;
5952 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
5953 track_scheduled_insns_and_blocks (insn);
5954 insn_emitted = handle_emitting_transformations (insn, expr, params);
5955 only_disconnect = (params->uid == INSN_UID (insn)
5956 && ! insn_emitted && ! EXPR_WAS_CHANGED (expr));
5958 /* Mark that we've disconnected an insn. */
5959 if (only_disconnect)
5961 remove_insn_from_stream (insn, only_disconnect);
5964 /* The function is called when original expr is found.
5965 INSN - current insn traversed, EXPR - the corresponding expr found,
5966 crosses_call and original_insns in STATIC_PARAMS are updated. */
5968 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
5969 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5970 void *static_params)
5972 fur_static_params_p params = (fur_static_params_p) static_params;
5976 params->crosses_call = true;
5978 def_list_add (params->original_insns, insn, params->crosses_call);
5980 /* Mark the registers that do not meet the following condition:
5981 (2) not among the live registers of the point
5982 immediately following the first original operation on
5983 a given downward path, except for the original target
5984 register of the operation. */
5985 tmp = get_clear_regset_from_pool ();
5986 compute_live_below_insn (insn, tmp);
5987 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
5988 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
5989 IOR_REG_SET (params->used_regs, tmp);
5990 return_regset_to_pool (tmp);
5992 /* (*1) We need to add to USED_REGS registers that are read by
5993 INSN's lhs. This may lead to choosing wrong src register.
5994 E.g. (scheduling const expr enabled):
5996 429: ax=0x0 <- Can't use AX for this expr (0x0)
6003 /* FIXME: see comment above and enable MEM_P
6004 in vinsn_separable_p. */
6005 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
6006 || !MEM_P (INSN_LHS (insn)));
6009 /* This function is called on the ascending pass, before returning from
6010 current basic block. */
6012 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
6013 void *static_params)
6015 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6016 basic_block book_block = NULL;
6018 /* When we have removed the boundary insn for scheduling, which also
6019 happened to be the end insn in its bb, we don't need to update sets. */
6020 if (!lparams->removed_last_insn
6022 && sel_bb_head_p (insn))
6024 /* We should generate bookkeeping code only if we are not at the
6025 top level of the move_op. */
6026 if (sel_num_cfg_preds_gt_1 (insn))
6027 book_block = generate_bookkeeping_insn (sparams->c_expr,
6028 lparams->e1, lparams->e2);
6029 /* Update data sets for the current insn. */
6030 update_data_sets (insn);
6033 /* If bookkeeping code was inserted, we need to update av sets of basic
6034 block that received bookkeeping. After generation of bookkeeping insn,
6035 bookkeeping block does not contain valid av set because we are not following
6036 the original algorithm in every detail with regards to e.g. renaming
6037 simple reg-reg copies. Consider example:
6039 bookkeeping block scheduling fence
6049 We try to schedule insn "r1 := r3" on the current
6050 scheduling fence. Also, note that av set of bookkeeping block
6051 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6052 been scheduled, the CFG is as follows:
6055 bookkeeping block scheduling fence
6065 Here, insn "r1 := r3" was scheduled at the current scheduling point
6066 and bookkeeping code was generated at the bookeeping block. This
6067 way insn "r1 := r2" is no longer available as a whole instruction
6068 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6069 This situation is handled by calling update_data_sets.
6071 Since update_data_sets is called only on the bookkeeping block, and
6072 it also may have predecessors with av_sets, containing instructions that
6073 are no longer available, we save all such expressions that become
6074 unavailable during data sets update on the bookkeeping block in
6075 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6076 expressions for scheduling. This allows us to avoid recomputation of
6077 av_sets outside the code motion path. */
6080 update_and_record_unavailable_insns (book_block);
6082 /* If INSN was previously marked for deletion, it's time to do it. */
6083 if (lparams->removed_last_insn)
6084 insn = PREV_INSN (insn);
6086 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6087 kill a block with a single nop in which the insn should be emitted. */
6089 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
6092 /* This function is called on the ascending pass, before returning from the
6093 current basic block. */
6095 fur_at_first_insn (insn_t insn,
6096 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6097 void *static_params ATTRIBUTE_UNUSED)
6099 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
6100 || AV_LEVEL (insn) == -1);
6103 /* Called on the backward stage of recursion to call moveup_expr for insn
6104 and sparams->c_expr. */
6106 move_op_ascend (insn_t insn, void *static_params)
6108 enum MOVEUP_EXPR_CODE res;
6109 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6111 if (! INSN_NOP_P (insn))
6113 res = moveup_expr_cached (sparams->c_expr, insn, false);
6114 gcc_assert (res != MOVEUP_EXPR_NULL);
6117 /* Update liveness for this insn as it was invalidated. */
6118 update_liveness_on_insn (insn);
6121 /* This function is called on enter to the basic block.
6122 Returns TRUE if this block already have been visited and
6123 code_motion_path_driver should return 1, FALSE otherwise. */
6125 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
6126 void *static_params, bool visited_p)
6128 fur_static_params_p sparams = (fur_static_params_p) static_params;
6132 /* If we have found something below this block, there should be at
6133 least one insn in ORIGINAL_INSNS. */
6134 gcc_assert (*sparams->original_insns);
6136 /* Adjust CROSSES_CALL, since we may have come to this block along
6138 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
6139 |= sparams->crosses_call;
6142 local_params->old_original_insns = *sparams->original_insns;
6147 /* Same as above but for move_op. */
6149 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
6150 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
6151 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
6158 /* This function is called while descending current basic block if current
6159 insn is not the original EXPR we're searching for.
6161 Return value: FALSE, if code_motion_path_driver should perform a local
6162 cleanup and return 0 itself;
6163 TRUE, if code_motion_path_driver should continue. */
6165 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
6166 void *static_params)
6168 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6170 #ifdef ENABLE_CHECKING
6171 sparams->failed_insn = insn;
6174 /* If we're scheduling separate expr, in order to generate correct code
6175 we need to stop the search at bookkeeping code generated with the
6176 same destination register or memory. */
6177 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
6182 /* This function is called while descending current basic block if current
6183 insn is not the original EXPR we're searching for.
6185 Return value: TRUE (code_motion_path_driver should continue). */
6187 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
6191 av_set_iterator avi;
6192 fur_static_params_p sparams = (fur_static_params_p) static_params;
6195 sparams->crosses_call = true;
6196 else if (DEBUG_INSN_P (insn))
6199 /* If current insn we are looking at cannot be executed together
6200 with original insn, then we can skip it safely.
6202 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6203 INSN = (!p6) r14 = r14 + 1;
6205 Here we can schedule ORIG_OP with lhs = r14, though only
6206 looking at the set of used and set registers of INSN we must
6207 forbid it. So, add set/used in INSN registers to the
6208 untouchable set only if there is an insn in ORIG_OPS that can
6211 FOR_EACH_EXPR (r, avi, orig_ops)
6212 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
6218 /* Mark all registers that do not meet the following condition:
6219 (1) Not set or read on any path from xi to an instance of the
6220 original operation. */
6223 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6224 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6225 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6231 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6232 struct code_motion_path_driver_info_def move_op_hooks = {
6234 move_op_orig_expr_found,
6235 move_op_orig_expr_not_found,
6236 move_op_merge_succs,
6237 move_op_after_merge_succs,
6239 move_op_at_first_insn,
6244 /* Hooks and data to perform find_used_regs operations
6245 with code_motion_path_driver. */
6246 struct code_motion_path_driver_info_def fur_hooks = {
6248 fur_orig_expr_found,
6249 fur_orig_expr_not_found,
6251 NULL, /* fur_after_merge_succs */
6252 NULL, /* fur_ascend */
6258 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6259 code_motion_path_driver is called recursively. Original operation
6260 was found at least on one path that is starting with one of INSN's
6261 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6262 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6263 of either move_op or find_used_regs depending on the caller.
6265 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6266 know for sure at this point. */
6268 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6269 ilist_t path, void *static_params)
6272 succ_iterator succ_i;
6278 struct cmpd_local_params lparams;
6281 lparams.c_expr_local = &_x;
6282 lparams.c_expr_merged = NULL;
6284 /* We need to process only NORMAL succs for move_op, and collect live
6285 registers from ALL branches (including those leading out of the
6286 region) for find_used_regs.
6288 In move_op, there can be a case when insn's bb number has changed
6289 due to created bookkeeping. This happens very rare, as we need to
6290 move expression from the beginning to the end of the same block.
6291 Rescan successors in this case. */
6294 bb = BLOCK_FOR_INSN (insn);
6295 old_index = bb->index;
6296 old_succs = EDGE_COUNT (bb->succs);
6298 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6302 lparams.e1 = succ_i.e1;
6303 lparams.e2 = succ_i.e2;
6305 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6307 if (succ_i.current_flags == SUCCS_NORMAL)
6308 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6313 /* Merge c_expres found or unify live register sets from different
6315 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6319 else if (b == -1 && res != 1)
6322 /* We have simplified the control flow below this point. In this case,
6323 the iterator becomes invalid. We need to try again. */
6324 if (BLOCK_FOR_INSN (insn)->index != old_index
6325 || EDGE_COUNT (bb->succs) != old_succs)
6329 #ifdef ENABLE_CHECKING
6330 /* Here, RES==1 if original expr was found at least for one of the
6331 successors. After the loop, RES may happen to have zero value
6332 only if at some point the expr searched is present in av_set, but is
6333 not found below. In most cases, this situation is an error.
6334 The exception is when the original operation is blocked by
6335 bookkeeping generated for another fence or for another path in current
6337 gcc_assert (res == 1
6339 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops,
6344 /* Merge data, clean up, etc. */
6345 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6346 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6352 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6353 is the pointer to the av set with expressions we were looking for,
6354 PATH_P is the pointer to the traversed path. */
6356 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6358 ilist_remove (path_p);
6359 av_set_clear (orig_ops_p);
6362 /* The driver function that implements move_op or find_used_regs
6363 functionality dependent whether code_motion_path_driver_INFO is set to
6364 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6365 of code (CFG traversal etc) that are shared among both functions. INSN
6366 is the insn we're starting the search from, ORIG_OPS are the expressions
6367 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6368 parameters of the driver, and STATIC_PARAMS are static parameters of
6371 Returns whether original instructions were found. Note that top-level
6372 code_motion_path_driver always returns true. */
6374 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6375 cmpd_local_params_p local_params_in,
6376 void *static_params)
6379 basic_block bb = BLOCK_FOR_INSN (insn);
6380 insn_t first_insn, bb_tail, before_first;
6381 bool removed_last_insn = false;
6383 if (sched_verbose >= 6)
6385 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6388 dump_av_set (orig_ops);
6392 gcc_assert (orig_ops);
6394 /* If no original operations exist below this insn, return immediately. */
6395 if (is_ineligible_successor (insn, path))
6397 if (sched_verbose >= 6)
6398 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6402 /* The block can have invalid av set, in which case it was created earlier
6403 during move_op. Return immediately. */
6404 if (sel_bb_head_p (insn))
6406 if (! AV_SET_VALID_P (insn))
6408 if (sched_verbose >= 6)
6409 sel_print ("Returned from block %d as it had invalid av set\n",
6414 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6416 /* We have already found an original operation on this branch, do not
6417 go any further and just return TRUE here. If we don't stop here,
6418 function can have exponential behaviour even on the small code
6419 with many different paths (e.g. with data speculation and
6420 recovery blocks). */
6421 if (sched_verbose >= 6)
6422 sel_print ("Block %d already visited in this traversal\n", bb->index);
6423 if (code_motion_path_driver_info->on_enter)
6424 return code_motion_path_driver_info->on_enter (insn,
6431 if (code_motion_path_driver_info->on_enter)
6432 code_motion_path_driver_info->on_enter (insn, local_params_in,
6433 static_params, false);
6434 orig_ops = av_set_copy (orig_ops);
6436 /* Filter the orig_ops set. */
6437 if (AV_SET_VALID_P (insn))
6438 av_set_intersect (&orig_ops, AV_SET (insn));
6440 /* If no more original ops, return immediately. */
6443 if (sched_verbose >= 6)
6444 sel_print ("No intersection with av set of block %d\n", bb->index);
6448 /* For non-speculative insns we have to leave only one form of the
6449 original operation, because if we don't, we may end up with
6450 different C_EXPRes and, consequently, with bookkeepings for different
6451 expression forms along the same code motion path. That may lead to
6452 generation of incorrect code. So for each code motion we stick to
6453 the single form of the instruction, except for speculative insns
6454 which we need to keep in different forms with all speculation
6456 av_set_leave_one_nonspec (&orig_ops);
6458 /* It is not possible that all ORIG_OPS are filtered out. */
6459 gcc_assert (orig_ops);
6461 /* It is enough to place only heads and tails of visited basic blocks into
6463 ilist_add (&path, insn);
6465 bb_tail = sel_bb_end (bb);
6467 /* Descend the basic block in search of the original expr; this part
6468 corresponds to the part of the original move_op procedure executed
6469 before the recursive call. */
6472 /* Look at the insn and decide if it could be an ancestor of currently
6473 scheduling operation. If it is so, then the insn "dest = op" could
6474 either be replaced with "dest = reg", because REG now holds the result
6475 of OP, or just removed, if we've scheduled the insn as a whole.
6477 If this insn doesn't contain currently scheduling OP, then proceed
6478 with searching and look at its successors. Operations we're searching
6479 for could have changed when moving up through this insn via
6480 substituting. In this case, perform unsubstitution on them first.
6482 When traversing the DAG below this insn is finished, insert
6483 bookkeeping code, if the insn is a joint point, and remove
6486 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6489 insn_t last_insn = PREV_INSN (insn);
6491 /* We have found the original operation. */
6492 if (sched_verbose >= 6)
6493 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6495 code_motion_path_driver_info->orig_expr_found
6496 (insn, expr, local_params_in, static_params);
6498 /* Step back, so on the way back we'll start traversing from the
6499 previous insn (or we'll see that it's bb_note and skip that
6501 if (insn == first_insn)
6503 first_insn = NEXT_INSN (last_insn);
6504 removed_last_insn = sel_bb_end_p (last_insn);
6511 /* We haven't found the original expr, continue descending the basic
6513 if (code_motion_path_driver_info->orig_expr_not_found
6514 (insn, orig_ops, static_params))
6516 /* Av set ops could have been changed when moving through this
6517 insn. To find them below it, we have to un-substitute them. */
6518 undo_transformations (&orig_ops, insn);
6522 /* Clean up and return, if the hook tells us to do so. It may
6523 happen if we've encountered the previously created
6525 code_motion_path_driver_cleanup (&orig_ops, &path);
6529 gcc_assert (orig_ops);
6532 /* Stop at insn if we got to the end of BB. */
6533 if (insn == bb_tail)
6536 insn = NEXT_INSN (insn);
6539 /* Here INSN either points to the insn before the original insn (may be
6540 bb_note, if original insn was a bb_head) or to the bb_end. */
6545 gcc_assert (insn == sel_bb_end (bb));
6547 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6548 it's already in PATH then). */
6549 if (insn != first_insn)
6550 ilist_add (&path, insn);
6552 /* Process_successors should be able to find at least one
6553 successor for which code_motion_path_driver returns TRUE. */
6554 res = code_motion_process_successors (insn, orig_ops,
6555 path, static_params);
6557 /* Remove bb tail from path. */
6558 if (insn != first_insn)
6559 ilist_remove (&path);
6563 /* This is the case when one of the original expr is no longer available
6564 due to bookkeeping created on this branch with the same register.
6565 In the original algorithm, which doesn't have update_data_sets call
6566 on a bookkeeping block, it would simply result in returning
6567 FALSE when we've encountered a previously generated bookkeeping
6568 insn in moveop_orig_expr_not_found. */
6569 code_motion_path_driver_cleanup (&orig_ops, &path);
6574 /* Don't need it any more. */
6575 av_set_clear (&orig_ops);
6577 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6578 the beginning of the basic block. */
6579 before_first = PREV_INSN (first_insn);
6580 while (insn != before_first)
6582 if (code_motion_path_driver_info->ascend)
6583 code_motion_path_driver_info->ascend (insn, static_params);
6585 insn = PREV_INSN (insn);
6588 /* Now we're at the bb head. */
6590 ilist_remove (&path);
6591 local_params_in->removed_last_insn = removed_last_insn;
6592 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6594 /* This should be the very last operation as at bb head we could change
6595 the numbering by creating bookkeeping blocks. */
6596 if (removed_last_insn)
6597 insn = PREV_INSN (insn);
6598 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6602 /* Move up the operations from ORIG_OPS set traversing the dag starting
6603 from INSN. PATH represents the edges traversed so far.
6604 DEST is the register chosen for scheduling the current expr. Insert
6605 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6606 C_EXPR is how it looks like at the given cfg point.
6607 Set *SHOULD_MOVE to indicate whether we have only disconnected
6608 one of the insns found.
6610 Returns whether original instructions were found, which is asserted
6611 to be true in the caller. */
6613 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6614 rtx dest, expr_t c_expr, bool *should_move)
6616 struct moveop_static_params sparams;
6617 struct cmpd_local_params lparams;
6620 /* Init params for code_motion_path_driver. */
6621 sparams.dest = dest;
6622 sparams.c_expr = c_expr;
6623 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6624 #ifdef ENABLE_CHECKING
6625 sparams.failed_insn = NULL;
6627 sparams.was_renamed = false;
6630 /* We haven't visited any blocks yet. */
6631 bitmap_clear (code_motion_visited_blocks);
6633 /* Set appropriate hooks and data. */
6634 code_motion_path_driver_info = &move_op_hooks;
6635 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6637 if (sparams.was_renamed)
6638 EXPR_WAS_RENAMED (expr_vliw) = true;
6640 *should_move = (sparams.uid == -1);
6646 /* Functions that work with regions. */
6648 /* Current number of seqno used in init_seqno and init_seqno_1. */
6649 static int cur_seqno;
6651 /* A helper for init_seqno. Traverse the region starting from BB and
6652 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6653 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6655 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6657 int bbi = BLOCK_TO_BB (bb->index);
6658 insn_t insn, note = bb_note (bb);
6662 SET_BIT (visited_bbs, bbi);
6663 if (blocks_to_reschedule)
6664 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6666 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6667 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6669 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6670 int succ_bbi = BLOCK_TO_BB (succ->index);
6672 gcc_assert (in_current_region_p (succ));
6674 if (!TEST_BIT (visited_bbs, succ_bbi))
6676 gcc_assert (succ_bbi > bbi);
6678 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6682 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6683 INSN_SEQNO (insn) = cur_seqno--;
6686 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6687 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6688 which we're rescheduling when pipelining, FROM is the block where
6689 traversing region begins (it may not be the head of the region when
6690 pipelining, but the head of the loop instead).
6692 Returns the maximal seqno found. */
6694 init_seqno (int number_of_insns, bitmap blocks_to_reschedule, basic_block from)
6696 sbitmap visited_bbs;
6700 visited_bbs = sbitmap_alloc (current_nr_blocks);
6702 if (blocks_to_reschedule)
6704 sbitmap_ones (visited_bbs);
6705 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6707 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6708 RESET_BIT (visited_bbs, BLOCK_TO_BB (bbi));
6713 sbitmap_zero (visited_bbs);
6714 from = EBB_FIRST_BB (0);
6717 cur_seqno = number_of_insns > 0 ? number_of_insns : sched_max_luid - 1;
6718 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6719 gcc_assert (cur_seqno == 0 || number_of_insns == 0);
6721 sbitmap_free (visited_bbs);
6722 return sched_max_luid - 1;
6725 /* Initialize scheduling parameters for current region. */
6727 sel_setup_region_sched_flags (void)
6729 enable_schedule_as_rhs_p = 1;
6731 pipelining_p = (bookkeeping_p
6732 && (flag_sel_sched_pipelining != 0)
6733 && current_loop_nest != NULL);
6734 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6738 /* Return true if all basic blocks of current region are empty. */
6740 current_region_empty_p (void)
6743 for (i = 0; i < current_nr_blocks; i++)
6744 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i))))
6750 /* Prepare and verify loop nest for pipelining. */
6752 setup_current_loop_nest (int rgn)
6754 current_loop_nest = get_loop_nest_for_rgn (rgn);
6756 if (!current_loop_nest)
6759 /* If this loop has any saved loop preheaders from nested loops,
6760 add these basic blocks to the current region. */
6761 sel_add_loop_preheaders ();
6763 /* Check that we're starting with a valid information. */
6764 gcc_assert (loop_latch_edge (current_loop_nest));
6765 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6768 /* Compute instruction priorities for current region. */
6770 sel_compute_priorities (int rgn)
6772 sched_rgn_compute_dependencies (rgn);
6774 /* Compute insn priorities in haifa style. Then free haifa style
6775 dependencies that we've calculated for this. */
6776 compute_priorities ();
6778 if (sched_verbose >= 5)
6779 debug_rgn_dependencies (0);
6784 /* Init scheduling data for RGN. Returns true when this region should not
6787 sel_region_init (int rgn)
6792 rgn_setup_region (rgn);
6794 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6795 do region initialization here so the region can be bundled correctly,
6796 but we'll skip the scheduling in sel_sched_region (). */
6797 if (current_region_empty_p ())
6800 if (flag_sel_sched_pipelining)
6801 setup_current_loop_nest (rgn);
6803 sel_setup_region_sched_flags ();
6805 bbs = VEC_alloc (basic_block, heap, current_nr_blocks);
6807 for (i = 0; i < current_nr_blocks; i++)
6808 VEC_quick_push (basic_block, bbs, BASIC_BLOCK (BB_TO_BLOCK (i)));
6810 sel_init_bbs (bbs, NULL);
6812 /* Initialize luids and dependence analysis which both sel-sched and haifa
6814 sched_init_luids (bbs, NULL, NULL, NULL);
6815 sched_deps_init (false);
6817 /* Initialize haifa data. */
6818 rgn_setup_sched_infos ();
6819 sel_set_sched_flags ();
6820 haifa_init_h_i_d (bbs, NULL, NULL, NULL);
6822 sel_compute_priorities (rgn);
6823 init_deps_global ();
6825 /* Main initialization. */
6826 sel_setup_sched_infos ();
6827 sel_init_global_and_expr (bbs);
6829 VEC_free (basic_block, heap, bbs);
6831 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6833 /* Init correct liveness sets on each instruction of a single-block loop.
6834 This is the only situation when we can't update liveness when calling
6835 compute_live for the first insn of the loop. */
6836 if (current_loop_nest)
6838 int header = (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6842 if (current_nr_blocks == header + 1)
6843 update_liveness_on_insn
6844 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header))));
6847 /* Set hooks so that no newly generated insn will go out unnoticed. */
6848 sel_register_cfg_hooks ();
6850 /* !!! We call target.sched.md_init () for the whole region, but we invoke
6851 targetm.sched.md_finish () for every ebb. */
6852 if (targetm.sched.md_init)
6853 /* None of the arguments are actually used in any target. */
6854 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6856 first_emitted_uid = get_max_uid () + 1;
6857 preheader_removed = false;
6859 /* Reset register allocation ticks array. */
6860 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6861 reg_rename_this_tick = 0;
6863 bitmap_initialize (forced_ebb_heads, 0);
6864 bitmap_clear (forced_ebb_heads);
6867 current_copies = BITMAP_ALLOC (NULL);
6868 current_originators = BITMAP_ALLOC (NULL);
6869 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
6874 /* Simplify insns after the scheduling. */
6876 simplify_changed_insns (void)
6880 for (i = 0; i < current_nr_blocks; i++)
6882 basic_block bb = BASIC_BLOCK (BB_TO_BLOCK (i));
6885 FOR_BB_INSNS (bb, insn)
6888 expr_t expr = INSN_EXPR (insn);
6890 if (EXPR_WAS_SUBSTITUTED (expr))
6891 validate_simplify_insn (insn);
6896 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6897 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6898 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6900 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
6903 basic_block bb1 = bb;
6904 if (sched_verbose >= 2)
6905 sel_print ("Finishing schedule in bbs: ");
6909 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
6911 if (sched_verbose >= 2)
6912 sel_print ("%d; ", bb1->index);
6914 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
6916 if (sched_verbose >= 2)
6919 get_ebb_head_tail (bb, bb1, &head, &tail);
6921 current_sched_info->head = head;
6922 current_sched_info->tail = tail;
6923 current_sched_info->prev_head = PREV_INSN (head);
6924 current_sched_info->next_tail = NEXT_INSN (tail);
6927 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6929 reset_sched_cycles_in_current_ebb (void)
6932 int haifa_last_clock = -1;
6933 int haifa_clock = 0;
6936 if (targetm.sched.md_init)
6938 /* None of the arguments are actually used in any target.
6939 NB: We should have md_reset () hook for cases like this. */
6940 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6943 state_reset (curr_state);
6944 advance_state (curr_state);
6946 for (insn = current_sched_info->head;
6947 insn != current_sched_info->next_tail;
6948 insn = NEXT_INSN (insn))
6950 int cost, haifa_cost;
6952 bool asm_p, real_insn, after_stall;
6959 real_insn = recog_memoized (insn) >= 0;
6960 clock = INSN_SCHED_CYCLE (insn);
6962 cost = clock - last_clock;
6964 /* Initialize HAIFA_COST. */
6967 asm_p = INSN_ASM_P (insn);
6970 /* This is asm insn which *had* to be scheduled first
6974 /* This is a use/clobber insn. It should not change
6979 haifa_cost = estimate_insn_cost (insn, curr_state);
6981 /* Stall for whatever cycles we've stalled before. */
6983 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
6993 while (haifa_cost--)
6995 advance_state (curr_state);
6998 if (sched_verbose >= 2)
7000 sel_print ("advance_state (state_transition)\n");
7001 debug_state (curr_state);
7004 /* The DFA may report that e.g. insn requires 2 cycles to be
7005 issued, but on the next cycle it says that insn is ready
7006 to go. Check this here. */
7010 && estimate_insn_cost (insn, curr_state) == 0)
7017 gcc_assert (haifa_cost == 0);
7019 if (sched_verbose >= 2)
7020 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
7022 if (targetm.sched.dfa_new_cycle)
7023 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
7024 haifa_last_clock, haifa_clock,
7027 advance_state (curr_state);
7029 if (sched_verbose >= 2)
7031 sel_print ("advance_state (dfa_new_cycle)\n");
7032 debug_state (curr_state);
7038 cost = state_transition (curr_state, insn);
7040 if (sched_verbose >= 2)
7041 debug_state (curr_state);
7043 gcc_assert (cost < 0);
7046 if (targetm.sched.variable_issue)
7047 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
7049 INSN_SCHED_CYCLE (insn) = haifa_clock;
7052 haifa_last_clock = haifa_clock;
7056 /* Put TImode markers on insns starting a new issue group. */
7060 int last_clock = -1;
7063 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
7064 insn = NEXT_INSN (insn))
7071 clock = INSN_SCHED_CYCLE (insn);
7072 cost = (last_clock == -1) ? 1 : clock - last_clock;
7074 gcc_assert (cost >= 0);
7077 && GET_CODE (PATTERN (insn)) != USE
7078 && GET_CODE (PATTERN (insn)) != CLOBBER)
7080 if (reload_completed && cost > 0)
7081 PUT_MODE (insn, TImode);
7086 if (sched_verbose >= 2)
7087 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
7091 /* Perform MD_FINISH on EBBs comprising current region. When
7092 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7093 to produce correct sched cycles on insns. */
7095 sel_region_target_finish (bool reset_sched_cycles_p)
7098 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
7100 for (i = 0; i < current_nr_blocks; i++)
7102 if (bitmap_bit_p (scheduled_blocks, i))
7105 /* While pipelining outer loops, skip bundling for loop
7106 preheaders. Those will be rescheduled in the outer loop. */
7107 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
7110 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
7112 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
7115 if (reset_sched_cycles_p)
7116 reset_sched_cycles_in_current_ebb ();
7118 if (targetm.sched.md_init)
7119 targetm.sched.md_init (sched_dump, sched_verbose, -1);
7123 if (targetm.sched.md_finish)
7125 targetm.sched.md_finish (sched_dump, sched_verbose);
7127 /* Extend luids so that insns generated by the target will
7129 sched_init_luids (NULL, NULL, NULL, NULL);
7133 BITMAP_FREE (scheduled_blocks);
7136 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7137 is true, make an additional pass emulating scheduler to get correct insn
7138 cycles for md_finish calls. */
7140 sel_region_finish (bool reset_sched_cycles_p)
7142 simplify_changed_insns ();
7143 sched_finish_ready_list ();
7146 /* Free the vectors. */
7148 VEC_free (expr_t, heap, vec_av_set);
7149 BITMAP_FREE (current_copies);
7150 BITMAP_FREE (current_originators);
7151 BITMAP_FREE (code_motion_visited_blocks);
7152 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns);
7153 vinsn_vec_free (&vec_target_unavailable_vinsns);
7155 /* If LV_SET of the region head should be updated, do it now because
7156 there will be no other chance. */
7161 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
7162 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
7164 basic_block bb = BLOCK_FOR_INSN (insn);
7166 if (!BB_LV_SET_VALID_P (bb))
7167 compute_live (insn);
7171 /* Emulate the Haifa scheduler for bundling. */
7172 if (reload_completed)
7173 sel_region_target_finish (reset_sched_cycles_p);
7175 sel_finish_global_and_expr ();
7177 bitmap_clear (forced_ebb_heads);
7181 finish_deps_global ();
7182 sched_finish_luids ();
7185 BITMAP_FREE (blocks_to_reschedule);
7187 sel_unregister_cfg_hooks ();
7193 /* Functions that implement the scheduler driver. */
7195 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7196 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7197 of insns scheduled -- these would be postprocessed later. */
7199 schedule_on_fences (flist_t fences, int max_seqno,
7200 ilist_t **scheduled_insns_tailpp)
7202 flist_t old_fences = fences;
7204 if (sched_verbose >= 1)
7206 sel_print ("\nScheduling on fences: ");
7207 dump_flist (fences);
7211 scheduled_something_on_previous_fence = false;
7212 for (; fences; fences = FLIST_NEXT (fences))
7214 fence_t fence = NULL;
7217 bool first_p = true;
7219 /* Choose the next fence group to schedule.
7220 The fact that insn can be scheduled only once
7221 on the cycle is guaranteed by two properties:
7222 1. seqnos of parallel groups decrease with each iteration.
7223 2. If is_ineligible_successor () sees the larger seqno, it
7224 checks if candidate insn is_in_current_fence_p (). */
7225 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7227 fence_t f = FLIST_FENCE (fences2);
7229 if (!FENCE_PROCESSED_P (f))
7231 int i = INSN_SEQNO (FENCE_INSN (f));
7233 if (first_p || i > seqno)
7240 /* ??? Seqnos of different groups should be different. */
7241 gcc_assert (1 || i != seqno);
7247 /* As FENCE is nonnull, SEQNO is initialized. */
7248 seqno -= max_seqno + 1;
7249 fill_insns (fence, seqno, scheduled_insns_tailpp);
7250 FENCE_PROCESSED_P (fence) = true;
7253 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7254 don't need to keep bookkeeping-invalidated and target-unavailable
7256 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7257 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7260 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7262 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7264 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7266 /* The first element is already processed. */
7267 while ((fences = FLIST_NEXT (fences)))
7269 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7271 if (*min_seqno > seqno)
7273 else if (*max_seqno < seqno)
7278 /* Calculate new fences from FENCES. */
7280 calculate_new_fences (flist_t fences, int orig_max_seqno)
7282 flist_t old_fences = fences;
7283 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7285 flist_tail_init (new_fences);
7286 for (; fences; fences = FLIST_NEXT (fences))
7288 fence_t fence = FLIST_FENCE (fences);
7291 if (!FENCE_BNDS (fence))
7293 /* This fence doesn't have any successors. */
7294 if (!FENCE_SCHEDULED_P (fence))
7296 /* Nothing was scheduled on this fence. */
7299 insn = FENCE_INSN (fence);
7300 seqno = INSN_SEQNO (insn);
7301 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7303 if (sched_verbose >= 1)
7304 sel_print ("Fence %d[%d] has not changed\n",
7307 move_fence_to_fences (fences, new_fences);
7311 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7314 flist_clear (&old_fences);
7315 return FLIST_TAIL_HEAD (new_fences);
7318 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7319 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7320 the highest seqno used in a region. Return the updated highest seqno. */
7322 update_seqnos_and_stage (int min_seqno, int max_seqno,
7323 int highest_seqno_in_use,
7324 ilist_t *pscheduled_insns)
7330 /* Actually, new_hs is the seqno of the instruction, that was
7331 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7332 if (*pscheduled_insns)
7334 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7335 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7336 gcc_assert (new_hs > highest_seqno_in_use);
7339 new_hs = highest_seqno_in_use;
7341 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7343 gcc_assert (INSN_SEQNO (insn) < 0);
7344 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7345 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7347 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7348 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7349 require > 1GB of memory e.g. on limit-fnargs.c. */
7351 free_data_for_scheduled_insn (insn);
7354 ilist_clear (pscheduled_insns);
7360 /* The main driver for scheduling a region. This function is responsible
7361 for correct propagation of fences (i.e. scheduling points) and creating
7362 a group of parallel insns at each of them. It also supports
7363 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7366 sel_sched_region_2 (int orig_max_seqno)
7368 int highest_seqno_in_use = orig_max_seqno;
7370 stat_bookkeeping_copies = 0;
7371 stat_insns_needed_bookkeeping = 0;
7372 stat_renamed_scheduled = 0;
7373 stat_substitutions_total = 0;
7374 num_insns_scheduled = 0;
7378 int min_seqno, max_seqno;
7379 ilist_t scheduled_insns = NULL;
7380 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7382 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7383 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7384 fences = calculate_new_fences (fences, orig_max_seqno);
7385 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7386 highest_seqno_in_use,
7390 if (sched_verbose >= 1)
7391 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7392 "bookkeeping, %d insns renamed, %d insns substituted\n",
7393 stat_bookkeeping_copies,
7394 stat_insns_needed_bookkeeping,
7395 stat_renamed_scheduled,
7396 stat_substitutions_total);
7399 /* Schedule a region. When pipelining, search for possibly never scheduled
7400 bookkeeping code and schedule it. Reschedule pipelined code without
7401 pipelining after. */
7403 sel_sched_region_1 (void)
7405 int number_of_insns;
7408 /* Remove empty blocks that might be in the region from the beginning.
7409 We need to do save sched_max_luid before that, as it actually shows
7410 the number of insns in the region, and purge_empty_blocks can
7412 number_of_insns = sched_max_luid - 1;
7413 purge_empty_blocks ();
7415 orig_max_seqno = init_seqno (number_of_insns, NULL, NULL);
7416 gcc_assert (orig_max_seqno >= 1);
7418 /* When pipelining outer loops, create fences on the loop header,
7421 if (current_loop_nest)
7422 init_fences (BB_END (EBB_FIRST_BB (0)));
7424 init_fences (bb_note (EBB_FIRST_BB (0)));
7427 sel_sched_region_2 (orig_max_seqno);
7429 gcc_assert (fences == NULL);
7435 struct flist_tail_def _new_fences;
7436 flist_tail_t new_fences = &_new_fences;
7439 pipelining_p = false;
7440 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7441 bookkeeping_p = false;
7442 enable_schedule_as_rhs_p = false;
7444 /* Schedule newly created code, that has not been scheduled yet. */
7451 for (i = 0; i < current_nr_blocks; i++)
7453 basic_block bb = EBB_FIRST_BB (i);
7455 if (sel_bb_empty_p (bb))
7457 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7461 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7463 clear_outdated_rtx_info (bb);
7464 if (sel_insn_is_speculation_check (BB_END (bb))
7465 && JUMP_P (BB_END (bb)))
7466 bitmap_set_bit (blocks_to_reschedule,
7467 BRANCH_EDGE (bb)->dest->index);
7469 else if (INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7470 bitmap_set_bit (blocks_to_reschedule, bb->index);
7473 for (i = 0; i < current_nr_blocks; i++)
7475 bb = EBB_FIRST_BB (i);
7477 /* While pipelining outer loops, skip bundling for loop
7478 preheaders. Those will be rescheduled in the outer
7480 if (sel_is_loop_preheader_p (bb))
7482 clear_outdated_rtx_info (bb);
7486 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7488 flist_tail_init (new_fences);
7490 orig_max_seqno = init_seqno (0, blocks_to_reschedule, bb);
7492 /* Mark BB as head of the new ebb. */
7493 bitmap_set_bit (forced_ebb_heads, bb->index);
7495 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7497 gcc_assert (fences == NULL);
7499 init_fences (bb_note (bb));
7501 sel_sched_region_2 (orig_max_seqno);
7511 /* Schedule the RGN region. */
7513 sel_sched_region (int rgn)
7516 bool reset_sched_cycles_p;
7518 if (sel_region_init (rgn))
7521 if (sched_verbose >= 1)
7522 sel_print ("Scheduling region %d\n", rgn);
7524 schedule_p = (!sched_is_disabled_for_current_region_p ()
7525 && dbg_cnt (sel_sched_region_cnt));
7526 reset_sched_cycles_p = pipelining_p;
7528 sel_sched_region_1 ();
7530 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7531 reset_sched_cycles_p = true;
7533 sel_region_finish (reset_sched_cycles_p);
7536 /* Perform global init for the scheduler. */
7538 sel_global_init (void)
7540 calculate_dominance_info (CDI_DOMINATORS);
7541 alloc_sched_pools ();
7543 /* Setup the infos for sched_init. */
7544 sel_setup_sched_infos ();
7545 setup_sched_dump ();
7547 sched_rgn_init (false);
7551 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7553 can_issue_more = issue_rate;
7555 sched_extend_target ();
7556 sched_deps_init (true);
7557 setup_nop_and_exit_insns ();
7558 sel_extend_global_bb_info ();
7560 init_hard_regs_data ();
7563 /* Free the global data of the scheduler. */
7565 sel_global_finish (void)
7567 free_bb_note_pool ();
7569 sel_finish_global_bb_info ();
7571 free_regset_pool ();
7572 free_nop_and_exit_insns ();
7574 sched_rgn_finish ();
7575 sched_deps_finish ();
7579 sel_finish_pipelining ();
7581 free_sched_pools ();
7582 free_dominance_info (CDI_DOMINATORS);
7585 /* Return true when we need to skip selective scheduling. Used for debugging. */
7587 maybe_skip_selective_scheduling (void)
7589 return ! dbg_cnt (sel_sched_cnt);
7592 /* The entry point. */
7594 run_selective_scheduling (void)
7598 if (n_basic_blocks == NUM_FIXED_BLOCKS)
7603 for (rgn = 0; rgn < nr_regions; rgn++)
7604 sel_sched_region (rgn);
7606 sel_global_finish ();