1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "rtl-error.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
39 #include "tree-pass.h"
40 #include "sched-int.h"
44 #include "langhooks.h"
45 #include "rtlhooks-def.h"
50 #ifdef INSN_SCHEDULING
51 #include "sel-sched-ir.h"
52 #include "sel-sched-dump.h"
53 #include "sel-sched.h"
56 /* Implementation of selective scheduling approach.
57 The below implementation follows the original approach with the following
60 o the scheduler works after register allocation (but can be also tuned
62 o some instructions are not copied or register renamed;
63 o conditional jumps are not moved with code duplication;
64 o several jumps in one parallel group are not supported;
65 o when pipelining outer loops, code motion through inner loops
67 o control and data speculation are supported;
68 o some improvements for better compile time/performance were made.
73 A vinsn, or virtual insn, is an insn with additional data characterizing
74 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
75 Vinsns also act as smart pointers to save memory by reusing them in
76 different expressions. A vinsn is described by vinsn_t type.
78 An expression is a vinsn with additional data characterizing its properties
79 at some point in the control flow graph. The data may be its usefulness,
80 priority, speculative status, whether it was renamed/subsituted, etc.
81 An expression is described by expr_t type.
83 Availability set (av_set) is a set of expressions at a given control flow
84 point. It is represented as av_set_t. The expressions in av sets are kept
85 sorted in the terms of expr_greater_p function. It allows to truncate
86 the set while leaving the best expressions.
88 A fence is a point through which code motion is prohibited. On each step,
89 we gather a parallel group of insns at a fence. It is possible to have
90 multiple fences. A fence is represented via fence_t.
92 A boundary is the border between the fence group and the rest of the code.
93 Currently, we never have more than one boundary per fence, as we finalize
94 the fence group when a jump is scheduled. A boundary is represented
100 The scheduler finds regions to schedule, schedules each one, and finalizes.
101 The regions are formed starting from innermost loops, so that when the inner
102 loop is pipelined, its prologue can be scheduled together with yet unprocessed
103 outer loop. The rest of acyclic regions are found using extend_rgns:
104 the blocks that are not yet allocated to any regions are traversed in top-down
105 order, and a block is added to a region to which all its predecessors belong;
106 otherwise, the block starts its own region.
108 The main scheduling loop (sel_sched_region_2) consists of just
109 scheduling on each fence and updating fences. For each fence,
110 we fill a parallel group of insns (fill_insns) until some insns can be added.
111 First, we compute available exprs (av-set) at the boundary of the current
112 group. Second, we choose the best expression from it. If the stall is
113 required to schedule any of the expressions, we advance the current cycle
114 appropriately. So, the final group does not exactly correspond to a VLIW
115 word. Third, we move the chosen expression to the boundary (move_op)
116 and update the intermediate av sets and liveness sets. We quit fill_insns
117 when either no insns left for scheduling or we have scheduled enough insns
118 so we feel like advancing a scheduling point.
120 Computing available expressions
121 ===============================
123 The computation (compute_av_set) is a bottom-up traversal. At each insn,
124 we're moving the union of its successors' sets through it via
125 moveup_expr_set. The dependent expressions are removed. Local
126 transformations (substitution, speculation) are applied to move more
127 exprs. Then the expr corresponding to the current insn is added.
128 The result is saved on each basic block header.
130 When traversing the CFG, we're moving down for no more than max_ws insns.
131 Also, we do not move down to ineligible successors (is_ineligible_successor),
132 which include moving along a back-edge, moving to already scheduled code,
133 and moving to another fence. The first two restrictions are lifted during
134 pipelining, which allows us to move insns along a back-edge. We always have
135 an acyclic region for scheduling because we forbid motion through fences.
137 Choosing the best expression
138 ============================
140 We sort the final availability set via sel_rank_for_schedule, then we remove
141 expressions which are not yet ready (tick_check_p) or which dest registers
142 cannot be used. For some of them, we choose another register via
143 find_best_reg. To do this, we run find_used_regs to calculate the set of
144 registers which cannot be used. The find_used_regs function performs
145 a traversal of code motion paths for an expr. We consider for renaming
146 only registers which are from the same regclass as the original one and
147 using which does not interfere with any live ranges. Finally, we convert
148 the resulting set to the ready list format and use max_issue and reorder*
149 hooks similarly to the Haifa scheduler.
151 Scheduling the best expression
152 ==============================
154 We run the move_op routine to perform the same type of code motion paths
155 traversal as in find_used_regs. (These are working via the same driver,
156 code_motion_path_driver.) When moving down the CFG, we look for original
157 instruction that gave birth to a chosen expression. We undo
158 the transformations performed on an expression via the history saved in it.
159 When found, we remove the instruction or leave a reg-reg copy/speculation
160 check if needed. On a way up, we insert bookkeeping copies at each join
161 point. If a copy is not needed, it will be removed later during this
162 traversal. We update the saved av sets and liveness sets on the way up, too.
164 Finalizing the schedule
165 =======================
167 When pipelining, we reschedule the blocks from which insns were pipelined
168 to get a tighter schedule. On Itanium, we also perform bundling via
169 the same routine from ia64.c.
171 Dependence analysis changes
172 ===========================
174 We augmented the sched-deps.c with hooks that get called when a particular
175 dependence is found in a particular part of an insn. Using these hooks, we
176 can do several actions such as: determine whether an insn can be moved through
177 another (has_dependence_p, moveup_expr); find out whether an insn can be
178 scheduled on the current cycle (tick_check_p); find out registers that
179 are set/used/clobbered by an insn and find out all the strange stuff that
180 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
181 init_global_and_expr_for_insn).
183 Initialization changes
184 ======================
186 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
187 reused in all of the schedulers. We have split up the initialization of data
188 of such parts into different functions prefixed with scheduler type and
189 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
190 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
191 The same splitting is done with current_sched_info structure:
192 dependence-related parts are in sched_deps_info, common part is in
193 common_sched_info, and haifa/sel/etc part is in current_sched_info.
198 As we now have multiple-point scheduling, this would not work with backends
199 which save some of the scheduler state to use it in the target hooks.
200 For this purpose, we introduce a concept of target contexts, which
201 encapsulate such information. The backend should implement simple routines
202 of allocating/freeing/setting such a context. The scheduler calls these
203 as target hooks and handles the target context as an opaque pointer (similar
204 to the DFA state type, state_t).
209 As the correct data dependence graph is not supported during scheduling (which
210 is to be changed in mid-term), we cache as much of the dependence analysis
211 results as possible to avoid reanalyzing. This includes: bitmap caches on
212 each insn in stream of the region saying yes/no for a query with a pair of
213 UIDs; hashtables with the previously done transformations on each insn in
214 stream; a vector keeping a history of transformations on each expr.
216 Also, we try to minimize the dependence context used on each fence to check
217 whether the given expression is ready for scheduling by removing from it
218 insns that are definitely completed the execution. The results of
219 tick_check_p checks are also cached in a vector on each fence.
221 We keep a valid liveness set on each insn in a region to avoid the high
222 cost of recomputation on large basic blocks.
224 Finally, we try to minimize the number of needed updates to the availability
225 sets. The updates happen in two cases: when fill_insns terminates,
226 we advance all fences and increase the stage number to show that the region
227 has changed and the sets are to be recomputed; and when the next iteration
228 of a loop in fill_insns happens (but this one reuses the saved av sets
229 on bb headers.) Thus, we try to break the fill_insns loop only when
230 "significant" number of insns from the current scheduling window was
231 scheduled. This should be made a target param.
234 TODO: correctly support the data dependence graph at all stages and get rid
235 of all caches. This should speed up the scheduler.
236 TODO: implement moving cond jumps with bookkeeping copies on both targets.
237 TODO: tune the scheduler before RA so it does not create too much pseudos.
241 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
242 selective scheduling and software pipelining.
243 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
245 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
246 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
247 for GCC. In Proceedings of GCC Developers' Summit 2006.
249 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
250 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
251 http://rogue.colorado.edu/EPIC7/.
255 /* True when pipelining is enabled. */
258 /* True if bookkeeping is enabled. */
261 /* Maximum number of insns that are eligible for renaming. */
262 int max_insns_to_rename;
265 /* Definitions of local types and macros. */
267 /* Represents possible outcomes of moving an expression through an insn. */
268 enum MOVEUP_EXPR_CODE
270 /* The expression is not changed. */
273 /* Not changed, but requires a new destination register. */
276 /* Cannot be moved. */
279 /* Changed (substituted or speculated). */
283 /* The container to be passed into rtx search & replace functions. */
284 struct rtx_search_arg
286 /* What we are searching for. */
289 /* The occurence counter. */
293 typedef struct rtx_search_arg *rtx_search_arg_p;
295 /* This struct contains precomputed hard reg sets that are needed when
296 computing registers available for renaming. */
297 struct hard_regs_data
299 /* For every mode, this stores registers available for use with
301 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
303 /* True when regs_for_mode[mode] is initialized. */
304 bool regs_for_mode_ok[NUM_MACHINE_MODES];
306 /* For every register, it has regs that are ok to rename into it.
307 The register in question is always set. If not, this means
308 that the whole set is not computed yet. */
309 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
311 /* For every mode, this stores registers not available due to
313 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
315 /* All registers that are used or call used. */
316 HARD_REG_SET regs_ever_used;
319 /* Stack registers. */
320 HARD_REG_SET stack_regs;
324 /* Holds the results of computation of available for renaming and
325 unavailable hard registers. */
328 /* These are unavailable due to calls crossing, globalness, etc. */
329 HARD_REG_SET unavailable_hard_regs;
331 /* These are *available* for renaming. */
332 HARD_REG_SET available_for_renaming;
334 /* Whether this code motion path crosses a call. */
338 /* A global structure that contains the needed information about harg
340 static struct hard_regs_data sel_hrd;
343 /* This structure holds local data used in code_motion_path_driver hooks on
344 the same or adjacent levels of recursion. Here we keep those parameters
345 that are not used in code_motion_path_driver routine itself, but only in
346 its hooks. Moreover, all parameters that can be modified in hooks are
347 in this structure, so all other parameters passed explicitly to hooks are
349 struct cmpd_local_params
351 /* Local params used in move_op_* functions. */
353 /* Edges for bookkeeping generation. */
356 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
357 expr_t c_expr_merged, c_expr_local;
359 /* Local params used in fur_* functions. */
360 /* Copy of the ORIGINAL_INSN list, stores the original insns already
361 found before entering the current level of code_motion_path_driver. */
362 def_list_t old_original_insns;
364 /* Local params used in move_op_* functions. */
365 /* True when we have removed last insn in the block which was
366 also a boundary. Do not update anything or create bookkeeping copies. */
367 BOOL_BITFIELD removed_last_insn : 1;
370 /* Stores the static parameters for move_op_* calls. */
371 struct moveop_static_params
373 /* Destination register. */
376 /* Current C_EXPR. */
379 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
380 they are to be removed. */
383 #ifdef ENABLE_CHECKING
384 /* This is initialized to the insn on which the driver stopped its traversal. */
388 /* True if we scheduled an insn with different register. */
392 /* Stores the static parameters for fur_* calls. */
393 struct fur_static_params
395 /* Set of registers unavailable on the code motion path. */
398 /* Pointer to the list of original insns definitions. */
399 def_list_t *original_insns;
401 /* True if a code motion path contains a CALL insn. */
405 typedef struct fur_static_params *fur_static_params_p;
406 typedef struct cmpd_local_params *cmpd_local_params_p;
407 typedef struct moveop_static_params *moveop_static_params_p;
409 /* Set of hooks and parameters that determine behaviour specific to
410 move_op or find_used_regs functions. */
411 struct code_motion_path_driver_info_def
413 /* Called on enter to the basic block. */
414 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
416 /* Called when original expr is found. */
417 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
419 /* Called while descending current basic block if current insn is not
420 the original EXPR we're searching for. */
421 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
423 /* Function to merge C_EXPRes from different successors. */
424 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
426 /* Function to finalize merge from different successors and possibly
427 deallocate temporary data structures used for merging. */
428 void (*after_merge_succs) (cmpd_local_params_p, void *);
430 /* Called on the backward stage of recursion to do moveup_expr.
431 Used only with move_op_*. */
432 void (*ascend) (insn_t, void *);
434 /* Called on the ascending pass, before returning from the current basic
435 block or from the whole traversal. */
436 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
438 /* When processing successors in move_op we need only descend into
439 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
442 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
443 const char *routine_name;
446 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
448 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
450 /* Set of hooks for performing move_op and find_used_regs routines with
451 code_motion_path_driver. */
452 extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
454 /* True if/when we want to emulate Haifa scheduler in the common code.
455 This is used in sched_rgn_local_init and in various places in
457 int sched_emulate_haifa_p;
459 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
460 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
461 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
462 scheduling window. */
465 /* Current fences. */
468 /* True when separable insns should be scheduled as RHSes. */
469 static bool enable_schedule_as_rhs_p;
471 /* Used in verify_target_availability to assert that target reg is reported
472 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
473 we haven't scheduled anything on the previous fence.
474 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
475 have more conservative value than the one returned by the
476 find_used_regs, thus we shouldn't assert that these values are equal. */
477 static bool scheduled_something_on_previous_fence;
479 /* All newly emitted insns will have their uids greater than this value. */
480 static int first_emitted_uid;
482 /* Set of basic blocks that are forced to start new ebbs. This is a subset
483 of all the ebb heads. */
484 static bitmap_head _forced_ebb_heads;
485 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
487 /* Blocks that need to be rescheduled after pipelining. */
488 bitmap blocks_to_reschedule = NULL;
490 /* True when the first lv set should be ignored when updating liveness. */
491 static bool ignore_first = false;
493 /* Number of insns max_issue has initialized data structures for. */
494 static int max_issue_size = 0;
496 /* Whether we can issue more instructions. */
497 static int can_issue_more;
499 /* Maximum software lookahead window size, reduced when rescheduling after
503 /* Number of insns scheduled in current region. */
504 static int num_insns_scheduled;
506 /* A vector of expressions is used to be able to sort them. */
508 DEF_VEC_ALLOC_P(expr_t,heap);
509 static VEC(expr_t, heap) *vec_av_set = NULL;
511 /* A vector of vinsns is used to hold temporary lists of vinsns. */
513 DEF_VEC_ALLOC_P(vinsn_t,heap);
514 typedef VEC(vinsn_t, heap) *vinsn_vec_t;
516 /* This vector has the exprs which may still present in av_sets, but actually
517 can't be moved up due to bookkeeping created during code motion to another
518 fence. See comment near the call to update_and_record_unavailable_insns
519 for the detailed explanations. */
520 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = NULL;
522 /* This vector has vinsns which are scheduled with renaming on the first fence
523 and then seen on the second. For expressions with such vinsns, target
524 availability information may be wrong. */
525 static vinsn_vec_t vec_target_unavailable_vinsns = NULL;
527 /* Vector to store temporary nops inserted in move_op to prevent removal
530 DEF_VEC_ALLOC_P(insn_t,heap);
531 static VEC(insn_t, heap) *vec_temp_moveop_nops = NULL;
533 /* These bitmaps record original instructions scheduled on the current
534 iteration and bookkeeping copies created by them. */
535 static bitmap current_originators = NULL;
536 static bitmap current_copies = NULL;
538 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
539 visit them afterwards. */
540 static bitmap code_motion_visited_blocks = NULL;
542 /* Variables to accumulate different statistics. */
544 /* The number of bookkeeping copies created. */
545 static int stat_bookkeeping_copies;
547 /* The number of insns that required bookkeeiping for their scheduling. */
548 static int stat_insns_needed_bookkeeping;
550 /* The number of insns that got renamed. */
551 static int stat_renamed_scheduled;
553 /* The number of substitutions made during scheduling. */
554 static int stat_substitutions_total;
557 /* Forward declarations of static functions. */
558 static bool rtx_ok_for_substitution_p (rtx, rtx);
559 static int sel_rank_for_schedule (const void *, const void *);
560 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
561 static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax);
563 static rtx get_dest_from_orig_ops (av_set_t);
564 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
565 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
567 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
568 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
569 cmpd_local_params_p, void *);
570 static void sel_sched_region_1 (void);
571 static void sel_sched_region_2 (int);
572 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
574 static void debug_state (state_t);
577 /* Functions that work with fences. */
579 /* Advance one cycle on FENCE. */
581 advance_one_cycle (fence_t fence)
587 advance_state (FENCE_STATE (fence));
588 cycle = ++FENCE_CYCLE (fence);
589 FENCE_ISSUED_INSNS (fence) = 0;
590 FENCE_STARTS_CYCLE_P (fence) = 1;
591 can_issue_more = issue_rate;
592 FENCE_ISSUE_MORE (fence) = can_issue_more;
594 for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); )
596 if (INSN_READY_CYCLE (insn) < cycle)
598 remove_from_deps (FENCE_DC (fence), insn);
599 VEC_unordered_remove (rtx, FENCE_EXECUTING_INSNS (fence), i);
604 if (sched_verbose >= 2)
606 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
607 debug_state (FENCE_STATE (fence));
611 /* Returns true when SUCC in a fallthru bb of INSN, possibly
612 skipping empty basic blocks. */
614 in_fallthru_bb_p (rtx insn, rtx succ)
616 basic_block bb = BLOCK_FOR_INSN (insn);
619 if (bb == BLOCK_FOR_INSN (succ))
622 e = find_fallthru_edge_from (bb);
628 while (sel_bb_empty_p (bb))
631 return bb == BLOCK_FOR_INSN (succ);
634 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
635 When a successor will continue a ebb, transfer all parameters of a fence
636 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
637 of scheduling helping to distinguish between the old and the new code. */
639 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
642 bool was_here_p = false;
643 insn_t insn = NULL_RTX;
647 fence_t fence = FLIST_FENCE (old_fences);
650 /* Get the only element of FENCE_BNDS (fence). */
651 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
653 gcc_assert (!was_here_p);
656 gcc_assert (was_here_p && insn != NULL_RTX);
658 /* When in the "middle" of the block, just move this fence
660 bb = BLOCK_FOR_INSN (insn);
661 if (! sel_bb_end_p (insn)
662 || (single_succ_p (bb)
663 && single_pred_p (single_succ (bb))))
667 succ = (sel_bb_end_p (insn)
668 ? sel_bb_head (single_succ (bb))
671 if (INSN_SEQNO (succ) > 0
672 && INSN_SEQNO (succ) <= orig_max_seqno
673 && INSN_SCHED_TIMES (succ) <= 0)
675 FENCE_INSN (fence) = succ;
676 move_fence_to_fences (old_fences, new_fences);
678 if (sched_verbose >= 1)
679 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
680 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
685 /* Otherwise copy fence's structures to (possibly) multiple successors. */
686 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
688 int seqno = INSN_SEQNO (succ);
690 if (0 < seqno && seqno <= orig_max_seqno
691 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
693 bool b = (in_same_ebb_p (insn, succ)
694 || in_fallthru_bb_p (insn, succ));
696 if (sched_verbose >= 1)
697 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
698 INSN_UID (insn), INSN_UID (succ),
699 BLOCK_NUM (succ), b ? "continue" : "reset");
702 add_dirty_fence_to_fences (new_fences, succ, fence);
705 /* Mark block of the SUCC as head of the new ebb. */
706 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
707 add_clean_fence_to_fences (new_fences, succ, fence);
714 /* Functions to support substitution. */
716 /* Returns whether INSN with dependence status DS is eligible for
717 substitution, i.e. it's a copy operation x := y, and RHS that is
718 moved up through this insn should be substituted. */
720 can_substitute_through_p (insn_t insn, ds_t ds)
722 /* We can substitute only true dependencies. */
723 if ((ds & DEP_OUTPUT)
726 || ! INSN_LHS (insn))
729 /* Now we just need to make sure the INSN_RHS consists of only one
731 if (REG_P (INSN_LHS (insn))
732 && REG_P (INSN_RHS (insn)))
737 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
738 source (if INSN is eligible for substitution). Returns TRUE if
739 substitution was actually performed, FALSE otherwise. Substitution might
740 be not performed because it's either EXPR' vinsn doesn't contain INSN's
741 destination or the resulting insn is invalid for the target machine.
742 When UNDO is true, perform unsubstitution instead (the difference is in
743 the part of rtx on which validate_replace_rtx is called). */
745 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
749 vinsn_t *vi = &EXPR_VINSN (expr);
750 bool has_rhs = VINSN_RHS (*vi) != NULL;
753 /* Do not try to replace in SET_DEST. Although we'll choose new
754 register for the RHS, we don't want to change RHS' original reg.
755 If the insn is not SET, we may still be able to substitute something
756 in it, and if we're here (don't have deps), it doesn't write INSN's
760 : &PATTERN (VINSN_INSN_RTX (*vi)));
761 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
763 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
764 if (rtx_ok_for_substitution_p (old, *where))
769 /* We should copy these rtxes before substitution. */
770 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
771 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
773 /* Where we'll replace.
774 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
775 used instead of SET_SRC. */
776 where_replace = (has_rhs
777 ? &SET_SRC (PATTERN (new_insn))
778 : &PATTERN (new_insn));
781 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
784 /* ??? Actually, constrain_operands result depends upon choice of
785 destination register. E.g. if we allow single register to be an rhs,
786 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
787 in invalid insn dx=dx, so we'll loose this rhs here.
788 Just can't come up with significant testcase for this, so just
789 leaving it for now. */
792 change_vinsn_in_expr (expr,
793 create_vinsn_from_insn_rtx (new_insn, false));
795 /* Do not allow clobbering the address register of speculative
797 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
798 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr)),
799 expr_dest_regno (expr)))
800 EXPR_TARGET_AVAILABLE (expr) = false;
811 /* Helper function for count_occurences_equiv. */
813 count_occurrences_1 (rtx *cur_rtx, void *arg)
815 rtx_search_arg_p p = (rtx_search_arg_p) arg;
817 /* The last param FOR_GCSE is true, because otherwise it performs excessive
821 for the last insn it presumes r33 equivalent to r8, so it changes it to
822 r33. Actually, there's no change, but it spoils debugging. */
823 if (exp_equiv_p (*cur_rtx, p->x, 0, true))
825 /* Bail out if we occupy more than one register. */
827 && HARD_REGISTER_P (*cur_rtx)
828 && hard_regno_nregs[REGNO(*cur_rtx)][GET_MODE (*cur_rtx)] > 1)
836 /* Do not traverse subexprs. */
840 if (GET_CODE (*cur_rtx) == SUBREG
842 && (!REG_P (SUBREG_REG (*cur_rtx))
843 || REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x)))
845 /* ??? Do not support substituting regs inside subregs. In that case,
846 simplify_subreg will be called by validate_replace_rtx, and
847 unsubstitution will fail later. */
852 /* Continue search. */
856 /* Return the number of places WHAT appears within WHERE.
857 Bail out when we found a reference occupying several hard registers. */
859 count_occurrences_equiv (rtx what, rtx where)
861 struct rtx_search_arg arg;
866 for_each_rtx (&where, &count_occurrences_1, (void *) &arg);
871 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
873 rtx_ok_for_substitution_p (rtx what, rtx where)
875 return (count_occurrences_equiv (what, where) > 0);
879 /* Functions to support register renaming. */
881 /* Substitute VI's set source with REGNO. Returns newly created pattern
882 that has REGNO as its source. */
884 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
890 lhs_rtx = copy_rtx (VINSN_LHS (vi));
892 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
893 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
898 /* Returns whether INSN's src can be replaced with register number
899 NEW_SRC_REG. E.g. the following insn is valid for i386:
901 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
902 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
903 (reg:SI 0 ax [orig:770 c1 ] [770]))
904 (const_int 288 [0x120])) [0 str S1 A8])
905 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
908 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
909 because of operand constraints:
911 (define_insn "*movqi_1"
912 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
913 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
916 So do constrain_operands here, before choosing NEW_SRC_REG as best
920 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
922 vinsn_t vi = INSN_VINSN (insn);
923 enum machine_mode mode;
927 gcc_assert (VINSN_SEPARABLE_P (vi));
929 get_dest_and_mode (insn, &dst_loc, &mode);
930 gcc_assert (mode == GET_MODE (new_src_reg));
932 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
935 /* See whether SET_SRC can be replaced with this register. */
936 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
937 res = verify_changes (0);
943 /* Returns whether INSN still be valid after replacing it's DEST with
946 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
948 vinsn_t vi = INSN_VINSN (insn);
951 /* We should deal here only with separable insns. */
952 gcc_assert (VINSN_SEPARABLE_P (vi));
953 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
955 /* See whether SET_DEST can be replaced with this register. */
956 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
957 res = verify_changes (0);
963 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
965 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
971 rhs_rtx = copy_rtx (VINSN_RHS (vi));
973 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
974 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
979 /* Substitute lhs in the given expression EXPR for the register with number
980 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
982 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
987 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
988 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
990 change_vinsn_in_expr (expr, vinsn);
991 EXPR_WAS_RENAMED (expr) = 1;
992 EXPR_TARGET_AVAILABLE (expr) = 1;
995 /* Returns whether VI writes either one of the USED_REGS registers or,
996 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
998 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
999 HARD_REG_SET unavailable_hard_regs)
1002 reg_set_iterator rsi;
1004 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
1006 if (REGNO_REG_SET_P (used_regs, regno))
1008 if (HARD_REGISTER_NUM_P (regno)
1009 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1013 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
1015 if (REGNO_REG_SET_P (used_regs, regno))
1017 if (HARD_REGISTER_NUM_P (regno)
1018 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1025 /* Returns register class of the output register in INSN.
1026 Returns NO_REGS for call insns because some targets have constraints on
1027 destination register of a call insn.
1029 Code adopted from regrename.c::build_def_use. */
1030 static enum reg_class
1031 get_reg_class (rtx insn)
1035 extract_insn (insn);
1036 if (! constrain_operands (1))
1037 fatal_insn_not_found (insn);
1038 preprocess_constraints ();
1039 alt = which_alternative;
1040 n_ops = recog_data.n_operands;
1042 for (i = 0; i < n_ops; ++i)
1044 int matches = recog_op_alt[i][alt].matches;
1046 recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;
1049 if (asm_noperands (PATTERN (insn)) > 0)
1051 for (i = 0; i < n_ops; i++)
1052 if (recog_data.operand_type[i] == OP_OUT)
1054 rtx *loc = recog_data.operand_loc[i];
1056 enum reg_class cl = recog_op_alt[i][alt].cl;
1059 && REGNO (op) == ORIGINAL_REGNO (op))
1065 else if (!CALL_P (insn))
1067 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1069 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1070 enum reg_class cl = recog_op_alt[opn][alt].cl;
1072 if (recog_data.operand_type[opn] == OP_OUT ||
1073 recog_data.operand_type[opn] == OP_INOUT)
1079 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1080 may result in returning NO_REGS, cause flags is written implicitly through
1081 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1085 #ifdef HARD_REGNO_RENAME_OK
1086 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1088 init_hard_regno_rename (int regno)
1092 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1094 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1096 /* We are not interested in renaming in other regs. */
1097 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1100 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1101 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1106 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1109 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1111 #ifdef HARD_REGNO_RENAME_OK
1112 /* Check whether this is all calculated. */
1113 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1114 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1116 init_hard_regno_rename (from);
1118 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1124 /* Calculate set of registers that are capable of holding MODE. */
1126 init_regs_for_mode (enum machine_mode mode)
1130 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1131 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1133 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1135 int nregs = hard_regno_nregs[cur_reg][mode];
1138 for (i = nregs - 1; i >= 0; --i)
1139 if (fixed_regs[cur_reg + i]
1140 || global_regs[cur_reg + i]
1141 /* Can't use regs which aren't saved by
1143 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1144 /* Can't use regs with non-null REG_BASE_VALUE, because adjusting
1145 it affects aliasing globally and invalidates all AV sets. */
1146 || get_reg_base_value (cur_reg + i)
1147 #ifdef LEAF_REGISTERS
1148 /* We can't use a non-leaf register if we're in a
1150 || (current_function_is_leaf
1151 && !LEAF_REGISTERS[cur_reg + i])
1159 /* See whether it accepts all modes that occur in
1161 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1164 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1165 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1168 /* If the CUR_REG passed all the checks above,
1170 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1173 sel_hrd.regs_for_mode_ok[mode] = true;
1176 /* Init all register sets gathered in HRD. */
1178 init_hard_regs_data (void)
1183 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1184 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1185 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1186 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1188 /* Initialize registers that are valid based on mode when this is
1190 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1191 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1193 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1194 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1195 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1198 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1200 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1201 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1205 /* Mark hardware regs in REG_RENAME_P that are not suitable
1206 for renaming rhs in INSN due to hardware restrictions (register class,
1207 modes compatibility etc). This doesn't affect original insn's dest reg,
1208 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1209 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1210 Registers that are in used_regs are always marked in
1211 unavailable_hard_regs as well. */
1214 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1215 regset used_regs ATTRIBUTE_UNUSED)
1217 enum machine_mode mode;
1218 enum reg_class cl = NO_REGS;
1220 unsigned cur_reg, regno;
1221 hard_reg_set_iterator hrsi;
1223 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1224 gcc_assert (reg_rename_p);
1226 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1228 /* We have decided not to rename 'mem = something;' insns, as 'something'
1229 is usually a register. */
1230 if (!REG_P (orig_dest))
1233 regno = REGNO (orig_dest);
1235 /* If before reload, don't try to work with pseudos. */
1236 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1239 if (reload_completed)
1240 cl = get_reg_class (def->orig_insn);
1242 /* Stop if the original register is one of the fixed_regs, global_regs or
1243 frame pointer, or we could not discover its class. */
1244 if (fixed_regs[regno]
1245 || global_regs[regno]
1246 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1247 || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
1249 || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
1251 || (reload_completed && cl == NO_REGS))
1253 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1255 /* Give a chance for original register, if it isn't in used_regs. */
1256 if (!def->crosses_call)
1257 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1262 /* If something allocated on stack in this function, mark frame pointer
1263 register unavailable, considering also modes.
1264 FIXME: it is enough to do this once per all original defs. */
1265 if (frame_pointer_needed)
1269 for (i = hard_regno_nregs[FRAME_POINTER_REGNUM][Pmode]; i--;)
1270 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1271 FRAME_POINTER_REGNUM + i);
1273 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1274 for (i = hard_regno_nregs[HARD_FRAME_POINTER_REGNUM][Pmode]; i--;)
1275 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1276 HARD_FRAME_POINTER_REGNUM + i);
1281 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1282 is equivalent to as if all stack regs were in this set.
1283 I.e. no stack register can be renamed, and even if it's an original
1284 register here we make sure it won't be lifted over it's previous def
1285 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1286 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1287 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1288 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1289 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1290 sel_hrd.stack_regs);
1293 /* If there's a call on this path, make regs from call_used_reg_set
1295 if (def->crosses_call)
1296 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1299 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1300 but not register classes. */
1301 if (!reload_completed)
1304 /* Leave regs as 'available' only from the current
1306 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1307 reg_class_contents[cl]);
1309 mode = GET_MODE (orig_dest);
1311 /* Leave only registers available for this mode. */
1312 if (!sel_hrd.regs_for_mode_ok[mode])
1313 init_regs_for_mode (mode);
1314 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1315 sel_hrd.regs_for_mode[mode]);
1317 /* Exclude registers that are partially call clobbered. */
1318 if (def->crosses_call
1319 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1320 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1321 sel_hrd.regs_for_call_clobbered[mode]);
1323 /* Leave only those that are ok to rename. */
1324 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1330 nregs = hard_regno_nregs[cur_reg][mode];
1331 gcc_assert (nregs > 0);
1333 for (i = nregs - 1; i >= 0; --i)
1334 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1338 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1342 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1343 reg_rename_p->unavailable_hard_regs);
1345 /* Regno is always ok from the renaming part of view, but it really
1346 could be in *unavailable_hard_regs already, so set it here instead
1348 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1351 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1352 best register more recently than REG2. */
1353 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1355 /* Indicates the number of times renaming happened before the current one. */
1356 static int reg_rename_this_tick;
1358 /* Choose the register among free, that is suitable for storing
1361 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1362 originally appears. There could be multiple original operations
1363 for single rhs since we moving it up and merging along different
1366 Some code is adapted from regrename.c (regrename_optimize).
1367 If original register is available, function returns it.
1368 Otherwise it performs the checks, so the new register should
1369 comply with the following:
1370 - it should not violate any live ranges (such registers are in
1371 REG_RENAME_P->available_for_renaming set);
1372 - it should not be in the HARD_REGS_USED regset;
1373 - it should be in the class compatible with original uses;
1374 - it should not be clobbered through reference with different mode;
1375 - if we're in the leaf function, then the new register should
1376 not be in the LEAF_REGISTERS;
1379 If several registers meet the conditions, the register with smallest
1380 tick is returned to achieve more even register allocation.
1382 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1384 If no register satisfies the above conditions, NULL_RTX is returned. */
1386 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1387 struct reg_rename *reg_rename_p,
1388 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1392 enum machine_mode mode = VOIDmode;
1393 unsigned regno, i, n;
1394 hard_reg_set_iterator hrsi;
1395 def_list_iterator di;
1398 /* If original register is available, return it. */
1399 *is_orig_reg_p_ptr = true;
1401 FOR_EACH_DEF (def, di, original_insns)
1403 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1405 gcc_assert (REG_P (orig_dest));
1407 /* Check that all original operations have the same mode.
1408 This is done for the next loop; if we'd return from this
1409 loop, we'd check only part of them, but in this case
1410 it doesn't matter. */
1411 if (mode == VOIDmode)
1412 mode = GET_MODE (orig_dest);
1413 gcc_assert (mode == GET_MODE (orig_dest));
1415 regno = REGNO (orig_dest);
1416 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1417 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1420 /* All hard registers are available. */
1423 gcc_assert (mode != VOIDmode);
1425 /* Hard registers should not be shared. */
1426 return gen_rtx_REG (mode, regno);
1430 *is_orig_reg_p_ptr = false;
1433 /* Among all available regs choose the register that was
1434 allocated earliest. */
1435 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1437 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1439 /* Check that all hard regs for mode are available. */
1440 for (i = 1, n = hard_regno_nregs[cur_reg][mode]; i < n; i++)
1441 if (TEST_HARD_REG_BIT (hard_regs_used, cur_reg + i)
1442 || !TEST_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1449 /* All hard registers are available. */
1450 if (best_new_reg < 0
1451 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1453 best_new_reg = cur_reg;
1455 /* Return immediately when we know there's no better reg. */
1456 if (! reg_rename_tick[best_new_reg])
1461 if (best_new_reg >= 0)
1463 /* Use the check from the above loop. */
1464 gcc_assert (mode != VOIDmode);
1465 return gen_rtx_REG (mode, best_new_reg);
1471 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1472 assumptions about available registers in the function. */
1474 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1475 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1477 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1478 original_insns, is_orig_reg_p_ptr);
1480 /* FIXME loop over hard_regno_nregs here. */
1481 gcc_assert (best_reg == NULL_RTX
1482 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1487 /* Choose the pseudo register for storing rhs value. As this is supposed
1488 to work before reload, we return either the original register or make
1489 the new one. The parameters are the same that in choose_nest_reg_1
1490 functions, except that USED_REGS may contain pseudos.
1491 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1493 TODO: take into account register pressure while doing this. Up to this
1494 moment, this function would never return NULL for pseudos, but we should
1495 not rely on this. */
1497 choose_best_pseudo_reg (regset used_regs,
1498 struct reg_rename *reg_rename_p,
1499 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1501 def_list_iterator i;
1503 enum machine_mode mode = VOIDmode;
1504 bool bad_hard_regs = false;
1506 /* We should not use this after reload. */
1507 gcc_assert (!reload_completed);
1509 /* If original register is available, return it. */
1510 *is_orig_reg_p_ptr = true;
1512 FOR_EACH_DEF (def, i, original_insns)
1514 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1517 gcc_assert (REG_P (dest));
1519 /* Check that all original operations have the same mode. */
1520 if (mode == VOIDmode)
1521 mode = GET_MODE (dest);
1523 gcc_assert (mode == GET_MODE (dest));
1524 orig_regno = REGNO (dest);
1526 if (!REGNO_REG_SET_P (used_regs, orig_regno))
1528 if (orig_regno < FIRST_PSEUDO_REGISTER)
1530 gcc_assert (df_regs_ever_live_p (orig_regno));
1532 /* For hard registers, we have to check hardware imposed
1533 limitations (frame/stack registers, calls crossed). */
1534 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1537 /* Don't let register cross a call if it doesn't already
1538 cross one. This condition is written in accordance with
1539 that in sched-deps.c sched_analyze_reg(). */
1540 if (!reg_rename_p->crosses_call
1541 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1542 return gen_rtx_REG (mode, orig_regno);
1545 bad_hard_regs = true;
1552 *is_orig_reg_p_ptr = false;
1554 /* We had some original hard registers that couldn't be used.
1555 Those were likely special. Don't try to create a pseudo. */
1559 /* We haven't found a register from original operations. Get a new one.
1560 FIXME: control register pressure somehow. */
1562 rtx new_reg = gen_reg_rtx (mode);
1564 gcc_assert (mode != VOIDmode);
1566 max_regno = max_reg_num ();
1567 maybe_extend_reg_info_p ();
1568 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1574 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1575 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1577 verify_target_availability (expr_t expr, regset used_regs,
1578 struct reg_rename *reg_rename_p)
1580 unsigned n, i, regno;
1581 enum machine_mode mode;
1582 bool target_available, live_available, hard_available;
1584 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1587 regno = expr_dest_regno (expr);
1588 mode = GET_MODE (EXPR_LHS (expr));
1589 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1590 n = reload_completed ? hard_regno_nregs[regno][mode] : 1;
1592 live_available = hard_available = true;
1593 for (i = 0; i < n; i++)
1595 if (bitmap_bit_p (used_regs, regno + i))
1596 live_available = false;
1597 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1598 hard_available = false;
1601 /* When target is not available, it may be due to hard register
1602 restrictions, e.g. crosses calls, so we check hard_available too. */
1603 if (target_available)
1604 gcc_assert (live_available);
1606 /* Check only if we haven't scheduled something on the previous fence,
1607 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1608 and having more than one fence, we may end having targ_un in a block
1609 in which successors target register is actually available.
1611 The last condition handles the case when a dependence from a call insn
1612 was created in sched-deps.c for insns with destination registers that
1613 never crossed a call before, but do cross one after our code motion.
1615 FIXME: in the latter case, we just uselessly called find_used_regs,
1616 because we can't move this expression with any other register
1618 gcc_assert (scheduled_something_on_previous_fence || !live_available
1620 || (!reload_completed && reg_rename_p->crosses_call
1621 && REG_N_CALLS_CROSSED (regno) == 0));
1624 /* Collect unavailable registers due to liveness for EXPR from BNDS
1625 into USED_REGS. Save additional information about available
1626 registers and unavailable due to hardware restriction registers
1627 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1630 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1631 struct reg_rename *reg_rename_p,
1632 def_list_t *original_insns)
1634 for (; bnds; bnds = BLIST_NEXT (bnds))
1637 av_set_t orig_ops = NULL;
1638 bnd_t bnd = BLIST_BND (bnds);
1640 /* If the chosen best expr doesn't belong to current boundary,
1642 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1645 /* Put in ORIG_OPS all exprs from this boundary that became
1647 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1649 /* Compute used regs and OR it into the USED_REGS. */
1650 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1651 reg_rename_p, original_insns);
1653 /* FIXME: the assert is true until we'd have several boundaries. */
1655 av_set_clear (&orig_ops);
1659 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1660 If BEST_REG is valid, replace LHS of EXPR with it. */
1662 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1664 /* Try whether we'll be able to generate the insn
1665 'dest := best_reg' at the place of the original operation. */
1666 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1668 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1670 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1672 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1673 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1674 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1678 /* Make sure that EXPR has the right destination
1680 if (expr_dest_regno (expr) != REGNO (best_reg))
1681 replace_dest_with_reg_in_expr (expr, best_reg);
1683 EXPR_TARGET_AVAILABLE (expr) = 1;
1688 /* Select and assign best register to EXPR searching from BNDS.
1689 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1690 Return FALSE if no register can be chosen, which could happen when:
1691 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1692 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1693 that are used on the moving path. */
1695 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1697 static struct reg_rename reg_rename_data;
1700 def_list_t original_insns = NULL;
1703 *is_orig_reg_p = false;
1705 /* Don't bother to do anything if this insn doesn't set any registers. */
1706 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1707 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1710 used_regs = get_clear_regset_from_pool ();
1711 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1713 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data,
1716 #ifdef ENABLE_CHECKING
1717 /* If after reload, make sure we're working with hard regs here. */
1718 if (reload_completed)
1720 reg_set_iterator rsi;
1723 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1728 if (EXPR_SEPARABLE_P (expr))
1730 rtx best_reg = NULL_RTX;
1731 /* Check that we have computed availability of a target register
1733 verify_target_availability (expr, used_regs, ®_rename_data);
1735 /* Turn everything in hard regs after reload. */
1736 if (reload_completed)
1738 HARD_REG_SET hard_regs_used;
1739 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1741 /* Join hard registers unavailable due to register class
1742 restrictions and live range intersection. */
1743 IOR_HARD_REG_SET (hard_regs_used,
1744 reg_rename_data.unavailable_hard_regs);
1746 best_reg = choose_best_reg (hard_regs_used, ®_rename_data,
1747 original_insns, is_orig_reg_p);
1750 best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data,
1751 original_insns, is_orig_reg_p);
1755 else if (*is_orig_reg_p)
1757 /* In case of unification BEST_REG may be different from EXPR's LHS
1758 when EXPR's LHS is unavailable, and there is another LHS among
1760 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1764 /* Forbid renaming of low-cost insns. */
1765 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1768 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1773 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1774 any of the HARD_REGS_USED set. */
1775 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1776 reg_rename_data.unavailable_hard_regs))
1779 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1784 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1788 ilist_clear (&original_insns);
1789 return_regset_to_pool (used_regs);
1795 /* Return true if dependence described by DS can be overcomed. */
1797 can_speculate_dep_p (ds_t ds)
1799 if (spec_info == NULL)
1802 /* Leave only speculative data. */
1809 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1810 that we can overcome. */
1811 ds_t spec_mask = spec_info->mask;
1813 if ((ds & spec_mask) != ds)
1817 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1823 /* Get a speculation check instruction.
1824 C_EXPR is a speculative expression,
1825 CHECK_DS describes speculations that should be checked,
1826 ORIG_INSN is the original non-speculative insn in the stream. */
1828 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1833 basic_block recovery_block;
1836 /* Create a recovery block if target is going to emit branchy check, or if
1837 ORIG_INSN was speculative already. */
1838 if (targetm.sched.needs_block_p (check_ds)
1839 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1841 recovery_block = sel_create_recovery_block (orig_insn);
1842 label = BB_HEAD (recovery_block);
1846 recovery_block = NULL;
1850 /* Get pattern of the check. */
1851 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1854 gcc_assert (check_pattern != NULL);
1857 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1859 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1860 INSN_SEQNO (orig_insn), orig_insn);
1862 /* Make check to be non-speculative. */
1863 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1864 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1866 /* Decrease priority of check by difference of load/check instruction
1868 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1869 - sel_vinsn_cost (INSN_VINSN (insn)));
1871 /* Emit copy of original insn (though with replaced target register,
1872 if needed) to the recovery block. */
1873 if (recovery_block != NULL)
1877 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1878 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1879 sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1880 INSN_EXPR (orig_insn),
1882 bb_note (recovery_block));
1885 /* If we've generated a data speculation check, make sure
1886 that all the bookkeeping instruction we'll create during
1887 this move_op () will allocate an ALAT entry so that the
1889 In case of control speculation we must convert C_EXPR to control
1890 speculative mode, because failing to do so will bring us an exception
1891 thrown by the non-control-speculative load. */
1892 check_ds = ds_get_max_dep_weak (check_ds);
1893 speculate_expr (c_expr, check_ds);
1898 /* True when INSN is a "regN = regN" copy. */
1900 identical_copy_p (rtx insn)
1904 pat = PATTERN (insn);
1906 if (GET_CODE (pat) != SET)
1909 lhs = SET_DEST (pat);
1913 rhs = SET_SRC (pat);
1917 return REGNO (lhs) == REGNO (rhs);
1920 /* Undo all transformations on *AV_PTR that were done when
1921 moving through INSN. */
1923 undo_transformations (av_set_t *av_ptr, rtx insn)
1925 av_set_iterator av_iter;
1927 av_set_t new_set = NULL;
1929 /* First, kill any EXPR that uses registers set by an insn. This is
1930 required for correctness. */
1931 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1932 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1933 && bitmap_intersect_p (INSN_REG_SETS (insn),
1934 VINSN_REG_USES (EXPR_VINSN (expr)))
1935 /* When an insn looks like 'r1 = r1', we could substitute through
1936 it, but the above condition will still hold. This happened with
1937 gcc.c-torture/execute/961125-1.c. */
1938 && !identical_copy_p (insn))
1940 if (sched_verbose >= 6)
1941 sel_print ("Expr %d removed due to use/set conflict\n",
1942 INSN_UID (EXPR_INSN_RTX (expr)));
1943 av_set_iter_remove (&av_iter);
1946 /* Undo transformations looking at the history vector. */
1947 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1949 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1950 insn, EXPR_VINSN (expr), true);
1954 expr_history_def *phist;
1956 phist = VEC_index (expr_history_def,
1957 EXPR_HISTORY_OF_CHANGES (expr),
1960 switch (phist->type)
1962 case TRANS_SPECULATION:
1964 ds_t old_ds, new_ds;
1966 /* Compute the difference between old and new speculative
1967 statuses: that's what we need to check.
1968 Earlier we used to assert that the status will really
1969 change. This no longer works because only the probability
1970 bits in the status may have changed during compute_av_set,
1971 and in the case of merging different probabilities of the
1972 same speculative status along different paths we do not
1973 record this in the history vector. */
1974 old_ds = phist->spec_ds;
1975 new_ds = EXPR_SPEC_DONE_DS (expr);
1977 old_ds &= SPECULATIVE;
1978 new_ds &= SPECULATIVE;
1981 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1984 case TRANS_SUBSTITUTION:
1986 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1990 new_vi = phist->old_expr_vinsn;
1992 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1993 == EXPR_SEPARABLE_P (expr));
1994 copy_expr (tmp_expr, expr);
1996 if (vinsn_equal_p (phist->new_expr_vinsn,
1997 EXPR_VINSN (tmp_expr)))
1998 change_vinsn_in_expr (tmp_expr, new_vi);
2000 /* This happens when we're unsubstituting on a bookkeeping
2001 copy, which was in turn substituted. The history is wrong
2002 in this case. Do it the hard way. */
2003 add = substitute_reg_in_expr (tmp_expr, insn, true);
2005 av_set_add (&new_set, tmp_expr);
2006 clear_expr (tmp_expr);
2016 av_set_union_and_clear (av_ptr, &new_set, NULL);
2020 /* Moveup_* helpers for code motion and computing av sets. */
2022 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2023 The difference from the below function is that only substitution is
2025 static enum MOVEUP_EXPR_CODE
2026 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
2028 vinsn_t vi = EXPR_VINSN (expr);
2032 /* Do this only inside insn group. */
2033 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
2035 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2037 return MOVEUP_EXPR_SAME;
2039 /* Substitution is the possible choice in this case. */
2040 if (has_dep_p[DEPS_IN_RHS])
2042 /* Can't substitute UNIQUE VINSNs. */
2043 gcc_assert (!VINSN_UNIQUE_P (vi));
2045 if (can_substitute_through_p (through_insn,
2046 has_dep_p[DEPS_IN_RHS])
2047 && substitute_reg_in_expr (expr, through_insn, false))
2049 EXPR_WAS_SUBSTITUTED (expr) = true;
2050 return MOVEUP_EXPR_CHANGED;
2053 /* Don't care about this, as even true dependencies may be allowed
2054 in an insn group. */
2055 return MOVEUP_EXPR_SAME;
2058 /* This can catch output dependencies in COND_EXECs. */
2059 if (has_dep_p[DEPS_IN_INSN])
2060 return MOVEUP_EXPR_NULL;
2062 /* This is either an output or an anti dependence, which usually have
2063 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2065 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2066 return MOVEUP_EXPR_AS_RHS;
2069 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2070 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2071 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2072 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2073 && !sel_insn_is_speculation_check (through_insn))
2075 /* True when a conflict on a target register was found during moveup_expr. */
2076 static bool was_target_conflict = false;
2078 /* Return true when moving a debug INSN across THROUGH_INSN will
2079 create a bookkeeping block. We don't want to create such blocks,
2080 for they would cause codegen differences between compilations with
2081 and without debug info. */
2084 moving_insn_creates_bookkeeping_block_p (insn_t insn,
2085 insn_t through_insn)
2087 basic_block bbi, bbt;
2089 edge_iterator ei1, ei2;
2091 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn))
2093 if (sched_verbose >= 9)
2094 sel_print ("no bookkeeping required: ");
2098 bbi = BLOCK_FOR_INSN (insn);
2100 if (EDGE_COUNT (bbi->preds) == 1)
2102 if (sched_verbose >= 9)
2103 sel_print ("only one pred edge: ");
2107 bbt = BLOCK_FOR_INSN (through_insn);
2109 FOR_EACH_EDGE (e1, ei1, bbt->succs)
2111 FOR_EACH_EDGE (e2, ei2, bbi->preds)
2113 if (find_block_for_bookkeeping (e1, e2, TRUE))
2115 if (sched_verbose >= 9)
2116 sel_print ("found existing block: ");
2122 if (sched_verbose >= 9)
2123 sel_print ("would create bookkeeping block: ");
2128 /* Return true when the conflict with newly created implicit clobbers
2129 between EXPR and THROUGH_INSN is found because of renaming. */
2131 implicit_clobber_conflict_p (insn_t through_insn, expr_t expr)
2134 rtx insn, reg, rhs, pat;
2135 hard_reg_set_iterator hrsi;
2139 /* Make a new pseudo register. */
2140 reg = gen_reg_rtx (GET_MODE (EXPR_LHS (expr)));
2141 max_regno = max_reg_num ();
2142 maybe_extend_reg_info_p ();
2144 /* Validate a change and bail out early. */
2145 insn = EXPR_INSN_RTX (expr);
2146 validate_change (insn, &SET_DEST (PATTERN (insn)), reg, true);
2147 valid = verify_changes (0);
2151 if (sched_verbose >= 6)
2152 sel_print ("implicit clobbers failed validation, ");
2156 /* Make a new insn with it. */
2157 rhs = copy_rtx (VINSN_RHS (EXPR_VINSN (expr)));
2158 pat = gen_rtx_SET (VOIDmode, reg, rhs);
2160 insn = emit_insn (pat);
2163 /* Calculate implicit clobbers. */
2164 extract_insn (insn);
2165 preprocess_constraints ();
2166 ira_implicitly_set_insn_hard_regs (&temp);
2167 AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs);
2169 /* If any implicit clobber registers intersect with regular ones in
2170 through_insn, we have a dependency and thus bail out. */
2171 EXECUTE_IF_SET_IN_HARD_REG_SET (temp, 0, regno, hrsi)
2173 vinsn_t vi = INSN_VINSN (through_insn);
2174 if (bitmap_bit_p (VINSN_REG_SETS (vi), regno)
2175 || bitmap_bit_p (VINSN_REG_CLOBBERS (vi), regno)
2176 || bitmap_bit_p (VINSN_REG_USES (vi), regno))
2183 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2184 performing necessary transformations. Record the type of transformation
2185 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2186 permit all dependencies except true ones, and try to remove those
2187 too via forward substitution. All cases when a non-eliminable
2188 non-zero cost dependency exists inside an insn group will be fixed
2189 in tick_check_p instead. */
2190 static enum MOVEUP_EXPR_CODE
2191 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2192 enum local_trans_type *ptrans_type)
2194 vinsn_t vi = EXPR_VINSN (expr);
2195 insn_t insn = VINSN_INSN_RTX (vi);
2196 bool was_changed = false;
2197 bool as_rhs = false;
2201 /* ??? We use dependencies of non-debug insns on debug insns to
2202 indicate that the debug insns need to be reset if the non-debug
2203 insn is pulled ahead of it. It's hard to figure out how to
2204 introduce such a notion in sel-sched, but it already fails to
2205 support debug insns in other ways, so we just go ahead and
2206 let the deug insns go corrupt for now. */
2207 if (DEBUG_INSN_P (through_insn) && !DEBUG_INSN_P (insn))
2208 return MOVEUP_EXPR_SAME;
2210 /* When inside_insn_group, delegate to the helper. */
2211 if (inside_insn_group)
2212 return moveup_expr_inside_insn_group (expr, through_insn);
2214 /* Deal with unique insns and control dependencies. */
2215 if (VINSN_UNIQUE_P (vi))
2217 /* We can move jumps without side-effects or jumps that are
2218 mutually exclusive with instruction THROUGH_INSN (all in cases
2219 dependencies allow to do so and jump is not speculative). */
2220 if (control_flow_insn_p (insn))
2222 basic_block fallthru_bb;
2224 /* Do not move checks and do not move jumps through other
2226 if (control_flow_insn_p (through_insn)
2227 || sel_insn_is_speculation_check (insn))
2228 return MOVEUP_EXPR_NULL;
2230 /* Don't move jumps through CFG joins. */
2231 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2232 return MOVEUP_EXPR_NULL;
2234 /* The jump should have a clear fallthru block, and
2235 this block should be in the current region. */
2236 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2237 || ! in_current_region_p (fallthru_bb))
2238 return MOVEUP_EXPR_NULL;
2240 /* And it should be mutually exclusive with through_insn. */
2241 if (! sched_insns_conditions_mutex_p (insn, through_insn)
2242 && ! DEBUG_INSN_P (through_insn))
2243 return MOVEUP_EXPR_NULL;
2246 /* Don't move what we can't move. */
2247 if (EXPR_CANT_MOVE (expr)
2248 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2249 return MOVEUP_EXPR_NULL;
2251 /* Don't move SCHED_GROUP instruction through anything.
2252 If we don't force this, then it will be possible to start
2253 scheduling a sched_group before all its dependencies are
2255 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2256 as late as possible through rank_for_schedule. */
2257 if (SCHED_GROUP_P (insn))
2258 return MOVEUP_EXPR_NULL;
2261 gcc_assert (!control_flow_insn_p (insn));
2263 /* Don't move debug insns if this would require bookkeeping. */
2264 if (DEBUG_INSN_P (insn)
2265 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)
2266 && moving_insn_creates_bookkeeping_block_p (insn, through_insn))
2267 return MOVEUP_EXPR_NULL;
2269 /* Deal with data dependencies. */
2270 was_target_conflict = false;
2271 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2274 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2275 return MOVEUP_EXPR_SAME;
2279 /* We can move UNIQUE insn up only as a whole and unchanged,
2280 so it shouldn't have any dependencies. */
2281 if (VINSN_UNIQUE_P (vi))
2282 return MOVEUP_EXPR_NULL;
2285 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2289 res = speculate_expr (expr, full_ds);
2292 /* Speculation was successful. */
2294 was_changed = (res > 0);
2296 was_target_conflict = true;
2298 *ptrans_type = TRANS_SPECULATION;
2299 sel_clear_has_dependence ();
2303 if (has_dep_p[DEPS_IN_INSN])
2304 /* We have some dependency that cannot be discarded. */
2305 return MOVEUP_EXPR_NULL;
2307 if (has_dep_p[DEPS_IN_LHS])
2309 /* Only separable insns can be moved up with the new register.
2310 Anyways, we should mark that the original register is
2312 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2313 return MOVEUP_EXPR_NULL;
2315 /* When renaming a hard register to a pseudo before reload, extra
2316 dependencies can occur from the implicit clobbers of the insn.
2317 Filter out such cases here. */
2318 if (!reload_completed && REG_P (EXPR_LHS (expr))
2319 && HARD_REGISTER_P (EXPR_LHS (expr))
2320 && implicit_clobber_conflict_p (through_insn, expr))
2322 if (sched_verbose >= 6)
2323 sel_print ("implicit clobbers conflict detected, ");
2324 return MOVEUP_EXPR_NULL;
2326 EXPR_TARGET_AVAILABLE (expr) = false;
2327 was_target_conflict = true;
2331 /* At this point we have either separable insns, that will be lifted
2332 up only as RHSes, or non-separable insns with no dependency in lhs.
2333 If dependency is in RHS, then try to perform substitution and move up
2340 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2341 moved above y=x assignment as z=x*2.
2343 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2344 side can be moved because of the output dependency. The operation was
2345 cropped to its rhs above. */
2346 if (has_dep_p[DEPS_IN_RHS])
2348 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2350 /* Can't substitute UNIQUE VINSNs. */
2351 gcc_assert (!VINSN_UNIQUE_P (vi));
2353 if (can_speculate_dep_p (*rhs_dsp))
2357 res = speculate_expr (expr, *rhs_dsp);
2360 /* Speculation was successful. */
2362 was_changed = (res > 0);
2364 was_target_conflict = true;
2366 *ptrans_type = TRANS_SPECULATION;
2369 return MOVEUP_EXPR_NULL;
2371 else if (can_substitute_through_p (through_insn,
2373 && substitute_reg_in_expr (expr, through_insn, false))
2375 /* ??? We cannot perform substitution AND speculation on the same
2377 gcc_assert (!was_changed);
2380 *ptrans_type = TRANS_SUBSTITUTION;
2381 EXPR_WAS_SUBSTITUTED (expr) = true;
2384 return MOVEUP_EXPR_NULL;
2387 /* Don't move trapping insns through jumps.
2388 This check should be at the end to give a chance to control speculation
2389 to perform its duties. */
2390 if (CANT_MOVE_TRAPPING (expr, through_insn))
2391 return MOVEUP_EXPR_NULL;
2394 ? MOVEUP_EXPR_CHANGED
2396 ? MOVEUP_EXPR_AS_RHS
2397 : MOVEUP_EXPR_SAME));
2400 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2401 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2402 that can exist within a parallel group. Write to RES the resulting
2403 code for moveup_expr. */
2405 try_bitmap_cache (expr_t expr, insn_t insn,
2406 bool inside_insn_group,
2407 enum MOVEUP_EXPR_CODE *res)
2409 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2411 /* First check whether we've analyzed this situation already. */
2412 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2414 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2416 if (sched_verbose >= 6)
2417 sel_print ("removed (cached)\n");
2418 *res = MOVEUP_EXPR_NULL;
2423 if (sched_verbose >= 6)
2424 sel_print ("unchanged (cached)\n");
2425 *res = MOVEUP_EXPR_SAME;
2429 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2431 if (inside_insn_group)
2433 if (sched_verbose >= 6)
2434 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2435 *res = MOVEUP_EXPR_SAME;
2440 EXPR_TARGET_AVAILABLE (expr) = false;
2442 /* This is the only case when propagation result can change over time,
2443 as we can dynamically switch off scheduling as RHS. In this case,
2444 just check the flag to reach the correct decision. */
2445 if (enable_schedule_as_rhs_p)
2447 if (sched_verbose >= 6)
2448 sel_print ("unchanged (as RHS, cached)\n");
2449 *res = MOVEUP_EXPR_AS_RHS;
2454 if (sched_verbose >= 6)
2455 sel_print ("removed (cached as RHS, but renaming"
2456 " is now disabled)\n");
2457 *res = MOVEUP_EXPR_NULL;
2465 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2466 if successful. Write to RES the resulting code for moveup_expr. */
2468 try_transformation_cache (expr_t expr, insn_t insn,
2469 enum MOVEUP_EXPR_CODE *res)
2471 struct transformed_insns *pti
2472 = (struct transformed_insns *)
2473 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2475 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2478 /* This EXPR was already moved through this insn and was
2479 changed as a result. Fetch the proper data from
2481 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2482 INSN_UID (insn), pti->type,
2483 pti->vinsn_old, pti->vinsn_new,
2484 EXPR_SPEC_DONE_DS (expr));
2486 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2487 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2488 change_vinsn_in_expr (expr, pti->vinsn_new);
2489 if (pti->was_target_conflict)
2490 EXPR_TARGET_AVAILABLE (expr) = false;
2491 if (pti->type == TRANS_SPECULATION)
2493 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2494 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2497 if (sched_verbose >= 6)
2499 sel_print ("changed (cached): ");
2504 *res = MOVEUP_EXPR_CHANGED;
2511 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2513 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2514 enum MOVEUP_EXPR_CODE res)
2516 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2518 /* Do not cache result of propagating jumps through an insn group,
2519 as it is always true, which is not useful outside the group. */
2520 if (inside_insn_group)
2523 if (res == MOVEUP_EXPR_NULL)
2525 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2526 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2528 else if (res == MOVEUP_EXPR_SAME)
2530 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2531 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2533 else if (res == MOVEUP_EXPR_AS_RHS)
2535 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2536 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2542 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2543 and transformation type TRANS_TYPE. */
2545 update_transformation_cache (expr_t expr, insn_t insn,
2546 bool inside_insn_group,
2547 enum local_trans_type trans_type,
2548 vinsn_t expr_old_vinsn)
2550 struct transformed_insns *pti;
2552 if (inside_insn_group)
2555 pti = XNEW (struct transformed_insns);
2556 pti->vinsn_old = expr_old_vinsn;
2557 pti->vinsn_new = EXPR_VINSN (expr);
2558 pti->type = trans_type;
2559 pti->was_target_conflict = was_target_conflict;
2560 pti->ds = EXPR_SPEC_DONE_DS (expr);
2561 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2562 vinsn_attach (pti->vinsn_old);
2563 vinsn_attach (pti->vinsn_new);
2564 *((struct transformed_insns **)
2565 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2566 pti, VINSN_HASH_RTX (expr_old_vinsn),
2570 /* Same as moveup_expr, but first looks up the result of
2571 transformation in caches. */
2572 static enum MOVEUP_EXPR_CODE
2573 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2575 enum MOVEUP_EXPR_CODE res;
2576 bool got_answer = false;
2578 if (sched_verbose >= 6)
2580 sel_print ("Moving ");
2582 sel_print (" through %d: ", INSN_UID (insn));
2585 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr))
2586 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr)))
2587 == EXPR_INSN_RTX (expr)))
2588 /* Don't use cached information for debug insns that are heads of
2590 else if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2591 /* When inside insn group, we do not want remove stores conflicting
2592 with previosly issued loads. */
2593 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2594 else if (try_transformation_cache (expr, insn, &res))
2599 /* Invoke moveup_expr and record the results. */
2600 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2601 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2602 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2603 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2604 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2606 /* ??? Invent something better than this. We can't allow old_vinsn
2607 to go, we need it for the history vector. */
2608 vinsn_attach (expr_old_vinsn);
2610 res = moveup_expr (expr, insn, inside_insn_group,
2614 case MOVEUP_EXPR_NULL:
2615 update_bitmap_cache (expr, insn, inside_insn_group, res);
2616 if (sched_verbose >= 6)
2617 sel_print ("removed\n");
2620 case MOVEUP_EXPR_SAME:
2621 update_bitmap_cache (expr, insn, inside_insn_group, res);
2622 if (sched_verbose >= 6)
2623 sel_print ("unchanged\n");
2626 case MOVEUP_EXPR_AS_RHS:
2627 gcc_assert (!unique_p || inside_insn_group);
2628 update_bitmap_cache (expr, insn, inside_insn_group, res);
2629 if (sched_verbose >= 6)
2630 sel_print ("unchanged (as RHS)\n");
2633 case MOVEUP_EXPR_CHANGED:
2634 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2635 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2636 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2637 INSN_UID (insn), trans_type,
2638 expr_old_vinsn, EXPR_VINSN (expr),
2640 update_transformation_cache (expr, insn, inside_insn_group,
2641 trans_type, expr_old_vinsn);
2642 if (sched_verbose >= 6)
2644 sel_print ("changed: ");
2653 vinsn_detach (expr_old_vinsn);
2659 /* Moves an av set AVP up through INSN, performing necessary
2662 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2667 FOR_EACH_EXPR_1 (expr, i, avp)
2670 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2672 case MOVEUP_EXPR_SAME:
2673 case MOVEUP_EXPR_AS_RHS:
2676 case MOVEUP_EXPR_NULL:
2677 av_set_iter_remove (&i);
2680 case MOVEUP_EXPR_CHANGED:
2681 expr = merge_with_other_exprs (avp, &i, expr);
2690 /* Moves AVP set along PATH. */
2692 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2696 if (sched_verbose >= 6)
2697 sel_print ("Moving expressions up in the insn group...\n");
2700 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2702 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2704 moveup_set_expr (avp, ILIST_INSN (path), true);
2705 path = ILIST_NEXT (path);
2709 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2711 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2713 expr_def _tmp, *tmp = &_tmp;
2717 copy_expr_onside (tmp, expr);
2718 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2721 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2723 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2724 != MOVEUP_EXPR_NULL);
2725 path = ILIST_NEXT (path);
2730 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2731 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2733 if (tmp_vinsn != expr_vliw_vinsn)
2734 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2742 /* Functions that compute av and lv sets. */
2744 /* Returns true if INSN is not a downward continuation of the given path P in
2745 the current stage. */
2747 is_ineligible_successor (insn_t insn, ilist_t p)
2751 /* Check if insn is not deleted. */
2752 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2754 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2757 /* If it's the first insn visited, then the successor is ok. */
2761 prev_insn = ILIST_INSN (p);
2763 if (/* a backward edge. */
2764 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2765 /* is already visited. */
2766 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2767 && (ilist_is_in_p (p, insn)
2768 /* We can reach another fence here and still seqno of insn
2769 would be equal to seqno of prev_insn. This is possible
2770 when prev_insn is a previously created bookkeeping copy.
2771 In that case it'd get a seqno of insn. Thus, check here
2772 whether insn is in current fence too. */
2773 || IN_CURRENT_FENCE_P (insn)))
2774 /* Was already scheduled on this round. */
2775 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2776 && IN_CURRENT_FENCE_P (insn))
2777 /* An insn from another fence could also be
2778 scheduled earlier even if this insn is not in
2779 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2781 && INSN_SCHED_TIMES (insn) > 0))
2787 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2788 of handling multiple successors and properly merging its av_sets. P is
2789 the current path traversed. WS is the size of lookahead window.
2790 Return the av set computed. */
2792 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2794 struct succs_info *sinfo;
2795 av_set_t expr_in_all_succ_branches = NULL;
2797 insn_t succ, zero_succ = NULL;
2798 av_set_t av1 = NULL;
2800 gcc_assert (sel_bb_end_p (insn));
2802 /* Find different kind of successors needed for correct computing of
2803 SPEC and TARGET_AVAILABLE attributes. */
2804 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2807 if (sched_verbose >= 6)
2809 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2810 dump_insn_vector (sinfo->succs_ok);
2812 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2813 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2816 /* Add insn to to the tail of current path. */
2817 ilist_add (&p, insn);
2819 FOR_EACH_VEC_ELT (rtx, sinfo->succs_ok, is, succ)
2823 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2824 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2826 av_set_split_usefulness (succ_set,
2827 VEC_index (int, sinfo->probs_ok, is),
2830 if (sinfo->all_succs_n > 1)
2832 /* Find EXPR'es that came from *all* successors and save them
2833 into expr_in_all_succ_branches. This set will be used later
2834 for calculating speculation attributes of EXPR'es. */
2837 expr_in_all_succ_branches = av_set_copy (succ_set);
2839 /* Remember the first successor for later. */
2847 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2848 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2849 av_set_iter_remove (&i);
2853 /* Union the av_sets. Check liveness restrictions on target registers
2854 in special case of two successors. */
2855 if (sinfo->succs_ok_n == 2 && is == 1)
2857 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2858 basic_block bb1 = BLOCK_FOR_INSN (succ);
2860 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2861 av_set_union_and_live (&av1, &succ_set,
2867 av_set_union_and_clear (&av1, &succ_set, insn);
2870 /* Check liveness restrictions via hard way when there are more than
2872 if (sinfo->succs_ok_n > 2)
2873 FOR_EACH_VEC_ELT (rtx, sinfo->succs_ok, is, succ)
2875 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2877 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2878 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2879 BB_LV_SET (succ_bb));
2882 /* Finally, check liveness restrictions on paths leaving the region. */
2883 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2884 FOR_EACH_VEC_ELT (rtx, sinfo->succs_other, is, succ)
2885 mark_unavailable_targets
2886 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2888 if (sinfo->all_succs_n > 1)
2893 /* Increase the spec attribute of all EXPR'es that didn't come
2894 from all successors. */
2895 FOR_EACH_EXPR (expr, i, av1)
2896 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2899 av_set_clear (&expr_in_all_succ_branches);
2901 /* Do not move conditional branches through other
2902 conditional branches. So, remove all conditional
2903 branches from av_set if current operator is a conditional
2905 av_set_substract_cond_branches (&av1);
2909 free_succs_info (sinfo);
2911 if (sched_verbose >= 6)
2913 sel_print ("av_succs (%d): ", INSN_UID (insn));
2921 /* This function computes av_set for the FIRST_INSN by dragging valid
2922 av_set through all basic block insns either from the end of basic block
2923 (computed using compute_av_set_at_bb_end) or from the insn on which
2924 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2925 below the basic block and handling conditional branches.
2926 FIRST_INSN - the basic block head, P - path consisting of the insns
2927 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2928 and bb ends are added to the path), WS - current window size,
2929 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2931 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2936 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2937 insn_t after_bb_end = NEXT_INSN (bb_end);
2940 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2942 /* Return NULL if insn is not on the legitimate downward path. */
2943 if (is_ineligible_successor (first_insn, p))
2945 if (sched_verbose >= 6)
2946 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2951 /* If insn already has valid av(insn) computed, just return it. */
2952 if (AV_SET_VALID_P (first_insn))
2956 if (sel_bb_head_p (first_insn))
2957 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2961 if (sched_verbose >= 6)
2963 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2964 dump_av_set (av_set);
2968 return need_copy_p ? av_set_copy (av_set) : av_set;
2971 ilist_add (&p, first_insn);
2973 /* As the result after this loop have completed, in LAST_INSN we'll
2974 have the insn which has valid av_set to start backward computation
2975 from: it either will be NULL because on it the window size was exceeded
2976 or other valid av_set as returned by compute_av_set for the last insn
2977 of the basic block. */
2978 for (last_insn = first_insn; last_insn != after_bb_end;
2979 last_insn = NEXT_INSN (last_insn))
2981 /* We may encounter valid av_set not only on bb_head, but also on
2982 those insns on which previously MAX_WS was exceeded. */
2983 if (AV_SET_VALID_P (last_insn))
2985 if (sched_verbose >= 6)
2986 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2990 /* The special case: the last insn of the BB may be an
2991 ineligible_successor due to its SEQ_NO that was set on
2992 it as a bookkeeping. */
2993 if (last_insn != first_insn
2994 && is_ineligible_successor (last_insn, p))
2996 if (sched_verbose >= 6)
2997 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
3001 if (DEBUG_INSN_P (last_insn))
3004 if (end_ws > max_ws)
3006 /* We can reach max lookahead size at bb_header, so clean av_set
3008 INSN_WS_LEVEL (last_insn) = global_level;
3010 if (sched_verbose >= 6)
3011 sel_print ("Insn %d is beyond the software lookahead window size\n",
3012 INSN_UID (last_insn));
3019 /* Get the valid av_set into AV above the LAST_INSN to start backward
3020 computation from. It either will be empty av_set or av_set computed from
3021 the successors on the last insn of the current bb. */
3022 if (last_insn != after_bb_end)
3026 /* This is needed only to obtain av_sets that are identical to
3027 those computed by the old compute_av_set version. */
3028 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
3029 av_set_add (&av, INSN_EXPR (last_insn));
3032 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
3033 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
3035 /* Compute av_set in AV starting from below the LAST_INSN up to
3036 location above the FIRST_INSN. */
3037 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
3038 cur_insn = PREV_INSN (cur_insn))
3039 if (!INSN_NOP_P (cur_insn))
3043 moveup_set_expr (&av, cur_insn, false);
3045 /* If the expression for CUR_INSN is already in the set,
3046 replace it by the new one. */
3047 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
3051 copy_expr (expr, INSN_EXPR (cur_insn));
3054 av_set_add (&av, INSN_EXPR (cur_insn));
3057 /* Clear stale bb_av_set. */
3058 if (sel_bb_head_p (first_insn))
3060 av_set_clear (&BB_AV_SET (cur_bb));
3061 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
3062 BB_AV_LEVEL (cur_bb) = global_level;
3065 if (sched_verbose >= 6)
3067 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
3076 /* Compute av set before INSN.
3077 INSN - the current operation (actual rtx INSN)
3078 P - the current path, which is list of insns visited so far
3079 WS - software lookahead window size.
3080 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3081 if we want to save computed av_set in s_i_d, we should make a copy of it.
3083 In the resulting set we will have only expressions that don't have delay
3084 stalls and nonsubstitutable dependences. */
3086 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
3088 return compute_av_set_inside_bb (insn, p, ws, unique_p);
3091 /* Propagate a liveness set LV through INSN. */
3093 propagate_lv_set (regset lv, insn_t insn)
3095 gcc_assert (INSN_P (insn));
3097 if (INSN_NOP_P (insn))
3100 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
3103 /* Return livness set at the end of BB. */
3105 compute_live_after_bb (basic_block bb)
3109 regset lv = get_clear_regset_from_pool ();
3111 gcc_assert (!ignore_first);
3113 FOR_EACH_EDGE (e, ei, bb->succs)
3114 if (sel_bb_empty_p (e->dest))
3116 if (! BB_LV_SET_VALID_P (e->dest))
3119 gcc_assert (BB_LV_SET (e->dest) == NULL);
3120 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
3121 BB_LV_SET_VALID_P (e->dest) = true;
3123 IOR_REG_SET (lv, BB_LV_SET (e->dest));
3126 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
3131 /* Compute the set of all live registers at the point before INSN and save
3132 it at INSN if INSN is bb header. */
3134 compute_live (insn_t insn)
3136 basic_block bb = BLOCK_FOR_INSN (insn);
3140 /* Return the valid set if we're already on it. */
3145 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3146 src = BB_LV_SET (bb);
3149 gcc_assert (in_current_region_p (bb));
3150 if (INSN_LIVE_VALID_P (insn))
3151 src = INSN_LIVE (insn);
3156 lv = get_regset_from_pool ();
3157 COPY_REG_SET (lv, src);
3159 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3161 COPY_REG_SET (BB_LV_SET (bb), lv);
3162 BB_LV_SET_VALID_P (bb) = true;
3165 return_regset_to_pool (lv);
3170 /* We've skipped the wrong lv_set. Don't skip the right one. */
3171 ignore_first = false;
3172 gcc_assert (in_current_region_p (bb));
3174 /* Find a valid LV set in this block or below, if needed.
3175 Start searching from the next insn: either ignore_first is true, or
3176 INSN doesn't have a correct live set. */
3177 temp = NEXT_INSN (insn);
3178 final = NEXT_INSN (BB_END (bb));
3179 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3180 temp = NEXT_INSN (temp);
3183 lv = compute_live_after_bb (bb);
3184 temp = PREV_INSN (temp);
3188 lv = get_regset_from_pool ();
3189 COPY_REG_SET (lv, INSN_LIVE (temp));
3192 /* Put correct lv sets on the insns which have bad sets. */
3193 final = PREV_INSN (insn);
3194 while (temp != final)
3196 propagate_lv_set (lv, temp);
3197 COPY_REG_SET (INSN_LIVE (temp), lv);
3198 INSN_LIVE_VALID_P (temp) = true;
3199 temp = PREV_INSN (temp);
3202 /* Also put it in a BB. */
3203 if (sel_bb_head_p (insn))
3205 basic_block bb = BLOCK_FOR_INSN (insn);
3207 COPY_REG_SET (BB_LV_SET (bb), lv);
3208 BB_LV_SET_VALID_P (bb) = true;
3211 /* We return LV to the pool, but will not clear it there. Thus we can
3212 legimatelly use LV till the next use of regset_pool_get (). */
3213 return_regset_to_pool (lv);
3217 /* Update liveness sets for INSN. */
3219 update_liveness_on_insn (rtx insn)
3221 ignore_first = true;
3222 compute_live (insn);
3225 /* Compute liveness below INSN and write it into REGS. */
3227 compute_live_below_insn (rtx insn, regset regs)
3232 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3233 IOR_REG_SET (regs, compute_live (succ));
3236 /* Update the data gathered in av and lv sets starting from INSN. */
3238 update_data_sets (rtx insn)
3240 update_liveness_on_insn (insn);
3241 if (sel_bb_head_p (insn))
3243 gcc_assert (AV_LEVEL (insn) != 0);
3244 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3245 compute_av_set (insn, NULL, 0, 0);
3250 /* Helper for move_op () and find_used_regs ().
3251 Return speculation type for which a check should be created on the place
3252 of INSN. EXPR is one of the original ops we are searching for. */
3254 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3257 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3259 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3261 if (targetm.sched.get_insn_checked_ds)
3262 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3264 if (spec_info != NULL
3265 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3266 already_checked_ds |= BEGIN_CONTROL;
3268 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3270 to_check_ds &= ~already_checked_ds;
3275 /* Find the set of registers that are unavailable for storing expres
3276 while moving ORIG_OPS up on the path starting from INSN due to
3277 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3279 All the original operations found during the traversal are saved in the
3280 ORIGINAL_INSNS list.
3282 REG_RENAME_P denotes the set of hardware registers that
3283 can not be used with renaming due to the register class restrictions,
3284 mode restrictions and other (the register we'll choose should be
3285 compatible class with the original uses, shouldn't be in call_used_regs,
3286 should be HARD_REGNO_RENAME_OK etc).
3288 Returns TRUE if we've found all original insns, FALSE otherwise.
3290 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3291 to traverse the code motion paths. This helper function finds registers
3292 that are not available for storing expres while moving ORIG_OPS up on the
3293 path starting from INSN. A register considered as used on the moving path,
3294 if one of the following conditions is not satisfied:
3296 (1) a register not set or read on any path from xi to an instance of
3297 the original operation,
3298 (2) not among the live registers of the point immediately following the
3299 first original operation on a given downward path, except for the
3300 original target register of the operation,
3301 (3) not live on the other path of any conditional branch that is passed
3302 by the operation, in case original operations are not present on
3303 both paths of the conditional branch.
3305 All the original operations found during the traversal are saved in the
3306 ORIGINAL_INSNS list.
3308 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3309 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3310 to unavailable hard regs at the point original operation is found. */
3313 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3314 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3316 def_list_iterator i;
3319 bool needs_spec_check_p = false;
3321 av_set_iterator expr_iter;
3322 struct fur_static_params sparams;
3323 struct cmpd_local_params lparams;
3325 /* We haven't visited any blocks yet. */
3326 bitmap_clear (code_motion_visited_blocks);
3328 /* Init parameters for code_motion_path_driver. */
3329 sparams.crosses_call = false;
3330 sparams.original_insns = original_insns;
3331 sparams.used_regs = used_regs;
3333 /* Set the appropriate hooks and data. */
3334 code_motion_path_driver_info = &fur_hooks;
3336 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3338 reg_rename_p->crosses_call |= sparams.crosses_call;
3340 gcc_assert (res == 1);
3341 gcc_assert (original_insns && *original_insns);
3343 /* ??? We calculate whether an expression needs a check when computing
3344 av sets. This information is not as precise as it could be due to
3345 merging this bit in merge_expr. We can do better in find_used_regs,
3346 but we want to avoid multiple traversals of the same code motion
3348 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3349 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3351 /* Mark hardware regs in REG_RENAME_P that are not suitable
3352 for renaming expr in INSN due to hardware restrictions (register class,
3353 modes compatibility etc). */
3354 FOR_EACH_DEF (def, i, *original_insns)
3356 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3358 if (VINSN_SEPARABLE_P (vinsn))
3359 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3361 /* Do not allow clobbering of ld.[sa] address in case some of the
3362 original operations need a check. */
3363 if (needs_spec_check_p)
3364 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3371 /* Functions to choose the best insn from available ones. */
3373 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3375 sel_target_adjust_priority (expr_t expr)
3377 int priority = EXPR_PRIORITY (expr);
3380 if (targetm.sched.adjust_priority)
3381 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3383 new_priority = priority;
3385 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3386 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3388 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3390 if (sched_verbose >= 4)
3391 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3392 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3393 EXPR_PRIORITY_ADJ (expr), new_priority);
3395 return new_priority;
3398 /* Rank two available exprs for schedule. Never return 0 here. */
3400 sel_rank_for_schedule (const void *x, const void *y)
3402 expr_t tmp = *(const expr_t *) y;
3403 expr_t tmp2 = *(const expr_t *) x;
3404 insn_t tmp_insn, tmp2_insn;
3405 vinsn_t tmp_vinsn, tmp2_vinsn;
3408 tmp_vinsn = EXPR_VINSN (tmp);
3409 tmp2_vinsn = EXPR_VINSN (tmp2);
3410 tmp_insn = EXPR_INSN_RTX (tmp);
3411 tmp2_insn = EXPR_INSN_RTX (tmp2);
3413 /* Schedule debug insns as early as possible. */
3414 if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn))
3416 else if (DEBUG_INSN_P (tmp2_insn))
3419 /* Prefer SCHED_GROUP_P insns to any others. */
3420 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3422 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3423 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3425 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3426 cannot be cloned. */
3427 if (VINSN_UNIQUE_P (tmp2_vinsn))
3432 /* Discourage scheduling of speculative checks. */
3433 val = (sel_insn_is_speculation_check (tmp_insn)
3434 - sel_insn_is_speculation_check (tmp2_insn));
3438 /* Prefer not scheduled insn over scheduled one. */
3439 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3441 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3446 /* Prefer jump over non-jump instruction. */
3447 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3449 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3452 /* Prefer an expr with greater priority. */
3453 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3455 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3456 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3458 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3461 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3462 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3466 if (spec_info != NULL && spec_info->mask != 0)
3467 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3473 ds1 = EXPR_SPEC_DONE_DS (tmp);
3475 dw1 = ds_weak (ds1);
3479 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3481 dw2 = ds_weak (ds2);
3486 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3490 /* Prefer an old insn to a bookkeeping insn. */
3491 if (INSN_UID (tmp_insn) < first_emitted_uid
3492 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3494 if (INSN_UID (tmp_insn) >= first_emitted_uid
3495 && INSN_UID (tmp2_insn) < first_emitted_uid)
3498 /* Prefer an insn with smaller UID, as a last resort.
3499 We can't safely use INSN_LUID as it is defined only for those insns
3500 that are in the stream. */
3501 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3504 /* Filter out expressions from av set pointed to by AV_PTR
3505 that are pipelined too many times. */
3507 process_pipelined_exprs (av_set_t *av_ptr)
3512 /* Don't pipeline already pipelined code as that would increase
3513 number of unnecessary register moves. */
3514 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3516 if (EXPR_SCHED_TIMES (expr)
3517 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3518 av_set_iter_remove (&si);
3522 /* Filter speculative insns from AV_PTR if we don't want them. */
3524 process_spec_exprs (av_set_t *av_ptr)
3526 bool try_data_p = true;
3527 bool try_control_p = true;
3531 if (spec_info == NULL)
3534 /* Scan *AV_PTR to find out if we want to consider speculative
3535 instructions for scheduling. */
3536 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3540 ds = EXPR_SPEC_DONE_DS (expr);
3542 /* The probability of a success is too low - don't speculate. */
3543 if ((ds & SPECULATIVE)
3544 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3545 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3546 || (pipelining_p && false
3548 && (ds & CONTROL_SPEC))))
3550 av_set_iter_remove (&si);
3554 if ((spec_info->flags & PREFER_NON_DATA_SPEC)
3555 && !(ds & BEGIN_DATA))
3558 if ((spec_info->flags & PREFER_NON_CONTROL_SPEC)
3559 && !(ds & BEGIN_CONTROL))
3560 try_control_p = false;
3563 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3567 ds = EXPR_SPEC_DONE_DS (expr);
3569 if (ds & SPECULATIVE)
3571 if ((ds & BEGIN_DATA) && !try_data_p)
3572 /* We don't want any data speculative instructions right
3574 av_set_iter_remove (&si);
3576 if ((ds & BEGIN_CONTROL) && !try_control_p)
3577 /* We don't want any control speculative instructions right
3579 av_set_iter_remove (&si);
3584 /* Search for any use-like insns in AV_PTR and decide on scheduling
3585 them. Return one when found, and NULL otherwise.
3586 Note that we check here whether a USE could be scheduled to avoid
3587 an infinite loop later. */
3589 process_use_exprs (av_set_t *av_ptr)
3593 bool uses_present_p = false;
3594 bool try_uses_p = true;
3596 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3598 /* This will also initialize INSN_CODE for later use. */
3599 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3601 /* If we have a USE in *AV_PTR that was not scheduled yet,
3602 do so because it will do good only. */
3603 if (EXPR_SCHED_TIMES (expr) <= 0)
3605 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3608 av_set_iter_remove (&si);
3612 gcc_assert (pipelining_p);
3614 uses_present_p = true;
3623 /* If we don't want to schedule any USEs right now and we have some
3624 in *AV_PTR, remove them, else just return the first one found. */
3627 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3628 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3629 av_set_iter_remove (&si);
3633 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3635 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3637 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3640 av_set_iter_remove (&si);
3648 /* Lookup EXPR in VINSN_VEC and return TRUE if found. Also check patterns from
3649 EXPR's history of changes. */
3651 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3653 vinsn_t vinsn, expr_vinsn;
3657 /* Start with checking expr itself and then proceed with all the old forms
3658 of expr taken from its history vector. */
3659 for (i = 0, expr_vinsn = EXPR_VINSN (expr);
3661 expr_vinsn = (i < VEC_length (expr_history_def,
3662 EXPR_HISTORY_OF_CHANGES (expr))
3663 ? VEC_index (expr_history_def,
3664 EXPR_HISTORY_OF_CHANGES (expr),
3665 i++)->old_expr_vinsn
3667 FOR_EACH_VEC_ELT (vinsn_t, vinsn_vec, n, vinsn)
3668 if (VINSN_SEPARABLE_P (vinsn))
3670 if (vinsn_equal_p (vinsn, expr_vinsn))
3675 /* For non-separable instructions, the blocking insn can have
3676 another pattern due to substitution, and we can't choose
3677 different register as in the above case. Check all registers
3678 being written instead. */
3679 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3680 VINSN_REG_SETS (expr_vinsn)))
3687 #ifdef ENABLE_CHECKING
3688 /* Return true if either of expressions from ORIG_OPS can be blocked
3689 by previously created bookkeeping code. STATIC_PARAMS points to static
3690 parameters of move_op. */
3692 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3695 av_set_iterator iter;
3696 moveop_static_params_p sparams;
3698 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3699 created while scheduling on another fence. */
3700 FOR_EACH_EXPR (expr, iter, orig_ops)
3701 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3704 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3705 sparams = (moveop_static_params_p) static_params;
3707 /* Expressions can be also blocked by bookkeeping created during current
3709 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3710 FOR_EACH_EXPR (expr, iter, orig_ops)
3711 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3714 /* Expressions in ORIG_OPS may have wrong destination register due to
3715 renaming. Check with the right register instead. */
3716 if (sparams->dest && REG_P (sparams->dest))
3718 unsigned regno = REGNO (sparams->dest);
3719 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3721 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn), regno)
3722 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn), regno)
3723 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn), regno))
3731 /* Clear VINSN_VEC and detach vinsns. */
3733 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3735 unsigned len = VEC_length (vinsn_t, *vinsn_vec);
3741 FOR_EACH_VEC_ELT (vinsn_t, *vinsn_vec, n, vinsn)
3742 vinsn_detach (vinsn);
3743 VEC_block_remove (vinsn_t, *vinsn_vec, 0, len);
3747 /* Add the vinsn of EXPR to the VINSN_VEC. */
3749 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3751 vinsn_attach (EXPR_VINSN (expr));
3752 VEC_safe_push (vinsn_t, heap, *vinsn_vec, EXPR_VINSN (expr));
3755 /* Free the vector representing blocked expressions. */
3757 vinsn_vec_free (vinsn_vec_t *vinsn_vec)
3760 VEC_free (vinsn_t, heap, *vinsn_vec);
3763 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3765 void sel_add_to_insn_priority (rtx insn, int amount)
3767 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3769 if (sched_verbose >= 2)
3770 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3771 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3772 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3775 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3776 true if there is something to schedule. BNDS and FENCE are current
3777 boundaries and fence, respectively. If we need to stall for some cycles
3778 before an expr from AV would become available, write this number to
3781 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3786 int sched_next_worked = 0, stalled, n;
3787 static int av_max_prio, est_ticks_till_branch;
3788 int min_need_stall = -1;
3789 deps_t dc = BND_DC (BLIST_BND (bnds));
3791 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3792 already scheduled. */
3796 /* Empty vector from the previous stuff. */
3797 if (VEC_length (expr_t, vec_av_set) > 0)
3798 VEC_block_remove (expr_t, vec_av_set, 0, VEC_length (expr_t, vec_av_set));
3800 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3802 gcc_assert (VEC_empty (expr_t, vec_av_set));
3803 FOR_EACH_EXPR (expr, si, av)
3805 VEC_safe_push (expr_t, heap, vec_av_set, expr);
3807 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3809 /* Adjust priority using target backend hook. */
3810 sel_target_adjust_priority (expr);
3813 /* Sort the vector. */
3814 VEC_qsort (expr_t, vec_av_set, sel_rank_for_schedule);
3816 /* We record maximal priority of insns in av set for current instruction
3818 if (FENCE_STARTS_CYCLE_P (fence))
3819 av_max_prio = est_ticks_till_branch = INT_MIN;
3821 /* Filter out inappropriate expressions. Loop's direction is reversed to
3822 visit "best" instructions first. We assume that VEC_unordered_remove
3823 moves last element in place of one being deleted. */
3824 for (n = VEC_length (expr_t, vec_av_set) - 1, stalled = 0; n >= 0; n--)
3826 expr_t expr = VEC_index (expr_t, vec_av_set, n);
3827 insn_t insn = EXPR_INSN_RTX (expr);
3828 signed char target_available;
3829 bool is_orig_reg_p = true;
3830 int need_cycles, new_prio;
3832 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3833 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3835 VEC_unordered_remove (expr_t, vec_av_set, n);
3839 /* Set number of sched_next insns (just in case there
3840 could be several). */
3841 if (FENCE_SCHED_NEXT (fence))
3842 sched_next_worked++;
3844 /* Check all liveness requirements and try renaming.
3845 FIXME: try to minimize calls to this. */
3846 target_available = EXPR_TARGET_AVAILABLE (expr);
3848 /* If insn was already scheduled on the current fence,
3849 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3850 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr))
3851 target_available = -1;
3853 /* If the availability of the EXPR is invalidated by the insertion of
3854 bookkeeping earlier, make sure that we won't choose this expr for
3855 scheduling if it's not separable, and if it is separable, then
3856 we have to recompute the set of available registers for it. */
3857 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3859 VEC_unordered_remove (expr_t, vec_av_set, n);
3860 if (sched_verbose >= 4)
3861 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3866 if (target_available == true)
3868 /* Do nothing -- we can use an existing register. */
3869 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3871 else if (/* Non-separable instruction will never
3872 get another register. */
3873 (target_available == false
3874 && !EXPR_SEPARABLE_P (expr))
3875 /* Don't try to find a register for low-priority expression. */
3876 || (int) VEC_length (expr_t, vec_av_set) - 1 - n >= max_insns_to_rename
3877 /* ??? FIXME: Don't try to rename data speculation. */
3878 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3879 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3881 VEC_unordered_remove (expr_t, vec_av_set, n);
3882 if (sched_verbose >= 4)
3883 sel_print ("Expr %d has no suitable target register\n",
3888 /* Filter expressions that need to be renamed or speculated when
3889 pipelining, because compensating register copies or speculation
3890 checks are likely to be placed near the beginning of the loop,
3892 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3893 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3895 /* Estimation of number of cycles until loop branch for
3896 renaming/speculation to be successful. */
3897 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3899 if ((int) current_loop_nest->ninsns < 9)
3901 VEC_unordered_remove (expr_t, vec_av_set, n);
3902 if (sched_verbose >= 4)
3903 sel_print ("Pipelining expr %d will likely cause stall\n",
3908 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3909 < need_n_ticks_till_branch * issue_rate / 2
3910 && est_ticks_till_branch < need_n_ticks_till_branch)
3912 VEC_unordered_remove (expr_t, vec_av_set, n);
3913 if (sched_verbose >= 4)
3914 sel_print ("Pipelining expr %d will likely cause stall\n",
3920 /* We want to schedule speculation checks as late as possible. Discard
3921 them from av set if there are instructions with higher priority. */
3922 if (sel_insn_is_speculation_check (insn)
3923 && EXPR_PRIORITY (expr) < av_max_prio)
3926 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3927 VEC_unordered_remove (expr_t, vec_av_set, n);
3928 if (sched_verbose >= 4)
3929 sel_print ("Delaying speculation check %d until its first use\n",
3934 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3935 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3936 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3938 /* Don't allow any insns whose data is not yet ready.
3939 Check first whether we've already tried them and failed. */
3940 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3942 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3943 - FENCE_CYCLE (fence));
3944 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3945 est_ticks_till_branch = MAX (est_ticks_till_branch,
3946 EXPR_PRIORITY (expr) + need_cycles);
3948 if (need_cycles > 0)
3951 min_need_stall = (min_need_stall < 0
3953 : MIN (min_need_stall, need_cycles));
3954 VEC_unordered_remove (expr_t, vec_av_set, n);
3956 if (sched_verbose >= 4)
3957 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3959 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3964 /* Now resort to dependence analysis to find whether EXPR might be
3965 stalled due to dependencies from FENCE's context. */
3966 need_cycles = tick_check_p (expr, dc, fence);
3967 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3969 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3970 est_ticks_till_branch = MAX (est_ticks_till_branch,
3973 if (need_cycles > 0)
3975 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3977 int new_size = INSN_UID (insn) * 3 / 2;
3979 FENCE_READY_TICKS (fence)
3980 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3981 new_size, FENCE_READY_TICKS_SIZE (fence),
3984 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3985 = FENCE_CYCLE (fence) + need_cycles;
3988 min_need_stall = (min_need_stall < 0
3990 : MIN (min_need_stall, need_cycles));
3992 VEC_unordered_remove (expr_t, vec_av_set, n);
3994 if (sched_verbose >= 4)
3995 sel_print ("Expr %d is not ready yet until cycle %d\n",
3997 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
4001 if (sched_verbose >= 4)
4002 sel_print ("Expr %d is ok\n", INSN_UID (insn));
4006 /* Clear SCHED_NEXT. */
4007 if (FENCE_SCHED_NEXT (fence))
4009 gcc_assert (sched_next_worked == 1);
4010 FENCE_SCHED_NEXT (fence) = NULL_RTX;
4013 /* No need to stall if this variable was not initialized. */
4014 if (min_need_stall < 0)
4017 if (VEC_empty (expr_t, vec_av_set))
4019 /* We need to set *pneed_stall here, because later we skip this code
4020 when ready list is empty. */
4021 *pneed_stall = min_need_stall;
4025 gcc_assert (min_need_stall == 0);
4027 /* Sort the vector. */
4028 VEC_qsort (expr_t, vec_av_set, sel_rank_for_schedule);
4030 if (sched_verbose >= 4)
4032 sel_print ("Total ready exprs: %d, stalled: %d\n",
4033 VEC_length (expr_t, vec_av_set), stalled);
4034 sel_print ("Sorted av set (%d): ", VEC_length (expr_t, vec_av_set));
4035 FOR_EACH_VEC_ELT (expr_t, vec_av_set, n, expr)
4044 /* Convert a vectored and sorted av set to the ready list that
4045 the rest of the backend wants to see. */
4047 convert_vec_av_set_to_ready (void)
4052 /* Allocate and fill the ready list from the sorted vector. */
4053 ready.n_ready = VEC_length (expr_t, vec_av_set);
4054 ready.first = ready.n_ready - 1;
4056 gcc_assert (ready.n_ready > 0);
4058 if (ready.n_ready > max_issue_size)
4060 max_issue_size = ready.n_ready;
4061 sched_extend_ready_list (ready.n_ready);
4064 FOR_EACH_VEC_ELT (expr_t, vec_av_set, n, expr)
4066 vinsn_t vi = EXPR_VINSN (expr);
4067 insn_t insn = VINSN_INSN_RTX (vi);
4070 ready.vec[n] = insn;
4074 /* Initialize ready list from *AV_PTR for the max_issue () call.
4075 If any unrecognizable insn found in *AV_PTR, return it (and skip
4076 max_issue). BND and FENCE are current boundary and fence,
4077 respectively. If we need to stall for some cycles before an expr
4078 from *AV_PTR would become available, write this number to *PNEED_STALL. */
4080 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
4085 /* We do not support multiple boundaries per fence. */
4086 gcc_assert (BLIST_NEXT (bnds) == NULL);
4088 /* Process expressions required special handling, i.e. pipelined,
4089 speculative and recog() < 0 expressions first. */
4090 process_pipelined_exprs (av_ptr);
4091 process_spec_exprs (av_ptr);
4093 /* A USE could be scheduled immediately. */
4094 expr = process_use_exprs (av_ptr);
4101 /* Turn the av set to a vector for sorting. */
4102 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
4108 /* Build the final ready list. */
4109 convert_vec_av_set_to_ready ();
4113 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4115 sel_dfa_new_cycle (insn_t insn, fence_t fence)
4117 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
4118 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
4119 : FENCE_CYCLE (fence) - 1;
4123 if (!targetm.sched.dfa_new_cycle)
4126 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4128 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
4129 insn, last_scheduled_cycle,
4130 FENCE_CYCLE (fence), &sort_p))
4132 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4133 advance_one_cycle (fence);
4134 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4141 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4142 we can issue. FENCE is the current fence. */
4144 invoke_reorder_hooks (fence_t fence)
4147 bool ran_hook = false;
4149 /* Call the reorder hook at the beginning of the cycle, and call
4150 the reorder2 hook in the middle of the cycle. */
4151 if (FENCE_ISSUED_INSNS (fence) == 0)
4153 if (targetm.sched.reorder
4154 && !SCHED_GROUP_P (ready_element (&ready, 0))
4155 && ready.n_ready > 1)
4157 /* Don't give reorder the most prioritized insn as it can break
4163 = targetm.sched.reorder (sched_dump, sched_verbose,
4164 ready_lastpos (&ready),
4165 &ready.n_ready, FENCE_CYCLE (fence));
4173 /* Initialize can_issue_more for variable_issue. */
4174 issue_more = issue_rate;
4176 else if (targetm.sched.reorder2
4177 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4179 if (ready.n_ready == 1)
4181 targetm.sched.reorder2 (sched_dump, sched_verbose,
4182 ready_lastpos (&ready),
4183 &ready.n_ready, FENCE_CYCLE (fence));
4190 targetm.sched.reorder2 (sched_dump, sched_verbose,
4192 ? ready_lastpos (&ready) : NULL,
4193 &ready.n_ready, FENCE_CYCLE (fence));
4202 issue_more = FENCE_ISSUE_MORE (fence);
4204 /* Ensure that ready list and vec_av_set are in line with each other,
4205 i.e. vec_av_set[i] == ready_element (&ready, i). */
4206 if (issue_more && ran_hook)
4209 rtx *arr = ready.vec;
4210 expr_t *vec = VEC_address (expr_t, vec_av_set);
4212 for (i = 0, n = ready.n_ready; i < n; i++)
4213 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4217 for (j = i; j < n; j++)
4218 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4231 /* Return an EXPR correponding to INDEX element of ready list, if
4232 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4233 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4234 ready.vec otherwise. */
4235 static inline expr_t
4236 find_expr_for_ready (int index, bool follow_ready_element)
4241 real_index = follow_ready_element ? ready.first - index : index;
4243 expr = VEC_index (expr_t, vec_av_set, real_index);
4244 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4249 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4250 of such insns found. */
4252 invoke_dfa_lookahead_guard (void)
4256 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4258 if (sched_verbose >= 2)
4259 sel_print ("ready after reorder: ");
4261 for (i = 0, n = 0; i < ready.n_ready; i++)
4267 /* In this loop insn is Ith element of the ready list given by
4268 ready_element, not Ith element of ready.vec. */
4269 insn = ready_element (&ready, i);
4271 if (! have_hook || i == 0)
4274 r = !targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn);
4276 gcc_assert (INSN_CODE (insn) >= 0);
4278 /* Only insns with ready_try = 0 can get here
4279 from fill_ready_list. */
4280 gcc_assert (ready_try [i] == 0);
4285 expr = find_expr_for_ready (i, true);
4287 if (sched_verbose >= 2)
4289 dump_vinsn (EXPR_VINSN (expr));
4290 sel_print (":%d; ", ready_try[i]);
4294 if (sched_verbose >= 2)
4299 /* Calculate the number of privileged insns and return it. */
4301 calculate_privileged_insns (void)
4303 expr_t cur_expr, min_spec_expr = NULL;
4304 int privileged_n = 0, i;
4306 for (i = 0; i < ready.n_ready; i++)
4311 if (! min_spec_expr)
4312 min_spec_expr = find_expr_for_ready (i, true);
4314 cur_expr = find_expr_for_ready (i, true);
4316 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4322 if (i == ready.n_ready)
4325 if (sched_verbose >= 2)
4326 sel_print ("privileged_n: %d insns with SPEC %d\n",
4327 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4328 return privileged_n;
4331 /* Call the rest of the hooks after the choice was made. Return
4332 the number of insns that still can be issued given that the current
4333 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4334 and the insn chosen for scheduling, respectively. */
4336 invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more)
4338 gcc_assert (INSN_P (best_insn));
4340 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4341 sel_dfa_new_cycle (best_insn, fence);
4343 if (targetm.sched.variable_issue)
4345 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4347 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4349 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4351 else if (GET_CODE (PATTERN (best_insn)) != USE
4352 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4358 /* Estimate the cost of issuing INSN on DFA state STATE. */
4360 estimate_insn_cost (rtx insn, state_t state)
4362 static state_t temp = NULL;
4366 temp = xmalloc (dfa_state_size);
4368 memcpy (temp, state, dfa_state_size);
4369 cost = state_transition (temp, insn);
4378 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4379 This function properly handles ASMs, USEs etc. */
4381 get_expr_cost (expr_t expr, fence_t fence)
4383 rtx insn = EXPR_INSN_RTX (expr);
4385 if (recog_memoized (insn) < 0)
4387 if (!FENCE_STARTS_CYCLE_P (fence)
4388 && INSN_ASM_P (insn))
4389 /* This is asm insn which is tryed to be issued on the
4390 cycle not first. Issue it on the next cycle. */
4393 /* A USE insn, or something else we don't need to
4394 understand. We can't pass these directly to
4395 state_transition because it will trigger a
4396 fatal error for unrecognizable insns. */
4400 return estimate_insn_cost (insn, FENCE_STATE (fence));
4403 /* Find the best insn for scheduling, either via max_issue or just take
4404 the most prioritized available. */
4406 choose_best_insn (fence_t fence, int privileged_n, int *index)
4410 if (dfa_lookahead > 0)
4412 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4413 /* TODO: pass equivalent of first_cycle_insn_p to max_issue (). */
4414 can_issue = max_issue (&ready, privileged_n,
4415 FENCE_STATE (fence), true, index);
4416 if (sched_verbose >= 2)
4417 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4418 can_issue, FENCE_ISSUED_INSNS (fence));
4422 /* We can't use max_issue; just return the first available element. */
4425 for (i = 0; i < ready.n_ready; i++)
4427 expr_t expr = find_expr_for_ready (i, true);
4429 if (get_expr_cost (expr, fence) < 1)
4431 can_issue = can_issue_more;
4434 if (sched_verbose >= 2)
4435 sel_print ("using %dth insn from the ready list\n", i + 1);
4441 if (i == ready.n_ready)
4451 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4452 BNDS and FENCE are current boundaries and scheduling fence respectively.
4453 Return the expr found and NULL if nothing can be issued atm.
4454 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4456 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4461 /* Choose the best insn for scheduling via:
4462 1) sorting the ready list based on priority;
4463 2) calling the reorder hook;
4464 3) calling max_issue. */
4465 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4466 if (best == NULL && ready.n_ready > 0)
4468 int privileged_n, index;
4470 can_issue_more = invoke_reorder_hooks (fence);
4471 if (can_issue_more > 0)
4473 /* Try choosing the best insn until we find one that is could be
4474 scheduled due to liveness restrictions on its destination register.
4475 In the future, we'd like to choose once and then just probe insns
4476 in the order of their priority. */
4477 invoke_dfa_lookahead_guard ();
4478 privileged_n = calculate_privileged_insns ();
4479 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4481 best = find_expr_for_ready (index, true);
4483 /* We had some available insns, so if we can't issue them,
4485 if (can_issue_more == 0)
4494 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4496 if (targetm.sched.variable_issue
4497 && can_issue_more == 0)
4501 if (sched_verbose >= 2)
4505 sel_print ("Best expression (vliw form): ");
4507 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4510 sel_print ("No best expr found!\n");
4517 /* Functions that implement the core of the scheduler. */
4520 /* Emit an instruction from EXPR with SEQNO and VINSN after
4523 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4524 insn_t place_to_insert)
4526 /* This assert fails when we have identical instructions
4527 one of which dominates the other. In this case move_op ()
4528 finds the first instruction and doesn't search for second one.
4529 The solution would be to compute av_set after the first found
4530 insn and, if insn present in that set, continue searching.
4531 For now we workaround this issue in move_op. */
4532 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4534 if (EXPR_WAS_RENAMED (expr))
4536 unsigned regno = expr_dest_regno (expr);
4538 if (HARD_REGISTER_NUM_P (regno))
4540 df_set_regs_ever_live (regno, true);
4541 reg_rename_tick[regno] = ++reg_rename_this_tick;
4545 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4549 /* Return TRUE if BB can hold bookkeeping code. */
4551 block_valid_for_bookkeeping_p (basic_block bb)
4553 insn_t bb_end = BB_END (bb);
4555 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4558 if (INSN_P (bb_end))
4560 if (INSN_SCHED_TIMES (bb_end) > 0)
4564 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4569 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4570 into E2->dest, except from E1->src (there may be a sequence of empty basic
4571 blocks between E1->src and E2->dest). Return found block, or NULL if new
4572 one must be created. If LAX holds, don't assume there is a simple path
4573 from E1->src to E2->dest. */
4575 find_block_for_bookkeeping (edge e1, edge e2, bool lax)
4577 basic_block candidate_block = NULL;
4580 /* Loop over edges from E1 to E2, inclusive. */
4581 for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR; e = EDGE_SUCC (e->dest, 0))
4583 if (EDGE_COUNT (e->dest->preds) == 2)
4585 if (candidate_block == NULL)
4586 candidate_block = (EDGE_PRED (e->dest, 0) == e
4587 ? EDGE_PRED (e->dest, 1)->src
4588 : EDGE_PRED (e->dest, 0)->src);
4590 /* Found additional edge leading to path from e1 to e2
4594 else if (EDGE_COUNT (e->dest->preds) > 2)
4595 /* Several edges leading to path from e1 to e2 from aside. */
4599 return ((!lax || candidate_block)
4600 && block_valid_for_bookkeeping_p (candidate_block)
4604 if (lax && EDGE_COUNT (e->dest->succs) != 1)
4614 /* Create new basic block for bookkeeping code for path(s) incoming into
4615 E2->dest, except from E1->src. Return created block. */
4617 create_block_for_bookkeeping (edge e1, edge e2)
4619 basic_block new_bb, bb = e2->dest;
4621 /* Check that we don't spoil the loop structure. */
4622 if (current_loop_nest)
4624 basic_block latch = current_loop_nest->latch;
4626 /* We do not split header. */
4627 gcc_assert (e2->dest != current_loop_nest->header);
4629 /* We do not redirect the only edge to the latch block. */
4630 gcc_assert (e1->dest != latch
4631 || !single_pred_p (latch)
4632 || e1 != single_pred_edge (latch));
4635 /* Split BB to insert BOOK_INSN there. */
4636 new_bb = sched_split_block (bb, NULL);
4638 /* Move note_list from the upper bb. */
4639 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4640 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4641 BB_NOTE_LIST (bb) = NULL_RTX;
4643 gcc_assert (e2->dest == bb);
4645 /* Skip block for bookkeeping copy when leaving E1->src. */
4646 if (e1->flags & EDGE_FALLTHRU)
4647 sel_redirect_edge_and_branch_force (e1, new_bb);
4649 sel_redirect_edge_and_branch (e1, new_bb);
4651 gcc_assert (e1->dest == new_bb);
4652 gcc_assert (sel_bb_empty_p (bb));
4654 /* To keep basic block numbers in sync between debug and non-debug
4655 compilations, we have to rotate blocks here. Consider that we
4656 started from (a,b)->d, (c,d)->e, and d contained only debug
4657 insns. It would have been removed before if the debug insns
4658 weren't there, so we'd have split e rather than d. So what we do
4659 now is to swap the block numbers of new_bb and
4660 single_succ(new_bb) == e, so that the insns that were in e before
4661 get the new block number. */
4663 if (MAY_HAVE_DEBUG_INSNS)
4666 insn_t insn = sel_bb_head (new_bb);
4669 if (DEBUG_INSN_P (insn)
4670 && single_succ_p (new_bb)
4671 && (succ = single_succ (new_bb))
4672 && succ != EXIT_BLOCK_PTR
4673 && DEBUG_INSN_P ((last = sel_bb_end (new_bb))))
4675 while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4676 insn = NEXT_INSN (insn);
4680 sel_global_bb_info_def gbi;
4681 sel_region_bb_info_def rbi;
4684 if (sched_verbose >= 2)
4685 sel_print ("Swapping block ids %i and %i\n",
4686 new_bb->index, succ->index);
4689 new_bb->index = succ->index;
4692 SET_BASIC_BLOCK (new_bb->index, new_bb);
4693 SET_BASIC_BLOCK (succ->index, succ);
4695 memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi));
4696 memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ),
4698 memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi));
4700 memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi));
4701 memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ),
4703 memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi));
4705 i = BLOCK_TO_BB (new_bb->index);
4706 BLOCK_TO_BB (new_bb->index) = BLOCK_TO_BB (succ->index);
4707 BLOCK_TO_BB (succ->index) = i;
4709 i = CONTAINING_RGN (new_bb->index);
4710 CONTAINING_RGN (new_bb->index) = CONTAINING_RGN (succ->index);
4711 CONTAINING_RGN (succ->index) = i;
4713 for (i = 0; i < current_nr_blocks; i++)
4714 if (BB_TO_BLOCK (i) == succ->index)
4715 BB_TO_BLOCK (i) = new_bb->index;
4716 else if (BB_TO_BLOCK (i) == new_bb->index)
4717 BB_TO_BLOCK (i) = succ->index;
4719 FOR_BB_INSNS (new_bb, insn)
4721 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index;
4723 FOR_BB_INSNS (succ, insn)
4725 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index;
4727 if (bitmap_clear_bit (code_motion_visited_blocks, new_bb->index))
4728 bitmap_set_bit (code_motion_visited_blocks, succ->index);
4730 gcc_assert (LABEL_P (BB_HEAD (new_bb))
4731 && LABEL_P (BB_HEAD (succ)));
4733 if (sched_verbose >= 4)
4734 sel_print ("Swapping code labels %i and %i\n",
4735 CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4736 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4738 i = CODE_LABEL_NUMBER (BB_HEAD (new_bb));
4739 CODE_LABEL_NUMBER (BB_HEAD (new_bb))
4740 = CODE_LABEL_NUMBER (BB_HEAD (succ));
4741 CODE_LABEL_NUMBER (BB_HEAD (succ)) = i;
4749 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4750 into E2->dest, except from E1->src. */
4752 find_place_for_bookkeeping (edge e1, edge e2)
4754 insn_t place_to_insert;
4755 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4756 create new basic block, but insert bookkeeping there. */
4757 basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE);
4761 place_to_insert = BB_END (book_block);
4763 /* Don't use a block containing only debug insns for
4764 bookkeeping, this causes scheduling differences between debug
4765 and non-debug compilations, for the block would have been
4767 if (DEBUG_INSN_P (place_to_insert))
4769 rtx insn = sel_bb_head (book_block);
4771 while (insn != place_to_insert &&
4772 (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4773 insn = NEXT_INSN (insn);
4775 if (insn == place_to_insert)
4782 book_block = create_block_for_bookkeeping (e1, e2);
4783 place_to_insert = BB_END (book_block);
4784 if (sched_verbose >= 9)
4785 sel_print ("New block is %i, split from bookkeeping block %i\n",
4786 EDGE_SUCC (book_block, 0)->dest->index, book_block->index);
4790 if (sched_verbose >= 9)
4791 sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index);
4794 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4795 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4796 place_to_insert = PREV_INSN (place_to_insert);
4798 return place_to_insert;
4801 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4804 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4809 /* Check if we are about to insert bookkeeping copy before a jump, and use
4810 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4811 next = NEXT_INSN (place_to_insert);
4814 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4816 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4817 seqno = INSN_SEQNO (next);
4819 else if (INSN_SEQNO (join_point) > 0)
4820 seqno = INSN_SEQNO (join_point);
4823 seqno = get_seqno_by_preds (place_to_insert);
4825 /* Sometimes the fences can move in such a way that there will be
4826 no instructions with positive seqno around this bookkeeping.
4827 This means that there will be no way to get to it by a regular
4828 fence movement. Never mind because we pick up such pieces for
4829 rescheduling anyways, so any positive value will do for now. */
4832 gcc_assert (pipelining_p);
4837 gcc_assert (seqno > 0);
4841 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4842 NEW_SEQNO to it. Return created insn. */
4844 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4846 rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4849 = create_vinsn_from_insn_rtx (new_insn_rtx,
4850 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4852 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4855 INSN_SCHED_TIMES (new_insn) = 0;
4856 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4861 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4862 E2->dest, except from E1->src (there may be a sequence of empty blocks
4863 between E1->src and E2->dest). Return block containing the copy.
4864 All scheduler data is initialized for the newly created insn. */
4866 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4868 insn_t join_point, place_to_insert, new_insn;
4870 bool need_to_exchange_data_sets;
4872 if (sched_verbose >= 4)
4873 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4876 join_point = sel_bb_head (e2->dest);
4877 place_to_insert = find_place_for_bookkeeping (e1, e2);
4878 if (!place_to_insert)
4880 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4881 need_to_exchange_data_sets
4882 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4884 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4886 /* When inserting bookkeeping insn in new block, av sets should be
4887 following: old basic block (that now holds bookkeeping) data sets are
4888 the same as was before generation of bookkeeping, and new basic block
4889 (that now hold all other insns of old basic block) data sets are
4890 invalid. So exchange data sets for these basic blocks as sel_split_block
4891 mistakenly exchanges them in this case. Cannot do it earlier because
4892 when single instruction is added to new basic block it should hold NULL
4894 if (need_to_exchange_data_sets)
4895 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4896 BLOCK_FOR_INSN (join_point));
4898 stat_bookkeeping_copies++;
4899 return BLOCK_FOR_INSN (new_insn);
4902 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4903 on FENCE, but we are unable to copy them. */
4905 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4910 /* An expression does not need bookkeeping if it is available on all paths
4911 from current block to original block and current block dominates
4912 original block. We check availability on all paths by examining
4913 EXPR_SPEC; this is not equivalent, because it may be positive even
4914 if expr is available on all paths (but if expr is not available on
4915 any path, EXPR_SPEC will be positive). */
4917 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4919 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4920 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4921 && (EXPR_SPEC (expr)
4922 || !EXPR_ORIG_BB_INDEX (expr)
4923 || !dominated_by_p (CDI_DOMINATORS,
4924 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr)),
4925 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4927 if (sched_verbose >= 4)
4928 sel_print ("Expr %d removed because it would need bookkeeping, which "
4929 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4930 av_set_iter_remove (&i);
4935 /* Moving conditional jump through some instructions.
4939 ... <- current scheduling point
4940 NOTE BASIC BLOCK: <- bb header
4941 (p8) add r14=r14+0x9;;
4947 We can schedule jump one cycle earlier, than mov, because they cannot be
4948 executed together as their predicates are mutually exclusive.
4950 This is done in this way: first, new fallthrough basic block is created
4951 after jump (it is always can be done, because there already should be a
4952 fallthrough block, where control flow goes in case of predicate being true -
4953 in our example; otherwise there should be a dependence between those
4954 instructions and jump and we cannot schedule jump right now);
4955 next, all instructions between jump and current scheduling point are moved
4956 to this new block. And the result is this:
4959 (!p8) jump L1 <- current scheduling point
4960 NOTE BASIC BLOCK: <- bb header
4961 (p8) add r14=r14+0x9;;
4967 move_cond_jump (rtx insn, bnd_t bnd)
4970 basic_block block_from, block_next, block_new, block_bnd, bb;
4971 rtx next, prev, link, head;
4973 block_from = BLOCK_FOR_INSN (insn);
4974 block_bnd = BLOCK_FOR_INSN (BND_TO (bnd));
4975 prev = BND_TO (bnd);
4977 #ifdef ENABLE_CHECKING
4978 /* Moving of jump should not cross any other jumps or beginnings of new
4979 basic blocks. The only exception is when we move a jump through
4980 mutually exclusive insns along fallthru edges. */
4981 if (block_from != block_bnd)
4984 for (link = PREV_INSN (insn); link != PREV_INSN (prev);
4985 link = PREV_INSN (link))
4988 gcc_assert (sched_insns_conditions_mutex_p (insn, link));
4989 if (BLOCK_FOR_INSN (link) && BLOCK_FOR_INSN (link) != bb)
4991 gcc_assert (single_pred (bb) == BLOCK_FOR_INSN (link));
4992 bb = BLOCK_FOR_INSN (link);
4998 /* Jump is moved to the boundary. */
4999 next = PREV_INSN (insn);
5000 BND_TO (bnd) = insn;
5002 ft_edge = find_fallthru_edge_from (block_from);
5003 block_next = ft_edge->dest;
5004 /* There must be a fallthrough block (or where should go
5005 control flow in case of false jump predicate otherwise?). */
5006 gcc_assert (block_next);
5008 /* Create new empty basic block after source block. */
5009 block_new = sel_split_edge (ft_edge);
5010 gcc_assert (block_new->next_bb == block_next
5011 && block_from->next_bb == block_new);
5013 /* Move all instructions except INSN to BLOCK_NEW. */
5015 head = BB_HEAD (block_new);
5016 while (bb != block_from->next_bb)
5019 from = bb == block_bnd ? prev : sel_bb_head (bb);
5020 to = bb == block_from ? next : sel_bb_end (bb);
5022 /* The jump being moved can be the first insn in the block.
5023 In this case we don't have to move anything in this block. */
5024 if (NEXT_INSN (to) != from)
5026 reorder_insns (from, to, head);
5028 for (link = to; link != head; link = PREV_INSN (link))
5029 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
5033 /* Cleanup possibly empty blocks left. */
5034 block_next = bb->next_bb;
5035 if (bb != block_from)
5036 tidy_control_flow (bb, false);
5040 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
5041 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
5043 gcc_assert (!sel_bb_empty_p (block_from)
5044 && !sel_bb_empty_p (block_new));
5046 /* Update data sets for BLOCK_NEW to represent that INSN and
5047 instructions from the other branch of INSN is no longer
5048 available at BLOCK_NEW. */
5049 BB_AV_LEVEL (block_new) = global_level;
5050 gcc_assert (BB_LV_SET (block_new) == NULL);
5051 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
5052 update_data_sets (sel_bb_head (block_new));
5054 /* INSN is a new basic block header - so prepare its data
5055 structures and update availability and liveness sets. */
5056 update_data_sets (insn);
5058 if (sched_verbose >= 4)
5059 sel_print ("Moving jump %d\n", INSN_UID (insn));
5062 /* Remove nops generated during move_op for preventing removal of empty
5065 remove_temp_moveop_nops (bool full_tidying)
5070 FOR_EACH_VEC_ELT (insn_t, vec_temp_moveop_nops, i, insn)
5072 gcc_assert (INSN_NOP_P (insn));
5073 return_nop_to_pool (insn, full_tidying);
5076 /* Empty the vector. */
5077 if (VEC_length (insn_t, vec_temp_moveop_nops) > 0)
5078 VEC_block_remove (insn_t, vec_temp_moveop_nops, 0,
5079 VEC_length (insn_t, vec_temp_moveop_nops));
5082 /* Records the maximal UID before moving up an instruction. Used for
5083 distinguishing between bookkeeping copies and original insns. */
5084 static int max_uid_before_move_op = 0;
5086 /* Remove from AV_VLIW_P all instructions but next when debug counter
5087 tells us so. Next instruction is fetched from BNDS. */
5089 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
5091 if (! dbg_cnt (sel_sched_insn_cnt))
5092 /* Leave only the next insn in av_vliw. */
5094 av_set_iterator av_it;
5096 bnd_t bnd = BLIST_BND (bnds);
5097 insn_t next = BND_TO (bnd);
5099 gcc_assert (BLIST_NEXT (bnds) == NULL);
5101 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
5102 if (EXPR_INSN_RTX (expr) != next)
5103 av_set_iter_remove (&av_it);
5107 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5108 the computed set to *AV_VLIW_P. */
5110 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
5112 if (sched_verbose >= 2)
5114 sel_print ("Boundaries: ");
5119 for (; bnds; bnds = BLIST_NEXT (bnds))
5121 bnd_t bnd = BLIST_BND (bnds);
5123 insn_t bnd_to = BND_TO (bnd);
5125 /* Rewind BND->TO to the basic block header in case some bookkeeping
5126 instructions were inserted before BND->TO and it needs to be
5128 if (sel_bb_head_p (bnd_to))
5129 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
5131 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
5133 bnd_to = PREV_INSN (bnd_to);
5134 if (sel_bb_head_p (bnd_to))
5138 if (BND_TO (bnd) != bnd_to)
5140 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
5141 FENCE_INSN (fence) = bnd_to;
5142 BND_TO (bnd) = bnd_to;
5145 av_set_clear (&BND_AV (bnd));
5146 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
5148 av_set_clear (&BND_AV1 (bnd));
5149 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
5151 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
5153 av1_copy = av_set_copy (BND_AV1 (bnd));
5154 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
5157 if (sched_verbose >= 2)
5159 sel_print ("Available exprs (vliw form): ");
5160 dump_av_set (*av_vliw_p);
5165 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5166 expression. When FOR_MOVEOP is true, also replace the register of
5167 expressions found with the register from EXPR_VLIW. */
5169 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
5171 av_set_t expr_seq = NULL;
5175 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
5177 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
5181 /* The sequential expression has the right form to pass
5182 to move_op except when renaming happened. Put the
5183 correct register in EXPR then. */
5184 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
5186 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
5188 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
5189 stat_renamed_scheduled++;
5191 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5192 This is needed when renaming came up with original
5194 else if (EXPR_TARGET_AVAILABLE (expr)
5195 != EXPR_TARGET_AVAILABLE (expr_vliw))
5197 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
5198 EXPR_TARGET_AVAILABLE (expr) = 1;
5201 if (EXPR_WAS_SUBSTITUTED (expr))
5202 stat_substitutions_total++;
5205 av_set_add (&expr_seq, expr);
5207 /* With substitution inside insn group, it is possible
5208 that more than one expression in expr_seq will correspond
5209 to expr_vliw. In this case, choose one as the attempt to
5210 move both leads to miscompiles. */
5215 if (for_moveop && sched_verbose >= 2)
5217 sel_print ("Best expression(s) (sequential form): ");
5218 dump_av_set (expr_seq);
5226 /* Move nop to previous block. */
5227 static void ATTRIBUTE_UNUSED
5228 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
5230 insn_t prev_insn, next_insn, note;
5232 gcc_assert (sel_bb_head_p (nop)
5233 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
5234 note = bb_note (BLOCK_FOR_INSN (nop));
5235 prev_insn = sel_bb_end (prev_bb);
5236 next_insn = NEXT_INSN (nop);
5237 gcc_assert (prev_insn != NULL_RTX
5238 && PREV_INSN (note) == prev_insn);
5240 NEXT_INSN (prev_insn) = nop;
5241 PREV_INSN (nop) = prev_insn;
5243 PREV_INSN (note) = nop;
5244 NEXT_INSN (note) = next_insn;
5246 NEXT_INSN (nop) = note;
5247 PREV_INSN (next_insn) = note;
5249 BB_END (prev_bb) = nop;
5250 BLOCK_FOR_INSN (nop) = prev_bb;
5253 /* Prepare a place to insert the chosen expression on BND. */
5255 prepare_place_to_insert (bnd_t bnd)
5257 insn_t place_to_insert;
5259 /* Init place_to_insert before calling move_op, as the later
5260 can possibly remove BND_TO (bnd). */
5261 if (/* If this is not the first insn scheduled. */
5264 /* Add it after last scheduled. */
5265 place_to_insert = ILIST_INSN (BND_PTR (bnd));
5266 if (DEBUG_INSN_P (place_to_insert))
5268 ilist_t l = BND_PTR (bnd);
5269 while ((l = ILIST_NEXT (l)) &&
5270 DEBUG_INSN_P (ILIST_INSN (l)))
5273 place_to_insert = NULL;
5277 place_to_insert = NULL;
5279 if (!place_to_insert)
5281 /* Add it before BND_TO. The difference is in the
5282 basic block, where INSN will be added. */
5283 place_to_insert = get_nop_from_pool (BND_TO (bnd));
5284 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
5285 == BLOCK_FOR_INSN (BND_TO (bnd)));
5288 return place_to_insert;
5291 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5292 Return the expression to emit in C_EXPR. */
5294 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5295 av_set_t expr_seq, expr_t c_expr)
5297 bool b, should_move;
5300 int n_bookkeeping_copies_before_moveop;
5302 /* Make a move. This call will remove the original operation,
5303 insert all necessary bookkeeping instructions and update the
5304 data sets. After that all we have to do is add the operation
5305 at before BND_TO (BND). */
5306 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5307 max_uid_before_move_op = get_max_uid ();
5308 bitmap_clear (current_copies);
5309 bitmap_clear (current_originators);
5311 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5312 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5314 /* We should be able to find the expression we've chosen for
5318 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5319 stat_insns_needed_bookkeeping++;
5321 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5326 /* We allocate these bitmaps lazily. */
5327 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5328 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5330 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5331 current_originators);
5333 /* Transitively add all originators' originators. */
5334 EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi)
5335 if (INSN_ORIGINATORS_BY_UID (uid))
5336 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid),
5337 INSN_ORIGINATORS_BY_UID (uid));
5344 /* Debug a DFA state as an array of bytes. */
5346 debug_state (state_t state)
5349 unsigned int i, size = dfa_state_size;
5351 sel_print ("state (%u):", size);
5352 for (i = 0, p = (unsigned char *) state; i < size; i++)
5353 sel_print (" %d", p[i]);
5357 /* Advance state on FENCE with INSN. Return true if INSN is
5358 an ASM, and we should advance state once more. */
5360 advance_state_on_fence (fence_t fence, insn_t insn)
5364 if (recog_memoized (insn) >= 0)
5367 state_t temp_state = alloca (dfa_state_size);
5369 gcc_assert (!INSN_ASM_P (insn));
5372 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5373 res = state_transition (FENCE_STATE (fence), insn);
5374 gcc_assert (res < 0);
5376 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5378 FENCE_ISSUED_INSNS (fence)++;
5380 /* We should never issue more than issue_rate insns. */
5381 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5387 /* This could be an ASM insn which we'd like to schedule
5388 on the next cycle. */
5389 asm_p = INSN_ASM_P (insn);
5390 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5391 advance_one_cycle (fence);
5394 if (sched_verbose >= 2)
5395 debug_state (FENCE_STATE (fence));
5396 if (!DEBUG_INSN_P (insn))
5397 FENCE_STARTS_CYCLE_P (fence) = 0;
5398 FENCE_ISSUE_MORE (fence) = can_issue_more;
5402 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5403 is nonzero if we need to stall after issuing INSN. */
5405 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5409 /* First, reflect that something is scheduled on this fence. */
5410 asm_p = advance_state_on_fence (fence, insn);
5411 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5412 VEC_safe_push (rtx, gc, FENCE_EXECUTING_INSNS (fence), insn);
5413 if (SCHED_GROUP_P (insn))
5415 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5416 SCHED_GROUP_P (insn) = 0;
5419 FENCE_SCHED_NEXT (fence) = NULL_RTX;
5420 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5421 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5423 /* Set instruction scheduling info. This will be used in bundling,
5424 pipelining, tick computations etc. */
5425 ++INSN_SCHED_TIMES (insn);
5426 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5427 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5428 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5429 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5431 /* This does not account for adjust_cost hooks, just add the biggest
5432 constant the hook may add to the latency. TODO: make this
5433 a target dependent constant. */
5434 INSN_READY_CYCLE (insn)
5435 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5437 : maximal_insn_latency (insn) + 1);
5439 /* Change these fields last, as they're used above. */
5440 FENCE_AFTER_STALL_P (fence) = 0;
5441 if (asm_p || need_stall)
5442 advance_one_cycle (fence);
5444 /* Indicate that we've scheduled something on this fence. */
5445 FENCE_SCHEDULED_P (fence) = true;
5446 scheduled_something_on_previous_fence = true;
5448 /* Print debug information when insn's fields are updated. */
5449 if (sched_verbose >= 2)
5451 sel_print ("Scheduling insn: ");
5452 dump_insn_1 (insn, 1);
5457 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5458 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5461 update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp,
5462 blist_t *bnds_tailp)
5467 advance_deps_context (BND_DC (bnd), insn);
5468 FOR_EACH_SUCC_1 (succ, si, insn,
5469 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5471 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5473 ilist_add (&ptr, insn);
5475 if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn)
5476 && is_ineligible_successor (succ, ptr))
5482 if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn))
5484 if (sched_verbose >= 9)
5485 sel_print ("Updating fence insn from %i to %i\n",
5486 INSN_UID (insn), INSN_UID (succ));
5487 FENCE_INSN (fence) = succ;
5489 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5490 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5493 blist_remove (bndsp);
5497 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5499 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5502 expr_t c_expr = XALLOCA (expr_def);
5503 insn_t place_to_insert;
5507 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5509 /* In case of scheduling a jump skipping some other instructions,
5510 prepare CFG. After this, jump is at the boundary and can be
5511 scheduled as usual insn by MOVE_OP. */
5512 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5514 insn = EXPR_INSN_RTX (expr_vliw);
5516 /* Speculative jumps are not handled. */
5517 if (insn != BND_TO (bnd)
5518 && !sel_insn_is_speculation_check (insn))
5519 move_cond_jump (insn, bnd);
5522 /* Find a place for C_EXPR to schedule. */
5523 place_to_insert = prepare_place_to_insert (bnd);
5524 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5525 clear_expr (c_expr);
5527 /* Add the instruction. The corner case to care about is when
5528 the expr_seq set has more than one expr, and we chose the one that
5529 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5530 we can't use it. Generate the new vinsn. */
5531 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5535 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5536 change_vinsn_in_expr (expr_vliw, vinsn_new);
5537 should_move = false;
5540 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5542 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5545 /* Return the nops generated for preserving of data sets back
5547 if (INSN_NOP_P (place_to_insert))
5548 return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn));
5549 remove_temp_moveop_nops (!DEBUG_INSN_P (insn));
5551 av_set_clear (&expr_seq);
5553 /* Save the expression scheduled so to reset target availability if we'll
5554 meet it later on the same fence. */
5555 if (EXPR_WAS_RENAMED (expr_vliw))
5556 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5558 /* Check that the recent movement didn't destroyed loop
5560 gcc_assert (!pipelining_p
5561 || current_loop_nest == NULL
5562 || loop_latch_edge (current_loop_nest));
5566 /* Stall for N cycles on FENCE. */
5568 stall_for_cycles (fence_t fence, int n)
5572 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5574 advance_one_cycle (fence);
5576 FENCE_AFTER_STALL_P (fence) = 1;
5579 /* Gather a parallel group of insns at FENCE and assign their seqno
5580 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5581 list for later recalculation of seqnos. */
5583 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5585 blist_t bnds = NULL, *bnds_tailp;
5586 av_set_t av_vliw = NULL;
5587 insn_t insn = FENCE_INSN (fence);
5589 if (sched_verbose >= 2)
5590 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5591 INSN_UID (insn), FENCE_CYCLE (fence));
5593 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5594 bnds_tailp = &BLIST_NEXT (bnds);
5595 set_target_context (FENCE_TC (fence));
5596 can_issue_more = FENCE_ISSUE_MORE (fence);
5597 target_bb = INSN_BB (insn);
5599 /* Do while we can add any operation to the current group. */
5602 blist_t *bnds_tailp1, *bndsp;
5605 int was_stall = 0, scheduled_insns = 0;
5606 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5607 int max_stall = pipelining_p ? 1 : 3;
5608 bool last_insn_was_debug = false;
5609 bool was_debug_bb_end_p = false;
5611 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5612 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5613 remove_insns_for_debug (bnds, &av_vliw);
5615 /* Return early if we have nothing to schedule. */
5616 if (av_vliw == NULL)
5619 /* Choose the best expression and, if needed, destination register
5623 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5624 if (! expr_vliw && need_stall)
5626 /* All expressions required a stall. Do not recompute av sets
5627 as we'll get the same answer (modulo the insns between
5628 the fence and its boundary, which will not be available for
5630 If we are going to stall for too long, break to recompute av
5631 sets and bring more insns for pipelining. */
5633 if (need_stall <= 3)
5634 stall_for_cycles (fence, need_stall);
5637 stall_for_cycles (fence, 1);
5642 while (! expr_vliw && need_stall);
5644 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5647 av_set_clear (&av_vliw);
5652 bnds_tailp1 = bnds_tailp;
5655 /* This code will be executed only once until we'd have several
5656 boundaries per fence. */
5658 bnd_t bnd = BLIST_BND (*bndsp);
5660 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5662 bndsp = &BLIST_NEXT (*bndsp);
5666 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5667 last_insn_was_debug = DEBUG_INSN_P (insn);
5668 if (last_insn_was_debug)
5669 was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn));
5670 update_fence_and_insn (fence, insn, need_stall);
5671 bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp);
5673 /* Add insn to the list of scheduled on this cycle instructions. */
5674 ilist_add (*scheduled_insns_tailpp, insn);
5675 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5677 while (*bndsp != *bnds_tailp1);
5679 av_set_clear (&av_vliw);
5680 if (!last_insn_was_debug)
5683 /* We currently support information about candidate blocks only for
5684 one 'target_bb' block. Hence we can't schedule after jump insn,
5685 as this will bring two boundaries and, hence, necessity to handle
5686 information for two or more blocks concurrently. */
5687 if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn))
5689 && (was_stall >= max_stall
5690 || scheduled_insns >= max_insns)))
5695 gcc_assert (!FENCE_BNDS (fence));
5697 /* Update boundaries of the FENCE. */
5700 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5704 insn = ILIST_INSN (ptr);
5706 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5707 ilist_add (&FENCE_BNDS (fence), insn);
5710 blist_remove (&bnds);
5713 /* Update target context on the fence. */
5714 reset_target_context (FENCE_TC (fence), false);
5717 /* All exprs in ORIG_OPS must have the same destination register or memory.
5718 Return that destination. */
5720 get_dest_from_orig_ops (av_set_t orig_ops)
5722 rtx dest = NULL_RTX;
5723 av_set_iterator av_it;
5725 bool first_p = true;
5727 FOR_EACH_EXPR (expr, av_it, orig_ops)
5729 rtx x = EXPR_LHS (expr);
5737 gcc_assert (dest == x
5738 || (dest != NULL_RTX && x != NULL_RTX
5739 && rtx_equal_p (dest, x)));
5745 /* Update data sets for the bookkeeping block and record those expressions
5746 which become no longer available after inserting this bookkeeping. */
5748 update_and_record_unavailable_insns (basic_block book_block)
5751 av_set_t old_av_set = NULL;
5753 rtx bb_end = sel_bb_end (book_block);
5755 /* First, get correct liveness in the bookkeeping block. The problem is
5756 the range between the bookeeping insn and the end of block. */
5757 update_liveness_on_insn (bb_end);
5758 if (control_flow_insn_p (bb_end))
5759 update_liveness_on_insn (PREV_INSN (bb_end));
5761 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5762 fence above, where we may choose to schedule an insn which is
5763 actually blocked from moving up with the bookkeeping we create here. */
5764 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5766 old_av_set = av_set_copy (BB_AV_SET (book_block));
5767 update_data_sets (sel_bb_head (book_block));
5769 /* Traverse all the expressions in the old av_set and check whether
5770 CUR_EXPR is in new AV_SET. */
5771 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5773 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5774 EXPR_VINSN (cur_expr));
5777 /* In this case, we can just turn off the E_T_A bit, but we can't
5778 represent this information with the current vector. */
5779 || EXPR_TARGET_AVAILABLE (new_expr)
5780 != EXPR_TARGET_AVAILABLE (cur_expr))
5781 /* Unfortunately, the below code could be also fired up on
5782 separable insns, e.g. when moving insns through the new
5783 speculation check as in PR 53701. */
5784 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5787 av_set_clear (&old_av_set);
5791 /* The main effect of this function is that sparams->c_expr is merged
5792 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5793 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5794 lparams->c_expr_merged is copied back to sparams->c_expr after all
5795 successors has been traversed. lparams->c_expr_local is an expr allocated
5796 on stack in the caller function, and is used if there is more than one
5799 SUCC is one of the SUCCS_NORMAL successors of INSN,
5800 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5801 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5803 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5804 insn_t succ ATTRIBUTE_UNUSED,
5805 int moveop_drv_call_res,
5806 cmpd_local_params_p lparams, void *static_params)
5808 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5810 /* Nothing to do, if original expr wasn't found below. */
5811 if (moveop_drv_call_res != 1)
5814 /* If this is a first successor. */
5815 if (!lparams->c_expr_merged)
5817 lparams->c_expr_merged = sparams->c_expr;
5818 sparams->c_expr = lparams->c_expr_local;
5822 /* We must merge all found expressions to get reasonable
5823 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5824 do so then we can first find the expr with epsilon
5825 speculation success probability and only then with the
5826 good probability. As a result the insn will get epsilon
5827 probability and will never be scheduled because of
5828 weakness_cutoff in find_best_expr.
5830 We call merge_expr_data here instead of merge_expr
5831 because due to speculation C_EXPR and X may have the
5832 same insns with different speculation types. And as of
5833 now such insns are considered non-equal.
5835 However, EXPR_SCHED_TIMES is different -- we must get
5836 SCHED_TIMES from a real insn, not a bookkeeping copy.
5837 We force this here. Instead, we may consider merging
5838 SCHED_TIMES to the maximum instead of minimum in the
5840 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5842 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5843 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5844 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5846 clear_expr (sparams->c_expr);
5850 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5852 SUCC is one of the SUCCS_NORMAL successors of INSN,
5853 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5854 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5855 STATIC_PARAMS contain USED_REGS set. */
5857 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5858 int moveop_drv_call_res,
5859 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5860 void *static_params)
5863 fur_static_params_p sparams = (fur_static_params_p) static_params;
5865 /* Here we compute live regsets only for branches that do not lie
5866 on the code motion paths. These branches correspond to value
5867 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5868 for such branches code_motion_path_driver is not called. */
5869 if (moveop_drv_call_res != 0)
5872 /* Mark all registers that do not meet the following condition:
5873 (3) not live on the other path of any conditional branch
5874 that is passed by the operation, in case original
5875 operations are not present on both paths of the
5876 conditional branch. */
5877 succ_live = compute_live (succ);
5878 IOR_REG_SET (sparams->used_regs, succ_live);
5881 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5884 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5886 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5888 sp->c_expr = lp->c_expr_merged;
5891 /* Track bookkeeping copies created, insns scheduled, and blocks for
5892 rescheduling when INSN is found by move_op. */
5894 track_scheduled_insns_and_blocks (rtx insn)
5896 /* Even if this insn can be a copy that will be removed during current move_op,
5897 we still need to count it as an originator. */
5898 bitmap_set_bit (current_originators, INSN_UID (insn));
5900 if (!bitmap_clear_bit (current_copies, INSN_UID (insn)))
5902 /* Note that original block needs to be rescheduled, as we pulled an
5903 instruction out of it. */
5904 if (INSN_SCHED_TIMES (insn) > 0)
5905 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5906 else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn))
5907 num_insns_scheduled++;
5910 /* For instructions we must immediately remove insn from the
5911 stream, so subsequent update_data_sets () won't include this
5913 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5914 if (INSN_UID (insn) > max_uid_before_move_op)
5915 stat_bookkeeping_copies--;
5918 /* Emit a register-register copy for INSN if needed. Return true if
5919 emitted one. PARAMS is the move_op static parameters. */
5921 maybe_emit_renaming_copy (rtx insn,
5922 moveop_static_params_p params)
5924 bool insn_emitted = false;
5927 /* Bail out early when expression can not be renamed at all. */
5928 if (!EXPR_SEPARABLE_P (params->c_expr))
5931 cur_reg = expr_dest_reg (params->c_expr);
5932 gcc_assert (cur_reg && params->dest && REG_P (params->dest));
5934 /* If original operation has expr and the register chosen for
5935 that expr is not original operation's dest reg, substitute
5936 operation's right hand side with the register chosen. */
5937 if (REGNO (params->dest) != REGNO (cur_reg))
5939 insn_t reg_move_insn, reg_move_insn_rtx;
5941 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5943 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5947 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5948 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5950 insn_emitted = true;
5951 params->was_renamed = true;
5954 return insn_emitted;
5957 /* Emit a speculative check for INSN speculated as EXPR if needed.
5958 Return true if we've emitted one. PARAMS is the move_op static
5961 maybe_emit_speculative_check (rtx insn, expr_t expr,
5962 moveop_static_params_p params)
5964 bool insn_emitted = false;
5968 check_ds = get_spec_check_type_for_insn (insn, expr);
5971 /* A speculation check should be inserted. */
5972 x = create_speculation_check (params->c_expr, check_ds, insn);
5973 insn_emitted = true;
5977 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5981 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5982 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5983 return insn_emitted;
5986 /* Handle transformations that leave an insn in place of original
5987 insn such as renaming/speculation. Return true if one of such
5988 transformations actually happened, and we have emitted this insn. */
5990 handle_emitting_transformations (rtx insn, expr_t expr,
5991 moveop_static_params_p params)
5993 bool insn_emitted = false;
5995 insn_emitted = maybe_emit_renaming_copy (insn, params);
5996 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5998 return insn_emitted;
6001 /* If INSN is the only insn in the basic block (not counting JUMP,
6002 which may be a jump to next insn, and DEBUG_INSNs), we want to
6003 leave a NOP there till the return to fill_insns. */
6006 need_nop_to_preserve_insn_bb (rtx insn)
6008 insn_t bb_head, bb_end, bb_next, in_next;
6009 basic_block bb = BLOCK_FOR_INSN (insn);
6011 bb_head = sel_bb_head (bb);
6012 bb_end = sel_bb_end (bb);
6014 if (bb_head == bb_end)
6017 while (bb_head != bb_end && DEBUG_INSN_P (bb_head))
6018 bb_head = NEXT_INSN (bb_head);
6020 if (bb_head == bb_end)
6023 while (bb_head != bb_end && DEBUG_INSN_P (bb_end))
6024 bb_end = PREV_INSN (bb_end);
6026 if (bb_head == bb_end)
6029 bb_next = NEXT_INSN (bb_head);
6030 while (bb_next != bb_end && DEBUG_INSN_P (bb_next))
6031 bb_next = NEXT_INSN (bb_next);
6033 if (bb_next == bb_end && JUMP_P (bb_end))
6036 in_next = NEXT_INSN (insn);
6037 while (DEBUG_INSN_P (in_next))
6038 in_next = NEXT_INSN (in_next);
6040 if (IN_CURRENT_FENCE_P (in_next))
6046 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
6047 is not removed but reused when INSN is re-emitted. */
6049 remove_insn_from_stream (rtx insn, bool only_disconnect)
6051 /* If there's only one insn in the BB, make sure that a nop is
6052 inserted into it, so the basic block won't disappear when we'll
6053 delete INSN below with sel_remove_insn. It should also survive
6054 till the return to fill_insns. */
6055 if (need_nop_to_preserve_insn_bb (insn))
6057 insn_t nop = get_nop_from_pool (insn);
6058 gcc_assert (INSN_NOP_P (nop));
6059 VEC_safe_push (insn_t, heap, vec_temp_moveop_nops, nop);
6062 sel_remove_insn (insn, only_disconnect, false);
6065 /* This function is called when original expr is found.
6066 INSN - current insn traversed, EXPR - the corresponding expr found.
6067 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
6068 is static parameters of move_op. */
6070 move_op_orig_expr_found (insn_t insn, expr_t expr,
6071 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6072 void *static_params)
6074 bool only_disconnect, insn_emitted;
6075 moveop_static_params_p params = (moveop_static_params_p) static_params;
6077 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
6078 track_scheduled_insns_and_blocks (insn);
6079 insn_emitted = handle_emitting_transformations (insn, expr, params);
6080 only_disconnect = (params->uid == INSN_UID (insn)
6081 && ! insn_emitted && ! EXPR_WAS_CHANGED (expr));
6083 /* Mark that we've disconnected an insn. */
6084 if (only_disconnect)
6086 remove_insn_from_stream (insn, only_disconnect);
6089 /* The function is called when original expr is found.
6090 INSN - current insn traversed, EXPR - the corresponding expr found,
6091 crosses_call and original_insns in STATIC_PARAMS are updated. */
6093 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
6094 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6095 void *static_params)
6097 fur_static_params_p params = (fur_static_params_p) static_params;
6101 params->crosses_call = true;
6103 def_list_add (params->original_insns, insn, params->crosses_call);
6105 /* Mark the registers that do not meet the following condition:
6106 (2) not among the live registers of the point
6107 immediately following the first original operation on
6108 a given downward path, except for the original target
6109 register of the operation. */
6110 tmp = get_clear_regset_from_pool ();
6111 compute_live_below_insn (insn, tmp);
6112 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
6113 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
6114 IOR_REG_SET (params->used_regs, tmp);
6115 return_regset_to_pool (tmp);
6117 /* (*1) We need to add to USED_REGS registers that are read by
6118 INSN's lhs. This may lead to choosing wrong src register.
6119 E.g. (scheduling const expr enabled):
6121 429: ax=0x0 <- Can't use AX for this expr (0x0)
6128 /* FIXME: see comment above and enable MEM_P
6129 in vinsn_separable_p. */
6130 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
6131 || !MEM_P (INSN_LHS (insn)));
6134 /* This function is called on the ascending pass, before returning from
6135 current basic block. */
6137 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
6138 void *static_params)
6140 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6141 basic_block book_block = NULL;
6143 /* When we have removed the boundary insn for scheduling, which also
6144 happened to be the end insn in its bb, we don't need to update sets. */
6145 if (!lparams->removed_last_insn
6147 && sel_bb_head_p (insn))
6149 /* We should generate bookkeeping code only if we are not at the
6150 top level of the move_op. */
6151 if (sel_num_cfg_preds_gt_1 (insn))
6152 book_block = generate_bookkeeping_insn (sparams->c_expr,
6153 lparams->e1, lparams->e2);
6154 /* Update data sets for the current insn. */
6155 update_data_sets (insn);
6158 /* If bookkeeping code was inserted, we need to update av sets of basic
6159 block that received bookkeeping. After generation of bookkeeping insn,
6160 bookkeeping block does not contain valid av set because we are not following
6161 the original algorithm in every detail with regards to e.g. renaming
6162 simple reg-reg copies. Consider example:
6164 bookkeeping block scheduling fence
6174 We try to schedule insn "r1 := r3" on the current
6175 scheduling fence. Also, note that av set of bookkeeping block
6176 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6177 been scheduled, the CFG is as follows:
6180 bookkeeping block scheduling fence
6190 Here, insn "r1 := r3" was scheduled at the current scheduling point
6191 and bookkeeping code was generated at the bookeeping block. This
6192 way insn "r1 := r2" is no longer available as a whole instruction
6193 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6194 This situation is handled by calling update_data_sets.
6196 Since update_data_sets is called only on the bookkeeping block, and
6197 it also may have predecessors with av_sets, containing instructions that
6198 are no longer available, we save all such expressions that become
6199 unavailable during data sets update on the bookkeeping block in
6200 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6201 expressions for scheduling. This allows us to avoid recomputation of
6202 av_sets outside the code motion path. */
6205 update_and_record_unavailable_insns (book_block);
6207 /* If INSN was previously marked for deletion, it's time to do it. */
6208 if (lparams->removed_last_insn)
6209 insn = PREV_INSN (insn);
6211 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6212 kill a block with a single nop in which the insn should be emitted. */
6214 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
6217 /* This function is called on the ascending pass, before returning from the
6218 current basic block. */
6220 fur_at_first_insn (insn_t insn,
6221 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6222 void *static_params ATTRIBUTE_UNUSED)
6224 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
6225 || AV_LEVEL (insn) == -1);
6228 /* Called on the backward stage of recursion to call moveup_expr for insn
6229 and sparams->c_expr. */
6231 move_op_ascend (insn_t insn, void *static_params)
6233 enum MOVEUP_EXPR_CODE res;
6234 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6236 if (! INSN_NOP_P (insn))
6238 res = moveup_expr_cached (sparams->c_expr, insn, false);
6239 gcc_assert (res != MOVEUP_EXPR_NULL);
6242 /* Update liveness for this insn as it was invalidated. */
6243 update_liveness_on_insn (insn);
6246 /* This function is called on enter to the basic block.
6247 Returns TRUE if this block already have been visited and
6248 code_motion_path_driver should return 1, FALSE otherwise. */
6250 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
6251 void *static_params, bool visited_p)
6253 fur_static_params_p sparams = (fur_static_params_p) static_params;
6257 /* If we have found something below this block, there should be at
6258 least one insn in ORIGINAL_INSNS. */
6259 gcc_assert (*sparams->original_insns);
6261 /* Adjust CROSSES_CALL, since we may have come to this block along
6263 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
6264 |= sparams->crosses_call;
6267 local_params->old_original_insns = *sparams->original_insns;
6272 /* Same as above but for move_op. */
6274 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
6275 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
6276 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
6283 /* This function is called while descending current basic block if current
6284 insn is not the original EXPR we're searching for.
6286 Return value: FALSE, if code_motion_path_driver should perform a local
6287 cleanup and return 0 itself;
6288 TRUE, if code_motion_path_driver should continue. */
6290 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
6291 void *static_params)
6293 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6295 #ifdef ENABLE_CHECKING
6296 sparams->failed_insn = insn;
6299 /* If we're scheduling separate expr, in order to generate correct code
6300 we need to stop the search at bookkeeping code generated with the
6301 same destination register or memory. */
6302 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
6307 /* This function is called while descending current basic block if current
6308 insn is not the original EXPR we're searching for.
6310 Return value: TRUE (code_motion_path_driver should continue). */
6312 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
6316 av_set_iterator avi;
6317 fur_static_params_p sparams = (fur_static_params_p) static_params;
6320 sparams->crosses_call = true;
6321 else if (DEBUG_INSN_P (insn))
6324 /* If current insn we are looking at cannot be executed together
6325 with original insn, then we can skip it safely.
6327 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6328 INSN = (!p6) r14 = r14 + 1;
6330 Here we can schedule ORIG_OP with lhs = r14, though only
6331 looking at the set of used and set registers of INSN we must
6332 forbid it. So, add set/used in INSN registers to the
6333 untouchable set only if there is an insn in ORIG_OPS that can
6336 FOR_EACH_EXPR (r, avi, orig_ops)
6337 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
6343 /* Mark all registers that do not meet the following condition:
6344 (1) Not set or read on any path from xi to an instance of the
6345 original operation. */
6348 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6349 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6350 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6356 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6357 struct code_motion_path_driver_info_def move_op_hooks = {
6359 move_op_orig_expr_found,
6360 move_op_orig_expr_not_found,
6361 move_op_merge_succs,
6362 move_op_after_merge_succs,
6364 move_op_at_first_insn,
6369 /* Hooks and data to perform find_used_regs operations
6370 with code_motion_path_driver. */
6371 struct code_motion_path_driver_info_def fur_hooks = {
6373 fur_orig_expr_found,
6374 fur_orig_expr_not_found,
6376 NULL, /* fur_after_merge_succs */
6377 NULL, /* fur_ascend */
6383 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6384 code_motion_path_driver is called recursively. Original operation
6385 was found at least on one path that is starting with one of INSN's
6386 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6387 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6388 of either move_op or find_used_regs depending on the caller.
6390 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6391 know for sure at this point. */
6393 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6394 ilist_t path, void *static_params)
6397 succ_iterator succ_i;
6403 struct cmpd_local_params lparams;
6406 lparams.c_expr_local = &_x;
6407 lparams.c_expr_merged = NULL;
6409 /* We need to process only NORMAL succs for move_op, and collect live
6410 registers from ALL branches (including those leading out of the
6411 region) for find_used_regs.
6413 In move_op, there can be a case when insn's bb number has changed
6414 due to created bookkeeping. This happens very rare, as we need to
6415 move expression from the beginning to the end of the same block.
6416 Rescan successors in this case. */
6419 bb = BLOCK_FOR_INSN (insn);
6420 old_index = bb->index;
6421 old_succs = EDGE_COUNT (bb->succs);
6423 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6427 lparams.e1 = succ_i.e1;
6428 lparams.e2 = succ_i.e2;
6430 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6432 if (succ_i.current_flags == SUCCS_NORMAL)
6433 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6438 /* Merge c_expres found or unify live register sets from different
6440 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6444 else if (b == -1 && res != 1)
6447 /* We have simplified the control flow below this point. In this case,
6448 the iterator becomes invalid. We need to try again. */
6449 if (BLOCK_FOR_INSN (insn)->index != old_index
6450 || EDGE_COUNT (bb->succs) != old_succs)
6454 #ifdef ENABLE_CHECKING
6455 /* Here, RES==1 if original expr was found at least for one of the
6456 successors. After the loop, RES may happen to have zero value
6457 only if at some point the expr searched is present in av_set, but is
6458 not found below. In most cases, this situation is an error.
6459 The exception is when the original operation is blocked by
6460 bookkeeping generated for another fence or for another path in current
6462 gcc_assert (res == 1
6464 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops,
6469 /* Merge data, clean up, etc. */
6470 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6471 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6477 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6478 is the pointer to the av set with expressions we were looking for,
6479 PATH_P is the pointer to the traversed path. */
6481 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6483 ilist_remove (path_p);
6484 av_set_clear (orig_ops_p);
6487 /* The driver function that implements move_op or find_used_regs
6488 functionality dependent whether code_motion_path_driver_INFO is set to
6489 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6490 of code (CFG traversal etc) that are shared among both functions. INSN
6491 is the insn we're starting the search from, ORIG_OPS are the expressions
6492 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6493 parameters of the driver, and STATIC_PARAMS are static parameters of
6496 Returns whether original instructions were found. Note that top-level
6497 code_motion_path_driver always returns true. */
6499 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6500 cmpd_local_params_p local_params_in,
6501 void *static_params)
6504 basic_block bb = BLOCK_FOR_INSN (insn);
6505 insn_t first_insn, bb_tail, before_first;
6506 bool removed_last_insn = false;
6508 if (sched_verbose >= 6)
6510 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6513 dump_av_set (orig_ops);
6517 gcc_assert (orig_ops);
6519 /* If no original operations exist below this insn, return immediately. */
6520 if (is_ineligible_successor (insn, path))
6522 if (sched_verbose >= 6)
6523 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6527 /* The block can have invalid av set, in which case it was created earlier
6528 during move_op. Return immediately. */
6529 if (sel_bb_head_p (insn))
6531 if (! AV_SET_VALID_P (insn))
6533 if (sched_verbose >= 6)
6534 sel_print ("Returned from block %d as it had invalid av set\n",
6539 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6541 /* We have already found an original operation on this branch, do not
6542 go any further and just return TRUE here. If we don't stop here,
6543 function can have exponential behaviour even on the small code
6544 with many different paths (e.g. with data speculation and
6545 recovery blocks). */
6546 if (sched_verbose >= 6)
6547 sel_print ("Block %d already visited in this traversal\n", bb->index);
6548 if (code_motion_path_driver_info->on_enter)
6549 return code_motion_path_driver_info->on_enter (insn,
6556 if (code_motion_path_driver_info->on_enter)
6557 code_motion_path_driver_info->on_enter (insn, local_params_in,
6558 static_params, false);
6559 orig_ops = av_set_copy (orig_ops);
6561 /* Filter the orig_ops set. */
6562 if (AV_SET_VALID_P (insn))
6563 av_set_code_motion_filter (&orig_ops, AV_SET (insn));
6565 /* If no more original ops, return immediately. */
6568 if (sched_verbose >= 6)
6569 sel_print ("No intersection with av set of block %d\n", bb->index);
6573 /* For non-speculative insns we have to leave only one form of the
6574 original operation, because if we don't, we may end up with
6575 different C_EXPRes and, consequently, with bookkeepings for different
6576 expression forms along the same code motion path. That may lead to
6577 generation of incorrect code. So for each code motion we stick to
6578 the single form of the instruction, except for speculative insns
6579 which we need to keep in different forms with all speculation
6581 av_set_leave_one_nonspec (&orig_ops);
6583 /* It is not possible that all ORIG_OPS are filtered out. */
6584 gcc_assert (orig_ops);
6586 /* It is enough to place only heads and tails of visited basic blocks into
6588 ilist_add (&path, insn);
6590 bb_tail = sel_bb_end (bb);
6592 /* Descend the basic block in search of the original expr; this part
6593 corresponds to the part of the original move_op procedure executed
6594 before the recursive call. */
6597 /* Look at the insn and decide if it could be an ancestor of currently
6598 scheduling operation. If it is so, then the insn "dest = op" could
6599 either be replaced with "dest = reg", because REG now holds the result
6600 of OP, or just removed, if we've scheduled the insn as a whole.
6602 If this insn doesn't contain currently scheduling OP, then proceed
6603 with searching and look at its successors. Operations we're searching
6604 for could have changed when moving up through this insn via
6605 substituting. In this case, perform unsubstitution on them first.
6607 When traversing the DAG below this insn is finished, insert
6608 bookkeeping code, if the insn is a joint point, and remove
6611 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6614 insn_t last_insn = PREV_INSN (insn);
6616 /* We have found the original operation. */
6617 if (sched_verbose >= 6)
6618 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6620 code_motion_path_driver_info->orig_expr_found
6621 (insn, expr, local_params_in, static_params);
6623 /* Step back, so on the way back we'll start traversing from the
6624 previous insn (or we'll see that it's bb_note and skip that
6626 if (insn == first_insn)
6628 first_insn = NEXT_INSN (last_insn);
6629 removed_last_insn = sel_bb_end_p (last_insn);
6636 /* We haven't found the original expr, continue descending the basic
6638 if (code_motion_path_driver_info->orig_expr_not_found
6639 (insn, orig_ops, static_params))
6641 /* Av set ops could have been changed when moving through this
6642 insn. To find them below it, we have to un-substitute them. */
6643 undo_transformations (&orig_ops, insn);
6647 /* Clean up and return, if the hook tells us to do so. It may
6648 happen if we've encountered the previously created
6650 code_motion_path_driver_cleanup (&orig_ops, &path);
6654 gcc_assert (orig_ops);
6657 /* Stop at insn if we got to the end of BB. */
6658 if (insn == bb_tail)
6661 insn = NEXT_INSN (insn);
6664 /* Here INSN either points to the insn before the original insn (may be
6665 bb_note, if original insn was a bb_head) or to the bb_end. */
6670 gcc_assert (insn == sel_bb_end (bb));
6672 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6673 it's already in PATH then). */
6674 if (insn != first_insn)
6675 ilist_add (&path, insn);
6677 /* Process_successors should be able to find at least one
6678 successor for which code_motion_path_driver returns TRUE. */
6679 res = code_motion_process_successors (insn, orig_ops,
6680 path, static_params);
6682 /* Remove bb tail from path. */
6683 if (insn != first_insn)
6684 ilist_remove (&path);
6688 /* This is the case when one of the original expr is no longer available
6689 due to bookkeeping created on this branch with the same register.
6690 In the original algorithm, which doesn't have update_data_sets call
6691 on a bookkeeping block, it would simply result in returning
6692 FALSE when we've encountered a previously generated bookkeeping
6693 insn in moveop_orig_expr_not_found. */
6694 code_motion_path_driver_cleanup (&orig_ops, &path);
6699 /* Don't need it any more. */
6700 av_set_clear (&orig_ops);
6702 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6703 the beginning of the basic block. */
6704 before_first = PREV_INSN (first_insn);
6705 while (insn != before_first)
6707 if (code_motion_path_driver_info->ascend)
6708 code_motion_path_driver_info->ascend (insn, static_params);
6710 insn = PREV_INSN (insn);
6713 /* Now we're at the bb head. */
6715 ilist_remove (&path);
6716 local_params_in->removed_last_insn = removed_last_insn;
6717 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6719 /* This should be the very last operation as at bb head we could change
6720 the numbering by creating bookkeeping blocks. */
6721 if (removed_last_insn)
6722 insn = PREV_INSN (insn);
6723 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6727 /* Move up the operations from ORIG_OPS set traversing the dag starting
6728 from INSN. PATH represents the edges traversed so far.
6729 DEST is the register chosen for scheduling the current expr. Insert
6730 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6731 C_EXPR is how it looks like at the given cfg point.
6732 Set *SHOULD_MOVE to indicate whether we have only disconnected
6733 one of the insns found.
6735 Returns whether original instructions were found, which is asserted
6736 to be true in the caller. */
6738 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6739 rtx dest, expr_t c_expr, bool *should_move)
6741 struct moveop_static_params sparams;
6742 struct cmpd_local_params lparams;
6745 /* Init params for code_motion_path_driver. */
6746 sparams.dest = dest;
6747 sparams.c_expr = c_expr;
6748 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6749 #ifdef ENABLE_CHECKING
6750 sparams.failed_insn = NULL;
6752 sparams.was_renamed = false;
6755 /* We haven't visited any blocks yet. */
6756 bitmap_clear (code_motion_visited_blocks);
6758 /* Set appropriate hooks and data. */
6759 code_motion_path_driver_info = &move_op_hooks;
6760 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6762 if (sparams.was_renamed)
6763 EXPR_WAS_RENAMED (expr_vliw) = true;
6765 *should_move = (sparams.uid == -1);
6771 /* Functions that work with regions. */
6773 /* Current number of seqno used in init_seqno and init_seqno_1. */
6774 static int cur_seqno;
6776 /* A helper for init_seqno. Traverse the region starting from BB and
6777 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6778 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6780 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6782 int bbi = BLOCK_TO_BB (bb->index);
6783 insn_t insn, note = bb_note (bb);
6787 SET_BIT (visited_bbs, bbi);
6788 if (blocks_to_reschedule)
6789 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6791 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6792 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6794 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6795 int succ_bbi = BLOCK_TO_BB (succ->index);
6797 gcc_assert (in_current_region_p (succ));
6799 if (!TEST_BIT (visited_bbs, succ_bbi))
6801 gcc_assert (succ_bbi > bbi);
6803 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6805 else if (blocks_to_reschedule)
6806 bitmap_set_bit (forced_ebb_heads, succ->index);
6809 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6810 INSN_SEQNO (insn) = cur_seqno--;
6813 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6814 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6815 which we're rescheduling when pipelining, FROM is the block where
6816 traversing region begins (it may not be the head of the region when
6817 pipelining, but the head of the loop instead).
6819 Returns the maximal seqno found. */
6821 init_seqno (int number_of_insns, bitmap blocks_to_reschedule, basic_block from)
6823 sbitmap visited_bbs;
6827 visited_bbs = sbitmap_alloc (current_nr_blocks);
6829 if (blocks_to_reschedule)
6831 sbitmap_ones (visited_bbs);
6832 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6834 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6835 RESET_BIT (visited_bbs, BLOCK_TO_BB (bbi));
6840 sbitmap_zero (visited_bbs);
6841 from = EBB_FIRST_BB (0);
6844 cur_seqno = number_of_insns > 0 ? number_of_insns : sched_max_luid - 1;
6845 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6846 gcc_assert (cur_seqno == 0 || number_of_insns == 0);
6848 sbitmap_free (visited_bbs);
6849 return sched_max_luid - 1;
6852 /* Initialize scheduling parameters for current region. */
6854 sel_setup_region_sched_flags (void)
6856 enable_schedule_as_rhs_p = 1;
6858 pipelining_p = (bookkeeping_p
6859 && (flag_sel_sched_pipelining != 0)
6860 && current_loop_nest != NULL
6861 && loop_has_exit_edges (current_loop_nest));
6862 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6866 /* Return true if all basic blocks of current region are empty. */
6868 current_region_empty_p (void)
6871 for (i = 0; i < current_nr_blocks; i++)
6872 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i))))
6878 /* Prepare and verify loop nest for pipelining. */
6880 setup_current_loop_nest (int rgn)
6882 current_loop_nest = get_loop_nest_for_rgn (rgn);
6884 if (!current_loop_nest)
6887 /* If this loop has any saved loop preheaders from nested loops,
6888 add these basic blocks to the current region. */
6889 sel_add_loop_preheaders ();
6891 /* Check that we're starting with a valid information. */
6892 gcc_assert (loop_latch_edge (current_loop_nest));
6893 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6896 /* Compute instruction priorities for current region. */
6898 sel_compute_priorities (int rgn)
6900 sched_rgn_compute_dependencies (rgn);
6902 /* Compute insn priorities in haifa style. Then free haifa style
6903 dependencies that we've calculated for this. */
6904 compute_priorities ();
6906 if (sched_verbose >= 5)
6907 debug_rgn_dependencies (0);
6912 /* Init scheduling data for RGN. Returns true when this region should not
6915 sel_region_init (int rgn)
6920 rgn_setup_region (rgn);
6922 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6923 do region initialization here so the region can be bundled correctly,
6924 but we'll skip the scheduling in sel_sched_region (). */
6925 if (current_region_empty_p ())
6928 if (flag_sel_sched_pipelining)
6929 setup_current_loop_nest (rgn);
6931 sel_setup_region_sched_flags ();
6933 bbs = VEC_alloc (basic_block, heap, current_nr_blocks);
6935 for (i = 0; i < current_nr_blocks; i++)
6936 VEC_quick_push (basic_block, bbs, BASIC_BLOCK (BB_TO_BLOCK (i)));
6938 sel_init_bbs (bbs, NULL);
6940 /* Initialize luids and dependence analysis which both sel-sched and haifa
6942 sched_init_luids (bbs, NULL, NULL, NULL);
6943 sched_deps_init (false);
6945 /* Initialize haifa data. */
6946 rgn_setup_sched_infos ();
6947 sel_set_sched_flags ();
6948 haifa_init_h_i_d (bbs, NULL, NULL, NULL);
6950 sel_compute_priorities (rgn);
6951 init_deps_global ();
6953 /* Main initialization. */
6954 sel_setup_sched_infos ();
6955 sel_init_global_and_expr (bbs);
6957 VEC_free (basic_block, heap, bbs);
6959 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6961 /* Init correct liveness sets on each instruction of a single-block loop.
6962 This is the only situation when we can't update liveness when calling
6963 compute_live for the first insn of the loop. */
6964 if (current_loop_nest)
6966 int header = (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6970 if (current_nr_blocks == header + 1)
6971 update_liveness_on_insn
6972 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header))));
6975 /* Set hooks so that no newly generated insn will go out unnoticed. */
6976 sel_register_cfg_hooks ();
6978 /* !!! We call target.sched.init () for the whole region, but we invoke
6979 targetm.sched.finish () for every ebb. */
6980 if (targetm.sched.init)
6981 /* None of the arguments are actually used in any target. */
6982 targetm.sched.init (sched_dump, sched_verbose, -1);
6984 first_emitted_uid = get_max_uid () + 1;
6985 preheader_removed = false;
6987 /* Reset register allocation ticks array. */
6988 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6989 reg_rename_this_tick = 0;
6991 bitmap_initialize (forced_ebb_heads, 0);
6992 bitmap_clear (forced_ebb_heads);
6995 current_copies = BITMAP_ALLOC (NULL);
6996 current_originators = BITMAP_ALLOC (NULL);
6997 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
7002 /* Simplify insns after the scheduling. */
7004 simplify_changed_insns (void)
7008 for (i = 0; i < current_nr_blocks; i++)
7010 basic_block bb = BASIC_BLOCK (BB_TO_BLOCK (i));
7013 FOR_BB_INSNS (bb, insn)
7016 expr_t expr = INSN_EXPR (insn);
7018 if (EXPR_WAS_SUBSTITUTED (expr))
7019 validate_simplify_insn (insn);
7024 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
7025 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
7026 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
7028 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
7031 basic_block bb1 = bb;
7032 if (sched_verbose >= 2)
7033 sel_print ("Finishing schedule in bbs: ");
7037 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
7039 if (sched_verbose >= 2)
7040 sel_print ("%d; ", bb1->index);
7042 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
7044 if (sched_verbose >= 2)
7047 get_ebb_head_tail (bb, bb1, &head, &tail);
7049 current_sched_info->head = head;
7050 current_sched_info->tail = tail;
7051 current_sched_info->prev_head = PREV_INSN (head);
7052 current_sched_info->next_tail = NEXT_INSN (tail);
7055 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
7057 reset_sched_cycles_in_current_ebb (void)
7060 int haifa_last_clock = -1;
7061 int haifa_clock = 0;
7062 int issued_insns = 0;
7065 if (targetm.sched.init)
7067 /* None of the arguments are actually used in any target.
7068 NB: We should have md_reset () hook for cases like this. */
7069 targetm.sched.init (sched_dump, sched_verbose, -1);
7072 state_reset (curr_state);
7073 advance_state (curr_state);
7075 for (insn = current_sched_info->head;
7076 insn != current_sched_info->next_tail;
7077 insn = NEXT_INSN (insn))
7079 int cost, haifa_cost;
7081 bool asm_p, real_insn, after_stall, all_issued;
7088 real_insn = recog_memoized (insn) >= 0;
7089 clock = INSN_SCHED_CYCLE (insn);
7091 cost = clock - last_clock;
7093 /* Initialize HAIFA_COST. */
7096 asm_p = INSN_ASM_P (insn);
7099 /* This is asm insn which *had* to be scheduled first
7103 /* This is a use/clobber insn. It should not change
7108 haifa_cost = estimate_insn_cost (insn, curr_state);
7110 /* Stall for whatever cycles we've stalled before. */
7112 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
7117 all_issued = issued_insns == issue_rate;
7118 if (haifa_cost == 0 && all_issued)
7124 while (haifa_cost--)
7126 advance_state (curr_state);
7130 if (sched_verbose >= 2)
7132 sel_print ("advance_state (state_transition)\n");
7133 debug_state (curr_state);
7136 /* The DFA may report that e.g. insn requires 2 cycles to be
7137 issued, but on the next cycle it says that insn is ready
7138 to go. Check this here. */
7142 && estimate_insn_cost (insn, curr_state) == 0)
7145 /* When the data dependency stall is longer than the DFA stall,
7146 and when we have issued exactly issue_rate insns and stalled,
7147 it could be that after this longer stall the insn will again
7148 become unavailable to the DFA restrictions. Looks strange
7149 but happens e.g. on x86-64. So recheck DFA on the last
7151 if ((after_stall || all_issued)
7154 haifa_cost = estimate_insn_cost (insn, curr_state);
7158 if (sched_verbose >= 2)
7159 sel_print ("haifa clock: %d\n", haifa_clock);
7162 gcc_assert (haifa_cost == 0);
7164 if (sched_verbose >= 2)
7165 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
7167 if (targetm.sched.dfa_new_cycle)
7168 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
7169 haifa_last_clock, haifa_clock,
7172 advance_state (curr_state);
7175 if (sched_verbose >= 2)
7177 sel_print ("advance_state (dfa_new_cycle)\n");
7178 debug_state (curr_state);
7179 sel_print ("haifa clock: %d\n", haifa_clock + 1);
7185 cost = state_transition (curr_state, insn);
7188 if (sched_verbose >= 2)
7190 sel_print ("scheduled insn %d, clock %d\n", INSN_UID (insn),
7192 debug_state (curr_state);
7194 gcc_assert (cost < 0);
7197 if (targetm.sched.variable_issue)
7198 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
7200 INSN_SCHED_CYCLE (insn) = haifa_clock;
7203 haifa_last_clock = haifa_clock;
7207 /* Put TImode markers on insns starting a new issue group. */
7211 int last_clock = -1;
7214 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
7215 insn = NEXT_INSN (insn))
7222 clock = INSN_SCHED_CYCLE (insn);
7223 cost = (last_clock == -1) ? 1 : clock - last_clock;
7225 gcc_assert (cost >= 0);
7228 && GET_CODE (PATTERN (insn)) != USE
7229 && GET_CODE (PATTERN (insn)) != CLOBBER)
7231 if (reload_completed && cost > 0)
7232 PUT_MODE (insn, TImode);
7237 if (sched_verbose >= 2)
7238 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
7242 /* Perform MD_FINISH on EBBs comprising current region. When
7243 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7244 to produce correct sched cycles on insns. */
7246 sel_region_target_finish (bool reset_sched_cycles_p)
7249 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
7251 for (i = 0; i < current_nr_blocks; i++)
7253 if (bitmap_bit_p (scheduled_blocks, i))
7256 /* While pipelining outer loops, skip bundling for loop
7257 preheaders. Those will be rescheduled in the outer loop. */
7258 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
7261 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
7263 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
7266 if (reset_sched_cycles_p)
7267 reset_sched_cycles_in_current_ebb ();
7269 if (targetm.sched.init)
7270 targetm.sched.init (sched_dump, sched_verbose, -1);
7274 if (targetm.sched.finish)
7276 targetm.sched.finish (sched_dump, sched_verbose);
7278 /* Extend luids so that insns generated by the target will
7280 sched_init_luids (NULL, NULL, NULL, NULL);
7284 BITMAP_FREE (scheduled_blocks);
7287 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7288 is true, make an additional pass emulating scheduler to get correct insn
7289 cycles for md_finish calls. */
7291 sel_region_finish (bool reset_sched_cycles_p)
7293 simplify_changed_insns ();
7294 sched_finish_ready_list ();
7297 /* Free the vectors. */
7299 VEC_free (expr_t, heap, vec_av_set);
7300 BITMAP_FREE (current_copies);
7301 BITMAP_FREE (current_originators);
7302 BITMAP_FREE (code_motion_visited_blocks);
7303 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns);
7304 vinsn_vec_free (&vec_target_unavailable_vinsns);
7306 /* If LV_SET of the region head should be updated, do it now because
7307 there will be no other chance. */
7312 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
7313 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
7315 basic_block bb = BLOCK_FOR_INSN (insn);
7317 if (!BB_LV_SET_VALID_P (bb))
7318 compute_live (insn);
7322 /* Emulate the Haifa scheduler for bundling. */
7323 if (reload_completed)
7324 sel_region_target_finish (reset_sched_cycles_p);
7326 sel_finish_global_and_expr ();
7328 bitmap_clear (forced_ebb_heads);
7332 finish_deps_global ();
7333 sched_finish_luids ();
7336 BITMAP_FREE (blocks_to_reschedule);
7338 sel_unregister_cfg_hooks ();
7344 /* Functions that implement the scheduler driver. */
7346 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7347 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7348 of insns scheduled -- these would be postprocessed later. */
7350 schedule_on_fences (flist_t fences, int max_seqno,
7351 ilist_t **scheduled_insns_tailpp)
7353 flist_t old_fences = fences;
7355 if (sched_verbose >= 1)
7357 sel_print ("\nScheduling on fences: ");
7358 dump_flist (fences);
7362 scheduled_something_on_previous_fence = false;
7363 for (; fences; fences = FLIST_NEXT (fences))
7365 fence_t fence = NULL;
7368 bool first_p = true;
7370 /* Choose the next fence group to schedule.
7371 The fact that insn can be scheduled only once
7372 on the cycle is guaranteed by two properties:
7373 1. seqnos of parallel groups decrease with each iteration.
7374 2. If is_ineligible_successor () sees the larger seqno, it
7375 checks if candidate insn is_in_current_fence_p (). */
7376 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7378 fence_t f = FLIST_FENCE (fences2);
7380 if (!FENCE_PROCESSED_P (f))
7382 int i = INSN_SEQNO (FENCE_INSN (f));
7384 if (first_p || i > seqno)
7391 /* ??? Seqnos of different groups should be different. */
7392 gcc_assert (1 || i != seqno);
7398 /* As FENCE is nonnull, SEQNO is initialized. */
7399 seqno -= max_seqno + 1;
7400 fill_insns (fence, seqno, scheduled_insns_tailpp);
7401 FENCE_PROCESSED_P (fence) = true;
7404 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7405 don't need to keep bookkeeping-invalidated and target-unavailable
7407 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7408 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7411 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7413 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7415 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7417 /* The first element is already processed. */
7418 while ((fences = FLIST_NEXT (fences)))
7420 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7422 if (*min_seqno > seqno)
7424 else if (*max_seqno < seqno)
7429 /* Calculate new fences from FENCES. */
7431 calculate_new_fences (flist_t fences, int orig_max_seqno)
7433 flist_t old_fences = fences;
7434 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7436 flist_tail_init (new_fences);
7437 for (; fences; fences = FLIST_NEXT (fences))
7439 fence_t fence = FLIST_FENCE (fences);
7442 if (!FENCE_BNDS (fence))
7444 /* This fence doesn't have any successors. */
7445 if (!FENCE_SCHEDULED_P (fence))
7447 /* Nothing was scheduled on this fence. */
7450 insn = FENCE_INSN (fence);
7451 seqno = INSN_SEQNO (insn);
7452 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7454 if (sched_verbose >= 1)
7455 sel_print ("Fence %d[%d] has not changed\n",
7458 move_fence_to_fences (fences, new_fences);
7462 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7465 flist_clear (&old_fences);
7466 return FLIST_TAIL_HEAD (new_fences);
7469 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7470 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7471 the highest seqno used in a region. Return the updated highest seqno. */
7473 update_seqnos_and_stage (int min_seqno, int max_seqno,
7474 int highest_seqno_in_use,
7475 ilist_t *pscheduled_insns)
7481 /* Actually, new_hs is the seqno of the instruction, that was
7482 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7483 if (*pscheduled_insns)
7485 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7486 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7487 gcc_assert (new_hs > highest_seqno_in_use);
7490 new_hs = highest_seqno_in_use;
7492 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7494 gcc_assert (INSN_SEQNO (insn) < 0);
7495 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7496 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7498 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7499 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7500 require > 1GB of memory e.g. on limit-fnargs.c. */
7502 free_data_for_scheduled_insn (insn);
7505 ilist_clear (pscheduled_insns);
7511 /* The main driver for scheduling a region. This function is responsible
7512 for correct propagation of fences (i.e. scheduling points) and creating
7513 a group of parallel insns at each of them. It also supports
7514 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7517 sel_sched_region_2 (int orig_max_seqno)
7519 int highest_seqno_in_use = orig_max_seqno;
7521 stat_bookkeeping_copies = 0;
7522 stat_insns_needed_bookkeeping = 0;
7523 stat_renamed_scheduled = 0;
7524 stat_substitutions_total = 0;
7525 num_insns_scheduled = 0;
7529 int min_seqno, max_seqno;
7530 ilist_t scheduled_insns = NULL;
7531 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7533 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7534 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7535 fences = calculate_new_fences (fences, orig_max_seqno);
7536 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7537 highest_seqno_in_use,
7541 if (sched_verbose >= 1)
7542 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7543 "bookkeeping, %d insns renamed, %d insns substituted\n",
7544 stat_bookkeeping_copies,
7545 stat_insns_needed_bookkeeping,
7546 stat_renamed_scheduled,
7547 stat_substitutions_total);
7550 /* Schedule a region. When pipelining, search for possibly never scheduled
7551 bookkeeping code and schedule it. Reschedule pipelined code without
7552 pipelining after. */
7554 sel_sched_region_1 (void)
7556 int number_of_insns;
7559 /* Remove empty blocks that might be in the region from the beginning.
7560 We need to do save sched_max_luid before that, as it actually shows
7561 the number of insns in the region, and purge_empty_blocks can
7563 number_of_insns = sched_max_luid - 1;
7564 purge_empty_blocks ();
7566 orig_max_seqno = init_seqno (number_of_insns, NULL, NULL);
7567 gcc_assert (orig_max_seqno >= 1);
7569 /* When pipelining outer loops, create fences on the loop header,
7572 if (current_loop_nest)
7573 init_fences (BB_END (EBB_FIRST_BB (0)));
7575 init_fences (bb_note (EBB_FIRST_BB (0)));
7578 sel_sched_region_2 (orig_max_seqno);
7580 gcc_assert (fences == NULL);
7586 struct flist_tail_def _new_fences;
7587 flist_tail_t new_fences = &_new_fences;
7590 pipelining_p = false;
7591 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7592 bookkeeping_p = false;
7593 enable_schedule_as_rhs_p = false;
7595 /* Schedule newly created code, that has not been scheduled yet. */
7602 for (i = 0; i < current_nr_blocks; i++)
7604 basic_block bb = EBB_FIRST_BB (i);
7606 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7608 if (! bb_ends_ebb_p (bb))
7609 bitmap_set_bit (blocks_to_reschedule, bb_next_bb (bb)->index);
7610 if (sel_bb_empty_p (bb))
7612 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7615 clear_outdated_rtx_info (bb);
7616 if (sel_insn_is_speculation_check (BB_END (bb))
7617 && JUMP_P (BB_END (bb)))
7618 bitmap_set_bit (blocks_to_reschedule,
7619 BRANCH_EDGE (bb)->dest->index);
7621 else if (! sel_bb_empty_p (bb)
7622 && INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7623 bitmap_set_bit (blocks_to_reschedule, bb->index);
7626 for (i = 0; i < current_nr_blocks; i++)
7628 bb = EBB_FIRST_BB (i);
7630 /* While pipelining outer loops, skip bundling for loop
7631 preheaders. Those will be rescheduled in the outer
7633 if (sel_is_loop_preheader_p (bb))
7635 clear_outdated_rtx_info (bb);
7639 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7641 flist_tail_init (new_fences);
7643 orig_max_seqno = init_seqno (0, blocks_to_reschedule, bb);
7645 /* Mark BB as head of the new ebb. */
7646 bitmap_set_bit (forced_ebb_heads, bb->index);
7648 gcc_assert (fences == NULL);
7650 init_fences (bb_note (bb));
7652 sel_sched_region_2 (orig_max_seqno);
7662 /* Schedule the RGN region. */
7664 sel_sched_region (int rgn)
7667 bool reset_sched_cycles_p;
7669 if (sel_region_init (rgn))
7672 if (sched_verbose >= 1)
7673 sel_print ("Scheduling region %d\n", rgn);
7675 schedule_p = (!sched_is_disabled_for_current_region_p ()
7676 && dbg_cnt (sel_sched_region_cnt));
7677 reset_sched_cycles_p = pipelining_p;
7679 sel_sched_region_1 ();
7681 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7682 reset_sched_cycles_p = true;
7684 sel_region_finish (reset_sched_cycles_p);
7687 /* Perform global init for the scheduler. */
7689 sel_global_init (void)
7691 calculate_dominance_info (CDI_DOMINATORS);
7692 alloc_sched_pools ();
7694 /* Setup the infos for sched_init. */
7695 sel_setup_sched_infos ();
7696 setup_sched_dump ();
7698 sched_rgn_init (false);
7702 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7704 can_issue_more = issue_rate;
7706 sched_extend_target ();
7707 sched_deps_init (true);
7708 setup_nop_and_exit_insns ();
7709 sel_extend_global_bb_info ();
7711 init_hard_regs_data ();
7714 /* Free the global data of the scheduler. */
7716 sel_global_finish (void)
7718 free_bb_note_pool ();
7720 sel_finish_global_bb_info ();
7722 free_regset_pool ();
7723 free_nop_and_exit_insns ();
7725 sched_rgn_finish ();
7726 sched_deps_finish ();
7730 sel_finish_pipelining ();
7732 free_sched_pools ();
7733 free_dominance_info (CDI_DOMINATORS);
7736 /* Return true when we need to skip selective scheduling. Used for debugging. */
7738 maybe_skip_selective_scheduling (void)
7740 return ! dbg_cnt (sel_sched_cnt);
7743 /* The entry point. */
7745 run_selective_scheduling (void)
7749 if (n_basic_blocks == NUM_FIXED_BLOCKS)
7754 for (rgn = 0; rgn < nr_regions; rgn++)
7755 sel_sched_region (rgn);
7757 sel_global_finish ();