1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
40 #include "tree-pass.h"
41 #include "sched-int.h"
45 #include "langhooks.h"
46 #include "rtlhooks-def.h"
49 #ifdef INSN_SCHEDULING
50 #include "sel-sched-ir.h"
51 #include "sel-sched-dump.h"
52 #include "sel-sched.h"
55 /* Implementation of selective scheduling approach.
56 The below implementation follows the original approach with the following
59 o the scheduler works after register allocation (but can be also tuned
61 o some instructions are not copied or register renamed;
62 o conditional jumps are not moved with code duplication;
63 o several jumps in one parallel group are not supported;
64 o when pipelining outer loops, code motion through inner loops
66 o control and data speculation are supported;
67 o some improvements for better compile time/performance were made.
72 A vinsn, or virtual insn, is an insn with additional data characterizing
73 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
74 Vinsns also act as smart pointers to save memory by reusing them in
75 different expressions. A vinsn is described by vinsn_t type.
77 An expression is a vinsn with additional data characterizing its properties
78 at some point in the control flow graph. The data may be its usefulness,
79 priority, speculative status, whether it was renamed/subsituted, etc.
80 An expression is described by expr_t type.
82 Availability set (av_set) is a set of expressions at a given control flow
83 point. It is represented as av_set_t. The expressions in av sets are kept
84 sorted in the terms of expr_greater_p function. It allows to truncate
85 the set while leaving the best expressions.
87 A fence is a point through which code motion is prohibited. On each step,
88 we gather a parallel group of insns at a fence. It is possible to have
89 multiple fences. A fence is represented via fence_t.
91 A boundary is the border between the fence group and the rest of the code.
92 Currently, we never have more than one boundary per fence, as we finalize
93 the fence group when a jump is scheduled. A boundary is represented
99 The scheduler finds regions to schedule, schedules each one, and finalizes.
100 The regions are formed starting from innermost loops, so that when the inner
101 loop is pipelined, its prologue can be scheduled together with yet unprocessed
102 outer loop. The rest of acyclic regions are found using extend_rgns:
103 the blocks that are not yet allocated to any regions are traversed in top-down
104 order, and a block is added to a region to which all its predecessors belong;
105 otherwise, the block starts its own region.
107 The main scheduling loop (sel_sched_region_2) consists of just
108 scheduling on each fence and updating fences. For each fence,
109 we fill a parallel group of insns (fill_insns) until some insns can be added.
110 First, we compute available exprs (av-set) at the boundary of the current
111 group. Second, we choose the best expression from it. If the stall is
112 required to schedule any of the expressions, we advance the current cycle
113 appropriately. So, the final group does not exactly correspond to a VLIW
114 word. Third, we move the chosen expression to the boundary (move_op)
115 and update the intermediate av sets and liveness sets. We quit fill_insns
116 when either no insns left for scheduling or we have scheduled enough insns
117 so we feel like advancing a scheduling point.
119 Computing available expressions
120 ===============================
122 The computation (compute_av_set) is a bottom-up traversal. At each insn,
123 we're moving the union of its successors' sets through it via
124 moveup_expr_set. The dependent expressions are removed. Local
125 transformations (substitution, speculation) are applied to move more
126 exprs. Then the expr corresponding to the current insn is added.
127 The result is saved on each basic block header.
129 When traversing the CFG, we're moving down for no more than max_ws insns.
130 Also, we do not move down to ineligible successors (is_ineligible_successor),
131 which include moving along a back-edge, moving to already scheduled code,
132 and moving to another fence. The first two restrictions are lifted during
133 pipelining, which allows us to move insns along a back-edge. We always have
134 an acyclic region for scheduling because we forbid motion through fences.
136 Choosing the best expression
137 ============================
139 We sort the final availability set via sel_rank_for_schedule, then we remove
140 expressions which are not yet ready (tick_check_p) or which dest registers
141 cannot be used. For some of them, we choose another register via
142 find_best_reg. To do this, we run find_used_regs to calculate the set of
143 registers which cannot be used. The find_used_regs function performs
144 a traversal of code motion paths for an expr. We consider for renaming
145 only registers which are from the same regclass as the original one and
146 using which does not interfere with any live ranges. Finally, we convert
147 the resulting set to the ready list format and use max_issue and reorder*
148 hooks similarly to the Haifa scheduler.
150 Scheduling the best expression
151 ==============================
153 We run the move_op routine to perform the same type of code motion paths
154 traversal as in find_used_regs. (These are working via the same driver,
155 code_motion_path_driver.) When moving down the CFG, we look for original
156 instruction that gave birth to a chosen expression. We undo
157 the transformations performed on an expression via the history saved in it.
158 When found, we remove the instruction or leave a reg-reg copy/speculation
159 check if needed. On a way up, we insert bookkeeping copies at each join
160 point. If a copy is not needed, it will be removed later during this
161 traversal. We update the saved av sets and liveness sets on the way up, too.
163 Finalizing the schedule
164 =======================
166 When pipelining, we reschedule the blocks from which insns were pipelined
167 to get a tighter schedule. On Itanium, we also perform bundling via
168 the same routine from ia64.c.
170 Dependence analysis changes
171 ===========================
173 We augmented the sched-deps.c with hooks that get called when a particular
174 dependence is found in a particular part of an insn. Using these hooks, we
175 can do several actions such as: determine whether an insn can be moved through
176 another (has_dependence_p, moveup_expr); find out whether an insn can be
177 scheduled on the current cycle (tick_check_p); find out registers that
178 are set/used/clobbered by an insn and find out all the strange stuff that
179 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
180 init_global_and_expr_for_insn).
182 Initialization changes
183 ======================
185 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
186 reused in all of the schedulers. We have split up the initialization of data
187 of such parts into different functions prefixed with scheduler type and
188 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
189 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
190 The same splitting is done with current_sched_info structure:
191 dependence-related parts are in sched_deps_info, common part is in
192 common_sched_info, and haifa/sel/etc part is in current_sched_info.
197 As we now have multiple-point scheduling, this would not work with backends
198 which save some of the scheduler state to use it in the target hooks.
199 For this purpose, we introduce a concept of target contexts, which
200 encapsulate such information. The backend should implement simple routines
201 of allocating/freeing/setting such a context. The scheduler calls these
202 as target hooks and handles the target context as an opaque pointer (similar
203 to the DFA state type, state_t).
208 As the correct data dependence graph is not supported during scheduling (which
209 is to be changed in mid-term), we cache as much of the dependence analysis
210 results as possible to avoid reanalyzing. This includes: bitmap caches on
211 each insn in stream of the region saying yes/no for a query with a pair of
212 UIDs; hashtables with the previously done transformations on each insn in
213 stream; a vector keeping a history of transformations on each expr.
215 Also, we try to minimize the dependence context used on each fence to check
216 whether the given expression is ready for scheduling by removing from it
217 insns that are definitely completed the execution. The results of
218 tick_check_p checks are also cached in a vector on each fence.
220 We keep a valid liveness set on each insn in a region to avoid the high
221 cost of recomputation on large basic blocks.
223 Finally, we try to minimize the number of needed updates to the availability
224 sets. The updates happen in two cases: when fill_insns terminates,
225 we advance all fences and increase the stage number to show that the region
226 has changed and the sets are to be recomputed; and when the next iteration
227 of a loop in fill_insns happens (but this one reuses the saved av sets
228 on bb headers.) Thus, we try to break the fill_insns loop only when
229 "significant" number of insns from the current scheduling window was
230 scheduled. This should be made a target param.
233 TODO: correctly support the data dependence graph at all stages and get rid
234 of all caches. This should speed up the scheduler.
235 TODO: implement moving cond jumps with bookkeeping copies on both targets.
236 TODO: tune the scheduler before RA so it does not create too much pseudos.
240 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
241 selective scheduling and software pipelining.
242 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
244 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
245 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
246 for GCC. In Proceedings of GCC Developers' Summit 2006.
248 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
249 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
250 http://rogue.colorado.edu/EPIC7/.
254 /* True when pipelining is enabled. */
257 /* True if bookkeeping is enabled. */
260 /* Maximum number of insns that are eligible for renaming. */
261 int max_insns_to_rename;
264 /* Definitions of local types and macros. */
266 /* Represents possible outcomes of moving an expression through an insn. */
267 enum MOVEUP_EXPR_CODE
269 /* The expression is not changed. */
272 /* Not changed, but requires a new destination register. */
275 /* Cannot be moved. */
278 /* Changed (substituted or speculated). */
282 /* The container to be passed into rtx search & replace functions. */
283 struct rtx_search_arg
285 /* What we are searching for. */
288 /* The occurence counter. */
292 typedef struct rtx_search_arg *rtx_search_arg_p;
294 /* This struct contains precomputed hard reg sets that are needed when
295 computing registers available for renaming. */
296 struct hard_regs_data
298 /* For every mode, this stores registers available for use with
300 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
302 /* True when regs_for_mode[mode] is initialized. */
303 bool regs_for_mode_ok[NUM_MACHINE_MODES];
305 /* For every register, it has regs that are ok to rename into it.
306 The register in question is always set. If not, this means
307 that the whole set is not computed yet. */
308 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
310 /* For every mode, this stores registers not available due to
312 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
314 /* All registers that are used or call used. */
315 HARD_REG_SET regs_ever_used;
318 /* Stack registers. */
319 HARD_REG_SET stack_regs;
323 /* Holds the results of computation of available for renaming and
324 unavailable hard registers. */
327 /* These are unavailable due to calls crossing, globalness, etc. */
328 HARD_REG_SET unavailable_hard_regs;
330 /* These are *available* for renaming. */
331 HARD_REG_SET available_for_renaming;
333 /* Whether this code motion path crosses a call. */
337 /* A global structure that contains the needed information about harg
339 static struct hard_regs_data sel_hrd;
342 /* This structure holds local data used in code_motion_path_driver hooks on
343 the same or adjacent levels of recursion. Here we keep those parameters
344 that are not used in code_motion_path_driver routine itself, but only in
345 its hooks. Moreover, all parameters that can be modified in hooks are
346 in this structure, so all other parameters passed explicitly to hooks are
348 struct cmpd_local_params
350 /* Local params used in move_op_* functions. */
352 /* Edges for bookkeeping generation. */
355 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
356 expr_t c_expr_merged, c_expr_local;
358 /* Local params used in fur_* functions. */
359 /* Copy of the ORIGINAL_INSN list, stores the original insns already
360 found before entering the current level of code_motion_path_driver. */
361 def_list_t old_original_insns;
363 /* Local params used in move_op_* functions. */
364 /* True when we have removed last insn in the block which was
365 also a boundary. Do not update anything or create bookkeeping copies. */
366 BOOL_BITFIELD removed_last_insn : 1;
369 /* Stores the static parameters for move_op_* calls. */
370 struct moveop_static_params
372 /* Destination register. */
375 /* Current C_EXPR. */
378 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
379 they are to be removed. */
382 #ifdef ENABLE_CHECKING
383 /* This is initialized to the insn on which the driver stopped its traversal. */
387 /* True if we scheduled an insn with different register. */
391 /* Stores the static parameters for fur_* calls. */
392 struct fur_static_params
394 /* Set of registers unavailable on the code motion path. */
397 /* Pointer to the list of original insns definitions. */
398 def_list_t *original_insns;
400 /* True if a code motion path contains a CALL insn. */
404 typedef struct fur_static_params *fur_static_params_p;
405 typedef struct cmpd_local_params *cmpd_local_params_p;
406 typedef struct moveop_static_params *moveop_static_params_p;
408 /* Set of hooks and parameters that determine behaviour specific to
409 move_op or find_used_regs functions. */
410 struct code_motion_path_driver_info_def
412 /* Called on enter to the basic block. */
413 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
415 /* Called when original expr is found. */
416 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
418 /* Called while descending current basic block if current insn is not
419 the original EXPR we're searching for. */
420 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
422 /* Function to merge C_EXPRes from different successors. */
423 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
425 /* Function to finalize merge from different successors and possibly
426 deallocate temporary data structures used for merging. */
427 void (*after_merge_succs) (cmpd_local_params_p, void *);
429 /* Called on the backward stage of recursion to do moveup_expr.
430 Used only with move_op_*. */
431 void (*ascend) (insn_t, void *);
433 /* Called on the ascending pass, before returning from the current basic
434 block or from the whole traversal. */
435 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
437 /* When processing successors in move_op we need only descend into
438 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
441 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
442 const char *routine_name;
445 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
447 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
449 /* Set of hooks for performing move_op and find_used_regs routines with
450 code_motion_path_driver. */
451 extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
453 /* True if/when we want to emulate Haifa scheduler in the common code.
454 This is used in sched_rgn_local_init and in various places in
456 int sched_emulate_haifa_p;
458 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
459 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
460 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
461 scheduling window. */
464 /* Current fences. */
467 /* True when separable insns should be scheduled as RHSes. */
468 static bool enable_schedule_as_rhs_p;
470 /* Used in verify_target_availability to assert that target reg is reported
471 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
472 we haven't scheduled anything on the previous fence.
473 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
474 have more conservative value than the one returned by the
475 find_used_regs, thus we shouldn't assert that these values are equal. */
476 static bool scheduled_something_on_previous_fence;
478 /* All newly emitted insns will have their uids greater than this value. */
479 static int first_emitted_uid;
481 /* Set of basic blocks that are forced to start new ebbs. This is a subset
482 of all the ebb heads. */
483 static bitmap_head _forced_ebb_heads;
484 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
486 /* Blocks that need to be rescheduled after pipelining. */
487 bitmap blocks_to_reschedule = NULL;
489 /* True when the first lv set should be ignored when updating liveness. */
490 static bool ignore_first = false;
492 /* Number of insns max_issue has initialized data structures for. */
493 static int max_issue_size = 0;
495 /* Whether we can issue more instructions. */
496 static int can_issue_more;
498 /* Maximum software lookahead window size, reduced when rescheduling after
502 /* Number of insns scheduled in current region. */
503 static int num_insns_scheduled;
505 /* A vector of expressions is used to be able to sort them. */
507 DEF_VEC_ALLOC_P(expr_t,heap);
508 static VEC(expr_t, heap) *vec_av_set = NULL;
510 /* A vector of vinsns is used to hold temporary lists of vinsns. */
512 DEF_VEC_ALLOC_P(vinsn_t,heap);
513 typedef VEC(vinsn_t, heap) *vinsn_vec_t;
515 /* This vector has the exprs which may still present in av_sets, but actually
516 can't be moved up due to bookkeeping created during code motion to another
517 fence. See comment near the call to update_and_record_unavailable_insns
518 for the detailed explanations. */
519 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = NULL;
521 /* This vector has vinsns which are scheduled with renaming on the first fence
522 and then seen on the second. For expressions with such vinsns, target
523 availability information may be wrong. */
524 static vinsn_vec_t vec_target_unavailable_vinsns = NULL;
526 /* Vector to store temporary nops inserted in move_op to prevent removal
529 DEF_VEC_ALLOC_P(insn_t,heap);
530 static VEC(insn_t, heap) *vec_temp_moveop_nops = NULL;
532 /* These bitmaps record original instructions scheduled on the current
533 iteration and bookkeeping copies created by them. */
534 static bitmap current_originators = NULL;
535 static bitmap current_copies = NULL;
537 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
538 visit them afterwards. */
539 static bitmap code_motion_visited_blocks = NULL;
541 /* Variables to accumulate different statistics. */
543 /* The number of bookkeeping copies created. */
544 static int stat_bookkeeping_copies;
546 /* The number of insns that required bookkeeiping for their scheduling. */
547 static int stat_insns_needed_bookkeeping;
549 /* The number of insns that got renamed. */
550 static int stat_renamed_scheduled;
552 /* The number of substitutions made during scheduling. */
553 static int stat_substitutions_total;
556 /* Forward declarations of static functions. */
557 static bool rtx_ok_for_substitution_p (rtx, rtx);
558 static int sel_rank_for_schedule (const void *, const void *);
559 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
560 static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax);
562 static rtx get_dest_from_orig_ops (av_set_t);
563 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
564 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
566 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
567 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
568 cmpd_local_params_p, void *);
569 static void sel_sched_region_1 (void);
570 static void sel_sched_region_2 (int);
571 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
573 static void debug_state (state_t);
576 /* Functions that work with fences. */
578 /* Advance one cycle on FENCE. */
580 advance_one_cycle (fence_t fence)
586 advance_state (FENCE_STATE (fence));
587 cycle = ++FENCE_CYCLE (fence);
588 FENCE_ISSUED_INSNS (fence) = 0;
589 FENCE_STARTS_CYCLE_P (fence) = 1;
590 can_issue_more = issue_rate;
591 FENCE_ISSUE_MORE (fence) = can_issue_more;
593 for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); )
595 if (INSN_READY_CYCLE (insn) < cycle)
597 remove_from_deps (FENCE_DC (fence), insn);
598 VEC_unordered_remove (rtx, FENCE_EXECUTING_INSNS (fence), i);
603 if (sched_verbose >= 2)
605 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
606 debug_state (FENCE_STATE (fence));
610 /* Returns true when SUCC in a fallthru bb of INSN, possibly
611 skipping empty basic blocks. */
613 in_fallthru_bb_p (rtx insn, rtx succ)
615 basic_block bb = BLOCK_FOR_INSN (insn);
617 if (bb == BLOCK_FOR_INSN (succ))
620 if (find_fallthru_edge (bb))
621 bb = find_fallthru_edge (bb)->dest;
625 while (sel_bb_empty_p (bb))
628 return bb == BLOCK_FOR_INSN (succ);
631 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
632 When a successor will continue a ebb, transfer all parameters of a fence
633 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
634 of scheduling helping to distinguish between the old and the new code. */
636 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
639 bool was_here_p = false;
640 insn_t insn = NULL_RTX;
644 fence_t fence = FLIST_FENCE (old_fences);
647 /* Get the only element of FENCE_BNDS (fence). */
648 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
650 gcc_assert (!was_here_p);
653 gcc_assert (was_here_p && insn != NULL_RTX);
655 /* When in the "middle" of the block, just move this fence
657 bb = BLOCK_FOR_INSN (insn);
658 if (! sel_bb_end_p (insn)
659 || (single_succ_p (bb)
660 && single_pred_p (single_succ (bb))))
664 succ = (sel_bb_end_p (insn)
665 ? sel_bb_head (single_succ (bb))
668 if (INSN_SEQNO (succ) > 0
669 && INSN_SEQNO (succ) <= orig_max_seqno
670 && INSN_SCHED_TIMES (succ) <= 0)
672 FENCE_INSN (fence) = succ;
673 move_fence_to_fences (old_fences, new_fences);
675 if (sched_verbose >= 1)
676 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
677 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
682 /* Otherwise copy fence's structures to (possibly) multiple successors. */
683 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
685 int seqno = INSN_SEQNO (succ);
687 if (0 < seqno && seqno <= orig_max_seqno
688 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
690 bool b = (in_same_ebb_p (insn, succ)
691 || in_fallthru_bb_p (insn, succ));
693 if (sched_verbose >= 1)
694 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
695 INSN_UID (insn), INSN_UID (succ),
696 BLOCK_NUM (succ), b ? "continue" : "reset");
699 add_dirty_fence_to_fences (new_fences, succ, fence);
702 /* Mark block of the SUCC as head of the new ebb. */
703 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
704 add_clean_fence_to_fences (new_fences, succ, fence);
711 /* Functions to support substitution. */
713 /* Returns whether INSN with dependence status DS is eligible for
714 substitution, i.e. it's a copy operation x := y, and RHS that is
715 moved up through this insn should be substituted. */
717 can_substitute_through_p (insn_t insn, ds_t ds)
719 /* We can substitute only true dependencies. */
720 if ((ds & DEP_OUTPUT)
723 || ! INSN_LHS (insn))
726 /* Now we just need to make sure the INSN_RHS consists of only one
728 if (REG_P (INSN_LHS (insn))
729 && REG_P (INSN_RHS (insn)))
734 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
735 source (if INSN is eligible for substitution). Returns TRUE if
736 substitution was actually performed, FALSE otherwise. Substitution might
737 be not performed because it's either EXPR' vinsn doesn't contain INSN's
738 destination or the resulting insn is invalid for the target machine.
739 When UNDO is true, perform unsubstitution instead (the difference is in
740 the part of rtx on which validate_replace_rtx is called). */
742 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
746 vinsn_t *vi = &EXPR_VINSN (expr);
747 bool has_rhs = VINSN_RHS (*vi) != NULL;
750 /* Do not try to replace in SET_DEST. Although we'll choose new
751 register for the RHS, we don't want to change RHS' original reg.
752 If the insn is not SET, we may still be able to substitute something
753 in it, and if we're here (don't have deps), it doesn't write INSN's
757 : &PATTERN (VINSN_INSN_RTX (*vi)));
758 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
760 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
761 if (rtx_ok_for_substitution_p (old, *where))
766 /* We should copy these rtxes before substitution. */
767 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
768 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
770 /* Where we'll replace.
771 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
772 used instead of SET_SRC. */
773 where_replace = (has_rhs
774 ? &SET_SRC (PATTERN (new_insn))
775 : &PATTERN (new_insn));
778 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
781 /* ??? Actually, constrain_operands result depends upon choice of
782 destination register. E.g. if we allow single register to be an rhs,
783 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
784 in invalid insn dx=dx, so we'll loose this rhs here.
785 Just can't come up with significant testcase for this, so just
786 leaving it for now. */
789 change_vinsn_in_expr (expr,
790 create_vinsn_from_insn_rtx (new_insn, false));
792 /* Do not allow clobbering the address register of speculative
794 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
795 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr)),
796 expr_dest_regno (expr)))
797 EXPR_TARGET_AVAILABLE (expr) = false;
808 /* Helper function for count_occurences_equiv. */
810 count_occurrences_1 (rtx *cur_rtx, void *arg)
812 rtx_search_arg_p p = (rtx_search_arg_p) arg;
814 /* The last param FOR_GCSE is true, because otherwise it performs excessive
818 for the last insn it presumes r33 equivalent to r8, so it changes it to
819 r33. Actually, there's no change, but it spoils debugging. */
820 if (exp_equiv_p (*cur_rtx, p->x, 0, true))
822 /* Bail out if we occupy more than one register. */
824 && HARD_REGISTER_P (*cur_rtx)
825 && hard_regno_nregs[REGNO(*cur_rtx)][GET_MODE (*cur_rtx)] > 1)
833 /* Do not traverse subexprs. */
837 if (GET_CODE (*cur_rtx) == SUBREG
839 && REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x))
841 /* ??? Do not support substituting regs inside subregs. In that case,
842 simplify_subreg will be called by validate_replace_rtx, and
843 unsubstitution will fail later. */
848 /* Continue search. */
852 /* Return the number of places WHAT appears within WHERE.
853 Bail out when we found a reference occupying several hard registers. */
855 count_occurrences_equiv (rtx what, rtx where)
857 struct rtx_search_arg arg;
862 for_each_rtx (&where, &count_occurrences_1, (void *) &arg);
867 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
869 rtx_ok_for_substitution_p (rtx what, rtx where)
871 return (count_occurrences_equiv (what, where) > 0);
875 /* Functions to support register renaming. */
877 /* Substitute VI's set source with REGNO. Returns newly created pattern
878 that has REGNO as its source. */
880 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
886 lhs_rtx = copy_rtx (VINSN_LHS (vi));
888 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
889 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
894 /* Returns whether INSN's src can be replaced with register number
895 NEW_SRC_REG. E.g. the following insn is valid for i386:
897 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
898 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
899 (reg:SI 0 ax [orig:770 c1 ] [770]))
900 (const_int 288 [0x120])) [0 str S1 A8])
901 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
904 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
905 because of operand constraints:
907 (define_insn "*movqi_1"
908 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
909 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
912 So do constrain_operands here, before choosing NEW_SRC_REG as best
916 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
918 vinsn_t vi = INSN_VINSN (insn);
919 enum machine_mode mode;
923 gcc_assert (VINSN_SEPARABLE_P (vi));
925 get_dest_and_mode (insn, &dst_loc, &mode);
926 gcc_assert (mode == GET_MODE (new_src_reg));
928 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
931 /* See whether SET_SRC can be replaced with this register. */
932 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
933 res = verify_changes (0);
939 /* Returns whether INSN still be valid after replacing it's DEST with
942 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
944 vinsn_t vi = INSN_VINSN (insn);
947 /* We should deal here only with separable insns. */
948 gcc_assert (VINSN_SEPARABLE_P (vi));
949 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
951 /* See whether SET_DEST can be replaced with this register. */
952 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
953 res = verify_changes (0);
959 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
961 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
967 rhs_rtx = copy_rtx (VINSN_RHS (vi));
969 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
970 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
975 /* Substitute lhs in the given expression EXPR for the register with number
976 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
978 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
983 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
984 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
986 change_vinsn_in_expr (expr, vinsn);
987 EXPR_WAS_RENAMED (expr) = 1;
988 EXPR_TARGET_AVAILABLE (expr) = 1;
991 /* Returns whether VI writes either one of the USED_REGS registers or,
992 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
994 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
995 HARD_REG_SET unavailable_hard_regs)
998 reg_set_iterator rsi;
1000 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
1002 if (REGNO_REG_SET_P (used_regs, regno))
1004 if (HARD_REGISTER_NUM_P (regno)
1005 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1009 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
1011 if (REGNO_REG_SET_P (used_regs, regno))
1013 if (HARD_REGISTER_NUM_P (regno)
1014 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1021 /* Returns register class of the output register in INSN.
1022 Returns NO_REGS for call insns because some targets have constraints on
1023 destination register of a call insn.
1025 Code adopted from regrename.c::build_def_use. */
1026 static enum reg_class
1027 get_reg_class (rtx insn)
1031 extract_insn (insn);
1032 if (! constrain_operands (1))
1033 fatal_insn_not_found (insn);
1034 preprocess_constraints ();
1035 alt = which_alternative;
1036 n_ops = recog_data.n_operands;
1038 for (i = 0; i < n_ops; ++i)
1040 int matches = recog_op_alt[i][alt].matches;
1042 recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;
1045 if (asm_noperands (PATTERN (insn)) > 0)
1047 for (i = 0; i < n_ops; i++)
1048 if (recog_data.operand_type[i] == OP_OUT)
1050 rtx *loc = recog_data.operand_loc[i];
1052 enum reg_class cl = recog_op_alt[i][alt].cl;
1055 && REGNO (op) == ORIGINAL_REGNO (op))
1061 else if (!CALL_P (insn))
1063 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1065 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1066 enum reg_class cl = recog_op_alt[opn][alt].cl;
1068 if (recog_data.operand_type[opn] == OP_OUT ||
1069 recog_data.operand_type[opn] == OP_INOUT)
1075 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1076 may result in returning NO_REGS, cause flags is written implicitly through
1077 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1081 #ifdef HARD_REGNO_RENAME_OK
1082 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1084 init_hard_regno_rename (int regno)
1088 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1090 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1092 /* We are not interested in renaming in other regs. */
1093 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1096 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1097 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1102 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1105 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1107 #ifdef HARD_REGNO_RENAME_OK
1108 /* Check whether this is all calculated. */
1109 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1110 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1112 init_hard_regno_rename (from);
1114 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1120 /* Calculate set of registers that are capable of holding MODE. */
1122 init_regs_for_mode (enum machine_mode mode)
1126 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1127 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1129 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1131 int nregs = hard_regno_nregs[cur_reg][mode];
1134 for (i = nregs - 1; i >= 0; --i)
1135 if (fixed_regs[cur_reg + i]
1136 || global_regs[cur_reg + i]
1137 /* Can't use regs which aren't saved by
1139 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1140 #ifdef LEAF_REGISTERS
1141 /* We can't use a non-leaf register if we're in a
1143 || (current_function_is_leaf
1144 && !LEAF_REGISTERS[cur_reg + i])
1152 /* See whether it accepts all modes that occur in
1154 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1157 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1158 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1161 /* If the CUR_REG passed all the checks above,
1163 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1166 sel_hrd.regs_for_mode_ok[mode] = true;
1169 /* Init all register sets gathered in HRD. */
1171 init_hard_regs_data (void)
1176 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1177 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1178 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1179 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1181 /* Initialize registers that are valid based on mode when this is
1183 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1184 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1186 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1187 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1188 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1191 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1193 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1194 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1198 /* Mark hardware regs in REG_RENAME_P that are not suitable
1199 for renaming rhs in INSN due to hardware restrictions (register class,
1200 modes compatibility etc). This doesn't affect original insn's dest reg,
1201 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1202 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1203 Registers that are in used_regs are always marked in
1204 unavailable_hard_regs as well. */
1207 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1208 regset used_regs ATTRIBUTE_UNUSED)
1210 enum machine_mode mode;
1211 enum reg_class cl = NO_REGS;
1213 unsigned cur_reg, regno;
1214 hard_reg_set_iterator hrsi;
1216 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1217 gcc_assert (reg_rename_p);
1219 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1221 /* We have decided not to rename 'mem = something;' insns, as 'something'
1222 is usually a register. */
1223 if (!REG_P (orig_dest))
1226 regno = REGNO (orig_dest);
1228 /* If before reload, don't try to work with pseudos. */
1229 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1232 if (reload_completed)
1233 cl = get_reg_class (def->orig_insn);
1235 /* Stop if the original register is one of the fixed_regs, global_regs or
1236 frame pointer, or we could not discover its class. */
1237 if (fixed_regs[regno]
1238 || global_regs[regno]
1239 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1240 || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
1242 || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
1244 || (reload_completed && cl == NO_REGS))
1246 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1248 /* Give a chance for original register, if it isn't in used_regs. */
1249 if (!def->crosses_call)
1250 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1255 /* If something allocated on stack in this function, mark frame pointer
1256 register unavailable, considering also modes.
1257 FIXME: it is enough to do this once per all original defs. */
1258 if (frame_pointer_needed)
1262 for (i = hard_regno_nregs[FRAME_POINTER_REGNUM][Pmode]; i--;)
1263 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1264 FRAME_POINTER_REGNUM + i);
1266 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1267 for (i = hard_regno_nregs[HARD_FRAME_POINTER_REGNUM][Pmode]; i--;)
1268 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1269 HARD_FRAME_POINTER_REGNUM + i);
1274 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1275 is equivalent to as if all stack regs were in this set.
1276 I.e. no stack register can be renamed, and even if it's an original
1277 register here we make sure it won't be lifted over it's previous def
1278 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1279 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1280 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1281 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1282 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1283 sel_hrd.stack_regs);
1286 /* If there's a call on this path, make regs from call_used_reg_set
1288 if (def->crosses_call)
1289 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1292 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1293 but not register classes. */
1294 if (!reload_completed)
1297 /* Leave regs as 'available' only from the current
1299 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1300 reg_class_contents[cl]);
1302 mode = GET_MODE (orig_dest);
1304 /* Leave only registers available for this mode. */
1305 if (!sel_hrd.regs_for_mode_ok[mode])
1306 init_regs_for_mode (mode);
1307 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1308 sel_hrd.regs_for_mode[mode]);
1310 /* Exclude registers that are partially call clobbered. */
1311 if (def->crosses_call
1312 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1313 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1314 sel_hrd.regs_for_call_clobbered[mode]);
1316 /* Leave only those that are ok to rename. */
1317 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1323 nregs = hard_regno_nregs[cur_reg][mode];
1324 gcc_assert (nregs > 0);
1326 for (i = nregs - 1; i >= 0; --i)
1327 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1331 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1335 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1336 reg_rename_p->unavailable_hard_regs);
1338 /* Regno is always ok from the renaming part of view, but it really
1339 could be in *unavailable_hard_regs already, so set it here instead
1341 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1344 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1345 best register more recently than REG2. */
1346 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1348 /* Indicates the number of times renaming happened before the current one. */
1349 static int reg_rename_this_tick;
1351 /* Choose the register among free, that is suitable for storing
1354 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1355 originally appears. There could be multiple original operations
1356 for single rhs since we moving it up and merging along different
1359 Some code is adapted from regrename.c (regrename_optimize).
1360 If original register is available, function returns it.
1361 Otherwise it performs the checks, so the new register should
1362 comply with the following:
1363 - it should not violate any live ranges (such registers are in
1364 REG_RENAME_P->available_for_renaming set);
1365 - it should not be in the HARD_REGS_USED regset;
1366 - it should be in the class compatible with original uses;
1367 - it should not be clobbered through reference with different mode;
1368 - if we're in the leaf function, then the new register should
1369 not be in the LEAF_REGISTERS;
1372 If several registers meet the conditions, the register with smallest
1373 tick is returned to achieve more even register allocation.
1375 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1377 If no register satisfies the above conditions, NULL_RTX is returned. */
1379 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1380 struct reg_rename *reg_rename_p,
1381 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1385 enum machine_mode mode = VOIDmode;
1386 unsigned regno, i, n;
1387 hard_reg_set_iterator hrsi;
1388 def_list_iterator di;
1391 /* If original register is available, return it. */
1392 *is_orig_reg_p_ptr = true;
1394 FOR_EACH_DEF (def, di, original_insns)
1396 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1398 gcc_assert (REG_P (orig_dest));
1400 /* Check that all original operations have the same mode.
1401 This is done for the next loop; if we'd return from this
1402 loop, we'd check only part of them, but in this case
1403 it doesn't matter. */
1404 if (mode == VOIDmode)
1405 mode = GET_MODE (orig_dest);
1406 gcc_assert (mode == GET_MODE (orig_dest));
1408 regno = REGNO (orig_dest);
1409 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1410 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1413 /* All hard registers are available. */
1416 gcc_assert (mode != VOIDmode);
1418 /* Hard registers should not be shared. */
1419 return gen_rtx_REG (mode, regno);
1423 *is_orig_reg_p_ptr = false;
1426 /* Among all available regs choose the register that was
1427 allocated earliest. */
1428 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1430 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1432 /* Check that all hard regs for mode are available. */
1433 for (i = 1, n = hard_regno_nregs[cur_reg][mode]; i < n; i++)
1434 if (TEST_HARD_REG_BIT (hard_regs_used, cur_reg + i)
1435 || !TEST_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1442 /* All hard registers are available. */
1443 if (best_new_reg < 0
1444 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1446 best_new_reg = cur_reg;
1448 /* Return immediately when we know there's no better reg. */
1449 if (! reg_rename_tick[best_new_reg])
1454 if (best_new_reg >= 0)
1456 /* Use the check from the above loop. */
1457 gcc_assert (mode != VOIDmode);
1458 return gen_rtx_REG (mode, best_new_reg);
1464 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1465 assumptions about available registers in the function. */
1467 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1468 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1470 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1471 original_insns, is_orig_reg_p_ptr);
1473 /* FIXME loop over hard_regno_nregs here. */
1474 gcc_assert (best_reg == NULL_RTX
1475 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1480 /* Choose the pseudo register for storing rhs value. As this is supposed
1481 to work before reload, we return either the original register or make
1482 the new one. The parameters are the same that in choose_nest_reg_1
1483 functions, except that USED_REGS may contain pseudos.
1484 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1486 TODO: take into account register pressure while doing this. Up to this
1487 moment, this function would never return NULL for pseudos, but we should
1488 not rely on this. */
1490 choose_best_pseudo_reg (regset used_regs,
1491 struct reg_rename *reg_rename_p,
1492 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1494 def_list_iterator i;
1496 enum machine_mode mode = VOIDmode;
1497 bool bad_hard_regs = false;
1499 /* We should not use this after reload. */
1500 gcc_assert (!reload_completed);
1502 /* If original register is available, return it. */
1503 *is_orig_reg_p_ptr = true;
1505 FOR_EACH_DEF (def, i, original_insns)
1507 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1510 gcc_assert (REG_P (dest));
1512 /* Check that all original operations have the same mode. */
1513 if (mode == VOIDmode)
1514 mode = GET_MODE (dest);
1516 gcc_assert (mode == GET_MODE (dest));
1517 orig_regno = REGNO (dest);
1519 if (!REGNO_REG_SET_P (used_regs, orig_regno))
1521 if (orig_regno < FIRST_PSEUDO_REGISTER)
1523 gcc_assert (df_regs_ever_live_p (orig_regno));
1525 /* For hard registers, we have to check hardware imposed
1526 limitations (frame/stack registers, calls crossed). */
1527 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1530 /* Don't let register cross a call if it doesn't already
1531 cross one. This condition is written in accordance with
1532 that in sched-deps.c sched_analyze_reg(). */
1533 if (!reg_rename_p->crosses_call
1534 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1535 return gen_rtx_REG (mode, orig_regno);
1538 bad_hard_regs = true;
1545 *is_orig_reg_p_ptr = false;
1547 /* We had some original hard registers that couldn't be used.
1548 Those were likely special. Don't try to create a pseudo. */
1552 /* We haven't found a register from original operations. Get a new one.
1553 FIXME: control register pressure somehow. */
1555 rtx new_reg = gen_reg_rtx (mode);
1557 gcc_assert (mode != VOIDmode);
1559 max_regno = max_reg_num ();
1560 maybe_extend_reg_info_p ();
1561 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1567 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1568 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1570 verify_target_availability (expr_t expr, regset used_regs,
1571 struct reg_rename *reg_rename_p)
1573 unsigned n, i, regno;
1574 enum machine_mode mode;
1575 bool target_available, live_available, hard_available;
1577 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1580 regno = expr_dest_regno (expr);
1581 mode = GET_MODE (EXPR_LHS (expr));
1582 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1583 n = reload_completed ? hard_regno_nregs[regno][mode] : 1;
1585 live_available = hard_available = true;
1586 for (i = 0; i < n; i++)
1588 if (bitmap_bit_p (used_regs, regno + i))
1589 live_available = false;
1590 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1591 hard_available = false;
1594 /* When target is not available, it may be due to hard register
1595 restrictions, e.g. crosses calls, so we check hard_available too. */
1596 if (target_available)
1597 gcc_assert (live_available);
1599 /* Check only if we haven't scheduled something on the previous fence,
1600 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1601 and having more than one fence, we may end having targ_un in a block
1602 in which successors target register is actually available.
1604 The last condition handles the case when a dependence from a call insn
1605 was created in sched-deps.c for insns with destination registers that
1606 never crossed a call before, but do cross one after our code motion.
1608 FIXME: in the latter case, we just uselessly called find_used_regs,
1609 because we can't move this expression with any other register
1611 gcc_assert (scheduled_something_on_previous_fence || !live_available
1613 || (!reload_completed && reg_rename_p->crosses_call
1614 && REG_N_CALLS_CROSSED (regno) == 0));
1617 /* Collect unavailable registers due to liveness for EXPR from BNDS
1618 into USED_REGS. Save additional information about available
1619 registers and unavailable due to hardware restriction registers
1620 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1623 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1624 struct reg_rename *reg_rename_p,
1625 def_list_t *original_insns)
1627 for (; bnds; bnds = BLIST_NEXT (bnds))
1630 av_set_t orig_ops = NULL;
1631 bnd_t bnd = BLIST_BND (bnds);
1633 /* If the chosen best expr doesn't belong to current boundary,
1635 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1638 /* Put in ORIG_OPS all exprs from this boundary that became
1640 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1642 /* Compute used regs and OR it into the USED_REGS. */
1643 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1644 reg_rename_p, original_insns);
1646 /* FIXME: the assert is true until we'd have several boundaries. */
1648 av_set_clear (&orig_ops);
1652 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1653 If BEST_REG is valid, replace LHS of EXPR with it. */
1655 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1657 /* Try whether we'll be able to generate the insn
1658 'dest := best_reg' at the place of the original operation. */
1659 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1661 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1663 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1665 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1666 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1667 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1671 /* Make sure that EXPR has the right destination
1673 if (expr_dest_regno (expr) != REGNO (best_reg))
1674 replace_dest_with_reg_in_expr (expr, best_reg);
1676 EXPR_TARGET_AVAILABLE (expr) = 1;
1681 /* Select and assign best register to EXPR searching from BNDS.
1682 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1683 Return FALSE if no register can be chosen, which could happen when:
1684 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1685 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1686 that are used on the moving path. */
1688 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1690 static struct reg_rename reg_rename_data;
1693 def_list_t original_insns = NULL;
1696 *is_orig_reg_p = false;
1698 /* Don't bother to do anything if this insn doesn't set any registers. */
1699 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1700 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1703 used_regs = get_clear_regset_from_pool ();
1704 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1706 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data,
1709 #ifdef ENABLE_CHECKING
1710 /* If after reload, make sure we're working with hard regs here. */
1711 if (reload_completed)
1713 reg_set_iterator rsi;
1716 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1721 if (EXPR_SEPARABLE_P (expr))
1723 rtx best_reg = NULL_RTX;
1724 /* Check that we have computed availability of a target register
1726 verify_target_availability (expr, used_regs, ®_rename_data);
1728 /* Turn everything in hard regs after reload. */
1729 if (reload_completed)
1731 HARD_REG_SET hard_regs_used;
1732 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1734 /* Join hard registers unavailable due to register class
1735 restrictions and live range intersection. */
1736 IOR_HARD_REG_SET (hard_regs_used,
1737 reg_rename_data.unavailable_hard_regs);
1739 best_reg = choose_best_reg (hard_regs_used, ®_rename_data,
1740 original_insns, is_orig_reg_p);
1743 best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data,
1744 original_insns, is_orig_reg_p);
1748 else if (*is_orig_reg_p)
1750 /* In case of unification BEST_REG may be different from EXPR's LHS
1751 when EXPR's LHS is unavailable, and there is another LHS among
1753 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1757 /* Forbid renaming of low-cost insns. */
1758 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1761 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1766 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1767 any of the HARD_REGS_USED set. */
1768 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1769 reg_rename_data.unavailable_hard_regs))
1772 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1777 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1781 ilist_clear (&original_insns);
1782 return_regset_to_pool (used_regs);
1788 /* Return true if dependence described by DS can be overcomed. */
1790 can_speculate_dep_p (ds_t ds)
1792 if (spec_info == NULL)
1795 /* Leave only speculative data. */
1802 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1803 that we can overcome. */
1804 ds_t spec_mask = spec_info->mask;
1806 if ((ds & spec_mask) != ds)
1810 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1816 /* Get a speculation check instruction.
1817 C_EXPR is a speculative expression,
1818 CHECK_DS describes speculations that should be checked,
1819 ORIG_INSN is the original non-speculative insn in the stream. */
1821 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1826 basic_block recovery_block;
1829 /* Create a recovery block if target is going to emit branchy check, or if
1830 ORIG_INSN was speculative already. */
1831 if (targetm.sched.needs_block_p (check_ds)
1832 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1834 recovery_block = sel_create_recovery_block (orig_insn);
1835 label = BB_HEAD (recovery_block);
1839 recovery_block = NULL;
1843 /* Get pattern of the check. */
1844 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1847 gcc_assert (check_pattern != NULL);
1850 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1852 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1853 INSN_SEQNO (orig_insn), orig_insn);
1855 /* Make check to be non-speculative. */
1856 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1857 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1859 /* Decrease priority of check by difference of load/check instruction
1861 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1862 - sel_vinsn_cost (INSN_VINSN (insn)));
1864 /* Emit copy of original insn (though with replaced target register,
1865 if needed) to the recovery block. */
1866 if (recovery_block != NULL)
1871 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1872 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1873 twin = sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1874 INSN_EXPR (orig_insn),
1876 bb_note (recovery_block));
1879 /* If we've generated a data speculation check, make sure
1880 that all the bookkeeping instruction we'll create during
1881 this move_op () will allocate an ALAT entry so that the
1883 In case of control speculation we must convert C_EXPR to control
1884 speculative mode, because failing to do so will bring us an exception
1885 thrown by the non-control-speculative load. */
1886 check_ds = ds_get_max_dep_weak (check_ds);
1887 speculate_expr (c_expr, check_ds);
1892 /* True when INSN is a "regN = regN" copy. */
1894 identical_copy_p (rtx insn)
1898 pat = PATTERN (insn);
1900 if (GET_CODE (pat) != SET)
1903 lhs = SET_DEST (pat);
1907 rhs = SET_SRC (pat);
1911 return REGNO (lhs) == REGNO (rhs);
1914 /* Undo all transformations on *AV_PTR that were done when
1915 moving through INSN. */
1917 undo_transformations (av_set_t *av_ptr, rtx insn)
1919 av_set_iterator av_iter;
1921 av_set_t new_set = NULL;
1923 /* First, kill any EXPR that uses registers set by an insn. This is
1924 required for correctness. */
1925 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1926 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1927 && bitmap_intersect_p (INSN_REG_SETS (insn),
1928 VINSN_REG_USES (EXPR_VINSN (expr)))
1929 /* When an insn looks like 'r1 = r1', we could substitute through
1930 it, but the above condition will still hold. This happened with
1931 gcc.c-torture/execute/961125-1.c. */
1932 && !identical_copy_p (insn))
1934 if (sched_verbose >= 6)
1935 sel_print ("Expr %d removed due to use/set conflict\n",
1936 INSN_UID (EXPR_INSN_RTX (expr)));
1937 av_set_iter_remove (&av_iter);
1940 /* Undo transformations looking at the history vector. */
1941 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1943 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1944 insn, EXPR_VINSN (expr), true);
1948 expr_history_def *phist;
1950 phist = VEC_index (expr_history_def,
1951 EXPR_HISTORY_OF_CHANGES (expr),
1954 switch (phist->type)
1956 case TRANS_SPECULATION:
1958 ds_t old_ds, new_ds;
1960 /* Compute the difference between old and new speculative
1961 statuses: that's what we need to check.
1962 Earlier we used to assert that the status will really
1963 change. This no longer works because only the probability
1964 bits in the status may have changed during compute_av_set,
1965 and in the case of merging different probabilities of the
1966 same speculative status along different paths we do not
1967 record this in the history vector. */
1968 old_ds = phist->spec_ds;
1969 new_ds = EXPR_SPEC_DONE_DS (expr);
1971 old_ds &= SPECULATIVE;
1972 new_ds &= SPECULATIVE;
1975 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1978 case TRANS_SUBSTITUTION:
1980 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1984 new_vi = phist->old_expr_vinsn;
1986 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1987 == EXPR_SEPARABLE_P (expr));
1988 copy_expr (tmp_expr, expr);
1990 if (vinsn_equal_p (phist->new_expr_vinsn,
1991 EXPR_VINSN (tmp_expr)))
1992 change_vinsn_in_expr (tmp_expr, new_vi);
1994 /* This happens when we're unsubstituting on a bookkeeping
1995 copy, which was in turn substituted. The history is wrong
1996 in this case. Do it the hard way. */
1997 add = substitute_reg_in_expr (tmp_expr, insn, true);
1999 av_set_add (&new_set, tmp_expr);
2000 clear_expr (tmp_expr);
2010 av_set_union_and_clear (av_ptr, &new_set, NULL);
2014 /* Moveup_* helpers for code motion and computing av sets. */
2016 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2017 The difference from the below function is that only substitution is
2019 static enum MOVEUP_EXPR_CODE
2020 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
2022 vinsn_t vi = EXPR_VINSN (expr);
2026 /* Do this only inside insn group. */
2027 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
2029 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2031 return MOVEUP_EXPR_SAME;
2033 /* Substitution is the possible choice in this case. */
2034 if (has_dep_p[DEPS_IN_RHS])
2036 /* Can't substitute UNIQUE VINSNs. */
2037 gcc_assert (!VINSN_UNIQUE_P (vi));
2039 if (can_substitute_through_p (through_insn,
2040 has_dep_p[DEPS_IN_RHS])
2041 && substitute_reg_in_expr (expr, through_insn, false))
2043 EXPR_WAS_SUBSTITUTED (expr) = true;
2044 return MOVEUP_EXPR_CHANGED;
2047 /* Don't care about this, as even true dependencies may be allowed
2048 in an insn group. */
2049 return MOVEUP_EXPR_SAME;
2052 /* This can catch output dependencies in COND_EXECs. */
2053 if (has_dep_p[DEPS_IN_INSN])
2054 return MOVEUP_EXPR_NULL;
2056 /* This is either an output or an anti dependence, which usually have
2057 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2059 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2060 return MOVEUP_EXPR_AS_RHS;
2063 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2064 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2065 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2066 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2067 && !sel_insn_is_speculation_check (through_insn))
2069 /* True when a conflict on a target register was found during moveup_expr. */
2070 static bool was_target_conflict = false;
2072 /* Return true when moving a debug INSN across THROUGH_INSN will
2073 create a bookkeeping block. We don't want to create such blocks,
2074 for they would cause codegen differences between compilations with
2075 and without debug info. */
2078 moving_insn_creates_bookkeeping_block_p (insn_t insn,
2079 insn_t through_insn)
2081 basic_block bbi, bbt;
2083 edge_iterator ei1, ei2;
2085 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn))
2087 if (sched_verbose >= 9)
2088 sel_print ("no bookkeeping required: ");
2092 bbi = BLOCK_FOR_INSN (insn);
2094 if (EDGE_COUNT (bbi->preds) == 1)
2096 if (sched_verbose >= 9)
2097 sel_print ("only one pred edge: ");
2101 bbt = BLOCK_FOR_INSN (through_insn);
2103 FOR_EACH_EDGE (e1, ei1, bbt->succs)
2105 FOR_EACH_EDGE (e2, ei2, bbi->preds)
2107 if (find_block_for_bookkeeping (e1, e2, TRUE))
2109 if (sched_verbose >= 9)
2110 sel_print ("found existing block: ");
2116 if (sched_verbose >= 9)
2117 sel_print ("would create bookkeeping block: ");
2122 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2123 performing necessary transformations. Record the type of transformation
2124 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2125 permit all dependencies except true ones, and try to remove those
2126 too via forward substitution. All cases when a non-eliminable
2127 non-zero cost dependency exists inside an insn group will be fixed
2128 in tick_check_p instead. */
2129 static enum MOVEUP_EXPR_CODE
2130 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2131 enum local_trans_type *ptrans_type)
2133 vinsn_t vi = EXPR_VINSN (expr);
2134 insn_t insn = VINSN_INSN_RTX (vi);
2135 bool was_changed = false;
2136 bool as_rhs = false;
2140 /* When inside_insn_group, delegate to the helper. */
2141 if (inside_insn_group)
2142 return moveup_expr_inside_insn_group (expr, through_insn);
2144 /* Deal with unique insns and control dependencies. */
2145 if (VINSN_UNIQUE_P (vi))
2147 /* We can move jumps without side-effects or jumps that are
2148 mutually exclusive with instruction THROUGH_INSN (all in cases
2149 dependencies allow to do so and jump is not speculative). */
2150 if (control_flow_insn_p (insn))
2152 basic_block fallthru_bb;
2154 /* Do not move checks and do not move jumps through other
2156 if (control_flow_insn_p (through_insn)
2157 || sel_insn_is_speculation_check (insn))
2158 return MOVEUP_EXPR_NULL;
2160 /* Don't move jumps through CFG joins. */
2161 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2162 return MOVEUP_EXPR_NULL;
2164 /* The jump should have a clear fallthru block, and
2165 this block should be in the current region. */
2166 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2167 || ! in_current_region_p (fallthru_bb))
2168 return MOVEUP_EXPR_NULL;
2170 /* And it should be mutually exclusive with through_insn, or
2171 be an unconditional jump. */
2172 if (! any_uncondjump_p (insn)
2173 && ! sched_insns_conditions_mutex_p (insn, through_insn)
2174 && ! DEBUG_INSN_P (through_insn))
2175 return MOVEUP_EXPR_NULL;
2178 /* Don't move what we can't move. */
2179 if (EXPR_CANT_MOVE (expr)
2180 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2181 return MOVEUP_EXPR_NULL;
2183 /* Don't move SCHED_GROUP instruction through anything.
2184 If we don't force this, then it will be possible to start
2185 scheduling a sched_group before all its dependencies are
2187 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2188 as late as possible through rank_for_schedule. */
2189 if (SCHED_GROUP_P (insn))
2190 return MOVEUP_EXPR_NULL;
2193 gcc_assert (!control_flow_insn_p (insn));
2195 /* Don't move debug insns if this would require bookkeeping. */
2196 if (DEBUG_INSN_P (insn)
2197 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)
2198 && moving_insn_creates_bookkeeping_block_p (insn, through_insn))
2199 return MOVEUP_EXPR_NULL;
2201 /* Deal with data dependencies. */
2202 was_target_conflict = false;
2203 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2206 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2207 return MOVEUP_EXPR_SAME;
2211 /* We can move UNIQUE insn up only as a whole and unchanged,
2212 so it shouldn't have any dependencies. */
2213 if (VINSN_UNIQUE_P (vi))
2214 return MOVEUP_EXPR_NULL;
2217 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2221 res = speculate_expr (expr, full_ds);
2224 /* Speculation was successful. */
2226 was_changed = (res > 0);
2228 was_target_conflict = true;
2230 *ptrans_type = TRANS_SPECULATION;
2231 sel_clear_has_dependence ();
2235 if (has_dep_p[DEPS_IN_INSN])
2236 /* We have some dependency that cannot be discarded. */
2237 return MOVEUP_EXPR_NULL;
2239 if (has_dep_p[DEPS_IN_LHS])
2241 /* Only separable insns can be moved up with the new register.
2242 Anyways, we should mark that the original register is
2244 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2245 return MOVEUP_EXPR_NULL;
2247 EXPR_TARGET_AVAILABLE (expr) = false;
2248 was_target_conflict = true;
2252 /* At this point we have either separable insns, that will be lifted
2253 up only as RHSes, or non-separable insns with no dependency in lhs.
2254 If dependency is in RHS, then try to perform substitution and move up
2261 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2262 moved above y=x assignment as z=x*2.
2264 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2265 side can be moved because of the output dependency. The operation was
2266 cropped to its rhs above. */
2267 if (has_dep_p[DEPS_IN_RHS])
2269 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2271 /* Can't substitute UNIQUE VINSNs. */
2272 gcc_assert (!VINSN_UNIQUE_P (vi));
2274 if (can_speculate_dep_p (*rhs_dsp))
2278 res = speculate_expr (expr, *rhs_dsp);
2281 /* Speculation was successful. */
2283 was_changed = (res > 0);
2285 was_target_conflict = true;
2287 *ptrans_type = TRANS_SPECULATION;
2290 return MOVEUP_EXPR_NULL;
2292 else if (can_substitute_through_p (through_insn,
2294 && substitute_reg_in_expr (expr, through_insn, false))
2296 /* ??? We cannot perform substitution AND speculation on the same
2298 gcc_assert (!was_changed);
2301 *ptrans_type = TRANS_SUBSTITUTION;
2302 EXPR_WAS_SUBSTITUTED (expr) = true;
2305 return MOVEUP_EXPR_NULL;
2308 /* Don't move trapping insns through jumps.
2309 This check should be at the end to give a chance to control speculation
2310 to perform its duties. */
2311 if (CANT_MOVE_TRAPPING (expr, through_insn))
2312 return MOVEUP_EXPR_NULL;
2315 ? MOVEUP_EXPR_CHANGED
2317 ? MOVEUP_EXPR_AS_RHS
2318 : MOVEUP_EXPR_SAME));
2321 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2322 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2323 that can exist within a parallel group. Write to RES the resulting
2324 code for moveup_expr. */
2326 try_bitmap_cache (expr_t expr, insn_t insn,
2327 bool inside_insn_group,
2328 enum MOVEUP_EXPR_CODE *res)
2330 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2332 /* First check whether we've analyzed this situation already. */
2333 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2335 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2337 if (sched_verbose >= 6)
2338 sel_print ("removed (cached)\n");
2339 *res = MOVEUP_EXPR_NULL;
2344 if (sched_verbose >= 6)
2345 sel_print ("unchanged (cached)\n");
2346 *res = MOVEUP_EXPR_SAME;
2350 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2352 if (inside_insn_group)
2354 if (sched_verbose >= 6)
2355 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2356 *res = MOVEUP_EXPR_SAME;
2361 EXPR_TARGET_AVAILABLE (expr) = false;
2363 /* This is the only case when propagation result can change over time,
2364 as we can dynamically switch off scheduling as RHS. In this case,
2365 just check the flag to reach the correct decision. */
2366 if (enable_schedule_as_rhs_p)
2368 if (sched_verbose >= 6)
2369 sel_print ("unchanged (as RHS, cached)\n");
2370 *res = MOVEUP_EXPR_AS_RHS;
2375 if (sched_verbose >= 6)
2376 sel_print ("removed (cached as RHS, but renaming"
2377 " is now disabled)\n");
2378 *res = MOVEUP_EXPR_NULL;
2386 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2387 if successful. Write to RES the resulting code for moveup_expr. */
2389 try_transformation_cache (expr_t expr, insn_t insn,
2390 enum MOVEUP_EXPR_CODE *res)
2392 struct transformed_insns *pti
2393 = (struct transformed_insns *)
2394 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2396 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2399 /* This EXPR was already moved through this insn and was
2400 changed as a result. Fetch the proper data from
2402 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2403 INSN_UID (insn), pti->type,
2404 pti->vinsn_old, pti->vinsn_new,
2405 EXPR_SPEC_DONE_DS (expr));
2407 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2408 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2409 change_vinsn_in_expr (expr, pti->vinsn_new);
2410 if (pti->was_target_conflict)
2411 EXPR_TARGET_AVAILABLE (expr) = false;
2412 if (pti->type == TRANS_SPECULATION)
2416 ds = EXPR_SPEC_DONE_DS (expr);
2418 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2419 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2422 if (sched_verbose >= 6)
2424 sel_print ("changed (cached): ");
2429 *res = MOVEUP_EXPR_CHANGED;
2436 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2438 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2439 enum MOVEUP_EXPR_CODE res)
2441 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2443 /* Do not cache result of propagating jumps through an insn group,
2444 as it is always true, which is not useful outside the group. */
2445 if (inside_insn_group)
2448 if (res == MOVEUP_EXPR_NULL)
2450 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2451 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2453 else if (res == MOVEUP_EXPR_SAME)
2455 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2456 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2458 else if (res == MOVEUP_EXPR_AS_RHS)
2460 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2461 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2467 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2468 and transformation type TRANS_TYPE. */
2470 update_transformation_cache (expr_t expr, insn_t insn,
2471 bool inside_insn_group,
2472 enum local_trans_type trans_type,
2473 vinsn_t expr_old_vinsn)
2475 struct transformed_insns *pti;
2477 if (inside_insn_group)
2480 pti = XNEW (struct transformed_insns);
2481 pti->vinsn_old = expr_old_vinsn;
2482 pti->vinsn_new = EXPR_VINSN (expr);
2483 pti->type = trans_type;
2484 pti->was_target_conflict = was_target_conflict;
2485 pti->ds = EXPR_SPEC_DONE_DS (expr);
2486 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2487 vinsn_attach (pti->vinsn_old);
2488 vinsn_attach (pti->vinsn_new);
2489 *((struct transformed_insns **)
2490 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2491 pti, VINSN_HASH_RTX (expr_old_vinsn),
2495 /* Same as moveup_expr, but first looks up the result of
2496 transformation in caches. */
2497 static enum MOVEUP_EXPR_CODE
2498 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2500 enum MOVEUP_EXPR_CODE res;
2501 bool got_answer = false;
2503 if (sched_verbose >= 6)
2505 sel_print ("Moving ");
2507 sel_print (" through %d: ", INSN_UID (insn));
2510 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr))
2511 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr)))
2512 == EXPR_INSN_RTX (expr)))
2513 /* Don't use cached information for debug insns that are heads of
2515 else if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2516 /* When inside insn group, we do not want remove stores conflicting
2517 with previosly issued loads. */
2518 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2519 else if (try_transformation_cache (expr, insn, &res))
2524 /* Invoke moveup_expr and record the results. */
2525 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2526 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2527 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2528 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2529 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2531 /* ??? Invent something better than this. We can't allow old_vinsn
2532 to go, we need it for the history vector. */
2533 vinsn_attach (expr_old_vinsn);
2535 res = moveup_expr (expr, insn, inside_insn_group,
2539 case MOVEUP_EXPR_NULL:
2540 update_bitmap_cache (expr, insn, inside_insn_group, res);
2541 if (sched_verbose >= 6)
2542 sel_print ("removed\n");
2545 case MOVEUP_EXPR_SAME:
2546 update_bitmap_cache (expr, insn, inside_insn_group, res);
2547 if (sched_verbose >= 6)
2548 sel_print ("unchanged\n");
2551 case MOVEUP_EXPR_AS_RHS:
2552 gcc_assert (!unique_p || inside_insn_group);
2553 update_bitmap_cache (expr, insn, inside_insn_group, res);
2554 if (sched_verbose >= 6)
2555 sel_print ("unchanged (as RHS)\n");
2558 case MOVEUP_EXPR_CHANGED:
2559 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2560 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2561 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2562 INSN_UID (insn), trans_type,
2563 expr_old_vinsn, EXPR_VINSN (expr),
2565 update_transformation_cache (expr, insn, inside_insn_group,
2566 trans_type, expr_old_vinsn);
2567 if (sched_verbose >= 6)
2569 sel_print ("changed: ");
2578 vinsn_detach (expr_old_vinsn);
2584 /* Moves an av set AVP up through INSN, performing necessary
2587 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2592 FOR_EACH_EXPR_1 (expr, i, avp)
2595 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2597 case MOVEUP_EXPR_SAME:
2598 case MOVEUP_EXPR_AS_RHS:
2601 case MOVEUP_EXPR_NULL:
2602 av_set_iter_remove (&i);
2605 case MOVEUP_EXPR_CHANGED:
2606 expr = merge_with_other_exprs (avp, &i, expr);
2615 /* Moves AVP set along PATH. */
2617 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2621 if (sched_verbose >= 6)
2622 sel_print ("Moving expressions up in the insn group...\n");
2625 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2627 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2629 moveup_set_expr (avp, ILIST_INSN (path), true);
2630 path = ILIST_NEXT (path);
2634 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2636 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2638 expr_def _tmp, *tmp = &_tmp;
2642 copy_expr_onside (tmp, expr);
2643 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2646 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2648 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2649 != MOVEUP_EXPR_NULL);
2650 path = ILIST_NEXT (path);
2655 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2656 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2658 if (tmp_vinsn != expr_vliw_vinsn)
2659 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2667 /* Functions that compute av and lv sets. */
2669 /* Returns true if INSN is not a downward continuation of the given path P in
2670 the current stage. */
2672 is_ineligible_successor (insn_t insn, ilist_t p)
2676 /* Check if insn is not deleted. */
2677 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2679 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2682 /* If it's the first insn visited, then the successor is ok. */
2686 prev_insn = ILIST_INSN (p);
2688 if (/* a backward edge. */
2689 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2690 /* is already visited. */
2691 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2692 && (ilist_is_in_p (p, insn)
2693 /* We can reach another fence here and still seqno of insn
2694 would be equal to seqno of prev_insn. This is possible
2695 when prev_insn is a previously created bookkeeping copy.
2696 In that case it'd get a seqno of insn. Thus, check here
2697 whether insn is in current fence too. */
2698 || IN_CURRENT_FENCE_P (insn)))
2699 /* Was already scheduled on this round. */
2700 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2701 && IN_CURRENT_FENCE_P (insn))
2702 /* An insn from another fence could also be
2703 scheduled earlier even if this insn is not in
2704 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2706 && INSN_SCHED_TIMES (insn) > 0))
2712 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2713 of handling multiple successors and properly merging its av_sets. P is
2714 the current path traversed. WS is the size of lookahead window.
2715 Return the av set computed. */
2717 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2719 struct succs_info *sinfo;
2720 av_set_t expr_in_all_succ_branches = NULL;
2722 insn_t succ, zero_succ = NULL;
2723 av_set_t av1 = NULL;
2725 gcc_assert (sel_bb_end_p (insn));
2727 /* Find different kind of successors needed for correct computing of
2728 SPEC and TARGET_AVAILABLE attributes. */
2729 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2732 if (sched_verbose >= 6)
2734 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2735 dump_insn_vector (sinfo->succs_ok);
2737 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2738 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2741 /* Add insn to to the tail of current path. */
2742 ilist_add (&p, insn);
2744 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2748 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2749 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2751 av_set_split_usefulness (succ_set,
2752 VEC_index (int, sinfo->probs_ok, is),
2755 if (sinfo->all_succs_n > 1)
2757 /* Find EXPR'es that came from *all* successors and save them
2758 into expr_in_all_succ_branches. This set will be used later
2759 for calculating speculation attributes of EXPR'es. */
2762 expr_in_all_succ_branches = av_set_copy (succ_set);
2764 /* Remember the first successor for later. */
2772 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2773 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2774 av_set_iter_remove (&i);
2778 /* Union the av_sets. Check liveness restrictions on target registers
2779 in special case of two successors. */
2780 if (sinfo->succs_ok_n == 2 && is == 1)
2782 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2783 basic_block bb1 = BLOCK_FOR_INSN (succ);
2785 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2786 av_set_union_and_live (&av1, &succ_set,
2792 av_set_union_and_clear (&av1, &succ_set, insn);
2795 /* Check liveness restrictions via hard way when there are more than
2797 if (sinfo->succs_ok_n > 2)
2798 for (is = 0; VEC_iterate (rtx, sinfo->succs_ok, is, succ); is++)
2800 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2802 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2803 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2804 BB_LV_SET (succ_bb));
2807 /* Finally, check liveness restrictions on paths leaving the region. */
2808 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2809 for (is = 0; VEC_iterate (rtx, sinfo->succs_other, is, succ); is++)
2810 mark_unavailable_targets
2811 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2813 if (sinfo->all_succs_n > 1)
2818 /* Increase the spec attribute of all EXPR'es that didn't come
2819 from all successors. */
2820 FOR_EACH_EXPR (expr, i, av1)
2821 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2824 av_set_clear (&expr_in_all_succ_branches);
2826 /* Do not move conditional branches through other
2827 conditional branches. So, remove all conditional
2828 branches from av_set if current operator is a conditional
2830 av_set_substract_cond_branches (&av1);
2834 free_succs_info (sinfo);
2836 if (sched_verbose >= 6)
2838 sel_print ("av_succs (%d): ", INSN_UID (insn));
2846 /* This function computes av_set for the FIRST_INSN by dragging valid
2847 av_set through all basic block insns either from the end of basic block
2848 (computed using compute_av_set_at_bb_end) or from the insn on which
2849 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2850 below the basic block and handling conditional branches.
2851 FIRST_INSN - the basic block head, P - path consisting of the insns
2852 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2853 and bb ends are added to the path), WS - current window size,
2854 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2856 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2861 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2862 insn_t after_bb_end = NEXT_INSN (bb_end);
2865 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2867 /* Return NULL if insn is not on the legitimate downward path. */
2868 if (is_ineligible_successor (first_insn, p))
2870 if (sched_verbose >= 6)
2871 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2876 /* If insn already has valid av(insn) computed, just return it. */
2877 if (AV_SET_VALID_P (first_insn))
2881 if (sel_bb_head_p (first_insn))
2882 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2886 if (sched_verbose >= 6)
2888 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2889 dump_av_set (av_set);
2893 return need_copy_p ? av_set_copy (av_set) : av_set;
2896 ilist_add (&p, first_insn);
2898 /* As the result after this loop have completed, in LAST_INSN we'll
2899 have the insn which has valid av_set to start backward computation
2900 from: it either will be NULL because on it the window size was exceeded
2901 or other valid av_set as returned by compute_av_set for the last insn
2902 of the basic block. */
2903 for (last_insn = first_insn; last_insn != after_bb_end;
2904 last_insn = NEXT_INSN (last_insn))
2906 /* We may encounter valid av_set not only on bb_head, but also on
2907 those insns on which previously MAX_WS was exceeded. */
2908 if (AV_SET_VALID_P (last_insn))
2910 if (sched_verbose >= 6)
2911 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2915 /* The special case: the last insn of the BB may be an
2916 ineligible_successor due to its SEQ_NO that was set on
2917 it as a bookkeeping. */
2918 if (last_insn != first_insn
2919 && is_ineligible_successor (last_insn, p))
2921 if (sched_verbose >= 6)
2922 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
2926 if (DEBUG_INSN_P (last_insn))
2929 if (end_ws > max_ws)
2931 /* We can reach max lookahead size at bb_header, so clean av_set
2933 INSN_WS_LEVEL (last_insn) = global_level;
2935 if (sched_verbose >= 6)
2936 sel_print ("Insn %d is beyond the software lookahead window size\n",
2937 INSN_UID (last_insn));
2944 /* Get the valid av_set into AV above the LAST_INSN to start backward
2945 computation from. It either will be empty av_set or av_set computed from
2946 the successors on the last insn of the current bb. */
2947 if (last_insn != after_bb_end)
2951 /* This is needed only to obtain av_sets that are identical to
2952 those computed by the old compute_av_set version. */
2953 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
2954 av_set_add (&av, INSN_EXPR (last_insn));
2957 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2958 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
2960 /* Compute av_set in AV starting from below the LAST_INSN up to
2961 location above the FIRST_INSN. */
2962 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
2963 cur_insn = PREV_INSN (cur_insn))
2964 if (!INSN_NOP_P (cur_insn))
2968 moveup_set_expr (&av, cur_insn, false);
2970 /* If the expression for CUR_INSN is already in the set,
2971 replace it by the new one. */
2972 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
2976 copy_expr (expr, INSN_EXPR (cur_insn));
2979 av_set_add (&av, INSN_EXPR (cur_insn));
2982 /* Clear stale bb_av_set. */
2983 if (sel_bb_head_p (first_insn))
2985 av_set_clear (&BB_AV_SET (cur_bb));
2986 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
2987 BB_AV_LEVEL (cur_bb) = global_level;
2990 if (sched_verbose >= 6)
2992 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
3001 /* Compute av set before INSN.
3002 INSN - the current operation (actual rtx INSN)
3003 P - the current path, which is list of insns visited so far
3004 WS - software lookahead window size.
3005 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3006 if we want to save computed av_set in s_i_d, we should make a copy of it.
3008 In the resulting set we will have only expressions that don't have delay
3009 stalls and nonsubstitutable dependences. */
3011 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
3013 return compute_av_set_inside_bb (insn, p, ws, unique_p);
3016 /* Propagate a liveness set LV through INSN. */
3018 propagate_lv_set (regset lv, insn_t insn)
3020 gcc_assert (INSN_P (insn));
3022 if (INSN_NOP_P (insn))
3025 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
3028 /* Return livness set at the end of BB. */
3030 compute_live_after_bb (basic_block bb)
3034 regset lv = get_clear_regset_from_pool ();
3036 gcc_assert (!ignore_first);
3038 FOR_EACH_EDGE (e, ei, bb->succs)
3039 if (sel_bb_empty_p (e->dest))
3041 if (! BB_LV_SET_VALID_P (e->dest))
3044 gcc_assert (BB_LV_SET (e->dest) == NULL);
3045 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
3046 BB_LV_SET_VALID_P (e->dest) = true;
3048 IOR_REG_SET (lv, BB_LV_SET (e->dest));
3051 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
3056 /* Compute the set of all live registers at the point before INSN and save
3057 it at INSN if INSN is bb header. */
3059 compute_live (insn_t insn)
3061 basic_block bb = BLOCK_FOR_INSN (insn);
3065 /* Return the valid set if we're already on it. */
3070 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3071 src = BB_LV_SET (bb);
3074 gcc_assert (in_current_region_p (bb));
3075 if (INSN_LIVE_VALID_P (insn))
3076 src = INSN_LIVE (insn);
3081 lv = get_regset_from_pool ();
3082 COPY_REG_SET (lv, src);
3084 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3086 COPY_REG_SET (BB_LV_SET (bb), lv);
3087 BB_LV_SET_VALID_P (bb) = true;
3090 return_regset_to_pool (lv);
3095 /* We've skipped the wrong lv_set. Don't skip the right one. */
3096 ignore_first = false;
3097 gcc_assert (in_current_region_p (bb));
3099 /* Find a valid LV set in this block or below, if needed.
3100 Start searching from the next insn: either ignore_first is true, or
3101 INSN doesn't have a correct live set. */
3102 temp = NEXT_INSN (insn);
3103 final = NEXT_INSN (BB_END (bb));
3104 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3105 temp = NEXT_INSN (temp);
3108 lv = compute_live_after_bb (bb);
3109 temp = PREV_INSN (temp);
3113 lv = get_regset_from_pool ();
3114 COPY_REG_SET (lv, INSN_LIVE (temp));
3117 /* Put correct lv sets on the insns which have bad sets. */
3118 final = PREV_INSN (insn);
3119 while (temp != final)
3121 propagate_lv_set (lv, temp);
3122 COPY_REG_SET (INSN_LIVE (temp), lv);
3123 INSN_LIVE_VALID_P (temp) = true;
3124 temp = PREV_INSN (temp);
3127 /* Also put it in a BB. */
3128 if (sel_bb_head_p (insn))
3130 basic_block bb = BLOCK_FOR_INSN (insn);
3132 COPY_REG_SET (BB_LV_SET (bb), lv);
3133 BB_LV_SET_VALID_P (bb) = true;
3136 /* We return LV to the pool, but will not clear it there. Thus we can
3137 legimatelly use LV till the next use of regset_pool_get (). */
3138 return_regset_to_pool (lv);
3142 /* Update liveness sets for INSN. */
3144 update_liveness_on_insn (rtx insn)
3146 ignore_first = true;
3147 compute_live (insn);
3150 /* Compute liveness below INSN and write it into REGS. */
3152 compute_live_below_insn (rtx insn, regset regs)
3157 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3158 IOR_REG_SET (regs, compute_live (succ));
3161 /* Update the data gathered in av and lv sets starting from INSN. */
3163 update_data_sets (rtx insn)
3165 update_liveness_on_insn (insn);
3166 if (sel_bb_head_p (insn))
3168 gcc_assert (AV_LEVEL (insn) != 0);
3169 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3170 compute_av_set (insn, NULL, 0, 0);
3175 /* Helper for move_op () and find_used_regs ().
3176 Return speculation type for which a check should be created on the place
3177 of INSN. EXPR is one of the original ops we are searching for. */
3179 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3182 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3184 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3186 if (targetm.sched.get_insn_checked_ds)
3187 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3189 if (spec_info != NULL
3190 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3191 already_checked_ds |= BEGIN_CONTROL;
3193 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3195 to_check_ds &= ~already_checked_ds;
3200 /* Find the set of registers that are unavailable for storing expres
3201 while moving ORIG_OPS up on the path starting from INSN due to
3202 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3204 All the original operations found during the traversal are saved in the
3205 ORIGINAL_INSNS list.
3207 REG_RENAME_P denotes the set of hardware registers that
3208 can not be used with renaming due to the register class restrictions,
3209 mode restrictions and other (the register we'll choose should be
3210 compatible class with the original uses, shouldn't be in call_used_regs,
3211 should be HARD_REGNO_RENAME_OK etc).
3213 Returns TRUE if we've found all original insns, FALSE otherwise.
3215 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3216 to traverse the code motion paths. This helper function finds registers
3217 that are not available for storing expres while moving ORIG_OPS up on the
3218 path starting from INSN. A register considered as used on the moving path,
3219 if one of the following conditions is not satisfied:
3221 (1) a register not set or read on any path from xi to an instance of
3222 the original operation,
3223 (2) not among the live registers of the point immediately following the
3224 first original operation on a given downward path, except for the
3225 original target register of the operation,
3226 (3) not live on the other path of any conditional branch that is passed
3227 by the operation, in case original operations are not present on
3228 both paths of the conditional branch.
3230 All the original operations found during the traversal are saved in the
3231 ORIGINAL_INSNS list.
3233 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3234 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3235 to unavailable hard regs at the point original operation is found. */
3238 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3239 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3241 def_list_iterator i;
3244 bool needs_spec_check_p = false;
3246 av_set_iterator expr_iter;
3247 struct fur_static_params sparams;
3248 struct cmpd_local_params lparams;
3250 /* We haven't visited any blocks yet. */
3251 bitmap_clear (code_motion_visited_blocks);
3253 /* Init parameters for code_motion_path_driver. */
3254 sparams.crosses_call = false;
3255 sparams.original_insns = original_insns;
3256 sparams.used_regs = used_regs;
3258 /* Set the appropriate hooks and data. */
3259 code_motion_path_driver_info = &fur_hooks;
3261 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3263 reg_rename_p->crosses_call |= sparams.crosses_call;
3265 gcc_assert (res == 1);
3266 gcc_assert (original_insns && *original_insns);
3268 /* ??? We calculate whether an expression needs a check when computing
3269 av sets. This information is not as precise as it could be due to
3270 merging this bit in merge_expr. We can do better in find_used_regs,
3271 but we want to avoid multiple traversals of the same code motion
3273 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3274 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3276 /* Mark hardware regs in REG_RENAME_P that are not suitable
3277 for renaming expr in INSN due to hardware restrictions (register class,
3278 modes compatibility etc). */
3279 FOR_EACH_DEF (def, i, *original_insns)
3281 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3283 if (VINSN_SEPARABLE_P (vinsn))
3284 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3286 /* Do not allow clobbering of ld.[sa] address in case some of the
3287 original operations need a check. */
3288 if (needs_spec_check_p)
3289 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3296 /* Functions to choose the best insn from available ones. */
3298 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3300 sel_target_adjust_priority (expr_t expr)
3302 int priority = EXPR_PRIORITY (expr);
3305 if (targetm.sched.adjust_priority)
3306 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3308 new_priority = priority;
3310 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3311 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3313 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3315 if (sched_verbose >= 4)
3316 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3317 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3318 EXPR_PRIORITY_ADJ (expr), new_priority);
3320 return new_priority;
3323 /* Rank two available exprs for schedule. Never return 0 here. */
3325 sel_rank_for_schedule (const void *x, const void *y)
3327 expr_t tmp = *(const expr_t *) y;
3328 expr_t tmp2 = *(const expr_t *) x;
3329 insn_t tmp_insn, tmp2_insn;
3330 vinsn_t tmp_vinsn, tmp2_vinsn;
3333 tmp_vinsn = EXPR_VINSN (tmp);
3334 tmp2_vinsn = EXPR_VINSN (tmp2);
3335 tmp_insn = EXPR_INSN_RTX (tmp);
3336 tmp2_insn = EXPR_INSN_RTX (tmp2);
3338 /* Schedule debug insns as early as possible. */
3339 if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn))
3341 else if (DEBUG_INSN_P (tmp2_insn))
3344 /* Prefer SCHED_GROUP_P insns to any others. */
3345 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3347 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3348 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3350 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3351 cannot be cloned. */
3352 if (VINSN_UNIQUE_P (tmp2_vinsn))
3357 /* Discourage scheduling of speculative checks. */
3358 val = (sel_insn_is_speculation_check (tmp_insn)
3359 - sel_insn_is_speculation_check (tmp2_insn));
3363 /* Prefer not scheduled insn over scheduled one. */
3364 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3366 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3371 /* Prefer jump over non-jump instruction. */
3372 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3374 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3377 /* Prefer an expr with greater priority. */
3378 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3380 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3381 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3383 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3386 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3387 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3391 if (spec_info != NULL && spec_info->mask != 0)
3392 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3398 ds1 = EXPR_SPEC_DONE_DS (tmp);
3400 dw1 = ds_weak (ds1);
3404 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3406 dw2 = ds_weak (ds2);
3411 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3415 /* Prefer an old insn to a bookkeeping insn. */
3416 if (INSN_UID (tmp_insn) < first_emitted_uid
3417 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3419 if (INSN_UID (tmp_insn) >= first_emitted_uid
3420 && INSN_UID (tmp2_insn) < first_emitted_uid)
3423 /* Prefer an insn with smaller UID, as a last resort.
3424 We can't safely use INSN_LUID as it is defined only for those insns
3425 that are in the stream. */
3426 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3429 /* Filter out expressions from av set pointed to by AV_PTR
3430 that are pipelined too many times. */
3432 process_pipelined_exprs (av_set_t *av_ptr)
3437 /* Don't pipeline already pipelined code as that would increase
3438 number of unnecessary register moves. */
3439 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3441 if (EXPR_SCHED_TIMES (expr)
3442 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3443 av_set_iter_remove (&si);
3447 /* Filter speculative insns from AV_PTR if we don't want them. */
3449 process_spec_exprs (av_set_t *av_ptr)
3451 bool try_data_p = true;
3452 bool try_control_p = true;
3456 if (spec_info == NULL)
3459 /* Scan *AV_PTR to find out if we want to consider speculative
3460 instructions for scheduling. */
3461 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3465 ds = EXPR_SPEC_DONE_DS (expr);
3467 /* The probability of a success is too low - don't speculate. */
3468 if ((ds & SPECULATIVE)
3469 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3470 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3471 || (pipelining_p && false
3473 && (ds & CONTROL_SPEC))))
3475 av_set_iter_remove (&si);
3479 if ((spec_info->flags & PREFER_NON_DATA_SPEC)
3480 && !(ds & BEGIN_DATA))
3483 if ((spec_info->flags & PREFER_NON_CONTROL_SPEC)
3484 && !(ds & BEGIN_CONTROL))
3485 try_control_p = false;
3488 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3492 ds = EXPR_SPEC_DONE_DS (expr);
3494 if (ds & SPECULATIVE)
3496 if ((ds & BEGIN_DATA) && !try_data_p)
3497 /* We don't want any data speculative instructions right
3499 av_set_iter_remove (&si);
3501 if ((ds & BEGIN_CONTROL) && !try_control_p)
3502 /* We don't want any control speculative instructions right
3504 av_set_iter_remove (&si);
3509 /* Search for any use-like insns in AV_PTR and decide on scheduling
3510 them. Return one when found, and NULL otherwise.
3511 Note that we check here whether a USE could be scheduled to avoid
3512 an infinite loop later. */
3514 process_use_exprs (av_set_t *av_ptr)
3518 bool uses_present_p = false;
3519 bool try_uses_p = true;
3521 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3523 /* This will also initialize INSN_CODE for later use. */
3524 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3526 /* If we have a USE in *AV_PTR that was not scheduled yet,
3527 do so because it will do good only. */
3528 if (EXPR_SCHED_TIMES (expr) <= 0)
3530 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3533 av_set_iter_remove (&si);
3537 gcc_assert (pipelining_p);
3539 uses_present_p = true;
3548 /* If we don't want to schedule any USEs right now and we have some
3549 in *AV_PTR, remove them, else just return the first one found. */
3552 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3553 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3554 av_set_iter_remove (&si);
3558 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3560 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3562 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3565 av_set_iter_remove (&si);
3573 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3575 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3580 for (n = 0; VEC_iterate (vinsn_t, vinsn_vec, n, vinsn); n++)
3581 if (VINSN_SEPARABLE_P (vinsn))
3583 if (vinsn_equal_p (vinsn, EXPR_VINSN (expr)))
3588 /* For non-separable instructions, the blocking insn can have
3589 another pattern due to substitution, and we can't choose
3590 different register as in the above case. Check all registers
3591 being written instead. */
3592 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3593 VINSN_REG_SETS (EXPR_VINSN (expr))))
3600 #ifdef ENABLE_CHECKING
3601 /* Return true if either of expressions from ORIG_OPS can be blocked
3602 by previously created bookkeeping code. STATIC_PARAMS points to static
3603 parameters of move_op. */
3605 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3608 av_set_iterator iter;
3609 moveop_static_params_p sparams;
3611 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3612 created while scheduling on another fence. */
3613 FOR_EACH_EXPR (expr, iter, orig_ops)
3614 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3617 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3618 sparams = (moveop_static_params_p) static_params;
3620 /* Expressions can be also blocked by bookkeeping created during current
3622 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3623 FOR_EACH_EXPR (expr, iter, orig_ops)
3624 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3627 /* Expressions in ORIG_OPS may have wrong destination register due to
3628 renaming. Check with the right register instead. */
3629 if (sparams->dest && REG_P (sparams->dest))
3631 unsigned regno = REGNO (sparams->dest);
3632 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3634 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn), regno)
3635 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn), regno)
3636 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn), regno))
3644 /* Clear VINSN_VEC and detach vinsns. */
3646 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3648 unsigned len = VEC_length (vinsn_t, *vinsn_vec);
3654 for (n = 0; VEC_iterate (vinsn_t, *vinsn_vec, n, vinsn); n++)
3655 vinsn_detach (vinsn);
3656 VEC_block_remove (vinsn_t, *vinsn_vec, 0, len);
3660 /* Add the vinsn of EXPR to the VINSN_VEC. */
3662 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3664 vinsn_attach (EXPR_VINSN (expr));
3665 VEC_safe_push (vinsn_t, heap, *vinsn_vec, EXPR_VINSN (expr));
3668 /* Free the vector representing blocked expressions. */
3670 vinsn_vec_free (vinsn_vec_t *vinsn_vec)
3673 VEC_free (vinsn_t, heap, *vinsn_vec);
3676 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3678 void sel_add_to_insn_priority (rtx insn, int amount)
3680 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3682 if (sched_verbose >= 2)
3683 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3684 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3685 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3688 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3689 true if there is something to schedule. BNDS and FENCE are current
3690 boundaries and fence, respectively. If we need to stall for some cycles
3691 before an expr from AV would become available, write this number to
3694 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3699 int sched_next_worked = 0, stalled, n;
3700 static int av_max_prio, est_ticks_till_branch;
3701 int min_need_stall = -1;
3702 deps_t dc = BND_DC (BLIST_BND (bnds));
3704 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3705 already scheduled. */
3709 /* Empty vector from the previous stuff. */
3710 if (VEC_length (expr_t, vec_av_set) > 0)
3711 VEC_block_remove (expr_t, vec_av_set, 0, VEC_length (expr_t, vec_av_set));
3713 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3715 gcc_assert (VEC_empty (expr_t, vec_av_set));
3716 FOR_EACH_EXPR (expr, si, av)
3718 VEC_safe_push (expr_t, heap, vec_av_set, expr);
3720 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3722 /* Adjust priority using target backend hook. */
3723 sel_target_adjust_priority (expr);
3726 /* Sort the vector. */
3727 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3728 sizeof (expr_t), sel_rank_for_schedule);
3730 /* We record maximal priority of insns in av set for current instruction
3732 if (FENCE_STARTS_CYCLE_P (fence))
3733 av_max_prio = est_ticks_till_branch = INT_MIN;
3735 /* Filter out inappropriate expressions. Loop's direction is reversed to
3736 visit "best" instructions first. We assume that VEC_unordered_remove
3737 moves last element in place of one being deleted. */
3738 for (n = VEC_length (expr_t, vec_av_set) - 1, stalled = 0; n >= 0; n--)
3740 expr_t expr = VEC_index (expr_t, vec_av_set, n);
3741 insn_t insn = EXPR_INSN_RTX (expr);
3742 char target_available;
3743 bool is_orig_reg_p = true;
3744 int need_cycles, new_prio;
3746 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3747 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3749 VEC_unordered_remove (expr_t, vec_av_set, n);
3753 /* Set number of sched_next insns (just in case there
3754 could be several). */
3755 if (FENCE_SCHED_NEXT (fence))
3756 sched_next_worked++;
3758 /* Check all liveness requirements and try renaming.
3759 FIXME: try to minimize calls to this. */
3760 target_available = EXPR_TARGET_AVAILABLE (expr);
3762 /* If insn was already scheduled on the current fence,
3763 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3764 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr))
3765 target_available = -1;
3767 /* If the availability of the EXPR is invalidated by the insertion of
3768 bookkeeping earlier, make sure that we won't choose this expr for
3769 scheduling if it's not separable, and if it is separable, then
3770 we have to recompute the set of available registers for it. */
3771 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3773 VEC_unordered_remove (expr_t, vec_av_set, n);
3774 if (sched_verbose >= 4)
3775 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3780 if (target_available == true)
3782 /* Do nothing -- we can use an existing register. */
3783 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3785 else if (/* Non-separable instruction will never
3786 get another register. */
3787 (target_available == false
3788 && !EXPR_SEPARABLE_P (expr))
3789 /* Don't try to find a register for low-priority expression. */
3790 || (int) VEC_length (expr_t, vec_av_set) - 1 - n >= max_insns_to_rename
3791 /* ??? FIXME: Don't try to rename data speculation. */
3792 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3793 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3795 VEC_unordered_remove (expr_t, vec_av_set, n);
3796 if (sched_verbose >= 4)
3797 sel_print ("Expr %d has no suitable target register\n",
3802 /* Filter expressions that need to be renamed or speculated when
3803 pipelining, because compensating register copies or speculation
3804 checks are likely to be placed near the beginning of the loop,
3806 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3807 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3809 /* Estimation of number of cycles until loop branch for
3810 renaming/speculation to be successful. */
3811 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3813 if ((int) current_loop_nest->ninsns < 9)
3815 VEC_unordered_remove (expr_t, vec_av_set, n);
3816 if (sched_verbose >= 4)
3817 sel_print ("Pipelining expr %d will likely cause stall\n",
3822 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3823 < need_n_ticks_till_branch * issue_rate / 2
3824 && est_ticks_till_branch < need_n_ticks_till_branch)
3826 VEC_unordered_remove (expr_t, vec_av_set, n);
3827 if (sched_verbose >= 4)
3828 sel_print ("Pipelining expr %d will likely cause stall\n",
3834 /* We want to schedule speculation checks as late as possible. Discard
3835 them from av set if there are instructions with higher priority. */
3836 if (sel_insn_is_speculation_check (insn)
3837 && EXPR_PRIORITY (expr) < av_max_prio)
3840 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3841 VEC_unordered_remove (expr_t, vec_av_set, n);
3842 if (sched_verbose >= 4)
3843 sel_print ("Delaying speculation check %d until its first use\n",
3848 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3849 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3850 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3852 /* Don't allow any insns whose data is not yet ready.
3853 Check first whether we've already tried them and failed. */
3854 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3856 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3857 - FENCE_CYCLE (fence));
3858 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3859 est_ticks_till_branch = MAX (est_ticks_till_branch,
3860 EXPR_PRIORITY (expr) + need_cycles);
3862 if (need_cycles > 0)
3865 min_need_stall = (min_need_stall < 0
3867 : MIN (min_need_stall, need_cycles));
3868 VEC_unordered_remove (expr_t, vec_av_set, n);
3870 if (sched_verbose >= 4)
3871 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3873 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3878 /* Now resort to dependence analysis to find whether EXPR might be
3879 stalled due to dependencies from FENCE's context. */
3880 need_cycles = tick_check_p (expr, dc, fence);
3881 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3883 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3884 est_ticks_till_branch = MAX (est_ticks_till_branch,
3887 if (need_cycles > 0)
3889 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3891 int new_size = INSN_UID (insn) * 3 / 2;
3893 FENCE_READY_TICKS (fence)
3894 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3895 new_size, FENCE_READY_TICKS_SIZE (fence),
3898 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3899 = FENCE_CYCLE (fence) + need_cycles;
3902 min_need_stall = (min_need_stall < 0
3904 : MIN (min_need_stall, need_cycles));
3906 VEC_unordered_remove (expr_t, vec_av_set, n);
3908 if (sched_verbose >= 4)
3909 sel_print ("Expr %d is not ready yet until cycle %d\n",
3911 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3915 if (sched_verbose >= 4)
3916 sel_print ("Expr %d is ok\n", INSN_UID (insn));
3920 /* Clear SCHED_NEXT. */
3921 if (FENCE_SCHED_NEXT (fence))
3923 gcc_assert (sched_next_worked == 1);
3924 FENCE_SCHED_NEXT (fence) = NULL_RTX;
3927 /* No need to stall if this variable was not initialized. */
3928 if (min_need_stall < 0)
3931 if (VEC_empty (expr_t, vec_av_set))
3933 /* We need to set *pneed_stall here, because later we skip this code
3934 when ready list is empty. */
3935 *pneed_stall = min_need_stall;
3939 gcc_assert (min_need_stall == 0);
3941 /* Sort the vector. */
3942 qsort (VEC_address (expr_t, vec_av_set), VEC_length (expr_t, vec_av_set),
3943 sizeof (expr_t), sel_rank_for_schedule);
3945 if (sched_verbose >= 4)
3947 sel_print ("Total ready exprs: %d, stalled: %d\n",
3948 VEC_length (expr_t, vec_av_set), stalled);
3949 sel_print ("Sorted av set (%d): ", VEC_length (expr_t, vec_av_set));
3950 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3959 /* Convert a vectored and sorted av set to the ready list that
3960 the rest of the backend wants to see. */
3962 convert_vec_av_set_to_ready (void)
3967 /* Allocate and fill the ready list from the sorted vector. */
3968 ready.n_ready = VEC_length (expr_t, vec_av_set);
3969 ready.first = ready.n_ready - 1;
3971 gcc_assert (ready.n_ready > 0);
3973 if (ready.n_ready > max_issue_size)
3975 max_issue_size = ready.n_ready;
3976 sched_extend_ready_list (ready.n_ready);
3979 for (n = 0; VEC_iterate (expr_t, vec_av_set, n, expr); n++)
3981 vinsn_t vi = EXPR_VINSN (expr);
3982 insn_t insn = VINSN_INSN_RTX (vi);
3985 ready.vec[n] = insn;
3989 /* Initialize ready list from *AV_PTR for the max_issue () call.
3990 If any unrecognizable insn found in *AV_PTR, return it (and skip
3991 max_issue). BND and FENCE are current boundary and fence,
3992 respectively. If we need to stall for some cycles before an expr
3993 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3995 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
4000 /* We do not support multiple boundaries per fence. */
4001 gcc_assert (BLIST_NEXT (bnds) == NULL);
4003 /* Process expressions required special handling, i.e. pipelined,
4004 speculative and recog() < 0 expressions first. */
4005 process_pipelined_exprs (av_ptr);
4006 process_spec_exprs (av_ptr);
4008 /* A USE could be scheduled immediately. */
4009 expr = process_use_exprs (av_ptr);
4016 /* Turn the av set to a vector for sorting. */
4017 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
4023 /* Build the final ready list. */
4024 convert_vec_av_set_to_ready ();
4028 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4030 sel_dfa_new_cycle (insn_t insn, fence_t fence)
4032 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
4033 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
4034 : FENCE_CYCLE (fence) - 1;
4038 if (!targetm.sched.dfa_new_cycle)
4041 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4043 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
4044 insn, last_scheduled_cycle,
4045 FENCE_CYCLE (fence), &sort_p))
4047 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4048 advance_one_cycle (fence);
4049 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4056 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4057 we can issue. FENCE is the current fence. */
4059 invoke_reorder_hooks (fence_t fence)
4062 bool ran_hook = false;
4064 /* Call the reorder hook at the beginning of the cycle, and call
4065 the reorder2 hook in the middle of the cycle. */
4066 if (FENCE_ISSUED_INSNS (fence) == 0)
4068 if (targetm.sched.reorder
4069 && !SCHED_GROUP_P (ready_element (&ready, 0))
4070 && ready.n_ready > 1)
4072 /* Don't give reorder the most prioritized insn as it can break
4078 = targetm.sched.reorder (sched_dump, sched_verbose,
4079 ready_lastpos (&ready),
4080 &ready.n_ready, FENCE_CYCLE (fence));
4088 /* Initialize can_issue_more for variable_issue. */
4089 issue_more = issue_rate;
4091 else if (targetm.sched.reorder2
4092 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4094 if (ready.n_ready == 1)
4096 targetm.sched.reorder2 (sched_dump, sched_verbose,
4097 ready_lastpos (&ready),
4098 &ready.n_ready, FENCE_CYCLE (fence));
4105 targetm.sched.reorder2 (sched_dump, sched_verbose,
4107 ? ready_lastpos (&ready) : NULL,
4108 &ready.n_ready, FENCE_CYCLE (fence));
4117 issue_more = FENCE_ISSUE_MORE (fence);
4119 /* Ensure that ready list and vec_av_set are in line with each other,
4120 i.e. vec_av_set[i] == ready_element (&ready, i). */
4121 if (issue_more && ran_hook)
4124 rtx *arr = ready.vec;
4125 expr_t *vec = VEC_address (expr_t, vec_av_set);
4127 for (i = 0, n = ready.n_ready; i < n; i++)
4128 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4132 for (j = i; j < n; j++)
4133 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4146 /* Return an EXPR correponding to INDEX element of ready list, if
4147 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4148 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4149 ready.vec otherwise. */
4150 static inline expr_t
4151 find_expr_for_ready (int index, bool follow_ready_element)
4156 real_index = follow_ready_element ? ready.first - index : index;
4158 expr = VEC_index (expr_t, vec_av_set, real_index);
4159 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4164 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4165 of such insns found. */
4167 invoke_dfa_lookahead_guard (void)
4171 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4173 if (sched_verbose >= 2)
4174 sel_print ("ready after reorder: ");
4176 for (i = 0, n = 0; i < ready.n_ready; i++)
4182 /* In this loop insn is Ith element of the ready list given by
4183 ready_element, not Ith element of ready.vec. */
4184 insn = ready_element (&ready, i);
4186 if (! have_hook || i == 0)
4189 r = !targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn);
4191 gcc_assert (INSN_CODE (insn) >= 0);
4193 /* Only insns with ready_try = 0 can get here
4194 from fill_ready_list. */
4195 gcc_assert (ready_try [i] == 0);
4200 expr = find_expr_for_ready (i, true);
4202 if (sched_verbose >= 2)
4204 dump_vinsn (EXPR_VINSN (expr));
4205 sel_print (":%d; ", ready_try[i]);
4209 if (sched_verbose >= 2)
4214 /* Calculate the number of privileged insns and return it. */
4216 calculate_privileged_insns (void)
4218 expr_t cur_expr, min_spec_expr = NULL;
4219 insn_t cur_insn, min_spec_insn;
4220 int privileged_n = 0, i;
4222 for (i = 0; i < ready.n_ready; i++)
4227 if (! min_spec_expr)
4229 min_spec_insn = ready_element (&ready, i);
4230 min_spec_expr = find_expr_for_ready (i, true);
4233 cur_insn = ready_element (&ready, i);
4234 cur_expr = find_expr_for_ready (i, true);
4236 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4242 if (i == ready.n_ready)
4245 if (sched_verbose >= 2)
4246 sel_print ("privileged_n: %d insns with SPEC %d\n",
4247 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4248 return privileged_n;
4251 /* Call the rest of the hooks after the choice was made. Return
4252 the number of insns that still can be issued given that the current
4253 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4254 and the insn chosen for scheduling, respectively. */
4256 invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more)
4258 gcc_assert (INSN_P (best_insn));
4260 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4261 sel_dfa_new_cycle (best_insn, fence);
4263 if (targetm.sched.variable_issue)
4265 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4267 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4269 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4271 else if (GET_CODE (PATTERN (best_insn)) != USE
4272 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4278 /* Estimate the cost of issuing INSN on DFA state STATE. */
4280 estimate_insn_cost (rtx insn, state_t state)
4282 static state_t temp = NULL;
4286 temp = xmalloc (dfa_state_size);
4288 memcpy (temp, state, dfa_state_size);
4289 cost = state_transition (temp, insn);
4298 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4299 This function properly handles ASMs, USEs etc. */
4301 get_expr_cost (expr_t expr, fence_t fence)
4303 rtx insn = EXPR_INSN_RTX (expr);
4305 if (recog_memoized (insn) < 0)
4307 if (!FENCE_STARTS_CYCLE_P (fence)
4308 && INSN_ASM_P (insn))
4309 /* This is asm insn which is tryed to be issued on the
4310 cycle not first. Issue it on the next cycle. */
4313 /* A USE insn, or something else we don't need to
4314 understand. We can't pass these directly to
4315 state_transition because it will trigger a
4316 fatal error for unrecognizable insns. */
4320 return estimate_insn_cost (insn, FENCE_STATE (fence));
4323 /* Find the best insn for scheduling, either via max_issue or just take
4324 the most prioritized available. */
4326 choose_best_insn (fence_t fence, int privileged_n, int *index)
4330 if (dfa_lookahead > 0)
4332 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4333 can_issue = max_issue (&ready, privileged_n,
4334 FENCE_STATE (fence), index);
4335 if (sched_verbose >= 2)
4336 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4337 can_issue, FENCE_ISSUED_INSNS (fence));
4341 /* We can't use max_issue; just return the first available element. */
4344 for (i = 0; i < ready.n_ready; i++)
4346 expr_t expr = find_expr_for_ready (i, true);
4348 if (get_expr_cost (expr, fence) < 1)
4350 can_issue = can_issue_more;
4353 if (sched_verbose >= 2)
4354 sel_print ("using %dth insn from the ready list\n", i + 1);
4360 if (i == ready.n_ready)
4370 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4371 BNDS and FENCE are current boundaries and scheduling fence respectively.
4372 Return the expr found and NULL if nothing can be issued atm.
4373 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4375 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4380 /* Choose the best insn for scheduling via:
4381 1) sorting the ready list based on priority;
4382 2) calling the reorder hook;
4383 3) calling max_issue. */
4384 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4385 if (best == NULL && ready.n_ready > 0)
4387 int privileged_n, index, avail_n;
4389 can_issue_more = invoke_reorder_hooks (fence);
4390 if (can_issue_more > 0)
4392 /* Try choosing the best insn until we find one that is could be
4393 scheduled due to liveness restrictions on its destination register.
4394 In the future, we'd like to choose once and then just probe insns
4395 in the order of their priority. */
4396 avail_n = invoke_dfa_lookahead_guard ();
4397 privileged_n = calculate_privileged_insns ();
4398 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4400 best = find_expr_for_ready (index, true);
4402 /* We had some available insns, so if we can't issue them,
4404 if (can_issue_more == 0)
4413 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4415 if (can_issue_more == 0)
4419 if (sched_verbose >= 2)
4423 sel_print ("Best expression (vliw form): ");
4425 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4428 sel_print ("No best expr found!\n");
4435 /* Functions that implement the core of the scheduler. */
4438 /* Emit an instruction from EXPR with SEQNO and VINSN after
4441 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4442 insn_t place_to_insert)
4444 /* This assert fails when we have identical instructions
4445 one of which dominates the other. In this case move_op ()
4446 finds the first instruction and doesn't search for second one.
4447 The solution would be to compute av_set after the first found
4448 insn and, if insn present in that set, continue searching.
4449 For now we workaround this issue in move_op. */
4450 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4452 if (EXPR_WAS_RENAMED (expr))
4454 unsigned regno = expr_dest_regno (expr);
4456 if (HARD_REGISTER_NUM_P (regno))
4458 df_set_regs_ever_live (regno, true);
4459 reg_rename_tick[regno] = ++reg_rename_this_tick;
4463 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4467 /* Return TRUE if BB can hold bookkeeping code. */
4469 block_valid_for_bookkeeping_p (basic_block bb)
4471 insn_t bb_end = BB_END (bb);
4473 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4476 if (INSN_P (bb_end))
4478 if (INSN_SCHED_TIMES (bb_end) > 0)
4482 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4487 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4488 into E2->dest, except from E1->src (there may be a sequence of empty basic
4489 blocks between E1->src and E2->dest). Return found block, or NULL if new
4490 one must be created. If LAX holds, don't assume there is a simple path
4491 from E1->src to E2->dest. */
4493 find_block_for_bookkeeping (edge e1, edge e2, bool lax)
4495 basic_block candidate_block = NULL;
4498 /* Loop over edges from E1 to E2, inclusive. */
4499 for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR; e = EDGE_SUCC (e->dest, 0))
4501 if (EDGE_COUNT (e->dest->preds) == 2)
4503 if (candidate_block == NULL)
4504 candidate_block = (EDGE_PRED (e->dest, 0) == e
4505 ? EDGE_PRED (e->dest, 1)->src
4506 : EDGE_PRED (e->dest, 0)->src);
4508 /* Found additional edge leading to path from e1 to e2
4512 else if (EDGE_COUNT (e->dest->preds) > 2)
4513 /* Several edges leading to path from e1 to e2 from aside. */
4517 return ((!lax || candidate_block)
4518 && block_valid_for_bookkeeping_p (candidate_block)
4522 if (lax && EDGE_COUNT (e->dest->succs) != 1)
4532 /* Create new basic block for bookkeeping code for path(s) incoming into
4533 E2->dest, except from E1->src. Return created block. */
4535 create_block_for_bookkeeping (edge e1, edge e2)
4537 basic_block new_bb, bb = e2->dest;
4539 /* Check that we don't spoil the loop structure. */
4540 if (current_loop_nest)
4542 basic_block latch = current_loop_nest->latch;
4544 /* We do not split header. */
4545 gcc_assert (e2->dest != current_loop_nest->header);
4547 /* We do not redirect the only edge to the latch block. */
4548 gcc_assert (e1->dest != latch
4549 || !single_pred_p (latch)
4550 || e1 != single_pred_edge (latch));
4553 /* Split BB to insert BOOK_INSN there. */
4554 new_bb = sched_split_block (bb, NULL);
4556 /* Move note_list from the upper bb. */
4557 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4558 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4559 BB_NOTE_LIST (bb) = NULL_RTX;
4561 gcc_assert (e2->dest == bb);
4563 /* Skip block for bookkeeping copy when leaving E1->src. */
4564 if (e1->flags & EDGE_FALLTHRU)
4565 sel_redirect_edge_and_branch_force (e1, new_bb);
4567 sel_redirect_edge_and_branch (e1, new_bb);
4569 gcc_assert (e1->dest == new_bb);
4570 gcc_assert (sel_bb_empty_p (bb));
4572 /* To keep basic block numbers in sync between debug and non-debug
4573 compilations, we have to rotate blocks here. Consider that we
4574 started from (a,b)->d, (c,d)->e, and d contained only debug
4575 insns. It would have been removed before if the debug insns
4576 weren't there, so we'd have split e rather than d. So what we do
4577 now is to swap the block numbers of new_bb and
4578 single_succ(new_bb) == e, so that the insns that were in e before
4579 get the new block number. */
4581 if (MAY_HAVE_DEBUG_INSNS)
4584 insn_t insn = sel_bb_head (new_bb);
4587 if (DEBUG_INSN_P (insn)
4588 && single_succ_p (new_bb)
4589 && (succ = single_succ (new_bb))
4590 && succ != EXIT_BLOCK_PTR
4591 && DEBUG_INSN_P ((last = sel_bb_end (new_bb))))
4593 while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4594 insn = NEXT_INSN (insn);
4598 sel_global_bb_info_def gbi;
4599 sel_region_bb_info_def rbi;
4602 if (sched_verbose >= 2)
4603 sel_print ("Swapping block ids %i and %i\n",
4604 new_bb->index, succ->index);
4607 new_bb->index = succ->index;
4610 SET_BASIC_BLOCK (new_bb->index, new_bb);
4611 SET_BASIC_BLOCK (succ->index, succ);
4613 memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi));
4614 memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ),
4616 memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi));
4618 memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi));
4619 memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ),
4621 memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi));
4623 i = BLOCK_TO_BB (new_bb->index);
4624 BLOCK_TO_BB (new_bb->index) = BLOCK_TO_BB (succ->index);
4625 BLOCK_TO_BB (succ->index) = i;
4627 i = CONTAINING_RGN (new_bb->index);
4628 CONTAINING_RGN (new_bb->index) = CONTAINING_RGN (succ->index);
4629 CONTAINING_RGN (succ->index) = i;
4631 for (i = 0; i < current_nr_blocks; i++)
4632 if (BB_TO_BLOCK (i) == succ->index)
4633 BB_TO_BLOCK (i) = new_bb->index;
4634 else if (BB_TO_BLOCK (i) == new_bb->index)
4635 BB_TO_BLOCK (i) = succ->index;
4637 FOR_BB_INSNS (new_bb, insn)
4639 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index;
4641 FOR_BB_INSNS (succ, insn)
4643 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index;
4645 if (bitmap_bit_p (code_motion_visited_blocks, new_bb->index))
4647 bitmap_set_bit (code_motion_visited_blocks, succ->index);
4648 bitmap_clear_bit (code_motion_visited_blocks, new_bb->index);
4651 gcc_assert (LABEL_P (BB_HEAD (new_bb))
4652 && LABEL_P (BB_HEAD (succ)));
4654 if (sched_verbose >= 4)
4655 sel_print ("Swapping code labels %i and %i\n",
4656 CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4657 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4659 i = CODE_LABEL_NUMBER (BB_HEAD (new_bb));
4660 CODE_LABEL_NUMBER (BB_HEAD (new_bb))
4661 = CODE_LABEL_NUMBER (BB_HEAD (succ));
4662 CODE_LABEL_NUMBER (BB_HEAD (succ)) = i;
4670 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4671 into E2->dest, except from E1->src. */
4673 find_place_for_bookkeeping (edge e1, edge e2)
4675 insn_t place_to_insert;
4676 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4677 create new basic block, but insert bookkeeping there. */
4678 basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE);
4682 place_to_insert = BB_END (book_block);
4684 /* Don't use a block containing only debug insns for
4685 bookkeeping, this causes scheduling differences between debug
4686 and non-debug compilations, for the block would have been
4688 if (DEBUG_INSN_P (place_to_insert))
4690 rtx insn = sel_bb_head (book_block);
4692 while (insn != place_to_insert &&
4693 (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4694 insn = NEXT_INSN (insn);
4696 if (insn == place_to_insert)
4703 book_block = create_block_for_bookkeeping (e1, e2);
4704 place_to_insert = BB_END (book_block);
4705 if (sched_verbose >= 9)
4706 sel_print ("New block is %i, split from bookkeeping block %i\n",
4707 EDGE_SUCC (book_block, 0)->dest->index, book_block->index);
4711 if (sched_verbose >= 9)
4712 sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index);
4715 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4716 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4717 place_to_insert = PREV_INSN (place_to_insert);
4719 return place_to_insert;
4722 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4725 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4730 /* Check if we are about to insert bookkeeping copy before a jump, and use
4731 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4732 next = NEXT_INSN (place_to_insert);
4735 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4737 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4738 seqno = INSN_SEQNO (next);
4740 else if (INSN_SEQNO (join_point) > 0)
4741 seqno = INSN_SEQNO (join_point);
4744 seqno = get_seqno_by_preds (place_to_insert);
4746 /* Sometimes the fences can move in such a way that there will be
4747 no instructions with positive seqno around this bookkeeping.
4748 This means that there will be no way to get to it by a regular
4749 fence movement. Never mind because we pick up such pieces for
4750 rescheduling anyways, so any positive value will do for now. */
4753 gcc_assert (pipelining_p);
4758 gcc_assert (seqno > 0);
4762 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4763 NEW_SEQNO to it. Return created insn. */
4765 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4767 rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4770 = create_vinsn_from_insn_rtx (new_insn_rtx,
4771 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4773 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4776 INSN_SCHED_TIMES (new_insn) = 0;
4777 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4782 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4783 E2->dest, except from E1->src (there may be a sequence of empty blocks
4784 between E1->src and E2->dest). Return block containing the copy.
4785 All scheduler data is initialized for the newly created insn. */
4787 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4789 insn_t join_point, place_to_insert, new_insn;
4791 bool need_to_exchange_data_sets;
4793 if (sched_verbose >= 4)
4794 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4797 join_point = sel_bb_head (e2->dest);
4798 place_to_insert = find_place_for_bookkeeping (e1, e2);
4799 if (!place_to_insert)
4801 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4802 need_to_exchange_data_sets
4803 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4805 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4807 /* When inserting bookkeeping insn in new block, av sets should be
4808 following: old basic block (that now holds bookkeeping) data sets are
4809 the same as was before generation of bookkeeping, and new basic block
4810 (that now hold all other insns of old basic block) data sets are
4811 invalid. So exchange data sets for these basic blocks as sel_split_block
4812 mistakenly exchanges them in this case. Cannot do it earlier because
4813 when single instruction is added to new basic block it should hold NULL
4815 if (need_to_exchange_data_sets)
4816 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4817 BLOCK_FOR_INSN (join_point));
4819 stat_bookkeeping_copies++;
4820 return BLOCK_FOR_INSN (new_insn);
4823 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4824 on FENCE, but we are unable to copy them. */
4826 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4831 /* An expression does not need bookkeeping if it is available on all paths
4832 from current block to original block and current block dominates
4833 original block. We check availability on all paths by examining
4834 EXPR_SPEC; this is not equivalent, because it may be positive even
4835 if expr is available on all paths (but if expr is not available on
4836 any path, EXPR_SPEC will be positive). */
4838 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4840 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4841 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4842 && (EXPR_SPEC (expr)
4843 || !EXPR_ORIG_BB_INDEX (expr)
4844 || !dominated_by_p (CDI_DOMINATORS,
4845 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr)),
4846 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4848 if (sched_verbose >= 4)
4849 sel_print ("Expr %d removed because it would need bookkeeping, which "
4850 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4851 av_set_iter_remove (&i);
4856 /* Moving conditional jump through some instructions.
4860 ... <- current scheduling point
4861 NOTE BASIC BLOCK: <- bb header
4862 (p8) add r14=r14+0x9;;
4868 We can schedule jump one cycle earlier, than mov, because they cannot be
4869 executed together as their predicates are mutually exclusive.
4871 This is done in this way: first, new fallthrough basic block is created
4872 after jump (it is always can be done, because there already should be a
4873 fallthrough block, where control flow goes in case of predicate being true -
4874 in our example; otherwise there should be a dependence between those
4875 instructions and jump and we cannot schedule jump right now);
4876 next, all instructions between jump and current scheduling point are moved
4877 to this new block. And the result is this:
4880 (!p8) jump L1 <- current scheduling point
4881 NOTE BASIC BLOCK: <- bb header
4882 (p8) add r14=r14+0x9;;
4888 move_cond_jump (rtx insn, bnd_t bnd)
4891 basic_block block_from, block_next, block_new;
4892 rtx next, prev, link;
4894 /* BLOCK_FROM holds basic block of the jump. */
4895 block_from = BLOCK_FOR_INSN (insn);
4897 /* Moving of jump should not cross any other jumps or
4898 beginnings of new basic blocks. */
4899 gcc_assert (block_from == BLOCK_FOR_INSN (BND_TO (bnd)));
4901 /* Jump is moved to the boundary. */
4902 prev = BND_TO (bnd);
4903 next = PREV_INSN (insn);
4904 BND_TO (bnd) = insn;
4906 ft_edge = find_fallthru_edge (block_from);
4907 block_next = ft_edge->dest;
4908 /* There must be a fallthrough block (or where should go
4909 control flow in case of false jump predicate otherwise?). */
4910 gcc_assert (block_next);
4912 /* Create new empty basic block after source block. */
4913 block_new = sel_split_edge (ft_edge);
4914 gcc_assert (block_new->next_bb == block_next
4915 && block_from->next_bb == block_new);
4917 gcc_assert (BB_END (block_from) == insn);
4919 /* Move all instructions except INSN from BLOCK_FROM to
4921 for (link = prev; link != insn; link = NEXT_INSN (link))
4923 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
4924 df_insn_change_bb (link, block_new);
4927 /* Set correct basic block and instructions properties. */
4928 BB_END (block_new) = PREV_INSN (insn);
4930 NEXT_INSN (PREV_INSN (prev)) = insn;
4931 PREV_INSN (insn) = PREV_INSN (prev);
4933 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4934 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
4935 PREV_INSN (prev) = BB_HEAD (block_new);
4936 NEXT_INSN (next) = NEXT_INSN (BB_HEAD (block_new));
4937 NEXT_INSN (BB_HEAD (block_new)) = prev;
4938 PREV_INSN (NEXT_INSN (next)) = next;
4940 gcc_assert (!sel_bb_empty_p (block_from)
4941 && !sel_bb_empty_p (block_new));
4943 /* Update data sets for BLOCK_NEW to represent that INSN and
4944 instructions from the other branch of INSN is no longer
4945 available at BLOCK_NEW. */
4946 BB_AV_LEVEL (block_new) = global_level;
4947 gcc_assert (BB_LV_SET (block_new) == NULL);
4948 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
4949 update_data_sets (sel_bb_head (block_new));
4951 /* INSN is a new basic block header - so prepare its data
4952 structures and update availability and liveness sets. */
4953 update_data_sets (insn);
4955 if (sched_verbose >= 4)
4956 sel_print ("Moving jump %d\n", INSN_UID (insn));
4959 /* Remove nops generated during move_op for preventing removal of empty
4962 remove_temp_moveop_nops (bool full_tidying)
4967 for (i = 0; VEC_iterate (insn_t, vec_temp_moveop_nops, i, insn); i++)
4969 gcc_assert (INSN_NOP_P (insn));
4970 return_nop_to_pool (insn, full_tidying);
4973 /* Empty the vector. */
4974 if (VEC_length (insn_t, vec_temp_moveop_nops) > 0)
4975 VEC_block_remove (insn_t, vec_temp_moveop_nops, 0,
4976 VEC_length (insn_t, vec_temp_moveop_nops));
4979 /* Records the maximal UID before moving up an instruction. Used for
4980 distinguishing between bookkeeping copies and original insns. */
4981 static int max_uid_before_move_op = 0;
4983 /* Remove from AV_VLIW_P all instructions but next when debug counter
4984 tells us so. Next instruction is fetched from BNDS. */
4986 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
4988 if (! dbg_cnt (sel_sched_insn_cnt))
4989 /* Leave only the next insn in av_vliw. */
4991 av_set_iterator av_it;
4993 bnd_t bnd = BLIST_BND (bnds);
4994 insn_t next = BND_TO (bnd);
4996 gcc_assert (BLIST_NEXT (bnds) == NULL);
4998 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
4999 if (EXPR_INSN_RTX (expr) != next)
5000 av_set_iter_remove (&av_it);
5004 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5005 the computed set to *AV_VLIW_P. */
5007 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
5009 if (sched_verbose >= 2)
5011 sel_print ("Boundaries: ");
5016 for (; bnds; bnds = BLIST_NEXT (bnds))
5018 bnd_t bnd = BLIST_BND (bnds);
5020 insn_t bnd_to = BND_TO (bnd);
5022 /* Rewind BND->TO to the basic block header in case some bookkeeping
5023 instructions were inserted before BND->TO and it needs to be
5025 if (sel_bb_head_p (bnd_to))
5026 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
5028 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
5030 bnd_to = PREV_INSN (bnd_to);
5031 if (sel_bb_head_p (bnd_to))
5035 if (BND_TO (bnd) != bnd_to)
5037 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
5038 FENCE_INSN (fence) = bnd_to;
5039 BND_TO (bnd) = bnd_to;
5042 av_set_clear (&BND_AV (bnd));
5043 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
5045 av_set_clear (&BND_AV1 (bnd));
5046 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
5048 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
5050 av1_copy = av_set_copy (BND_AV1 (bnd));
5051 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
5054 if (sched_verbose >= 2)
5056 sel_print ("Available exprs (vliw form): ");
5057 dump_av_set (*av_vliw_p);
5062 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5063 expression. When FOR_MOVEOP is true, also replace the register of
5064 expressions found with the register from EXPR_VLIW. */
5066 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
5068 av_set_t expr_seq = NULL;
5072 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
5074 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
5078 /* The sequential expression has the right form to pass
5079 to move_op except when renaming happened. Put the
5080 correct register in EXPR then. */
5081 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
5083 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
5085 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
5086 stat_renamed_scheduled++;
5088 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5089 This is needed when renaming came up with original
5091 else if (EXPR_TARGET_AVAILABLE (expr)
5092 != EXPR_TARGET_AVAILABLE (expr_vliw))
5094 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
5095 EXPR_TARGET_AVAILABLE (expr) = 1;
5098 if (EXPR_WAS_SUBSTITUTED (expr))
5099 stat_substitutions_total++;
5102 av_set_add (&expr_seq, expr);
5104 /* With substitution inside insn group, it is possible
5105 that more than one expression in expr_seq will correspond
5106 to expr_vliw. In this case, choose one as the attempt to
5107 move both leads to miscompiles. */
5112 if (for_moveop && sched_verbose >= 2)
5114 sel_print ("Best expression(s) (sequential form): ");
5115 dump_av_set (expr_seq);
5123 /* Move nop to previous block. */
5124 static void ATTRIBUTE_UNUSED
5125 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
5127 insn_t prev_insn, next_insn, note;
5129 gcc_assert (sel_bb_head_p (nop)
5130 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
5131 note = bb_note (BLOCK_FOR_INSN (nop));
5132 prev_insn = sel_bb_end (prev_bb);
5133 next_insn = NEXT_INSN (nop);
5134 gcc_assert (prev_insn != NULL_RTX
5135 && PREV_INSN (note) == prev_insn);
5137 NEXT_INSN (prev_insn) = nop;
5138 PREV_INSN (nop) = prev_insn;
5140 PREV_INSN (note) = nop;
5141 NEXT_INSN (note) = next_insn;
5143 NEXT_INSN (nop) = note;
5144 PREV_INSN (next_insn) = note;
5146 BB_END (prev_bb) = nop;
5147 BLOCK_FOR_INSN (nop) = prev_bb;
5150 /* Prepare a place to insert the chosen expression on BND. */
5152 prepare_place_to_insert (bnd_t bnd)
5154 insn_t place_to_insert;
5156 /* Init place_to_insert before calling move_op, as the later
5157 can possibly remove BND_TO (bnd). */
5158 if (/* If this is not the first insn scheduled. */
5161 /* Add it after last scheduled. */
5162 place_to_insert = ILIST_INSN (BND_PTR (bnd));
5163 if (DEBUG_INSN_P (place_to_insert))
5165 ilist_t l = BND_PTR (bnd);
5166 while ((l = ILIST_NEXT (l)) &&
5167 DEBUG_INSN_P (ILIST_INSN (l)))
5170 place_to_insert = NULL;
5174 place_to_insert = NULL;
5176 if (!place_to_insert)
5178 /* Add it before BND_TO. The difference is in the
5179 basic block, where INSN will be added. */
5180 place_to_insert = get_nop_from_pool (BND_TO (bnd));
5181 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
5182 == BLOCK_FOR_INSN (BND_TO (bnd)));
5185 return place_to_insert;
5188 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5189 Return the expression to emit in C_EXPR. */
5191 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5192 av_set_t expr_seq, expr_t c_expr)
5194 bool b, should_move;
5197 int n_bookkeeping_copies_before_moveop;
5199 /* Make a move. This call will remove the original operation,
5200 insert all necessary bookkeeping instructions and update the
5201 data sets. After that all we have to do is add the operation
5202 at before BND_TO (BND). */
5203 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5204 max_uid_before_move_op = get_max_uid ();
5205 bitmap_clear (current_copies);
5206 bitmap_clear (current_originators);
5208 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5209 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5211 /* We should be able to find the expression we've chosen for
5215 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5216 stat_insns_needed_bookkeeping++;
5218 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5223 /* We allocate these bitmaps lazily. */
5224 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5225 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5227 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5228 current_originators);
5230 /* Transitively add all originators' originators. */
5231 EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi)
5232 if (INSN_ORIGINATORS_BY_UID (uid))
5233 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid),
5234 INSN_ORIGINATORS_BY_UID (uid));
5241 /* Debug a DFA state as an array of bytes. */
5243 debug_state (state_t state)
5246 unsigned int i, size = dfa_state_size;
5248 sel_print ("state (%u):", size);
5249 for (i = 0, p = (unsigned char *) state; i < size; i++)
5250 sel_print (" %d", p[i]);
5254 /* Advance state on FENCE with INSN. Return true if INSN is
5255 an ASM, and we should advance state once more. */
5257 advance_state_on_fence (fence_t fence, insn_t insn)
5261 if (recog_memoized (insn) >= 0)
5264 state_t temp_state = alloca (dfa_state_size);
5266 gcc_assert (!INSN_ASM_P (insn));
5269 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5270 res = state_transition (FENCE_STATE (fence), insn);
5271 gcc_assert (res < 0);
5273 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5275 FENCE_ISSUED_INSNS (fence)++;
5277 /* We should never issue more than issue_rate insns. */
5278 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5284 /* This could be an ASM insn which we'd like to schedule
5285 on the next cycle. */
5286 asm_p = INSN_ASM_P (insn);
5287 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5288 advance_one_cycle (fence);
5291 if (sched_verbose >= 2)
5292 debug_state (FENCE_STATE (fence));
5293 if (!DEBUG_INSN_P (insn))
5294 FENCE_STARTS_CYCLE_P (fence) = 0;
5295 FENCE_ISSUE_MORE (fence) = can_issue_more;
5299 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5300 is nonzero if we need to stall after issuing INSN. */
5302 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5306 /* First, reflect that something is scheduled on this fence. */
5307 asm_p = advance_state_on_fence (fence, insn);
5308 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5309 VEC_safe_push (rtx, gc, FENCE_EXECUTING_INSNS (fence), insn);
5310 if (SCHED_GROUP_P (insn))
5312 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5313 SCHED_GROUP_P (insn) = 0;
5316 FENCE_SCHED_NEXT (fence) = NULL_RTX;
5317 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5318 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5320 /* Set instruction scheduling info. This will be used in bundling,
5321 pipelining, tick computations etc. */
5322 ++INSN_SCHED_TIMES (insn);
5323 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5324 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5325 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5326 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5328 /* This does not account for adjust_cost hooks, just add the biggest
5329 constant the hook may add to the latency. TODO: make this
5330 a target dependent constant. */
5331 INSN_READY_CYCLE (insn)
5332 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5334 : maximal_insn_latency (insn) + 1);
5336 /* Change these fields last, as they're used above. */
5337 FENCE_AFTER_STALL_P (fence) = 0;
5338 if (asm_p || need_stall)
5339 advance_one_cycle (fence);
5341 /* Indicate that we've scheduled something on this fence. */
5342 FENCE_SCHEDULED_P (fence) = true;
5343 scheduled_something_on_previous_fence = true;
5345 /* Print debug information when insn's fields are updated. */
5346 if (sched_verbose >= 2)
5348 sel_print ("Scheduling insn: ");
5349 dump_insn_1 (insn, 1);
5354 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5355 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5358 update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp,
5359 blist_t *bnds_tailp)
5364 advance_deps_context (BND_DC (bnd), insn);
5365 FOR_EACH_SUCC_1 (succ, si, insn,
5366 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5368 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5370 ilist_add (&ptr, insn);
5372 if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn)
5373 && is_ineligible_successor (succ, ptr))
5379 if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn))
5381 if (sched_verbose >= 9)
5382 sel_print ("Updating fence insn from %i to %i\n",
5383 INSN_UID (insn), INSN_UID (succ));
5384 FENCE_INSN (fence) = succ;
5386 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5387 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5390 blist_remove (bndsp);
5394 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5396 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5399 expr_t c_expr = XALLOCA (expr_def);
5400 insn_t place_to_insert;
5404 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5406 /* In case of scheduling a jump skipping some other instructions,
5407 prepare CFG. After this, jump is at the boundary and can be
5408 scheduled as usual insn by MOVE_OP. */
5409 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5411 insn = EXPR_INSN_RTX (expr_vliw);
5413 /* Speculative jumps are not handled. */
5414 if (insn != BND_TO (bnd)
5415 && !sel_insn_is_speculation_check (insn))
5416 move_cond_jump (insn, bnd);
5419 /* Find a place for C_EXPR to schedule. */
5420 place_to_insert = prepare_place_to_insert (bnd);
5421 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5422 clear_expr (c_expr);
5424 /* Add the instruction. The corner case to care about is when
5425 the expr_seq set has more than one expr, and we chose the one that
5426 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5427 we can't use it. Generate the new vinsn. */
5428 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5432 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5433 change_vinsn_in_expr (expr_vliw, vinsn_new);
5434 should_move = false;
5437 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5439 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5442 /* Return the nops generated for preserving of data sets back
5444 if (INSN_NOP_P (place_to_insert))
5445 return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn));
5446 remove_temp_moveop_nops (!DEBUG_INSN_P (insn));
5448 av_set_clear (&expr_seq);
5450 /* Save the expression scheduled so to reset target availability if we'll
5451 meet it later on the same fence. */
5452 if (EXPR_WAS_RENAMED (expr_vliw))
5453 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5455 /* Check that the recent movement didn't destroyed loop
5457 gcc_assert (!pipelining_p
5458 || current_loop_nest == NULL
5459 || loop_latch_edge (current_loop_nest));
5463 /* Stall for N cycles on FENCE. */
5465 stall_for_cycles (fence_t fence, int n)
5469 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5471 advance_one_cycle (fence);
5473 FENCE_AFTER_STALL_P (fence) = 1;
5476 /* Gather a parallel group of insns at FENCE and assign their seqno
5477 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5478 list for later recalculation of seqnos. */
5480 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5482 blist_t bnds = NULL, *bnds_tailp;
5483 av_set_t av_vliw = NULL;
5484 insn_t insn = FENCE_INSN (fence);
5486 if (sched_verbose >= 2)
5487 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5488 INSN_UID (insn), FENCE_CYCLE (fence));
5490 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5491 bnds_tailp = &BLIST_NEXT (bnds);
5492 set_target_context (FENCE_TC (fence));
5493 can_issue_more = FENCE_ISSUE_MORE (fence);
5494 target_bb = INSN_BB (insn);
5496 /* Do while we can add any operation to the current group. */
5499 blist_t *bnds_tailp1, *bndsp;
5502 int was_stall = 0, scheduled_insns = 0, stall_iterations = 0;
5503 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5504 int max_stall = pipelining_p ? 1 : 3;
5505 bool last_insn_was_debug = false;
5506 bool was_debug_bb_end_p = false;
5508 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5509 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5510 remove_insns_for_debug (bnds, &av_vliw);
5512 /* Return early if we have nothing to schedule. */
5513 if (av_vliw == NULL)
5516 /* Choose the best expression and, if needed, destination register
5520 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5521 if (!expr_vliw && need_stall)
5523 /* All expressions required a stall. Do not recompute av sets
5524 as we'll get the same answer (modulo the insns between
5525 the fence and its boundary, which will not be available for
5527 gcc_assert (! expr_vliw && stall_iterations < 2);
5529 /* If we are going to stall for too long, break to recompute av
5530 sets and bring more insns for pipelining. */
5531 if (need_stall <= 3)
5532 stall_for_cycles (fence, need_stall);
5535 stall_for_cycles (fence, 1);
5540 while (! expr_vliw && need_stall);
5542 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5545 av_set_clear (&av_vliw);
5550 bnds_tailp1 = bnds_tailp;
5553 /* This code will be executed only once until we'd have several
5554 boundaries per fence. */
5556 bnd_t bnd = BLIST_BND (*bndsp);
5558 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5560 bndsp = &BLIST_NEXT (*bndsp);
5564 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5565 last_insn_was_debug = DEBUG_INSN_P (insn);
5566 if (last_insn_was_debug)
5567 was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn));
5568 update_fence_and_insn (fence, insn, need_stall);
5569 bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp);
5571 /* Add insn to the list of scheduled on this cycle instructions. */
5572 ilist_add (*scheduled_insns_tailpp, insn);
5573 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5575 while (*bndsp != *bnds_tailp1);
5577 av_set_clear (&av_vliw);
5578 if (!last_insn_was_debug)
5581 /* We currently support information about candidate blocks only for
5582 one 'target_bb' block. Hence we can't schedule after jump insn,
5583 as this will bring two boundaries and, hence, necessity to handle
5584 information for two or more blocks concurrently. */
5585 if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn))
5587 && (was_stall >= max_stall
5588 || scheduled_insns >= max_insns)))
5593 gcc_assert (!FENCE_BNDS (fence));
5595 /* Update boundaries of the FENCE. */
5598 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5602 insn = ILIST_INSN (ptr);
5604 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5605 ilist_add (&FENCE_BNDS (fence), insn);
5608 blist_remove (&bnds);
5611 /* Update target context on the fence. */
5612 reset_target_context (FENCE_TC (fence), false);
5615 /* All exprs in ORIG_OPS must have the same destination register or memory.
5616 Return that destination. */
5618 get_dest_from_orig_ops (av_set_t orig_ops)
5620 rtx dest = NULL_RTX;
5621 av_set_iterator av_it;
5623 bool first_p = true;
5625 FOR_EACH_EXPR (expr, av_it, orig_ops)
5627 rtx x = EXPR_LHS (expr);
5635 gcc_assert (dest == x
5636 || (dest != NULL_RTX && x != NULL_RTX
5637 && rtx_equal_p (dest, x)));
5643 /* Update data sets for the bookkeeping block and record those expressions
5644 which become no longer available after inserting this bookkeeping. */
5646 update_and_record_unavailable_insns (basic_block book_block)
5649 av_set_t old_av_set = NULL;
5651 rtx bb_end = sel_bb_end (book_block);
5653 /* First, get correct liveness in the bookkeeping block. The problem is
5654 the range between the bookeeping insn and the end of block. */
5655 update_liveness_on_insn (bb_end);
5656 if (control_flow_insn_p (bb_end))
5657 update_liveness_on_insn (PREV_INSN (bb_end));
5659 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5660 fence above, where we may choose to schedule an insn which is
5661 actually blocked from moving up with the bookkeeping we create here. */
5662 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5664 old_av_set = av_set_copy (BB_AV_SET (book_block));
5665 update_data_sets (sel_bb_head (book_block));
5667 /* Traverse all the expressions in the old av_set and check whether
5668 CUR_EXPR is in new AV_SET. */
5669 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5671 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5672 EXPR_VINSN (cur_expr));
5675 /* In this case, we can just turn off the E_T_A bit, but we can't
5676 represent this information with the current vector. */
5677 || EXPR_TARGET_AVAILABLE (new_expr)
5678 != EXPR_TARGET_AVAILABLE (cur_expr))
5679 /* Unfortunately, the below code could be also fired up on
5681 FIXME: add an example of how this could happen. */
5682 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5685 av_set_clear (&old_av_set);
5689 /* The main effect of this function is that sparams->c_expr is merged
5690 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5691 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5692 lparams->c_expr_merged is copied back to sparams->c_expr after all
5693 successors has been traversed. lparams->c_expr_local is an expr allocated
5694 on stack in the caller function, and is used if there is more than one
5697 SUCC is one of the SUCCS_NORMAL successors of INSN,
5698 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5699 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5701 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5702 insn_t succ ATTRIBUTE_UNUSED,
5703 int moveop_drv_call_res,
5704 cmpd_local_params_p lparams, void *static_params)
5706 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5708 /* Nothing to do, if original expr wasn't found below. */
5709 if (moveop_drv_call_res != 1)
5712 /* If this is a first successor. */
5713 if (!lparams->c_expr_merged)
5715 lparams->c_expr_merged = sparams->c_expr;
5716 sparams->c_expr = lparams->c_expr_local;
5720 /* We must merge all found expressions to get reasonable
5721 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5722 do so then we can first find the expr with epsilon
5723 speculation success probability and only then with the
5724 good probability. As a result the insn will get epsilon
5725 probability and will never be scheduled because of
5726 weakness_cutoff in find_best_expr.
5728 We call merge_expr_data here instead of merge_expr
5729 because due to speculation C_EXPR and X may have the
5730 same insns with different speculation types. And as of
5731 now such insns are considered non-equal.
5733 However, EXPR_SCHED_TIMES is different -- we must get
5734 SCHED_TIMES from a real insn, not a bookkeeping copy.
5735 We force this here. Instead, we may consider merging
5736 SCHED_TIMES to the maximum instead of minimum in the
5738 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5740 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5741 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5742 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5744 clear_expr (sparams->c_expr);
5748 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5750 SUCC is one of the SUCCS_NORMAL successors of INSN,
5751 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5752 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5753 STATIC_PARAMS contain USED_REGS set. */
5755 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5756 int moveop_drv_call_res,
5757 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5758 void *static_params)
5761 fur_static_params_p sparams = (fur_static_params_p) static_params;
5763 /* Here we compute live regsets only for branches that do not lie
5764 on the code motion paths. These branches correspond to value
5765 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5766 for such branches code_motion_path_driver is not called. */
5767 if (moveop_drv_call_res != 0)
5770 /* Mark all registers that do not meet the following condition:
5771 (3) not live on the other path of any conditional branch
5772 that is passed by the operation, in case original
5773 operations are not present on both paths of the
5774 conditional branch. */
5775 succ_live = compute_live (succ);
5776 IOR_REG_SET (sparams->used_regs, succ_live);
5779 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5782 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5784 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5786 sp->c_expr = lp->c_expr_merged;
5789 /* Track bookkeeping copies created, insns scheduled, and blocks for
5790 rescheduling when INSN is found by move_op. */
5792 track_scheduled_insns_and_blocks (rtx insn)
5794 /* Even if this insn can be a copy that will be removed during current move_op,
5795 we still need to count it as an originator. */
5796 bitmap_set_bit (current_originators, INSN_UID (insn));
5798 if (!bitmap_bit_p (current_copies, INSN_UID (insn)))
5800 /* Note that original block needs to be rescheduled, as we pulled an
5801 instruction out of it. */
5802 if (INSN_SCHED_TIMES (insn) > 0)
5803 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5804 else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn))
5805 num_insns_scheduled++;
5808 bitmap_clear_bit (current_copies, INSN_UID (insn));
5810 /* For instructions we must immediately remove insn from the
5811 stream, so subsequent update_data_sets () won't include this
5813 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5814 if (INSN_UID (insn) > max_uid_before_move_op)
5815 stat_bookkeeping_copies--;
5818 /* Emit a register-register copy for INSN if needed. Return true if
5819 emitted one. PARAMS is the move_op static parameters. */
5821 maybe_emit_renaming_copy (rtx insn,
5822 moveop_static_params_p params)
5824 bool insn_emitted = false;
5827 /* Bail out early when expression can not be renamed at all. */
5828 if (!EXPR_SEPARABLE_P (params->c_expr))
5831 cur_reg = expr_dest_reg (params->c_expr);
5832 gcc_assert (cur_reg && params->dest && REG_P (params->dest));
5834 /* If original operation has expr and the register chosen for
5835 that expr is not original operation's dest reg, substitute
5836 operation's right hand side with the register chosen. */
5837 if (REGNO (params->dest) != REGNO (cur_reg))
5839 insn_t reg_move_insn, reg_move_insn_rtx;
5841 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5843 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5847 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5848 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5850 insn_emitted = true;
5851 params->was_renamed = true;
5854 return insn_emitted;
5857 /* Emit a speculative check for INSN speculated as EXPR if needed.
5858 Return true if we've emitted one. PARAMS is the move_op static
5861 maybe_emit_speculative_check (rtx insn, expr_t expr,
5862 moveop_static_params_p params)
5864 bool insn_emitted = false;
5868 check_ds = get_spec_check_type_for_insn (insn, expr);
5871 /* A speculation check should be inserted. */
5872 x = create_speculation_check (params->c_expr, check_ds, insn);
5873 insn_emitted = true;
5877 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5881 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5882 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5883 return insn_emitted;
5886 /* Handle transformations that leave an insn in place of original
5887 insn such as renaming/speculation. Return true if one of such
5888 transformations actually happened, and we have emitted this insn. */
5890 handle_emitting_transformations (rtx insn, expr_t expr,
5891 moveop_static_params_p params)
5893 bool insn_emitted = false;
5895 insn_emitted = maybe_emit_renaming_copy (insn, params);
5896 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5898 return insn_emitted;
5901 /* If INSN is the only insn in the basic block (not counting JUMP,
5902 which may be a jump to next insn, and DEBUG_INSNs), we want to
5903 leave a NOP there till the return to fill_insns. */
5906 need_nop_to_preserve_insn_bb (rtx insn)
5908 insn_t bb_head, bb_end, bb_next, in_next;
5909 basic_block bb = BLOCK_FOR_INSN (insn);
5911 bb_head = sel_bb_head (bb);
5912 bb_end = sel_bb_end (bb);
5914 if (bb_head == bb_end)
5917 while (bb_head != bb_end && DEBUG_INSN_P (bb_head))
5918 bb_head = NEXT_INSN (bb_head);
5920 if (bb_head == bb_end)
5923 while (bb_head != bb_end && DEBUG_INSN_P (bb_end))
5924 bb_end = PREV_INSN (bb_end);
5926 if (bb_head == bb_end)
5929 bb_next = NEXT_INSN (bb_head);
5930 while (bb_next != bb_end && DEBUG_INSN_P (bb_next))
5931 bb_next = NEXT_INSN (bb_next);
5933 if (bb_next == bb_end && JUMP_P (bb_end))
5936 in_next = NEXT_INSN (insn);
5937 while (DEBUG_INSN_P (in_next))
5938 in_next = NEXT_INSN (in_next);
5940 if (IN_CURRENT_FENCE_P (in_next))
5946 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5947 is not removed but reused when INSN is re-emitted. */
5949 remove_insn_from_stream (rtx insn, bool only_disconnect)
5951 /* If there's only one insn in the BB, make sure that a nop is
5952 inserted into it, so the basic block won't disappear when we'll
5953 delete INSN below with sel_remove_insn. It should also survive
5954 till the return to fill_insns. */
5955 if (need_nop_to_preserve_insn_bb (insn))
5957 insn_t nop = get_nop_from_pool (insn);
5958 gcc_assert (INSN_NOP_P (nop));
5959 VEC_safe_push (insn_t, heap, vec_temp_moveop_nops, nop);
5962 sel_remove_insn (insn, only_disconnect, false);
5965 /* This function is called when original expr is found.
5966 INSN - current insn traversed, EXPR - the corresponding expr found.
5967 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5968 is static parameters of move_op. */
5970 move_op_orig_expr_found (insn_t insn, expr_t expr,
5971 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5972 void *static_params)
5974 bool only_disconnect, insn_emitted;
5975 moveop_static_params_p params = (moveop_static_params_p) static_params;
5977 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
5978 track_scheduled_insns_and_blocks (insn);
5979 insn_emitted = handle_emitting_transformations (insn, expr, params);
5980 only_disconnect = (params->uid == INSN_UID (insn)
5981 && ! insn_emitted && ! EXPR_WAS_CHANGED (expr));
5983 /* Mark that we've disconnected an insn. */
5984 if (only_disconnect)
5986 remove_insn_from_stream (insn, only_disconnect);
5989 /* The function is called when original expr is found.
5990 INSN - current insn traversed, EXPR - the corresponding expr found,
5991 crosses_call and original_insns in STATIC_PARAMS are updated. */
5993 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
5994 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5995 void *static_params)
5997 fur_static_params_p params = (fur_static_params_p) static_params;
6001 params->crosses_call = true;
6003 def_list_add (params->original_insns, insn, params->crosses_call);
6005 /* Mark the registers that do not meet the following condition:
6006 (2) not among the live registers of the point
6007 immediately following the first original operation on
6008 a given downward path, except for the original target
6009 register of the operation. */
6010 tmp = get_clear_regset_from_pool ();
6011 compute_live_below_insn (insn, tmp);
6012 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
6013 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
6014 IOR_REG_SET (params->used_regs, tmp);
6015 return_regset_to_pool (tmp);
6017 /* (*1) We need to add to USED_REGS registers that are read by
6018 INSN's lhs. This may lead to choosing wrong src register.
6019 E.g. (scheduling const expr enabled):
6021 429: ax=0x0 <- Can't use AX for this expr (0x0)
6028 /* FIXME: see comment above and enable MEM_P
6029 in vinsn_separable_p. */
6030 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
6031 || !MEM_P (INSN_LHS (insn)));
6034 /* This function is called on the ascending pass, before returning from
6035 current basic block. */
6037 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
6038 void *static_params)
6040 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6041 basic_block book_block = NULL;
6043 /* When we have removed the boundary insn for scheduling, which also
6044 happened to be the end insn in its bb, we don't need to update sets. */
6045 if (!lparams->removed_last_insn
6047 && sel_bb_head_p (insn))
6049 /* We should generate bookkeeping code only if we are not at the
6050 top level of the move_op. */
6051 if (sel_num_cfg_preds_gt_1 (insn))
6052 book_block = generate_bookkeeping_insn (sparams->c_expr,
6053 lparams->e1, lparams->e2);
6054 /* Update data sets for the current insn. */
6055 update_data_sets (insn);
6058 /* If bookkeeping code was inserted, we need to update av sets of basic
6059 block that received bookkeeping. After generation of bookkeeping insn,
6060 bookkeeping block does not contain valid av set because we are not following
6061 the original algorithm in every detail with regards to e.g. renaming
6062 simple reg-reg copies. Consider example:
6064 bookkeeping block scheduling fence
6074 We try to schedule insn "r1 := r3" on the current
6075 scheduling fence. Also, note that av set of bookkeeping block
6076 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6077 been scheduled, the CFG is as follows:
6080 bookkeeping block scheduling fence
6090 Here, insn "r1 := r3" was scheduled at the current scheduling point
6091 and bookkeeping code was generated at the bookeeping block. This
6092 way insn "r1 := r2" is no longer available as a whole instruction
6093 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6094 This situation is handled by calling update_data_sets.
6096 Since update_data_sets is called only on the bookkeeping block, and
6097 it also may have predecessors with av_sets, containing instructions that
6098 are no longer available, we save all such expressions that become
6099 unavailable during data sets update on the bookkeeping block in
6100 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6101 expressions for scheduling. This allows us to avoid recomputation of
6102 av_sets outside the code motion path. */
6105 update_and_record_unavailable_insns (book_block);
6107 /* If INSN was previously marked for deletion, it's time to do it. */
6108 if (lparams->removed_last_insn)
6109 insn = PREV_INSN (insn);
6111 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6112 kill a block with a single nop in which the insn should be emitted. */
6114 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
6117 /* This function is called on the ascending pass, before returning from the
6118 current basic block. */
6120 fur_at_first_insn (insn_t insn,
6121 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6122 void *static_params ATTRIBUTE_UNUSED)
6124 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
6125 || AV_LEVEL (insn) == -1);
6128 /* Called on the backward stage of recursion to call moveup_expr for insn
6129 and sparams->c_expr. */
6131 move_op_ascend (insn_t insn, void *static_params)
6133 enum MOVEUP_EXPR_CODE res;
6134 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6136 if (! INSN_NOP_P (insn))
6138 res = moveup_expr_cached (sparams->c_expr, insn, false);
6139 gcc_assert (res != MOVEUP_EXPR_NULL);
6142 /* Update liveness for this insn as it was invalidated. */
6143 update_liveness_on_insn (insn);
6146 /* This function is called on enter to the basic block.
6147 Returns TRUE if this block already have been visited and
6148 code_motion_path_driver should return 1, FALSE otherwise. */
6150 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
6151 void *static_params, bool visited_p)
6153 fur_static_params_p sparams = (fur_static_params_p) static_params;
6157 /* If we have found something below this block, there should be at
6158 least one insn in ORIGINAL_INSNS. */
6159 gcc_assert (*sparams->original_insns);
6161 /* Adjust CROSSES_CALL, since we may have come to this block along
6163 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
6164 |= sparams->crosses_call;
6167 local_params->old_original_insns = *sparams->original_insns;
6172 /* Same as above but for move_op. */
6174 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
6175 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
6176 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
6183 /* This function is called while descending current basic block if current
6184 insn is not the original EXPR we're searching for.
6186 Return value: FALSE, if code_motion_path_driver should perform a local
6187 cleanup and return 0 itself;
6188 TRUE, if code_motion_path_driver should continue. */
6190 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
6191 void *static_params)
6193 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6195 #ifdef ENABLE_CHECKING
6196 sparams->failed_insn = insn;
6199 /* If we're scheduling separate expr, in order to generate correct code
6200 we need to stop the search at bookkeeping code generated with the
6201 same destination register or memory. */
6202 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
6207 /* This function is called while descending current basic block if current
6208 insn is not the original EXPR we're searching for.
6210 Return value: TRUE (code_motion_path_driver should continue). */
6212 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
6216 av_set_iterator avi;
6217 fur_static_params_p sparams = (fur_static_params_p) static_params;
6220 sparams->crosses_call = true;
6221 else if (DEBUG_INSN_P (insn))
6224 /* If current insn we are looking at cannot be executed together
6225 with original insn, then we can skip it safely.
6227 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6228 INSN = (!p6) r14 = r14 + 1;
6230 Here we can schedule ORIG_OP with lhs = r14, though only
6231 looking at the set of used and set registers of INSN we must
6232 forbid it. So, add set/used in INSN registers to the
6233 untouchable set only if there is an insn in ORIG_OPS that can
6236 FOR_EACH_EXPR (r, avi, orig_ops)
6237 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
6243 /* Mark all registers that do not meet the following condition:
6244 (1) Not set or read on any path from xi to an instance of the
6245 original operation. */
6248 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6249 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6250 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6256 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6257 struct code_motion_path_driver_info_def move_op_hooks = {
6259 move_op_orig_expr_found,
6260 move_op_orig_expr_not_found,
6261 move_op_merge_succs,
6262 move_op_after_merge_succs,
6264 move_op_at_first_insn,
6269 /* Hooks and data to perform find_used_regs operations
6270 with code_motion_path_driver. */
6271 struct code_motion_path_driver_info_def fur_hooks = {
6273 fur_orig_expr_found,
6274 fur_orig_expr_not_found,
6276 NULL, /* fur_after_merge_succs */
6277 NULL, /* fur_ascend */
6283 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6284 code_motion_path_driver is called recursively. Original operation
6285 was found at least on one path that is starting with one of INSN's
6286 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6287 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6288 of either move_op or find_used_regs depending on the caller.
6290 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6291 know for sure at this point. */
6293 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6294 ilist_t path, void *static_params)
6297 succ_iterator succ_i;
6303 struct cmpd_local_params lparams;
6306 lparams.c_expr_local = &_x;
6307 lparams.c_expr_merged = NULL;
6309 /* We need to process only NORMAL succs for move_op, and collect live
6310 registers from ALL branches (including those leading out of the
6311 region) for find_used_regs.
6313 In move_op, there can be a case when insn's bb number has changed
6314 due to created bookkeeping. This happens very rare, as we need to
6315 move expression from the beginning to the end of the same block.
6316 Rescan successors in this case. */
6319 bb = BLOCK_FOR_INSN (insn);
6320 old_index = bb->index;
6321 old_succs = EDGE_COUNT (bb->succs);
6323 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6327 lparams.e1 = succ_i.e1;
6328 lparams.e2 = succ_i.e2;
6330 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6332 if (succ_i.current_flags == SUCCS_NORMAL)
6333 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6338 /* Merge c_expres found or unify live register sets from different
6340 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6344 else if (b == -1 && res != 1)
6347 /* We have simplified the control flow below this point. In this case,
6348 the iterator becomes invalid. We need to try again. */
6349 if (BLOCK_FOR_INSN (insn)->index != old_index
6350 || EDGE_COUNT (bb->succs) != old_succs)
6354 #ifdef ENABLE_CHECKING
6355 /* Here, RES==1 if original expr was found at least for one of the
6356 successors. After the loop, RES may happen to have zero value
6357 only if at some point the expr searched is present in av_set, but is
6358 not found below. In most cases, this situation is an error.
6359 The exception is when the original operation is blocked by
6360 bookkeeping generated for another fence or for another path in current
6362 gcc_assert (res == 1
6364 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops,
6369 /* Merge data, clean up, etc. */
6370 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6371 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6377 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6378 is the pointer to the av set with expressions we were looking for,
6379 PATH_P is the pointer to the traversed path. */
6381 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6383 ilist_remove (path_p);
6384 av_set_clear (orig_ops_p);
6387 /* The driver function that implements move_op or find_used_regs
6388 functionality dependent whether code_motion_path_driver_INFO is set to
6389 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6390 of code (CFG traversal etc) that are shared among both functions. INSN
6391 is the insn we're starting the search from, ORIG_OPS are the expressions
6392 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6393 parameters of the driver, and STATIC_PARAMS are static parameters of
6396 Returns whether original instructions were found. Note that top-level
6397 code_motion_path_driver always returns true. */
6399 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6400 cmpd_local_params_p local_params_in,
6401 void *static_params)
6404 basic_block bb = BLOCK_FOR_INSN (insn);
6405 insn_t first_insn, bb_tail, before_first;
6406 bool removed_last_insn = false;
6408 if (sched_verbose >= 6)
6410 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6413 dump_av_set (orig_ops);
6417 gcc_assert (orig_ops);
6419 /* If no original operations exist below this insn, return immediately. */
6420 if (is_ineligible_successor (insn, path))
6422 if (sched_verbose >= 6)
6423 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6427 /* The block can have invalid av set, in which case it was created earlier
6428 during move_op. Return immediately. */
6429 if (sel_bb_head_p (insn))
6431 if (! AV_SET_VALID_P (insn))
6433 if (sched_verbose >= 6)
6434 sel_print ("Returned from block %d as it had invalid av set\n",
6439 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6441 /* We have already found an original operation on this branch, do not
6442 go any further and just return TRUE here. If we don't stop here,
6443 function can have exponential behaviour even on the small code
6444 with many different paths (e.g. with data speculation and
6445 recovery blocks). */
6446 if (sched_verbose >= 6)
6447 sel_print ("Block %d already visited in this traversal\n", bb->index);
6448 if (code_motion_path_driver_info->on_enter)
6449 return code_motion_path_driver_info->on_enter (insn,
6456 if (code_motion_path_driver_info->on_enter)
6457 code_motion_path_driver_info->on_enter (insn, local_params_in,
6458 static_params, false);
6459 orig_ops = av_set_copy (orig_ops);
6461 /* Filter the orig_ops set. */
6462 if (AV_SET_VALID_P (insn))
6463 av_set_intersect (&orig_ops, AV_SET (insn));
6465 /* If no more original ops, return immediately. */
6468 if (sched_verbose >= 6)
6469 sel_print ("No intersection with av set of block %d\n", bb->index);
6473 /* For non-speculative insns we have to leave only one form of the
6474 original operation, because if we don't, we may end up with
6475 different C_EXPRes and, consequently, with bookkeepings for different
6476 expression forms along the same code motion path. That may lead to
6477 generation of incorrect code. So for each code motion we stick to
6478 the single form of the instruction, except for speculative insns
6479 which we need to keep in different forms with all speculation
6481 av_set_leave_one_nonspec (&orig_ops);
6483 /* It is not possible that all ORIG_OPS are filtered out. */
6484 gcc_assert (orig_ops);
6486 /* It is enough to place only heads and tails of visited basic blocks into
6488 ilist_add (&path, insn);
6490 bb_tail = sel_bb_end (bb);
6492 /* Descend the basic block in search of the original expr; this part
6493 corresponds to the part of the original move_op procedure executed
6494 before the recursive call. */
6497 /* Look at the insn and decide if it could be an ancestor of currently
6498 scheduling operation. If it is so, then the insn "dest = op" could
6499 either be replaced with "dest = reg", because REG now holds the result
6500 of OP, or just removed, if we've scheduled the insn as a whole.
6502 If this insn doesn't contain currently scheduling OP, then proceed
6503 with searching and look at its successors. Operations we're searching
6504 for could have changed when moving up through this insn via
6505 substituting. In this case, perform unsubstitution on them first.
6507 When traversing the DAG below this insn is finished, insert
6508 bookkeeping code, if the insn is a joint point, and remove
6511 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6514 insn_t last_insn = PREV_INSN (insn);
6516 /* We have found the original operation. */
6517 if (sched_verbose >= 6)
6518 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6520 code_motion_path_driver_info->orig_expr_found
6521 (insn, expr, local_params_in, static_params);
6523 /* Step back, so on the way back we'll start traversing from the
6524 previous insn (or we'll see that it's bb_note and skip that
6526 if (insn == first_insn)
6528 first_insn = NEXT_INSN (last_insn);
6529 removed_last_insn = sel_bb_end_p (last_insn);
6536 /* We haven't found the original expr, continue descending the basic
6538 if (code_motion_path_driver_info->orig_expr_not_found
6539 (insn, orig_ops, static_params))
6541 /* Av set ops could have been changed when moving through this
6542 insn. To find them below it, we have to un-substitute them. */
6543 undo_transformations (&orig_ops, insn);
6547 /* Clean up and return, if the hook tells us to do so. It may
6548 happen if we've encountered the previously created
6550 code_motion_path_driver_cleanup (&orig_ops, &path);
6554 gcc_assert (orig_ops);
6557 /* Stop at insn if we got to the end of BB. */
6558 if (insn == bb_tail)
6561 insn = NEXT_INSN (insn);
6564 /* Here INSN either points to the insn before the original insn (may be
6565 bb_note, if original insn was a bb_head) or to the bb_end. */
6570 gcc_assert (insn == sel_bb_end (bb));
6572 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6573 it's already in PATH then). */
6574 if (insn != first_insn)
6575 ilist_add (&path, insn);
6577 /* Process_successors should be able to find at least one
6578 successor for which code_motion_path_driver returns TRUE. */
6579 res = code_motion_process_successors (insn, orig_ops,
6580 path, static_params);
6582 /* Remove bb tail from path. */
6583 if (insn != first_insn)
6584 ilist_remove (&path);
6588 /* This is the case when one of the original expr is no longer available
6589 due to bookkeeping created on this branch with the same register.
6590 In the original algorithm, which doesn't have update_data_sets call
6591 on a bookkeeping block, it would simply result in returning
6592 FALSE when we've encountered a previously generated bookkeeping
6593 insn in moveop_orig_expr_not_found. */
6594 code_motion_path_driver_cleanup (&orig_ops, &path);
6599 /* Don't need it any more. */
6600 av_set_clear (&orig_ops);
6602 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6603 the beginning of the basic block. */
6604 before_first = PREV_INSN (first_insn);
6605 while (insn != before_first)
6607 if (code_motion_path_driver_info->ascend)
6608 code_motion_path_driver_info->ascend (insn, static_params);
6610 insn = PREV_INSN (insn);
6613 /* Now we're at the bb head. */
6615 ilist_remove (&path);
6616 local_params_in->removed_last_insn = removed_last_insn;
6617 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6619 /* This should be the very last operation as at bb head we could change
6620 the numbering by creating bookkeeping blocks. */
6621 if (removed_last_insn)
6622 insn = PREV_INSN (insn);
6623 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6627 /* Move up the operations from ORIG_OPS set traversing the dag starting
6628 from INSN. PATH represents the edges traversed so far.
6629 DEST is the register chosen for scheduling the current expr. Insert
6630 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6631 C_EXPR is how it looks like at the given cfg point.
6632 Set *SHOULD_MOVE to indicate whether we have only disconnected
6633 one of the insns found.
6635 Returns whether original instructions were found, which is asserted
6636 to be true in the caller. */
6638 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6639 rtx dest, expr_t c_expr, bool *should_move)
6641 struct moveop_static_params sparams;
6642 struct cmpd_local_params lparams;
6645 /* Init params for code_motion_path_driver. */
6646 sparams.dest = dest;
6647 sparams.c_expr = c_expr;
6648 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6649 #ifdef ENABLE_CHECKING
6650 sparams.failed_insn = NULL;
6652 sparams.was_renamed = false;
6655 /* We haven't visited any blocks yet. */
6656 bitmap_clear (code_motion_visited_blocks);
6658 /* Set appropriate hooks and data. */
6659 code_motion_path_driver_info = &move_op_hooks;
6660 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6662 if (sparams.was_renamed)
6663 EXPR_WAS_RENAMED (expr_vliw) = true;
6665 *should_move = (sparams.uid == -1);
6671 /* Functions that work with regions. */
6673 /* Current number of seqno used in init_seqno and init_seqno_1. */
6674 static int cur_seqno;
6676 /* A helper for init_seqno. Traverse the region starting from BB and
6677 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6678 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6680 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6682 int bbi = BLOCK_TO_BB (bb->index);
6683 insn_t insn, note = bb_note (bb);
6687 SET_BIT (visited_bbs, bbi);
6688 if (blocks_to_reschedule)
6689 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6691 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6692 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6694 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6695 int succ_bbi = BLOCK_TO_BB (succ->index);
6697 gcc_assert (in_current_region_p (succ));
6699 if (!TEST_BIT (visited_bbs, succ_bbi))
6701 gcc_assert (succ_bbi > bbi);
6703 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6707 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6708 INSN_SEQNO (insn) = cur_seqno--;
6711 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6712 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6713 which we're rescheduling when pipelining, FROM is the block where
6714 traversing region begins (it may not be the head of the region when
6715 pipelining, but the head of the loop instead).
6717 Returns the maximal seqno found. */
6719 init_seqno (int number_of_insns, bitmap blocks_to_reschedule, basic_block from)
6721 sbitmap visited_bbs;
6725 visited_bbs = sbitmap_alloc (current_nr_blocks);
6727 if (blocks_to_reschedule)
6729 sbitmap_ones (visited_bbs);
6730 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6732 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6733 RESET_BIT (visited_bbs, BLOCK_TO_BB (bbi));
6738 sbitmap_zero (visited_bbs);
6739 from = EBB_FIRST_BB (0);
6742 cur_seqno = number_of_insns > 0 ? number_of_insns : sched_max_luid - 1;
6743 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6744 gcc_assert (cur_seqno == 0 || number_of_insns == 0);
6746 sbitmap_free (visited_bbs);
6747 return sched_max_luid - 1;
6750 /* Initialize scheduling parameters for current region. */
6752 sel_setup_region_sched_flags (void)
6754 enable_schedule_as_rhs_p = 1;
6756 pipelining_p = (bookkeeping_p
6757 && (flag_sel_sched_pipelining != 0)
6758 && current_loop_nest != NULL);
6759 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6763 /* Return true if all basic blocks of current region are empty. */
6765 current_region_empty_p (void)
6768 for (i = 0; i < current_nr_blocks; i++)
6769 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i))))
6775 /* Prepare and verify loop nest for pipelining. */
6777 setup_current_loop_nest (int rgn)
6779 current_loop_nest = get_loop_nest_for_rgn (rgn);
6781 if (!current_loop_nest)
6784 /* If this loop has any saved loop preheaders from nested loops,
6785 add these basic blocks to the current region. */
6786 sel_add_loop_preheaders ();
6788 /* Check that we're starting with a valid information. */
6789 gcc_assert (loop_latch_edge (current_loop_nest));
6790 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6793 /* Compute instruction priorities for current region. */
6795 sel_compute_priorities (int rgn)
6797 sched_rgn_compute_dependencies (rgn);
6799 /* Compute insn priorities in haifa style. Then free haifa style
6800 dependencies that we've calculated for this. */
6801 compute_priorities ();
6803 if (sched_verbose >= 5)
6804 debug_rgn_dependencies (0);
6809 /* Init scheduling data for RGN. Returns true when this region should not
6812 sel_region_init (int rgn)
6817 rgn_setup_region (rgn);
6819 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6820 do region initialization here so the region can be bundled correctly,
6821 but we'll skip the scheduling in sel_sched_region (). */
6822 if (current_region_empty_p ())
6825 if (flag_sel_sched_pipelining)
6826 setup_current_loop_nest (rgn);
6828 sel_setup_region_sched_flags ();
6830 bbs = VEC_alloc (basic_block, heap, current_nr_blocks);
6832 for (i = 0; i < current_nr_blocks; i++)
6833 VEC_quick_push (basic_block, bbs, BASIC_BLOCK (BB_TO_BLOCK (i)));
6835 sel_init_bbs (bbs, NULL);
6837 /* Initialize luids and dependence analysis which both sel-sched and haifa
6839 sched_init_luids (bbs, NULL, NULL, NULL);
6840 sched_deps_init (false);
6842 /* Initialize haifa data. */
6843 rgn_setup_sched_infos ();
6844 sel_set_sched_flags ();
6845 haifa_init_h_i_d (bbs, NULL, NULL, NULL);
6847 sel_compute_priorities (rgn);
6848 init_deps_global ();
6850 /* Main initialization. */
6851 sel_setup_sched_infos ();
6852 sel_init_global_and_expr (bbs);
6854 VEC_free (basic_block, heap, bbs);
6856 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6858 /* Init correct liveness sets on each instruction of a single-block loop.
6859 This is the only situation when we can't update liveness when calling
6860 compute_live for the first insn of the loop. */
6861 if (current_loop_nest)
6863 int header = (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6867 if (current_nr_blocks == header + 1)
6868 update_liveness_on_insn
6869 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header))));
6872 /* Set hooks so that no newly generated insn will go out unnoticed. */
6873 sel_register_cfg_hooks ();
6875 /* !!! We call target.sched.md_init () for the whole region, but we invoke
6876 targetm.sched.md_finish () for every ebb. */
6877 if (targetm.sched.md_init)
6878 /* None of the arguments are actually used in any target. */
6879 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6881 first_emitted_uid = get_max_uid () + 1;
6882 preheader_removed = false;
6884 /* Reset register allocation ticks array. */
6885 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6886 reg_rename_this_tick = 0;
6888 bitmap_initialize (forced_ebb_heads, 0);
6889 bitmap_clear (forced_ebb_heads);
6892 current_copies = BITMAP_ALLOC (NULL);
6893 current_originators = BITMAP_ALLOC (NULL);
6894 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
6899 /* Simplify insns after the scheduling. */
6901 simplify_changed_insns (void)
6905 for (i = 0; i < current_nr_blocks; i++)
6907 basic_block bb = BASIC_BLOCK (BB_TO_BLOCK (i));
6910 FOR_BB_INSNS (bb, insn)
6913 expr_t expr = INSN_EXPR (insn);
6915 if (EXPR_WAS_SUBSTITUTED (expr))
6916 validate_simplify_insn (insn);
6921 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6922 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6923 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6925 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
6928 basic_block bb1 = bb;
6929 if (sched_verbose >= 2)
6930 sel_print ("Finishing schedule in bbs: ");
6934 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
6936 if (sched_verbose >= 2)
6937 sel_print ("%d; ", bb1->index);
6939 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
6941 if (sched_verbose >= 2)
6944 get_ebb_head_tail (bb, bb1, &head, &tail);
6946 current_sched_info->head = head;
6947 current_sched_info->tail = tail;
6948 current_sched_info->prev_head = PREV_INSN (head);
6949 current_sched_info->next_tail = NEXT_INSN (tail);
6952 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6954 reset_sched_cycles_in_current_ebb (void)
6957 int haifa_last_clock = -1;
6958 int haifa_clock = 0;
6961 if (targetm.sched.md_init)
6963 /* None of the arguments are actually used in any target.
6964 NB: We should have md_reset () hook for cases like this. */
6965 targetm.sched.md_init (sched_dump, sched_verbose, -1);
6968 state_reset (curr_state);
6969 advance_state (curr_state);
6971 for (insn = current_sched_info->head;
6972 insn != current_sched_info->next_tail;
6973 insn = NEXT_INSN (insn))
6975 int cost, haifa_cost;
6977 bool asm_p, real_insn, after_stall;
6984 real_insn = recog_memoized (insn) >= 0;
6985 clock = INSN_SCHED_CYCLE (insn);
6987 cost = clock - last_clock;
6989 /* Initialize HAIFA_COST. */
6992 asm_p = INSN_ASM_P (insn);
6995 /* This is asm insn which *had* to be scheduled first
6999 /* This is a use/clobber insn. It should not change
7004 haifa_cost = estimate_insn_cost (insn, curr_state);
7006 /* Stall for whatever cycles we've stalled before. */
7008 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
7018 while (haifa_cost--)
7020 advance_state (curr_state);
7023 if (sched_verbose >= 2)
7025 sel_print ("advance_state (state_transition)\n");
7026 debug_state (curr_state);
7029 /* The DFA may report that e.g. insn requires 2 cycles to be
7030 issued, but on the next cycle it says that insn is ready
7031 to go. Check this here. */
7035 && estimate_insn_cost (insn, curr_state) == 0)
7042 gcc_assert (haifa_cost == 0);
7044 if (sched_verbose >= 2)
7045 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
7047 if (targetm.sched.dfa_new_cycle)
7048 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
7049 haifa_last_clock, haifa_clock,
7052 advance_state (curr_state);
7054 if (sched_verbose >= 2)
7056 sel_print ("advance_state (dfa_new_cycle)\n");
7057 debug_state (curr_state);
7063 cost = state_transition (curr_state, insn);
7065 if (sched_verbose >= 2)
7066 debug_state (curr_state);
7068 gcc_assert (cost < 0);
7071 if (targetm.sched.variable_issue)
7072 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
7074 INSN_SCHED_CYCLE (insn) = haifa_clock;
7077 haifa_last_clock = haifa_clock;
7081 /* Put TImode markers on insns starting a new issue group. */
7085 int last_clock = -1;
7088 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
7089 insn = NEXT_INSN (insn))
7096 clock = INSN_SCHED_CYCLE (insn);
7097 cost = (last_clock == -1) ? 1 : clock - last_clock;
7099 gcc_assert (cost >= 0);
7102 && GET_CODE (PATTERN (insn)) != USE
7103 && GET_CODE (PATTERN (insn)) != CLOBBER)
7105 if (reload_completed && cost > 0)
7106 PUT_MODE (insn, TImode);
7111 if (sched_verbose >= 2)
7112 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
7116 /* Perform MD_FINISH on EBBs comprising current region. When
7117 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7118 to produce correct sched cycles on insns. */
7120 sel_region_target_finish (bool reset_sched_cycles_p)
7123 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
7125 for (i = 0; i < current_nr_blocks; i++)
7127 if (bitmap_bit_p (scheduled_blocks, i))
7130 /* While pipelining outer loops, skip bundling for loop
7131 preheaders. Those will be rescheduled in the outer loop. */
7132 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
7135 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
7137 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
7140 if (reset_sched_cycles_p)
7141 reset_sched_cycles_in_current_ebb ();
7143 if (targetm.sched.md_init)
7144 targetm.sched.md_init (sched_dump, sched_verbose, -1);
7148 if (targetm.sched.md_finish)
7150 targetm.sched.md_finish (sched_dump, sched_verbose);
7152 /* Extend luids so that insns generated by the target will
7154 sched_init_luids (NULL, NULL, NULL, NULL);
7158 BITMAP_FREE (scheduled_blocks);
7161 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7162 is true, make an additional pass emulating scheduler to get correct insn
7163 cycles for md_finish calls. */
7165 sel_region_finish (bool reset_sched_cycles_p)
7167 simplify_changed_insns ();
7168 sched_finish_ready_list ();
7171 /* Free the vectors. */
7173 VEC_free (expr_t, heap, vec_av_set);
7174 BITMAP_FREE (current_copies);
7175 BITMAP_FREE (current_originators);
7176 BITMAP_FREE (code_motion_visited_blocks);
7177 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns);
7178 vinsn_vec_free (&vec_target_unavailable_vinsns);
7180 /* If LV_SET of the region head should be updated, do it now because
7181 there will be no other chance. */
7186 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
7187 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
7189 basic_block bb = BLOCK_FOR_INSN (insn);
7191 if (!BB_LV_SET_VALID_P (bb))
7192 compute_live (insn);
7196 /* Emulate the Haifa scheduler for bundling. */
7197 if (reload_completed)
7198 sel_region_target_finish (reset_sched_cycles_p);
7200 sel_finish_global_and_expr ();
7202 bitmap_clear (forced_ebb_heads);
7206 finish_deps_global ();
7207 sched_finish_luids ();
7210 BITMAP_FREE (blocks_to_reschedule);
7212 sel_unregister_cfg_hooks ();
7218 /* Functions that implement the scheduler driver. */
7220 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7221 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7222 of insns scheduled -- these would be postprocessed later. */
7224 schedule_on_fences (flist_t fences, int max_seqno,
7225 ilist_t **scheduled_insns_tailpp)
7227 flist_t old_fences = fences;
7229 if (sched_verbose >= 1)
7231 sel_print ("\nScheduling on fences: ");
7232 dump_flist (fences);
7236 scheduled_something_on_previous_fence = false;
7237 for (; fences; fences = FLIST_NEXT (fences))
7239 fence_t fence = NULL;
7242 bool first_p = true;
7244 /* Choose the next fence group to schedule.
7245 The fact that insn can be scheduled only once
7246 on the cycle is guaranteed by two properties:
7247 1. seqnos of parallel groups decrease with each iteration.
7248 2. If is_ineligible_successor () sees the larger seqno, it
7249 checks if candidate insn is_in_current_fence_p (). */
7250 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7252 fence_t f = FLIST_FENCE (fences2);
7254 if (!FENCE_PROCESSED_P (f))
7256 int i = INSN_SEQNO (FENCE_INSN (f));
7258 if (first_p || i > seqno)
7265 /* ??? Seqnos of different groups should be different. */
7266 gcc_assert (1 || i != seqno);
7272 /* As FENCE is nonnull, SEQNO is initialized. */
7273 seqno -= max_seqno + 1;
7274 fill_insns (fence, seqno, scheduled_insns_tailpp);
7275 FENCE_PROCESSED_P (fence) = true;
7278 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7279 don't need to keep bookkeeping-invalidated and target-unavailable
7281 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7282 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7285 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7287 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7289 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7291 /* The first element is already processed. */
7292 while ((fences = FLIST_NEXT (fences)))
7294 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7296 if (*min_seqno > seqno)
7298 else if (*max_seqno < seqno)
7303 /* Calculate new fences from FENCES. */
7305 calculate_new_fences (flist_t fences, int orig_max_seqno)
7307 flist_t old_fences = fences;
7308 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7310 flist_tail_init (new_fences);
7311 for (; fences; fences = FLIST_NEXT (fences))
7313 fence_t fence = FLIST_FENCE (fences);
7316 if (!FENCE_BNDS (fence))
7318 /* This fence doesn't have any successors. */
7319 if (!FENCE_SCHEDULED_P (fence))
7321 /* Nothing was scheduled on this fence. */
7324 insn = FENCE_INSN (fence);
7325 seqno = INSN_SEQNO (insn);
7326 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7328 if (sched_verbose >= 1)
7329 sel_print ("Fence %d[%d] has not changed\n",
7332 move_fence_to_fences (fences, new_fences);
7336 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7339 flist_clear (&old_fences);
7340 return FLIST_TAIL_HEAD (new_fences);
7343 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7344 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7345 the highest seqno used in a region. Return the updated highest seqno. */
7347 update_seqnos_and_stage (int min_seqno, int max_seqno,
7348 int highest_seqno_in_use,
7349 ilist_t *pscheduled_insns)
7355 /* Actually, new_hs is the seqno of the instruction, that was
7356 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7357 if (*pscheduled_insns)
7359 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7360 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7361 gcc_assert (new_hs > highest_seqno_in_use);
7364 new_hs = highest_seqno_in_use;
7366 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7368 gcc_assert (INSN_SEQNO (insn) < 0);
7369 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7370 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7372 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7373 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7374 require > 1GB of memory e.g. on limit-fnargs.c. */
7376 free_data_for_scheduled_insn (insn);
7379 ilist_clear (pscheduled_insns);
7385 /* The main driver for scheduling a region. This function is responsible
7386 for correct propagation of fences (i.e. scheduling points) and creating
7387 a group of parallel insns at each of them. It also supports
7388 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7391 sel_sched_region_2 (int orig_max_seqno)
7393 int highest_seqno_in_use = orig_max_seqno;
7395 stat_bookkeeping_copies = 0;
7396 stat_insns_needed_bookkeeping = 0;
7397 stat_renamed_scheduled = 0;
7398 stat_substitutions_total = 0;
7399 num_insns_scheduled = 0;
7403 int min_seqno, max_seqno;
7404 ilist_t scheduled_insns = NULL;
7405 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7407 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7408 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7409 fences = calculate_new_fences (fences, orig_max_seqno);
7410 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7411 highest_seqno_in_use,
7415 if (sched_verbose >= 1)
7416 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7417 "bookkeeping, %d insns renamed, %d insns substituted\n",
7418 stat_bookkeeping_copies,
7419 stat_insns_needed_bookkeeping,
7420 stat_renamed_scheduled,
7421 stat_substitutions_total);
7424 /* Schedule a region. When pipelining, search for possibly never scheduled
7425 bookkeeping code and schedule it. Reschedule pipelined code without
7426 pipelining after. */
7428 sel_sched_region_1 (void)
7430 int number_of_insns;
7433 /* Remove empty blocks that might be in the region from the beginning.
7434 We need to do save sched_max_luid before that, as it actually shows
7435 the number of insns in the region, and purge_empty_blocks can
7437 number_of_insns = sched_max_luid - 1;
7438 purge_empty_blocks ();
7440 orig_max_seqno = init_seqno (number_of_insns, NULL, NULL);
7441 gcc_assert (orig_max_seqno >= 1);
7443 /* When pipelining outer loops, create fences on the loop header,
7446 if (current_loop_nest)
7447 init_fences (BB_END (EBB_FIRST_BB (0)));
7449 init_fences (bb_note (EBB_FIRST_BB (0)));
7452 sel_sched_region_2 (orig_max_seqno);
7454 gcc_assert (fences == NULL);
7460 struct flist_tail_def _new_fences;
7461 flist_tail_t new_fences = &_new_fences;
7464 pipelining_p = false;
7465 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7466 bookkeeping_p = false;
7467 enable_schedule_as_rhs_p = false;
7469 /* Schedule newly created code, that has not been scheduled yet. */
7476 for (i = 0; i < current_nr_blocks; i++)
7478 basic_block bb = EBB_FIRST_BB (i);
7480 if (sel_bb_empty_p (bb))
7482 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7486 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7488 clear_outdated_rtx_info (bb);
7489 if (sel_insn_is_speculation_check (BB_END (bb))
7490 && JUMP_P (BB_END (bb)))
7491 bitmap_set_bit (blocks_to_reschedule,
7492 BRANCH_EDGE (bb)->dest->index);
7494 else if (INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7495 bitmap_set_bit (blocks_to_reschedule, bb->index);
7498 for (i = 0; i < current_nr_blocks; i++)
7500 bb = EBB_FIRST_BB (i);
7502 /* While pipelining outer loops, skip bundling for loop
7503 preheaders. Those will be rescheduled in the outer
7505 if (sel_is_loop_preheader_p (bb))
7507 clear_outdated_rtx_info (bb);
7511 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7513 flist_tail_init (new_fences);
7515 orig_max_seqno = init_seqno (0, blocks_to_reschedule, bb);
7517 /* Mark BB as head of the new ebb. */
7518 bitmap_set_bit (forced_ebb_heads, bb->index);
7520 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7522 gcc_assert (fences == NULL);
7524 init_fences (bb_note (bb));
7526 sel_sched_region_2 (orig_max_seqno);
7536 /* Schedule the RGN region. */
7538 sel_sched_region (int rgn)
7541 bool reset_sched_cycles_p;
7543 if (sel_region_init (rgn))
7546 if (sched_verbose >= 1)
7547 sel_print ("Scheduling region %d\n", rgn);
7549 schedule_p = (!sched_is_disabled_for_current_region_p ()
7550 && dbg_cnt (sel_sched_region_cnt));
7551 reset_sched_cycles_p = pipelining_p;
7553 sel_sched_region_1 ();
7555 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7556 reset_sched_cycles_p = true;
7558 sel_region_finish (reset_sched_cycles_p);
7561 /* Perform global init for the scheduler. */
7563 sel_global_init (void)
7565 calculate_dominance_info (CDI_DOMINATORS);
7566 alloc_sched_pools ();
7568 /* Setup the infos for sched_init. */
7569 sel_setup_sched_infos ();
7570 setup_sched_dump ();
7572 sched_rgn_init (false);
7576 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7578 can_issue_more = issue_rate;
7580 sched_extend_target ();
7581 sched_deps_init (true);
7582 setup_nop_and_exit_insns ();
7583 sel_extend_global_bb_info ();
7585 init_hard_regs_data ();
7588 /* Free the global data of the scheduler. */
7590 sel_global_finish (void)
7592 free_bb_note_pool ();
7594 sel_finish_global_bb_info ();
7596 free_regset_pool ();
7597 free_nop_and_exit_insns ();
7599 sched_rgn_finish ();
7600 sched_deps_finish ();
7604 sel_finish_pipelining ();
7606 free_sched_pools ();
7607 free_dominance_info (CDI_DOMINATORS);
7610 /* Return true when we need to skip selective scheduling. Used for debugging. */
7612 maybe_skip_selective_scheduling (void)
7614 return ! dbg_cnt (sel_sched_cnt);
7617 /* The entry point. */
7619 run_selective_scheduling (void)
7623 if (n_basic_blocks == NUM_FIXED_BLOCKS)
7628 for (rgn = 0; rgn < nr_regions; rgn++)
7629 sel_sched_region (rgn);
7631 sel_global_finish ();