1 /* Instruction scheduling pass.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 Enhanced by, and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Instruction scheduling pass.
24 This pass implements list scheduling within basic blocks. It is
25 run after flow analysis, but before register allocation. The
26 scheduler works as follows:
28 We compute insn priorities based on data dependencies. Flow
29 analysis only creates a fraction of the data-dependencies we must
30 observe: namely, only those dependencies which the combiner can be
31 expected to use. For this pass, we must therefore create the
32 remaining dependencies we need to observe: register dependencies,
33 memory dependencies, dependencies to keep function calls in order,
34 and the dependence between a conditional branch and the setting of
35 condition codes are all dealt with here.
37 The scheduler first traverses the data flow graph, starting with
38 the last instruction, and proceeding to the first, assigning
39 values to insn_priority as it goes. This sorts the instructions
40 topologically by data dependence.
42 Once priorities have been established, we order the insns using
43 list scheduling. This works as follows: starting with a list of
44 all the ready insns, and sorted according to priority number, we
45 schedule the insn from the end of the list by placing its
46 predecessors in the list according to their priority order. We
47 consider this insn scheduled by setting the pointer to the "end" of
48 the list to point to the previous insn. When an insn has no
49 predecessors, we either queue it until sufficient time has elapsed
50 or add it to the ready list. As the instructions are scheduled or
51 when stalls are introduced, the queue advances and dumps insns into
52 the ready list. When all insns down to the lowest priority have
53 been scheduled, the critical path of the basic block has been made
54 as short as possible. The remaining insns are then scheduled in
57 Function unit conflicts are resolved during reverse list scheduling
58 by tracking the time when each insn is committed to the schedule
59 and from that, the time the function units it uses must be free.
60 As insns on the ready list are considered for scheduling, those
61 that would result in a blockage of the already committed insns are
62 queued until no blockage will result. Among the remaining insns on
63 the ready list to be considered, the first one with the largest
64 potential for causing a subsequent blockage is chosen.
66 The following list shows the order in which we want to break ties
67 among insns in the ready list:
69 1. choose insn with lowest conflict cost, ties broken by
70 2. choose insn with the longest path to end of bb, ties broken by
71 3. choose insn that kills the most registers, ties broken by
72 4. choose insn that conflicts with the most ready insns, or finally
73 5. choose insn with lowest UID.
75 Memory references complicate matters. Only if we can be certain
76 that memory references are not part of the data dependency graph
77 (via true, anti, or output dependence), can we move operations past
78 memory references. To first approximation, reads can be done
79 independently, while writes introduce dependencies. Better
80 approximations will yield fewer dependencies.
82 Dependencies set up by memory references are treated in exactly the
83 same way as other dependencies, by using LOG_LINKS.
85 Having optimized the critical path, we may have also unduly
86 extended the lifetimes of some registers. If an operation requires
87 that constants be loaded into registers, it is certainly desirable
88 to load those constants as early as necessary, but no earlier.
89 I.e., it will not do to load up a bunch of registers at the
90 beginning of a basic block only to use them at the end, if they
91 could be loaded later, since this may result in excessive register
94 Note that since branches are never in basic blocks, but only end
95 basic blocks, this pass will not do any branch scheduling. But
96 that is ok, since we can use GNU's delayed branch scheduling
97 pass to take care of this case.
99 Also note that no further optimizations based on algebraic identities
100 are performed, so this pass would be a good one to perform instruction
101 splitting, such as breaking up a multiply instruction into shifts
102 and adds where that is profitable.
104 Given the memory aliasing analysis that this pass should perform,
105 it should be possible to remove redundant stores to memory, and to
106 load values from registers instead of hitting memory.
108 This pass must update information that subsequent passes expect to be
109 correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
110 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
113 The information in the line number notes is carefully retained by this
114 pass. All other NOTE insns are grouped in their same relative order at
115 the beginning of basic blocks that have been scheduled. */
120 #include "basic-block.h"
122 #include "hard-reg-set.h"
124 #include "insn-config.h"
125 #include "insn-attr.h"
127 #ifdef INSN_SCHEDULING
128 /* Arrays set up by scheduling for the same respective purposes as
129 similar-named arrays set up by flow analysis. We work with these
130 arrays during the scheduling pass so we can compare values against
133 Values of these arrays are copied at the end of this pass into the
134 arrays set up by flow analysis. */
135 static short *sched_reg_n_deaths;
136 static int *sched_reg_n_calls_crossed;
137 static int *sched_reg_live_length;
139 /* Element N is the next insn that sets (hard or pseudo) register
140 N within the current basic block; or zero, if there is no
141 such insn. Needed for new registers which may be introduced
142 by splitting insns. */
143 static rtx *reg_last_uses;
144 static rtx *reg_last_sets;
146 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
147 static int *insn_luid;
148 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
150 /* Vector indexed by INSN_UID giving each instruction a priority. */
151 static int *insn_priority;
152 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
154 static short *insn_costs;
155 #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
157 /* Vector indexed by INSN_UID giving an encoding of the function units
159 static short *insn_units;
160 #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)]
162 /* Vector indexed by INSN_UID giving an encoding of the blockage range
163 function. The unit and the range are encoded. */
164 static unsigned int *insn_blockage;
165 #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)]
167 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
168 #define ENCODE_BLOCKAGE(U,R) \
169 ((((U) << UNIT_BITS) << BLOCKAGE_BITS \
170 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
171 | MAX_BLOCKAGE_COST (R))
172 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
173 #define BLOCKAGE_RANGE(B) \
174 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
175 | (B) & BLOCKAGE_MASK)
177 /* Encodings of the `<name>_unit_blockage_range' function. */
178 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
179 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
181 #define DONE_PRIORITY -1
182 #define MAX_PRIORITY 0x7fffffff
183 #define TAIL_PRIORITY 0x7ffffffe
184 #define LAUNCH_PRIORITY 0x7f000001
185 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
186 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
188 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
189 static int *insn_ref_count;
190 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
192 /* Vector indexed by INSN_UID giving line-number note in effect for each
193 insn. For line-number notes, this indicates whether the note may be
195 static rtx *line_note;
196 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
198 /* Vector indexed by basic block number giving the starting line-number
199 for each basic block. */
200 static rtx *line_note_head;
202 /* List of important notes we must keep around. This is a pointer to the
203 last element in the list. */
204 static rtx note_list;
206 /* Regsets telling whether a given register is live or dead before the last
207 scheduled insn. Must scan the instructions once before scheduling to
208 determine what registers are live or dead at the end of the block. */
209 static regset bb_dead_regs;
210 static regset bb_live_regs;
212 /* Regset telling whether a given register is live after the insn currently
213 being scheduled. Before processing an insn, this is equal to bb_live_regs
214 above. This is used so that we can find registers that are newly born/dead
215 after processing an insn. */
216 static regset old_live_regs;
218 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
219 during the initial scan and reused later. If there are not exactly as
220 many REG_DEAD notes in the post scheduled code as there were in the
221 prescheduled code then we trigger an abort because this indicates a bug. */
222 static rtx dead_notes;
226 /* An instruction is ready to be scheduled when all insns following it
227 have already been scheduled. It is important to ensure that all
228 insns which use its result will not be executed until its result
229 has been computed. An insn is maintained in one of four structures:
231 (P) the "Pending" set of insns which cannot be scheduled until
232 their dependencies have been satisfied.
233 (Q) the "Queued" set of insns that can be scheduled when sufficient
235 (R) the "Ready" list of unscheduled, uncommitted insns.
236 (S) the "Scheduled" list of insns.
238 Initially, all insns are either "Pending" or "Ready" depending on
239 whether their dependencies are satisfied.
241 Insns move from the "Ready" list to the "Scheduled" list as they
242 are committed to the schedule. As this occurs, the insns in the
243 "Pending" list have their dependencies satisfied and move to either
244 the "Ready" list or the "Queued" set depending on whether
245 sufficient time has passed to make them ready. As time passes,
246 insns move from the "Queued" set to the "Ready" list. Insns may
247 move from the "Ready" list to the "Queued" set if they are blocked
248 due to a function unit conflict.
250 The "Pending" list (P) are the insns in the LOG_LINKS of the unscheduled
251 insns, i.e., those that are ready, queued, and pending.
252 The "Queued" set (Q) is implemented by the variable `insn_queue'.
253 The "Ready" list (R) is implemented by the variables `ready' and
255 The "Scheduled" list (S) is the new insn chain built by this pass.
257 The transition (R->S) is implemented in the scheduling loop in
258 `schedule_block' when the best insn to schedule is chosen.
259 The transition (R->Q) is implemented in `schedule_select' when an
260 insn is found to to have a function unit conflict with the already
262 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
263 insns move from the ready list to the scheduled list.
264 The transition (Q->R) is implemented at the top of the scheduling
265 loop in `schedule_block' as time passes or stalls are introduced. */
267 /* Implement a circular buffer to delay instructions until sufficient
268 time has passed. INSN_QUEUE_SIZE is a power of two larger than
269 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
270 longest time an isnsn may be queued. */
271 static rtx insn_queue[INSN_QUEUE_SIZE];
272 static int q_ptr = 0;
273 static int q_size = 0;
274 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
275 #define NEXT_Q_AFTER(X,C) (((X)+C) & (INSN_QUEUE_SIZE-1))
277 /* Vector indexed by INSN_UID giving the minimum clock tick at which
278 the insn becomes ready. This is used to note timing constraints for
279 insns in the pending list. */
280 static int *insn_tick;
281 #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)])
283 /* Forward declarations. */
284 static void sched_analyze_2 ();
285 static void schedule_block ();
287 /* Main entry point of this file. */
288 void schedule_insns ();
289 #endif /* INSN_SCHEDULING */
291 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
293 /* Vector indexed by N giving the initial (unchanging) value known
294 for pseudo-register N. */
295 static rtx *reg_known_value;
297 /* Indicates number of valid entries in reg_known_value. */
298 static int reg_known_value_size;
304 if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
305 && REGNO (x) <= reg_known_value_size)
306 return reg_known_value[REGNO (x)];
307 else if (GET_CODE (x) == PLUS)
309 rtx x0 = canon_rtx (XEXP (x, 0));
310 rtx x1 = canon_rtx (XEXP (x, 1));
312 if (x0 != XEXP (x, 0) || x1 != XEXP (x, 1))
314 /* We can tolerate LO_SUMs being offset here; these
315 rtl are used for nothing other than comparisons. */
316 if (GET_CODE (x0) == CONST_INT)
317 return plus_constant_for_output (x1, INTVAL (x0));
318 else if (GET_CODE (x1) == CONST_INT)
319 return plus_constant_for_output (x0, INTVAL (x1));
320 return gen_rtx (PLUS, GET_MODE (x), x0, x1);
326 /* Set up all info needed to perform alias analysis on memory references. */
329 init_alias_analysis ()
331 int maxreg = max_reg_num ();
336 reg_known_value_size = maxreg;
339 = (rtx *) oballoc ((maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx))
340 - FIRST_PSEUDO_REGISTER;
341 bzero (reg_known_value+FIRST_PSEUDO_REGISTER,
342 (maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx));
344 /* Fill in the entries with known constant values. */
345 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
346 if ((set = single_set (insn)) != 0
347 && GET_CODE (SET_DEST (set)) == REG
348 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER
349 && (((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
350 && reg_n_sets[REGNO (SET_DEST (set))] == 1)
351 || (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != 0)
352 && GET_CODE (XEXP (note, 0)) != EXPR_LIST)
353 reg_known_value[REGNO (SET_DEST (set))] = XEXP (note, 0);
355 /* Fill in the remaining entries. */
356 while (--maxreg >= FIRST_PSEUDO_REGISTER)
357 if (reg_known_value[maxreg] == 0)
358 reg_known_value[maxreg] = regno_reg_rtx[maxreg];
361 /* Return 1 if X and Y are identical-looking rtx's.
363 We use the data in reg_known_value above to see if two registers with
364 different numbers are, in fact, equivalent. */
367 rtx_equal_for_memref_p (x, y)
372 register enum rtx_code code;
375 if (x == 0 && y == 0)
377 if (x == 0 || y == 0)
386 /* Rtx's of different codes cannot be equal. */
387 if (code != GET_CODE (y))
390 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
391 (REG:SI x) and (REG:HI x) are NOT equivalent. */
393 if (GET_MODE (x) != GET_MODE (y))
396 /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */
399 return REGNO (x) == REGNO (y);
400 if (code == LABEL_REF)
401 return XEXP (x, 0) == XEXP (y, 0);
402 if (code == SYMBOL_REF)
403 return XSTR (x, 0) == XSTR (y, 0);
405 /* Compare the elements. If any pair of corresponding elements
406 fail to match, return 0 for the whole things. */
408 fmt = GET_RTX_FORMAT (code);
409 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
414 if (XWINT (x, i) != XWINT (y, i))
420 if (XINT (x, i) != XINT (y, i))
426 /* Two vectors must have the same length. */
427 if (XVECLEN (x, i) != XVECLEN (y, i))
430 /* And the corresponding elements must match. */
431 for (j = 0; j < XVECLEN (x, i); j++)
432 if (rtx_equal_for_memref_p (XVECEXP (x, i, j), XVECEXP (y, i, j)) == 0)
437 if (rtx_equal_for_memref_p (XEXP (x, i), XEXP (y, i)) == 0)
443 if (strcmp (XSTR (x, i), XSTR (y, i)))
448 /* These are just backpointers, so they don't matter. */
454 /* It is believed that rtx's at this level will never
455 contain anything but integers and other rtx's,
456 except for within LABEL_REFs and SYMBOL_REFs. */
464 /* Given an rtx X, find a SYMBOL_REF or LABEL_REF within
465 X and return it, or return 0 if none found. */
468 find_symbolic_term (x)
472 register enum rtx_code code;
476 if (code == SYMBOL_REF || code == LABEL_REF)
478 if (GET_RTX_CLASS (code) == 'o')
481 fmt = GET_RTX_FORMAT (code);
482 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
488 t = find_symbolic_term (XEXP (x, i));
492 else if (fmt[i] == 'E')
498 /* Return nonzero if X and Y (memory addresses) could reference the
499 same location in memory. C is an offset accumulator. When
500 C is nonzero, we are testing aliases between X and Y + C.
501 XSIZE is the size in bytes of the X reference,
502 similarly YSIZE is the size in bytes for Y.
504 If XSIZE or YSIZE is zero, we do not know the amount of memory being
505 referenced (the reference was BLKmode), so make the most pessimistic
508 We recognize the following cases of non-conflicting memory:
510 (1) addresses involving the frame pointer cannot conflict
511 with addresses involving static variables.
512 (2) static variables with different addresses cannot conflict.
514 Nice to notice that varying addresses cannot conflict with fp if no
515 local variables had their addresses taken, but that's too hard now. */
518 memrefs_conflict_p (xsize, x, ysize, y, c)
523 if (GET_CODE (x) == HIGH)
525 else if (GET_CODE (x) == LO_SUM)
529 if (GET_CODE (y) == HIGH)
531 else if (GET_CODE (y) == LO_SUM)
536 if (rtx_equal_for_memref_p (x, y))
537 return (xsize == 0 || ysize == 0 ||
538 (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
540 if (y == frame_pointer_rtx || y == stack_pointer_rtx)
544 y = x; ysize = xsize;
545 x = t; xsize = tsize;
548 if (x == frame_pointer_rtx || x == stack_pointer_rtx)
555 if (GET_CODE (y) == PLUS
556 && canon_rtx (XEXP (y, 0)) == x
557 && (y1 = canon_rtx (XEXP (y, 1)))
558 && GET_CODE (y1) == CONST_INT)
561 return (xsize == 0 || ysize == 0
562 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
565 if (GET_CODE (y) == PLUS
566 && (y1 = canon_rtx (XEXP (y, 0)))
573 if (GET_CODE (x) == PLUS)
575 /* The fact that X is canonicalized means that this
576 PLUS rtx is canonicalized. */
577 rtx x0 = XEXP (x, 0);
578 rtx x1 = XEXP (x, 1);
580 if (GET_CODE (y) == PLUS)
582 /* The fact that Y is canonicalized means that this
583 PLUS rtx is canonicalized. */
584 rtx y0 = XEXP (y, 0);
585 rtx y1 = XEXP (y, 1);
587 if (rtx_equal_for_memref_p (x1, y1))
588 return memrefs_conflict_p (xsize, x0, ysize, y0, c);
589 if (rtx_equal_for_memref_p (x0, y0))
590 return memrefs_conflict_p (xsize, x1, ysize, y1, c);
591 if (GET_CODE (x1) == CONST_INT)
592 if (GET_CODE (y1) == CONST_INT)
593 return memrefs_conflict_p (xsize, x0, ysize, y0,
594 c - INTVAL (x1) + INTVAL (y1));
596 return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1));
597 else if (GET_CODE (y1) == CONST_INT)
598 return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1));
600 /* Handle case where we cannot understand iteration operators,
601 but we notice that the base addresses are distinct objects. */
602 x = find_symbolic_term (x);
605 y = find_symbolic_term (y);
608 return rtx_equal_for_memref_p (x, y);
610 else if (GET_CODE (x1) == CONST_INT)
611 return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1));
613 else if (GET_CODE (y) == PLUS)
615 /* The fact that Y is canonicalized means that this
616 PLUS rtx is canonicalized. */
617 rtx y0 = XEXP (y, 0);
618 rtx y1 = XEXP (y, 1);
620 if (GET_CODE (y1) == CONST_INT)
621 return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1));
626 if (GET_CODE (x) == GET_CODE (y))
627 switch (GET_CODE (x))
631 /* Handle cases where we expect the second operands to be the
632 same, and check only whether the first operand would conflict
635 rtx x1 = canon_rtx (XEXP (x, 1));
636 rtx y1 = canon_rtx (XEXP (y, 1));
637 if (! rtx_equal_for_memref_p (x1, y1))
639 x0 = canon_rtx (XEXP (x, 0));
640 y0 = canon_rtx (XEXP (y, 0));
641 if (rtx_equal_for_memref_p (x0, y0))
642 return (xsize == 0 || ysize == 0
643 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
645 /* Can't properly adjust our sizes. */
646 if (GET_CODE (x1) != CONST_INT)
648 xsize /= INTVAL (x1);
649 ysize /= INTVAL (x1);
651 return memrefs_conflict_p (xsize, x0, ysize, y0, c);
657 if (GET_CODE (x) == CONST_INT && GET_CODE (y) == CONST_INT)
659 c += (INTVAL (y) - INTVAL (x));
660 return (xsize == 0 || ysize == 0
661 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
664 if (GET_CODE (x) == CONST)
666 if (GET_CODE (y) == CONST)
667 return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
668 ysize, canon_rtx (XEXP (y, 0)), c);
670 return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
673 if (GET_CODE (y) == CONST)
674 return memrefs_conflict_p (xsize, x, ysize,
675 canon_rtx (XEXP (y, 0)), c);
678 return (rtx_equal_for_memref_p (x, y)
679 && (xsize == 0 || ysize == 0
680 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0)));
687 /* Functions to compute memory dependencies.
689 Since we process the insns in execution order, we can build tables
690 to keep track of what registers are fixed (and not aliased), what registers
691 are varying in known ways, and what registers are varying in unknown
694 If both memory references are volatile, then there must always be a
695 dependence between the two references, since their order can not be
696 changed. A volatile and non-volatile reference can be interchanged
699 A MEM_IN_STRUCT reference at a varying address can never conflict with a
700 non-MEM_IN_STRUCT reference at a fixed address. */
702 /* Read dependence: X is read after read in MEM takes place. There can
703 only be a dependence here if both reads are volatile. */
706 read_dependence (mem, x)
710 return MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem);
713 /* True dependence: X is read after store in MEM takes place. */
716 true_dependence (mem, x)
720 /* If X is an unchanging read, then it can't possibly conflict with any
721 non-unchanging store. It may conflict with an unchanging write though,
722 because there may be a single store to this address to initialize it.
723 Just fall through to the code below to resolve the case where we have
724 both an unchanging read and an unchanging write. This won't handle all
725 cases optimally, but the possible performance loss should be
727 if (RTX_UNCHANGING_P (x) && ! RTX_UNCHANGING_P (mem))
730 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
731 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
732 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
733 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
734 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
735 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
736 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
739 /* Anti dependence: X is written after read in MEM takes place. */
742 anti_dependence (mem, x)
746 /* If MEM is an unchanging read, then it can't possibly conflict with
747 the store to X, because there is at most one store to MEM, and it must
748 have occured somewhere before MEM. */
749 if (RTX_UNCHANGING_P (mem))
752 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
753 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
754 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
755 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
756 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
757 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
758 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
761 /* Output dependence: X is written after store in MEM takes place. */
764 output_dependence (mem, x)
768 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
769 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
770 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
771 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
772 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
773 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
774 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
777 /* Helper functions for instruction scheduling. */
779 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
780 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
781 of dependence that this link represents. */
784 add_dependence (insn, elem, dep_type)
787 enum reg_note dep_type;
791 /* Don't depend an insn on itself. */
795 /* If elem is part of a sequence that must be scheduled together, then
796 make the dependence point to the last insn of the sequence.
797 When HAVE_cc0, it is possible for NOTEs to exist between users and
798 setters of the condition codes, so we must skip past notes here.
799 Otherwise, NOTEs are impossible here. */
801 next = NEXT_INSN (elem);
804 while (next && GET_CODE (next) == NOTE)
805 next = NEXT_INSN (next);
808 if (next && SCHED_GROUP_P (next))
810 /* Notes will never intervene here though, so don't bother checking
812 while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next)))
813 next = NEXT_INSN (next);
815 /* Again, don't depend an insn on itself. */
819 /* Make the dependence to NEXT, the last insn of the group, instead
820 of the original ELEM. */
824 /* Check that we don't already have this dependence. */
825 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
826 if (XEXP (link, 0) == elem)
828 /* If this is a more restrictive type of dependence than the existing
829 one, then change the existing dependence to this type. */
830 if ((int) dep_type < (int) REG_NOTE_KIND (link))
831 PUT_REG_NOTE_KIND (link, dep_type);
834 /* Might want to check one level of transitivity to save conses. */
836 link = rtx_alloc (INSN_LIST);
837 /* Insn dependency, not data dependency. */
838 PUT_REG_NOTE_KIND (link, dep_type);
839 XEXP (link, 0) = elem;
840 XEXP (link, 1) = LOG_LINKS (insn);
841 LOG_LINKS (insn) = link;
844 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
845 of INSN. Abort if not found. */
847 remove_dependence (insn, elem)
854 for (prev = 0, link = LOG_LINKS (insn); link;
855 prev = link, link = XEXP (link, 1))
857 if (XEXP (link, 0) == elem)
860 XEXP (prev, 1) = XEXP (link, 1);
862 LOG_LINKS (insn) = XEXP (link, 1);
872 #ifndef INSN_SCHEDULING
873 void schedule_insns () {}
879 /* Computation of memory dependencies. */
881 /* The *_insns and *_mems are paired lists. Each pending memory operation
882 will have a pointer to the MEM rtx on one list and a pointer to the
883 containing insn on the other list in the same place in the list. */
885 /* We can't use add_dependence like the old code did, because a single insn
886 may have multiple memory accesses, and hence needs to be on the list
887 once for each memory access. Add_dependence won't let you add an insn
888 to a list more than once. */
890 /* An INSN_LIST containing all insns with pending read operations. */
891 static rtx pending_read_insns;
893 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
894 static rtx pending_read_mems;
896 /* An INSN_LIST containing all insns with pending write operations. */
897 static rtx pending_write_insns;
899 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
900 static rtx pending_write_mems;
902 /* Indicates the combined length of the two pending lists. We must prevent
903 these lists from ever growing too large since the number of dependencies
904 produced is at least O(N*N), and execution time is at least O(4*N*N), as
905 a function of the length of these pending lists. */
907 static int pending_lists_length;
909 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
911 static rtx unused_insn_list;
913 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
915 static rtx unused_expr_list;
917 /* The last insn upon which all memory references must depend.
918 This is an insn which flushed the pending lists, creating a dependency
919 between it and all previously pending memory references. This creates
920 a barrier (or a checkpoint) which no memory reference is allowed to cross.
922 This includes all non constant CALL_INSNs. When we do interprocedural
923 alias analysis, this restriction can be relaxed.
924 This may also be an INSN that writes memory if the pending lists grow
927 static rtx last_pending_memory_flush;
929 /* The last function call we have seen. All hard regs, and, of course,
930 the last function call, must depend on this. */
932 static rtx last_function_call;
934 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
935 that does not already cross a call. We create dependencies between each
936 of those insn and the next call insn, to ensure that they won't cross a call
937 after scheduling is done. */
939 static rtx sched_before_next_call;
941 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
942 so that insns independent of the last scheduled insn will be preferred
943 over dependent instructions. */
945 static rtx last_scheduled_insn;
947 /* Process an insn's memory dependencies. There are four kinds of
950 (0) read dependence: read follows read
951 (1) true dependence: read follows write
952 (2) anti dependence: write follows read
953 (3) output dependence: write follows write
955 We are careful to build only dependencies which actually exist, and
956 use transitivity to avoid building too many links. */
958 /* Return the INSN_LIST containing INSN in LIST, or NULL
959 if LIST does not contain INSN. */
962 find_insn_list (insn, list)
968 if (XEXP (list, 0) == insn)
970 list = XEXP (list, 1);
975 /* Compute the function units used by INSN. This caches the value
976 returned by function_units_used. A function unit is encoded as the
977 unit number if the value is non-negative and the compliment of a
978 mask if the value is negative. A function unit index is the
979 non-negative encoding. */
985 register int unit = INSN_UNIT (insn);
989 recog_memoized (insn);
991 /* A USE insn, or something else we don't need to understand.
992 We can't pass these directly to function_units_used because it will
993 trigger a fatal error for unrecognizable insns. */
994 if (INSN_CODE (insn) < 0)
998 unit = function_units_used (insn);
999 /* Increment non-negative values so we can cache zero. */
1000 if (unit >= 0) unit++;
1002 /* We only cache 16 bits of the result, so if the value is out of
1003 range, don't cache it. */
1004 if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
1006 || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
1007 INSN_UNIT (insn) = unit;
1009 return (unit > 0 ? unit - 1 : unit);
1012 /* Compute the blockage range for executing INSN on UNIT. This caches
1013 the value returned by the blockage_range_function for the unit.
1014 These values are encoded in an int where the upper half gives the
1015 minimum value and the lower half gives the maximum value. */
1017 __inline static unsigned int
1018 blockage_range (unit, insn)
1022 unsigned int blockage = INSN_BLOCKAGE (insn);
1025 if (UNIT_BLOCKED (blockage) != unit + 1)
1027 range = function_units[unit].blockage_range_function (insn);
1028 /* We only cache the blockage range for one unit and then only if
1030 if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
1031 INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
1034 range = BLOCKAGE_RANGE (blockage);
1039 /* A vector indexed by function unit instance giving the last insn to use
1040 the unit. The value of the function unit instance index for unit U
1041 instance I is (U + I * FUNCTION_UNITS_SIZE). */
1042 static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
1044 /* A vector indexed by function unit instance giving the minimum time when
1045 the unit will unblock based on the maximum blockage cost. */
1046 static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
1048 /* A vector indexed by function unit number giving the number of insns
1049 that remain to use the unit. */
1050 static int unit_n_insns[FUNCTION_UNITS_SIZE];
1052 /* Reset the function unit state to the null state. */
1059 bzero (unit_last_insn, sizeof (unit_last_insn));
1060 bzero (unit_tick, sizeof (unit_tick));
1061 bzero (unit_n_insns, sizeof (unit_n_insns));
1064 /* Record an insn as one that will use the units encoded by UNIT. */
1066 __inline static void
1073 unit_n_insns[unit]++;
1075 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1076 if ((unit & 1) != 0)
1080 /* Return the actual hazard cost of executing INSN on the unit UNIT,
1081 instance INSTANCE at time CLOCK if the previous actual hazard cost
1085 actual_hazard_this_instance (unit, instance, insn, clock, cost)
1086 int unit, instance, clock, cost;
1090 int tick = unit_tick[instance];
1092 if (tick - clock > cost)
1094 /* The scheduler is operating in reverse, so INSN is the executing
1095 insn and the unit's last insn is the candidate insn. We want a
1096 more exact measure of the blockage if we execute INSN at CLOCK
1097 given when we committed the execution of the unit's last insn.
1099 The blockage value is given by either the unit's max blockage
1100 constant, blockage range function, or blockage function. Use
1101 the most exact form for the given unit. */
1103 if (function_units[unit].blockage_range_function)
1105 if (function_units[unit].blockage_function)
1106 tick += (function_units[unit].blockage_function
1107 (insn, unit_last_insn[instance])
1108 - function_units[unit].max_blockage);
1110 tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
1111 - function_units[unit].max_blockage);
1113 if (tick - clock > cost)
1114 cost = tick - clock;
1119 /* Record INSN as having begun execution on the units encoded by UNIT at
1122 __inline static void
1123 schedule_unit (unit, insn, clock)
1131 int instance = unit;
1132 #if MAX_MULTIPLICITY > 1
1133 /* Find the first free instance of the function unit and use that
1134 one. We assume that one is free. */
1135 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
1137 if (! actual_hazard_this_instance (unit, instance, insn, clock, 0))
1139 instance += FUNCTION_UNITS_SIZE;
1142 unit_last_insn[instance] = insn;
1143 unit_tick[instance] = (clock + function_units[unit].max_blockage);
1146 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1147 if ((unit & 1) != 0)
1148 schedule_unit (i, insn, clock);
1151 /* Return the actual hazard cost of executing INSN on the units encoded by
1152 UNIT at time CLOCK if the previous actual hazard cost was COST. */
1155 actual_hazard (unit, insn, clock, cost)
1156 int unit, clock, cost;
1163 /* Find the instance of the function unit with the minimum hazard. */
1164 int instance = unit;
1165 int best = instance;
1166 int best_cost = actual_hazard_this_instance (unit, instance, insn,
1170 #if MAX_MULTIPLICITY > 1
1171 if (best_cost > cost)
1173 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
1175 instance += FUNCTION_UNITS_SIZE;
1176 this_cost = actual_hazard_this_instance (unit, instance, insn,
1178 if (this_cost < best_cost)
1181 best_cost = this_cost;
1182 if (this_cost <= cost)
1188 cost = MAX (cost, best_cost);
1191 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1192 if ((unit & 1) != 0)
1193 cost = actual_hazard (i, insn, clock, cost);
1198 /* Return the potential hazard cost of executing an instruction on the
1199 units encoded by UNIT if the previous potential hazard cost was COST.
1200 An insn with a large blockage time is chosen in preference to one
1201 with a smaller time; an insn that uses a unit that is more likely
1202 to be used is chosen in preference to one with a unit that is less
1203 used. We are trying to minimize a subsequent actual hazard. */
1206 potential_hazard (unit, insn, cost)
1211 unsigned int minb, maxb;
1215 minb = maxb = function_units[unit].max_blockage;
1218 if (function_units[unit].blockage_range_function)
1220 maxb = minb = blockage_range (unit, insn);
1221 maxb = MAX_BLOCKAGE_COST (maxb);
1222 minb = MIN_BLOCKAGE_COST (minb);
1227 /* Make the number of instructions left dominate. Make the
1228 minimum delay dominate the maximum delay. If all these
1229 are the same, use the unit number to add an arbitrary
1230 ordering. Other terms can be added. */
1231 ncost = minb * 0x40 + maxb;
1232 ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
1239 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1240 if ((unit & 1) != 0)
1241 cost = potential_hazard (i, insn, cost);
1246 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
1247 This is the number of virtual cycles taken between instruction issue and
1248 instruction results. */
1251 insn_cost (insn, link, used)
1252 rtx insn, link, used;
1254 register int cost = INSN_COST (insn);
1258 recog_memoized (insn);
1260 /* A USE insn, or something else we don't need to understand.
1261 We can't pass these directly to result_ready_cost because it will
1262 trigger a fatal error for unrecognizable insns. */
1263 if (INSN_CODE (insn) < 0)
1265 INSN_COST (insn) = 1;
1270 cost = result_ready_cost (insn);
1275 INSN_COST (insn) = cost;
1279 /* A USE insn should never require the value used to be computed. This
1280 allows the computation of a function's result and parameter values to
1281 overlap the return and call. */
1282 recog_memoized (used);
1283 if (INSN_CODE (used) < 0)
1284 LINK_COST_FREE (link) = 1;
1286 /* If some dependencies vary the cost, compute the adjustment. Most
1287 commonly, the adjustment is complete: either the cost is ignored
1288 (in the case of an output- or anti-dependence), or the cost is
1289 unchanged. These values are cached in the link as LINK_COST_FREE
1290 and LINK_COST_ZERO. */
1292 if (LINK_COST_FREE (link))
1295 else if (! LINK_COST_ZERO (link))
1299 ADJUST_COST (used, link, insn, ncost);
1301 LINK_COST_FREE (link) = ncost = 1;
1303 LINK_COST_ZERO (link) = 1;
1310 /* Compute the priority number for INSN. */
1316 if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1320 int this_priority = INSN_PRIORITY (insn);
1323 if (this_priority > 0)
1324 return this_priority;
1328 /* Nonzero if these insns must be scheduled together. */
1329 if (SCHED_GROUP_P (insn))
1332 while (SCHED_GROUP_P (prev))
1334 prev = PREV_INSN (prev);
1335 INSN_REF_COUNT (prev) += 1;
1339 for (prev = LOG_LINKS (insn); prev; prev = XEXP (prev, 1))
1341 rtx x = XEXP (prev, 0);
1343 /* A dependence pointing to a note is always obsolete, because
1344 sched_analyze_insn will have created any necessary new dependences
1345 which replace it. Notes can be created when instructions are
1346 deleted by insn splitting, or by register allocation. */
1347 if (GET_CODE (x) == NOTE)
1349 remove_dependence (insn, x);
1353 /* Clear the link cost adjustment bits. */
1354 LINK_COST_FREE (prev) = 0;
1356 LINK_COST_ZERO (prev) = 0;
1359 /* This priority calculation was chosen because it results in the
1360 least instruction movement, and does not hurt the performance
1361 of the resulting code compared to the old algorithm.
1362 This makes the sched algorithm more stable, which results
1363 in better code, because there is less register pressure,
1364 cross jumping is more likely to work, and debugging is easier.
1366 When all instructions have a latency of 1, there is no need to
1367 move any instructions. Subtracting one here ensures that in such
1368 cases all instructions will end up with a priority of one, and
1369 hence no scheduling will be done.
1371 The original code did not subtract the one, and added the
1372 insn_cost of the current instruction to its priority (e.g.
1373 move the insn_cost call down to the end). */
1375 if (REG_NOTE_KIND (prev) == 0)
1376 /* Data dependence. */
1377 prev_priority = priority (x) + insn_cost (x, prev, insn) - 1;
1379 /* Anti or output dependence. Don't add the latency of this
1380 insn's result, because it isn't being used. */
1381 prev_priority = priority (x);
1383 if (prev_priority > max_priority)
1384 max_priority = prev_priority;
1385 INSN_REF_COUNT (x) += 1;
1388 prepare_unit (insn_unit (insn));
1389 INSN_PRIORITY (insn) = max_priority;
1390 return INSN_PRIORITY (insn);
1395 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
1396 them to the unused_*_list variables, so that they can be reused. */
1399 free_pending_lists ()
1401 register rtx link, prev_link;
1403 if (pending_read_insns)
1405 prev_link = pending_read_insns;
1406 link = XEXP (prev_link, 1);
1411 link = XEXP (link, 1);
1414 XEXP (prev_link, 1) = unused_insn_list;
1415 unused_insn_list = pending_read_insns;
1416 pending_read_insns = 0;
1419 if (pending_write_insns)
1421 prev_link = pending_write_insns;
1422 link = XEXP (prev_link, 1);
1427 link = XEXP (link, 1);
1430 XEXP (prev_link, 1) = unused_insn_list;
1431 unused_insn_list = pending_write_insns;
1432 pending_write_insns = 0;
1435 if (pending_read_mems)
1437 prev_link = pending_read_mems;
1438 link = XEXP (prev_link, 1);
1443 link = XEXP (link, 1);
1446 XEXP (prev_link, 1) = unused_expr_list;
1447 unused_expr_list = pending_read_mems;
1448 pending_read_mems = 0;
1451 if (pending_write_mems)
1453 prev_link = pending_write_mems;
1454 link = XEXP (prev_link, 1);
1459 link = XEXP (link, 1);
1462 XEXP (prev_link, 1) = unused_expr_list;
1463 unused_expr_list = pending_write_mems;
1464 pending_write_mems = 0;
1468 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
1469 The MEM is a memory reference contained within INSN, which we are saving
1470 so that we can do memory aliasing on it. */
1473 add_insn_mem_dependence (insn_list, mem_list, insn, mem)
1474 rtx *insn_list, *mem_list, insn, mem;
1478 if (unused_insn_list)
1480 link = unused_insn_list;
1481 unused_insn_list = XEXP (link, 1);
1484 link = rtx_alloc (INSN_LIST);
1485 XEXP (link, 0) = insn;
1486 XEXP (link, 1) = *insn_list;
1489 if (unused_expr_list)
1491 link = unused_expr_list;
1492 unused_expr_list = XEXP (link, 1);
1495 link = rtx_alloc (EXPR_LIST);
1496 XEXP (link, 0) = mem;
1497 XEXP (link, 1) = *mem_list;
1500 pending_lists_length++;
1503 /* Make a dependency between every memory reference on the pending lists
1504 and INSN, thus flushing the pending lists. */
1507 flush_pending_lists (insn)
1512 while (pending_read_insns)
1514 add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI);
1516 link = pending_read_insns;
1517 pending_read_insns = XEXP (pending_read_insns, 1);
1518 XEXP (link, 1) = unused_insn_list;
1519 unused_insn_list = link;
1521 link = pending_read_mems;
1522 pending_read_mems = XEXP (pending_read_mems, 1);
1523 XEXP (link, 1) = unused_expr_list;
1524 unused_expr_list = link;
1526 while (pending_write_insns)
1528 add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI);
1530 link = pending_write_insns;
1531 pending_write_insns = XEXP (pending_write_insns, 1);
1532 XEXP (link, 1) = unused_insn_list;
1533 unused_insn_list = link;
1535 link = pending_write_mems;
1536 pending_write_mems = XEXP (pending_write_mems, 1);
1537 XEXP (link, 1) = unused_expr_list;
1538 unused_expr_list = link;
1540 pending_lists_length = 0;
1542 if (last_pending_memory_flush)
1543 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1545 last_pending_memory_flush = insn;
1548 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
1549 by the write to the destination of X, and reads of everything mentioned. */
1552 sched_analyze_1 (x, insn)
1557 register rtx dest = SET_DEST (x);
1562 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
1563 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
1565 if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
1567 /* The second and third arguments are values read by this insn. */
1568 sched_analyze_2 (XEXP (dest, 1), insn);
1569 sched_analyze_2 (XEXP (dest, 2), insn);
1571 dest = SUBREG_REG (dest);
1574 if (GET_CODE (dest) == REG)
1576 register int offset, bit, i;
1578 regno = REGNO (dest);
1580 /* A hard reg in a wide mode may really be multiple registers.
1581 If so, mark all of them just like the first. */
1582 if (regno < FIRST_PSEUDO_REGISTER)
1584 i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
1589 for (u = reg_last_uses[regno+i]; u; u = XEXP (u, 1))
1590 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1591 reg_last_uses[regno + i] = 0;
1592 if (reg_last_sets[regno + i])
1593 add_dependence (insn, reg_last_sets[regno + i],
1595 reg_last_sets[regno + i] = insn;
1596 if ((call_used_regs[i] || global_regs[i])
1597 && last_function_call)
1598 /* Function calls clobber all call_used regs. */
1599 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1606 for (u = reg_last_uses[regno]; u; u = XEXP (u, 1))
1607 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1608 reg_last_uses[regno] = 0;
1609 if (reg_last_sets[regno])
1610 add_dependence (insn, reg_last_sets[regno], REG_DEP_OUTPUT);
1611 reg_last_sets[regno] = insn;
1613 /* Don't let it cross a call after scheduling if it doesn't
1614 already cross one. */
1615 if (reg_n_calls_crossed[regno] == 0 && last_function_call)
1616 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1619 else if (GET_CODE (dest) == MEM)
1621 /* Writing memory. */
1623 if (pending_lists_length > 32)
1625 /* Flush all pending reads and writes to prevent the pending lists
1626 from getting any larger. Insn scheduling runs too slowly when
1627 these lists get long. The number 32 was chosen because it
1628 seems like a reasonable number. When compiling GCC with itself,
1629 this flush occurs 8 times for sparc, and 10 times for m88k using
1631 flush_pending_lists (insn);
1635 rtx pending, pending_mem;
1637 pending = pending_read_insns;
1638 pending_mem = pending_read_mems;
1641 /* If a dependency already exists, don't create a new one. */
1642 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1643 if (anti_dependence (XEXP (pending_mem, 0), dest, insn))
1644 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
1646 pending = XEXP (pending, 1);
1647 pending_mem = XEXP (pending_mem, 1);
1650 pending = pending_write_insns;
1651 pending_mem = pending_write_mems;
1654 /* If a dependency already exists, don't create a new one. */
1655 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1656 if (output_dependence (XEXP (pending_mem, 0), dest))
1657 add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT);
1659 pending = XEXP (pending, 1);
1660 pending_mem = XEXP (pending_mem, 1);
1663 if (last_pending_memory_flush)
1664 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1666 add_insn_mem_dependence (&pending_write_insns, &pending_write_mems,
1669 sched_analyze_2 (XEXP (dest, 0), insn);
1672 /* Analyze reads. */
1673 if (GET_CODE (x) == SET)
1674 sched_analyze_2 (SET_SRC (x), insn);
1677 /* Analyze the uses of memory and registers in rtx X in INSN. */
1680 sched_analyze_2 (x, insn)
1686 register enum rtx_code code;
1692 code = GET_CODE (x);
1701 /* Ignore constants. Note that we must handle CONST_DOUBLE here
1702 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
1703 this does not mean that this insn is using cc0. */
1711 /* There may be a note before this insn now, but all notes will
1712 be removed before we actually try to schedule the insns, so
1713 it won't cause a problem later. We must avoid it here though. */
1715 /* User of CC0 depends on immediately preceding insn. */
1716 SCHED_GROUP_P (insn) = 1;
1718 /* Make a copy of all dependencies on the immediately previous insn,
1719 and add to this insn. This is so that all the dependencies will
1720 apply to the group. */
1722 prev = PREV_INSN (insn);
1723 while (GET_CODE (prev) == NOTE)
1724 prev = PREV_INSN (prev);
1726 for (link = LOG_LINKS (prev); link; link = XEXP (link, 1))
1727 add_dependence (insn, XEXP (link, 0), GET_MODE (link));
1735 int regno = REGNO (x);
1736 if (regno < FIRST_PSEUDO_REGISTER)
1740 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
1743 reg_last_uses[regno + i]
1744 = gen_rtx (INSN_LIST, VOIDmode,
1745 insn, reg_last_uses[regno + i]);
1746 if (reg_last_sets[regno + i])
1747 add_dependence (insn, reg_last_sets[regno + i], 0);
1748 if ((call_used_regs[regno + i] || global_regs[regno + i])
1749 && last_function_call)
1750 /* Function calls clobber all call_used regs. */
1751 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1756 reg_last_uses[regno]
1757 = gen_rtx (INSN_LIST, VOIDmode, insn, reg_last_uses[regno]);
1758 if (reg_last_sets[regno])
1759 add_dependence (insn, reg_last_sets[regno], 0);
1761 /* If the register does not already cross any calls, then add this
1762 insn to the sched_before_next_call list so that it will still
1763 not cross calls after scheduling. */
1764 if (reg_n_calls_crossed[regno] == 0)
1765 add_dependence (sched_before_next_call, insn, REG_DEP_ANTI);
1772 /* Reading memory. */
1774 rtx pending, pending_mem;
1776 pending = pending_read_insns;
1777 pending_mem = pending_read_mems;
1780 /* If a dependency already exists, don't create a new one. */
1781 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1782 if (read_dependence (XEXP (pending_mem, 0), x))
1783 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
1785 pending = XEXP (pending, 1);
1786 pending_mem = XEXP (pending_mem, 1);
1789 pending = pending_write_insns;
1790 pending_mem = pending_write_mems;
1793 /* If a dependency already exists, don't create a new one. */
1794 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1795 if (true_dependence (XEXP (pending_mem, 0), x))
1796 add_dependence (insn, XEXP (pending, 0), 0);
1798 pending = XEXP (pending, 1);
1799 pending_mem = XEXP (pending_mem, 1);
1801 if (last_pending_memory_flush)
1802 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1804 /* Always add these dependencies to pending_reads, since
1805 this insn may be followed by a write. */
1806 add_insn_mem_dependence (&pending_read_insns, &pending_read_mems,
1809 /* Take advantage of tail recursion here. */
1810 sched_analyze_2 (XEXP (x, 0), insn);
1816 case UNSPEC_VOLATILE:
1821 /* Traditional and volatile asm instructions must be considered to use
1822 and clobber all hard registers and all of memory. So must
1823 TRAP_IF and UNSPEC_VOLATILE operations. */
1824 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
1826 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1828 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
1829 if (GET_CODE (PATTERN (XEXP (u, 0))) != USE)
1830 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1831 reg_last_uses[i] = 0;
1832 if (reg_last_sets[i]
1833 && GET_CODE (PATTERN (reg_last_sets[i])) != USE)
1834 add_dependence (insn, reg_last_sets[i], 0);
1835 reg_last_sets[i] = insn;
1838 flush_pending_lists (insn);
1841 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
1842 We can not just fall through here since then we would be confused
1843 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
1844 traditional asms unlike their normal usage. */
1846 if (code == ASM_OPERANDS)
1848 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
1849 sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn);
1859 /* These read and modify the result; just consider them writes. */
1860 sched_analyze_1 (x, insn);
1864 /* Other cases: walk the insn. */
1865 fmt = GET_RTX_FORMAT (code);
1866 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1869 sched_analyze_2 (XEXP (x, i), insn);
1870 else if (fmt[i] == 'E')
1871 for (j = 0; j < XVECLEN (x, i); j++)
1872 sched_analyze_2 (XVECEXP (x, i, j), insn);
1876 /* Analyze an INSN with pattern X to find all dependencies. */
1879 sched_analyze_insn (x, insn)
1882 register RTX_CODE code = GET_CODE (x);
1885 if (code == SET || code == CLOBBER)
1886 sched_analyze_1 (x, insn);
1887 else if (code == PARALLEL)
1890 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
1892 code = GET_CODE (XVECEXP (x, 0, i));
1893 if (code == SET || code == CLOBBER)
1894 sched_analyze_1 (XVECEXP (x, 0, i), insn);
1896 sched_analyze_2 (XVECEXP (x, 0, i), insn);
1900 sched_analyze_2 (x, insn);
1902 /* Handle function calls. */
1903 if (GET_CODE (insn) == CALL_INSN)
1908 /* When scheduling instructions, we make sure calls don't lose their
1909 accompanying USE insns by depending them one on another in order. */
1911 prev_dep_insn = insn;
1912 dep_insn = PREV_INSN (insn);
1913 while (GET_CODE (dep_insn) == INSN
1914 && GET_CODE (PATTERN (dep_insn)) == USE)
1916 SCHED_GROUP_P (prev_dep_insn) = 1;
1918 /* Make a copy of all dependencies on dep_insn, and add to insn.
1919 This is so that all of the dependencies will apply to the
1922 for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1))
1923 add_dependence (insn, XEXP (link, 0), GET_MODE (link));
1925 prev_dep_insn = dep_insn;
1926 dep_insn = PREV_INSN (dep_insn);
1931 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
1932 for every dependency. */
1935 sched_analyze (head, tail)
1939 register int n_insns = 0;
1941 register int luid = 0;
1943 for (insn = head; ; insn = NEXT_INSN (insn))
1945 INSN_LUID (insn) = luid++;
1947 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
1949 sched_analyze_insn (PATTERN (insn), insn);
1952 else if (GET_CODE (insn) == CALL_INSN)
1958 /* Any instruction using a hard register which may get clobbered
1959 by a call needs to be marked as dependent on this call.
1960 This prevents a use of a hard return reg from being moved
1961 past a void call (i.e. it does not explicitly set the hard
1964 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1965 if (call_used_regs[i] || global_regs[i])
1967 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
1968 if (GET_CODE (PATTERN (XEXP (u, 0))) != USE)
1969 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1970 reg_last_uses[i] = 0;
1971 if (reg_last_sets[i]
1972 && GET_CODE (PATTERN (reg_last_sets[i])) != USE)
1973 add_dependence (insn, reg_last_sets[i], REG_DEP_ANTI);
1974 reg_last_sets[i] = insn;
1975 /* Insn, being a CALL_INSN, magically depends on
1976 `last_function_call' already. */
1979 /* For each insn which shouldn't cross a call, add a dependence
1980 between that insn and this call insn. */
1981 x = LOG_LINKS (sched_before_next_call);
1984 add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI);
1987 LOG_LINKS (sched_before_next_call) = 0;
1989 sched_analyze_insn (PATTERN (insn), insn);
1991 /* We don't need to flush memory for a function call which does
1992 not involve memory. */
1993 if (! CONST_CALL_P (insn))
1995 /* In the absence of interprocedural alias analysis,
1996 we must flush all pending reads and writes, and
1997 start new dependencies starting from here. */
1998 flush_pending_lists (insn);
2001 /* Depend this function call (actually, the user of this
2002 function call) on all hard register clobberage. */
2003 last_function_call = insn;
2012 /* Called when we see a set of a register. If death is true, then we are
2013 scanning backwards. Mark that register as unborn. If nobody says
2014 otherwise, that is how things will remain. If death is false, then we
2015 are scanning forwards. Mark that register as being born. */
2018 sched_note_set (b, x, death)
2023 register int regno, j;
2024 register rtx reg = SET_DEST (x);
2030 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART
2031 || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT)
2033 /* Must treat modification of just one hardware register of a multi-reg
2034 value or just a byte field of a register exactly the same way that
2035 mark_set_1 in flow.c does. */
2036 if (GET_CODE (reg) == ZERO_EXTRACT
2037 || GET_CODE (reg) == SIGN_EXTRACT
2038 || (GET_CODE (reg) == SUBREG
2039 && REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg)))
2042 reg = SUBREG_REG (reg);
2045 if (GET_CODE (reg) != REG)
2048 /* Global registers are always live, so the code below does not apply
2051 regno = REGNO (reg);
2052 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
2054 register int offset = regno / REGSET_ELT_BITS;
2055 register REGSET_ELT_TYPE bit
2056 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
2060 /* If we only set part of the register, then this set does not
2065 /* Try killing this register. */
2066 if (regno < FIRST_PSEUDO_REGISTER)
2068 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2071 offset = (regno + j) / REGSET_ELT_BITS;
2072 bit = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS);
2074 bb_live_regs[offset] &= ~bit;
2075 bb_dead_regs[offset] |= bit;
2080 bb_live_regs[offset] &= ~bit;
2081 bb_dead_regs[offset] |= bit;
2086 /* Make the register live again. */
2087 if (regno < FIRST_PSEUDO_REGISTER)
2089 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2092 offset = (regno + j) / REGSET_ELT_BITS;
2093 bit = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS);
2095 bb_live_regs[offset] |= bit;
2096 bb_dead_regs[offset] &= ~bit;
2101 bb_live_regs[offset] |= bit;
2102 bb_dead_regs[offset] &= ~bit;
2108 /* Macros and functions for keeping the priority queue sorted, and
2109 dealing with queueing and unqueueing of instructions. */
2111 #define SCHED_SORT(READY, NEW_READY, OLD_READY) \
2112 do { if ((NEW_READY) - (OLD_READY) == 1) \
2113 swap_sort (READY, NEW_READY); \
2114 else if ((NEW_READY) - (OLD_READY) > 1) \
2115 qsort (READY, NEW_READY, sizeof (rtx), rank_for_schedule); } \
2118 /* Returns a positive value if y is preferred; returns a negative value if
2119 x is preferred. Should never return 0, since that will make the sort
2123 rank_for_schedule (x, y)
2129 int tmp_class, tmp2_class;
2132 /* Choose the instruction with the highest priority, if different. */
2133 if (value = INSN_PRIORITY (tmp) - INSN_PRIORITY (tmp2))
2136 if (last_scheduled_insn)
2138 /* Classify the instructions into three classes:
2139 1) Data dependent on last schedule insn.
2140 2) Anti/Output dependent on last scheduled insn.
2141 3) Independent of last scheduled insn, or has latency of one.
2142 Choose the insn from the highest numbered class if different. */
2143 link = find_insn_list (tmp, LOG_LINKS (last_scheduled_insn));
2144 if (link == 0 || insn_cost (tmp, link, last_scheduled_insn) == 1)
2146 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
2151 link = find_insn_list (tmp2, LOG_LINKS (last_scheduled_insn));
2152 if (link == 0 || insn_cost (tmp2, link, last_scheduled_insn) == 1)
2154 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
2159 if (value = tmp_class - tmp2_class)
2163 /* If insns are equally good, sort by INSN_LUID (original insn order),
2164 so that we make the sort stable. This minimizes instruction movement,
2165 thus minimizing sched's effect on debugging and cross-jumping. */
2166 return INSN_LUID (tmp) - INSN_LUID (tmp2);
2169 /* Resort the array A in which only element at index N may be out of order. */
2171 __inline static void
2179 while (i >= 0 && rank_for_schedule (a+i, &insn) >= 0)
2187 static int max_priority;
2189 /* Add INSN to the insn queue so that it fires at least N_CYCLES
2190 before the currently executing insn. */
2192 __inline static void
2193 queue_insn (insn, n_cycles)
2197 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
2198 NEXT_INSN (insn) = insn_queue[next_q];
2199 insn_queue[next_q] = insn;
2203 /* Return nonzero if PAT is the pattern of an insn which makes a
2207 birthing_insn_p (pat)
2212 if (reload_completed == 1)
2215 if (GET_CODE (pat) == SET
2216 && GET_CODE (SET_DEST (pat)) == REG)
2218 rtx dest = SET_DEST (pat);
2219 int i = REGNO (dest);
2220 int offset = i / REGSET_ELT_BITS;
2221 REGSET_ELT_TYPE bit = (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS);
2223 /* It would be more accurate to use refers_to_regno_p or
2224 reg_mentioned_p to determine when the dest is not live before this
2227 if (bb_live_regs[offset] & bit)
2228 return (reg_n_sets[i] == 1);
2232 if (GET_CODE (pat) == PARALLEL)
2234 for (j = 0; j < XVECLEN (pat, 0); j++)
2235 if (birthing_insn_p (XVECEXP (pat, 0, j)))
2241 /* PREV is an insn that is ready to execute. Adjust its priority if that
2242 will help shorten register lifetimes. */
2244 __inline static void
2245 adjust_priority (prev)
2248 /* Trying to shorten register lives after reload has completed
2249 is useless and wrong. It gives inaccurate schedules. */
2250 if (reload_completed == 0)
2255 for (note = REG_NOTES (prev); note; note = XEXP (note, 1))
2256 if (REG_NOTE_KIND (note) == REG_DEAD)
2259 /* Defer scheduling insns which kill registers, since that
2260 shortens register lives. Prefer scheduling insns which
2261 make registers live for the same reason. */
2265 INSN_PRIORITY (prev) >>= 3;
2268 INSN_PRIORITY (prev) >>= 2;
2272 INSN_PRIORITY (prev) >>= 1;
2275 if (birthing_insn_p (PATTERN (prev)))
2277 int max = max_priority;
2279 if (max > INSN_PRIORITY (prev))
2280 INSN_PRIORITY (prev) = max;
2287 /* INSN is the "currently executing insn". Launch each insn which was
2288 waiting on INSN (in the backwards dataflow sense). READY is a
2289 vector of insns which are ready to fire. N_READY is the number of
2290 elements in READY. CLOCK is the current virtual cycle. */
2293 schedule_insn (insn, ready, n_ready, clock)
2300 int new_ready = n_ready;
2302 if (MAX_BLOCKAGE > 1)
2303 schedule_unit (insn_unit (insn), insn, clock);
2305 if (LOG_LINKS (insn) == 0)
2308 /* This is used by the function adjust_priority above. */
2310 max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn));
2312 max_priority = INSN_PRIORITY (insn);
2314 for (link = LOG_LINKS (insn); link != 0; link = XEXP (link, 1))
2316 rtx prev = XEXP (link, 0);
2317 int cost = insn_cost (prev, link, insn);
2319 if ((INSN_REF_COUNT (prev) -= 1) != 0)
2321 /* We satisfied one requirement to fire PREV. Record the earliest
2322 time when PREV can fire. No need to do this if the cost is 1,
2323 because PREV can fire no sooner than the next cycle. */
2325 INSN_TICK (prev) = MAX (INSN_TICK (prev), clock + cost);
2329 /* We satisfied the last requirement to fire PREV. Ensure that all
2330 timing requirements are satisfied. */
2331 if (INSN_TICK (prev) - clock > cost)
2332 cost = INSN_TICK (prev) - clock;
2334 /* Adjust the priority of PREV and either put it on the ready
2335 list or queue it. */
2336 adjust_priority (prev);
2338 ready[new_ready++] = prev;
2340 queue_insn (prev, cost);
2347 /* Given N_READY insns in the ready list READY at time CLOCK, queue
2348 those that are blocked due to function unit hazards and rearrange
2349 the remaining ones to minimize subsequent function unit hazards. */
2352 schedule_select (ready, n_ready, clock, file)
2357 int pri = INSN_PRIORITY (ready[0]);
2358 int i, j, k, q, cost, best_cost, best_insn = 0, new_ready = n_ready;
2361 /* Work down the ready list in groups of instructions with the same
2362 priority value. Queue insns in the group that are blocked and
2363 select among those that remain for the one with the largest
2364 potential hazard. */
2365 for (i = 0; i < n_ready; i = j)
2368 for (j = i + 1; j < n_ready; j++)
2369 if ((pri = INSN_PRIORITY (ready[j])) != opri)
2372 /* Queue insns in the group that are blocked. */
2373 for (k = i, q = 0; k < j; k++)
2376 if ((cost = actual_hazard (insn_unit (insn), insn, clock, 0)) != 0)
2380 queue_insn (insn, cost);
2382 fprintf (file, "\n;; blocking insn %d for %d cycles",
2383 INSN_UID (insn), cost);
2388 /* Check the next group if all insns were queued. */
2392 /* If more than one remains, select the first one with the largest
2393 potential hazard. */
2394 else if (j - i - q > 1)
2397 for (k = i; k < j; k++)
2399 if ((insn = ready[k]) == 0)
2401 if ((cost = potential_hazard (insn_unit (insn), insn, 0))
2409 /* We have found a suitable insn to schedule. */
2413 /* Move the best insn to be front of the ready list. */
2418 fprintf (file, ", now");
2419 for (i = 0; i < n_ready; i++)
2421 fprintf (file, " %d", INSN_UID (ready[i]));
2422 fprintf (file, "\n;; insn %d has a greater potential hazard",
2423 INSN_UID (ready[best_insn]));
2425 for (i = best_insn; i > 0; i--)
2428 ready[i-1] = ready[i];
2433 /* Compact the ready list. */
2434 if (new_ready < n_ready)
2435 for (i = j = 0; i < n_ready; i++)
2437 ready[j++] = ready[i];
2442 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
2446 create_reg_dead_note (reg, insn)
2449 rtx link = dead_notes;
2452 /* In theory, we should not end up with more REG_DEAD reg notes than we
2453 started with. In practice, this can occur as the result of bugs in
2454 flow, combine and/or sched. */
2459 link = rtx_alloc (EXPR_LIST);
2460 PUT_REG_NOTE_KIND (link, REG_DEAD);
2464 dead_notes = XEXP (dead_notes, 1);
2466 XEXP (link, 0) = reg;
2467 XEXP (link, 1) = REG_NOTES (insn);
2468 REG_NOTES (insn) = link;
2471 /* Subroutine on attach_deaths_insn--handles the recursive search
2472 through INSN. If SET_P is true, then x is being modified by the insn. */
2475 attach_deaths (x, insn, set_p)
2482 register enum rtx_code code;
2488 code = GET_CODE (x);
2500 /* Get rid of the easy cases first. */
2505 /* If the register dies in this insn, queue that note, and mark
2506 this register as needing to die. */
2507 /* This code is very similar to mark_used_1 (if set_p is false)
2508 and mark_set_1 (if set_p is true) in flow.c. */
2510 register int regno = REGNO (x);
2511 register int offset = regno / REGSET_ELT_BITS;
2512 register REGSET_ELT_TYPE bit
2513 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
2514 REGSET_ELT_TYPE all_needed = (old_live_regs[offset] & bit);
2515 REGSET_ELT_TYPE some_needed = (old_live_regs[offset] & bit);
2520 if (regno < FIRST_PSEUDO_REGISTER)
2524 n = HARD_REGNO_NREGS (regno, GET_MODE (x));
2527 some_needed |= (old_live_regs[(regno + n) / REGSET_ELT_BITS]
2528 & ((REGSET_ELT_TYPE) 1
2529 << ((regno + n) % REGSET_ELT_BITS)));
2530 all_needed &= (old_live_regs[(regno + n) / REGSET_ELT_BITS]
2531 & ((REGSET_ELT_TYPE) 1
2532 << ((regno + n) % REGSET_ELT_BITS)));
2536 /* If it wasn't live before we started, then add a REG_DEAD note.
2537 We must check the previous lifetime info not the current info,
2538 because we may have to execute this code several times, e.g.
2539 once for a clobber (which doesn't add a note) and later
2540 for a use (which does add a note).
2542 Always make the register live. We must do this even if it was
2543 live before, because this may be an insn which sets and uses
2544 the same register, in which case the register has already been
2545 killed, so we must make it live again.
2547 Global registers are always live, and should never have a REG_DEAD
2548 note added for them, so none of the code below applies to them. */
2550 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
2552 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2553 STACK_POINTER_REGNUM, since these are always considered to be
2554 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2555 if (regno != FRAME_POINTER_REGNUM
2556 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2557 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
2559 && regno != STACK_POINTER_REGNUM)
2561 if (! all_needed && ! dead_or_set_p (insn, x))
2563 /* If none of the words in X is needed, make a REG_DEAD
2564 note. Otherwise, we must make partial REG_DEAD
2567 create_reg_dead_note (x, insn);
2572 /* Don't make a REG_DEAD note for a part of a
2573 register that is set in the insn. */
2574 for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1;
2576 if ((old_live_regs[(regno + i) / REGSET_ELT_BITS]
2577 & ((REGSET_ELT_TYPE) 1
2578 << ((regno +i) % REGSET_ELT_BITS))) == 0
2579 && ! dead_or_set_regno_p (insn, regno + i))
2580 create_reg_dead_note (gen_rtx (REG, word_mode,
2587 if (regno < FIRST_PSEUDO_REGISTER)
2589 int j = HARD_REGNO_NREGS (regno, GET_MODE (x));
2592 offset = (regno + j) / REGSET_ELT_BITS;
2594 = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS);
2596 bb_dead_regs[offset] &= ~bit;
2597 bb_live_regs[offset] |= bit;
2602 bb_dead_regs[offset] &= ~bit;
2603 bb_live_regs[offset] |= bit;
2610 /* Handle tail-recursive case. */
2611 attach_deaths (XEXP (x, 0), insn, 0);
2615 case STRICT_LOW_PART:
2616 /* These two cases preserve the value of SET_P, so handle them
2618 attach_deaths (XEXP (x, 0), insn, set_p);
2623 /* This case preserves the value of SET_P for the first operand, but
2624 clears it for the other two. */
2625 attach_deaths (XEXP (x, 0), insn, set_p);
2626 attach_deaths (XEXP (x, 1), insn, 0);
2627 attach_deaths (XEXP (x, 2), insn, 0);
2631 /* Other cases: walk the insn. */
2632 fmt = GET_RTX_FORMAT (code);
2633 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2636 attach_deaths (XEXP (x, i), insn, 0);
2637 else if (fmt[i] == 'E')
2638 for (j = 0; j < XVECLEN (x, i); j++)
2639 attach_deaths (XVECEXP (x, i, j), insn, 0);
2644 /* After INSN has executed, add register death notes for each register
2645 that is dead after INSN. */
2648 attach_deaths_insn (insn)
2651 rtx x = PATTERN (insn);
2652 register RTX_CODE code = GET_CODE (x);
2656 attach_deaths (SET_SRC (x), insn, 0);
2658 /* A register might die here even if it is the destination, e.g.
2659 it is the target of a volatile read and is otherwise unused.
2660 Hence we must always call attach_deaths for the SET_DEST. */
2661 attach_deaths (SET_DEST (x), insn, 1);
2663 else if (code == PARALLEL)
2666 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2668 code = GET_CODE (XVECEXP (x, 0, i));
2671 attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0);
2673 attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1);
2675 /* Flow does not add REG_DEAD notes to registers that die in
2676 clobbers, so we can't either. */
2677 else if (code != CLOBBER)
2678 attach_deaths (XVECEXP (x, 0, i), insn, 0);
2681 /* Flow does not add REG_DEAD notes to registers that die in
2682 clobbers, so we can't either. */
2683 else if (code != CLOBBER)
2684 attach_deaths (x, insn, 0);
2687 /* Delete notes beginning with INSN and maybe put them in the chain
2688 of notes ended by NOTE_LIST.
2689 Returns the insn following the notes. */
2692 unlink_notes (insn, tail)
2695 rtx prev = PREV_INSN (insn);
2697 while (insn != tail && GET_CODE (insn) == NOTE)
2699 rtx next = NEXT_INSN (insn);
2700 /* Delete the note from its current position. */
2702 NEXT_INSN (prev) = next;
2704 PREV_INSN (next) = prev;
2706 if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
2707 /* Record line-number notes so they can be reused. */
2708 LINE_NOTE (insn) = insn;
2711 /* Insert the note at the end of the notes list. */
2712 PREV_INSN (insn) = note_list;
2714 NEXT_INSN (note_list) = insn;
2723 /* Data structure for keeping track of register information
2724 during that register's life. */
2728 short offset; short bit;
2729 short live_length; short calls_crossed;
2732 /* Constructor for `sometimes' data structure. */
2735 new_sometimes_live (regs_sometimes_live, offset, bit, sometimes_max)
2736 struct sometimes *regs_sometimes_live;
2740 register struct sometimes *p;
2741 register int regno = offset * REGSET_ELT_BITS + bit;
2744 /* There should never be a register greater than max_regno here. If there
2745 is, it means that a define_split has created a new pseudo reg. This
2746 is not allowed, since there will not be flow info available for any
2747 new register, so catch the error here. */
2748 if (regno >= max_regno)
2751 p = ®s_sometimes_live[sometimes_max];
2755 p->calls_crossed = 0;
2757 return sometimes_max;
2760 /* Count lengths of all regs we are currently tracking,
2761 and find new registers no longer live. */
2764 finish_sometimes_live (regs_sometimes_live, sometimes_max)
2765 struct sometimes *regs_sometimes_live;
2770 for (i = 0; i < sometimes_max; i++)
2772 register struct sometimes *p = ®s_sometimes_live[i];
2775 regno = p->offset * REGSET_ELT_BITS + p->bit;
2777 sched_reg_live_length[regno] += p->live_length;
2778 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
2782 /* Use modified list scheduling to rearrange insns in basic block
2783 B. FILE, if nonzero, is where we dump interesting output about
2787 schedule_block (b, file)
2794 int i, j, n_ready = 0, new_ready, n_insns = 0;
2795 int sched_n_insns = 0;
2797 #define NEED_NOTHING 0
2802 /* HEAD and TAIL delimit the region being scheduled. */
2803 rtx head = basic_block_head[b];
2804 rtx tail = basic_block_end[b];
2805 /* PREV_HEAD and NEXT_TAIL are the boundaries of the insns
2806 being scheduled. When the insns have been ordered,
2807 these insns delimit where the new insns are to be
2808 spliced back into the insn chain. */
2812 /* Keep life information accurate. */
2813 register struct sometimes *regs_sometimes_live;
2817 fprintf (file, ";;\t -- basic block number %d from %d to %d --\n",
2818 b, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b]));
2821 reg_last_uses = (rtx *) alloca (i * sizeof (rtx));
2822 bzero (reg_last_uses, i * sizeof (rtx));
2823 reg_last_sets = (rtx *) alloca (i * sizeof (rtx));
2824 bzero (reg_last_sets, i * sizeof (rtx));
2827 /* Remove certain insns at the beginning from scheduling,
2828 by advancing HEAD. */
2830 /* At the start of a function, before reload has run, don't delay getting
2831 parameters from hard registers into pseudo registers. */
2832 if (reload_completed == 0 && b == 0)
2835 && GET_CODE (head) == NOTE
2836 && NOTE_LINE_NUMBER (head) != NOTE_INSN_FUNCTION_BEG)
2837 head = NEXT_INSN (head);
2839 && GET_CODE (head) == INSN
2840 && GET_CODE (PATTERN (head)) == SET)
2842 rtx src = SET_SRC (PATTERN (head));
2843 while (GET_CODE (src) == SUBREG
2844 || GET_CODE (src) == SIGN_EXTEND
2845 || GET_CODE (src) == ZERO_EXTEND
2846 || GET_CODE (src) == SIGN_EXTRACT
2847 || GET_CODE (src) == ZERO_EXTRACT)
2848 src = XEXP (src, 0);
2849 if (GET_CODE (src) != REG
2850 || REGNO (src) >= FIRST_PSEUDO_REGISTER)
2852 /* Keep this insn from ever being scheduled. */
2853 INSN_REF_COUNT (head) = 1;
2854 head = NEXT_INSN (head);
2858 /* Don't include any notes or labels at the beginning of the
2859 basic block, or notes at the ends of basic blocks. */
2860 while (head != tail)
2862 if (GET_CODE (head) == NOTE)
2863 head = NEXT_INSN (head);
2864 else if (GET_CODE (tail) == NOTE)
2865 tail = PREV_INSN (tail);
2866 else if (GET_CODE (head) == CODE_LABEL)
2867 head = NEXT_INSN (head);
2870 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
2871 to schedule this block. */
2873 && (GET_CODE (head) == NOTE || GET_CODE (head) == CODE_LABEL))
2877 /* This short-cut doesn't work. It does not count call insns crossed by
2878 registers in reg_sometimes_live. It does not mark these registers as
2879 dead if they die in this block. It does not mark these registers live
2880 (or create new reg_sometimes_live entries if necessary) if they are born
2883 The easy solution is to just always schedule a block. This block only
2884 has one insn, so this won't slow down this pass by much. */
2890 /* Now HEAD through TAIL are the insns actually to be rearranged;
2891 Let PREV_HEAD and NEXT_TAIL enclose them. */
2892 prev_head = PREV_INSN (head);
2893 next_tail = NEXT_INSN (tail);
2895 /* Initialize basic block data structures. */
2897 pending_read_insns = 0;
2898 pending_read_mems = 0;
2899 pending_write_insns = 0;
2900 pending_write_mems = 0;
2901 pending_lists_length = 0;
2902 last_pending_memory_flush = 0;
2903 last_function_call = 0;
2904 last_scheduled_insn = 0;
2906 LOG_LINKS (sched_before_next_call) = 0;
2908 n_insns += sched_analyze (head, tail);
2911 free_pending_lists ();
2915 /* Allocate vector to hold insns to be rearranged (except those
2916 insns which are controlled by an insn with SCHED_GROUP_P set).
2917 All these insns are included between ORIG_HEAD and ORIG_TAIL,
2918 as those variables ultimately are set up. */
2919 ready = (rtx *) alloca ((n_insns+1) * sizeof (rtx));
2921 /* TAIL is now the last of the insns to be rearranged.
2922 Put those insns into the READY vector. */
2925 /* For all branches, calls, uses, and cc0 setters, force them to remain
2926 in order at the end of the block by adding dependencies and giving
2927 the last a high priority. There may be notes present, and prev_head
2930 Branches must obviously remain at the end. Calls should remain at the
2931 end since moving them results in worse register allocation. Uses remain
2932 at the end to ensure proper register allocation. cc0 setters remaim
2933 at the end because they can't be moved away from their cc0 user. */
2935 while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN
2936 || (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
2938 || sets_cc0_p (PATTERN (insn))
2940 || GET_CODE (insn) == NOTE)
2942 if (GET_CODE (insn) != NOTE)
2947 ready[n_ready++] = insn;
2948 INSN_PRIORITY (insn) = TAIL_PRIORITY - i;
2949 INSN_REF_COUNT (insn) = 0;
2951 else if (! find_insn_list (insn, LOG_LINKS (last)))
2953 add_dependence (last, insn, REG_DEP_ANTI);
2954 INSN_REF_COUNT (insn)++;
2958 /* Skip over insns that are part of a group. */
2959 while (SCHED_GROUP_P (insn))
2961 insn = prev_nonnote_insn (insn);
2966 insn = PREV_INSN (insn);
2967 /* Don't overrun the bounds of the basic block. */
2968 if (insn == prev_head)
2972 /* Assign priorities to instructions. Also check whether they
2973 are in priority order already. If so then I will be nonnegative.
2974 We use this shortcut only before reloading. */
2976 i = reload_completed ? DONE_PRIORITY : MAX_PRIORITY;
2979 for (; insn != prev_head; insn = PREV_INSN (insn))
2981 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2984 if (INSN_REF_COUNT (insn) == 0)
2987 ready[n_ready++] = insn;
2990 /* Make this dependent on the last of the instructions
2991 that must remain in order at the end of the block. */
2992 add_dependence (last, insn, REG_DEP_ANTI);
2993 INSN_REF_COUNT (insn) = 1;
2996 if (SCHED_GROUP_P (insn))
2998 while (SCHED_GROUP_P (insn))
3000 insn = PREV_INSN (insn);
3001 while (GET_CODE (insn) == NOTE)
3002 insn = PREV_INSN (insn);
3010 if (INSN_PRIORITY (insn) < i)
3011 i = INSN_PRIORITY (insn);
3012 else if (INSN_PRIORITY (insn) > i)
3019 /* This short-cut doesn't work. It does not count call insns crossed by
3020 registers in reg_sometimes_live. It does not mark these registers as
3021 dead if they die in this block. It does not mark these registers live
3022 (or create new reg_sometimes_live entries if necessary) if they are born
3025 The easy solution is to just always schedule a block. These blocks tend
3026 to be very short, so this doesn't slow down this pass by much. */
3028 /* If existing order is good, don't bother to reorder. */
3029 if (i != DONE_PRIORITY)
3032 fprintf (file, ";; already scheduled\n");
3034 if (reload_completed == 0)
3036 for (i = 0; i < sometimes_max; i++)
3037 regs_sometimes_live[i].live_length += n_insns;
3039 finish_sometimes_live (regs_sometimes_live, sometimes_max);
3041 free_pending_lists ();
3046 /* Scan all the insns to be scheduled, removing NOTE insns
3047 and register death notes.
3048 Line number NOTE insns end up in NOTE_LIST.
3049 Register death notes end up in DEAD_NOTES.
3051 Recreate the register life information for the end of this basic
3054 if (reload_completed == 0)
3056 bcopy (basic_block_live_at_start[b], bb_live_regs, regset_bytes);
3057 bzero (bb_dead_regs, regset_bytes);
3061 /* This is the first block in the function. There may be insns
3062 before head that we can't schedule. We still need to examine
3063 them though for accurate register lifetime analysis. */
3065 /* We don't want to remove any REG_DEAD notes as the code below
3068 for (insn = basic_block_head[b]; insn != head;
3069 insn = NEXT_INSN (insn))
3070 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3072 /* See if the register gets born here. */
3073 /* We must check for registers being born before we check for
3074 registers dying. It is possible for a register to be born
3075 and die in the same insn, e.g. reading from a volatile
3076 memory location into an otherwise unused register. Such
3077 a register must be marked as dead after this insn. */
3078 if (GET_CODE (PATTERN (insn)) == SET
3079 || GET_CODE (PATTERN (insn)) == CLOBBER)
3080 sched_note_set (b, PATTERN (insn), 0);
3081 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3084 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3085 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3086 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3087 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3089 /* ??? This code is obsolete and should be deleted. It
3090 is harmless though, so we will leave it in for now. */
3091 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3092 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
3093 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3096 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
3098 if ((REG_NOTE_KIND (link) == REG_DEAD
3099 || REG_NOTE_KIND (link) == REG_UNUSED)
3100 /* Verify that the REG_NOTE has a legal value. */
3101 && GET_CODE (XEXP (link, 0)) == REG)
3103 register int regno = REGNO (XEXP (link, 0));
3104 register int offset = regno / REGSET_ELT_BITS;
3105 register REGSET_ELT_TYPE bit
3106 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
3108 if (regno < FIRST_PSEUDO_REGISTER)
3110 int j = HARD_REGNO_NREGS (regno,
3111 GET_MODE (XEXP (link, 0)));
3114 offset = (regno + j) / REGSET_ELT_BITS;
3115 bit = ((REGSET_ELT_TYPE) 1
3116 << ((regno + j) % REGSET_ELT_BITS));
3118 bb_live_regs[offset] &= ~bit;
3119 bb_dead_regs[offset] |= bit;
3124 bb_live_regs[offset] &= ~bit;
3125 bb_dead_regs[offset] |= bit;
3133 /* If debugging information is being produced, keep track of the line
3134 number notes for each insn. */
3135 if (write_symbols != NO_DEBUG)
3137 /* We must use the true line number for the first insn in the block
3138 that was computed and saved at the start of this pass. We can't
3139 use the current line number, because scheduling of the previous
3140 block may have changed the current line number. */
3141 rtx line = line_note_head[b];
3143 for (insn = basic_block_head[b];
3145 insn = NEXT_INSN (insn))
3146 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
3149 LINE_NOTE (insn) = line;
3152 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
3154 rtx prev, next, link;
3156 /* Farm out notes. This is needed to keep the debugger from
3157 getting completely deranged. */
3158 if (GET_CODE (insn) == NOTE)
3161 insn = unlink_notes (insn, next_tail);
3166 if (insn == next_tail)
3170 if (reload_completed == 0
3171 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3173 /* See if the register gets born here. */
3174 /* We must check for registers being born before we check for
3175 registers dying. It is possible for a register to be born and
3176 die in the same insn, e.g. reading from a volatile memory
3177 location into an otherwise unused register. Such a register
3178 must be marked as dead after this insn. */
3179 if (GET_CODE (PATTERN (insn)) == SET
3180 || GET_CODE (PATTERN (insn)) == CLOBBER)
3181 sched_note_set (b, PATTERN (insn), 0);
3182 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3185 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3186 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3187 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3188 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3190 /* ??? This code is obsolete and should be deleted. It
3191 is harmless though, so we will leave it in for now. */
3192 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3193 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
3194 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3197 /* Need to know what registers this insn kills. */
3198 for (prev = 0, link = REG_NOTES (insn); link; link = next)
3202 next = XEXP (link, 1);
3203 if ((REG_NOTE_KIND (link) == REG_DEAD
3204 || REG_NOTE_KIND (link) == REG_UNUSED)
3205 /* Verify that the REG_NOTE has a legal value. */
3206 && GET_CODE (XEXP (link, 0)) == REG)
3208 register int regno = REGNO (XEXP (link, 0));
3209 register int offset = regno / REGSET_ELT_BITS;
3210 register REGSET_ELT_TYPE bit
3211 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
3213 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
3215 if (REG_NOTE_KIND (link) == REG_DEAD)
3218 XEXP (prev, 1) = next;
3220 REG_NOTES (insn) = next;
3221 XEXP (link, 1) = dead_notes;
3227 if (regno < FIRST_PSEUDO_REGISTER)
3229 int j = HARD_REGNO_NREGS (regno,
3230 GET_MODE (XEXP (link, 0)));
3233 offset = (regno + j) / REGSET_ELT_BITS;
3234 bit = ((REGSET_ELT_TYPE) 1
3235 << ((regno + j) % REGSET_ELT_BITS));
3237 bb_live_regs[offset] &= ~bit;
3238 bb_dead_regs[offset] |= bit;
3243 bb_live_regs[offset] &= ~bit;
3244 bb_dead_regs[offset] |= bit;
3253 if (reload_completed == 0)
3255 /* Keep track of register lives. */
3256 old_live_regs = (regset) alloca (regset_bytes);
3258 = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes));
3261 /* Start with registers live at end. */
3262 for (j = 0; j < regset_size; j++)
3264 REGSET_ELT_TYPE live = bb_live_regs[j];
3265 old_live_regs[j] = live;
3268 register REGSET_ELT_TYPE bit;
3269 for (bit = 0; bit < REGSET_ELT_BITS; bit++)
3270 if (live & ((REGSET_ELT_TYPE) 1 << bit))
3271 sometimes_max = new_sometimes_live (regs_sometimes_live, j,
3272 bit, sometimes_max);
3277 SCHED_SORT (ready, n_ready, 1);
3281 fprintf (file, ";; ready list initially:\n;; ");
3282 for (i = 0; i < n_ready; i++)
3283 fprintf (file, "%d ", INSN_UID (ready[i]));
3284 fprintf (file, "\n\n");
3286 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
3287 if (INSN_PRIORITY (insn) > 0)
3288 fprintf (file, ";; insn[%4d]: priority = %4d, ref_count = %4d\n",
3289 INSN_UID (insn), INSN_PRIORITY (insn),
3290 INSN_REF_COUNT (insn));
3293 /* Now HEAD and TAIL are going to become disconnected
3294 entirely from the insn chain. */
3297 /* Q_SIZE will always be zero here. */
3298 q_ptr = 0; clock = 0;
3299 bzero (insn_queue, sizeof (insn_queue));
3301 /* Now, perform list scheduling. */
3303 /* Where we start inserting insns is after TAIL. */
3306 new_needs = (NEXT_INSN (prev_head) == basic_block_head[b]
3307 ? NEED_HEAD : NEED_NOTHING);
3308 if (PREV_INSN (next_tail) == basic_block_end[b])
3309 new_needs |= NEED_TAIL;
3311 new_ready = n_ready;
3312 while (sched_n_insns < n_insns)
3314 q_ptr = NEXT_Q (q_ptr); clock++;
3316 /* Add all pending insns that can be scheduled without stalls to the
3318 for (insn = insn_queue[q_ptr]; insn; insn = NEXT_INSN (insn))
3321 fprintf (file, ";; launching %d before %d with no stalls at T-%d\n",
3322 INSN_UID (insn), INSN_UID (last), clock);
3323 ready[new_ready++] = insn;
3326 insn_queue[q_ptr] = 0;
3328 /* If there are no ready insns, stall until one is ready and add all
3329 of the pending insns at that point to the ready list. */
3332 register int stalls;
3334 for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++)
3335 if (insn = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])
3337 for (; insn; insn = NEXT_INSN (insn))
3340 fprintf (file, ";; launching %d before %d with %d stalls at T-%d\n",
3341 INSN_UID (insn), INSN_UID (last), stalls, clock);
3342 ready[new_ready++] = insn;
3345 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
3349 q_ptr = NEXT_Q_AFTER (q_ptr, stalls); clock += stalls;
3352 /* There should be some instructions waiting to fire. */
3358 fprintf (file, ";; ready list at T-%d:", clock);
3359 for (i = 0; i < new_ready; i++)
3360 fprintf (file, " %d (%x)",
3361 INSN_UID (ready[i]), INSN_PRIORITY (ready[i]));
3364 /* Sort the ready list and choose the best insn to schedule. Select
3365 which insn should issue in this cycle and queue those that are
3366 blocked by function unit hazards.
3368 N_READY holds the number of items that were scheduled the last time,
3369 minus the one instruction scheduled on the last loop iteration; it
3370 is not modified for any other reason in this loop. */
3372 SCHED_SORT (ready, new_ready, n_ready);
3373 if (MAX_BLOCKAGE > 1)
3375 new_ready = schedule_select (ready, new_ready, clock, file);
3379 fprintf (file, "\n");
3383 n_ready = new_ready;
3384 last_scheduled_insn = insn = ready[0];
3386 /* The first insn scheduled becomes the new tail. */
3392 fprintf (file, ", now");
3393 for (i = 0; i < n_ready; i++)
3394 fprintf (file, " %d", INSN_UID (ready[i]));
3395 fprintf (file, "\n");
3398 if (DONE_PRIORITY_P (insn))
3401 if (reload_completed == 0)
3403 /* Process this insn, and each insn linked to this one which must
3404 be immediately output after this insn. */
3407 /* First we kill registers set by this insn, and then we
3408 make registers used by this insn live. This is the opposite
3409 order used above because we are traversing the instructions
3412 /* Strictly speaking, we should scan REG_UNUSED notes and make
3413 every register mentioned there live, however, we will just
3414 kill them again immediately below, so there doesn't seem to
3415 be any reason why we bother to do this. */
3417 /* See if this is the last notice we must take of a register. */
3418 if (GET_CODE (PATTERN (insn)) == SET
3419 || GET_CODE (PATTERN (insn)) == CLOBBER)
3420 sched_note_set (b, PATTERN (insn), 1);
3421 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3424 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3425 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3426 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3427 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 1);
3430 /* This code keeps life analysis information up to date. */
3431 if (GET_CODE (insn) == CALL_INSN)
3433 register struct sometimes *p;
3435 /* A call kills all call used and global registers, except
3436 for those mentioned in the call pattern which will be
3437 made live again later. */
3438 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3439 if (call_used_regs[i] || global_regs[i])
3441 register int offset = i / REGSET_ELT_BITS;
3442 register REGSET_ELT_TYPE bit
3443 = (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS);
3445 bb_live_regs[offset] &= ~bit;
3446 bb_dead_regs[offset] |= bit;
3449 /* Regs live at the time of a call instruction must not
3450 go in a register clobbered by calls. Record this for
3451 all regs now live. Note that insns which are born or
3452 die in a call do not cross a call, so this must be done
3453 after the killings (above) and before the births
3455 p = regs_sometimes_live;
3456 for (i = 0; i < sometimes_max; i++, p++)
3457 if (bb_live_regs[p->offset]
3458 & ((REGSET_ELT_TYPE) 1 << p->bit))
3459 p->calls_crossed += 1;
3462 /* Make every register used live, and add REG_DEAD notes for
3463 registers which were not live before we started. */
3464 attach_deaths_insn (insn);
3466 /* Find registers now made live by that instruction. */
3467 for (i = 0; i < regset_size; i++)
3469 REGSET_ELT_TYPE diff = bb_live_regs[i] & ~old_live_regs[i];
3473 old_live_regs[i] |= diff;
3474 for (bit = 0; bit < REGSET_ELT_BITS; bit++)
3475 if (diff & ((REGSET_ELT_TYPE) 1 << bit))
3477 = new_sometimes_live (regs_sometimes_live, i, bit,
3482 /* Count lengths of all regs we are worrying about now,
3483 and handle registers no longer live. */
3485 for (i = 0; i < sometimes_max; i++)
3487 register struct sometimes *p = ®s_sometimes_live[i];
3488 int regno = p->offset*REGSET_ELT_BITS + p->bit;
3490 p->live_length += 1;
3492 if ((bb_live_regs[p->offset]
3493 & ((REGSET_ELT_TYPE) 1 << p->bit)) == 0)
3495 /* This is the end of one of this register's lifetime
3496 segments. Save the lifetime info collected so far,
3497 and clear its bit in the old_live_regs entry. */
3498 sched_reg_live_length[regno] += p->live_length;
3499 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
3500 old_live_regs[p->offset]
3501 &= ~((REGSET_ELT_TYPE) 1 << p->bit);
3503 /* Delete the reg_sometimes_live entry for this reg by
3504 copying the last entry over top of it. */
3505 *p = regs_sometimes_live[--sometimes_max];
3506 /* ...and decrement i so that this newly copied entry
3507 will be processed. */
3513 insn = PREV_INSN (insn);
3515 while (SCHED_GROUP_P (link));
3517 /* Set INSN back to the insn we are scheduling now. */
3521 /* Schedule INSN. Remove it from the ready list. */
3526 NEXT_INSN (insn) = last;
3527 PREV_INSN (last) = insn;
3530 /* Everything that precedes INSN now either becomes "ready", if
3531 it can execute immediately before INSN, or "pending", if
3532 there must be a delay. Give INSN high enough priority that
3533 at least one (maybe more) reg-killing insns can be launched
3534 ahead of all others. Mark INSN as scheduled by changing its
3536 INSN_PRIORITY (insn) = LAUNCH_PRIORITY;
3537 new_ready = schedule_insn (insn, ready, n_ready, clock);
3538 INSN_PRIORITY (insn) = DONE_PRIORITY;
3540 /* Schedule all prior insns that must not be moved. */
3541 if (SCHED_GROUP_P (insn))
3543 /* Disable these insns from being launched. */
3545 while (SCHED_GROUP_P (link))
3547 /* Disable these insns from being launched by anybody. */
3548 link = PREV_INSN (link);
3549 INSN_REF_COUNT (link) = 0;
3552 /* None of these insns can move forward into delay slots. */
3553 while (SCHED_GROUP_P (insn))
3555 insn = PREV_INSN (insn);
3556 new_ready = schedule_insn (insn, ready, new_ready, clock);
3557 INSN_PRIORITY (insn) = DONE_PRIORITY;
3560 NEXT_INSN (insn) = last;
3561 PREV_INSN (last) = insn;
3569 if (reload_completed == 0)
3570 finish_sometimes_live (regs_sometimes_live, sometimes_max);
3572 /* HEAD is now the first insn in the chain of insns that
3573 been scheduled by the loop above.
3574 TAIL is the last of those insns. */
3577 /* NOTE_LIST is the end of a chain of notes previously found
3578 among the insns. Insert them at the beginning of the insns. */
3581 rtx note_head = note_list;
3582 while (PREV_INSN (note_head))
3583 note_head = PREV_INSN (note_head);
3585 PREV_INSN (head) = note_list;
3586 NEXT_INSN (note_list) = head;
3590 /* In theory, there should be no REG_DEAD notes leftover at the end.
3591 In practice, this can occur as the result of bugs in flow, combine.c,
3592 and/or sched.c. The values of the REG_DEAD notes remaining are
3593 meaningless, because dead_notes is just used as a free list. */
3595 if (dead_notes != 0)
3599 if (new_needs & NEED_HEAD)
3600 basic_block_head[b] = head;
3601 PREV_INSN (head) = prev_head;
3602 NEXT_INSN (prev_head) = head;
3604 if (new_needs & NEED_TAIL)
3605 basic_block_end[b] = tail;
3606 NEXT_INSN (tail) = next_tail;
3607 PREV_INSN (next_tail) = tail;
3609 /* Restore the line-number notes of each insn. */
3610 if (write_symbols != NO_DEBUG)
3612 rtx line, note, prev, new;
3615 head = basic_block_head[b];
3616 next_tail = NEXT_INSN (basic_block_end[b]);
3618 /* Determine the current line-number. We want to know the current
3619 line number of the first insn of the block here, in case it is
3620 different from the true line number that was saved earlier. If
3621 different, then we need a line number note before the first insn
3622 of this block. If it happens to be the same, then we don't want to
3623 emit another line number note here. */
3624 for (line = head; line; line = PREV_INSN (line))
3625 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
3628 /* Walk the insns keeping track of the current line-number and inserting
3629 the line-number notes as needed. */
3630 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
3631 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
3633 else if (! (GET_CODE (insn) == NOTE
3634 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
3635 && (note = LINE_NOTE (insn)) != 0
3638 || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
3639 || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
3642 prev = PREV_INSN (insn);
3643 if (LINE_NOTE (note))
3645 /* Re-use the original line-number note. */
3646 LINE_NOTE (note) = 0;
3647 PREV_INSN (note) = prev;
3648 NEXT_INSN (prev) = note;
3649 PREV_INSN (insn) = note;
3650 NEXT_INSN (note) = insn;
3655 new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
3656 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
3660 fprintf (file, ";; added %d line-number notes\n", notes);
3665 fprintf (file, ";; total time = %d\n;; new basic block head = %d\n;; new basic block end = %d\n\n",
3666 clock, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b]));
3669 /* Yow! We're done! */
3670 free_pending_lists ();
3675 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
3676 REGNO, returning the rtx of the reference found if any. Otherwise,
3680 regno_use_in (regno, x)
3688 if (GET_CODE (x) == REG && REGNO (x) == regno)
3691 fmt = GET_RTX_FORMAT (GET_CODE (x));
3692 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3696 if (tem = regno_use_in (regno, XEXP (x, i)))
3699 else if (fmt[i] == 'E')
3700 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3701 if (tem = regno_use_in (regno , XVECEXP (x, i, j)))
3708 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
3709 needed for the hard register mentioned in the note. This can happen
3710 if the reference to the hard register in the original insn was split into
3711 several smaller hard register references in the split insns. */
3714 split_hard_reg_notes (note, first, last, orig_insn)
3715 rtx note, first, last, orig_insn;
3717 rtx reg, temp, link;
3718 int n_regs, i, new_reg;
3721 /* Assume that this is a REG_DEAD note. */
3722 if (REG_NOTE_KIND (note) != REG_DEAD)
3725 reg = XEXP (note, 0);
3727 n_regs = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
3729 /* ??? Could add check here to see whether, the hard register is referenced
3730 in the same mode as in the original insn. If so, then it has not been
3731 split, and the rest of the code below is unnecessary. */
3733 for (i = 1; i < n_regs; i++)
3735 new_reg = REGNO (reg) + i;
3737 /* Check for references to new_reg in the split insns. */
3738 for (insn = last; ; insn = PREV_INSN (insn))
3740 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
3741 && (temp = regno_use_in (new_reg, PATTERN (insn))))
3743 /* Create a new reg dead note here. */
3744 link = rtx_alloc (EXPR_LIST);
3745 PUT_REG_NOTE_KIND (link, REG_DEAD);
3746 XEXP (link, 0) = temp;
3747 XEXP (link, 1) = REG_NOTES (insn);
3748 REG_NOTES (insn) = link;
3751 /* It isn't mentioned anywhere, so no new reg note is needed for
3759 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
3760 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
3763 new_insn_dead_notes (pat, insn, last, orig_insn)
3764 rtx pat, insn, last, orig_insn;
3768 /* PAT is either a CLOBBER or a SET here. */
3769 dest = XEXP (pat, 0);
3771 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
3772 || GET_CODE (dest) == STRICT_LOW_PART
3773 || GET_CODE (dest) == SIGN_EXTRACT)
3774 dest = XEXP (dest, 0);
3776 if (GET_CODE (dest) == REG)
3778 for (tem = last; tem != insn; tem = PREV_INSN (tem))
3780 if (GET_RTX_CLASS (GET_CODE (tem)) == 'i'
3781 && reg_overlap_mentioned_p (dest, PATTERN (tem))
3782 && (set = single_set (tem)))
3784 rtx tem_dest = SET_DEST (set);
3786 while (GET_CODE (tem_dest) == ZERO_EXTRACT
3787 || GET_CODE (tem_dest) == SUBREG
3788 || GET_CODE (tem_dest) == STRICT_LOW_PART
3789 || GET_CODE (tem_dest) == SIGN_EXTRACT)
3790 tem_dest = XEXP (tem_dest, 0);
3792 if (tem_dest != dest)
3794 /* Use the same scheme as combine.c, don't put both REG_DEAD
3795 and REG_UNUSED notes on the same insn. */
3796 if (! find_regno_note (tem, REG_UNUSED, REGNO (dest))
3797 && ! find_regno_note (tem, REG_DEAD, REGNO (dest)))
3799 rtx note = rtx_alloc (EXPR_LIST);
3800 PUT_REG_NOTE_KIND (note, REG_DEAD);
3801 XEXP (note, 0) = dest;
3802 XEXP (note, 1) = REG_NOTES (tem);
3803 REG_NOTES (tem) = note;
3805 /* The reg only dies in one insn, the last one that uses
3809 else if (reg_overlap_mentioned_p (dest, SET_SRC (set)))
3810 /* We found an instruction that both uses the register,
3811 and sets it, so no new REG_NOTE is needed for this set. */
3815 /* If this is a set, it must die somewhere, unless it is the dest of
3816 the original insn, and hence is live after the original insn. Abort
3817 if it isn't supposed to be live after the original insn.
3819 If this is a clobber, then just add a REG_UNUSED note. */
3822 int live_after_orig_insn = 0;
3823 rtx pattern = PATTERN (orig_insn);
3826 if (GET_CODE (pat) == CLOBBER)
3828 rtx note = rtx_alloc (EXPR_LIST);
3829 PUT_REG_NOTE_KIND (note, REG_UNUSED);
3830 XEXP (note, 0) = dest;
3831 XEXP (note, 1) = REG_NOTES (insn);
3832 REG_NOTES (insn) = note;
3836 /* The original insn could have multiple sets, so search the
3837 insn for all sets. */
3838 if (GET_CODE (pattern) == SET)
3840 if (reg_overlap_mentioned_p (dest, SET_DEST (pattern)))
3841 live_after_orig_insn = 1;
3843 else if (GET_CODE (pattern) == PARALLEL)
3845 for (i = 0; i < XVECLEN (pattern, 0); i++)
3846 if (GET_CODE (XVECEXP (pattern, 0, i)) == SET
3847 && reg_overlap_mentioned_p (dest,
3848 SET_DEST (XVECEXP (pattern,
3850 live_after_orig_insn = 1;
3853 if (! live_after_orig_insn)
3859 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
3860 registers modified by X. INC is -1 if the containing insn is being deleted,
3861 and is 1 if the containing insn is a newly generated insn. */
3864 update_n_sets (x, inc)
3868 rtx dest = SET_DEST (x);
3870 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
3871 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
3872 dest = SUBREG_REG (dest);
3874 if (GET_CODE (dest) == REG)
3876 int regno = REGNO (dest);
3878 if (regno < FIRST_PSEUDO_REGISTER)
3881 int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest));
3883 for (i = regno; i < endregno; i++)
3884 reg_n_sets[i] += inc;
3887 reg_n_sets[regno] += inc;
3891 /* Updates all flow-analysis related quantities (including REG_NOTES) for
3892 the insns from FIRST to LAST inclusive that were created by splitting
3893 ORIG_INSN. NOTES are the original REG_NOTES. */
3896 update_flow_info (notes, first, last, orig_insn)
3903 rtx orig_dest, temp;
3906 /* Get and save the destination set by the original insn. */
3908 orig_dest = single_set (orig_insn);
3910 orig_dest = SET_DEST (orig_dest);
3912 /* Move REG_NOTES from the original insn to where they now belong. */
3914 for (note = notes; note; note = next)
3916 next = XEXP (note, 1);
3917 switch (REG_NOTE_KIND (note))
3921 /* Move these notes from the original insn to the last new insn where
3922 the register is now set. */
3924 for (insn = last; ; insn = PREV_INSN (insn))
3926 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
3927 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
3929 XEXP (note, 1) = REG_NOTES (insn);
3930 REG_NOTES (insn) = note;
3932 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
3934 /* ??? This won't handle multiple word registers correctly,
3935 but should be good enough for now. */
3936 if (REG_NOTE_KIND (note) == REG_UNUSED
3937 && ! dead_or_set_p (insn, XEXP (note, 0)))
3938 PUT_REG_NOTE_KIND (note, REG_DEAD);
3940 /* The reg only dies in one insn, the last one that uses
3944 /* It must die somewhere, fail it we couldn't find where it died.
3946 If this is a REG_UNUSED note, then it must be a temporary
3947 register that was not needed by this instantiation of the
3948 pattern, so we can safely ignore it. */
3951 if (REG_NOTE_KIND (note) != REG_UNUSED)
3958 /* If this note refers to a multiple word hard register, it may
3959 have been split into several smaller hard register references.
3960 Check to see if there are any new register references that
3961 need REG_NOTES added for them. */
3962 temp = XEXP (note, 0);
3963 if (REG_NOTE_KIND (note) == REG_DEAD
3964 && GET_CODE (temp) == REG
3965 && REGNO (temp) < FIRST_PSEUDO_REGISTER
3966 && HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)))
3967 split_hard_reg_notes (note, first, last, orig_insn);
3971 /* This note applies to the dest of the original insn. Find the
3972 first new insn that now has the same dest, and move the note
3978 for (insn = first; ; insn = NEXT_INSN (insn))
3980 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
3981 && (temp = single_set (insn))
3982 && rtx_equal_p (SET_DEST (temp), orig_dest))
3984 XEXP (note, 1) = REG_NOTES (insn);
3985 REG_NOTES (insn) = note;
3986 /* The reg is only zero before one insn, the first that
3990 /* It must be set somewhere, fail if we couldn't find where it
3999 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
4000 set is meaningless. Just drop the note. */
4004 case REG_NO_CONFLICT:
4005 /* These notes apply to the dest of the original insn. Find the last
4006 new insn that now has the same dest, and move the note there. */
4011 for (insn = last; ; insn = PREV_INSN (insn))
4013 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4014 && (temp = single_set (insn))
4015 && rtx_equal_p (SET_DEST (temp), orig_dest))
4017 XEXP (note, 1) = REG_NOTES (insn);
4018 REG_NOTES (insn) = note;
4019 /* Only put this note on one of the new insns. */
4023 /* The original dest must still be set someplace. Abort if we
4024 couldn't find it. */
4031 /* Move a REG_LIBCALL note to the first insn created, and update
4032 the corresponding REG_RETVAL note. */
4033 XEXP (note, 1) = REG_NOTES (first);
4034 REG_NOTES (first) = note;
4036 insn = XEXP (note, 0);
4037 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
4039 XEXP (note, 0) = first;
4043 /* Move a REG_RETVAL note to the last insn created, and update
4044 the corresponding REG_LIBCALL note. */
4045 XEXP (note, 1) = REG_NOTES (last);
4046 REG_NOTES (last) = note;
4048 insn = XEXP (note, 0);
4049 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
4051 XEXP (note, 0) = last;
4055 /* This should be moved to whichever instruction is a JUMP_INSN. */
4057 for (insn = last; ; insn = PREV_INSN (insn))
4059 if (GET_CODE (insn) == JUMP_INSN)
4061 XEXP (note, 1) = REG_NOTES (insn);
4062 REG_NOTES (insn) = note;
4063 /* Only put this note on one of the new insns. */
4066 /* Fail if we couldn't find a JUMP_INSN. */
4073 /* This should be moved to whichever instruction now has the
4074 increment operation. */
4078 /* Should be moved to the new insn(s) which use the label. */
4079 for (insn = first; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
4080 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4081 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
4082 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL,
4083 XEXP (note, 0), REG_NOTES (insn));
4088 /* These two notes will never appear until after reorg, so we don't
4089 have to handle them here. */
4095 /* Each new insn created, except the last, has a new set. If the destination
4096 is a register, then this reg is now live across several insns, whereas
4097 previously the dest reg was born and died within the same insn. To
4098 reflect this, we now need a REG_DEAD note on the insn where this
4101 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
4103 for (insn = first; insn != last; insn = NEXT_INSN (insn))
4108 pat = PATTERN (insn);
4109 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
4110 new_insn_dead_notes (pat, insn, last, orig_insn);
4111 else if (GET_CODE (pat) == PARALLEL)
4113 for (i = 0; i < XVECLEN (pat, 0); i++)
4114 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
4115 || GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER)
4116 new_insn_dead_notes (XVECEXP (pat, 0, i), insn, last, orig_insn);
4120 /* If any insn, except the last, uses the register set by the last insn,
4121 then we need a new REG_DEAD note on that insn. In this case, there
4122 would not have been a REG_DEAD note for this register in the original
4123 insn because it was used and set within one insn.
4125 There is no new REG_DEAD note needed if the last insn uses the register
4126 that it is setting. */
4128 set = single_set (last);
4131 rtx dest = SET_DEST (set);
4133 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
4134 || GET_CODE (dest) == STRICT_LOW_PART
4135 || GET_CODE (dest) == SIGN_EXTRACT)
4136 dest = XEXP (dest, 0);
4138 if (GET_CODE (dest) == REG
4139 && ! reg_overlap_mentioned_p (dest, SET_SRC (set)))
4141 for (insn = PREV_INSN (last); ; insn = PREV_INSN (insn))
4143 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4144 && reg_mentioned_p (dest, PATTERN (insn))
4145 && (set = single_set (insn)))
4147 rtx insn_dest = SET_DEST (set);
4149 while (GET_CODE (insn_dest) == ZERO_EXTRACT
4150 || GET_CODE (insn_dest) == SUBREG
4151 || GET_CODE (insn_dest) == STRICT_LOW_PART
4152 || GET_CODE (insn_dest) == SIGN_EXTRACT)
4153 insn_dest = XEXP (insn_dest, 0);
4155 if (insn_dest != dest)
4157 note = rtx_alloc (EXPR_LIST);
4158 PUT_REG_NOTE_KIND (note, REG_DEAD);
4159 XEXP (note, 0) = dest;
4160 XEXP (note, 1) = REG_NOTES (insn);
4161 REG_NOTES (insn) = note;
4162 /* The reg only dies in one insn, the last one
4173 /* If the original dest is modifying a multiple register target, and the
4174 original instruction was split such that the original dest is now set
4175 by two or more SUBREG sets, then the split insns no longer kill the
4176 destination of the original insn.
4178 In this case, if there exists an instruction in the same basic block,
4179 before the split insn, which uses the original dest, and this use is
4180 killed by the original insn, then we must remove the REG_DEAD note on
4181 this insn, because it is now superfluous.
4183 This does not apply when a hard register gets split, because the code
4184 knows how to handle overlapping hard registers properly. */
4185 if (orig_dest && GET_CODE (orig_dest) == REG)
4187 int found_orig_dest = 0;
4188 int found_split_dest = 0;
4190 for (insn = first; ; insn = NEXT_INSN (insn))
4192 set = single_set (insn);
4195 if (GET_CODE (SET_DEST (set)) == REG
4196 && REGNO (SET_DEST (set)) == REGNO (orig_dest))
4198 found_orig_dest = 1;
4201 else if (GET_CODE (SET_DEST (set)) == SUBREG
4202 && SUBREG_REG (SET_DEST (set)) == orig_dest)
4204 found_split_dest = 1;
4213 if (found_split_dest)
4215 /* Search backwards from FIRST, looking for the first insn that uses
4216 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
4217 If we find an insn, and it has a REG_DEAD note, then delete the
4220 for (insn = first; insn; insn = PREV_INSN (insn))
4222 if (GET_CODE (insn) == CODE_LABEL
4223 || GET_CODE (insn) == JUMP_INSN)
4225 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4226 && reg_mentioned_p (orig_dest, insn))
4228 note = find_regno_note (insn, REG_DEAD, REGNO (orig_dest));
4230 remove_note (insn, note);
4234 else if (! found_orig_dest)
4236 /* This should never happen. */
4241 /* Update reg_n_sets. This is necessary to prevent local alloc from
4242 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
4243 a reg from set once to set multiple times. */
4246 rtx x = PATTERN (orig_insn);
4247 RTX_CODE code = GET_CODE (x);
4249 if (code == SET || code == CLOBBER)
4250 update_n_sets (x, -1);
4251 else if (code == PARALLEL)
4254 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4256 code = GET_CODE (XVECEXP (x, 0, i));
4257 if (code == SET || code == CLOBBER)
4258 update_n_sets (XVECEXP (x, 0, i), -1);
4262 for (insn = first; ; insn = NEXT_INSN (insn))
4265 code = GET_CODE (x);
4267 if (code == SET || code == CLOBBER)
4268 update_n_sets (x, 1);
4269 else if (code == PARALLEL)
4272 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4274 code = GET_CODE (XVECEXP (x, 0, i));
4275 if (code == SET || code == CLOBBER)
4276 update_n_sets (XVECEXP (x, 0, i), 1);
4286 /* The one entry point in this file. DUMP_FILE is the dump file for
4290 schedule_insns (dump_file)
4293 int max_uid = MAX_INSNS_PER_SPLIT * (get_max_uid () + 1);
4297 /* Taking care of this degenerate case makes the rest of
4298 this code simpler. */
4299 if (n_basic_blocks == 0)
4302 /* Create an insn here so that we can hang dependencies off of it later. */
4303 sched_before_next_call
4304 = gen_rtx (INSN, VOIDmode, 0, NULL_RTX, NULL_RTX,
4305 NULL_RTX, 0, NULL_RTX, 0);
4307 /* Initialize the unused_*_lists. We can't use the ones left over from
4308 the previous function, because gcc has freed that memory. We can use
4309 the ones left over from the first sched pass in the second pass however,
4310 so only clear them on the first sched pass. The first pass is before
4311 reload if flag_schedule_insns is set, otherwise it is afterwards. */
4313 if (reload_completed == 0 || ! flag_schedule_insns)
4315 unused_insn_list = 0;
4316 unused_expr_list = 0;
4319 /* We create no insns here, only reorder them, so we
4320 remember how far we can cut back the stack on exit. */
4322 /* Allocate data for this pass. See comments, above,
4323 for what these vectors do. */
4324 insn_luid = (int *) alloca (max_uid * sizeof (int));
4325 insn_priority = (int *) alloca (max_uid * sizeof (int));
4326 insn_tick = (int *) alloca (max_uid * sizeof (int));
4327 insn_costs = (short *) alloca (max_uid * sizeof (short));
4328 insn_units = (short *) alloca (max_uid * sizeof (short));
4329 insn_blockage = (unsigned int *) alloca (max_uid * sizeof (unsigned int));
4330 insn_ref_count = (int *) alloca (max_uid * sizeof (int));
4332 if (reload_completed == 0)
4334 sched_reg_n_deaths = (short *) alloca (max_regno * sizeof (short));
4335 sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int));
4336 sched_reg_live_length = (int *) alloca (max_regno * sizeof (int));
4337 bb_dead_regs = (regset) alloca (regset_bytes);
4338 bb_live_regs = (regset) alloca (regset_bytes);
4339 bzero (sched_reg_n_calls_crossed, max_regno * sizeof (int));
4340 bzero (sched_reg_live_length, max_regno * sizeof (int));
4341 bcopy (reg_n_deaths, sched_reg_n_deaths, max_regno * sizeof (short));
4342 init_alias_analysis ();
4346 sched_reg_n_deaths = 0;
4347 sched_reg_n_calls_crossed = 0;
4348 sched_reg_live_length = 0;
4351 if (! flag_schedule_insns)
4352 init_alias_analysis ();
4355 if (write_symbols != NO_DEBUG)
4359 line_note = (rtx *) alloca (max_uid * sizeof (rtx));
4360 bzero (line_note, max_uid * sizeof (rtx));
4361 line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx));
4362 bzero (line_note_head, n_basic_blocks * sizeof (rtx));
4364 /* Determine the line-number at the start of each basic block.
4365 This must be computed and saved now, because after a basic block's
4366 predecessor has been scheduled, it is impossible to accurately
4367 determine the correct line number for the first insn of the block. */
4369 for (b = 0; b < n_basic_blocks; b++)
4370 for (line = basic_block_head[b]; line; line = PREV_INSN (line))
4371 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4373 line_note_head[b] = line;
4378 bzero (insn_luid, max_uid * sizeof (int));
4379 bzero (insn_priority, max_uid * sizeof (int));
4380 bzero (insn_tick, max_uid * sizeof (int));
4381 bzero (insn_costs, max_uid * sizeof (short));
4382 bzero (insn_units, max_uid * sizeof (short));
4383 bzero (insn_blockage, max_uid * sizeof (unsigned int));
4384 bzero (insn_ref_count, max_uid * sizeof (int));
4386 /* Schedule each basic block, block by block. */
4388 if (NEXT_INSN (basic_block_end[n_basic_blocks-1]) == 0
4389 || (GET_CODE (basic_block_end[n_basic_blocks-1]) != NOTE
4390 && GET_CODE (basic_block_end[n_basic_blocks-1]) != CODE_LABEL))
4391 emit_note_after (NOTE_INSN_DELETED, basic_block_end[n_basic_blocks-1]);
4393 for (b = 0; b < n_basic_blocks; b++)
4400 for (insn = basic_block_head[b]; ; insn = next)
4405 /* Can't use `next_real_insn' because that
4406 might go across CODE_LABELS and short-out basic blocks. */
4407 next = NEXT_INSN (insn);
4408 if (GET_CODE (insn) != INSN)
4410 if (insn == basic_block_end[b])
4416 /* Don't split no-op move insns. These should silently disappear
4417 later in final. Splitting such insns would break the code
4418 that handles REG_NO_CONFLICT blocks. */
4419 set = single_set (insn);
4420 if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
4422 if (insn == basic_block_end[b])
4425 /* Nops get in the way while scheduling, so delete them now if
4426 register allocation has already been done. It is too risky
4427 to try to do this before register allocation, and there are
4428 unlikely to be very many nops then anyways. */
4429 if (reload_completed)
4431 PUT_CODE (insn, NOTE);
4432 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4433 NOTE_SOURCE_FILE (insn) = 0;
4439 /* Split insns here to get max fine-grain parallelism. */
4440 prev = PREV_INSN (insn);
4441 if (reload_completed == 0)
4443 rtx last, first = PREV_INSN (insn);
4444 rtx notes = REG_NOTES (insn);
4446 last = try_split (PATTERN (insn), insn, 1);
4449 /* try_split returns the NOTE that INSN became. */
4450 first = NEXT_INSN (first);
4451 update_flow_info (notes, first, last, insn);
4453 PUT_CODE (insn, NOTE);
4454 NOTE_SOURCE_FILE (insn) = 0;
4455 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4456 if (insn == basic_block_head[b])
4457 basic_block_head[b] = first;
4458 if (insn == basic_block_end[b])
4460 basic_block_end[b] = last;
4466 if (insn == basic_block_end[b])
4470 schedule_block (b, dump_file);
4477 /* Reposition the prologue and epilogue notes in case we moved the
4478 prologue/epilogue insns. */
4479 if (reload_completed)
4480 reposition_prologue_and_epilogue_notes (get_insns ());
4482 if (write_symbols != NO_DEBUG)
4485 rtx insn = get_insns ();
4486 int active_insn = 0;
4489 /* Walk the insns deleting redundant line-number notes. Many of these
4490 are already present. The remainder tend to occur at basic
4491 block boundaries. */
4492 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
4493 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4495 /* If there are no active insns following, INSN is redundant. */
4496 if (active_insn == 0)
4499 NOTE_SOURCE_FILE (insn) = 0;
4500 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4502 /* If the line number is unchanged, LINE is redundant. */
4504 && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
4505 && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
4508 NOTE_SOURCE_FILE (line) = 0;
4509 NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
4516 else if (! ((GET_CODE (insn) == NOTE
4517 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
4518 || (GET_CODE (insn) == INSN
4519 && (GET_CODE (PATTERN (insn)) == USE
4520 || GET_CODE (PATTERN (insn)) == CLOBBER))))
4523 if (dump_file && notes)
4524 fprintf (dump_file, ";; deleted %d line-number notes\n", notes);
4527 if (reload_completed == 0)
4530 for (regno = 0; regno < max_regno; regno++)
4531 if (sched_reg_live_length[regno])
4535 if (reg_live_length[regno] > sched_reg_live_length[regno])
4537 ";; register %d life shortened from %d to %d\n",
4538 regno, reg_live_length[regno],
4539 sched_reg_live_length[regno]);
4540 /* Negative values are special; don't overwrite the current
4541 reg_live_length value if it is negative. */
4542 else if (reg_live_length[regno] < sched_reg_live_length[regno]
4543 && reg_live_length[regno] >= 0)
4545 ";; register %d life extended from %d to %d\n",
4546 regno, reg_live_length[regno],
4547 sched_reg_live_length[regno]);
4549 if (reg_n_calls_crossed[regno]
4550 && ! sched_reg_n_calls_crossed[regno])
4552 ";; register %d no longer crosses calls\n", regno);
4553 else if (! reg_n_calls_crossed[regno]
4554 && sched_reg_n_calls_crossed[regno])
4556 ";; register %d now crosses calls\n", regno);
4558 /* Negative values are special; don't overwrite the current
4559 reg_live_length value if it is negative. */
4560 if (reg_live_length[regno] >= 0)
4561 reg_live_length[regno] = sched_reg_live_length[regno];
4562 reg_n_calls_crossed[regno] = sched_reg_n_calls_crossed[regno];
4566 #endif /* INSN_SCHEDULING */