1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 93-96, 1997 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 Enhanced by, and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Instruction scheduling pass.
25 This pass implements list scheduling within basic blocks. It is
26 run after flow analysis, but before register allocation. The
27 scheduler works as follows:
29 We compute insn priorities based on data dependencies. Flow
30 analysis only creates a fraction of the data-dependencies we must
31 observe: namely, only those dependencies which the combiner can be
32 expected to use. For this pass, we must therefore create the
33 remaining dependencies we need to observe: register dependencies,
34 memory dependencies, dependencies to keep function calls in order,
35 and the dependence between a conditional branch and the setting of
36 condition codes are all dealt with here.
38 The scheduler first traverses the data flow graph, starting with
39 the last instruction, and proceeding to the first, assigning
40 values to insn_priority as it goes. This sorts the instructions
41 topologically by data dependence.
43 Once priorities have been established, we order the insns using
44 list scheduling. This works as follows: starting with a list of
45 all the ready insns, and sorted according to priority number, we
46 schedule the insn from the end of the list by placing its
47 predecessors in the list according to their priority order. We
48 consider this insn scheduled by setting the pointer to the "end" of
49 the list to point to the previous insn. When an insn has no
50 predecessors, we either queue it until sufficient time has elapsed
51 or add it to the ready list. As the instructions are scheduled or
52 when stalls are introduced, the queue advances and dumps insns into
53 the ready list. When all insns down to the lowest priority have
54 been scheduled, the critical path of the basic block has been made
55 as short as possible. The remaining insns are then scheduled in
58 Function unit conflicts are resolved during reverse list scheduling
59 by tracking the time when each insn is committed to the schedule
60 and from that, the time the function units it uses must be free.
61 As insns on the ready list are considered for scheduling, those
62 that would result in a blockage of the already committed insns are
63 queued until no blockage will result. Among the remaining insns on
64 the ready list to be considered, the first one with the largest
65 potential for causing a subsequent blockage is chosen.
67 The following list shows the order in which we want to break ties
68 among insns in the ready list:
70 1. choose insn with lowest conflict cost, ties broken by
71 2. choose insn with the longest path to end of bb, ties broken by
72 3. choose insn that kills the most registers, ties broken by
73 4. choose insn that conflicts with the most ready insns, or finally
74 5. choose insn with lowest UID.
76 Memory references complicate matters. Only if we can be certain
77 that memory references are not part of the data dependency graph
78 (via true, anti, or output dependence), can we move operations past
79 memory references. To first approximation, reads can be done
80 independently, while writes introduce dependencies. Better
81 approximations will yield fewer dependencies.
83 Dependencies set up by memory references are treated in exactly the
84 same way as other dependencies, by using LOG_LINKS.
86 Having optimized the critical path, we may have also unduly
87 extended the lifetimes of some registers. If an operation requires
88 that constants be loaded into registers, it is certainly desirable
89 to load those constants as early as necessary, but no earlier.
90 I.e., it will not do to load up a bunch of registers at the
91 beginning of a basic block only to use them at the end, if they
92 could be loaded later, since this may result in excessive register
95 Note that since branches are never in basic blocks, but only end
96 basic blocks, this pass will not do any branch scheduling. But
97 that is ok, since we can use GNU's delayed branch scheduling
98 pass to take care of this case.
100 Also note that no further optimizations based on algebraic identities
101 are performed, so this pass would be a good one to perform instruction
102 splitting, such as breaking up a multiply instruction into shifts
103 and adds where that is profitable.
105 Given the memory aliasing analysis that this pass should perform,
106 it should be possible to remove redundant stores to memory, and to
107 load values from registers instead of hitting memory.
109 This pass must update information that subsequent passes expect to be
110 correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
111 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
114 The information in the line number notes is carefully retained by
115 this pass. Notes that refer to the starting and ending of
116 exception regions are also carefully retained by this pass. All
117 other NOTE insns are grouped in their same relative order at the
118 beginning of basic blocks that have been scheduled. */
123 #include "basic-block.h"
125 #include "hard-reg-set.h"
127 #include "insn-config.h"
128 #include "insn-attr.h"
130 #ifdef INSN_SCHEDULING
131 /* Arrays set up by scheduling for the same respective purposes as
132 similar-named arrays set up by flow analysis. We work with these
133 arrays during the scheduling pass so we can compare values against
136 Values of these arrays are copied at the end of this pass into the
137 arrays set up by flow analysis. */
138 static int *sched_reg_n_calls_crossed;
139 static int *sched_reg_live_length;
141 /* Element N is the next insn that sets (hard or pseudo) register
142 N within the current basic block; or zero, if there is no
143 such insn. Needed for new registers which may be introduced
144 by splitting insns. */
145 static rtx *reg_last_uses;
146 static rtx *reg_last_sets;
147 static regset reg_pending_sets;
148 static int reg_pending_sets_all;
150 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
151 static int *insn_luid;
152 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
154 /* Vector indexed by INSN_UID giving each instruction a priority. */
155 static int *insn_priority;
156 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
158 static short *insn_costs;
159 #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
161 /* Vector indexed by INSN_UID giving an encoding of the function units
163 static short *insn_units;
164 #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)]
166 /* Vector indexed by INSN_UID giving an encoding of the blockage range
167 function. The unit and the range are encoded. */
168 static unsigned int *insn_blockage;
169 #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)]
171 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
172 #define ENCODE_BLOCKAGE(U,R) \
173 ((((U) << UNIT_BITS) << BLOCKAGE_BITS \
174 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
175 | MAX_BLOCKAGE_COST (R))
176 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
177 #define BLOCKAGE_RANGE(B) \
178 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
179 | (B) & BLOCKAGE_MASK)
181 /* Encodings of the `<name>_unit_blockage_range' function. */
182 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
183 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
185 #define DONE_PRIORITY -1
186 #define MAX_PRIORITY 0x7fffffff
187 #define TAIL_PRIORITY 0x7ffffffe
188 #define LAUNCH_PRIORITY 0x7f000001
189 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
190 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
192 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
193 static int *insn_ref_count;
194 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
196 /* Vector indexed by INSN_UID giving line-number note in effect for each
197 insn. For line-number notes, this indicates whether the note may be
199 static rtx *line_note;
200 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
202 /* Vector indexed by basic block number giving the starting line-number
203 for each basic block. */
204 static rtx *line_note_head;
206 /* List of important notes we must keep around. This is a pointer to the
207 last element in the list. */
208 static rtx note_list;
210 /* Regsets telling whether a given register is live or dead before the last
211 scheduled insn. Must scan the instructions once before scheduling to
212 determine what registers are live or dead at the end of the block. */
213 static regset bb_dead_regs;
214 static regset bb_live_regs;
216 /* Regset telling whether a given register is live after the insn currently
217 being scheduled. Before processing an insn, this is equal to bb_live_regs
218 above. This is used so that we can find registers that are newly born/dead
219 after processing an insn. */
220 static regset old_live_regs;
222 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
223 during the initial scan and reused later. If there are not exactly as
224 many REG_DEAD notes in the post scheduled code as there were in the
225 prescheduled code then we trigger an abort because this indicates a bug. */
226 static rtx dead_notes;
230 /* An instruction is ready to be scheduled when all insns following it
231 have already been scheduled. It is important to ensure that all
232 insns which use its result will not be executed until its result
233 has been computed. An insn is maintained in one of four structures:
235 (P) the "Pending" set of insns which cannot be scheduled until
236 their dependencies have been satisfied.
237 (Q) the "Queued" set of insns that can be scheduled when sufficient
239 (R) the "Ready" list of unscheduled, uncommitted insns.
240 (S) the "Scheduled" list of insns.
242 Initially, all insns are either "Pending" or "Ready" depending on
243 whether their dependencies are satisfied.
245 Insns move from the "Ready" list to the "Scheduled" list as they
246 are committed to the schedule. As this occurs, the insns in the
247 "Pending" list have their dependencies satisfied and move to either
248 the "Ready" list or the "Queued" set depending on whether
249 sufficient time has passed to make them ready. As time passes,
250 insns move from the "Queued" set to the "Ready" list. Insns may
251 move from the "Ready" list to the "Queued" set if they are blocked
252 due to a function unit conflict.
254 The "Pending" list (P) are the insns in the LOG_LINKS of the unscheduled
255 insns, i.e., those that are ready, queued, and pending.
256 The "Queued" set (Q) is implemented by the variable `insn_queue'.
257 The "Ready" list (R) is implemented by the variables `ready' and
259 The "Scheduled" list (S) is the new insn chain built by this pass.
261 The transition (R->S) is implemented in the scheduling loop in
262 `schedule_block' when the best insn to schedule is chosen.
263 The transition (R->Q) is implemented in `schedule_select' when an
264 insn is found to to have a function unit conflict with the already
266 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
267 insns move from the ready list to the scheduled list.
268 The transition (Q->R) is implemented at the top of the scheduling
269 loop in `schedule_block' as time passes or stalls are introduced. */
271 /* Implement a circular buffer to delay instructions until sufficient
272 time has passed. INSN_QUEUE_SIZE is a power of two larger than
273 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
274 longest time an isnsn may be queued. */
275 static rtx insn_queue[INSN_QUEUE_SIZE];
276 static int q_ptr = 0;
277 static int q_size = 0;
278 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
279 #define NEXT_Q_AFTER(X,C) (((X)+C) & (INSN_QUEUE_SIZE-1))
281 /* Vector indexed by INSN_UID giving the minimum clock tick at which
282 the insn becomes ready. This is used to note timing constraints for
283 insns in the pending list. */
284 static int *insn_tick;
285 #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)])
287 /* Data structure for keeping track of register information
288 during that register's life. */
297 /* Forward declarations. */
298 static rtx canon_rtx PROTO((rtx));
299 static int rtx_equal_for_memref_p PROTO((rtx, rtx));
300 static rtx find_symbolic_term PROTO((rtx));
301 static int memrefs_conflict_p PROTO((int, rtx, int, rtx,
303 static void add_dependence PROTO((rtx, rtx, enum reg_note));
304 static void remove_dependence PROTO((rtx, rtx));
305 static rtx find_insn_list PROTO((rtx, rtx));
306 static int insn_unit PROTO((rtx));
307 static unsigned int blockage_range PROTO((int, rtx));
308 static void clear_units PROTO((void));
309 static void prepare_unit PROTO((int));
310 static int actual_hazard_this_instance PROTO((int, int, rtx, int, int));
311 static void schedule_unit PROTO((int, rtx, int));
312 static int actual_hazard PROTO((int, rtx, int, int));
313 static int potential_hazard PROTO((int, rtx, int));
314 static int insn_cost PROTO((rtx, rtx, rtx));
315 static int priority PROTO((rtx));
316 static void free_pending_lists PROTO((void));
317 static void add_insn_mem_dependence PROTO((rtx *, rtx *, rtx, rtx));
318 static void flush_pending_lists PROTO((rtx, int));
319 static void sched_analyze_1 PROTO((rtx, rtx));
320 static void sched_analyze_2 PROTO((rtx, rtx));
321 static void sched_analyze_insn PROTO((rtx, rtx, rtx));
322 static int sched_analyze PROTO((rtx, rtx));
323 static void sched_note_set PROTO((int, rtx, int));
324 static int rank_for_schedule PROTO((rtx *, rtx *));
325 static void swap_sort PROTO((rtx *, int));
326 static void queue_insn PROTO((rtx, int));
327 static int birthing_insn PROTO((rtx));
328 static void adjust_priority PROTO((rtx));
329 static int schedule_insn PROTO((rtx, rtx *, int, int));
330 static int schedule_select PROTO((rtx *, int, int, FILE *));
331 static void create_reg_dead_note PROTO((rtx, rtx));
332 static void attach_deaths PROTO((rtx, rtx, int));
333 static void attach_deaths_insn PROTO((rtx));
334 static rtx unlink_notes PROTO((rtx, rtx));
335 static int new_sometimes_live PROTO((struct sometimes *, int, int));
336 static void finish_sometimes_live PROTO((struct sometimes *, int));
337 static rtx reemit_notes PROTO((rtx, rtx));
338 static void schedule_block PROTO((int, FILE *));
339 static rtx regno_use_in PROTO((int, rtx));
340 static void split_hard_reg_notes PROTO((rtx, rtx, rtx, rtx));
341 static void new_insn_dead_notes PROTO((rtx, rtx, rtx, rtx));
342 static void update_n_sets PROTO((rtx, int));
343 static void update_flow_info PROTO((rtx, rtx, rtx, rtx));
345 /* Main entry point of this file. */
346 void schedule_insns PROTO((FILE *));
348 #endif /* INSN_SCHEDULING */
350 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
352 /* Vector indexed by N giving the initial (unchanging) value known
353 for pseudo-register N. */
354 static rtx *reg_known_value;
356 /* Vector recording for each reg_known_value whether it is due to a
357 REG_EQUIV note. Future passes (viz., reload) may replace the
358 pseudo with the equivalent expression and so we account for the
359 dependences that would be introduced if that happens. */
360 /* ??? This is a problem only on the Convex. The REG_EQUIV notes created in
361 assign_parms mention the arg pointer, and there are explicit insns in the
362 RTL that modify the arg pointer. Thus we must ensure that such insns don't
363 get scheduled across each other because that would invalidate the REG_EQUIV
364 notes. One could argue that the REG_EQUIV notes are wrong, but solving
365 the problem in the scheduler will likely give better code, so we do it
367 static char *reg_known_equiv_p;
369 /* Indicates number of valid entries in reg_known_value. */
370 static int reg_known_value_size;
376 /* Recursively look for equivalences. */
377 if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
378 && REGNO (x) <= reg_known_value_size)
379 return reg_known_value[REGNO (x)] == x
380 ? x : canon_rtx (reg_known_value[REGNO (x)]);
381 else if (GET_CODE (x) == PLUS)
383 rtx x0 = canon_rtx (XEXP (x, 0));
384 rtx x1 = canon_rtx (XEXP (x, 1));
386 if (x0 != XEXP (x, 0) || x1 != XEXP (x, 1))
388 /* We can tolerate LO_SUMs being offset here; these
389 rtl are used for nothing other than comparisons. */
390 if (GET_CODE (x0) == CONST_INT)
391 return plus_constant_for_output (x1, INTVAL (x0));
392 else if (GET_CODE (x1) == CONST_INT)
393 return plus_constant_for_output (x0, INTVAL (x1));
394 return gen_rtx (PLUS, GET_MODE (x), x0, x1);
397 /* This gives us much better alias analysis when called from
398 the loop optimizer. Note we want to leave the original
399 MEM alone, but need to return the canonicalized MEM with
400 all the flags with their original values. */
401 else if (GET_CODE (x) == MEM)
403 rtx copy = copy_rtx (x);
404 XEXP (copy, 0) = canon_rtx (XEXP (copy, 0));
410 /* Set up all info needed to perform alias analysis on memory references. */
413 init_alias_analysis ()
415 int maxreg = max_reg_num ();
420 reg_known_value_size = maxreg;
423 = (rtx *) oballoc ((maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx))
424 - FIRST_PSEUDO_REGISTER;
425 bzero ((char *) (reg_known_value + FIRST_PSEUDO_REGISTER),
426 (maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx));
429 = (char *) oballoc ((maxreg -FIRST_PSEUDO_REGISTER) * sizeof (char))
430 - FIRST_PSEUDO_REGISTER;
431 bzero (reg_known_equiv_p + FIRST_PSEUDO_REGISTER,
432 (maxreg - FIRST_PSEUDO_REGISTER) * sizeof (char));
434 /* Fill in the entries with known constant values. */
435 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
436 if ((set = single_set (insn)) != 0
437 && GET_CODE (SET_DEST (set)) == REG
438 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER
439 && (((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
440 && REG_N_SETS (REGNO (SET_DEST (set))) == 1)
441 || (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != 0)
442 && GET_CODE (XEXP (note, 0)) != EXPR_LIST)
444 int regno = REGNO (SET_DEST (set));
445 reg_known_value[regno] = XEXP (note, 0);
446 reg_known_equiv_p[regno] = REG_NOTE_KIND (note) == REG_EQUIV;
449 /* Fill in the remaining entries. */
450 while (--maxreg >= FIRST_PSEUDO_REGISTER)
451 if (reg_known_value[maxreg] == 0)
452 reg_known_value[maxreg] = regno_reg_rtx[maxreg];
455 /* Return 1 if X and Y are identical-looking rtx's.
457 We use the data in reg_known_value above to see if two registers with
458 different numbers are, in fact, equivalent. */
461 rtx_equal_for_memref_p (x, y)
466 register enum rtx_code code;
469 if (x == 0 && y == 0)
471 if (x == 0 || y == 0)
480 /* Rtx's of different codes cannot be equal. */
481 if (code != GET_CODE (y))
484 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
485 (REG:SI x) and (REG:HI x) are NOT equivalent. */
487 if (GET_MODE (x) != GET_MODE (y))
490 /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */
493 return REGNO (x) == REGNO (y);
494 if (code == LABEL_REF)
495 return XEXP (x, 0) == XEXP (y, 0);
496 if (code == SYMBOL_REF)
497 return XSTR (x, 0) == XSTR (y, 0);
499 /* For commutative operations, the RTX match if the operand match in any
500 order. Also handle the simple binary and unary cases without a loop. */
501 if (code == EQ || code == NE || GET_RTX_CLASS (code) == 'c')
502 return ((rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 0))
503 && rtx_equal_for_memref_p (XEXP (x, 1), XEXP (y, 1)))
504 || (rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 1))
505 && rtx_equal_for_memref_p (XEXP (x, 1), XEXP (y, 0))));
506 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == '2')
507 return (rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 0))
508 && rtx_equal_for_memref_p (XEXP (x, 1), XEXP (y, 1)));
509 else if (GET_RTX_CLASS (code) == '1')
510 return rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 0));
512 /* Compare the elements. If any pair of corresponding elements
513 fail to match, return 0 for the whole things. */
515 fmt = GET_RTX_FORMAT (code);
516 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
521 if (XWINT (x, i) != XWINT (y, i))
527 if (XINT (x, i) != XINT (y, i))
533 /* Two vectors must have the same length. */
534 if (XVECLEN (x, i) != XVECLEN (y, i))
537 /* And the corresponding elements must match. */
538 for (j = 0; j < XVECLEN (x, i); j++)
539 if (rtx_equal_for_memref_p (XVECEXP (x, i, j), XVECEXP (y, i, j)) == 0)
544 if (rtx_equal_for_memref_p (XEXP (x, i), XEXP (y, i)) == 0)
550 if (strcmp (XSTR (x, i), XSTR (y, i)))
555 /* These are just backpointers, so they don't matter. */
561 /* It is believed that rtx's at this level will never
562 contain anything but integers and other rtx's,
563 except for within LABEL_REFs and SYMBOL_REFs. */
571 /* Given an rtx X, find a SYMBOL_REF or LABEL_REF within
572 X and return it, or return 0 if none found. */
575 find_symbolic_term (x)
579 register enum rtx_code code;
583 if (code == SYMBOL_REF || code == LABEL_REF)
585 if (GET_RTX_CLASS (code) == 'o')
588 fmt = GET_RTX_FORMAT (code);
589 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
595 t = find_symbolic_term (XEXP (x, i));
599 else if (fmt[i] == 'E')
605 /* Return nonzero if X and Y (memory addresses) could reference the
606 same location in memory. C is an offset accumulator. When
607 C is nonzero, we are testing aliases between X and Y + C.
608 XSIZE is the size in bytes of the X reference,
609 similarly YSIZE is the size in bytes for Y.
611 If XSIZE or YSIZE is zero, we do not know the amount of memory being
612 referenced (the reference was BLKmode), so make the most pessimistic
615 We recognize the following cases of non-conflicting memory:
617 (1) addresses involving the frame pointer cannot conflict
618 with addresses involving static variables.
619 (2) static variables with different addresses cannot conflict.
621 Nice to notice that varying addresses cannot conflict with fp if no
622 local variables had their addresses taken, but that's too hard now. */
624 /* ??? In Fortran, references to a array parameter can never conflict with
625 another array parameter. */
628 memrefs_conflict_p (xsize, x, ysize, y, c)
633 if (GET_CODE (x) == HIGH)
635 else if (GET_CODE (x) == LO_SUM)
639 if (GET_CODE (y) == HIGH)
641 else if (GET_CODE (y) == LO_SUM)
646 if (rtx_equal_for_memref_p (x, y))
647 return (xsize == 0 || ysize == 0
648 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
650 if (y == frame_pointer_rtx || y == hard_frame_pointer_rtx
651 || y == stack_pointer_rtx)
655 y = x; ysize = xsize;
656 x = t; xsize = tsize;
659 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
660 || x == stack_pointer_rtx)
667 if (GET_CODE (y) == PLUS
668 && canon_rtx (XEXP (y, 0)) == x
669 && (y1 = canon_rtx (XEXP (y, 1)))
670 && GET_CODE (y1) == CONST_INT)
673 return (xsize == 0 || ysize == 0
674 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
677 if (GET_CODE (y) == PLUS
678 && (y1 = canon_rtx (XEXP (y, 0)))
685 if (GET_CODE (x) == PLUS)
687 /* The fact that X is canonicalized means that this
688 PLUS rtx is canonicalized. */
689 rtx x0 = XEXP (x, 0);
690 rtx x1 = XEXP (x, 1);
692 if (GET_CODE (y) == PLUS)
694 /* The fact that Y is canonicalized means that this
695 PLUS rtx is canonicalized. */
696 rtx y0 = XEXP (y, 0);
697 rtx y1 = XEXP (y, 1);
699 if (rtx_equal_for_memref_p (x1, y1))
700 return memrefs_conflict_p (xsize, x0, ysize, y0, c);
701 if (rtx_equal_for_memref_p (x0, y0))
702 return memrefs_conflict_p (xsize, x1, ysize, y1, c);
703 if (GET_CODE (x1) == CONST_INT)
704 if (GET_CODE (y1) == CONST_INT)
705 return memrefs_conflict_p (xsize, x0, ysize, y0,
706 c - INTVAL (x1) + INTVAL (y1));
708 return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1));
709 else if (GET_CODE (y1) == CONST_INT)
710 return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1));
712 /* Handle case where we cannot understand iteration operators,
713 but we notice that the base addresses are distinct objects. */
714 x = find_symbolic_term (x);
717 y = find_symbolic_term (y);
720 return rtx_equal_for_memref_p (x, y);
722 else if (GET_CODE (x1) == CONST_INT)
723 return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1));
725 else if (GET_CODE (y) == PLUS)
727 /* The fact that Y is canonicalized means that this
728 PLUS rtx is canonicalized. */
729 rtx y0 = XEXP (y, 0);
730 rtx y1 = XEXP (y, 1);
732 if (GET_CODE (y1) == CONST_INT)
733 return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1));
738 if (GET_CODE (x) == GET_CODE (y))
739 switch (GET_CODE (x))
743 /* Handle cases where we expect the second operands to be the
744 same, and check only whether the first operand would conflict
747 rtx x1 = canon_rtx (XEXP (x, 1));
748 rtx y1 = canon_rtx (XEXP (y, 1));
749 if (! rtx_equal_for_memref_p (x1, y1))
751 x0 = canon_rtx (XEXP (x, 0));
752 y0 = canon_rtx (XEXP (y, 0));
753 if (rtx_equal_for_memref_p (x0, y0))
754 return (xsize == 0 || ysize == 0
755 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
757 /* Can't properly adjust our sizes. */
758 if (GET_CODE (x1) != CONST_INT)
760 xsize /= INTVAL (x1);
761 ysize /= INTVAL (x1);
763 return memrefs_conflict_p (xsize, x0, ysize, y0, c);
769 if (GET_CODE (x) == CONST_INT && GET_CODE (y) == CONST_INT)
771 c += (INTVAL (y) - INTVAL (x));
772 return (xsize == 0 || ysize == 0
773 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
776 if (GET_CODE (x) == CONST)
778 if (GET_CODE (y) == CONST)
779 return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
780 ysize, canon_rtx (XEXP (y, 0)), c);
782 return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
785 if (GET_CODE (y) == CONST)
786 return memrefs_conflict_p (xsize, x, ysize,
787 canon_rtx (XEXP (y, 0)), c);
790 return (rtx_equal_for_memref_p (x, y)
791 && (xsize == 0 || ysize == 0
792 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0)));
799 /* Functions to compute memory dependencies.
801 Since we process the insns in execution order, we can build tables
802 to keep track of what registers are fixed (and not aliased), what registers
803 are varying in known ways, and what registers are varying in unknown
806 If both memory references are volatile, then there must always be a
807 dependence between the two references, since their order can not be
808 changed. A volatile and non-volatile reference can be interchanged
811 A MEM_IN_STRUCT reference at a non-QImode non-AND varying address can never
812 conflict with a non-MEM_IN_STRUCT reference at a fixed address. We must
813 allow QImode aliasing because the ANSI C standard allows character
814 pointers to alias anything. We are assuming that characters are
815 always QImode here. We also must allow AND addresses, because they may
816 generate accesses outside the object being referenced. This is used to
817 generate aligned addresses from unaligned addresses, for instance, the
818 alpha storeqi_unaligned pattern. */
820 /* Read dependence: X is read after read in MEM takes place. There can
821 only be a dependence here if both reads are volatile. */
824 read_dependence (mem, x)
828 return MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem);
831 /* True dependence: X is read after store in MEM takes place. */
834 true_dependence (mem, x)
838 /* If X is an unchanging read, then it can't possibly conflict with any
839 non-unchanging store. It may conflict with an unchanging write though,
840 because there may be a single store to this address to initialize it.
841 Just fall through to the code below to resolve the case where we have
842 both an unchanging read and an unchanging write. This won't handle all
843 cases optimally, but the possible performance loss should be
846 mem = canon_rtx (mem);
847 if (RTX_UNCHANGING_P (x) && ! RTX_UNCHANGING_P (mem))
850 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
851 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
852 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
853 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
854 && GET_MODE (mem) != QImode
855 && GET_CODE (XEXP (mem, 0)) != AND
856 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
857 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
858 && GET_MODE (x) != QImode
859 && GET_CODE (XEXP (x, 0)) != AND
860 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
863 /* Anti dependence: X is written after read in MEM takes place. */
866 anti_dependence (mem, x)
870 /* If MEM is an unchanging read, then it can't possibly conflict with
871 the store to X, because there is at most one store to MEM, and it must
872 have occurred somewhere before MEM. */
874 mem = canon_rtx (mem);
875 if (RTX_UNCHANGING_P (mem))
878 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
879 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
880 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
881 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
882 && GET_MODE (mem) != QImode
883 && GET_CODE (XEXP (mem, 0)) != AND
884 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
885 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
886 && GET_MODE (x) != QImode
887 && GET_CODE (XEXP (x, 0)) != AND
888 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
891 /* Output dependence: X is written after store in MEM takes place. */
894 output_dependence (mem, x)
899 mem = canon_rtx (mem);
900 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
901 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
902 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
903 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
904 && GET_MODE (mem) != QImode
905 && GET_CODE (XEXP (mem, 0)) != AND
906 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
907 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
908 && GET_MODE (x) != QImode
909 && GET_CODE (XEXP (x, 0)) != AND
910 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
913 /* Helper functions for instruction scheduling. */
915 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
916 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
917 of dependence that this link represents. */
920 add_dependence (insn, elem, dep_type)
923 enum reg_note dep_type;
927 /* Don't depend an insn on itself. */
931 /* If elem is part of a sequence that must be scheduled together, then
932 make the dependence point to the last insn of the sequence.
933 When HAVE_cc0, it is possible for NOTEs to exist between users and
934 setters of the condition codes, so we must skip past notes here.
935 Otherwise, NOTEs are impossible here. */
937 next = NEXT_INSN (elem);
940 while (next && GET_CODE (next) == NOTE)
941 next = NEXT_INSN (next);
944 if (next && SCHED_GROUP_P (next)
945 && GET_CODE (next) != CODE_LABEL)
947 /* Notes will never intervene here though, so don't bother checking
949 /* We must reject CODE_LABELs, so that we don't get confused by one
950 that has LABEL_PRESERVE_P set, which is represented by the same
951 bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be
953 while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next))
954 && GET_CODE (NEXT_INSN (next)) != CODE_LABEL)
955 next = NEXT_INSN (next);
957 /* Again, don't depend an insn on itself. */
961 /* Make the dependence to NEXT, the last insn of the group, instead
962 of the original ELEM. */
966 /* Check that we don't already have this dependence. */
967 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
968 if (XEXP (link, 0) == elem)
970 /* If this is a more restrictive type of dependence than the existing
971 one, then change the existing dependence to this type. */
972 if ((int) dep_type < (int) REG_NOTE_KIND (link))
973 PUT_REG_NOTE_KIND (link, dep_type);
976 /* Might want to check one level of transitivity to save conses. */
978 link = rtx_alloc (INSN_LIST);
979 /* Insn dependency, not data dependency. */
980 PUT_REG_NOTE_KIND (link, dep_type);
981 XEXP (link, 0) = elem;
982 XEXP (link, 1) = LOG_LINKS (insn);
983 LOG_LINKS (insn) = link;
986 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
987 of INSN. Abort if not found. */
990 remove_dependence (insn, elem)
997 for (prev = 0, link = LOG_LINKS (insn); link;
998 prev = link, link = XEXP (link, 1))
1000 if (XEXP (link, 0) == elem)
1003 XEXP (prev, 1) = XEXP (link, 1);
1005 LOG_LINKS (insn) = XEXP (link, 1);
1015 #ifndef INSN_SCHEDULING
1017 schedule_insns (dump_file)
1026 /* Computation of memory dependencies. */
1028 /* The *_insns and *_mems are paired lists. Each pending memory operation
1029 will have a pointer to the MEM rtx on one list and a pointer to the
1030 containing insn on the other list in the same place in the list. */
1032 /* We can't use add_dependence like the old code did, because a single insn
1033 may have multiple memory accesses, and hence needs to be on the list
1034 once for each memory access. Add_dependence won't let you add an insn
1035 to a list more than once. */
1037 /* An INSN_LIST containing all insns with pending read operations. */
1038 static rtx pending_read_insns;
1040 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
1041 static rtx pending_read_mems;
1043 /* An INSN_LIST containing all insns with pending write operations. */
1044 static rtx pending_write_insns;
1046 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
1047 static rtx pending_write_mems;
1049 /* Indicates the combined length of the two pending lists. We must prevent
1050 these lists from ever growing too large since the number of dependencies
1051 produced is at least O(N*N), and execution time is at least O(4*N*N), as
1052 a function of the length of these pending lists. */
1054 static int pending_lists_length;
1056 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
1058 static rtx unused_insn_list;
1060 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
1062 static rtx unused_expr_list;
1064 /* The last insn upon which all memory references must depend.
1065 This is an insn which flushed the pending lists, creating a dependency
1066 between it and all previously pending memory references. This creates
1067 a barrier (or a checkpoint) which no memory reference is allowed to cross.
1069 This includes all non constant CALL_INSNs. When we do interprocedural
1070 alias analysis, this restriction can be relaxed.
1071 This may also be an INSN that writes memory if the pending lists grow
1074 static rtx last_pending_memory_flush;
1076 /* The last function call we have seen. All hard regs, and, of course,
1077 the last function call, must depend on this. */
1079 static rtx last_function_call;
1081 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
1082 that does not already cross a call. We create dependencies between each
1083 of those insn and the next call insn, to ensure that they won't cross a call
1084 after scheduling is done. */
1086 static rtx sched_before_next_call;
1088 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
1089 so that insns independent of the last scheduled insn will be preferred
1090 over dependent instructions. */
1092 static rtx last_scheduled_insn;
1094 /* Process an insn's memory dependencies. There are four kinds of
1097 (0) read dependence: read follows read
1098 (1) true dependence: read follows write
1099 (2) anti dependence: write follows read
1100 (3) output dependence: write follows write
1102 We are careful to build only dependencies which actually exist, and
1103 use transitivity to avoid building too many links. */
1105 /* Return the INSN_LIST containing INSN in LIST, or NULL
1106 if LIST does not contain INSN. */
1109 find_insn_list (insn, list)
1115 if (XEXP (list, 0) == insn)
1117 list = XEXP (list, 1);
1122 /* Compute the function units used by INSN. This caches the value
1123 returned by function_units_used. A function unit is encoded as the
1124 unit number if the value is non-negative and the compliment of a
1125 mask if the value is negative. A function unit index is the
1126 non-negative encoding. */
1132 register int unit = INSN_UNIT (insn);
1136 recog_memoized (insn);
1138 /* A USE insn, or something else we don't need to understand.
1139 We can't pass these directly to function_units_used because it will
1140 trigger a fatal error for unrecognizable insns. */
1141 if (INSN_CODE (insn) < 0)
1145 unit = function_units_used (insn);
1146 /* Increment non-negative values so we can cache zero. */
1147 if (unit >= 0) unit++;
1149 /* We only cache 16 bits of the result, so if the value is out of
1150 range, don't cache it. */
1151 if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
1153 || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
1154 INSN_UNIT (insn) = unit;
1156 return (unit > 0 ? unit - 1 : unit);
1159 /* Compute the blockage range for executing INSN on UNIT. This caches
1160 the value returned by the blockage_range_function for the unit.
1161 These values are encoded in an int where the upper half gives the
1162 minimum value and the lower half gives the maximum value. */
1164 __inline static unsigned int
1165 blockage_range (unit, insn)
1169 unsigned int blockage = INSN_BLOCKAGE (insn);
1172 if (UNIT_BLOCKED (blockage) != unit + 1)
1174 range = function_units[unit].blockage_range_function (insn);
1175 /* We only cache the blockage range for one unit and then only if
1177 if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
1178 INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
1181 range = BLOCKAGE_RANGE (blockage);
1186 /* A vector indexed by function unit instance giving the last insn to use
1187 the unit. The value of the function unit instance index for unit U
1188 instance I is (U + I * FUNCTION_UNITS_SIZE). */
1189 static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
1191 /* A vector indexed by function unit instance giving the minimum time when
1192 the unit will unblock based on the maximum blockage cost. */
1193 static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
1195 /* A vector indexed by function unit number giving the number of insns
1196 that remain to use the unit. */
1197 static int unit_n_insns[FUNCTION_UNITS_SIZE];
1199 /* Reset the function unit state to the null state. */
1204 bzero ((char *) unit_last_insn, sizeof (unit_last_insn));
1205 bzero ((char *) unit_tick, sizeof (unit_tick));
1206 bzero ((char *) unit_n_insns, sizeof (unit_n_insns));
1209 /* Record an insn as one that will use the units encoded by UNIT. */
1211 __inline static void
1218 unit_n_insns[unit]++;
1220 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1221 if ((unit & 1) != 0)
1225 /* Return the actual hazard cost of executing INSN on the unit UNIT,
1226 instance INSTANCE at time CLOCK if the previous actual hazard cost
1230 actual_hazard_this_instance (unit, instance, insn, clock, cost)
1231 int unit, instance, clock, cost;
1234 int tick = unit_tick[instance];
1236 if (tick - clock > cost)
1238 /* The scheduler is operating in reverse, so INSN is the executing
1239 insn and the unit's last insn is the candidate insn. We want a
1240 more exact measure of the blockage if we execute INSN at CLOCK
1241 given when we committed the execution of the unit's last insn.
1243 The blockage value is given by either the unit's max blockage
1244 constant, blockage range function, or blockage function. Use
1245 the most exact form for the given unit. */
1247 if (function_units[unit].blockage_range_function)
1249 if (function_units[unit].blockage_function)
1250 tick += (function_units[unit].blockage_function
1251 (insn, unit_last_insn[instance])
1252 - function_units[unit].max_blockage);
1254 tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
1255 - function_units[unit].max_blockage);
1257 if (tick - clock > cost)
1258 cost = tick - clock;
1263 /* Record INSN as having begun execution on the units encoded by UNIT at
1266 __inline static void
1267 schedule_unit (unit, insn, clock)
1275 int instance = unit;
1276 #if MAX_MULTIPLICITY > 1
1277 /* Find the first free instance of the function unit and use that
1278 one. We assume that one is free. */
1279 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
1281 if (! actual_hazard_this_instance (unit, instance, insn, clock, 0))
1283 instance += FUNCTION_UNITS_SIZE;
1286 unit_last_insn[instance] = insn;
1287 unit_tick[instance] = (clock + function_units[unit].max_blockage);
1290 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1291 if ((unit & 1) != 0)
1292 schedule_unit (i, insn, clock);
1295 /* Return the actual hazard cost of executing INSN on the units encoded by
1296 UNIT at time CLOCK if the previous actual hazard cost was COST. */
1299 actual_hazard (unit, insn, clock, cost)
1300 int unit, clock, cost;
1307 /* Find the instance of the function unit with the minimum hazard. */
1308 int instance = unit;
1309 int best_cost = actual_hazard_this_instance (unit, instance, insn,
1313 #if MAX_MULTIPLICITY > 1
1314 if (best_cost > cost)
1316 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
1318 instance += FUNCTION_UNITS_SIZE;
1319 this_cost = actual_hazard_this_instance (unit, instance, insn,
1321 if (this_cost < best_cost)
1323 best_cost = this_cost;
1324 if (this_cost <= cost)
1330 cost = MAX (cost, best_cost);
1333 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1334 if ((unit & 1) != 0)
1335 cost = actual_hazard (i, insn, clock, cost);
1340 /* Return the potential hazard cost of executing an instruction on the
1341 units encoded by UNIT if the previous potential hazard cost was COST.
1342 An insn with a large blockage time is chosen in preference to one
1343 with a smaller time; an insn that uses a unit that is more likely
1344 to be used is chosen in preference to one with a unit that is less
1345 used. We are trying to minimize a subsequent actual hazard. */
1348 potential_hazard (unit, insn, cost)
1353 unsigned int minb, maxb;
1357 minb = maxb = function_units[unit].max_blockage;
1360 if (function_units[unit].blockage_range_function)
1362 maxb = minb = blockage_range (unit, insn);
1363 maxb = MAX_BLOCKAGE_COST (maxb);
1364 minb = MIN_BLOCKAGE_COST (minb);
1369 /* Make the number of instructions left dominate. Make the
1370 minimum delay dominate the maximum delay. If all these
1371 are the same, use the unit number to add an arbitrary
1372 ordering. Other terms can be added. */
1373 ncost = minb * 0x40 + maxb;
1374 ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
1381 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1382 if ((unit & 1) != 0)
1383 cost = potential_hazard (i, insn, cost);
1388 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
1389 This is the number of virtual cycles taken between instruction issue and
1390 instruction results. */
1393 insn_cost (insn, link, used)
1394 rtx insn, link, used;
1396 register int cost = INSN_COST (insn);
1400 recog_memoized (insn);
1402 /* A USE insn, or something else we don't need to understand.
1403 We can't pass these directly to result_ready_cost because it will
1404 trigger a fatal error for unrecognizable insns. */
1405 if (INSN_CODE (insn) < 0)
1407 INSN_COST (insn) = 1;
1412 cost = result_ready_cost (insn);
1417 INSN_COST (insn) = cost;
1421 /* A USE insn should never require the value used to be computed. This
1422 allows the computation of a function's result and parameter values to
1423 overlap the return and call. */
1424 recog_memoized (used);
1425 if (INSN_CODE (used) < 0)
1426 LINK_COST_FREE (link) = 1;
1428 /* If some dependencies vary the cost, compute the adjustment. Most
1429 commonly, the adjustment is complete: either the cost is ignored
1430 (in the case of an output- or anti-dependence), or the cost is
1431 unchanged. These values are cached in the link as LINK_COST_FREE
1432 and LINK_COST_ZERO. */
1434 if (LINK_COST_FREE (link))
1437 else if (! LINK_COST_ZERO (link))
1441 ADJUST_COST (used, link, insn, ncost);
1443 LINK_COST_FREE (link) = ncost = 1;
1445 LINK_COST_ZERO (link) = 1;
1452 /* Compute the priority number for INSN. */
1458 if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1462 int this_priority = INSN_PRIORITY (insn);
1465 if (this_priority > 0)
1466 return this_priority;
1470 /* Nonzero if these insns must be scheduled together. */
1471 if (SCHED_GROUP_P (insn))
1474 while (SCHED_GROUP_P (prev))
1476 prev = PREV_INSN (prev);
1477 INSN_REF_COUNT (prev) += 1;
1481 for (prev = LOG_LINKS (insn); prev; prev = XEXP (prev, 1))
1483 rtx x = XEXP (prev, 0);
1485 /* A dependence pointing to a note or deleted insn is always
1486 obsolete, because sched_analyze_insn will have created any
1487 necessary new dependences which replace it. Notes and deleted
1488 insns can be created when instructions are deleted by insn
1489 splitting, or by register allocation. */
1490 if (GET_CODE (x) == NOTE || INSN_DELETED_P (x))
1492 remove_dependence (insn, x);
1496 /* Clear the link cost adjustment bits. */
1497 LINK_COST_FREE (prev) = 0;
1499 LINK_COST_ZERO (prev) = 0;
1502 /* This priority calculation was chosen because it results in the
1503 least instruction movement, and does not hurt the performance
1504 of the resulting code compared to the old algorithm.
1505 This makes the sched algorithm more stable, which results
1506 in better code, because there is less register pressure,
1507 cross jumping is more likely to work, and debugging is easier.
1509 When all instructions have a latency of 1, there is no need to
1510 move any instructions. Subtracting one here ensures that in such
1511 cases all instructions will end up with a priority of one, and
1512 hence no scheduling will be done.
1514 The original code did not subtract the one, and added the
1515 insn_cost of the current instruction to its priority (e.g.
1516 move the insn_cost call down to the end). */
1518 prev_priority = priority (x) + insn_cost (x, prev, insn) - 1;
1520 if (prev_priority > max_priority)
1521 max_priority = prev_priority;
1522 INSN_REF_COUNT (x) += 1;
1525 prepare_unit (insn_unit (insn));
1526 INSN_PRIORITY (insn) = max_priority;
1527 return INSN_PRIORITY (insn);
1532 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
1533 them to the unused_*_list variables, so that they can be reused. */
1536 free_pending_lists ()
1538 register rtx link, prev_link;
1540 if (pending_read_insns)
1542 prev_link = pending_read_insns;
1543 link = XEXP (prev_link, 1);
1548 link = XEXP (link, 1);
1551 XEXP (prev_link, 1) = unused_insn_list;
1552 unused_insn_list = pending_read_insns;
1553 pending_read_insns = 0;
1556 if (pending_write_insns)
1558 prev_link = pending_write_insns;
1559 link = XEXP (prev_link, 1);
1564 link = XEXP (link, 1);
1567 XEXP (prev_link, 1) = unused_insn_list;
1568 unused_insn_list = pending_write_insns;
1569 pending_write_insns = 0;
1572 if (pending_read_mems)
1574 prev_link = pending_read_mems;
1575 link = XEXP (prev_link, 1);
1580 link = XEXP (link, 1);
1583 XEXP (prev_link, 1) = unused_expr_list;
1584 unused_expr_list = pending_read_mems;
1585 pending_read_mems = 0;
1588 if (pending_write_mems)
1590 prev_link = pending_write_mems;
1591 link = XEXP (prev_link, 1);
1596 link = XEXP (link, 1);
1599 XEXP (prev_link, 1) = unused_expr_list;
1600 unused_expr_list = pending_write_mems;
1601 pending_write_mems = 0;
1605 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
1606 The MEM is a memory reference contained within INSN, which we are saving
1607 so that we can do memory aliasing on it. */
1610 add_insn_mem_dependence (insn_list, mem_list, insn, mem)
1611 rtx *insn_list, *mem_list, insn, mem;
1615 if (unused_insn_list)
1617 link = unused_insn_list;
1618 unused_insn_list = XEXP (link, 1);
1621 link = rtx_alloc (INSN_LIST);
1622 XEXP (link, 0) = insn;
1623 XEXP (link, 1) = *insn_list;
1626 if (unused_expr_list)
1628 link = unused_expr_list;
1629 unused_expr_list = XEXP (link, 1);
1632 link = rtx_alloc (EXPR_LIST);
1633 XEXP (link, 0) = mem;
1634 XEXP (link, 1) = *mem_list;
1637 pending_lists_length++;
1640 /* Make a dependency between every memory reference on the pending lists
1641 and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush
1645 flush_pending_lists (insn, only_write)
1651 while (pending_read_insns && ! only_write)
1653 add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI);
1655 link = pending_read_insns;
1656 pending_read_insns = XEXP (pending_read_insns, 1);
1657 XEXP (link, 1) = unused_insn_list;
1658 unused_insn_list = link;
1660 link = pending_read_mems;
1661 pending_read_mems = XEXP (pending_read_mems, 1);
1662 XEXP (link, 1) = unused_expr_list;
1663 unused_expr_list = link;
1665 while (pending_write_insns)
1667 add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI);
1669 link = pending_write_insns;
1670 pending_write_insns = XEXP (pending_write_insns, 1);
1671 XEXP (link, 1) = unused_insn_list;
1672 unused_insn_list = link;
1674 link = pending_write_mems;
1675 pending_write_mems = XEXP (pending_write_mems, 1);
1676 XEXP (link, 1) = unused_expr_list;
1677 unused_expr_list = link;
1679 pending_lists_length = 0;
1681 if (last_pending_memory_flush)
1682 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1684 last_pending_memory_flush = insn;
1687 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
1688 by the write to the destination of X, and reads of everything mentioned. */
1691 sched_analyze_1 (x, insn)
1696 register rtx dest = SET_DEST (x);
1701 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
1702 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
1704 if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
1706 /* The second and third arguments are values read by this insn. */
1707 sched_analyze_2 (XEXP (dest, 1), insn);
1708 sched_analyze_2 (XEXP (dest, 2), insn);
1710 dest = SUBREG_REG (dest);
1713 if (GET_CODE (dest) == REG)
1717 regno = REGNO (dest);
1719 /* A hard reg in a wide mode may really be multiple registers.
1720 If so, mark all of them just like the first. */
1721 if (regno < FIRST_PSEUDO_REGISTER)
1723 i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
1728 for (u = reg_last_uses[regno+i]; u; u = XEXP (u, 1))
1729 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1730 reg_last_uses[regno + i] = 0;
1731 if (reg_last_sets[regno + i])
1732 add_dependence (insn, reg_last_sets[regno + i],
1734 SET_REGNO_REG_SET (reg_pending_sets, regno + i);
1735 if ((call_used_regs[i] || global_regs[i])
1736 && last_function_call)
1737 /* Function calls clobber all call_used regs. */
1738 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1745 for (u = reg_last_uses[regno]; u; u = XEXP (u, 1))
1746 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1747 reg_last_uses[regno] = 0;
1748 if (reg_last_sets[regno])
1749 add_dependence (insn, reg_last_sets[regno], REG_DEP_OUTPUT);
1750 SET_REGNO_REG_SET (reg_pending_sets, regno);
1752 /* Pseudos that are REG_EQUIV to something may be replaced
1753 by that during reloading. We need only add dependencies for
1754 the address in the REG_EQUIV note. */
1755 if (! reload_completed
1756 && reg_known_equiv_p[regno]
1757 && GET_CODE (reg_known_value[regno]) == MEM)
1758 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
1760 /* Don't let it cross a call after scheduling if it doesn't
1761 already cross one. */
1762 if (REG_N_CALLS_CROSSED (regno) == 0 && last_function_call)
1763 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1766 else if (GET_CODE (dest) == MEM)
1768 /* Writing memory. */
1770 if (pending_lists_length > 32)
1772 /* Flush all pending reads and writes to prevent the pending lists
1773 from getting any larger. Insn scheduling runs too slowly when
1774 these lists get long. The number 32 was chosen because it
1775 seems like a reasonable number. When compiling GCC with itself,
1776 this flush occurs 8 times for sparc, and 10 times for m88k using
1778 flush_pending_lists (insn, 0);
1782 rtx pending, pending_mem;
1784 pending = pending_read_insns;
1785 pending_mem = pending_read_mems;
1788 /* If a dependency already exists, don't create a new one. */
1789 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1790 if (anti_dependence (XEXP (pending_mem, 0), dest))
1791 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
1793 pending = XEXP (pending, 1);
1794 pending_mem = XEXP (pending_mem, 1);
1797 pending = pending_write_insns;
1798 pending_mem = pending_write_mems;
1801 /* If a dependency already exists, don't create a new one. */
1802 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1803 if (output_dependence (XEXP (pending_mem, 0), dest))
1804 add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT);
1806 pending = XEXP (pending, 1);
1807 pending_mem = XEXP (pending_mem, 1);
1810 if (last_pending_memory_flush)
1811 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1813 add_insn_mem_dependence (&pending_write_insns, &pending_write_mems,
1816 sched_analyze_2 (XEXP (dest, 0), insn);
1819 /* Analyze reads. */
1820 if (GET_CODE (x) == SET)
1821 sched_analyze_2 (SET_SRC (x), insn);
1824 /* Analyze the uses of memory and registers in rtx X in INSN. */
1827 sched_analyze_2 (x, insn)
1833 register enum rtx_code code;
1839 code = GET_CODE (x);
1848 /* Ignore constants. Note that we must handle CONST_DOUBLE here
1849 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
1850 this does not mean that this insn is using cc0. */
1858 /* User of CC0 depends on immediately preceding insn. */
1859 SCHED_GROUP_P (insn) = 1;
1861 /* There may be a note before this insn now, but all notes will
1862 be removed before we actually try to schedule the insns, so
1863 it won't cause a problem later. We must avoid it here though. */
1864 prev = prev_nonnote_insn (insn);
1866 /* Make a copy of all dependencies on the immediately previous insn,
1867 and add to this insn. This is so that all the dependencies will
1868 apply to the group. Remove an explicit dependence on this insn
1869 as SCHED_GROUP_P now represents it. */
1871 if (find_insn_list (prev, LOG_LINKS (insn)))
1872 remove_dependence (insn, prev);
1874 for (link = LOG_LINKS (prev); link; link = XEXP (link, 1))
1875 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
1883 int regno = REGNO (x);
1884 if (regno < FIRST_PSEUDO_REGISTER)
1888 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
1891 reg_last_uses[regno + i]
1892 = gen_rtx (INSN_LIST, VOIDmode,
1893 insn, reg_last_uses[regno + i]);
1894 if (reg_last_sets[regno + i])
1895 add_dependence (insn, reg_last_sets[regno + i], 0);
1896 if ((call_used_regs[regno + i] || global_regs[regno + i])
1897 && last_function_call)
1898 /* Function calls clobber all call_used regs. */
1899 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1904 reg_last_uses[regno]
1905 = gen_rtx (INSN_LIST, VOIDmode, insn, reg_last_uses[regno]);
1906 if (reg_last_sets[regno])
1907 add_dependence (insn, reg_last_sets[regno], 0);
1909 /* Pseudos that are REG_EQUIV to something may be replaced
1910 by that during reloading. We need only add dependencies for
1911 the address in the REG_EQUIV note. */
1912 if (! reload_completed
1913 && reg_known_equiv_p[regno]
1914 && GET_CODE (reg_known_value[regno]) == MEM)
1915 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
1917 /* If the register does not already cross any calls, then add this
1918 insn to the sched_before_next_call list so that it will still
1919 not cross calls after scheduling. */
1920 if (REG_N_CALLS_CROSSED (regno) == 0)
1921 add_dependence (sched_before_next_call, insn, REG_DEP_ANTI);
1928 /* Reading memory. */
1930 rtx pending, pending_mem;
1932 pending = pending_read_insns;
1933 pending_mem = pending_read_mems;
1936 /* If a dependency already exists, don't create a new one. */
1937 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1938 if (read_dependence (XEXP (pending_mem, 0), x))
1939 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
1941 pending = XEXP (pending, 1);
1942 pending_mem = XEXP (pending_mem, 1);
1945 pending = pending_write_insns;
1946 pending_mem = pending_write_mems;
1949 /* If a dependency already exists, don't create a new one. */
1950 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1951 if (true_dependence (XEXP (pending_mem, 0), x))
1952 add_dependence (insn, XEXP (pending, 0), 0);
1954 pending = XEXP (pending, 1);
1955 pending_mem = XEXP (pending_mem, 1);
1957 if (last_pending_memory_flush)
1958 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1960 /* Always add these dependencies to pending_reads, since
1961 this insn may be followed by a write. */
1962 add_insn_mem_dependence (&pending_read_insns, &pending_read_mems,
1965 /* Take advantage of tail recursion here. */
1966 sched_analyze_2 (XEXP (x, 0), insn);
1972 case UNSPEC_VOLATILE:
1977 /* Traditional and volatile asm instructions must be considered to use
1978 and clobber all hard registers, all pseudo-registers and all of
1979 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
1981 Consider for instance a volatile asm that changes the fpu rounding
1982 mode. An insn should not be moved across this even if it only uses
1983 pseudo-regs because it might give an incorrectly rounded result. */
1984 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
1986 int max_reg = max_reg_num ();
1987 for (i = 0; i < max_reg; i++)
1989 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
1990 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1991 reg_last_uses[i] = 0;
1992 if (reg_last_sets[i])
1993 add_dependence (insn, reg_last_sets[i], 0);
1995 reg_pending_sets_all = 1;
1997 flush_pending_lists (insn, 0);
2000 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
2001 We can not just fall through here since then we would be confused
2002 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
2003 traditional asms unlike their normal usage. */
2005 if (code == ASM_OPERANDS)
2007 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
2008 sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn);
2018 /* These both read and modify the result. We must handle them as writes
2019 to get proper dependencies for following instructions. We must handle
2020 them as reads to get proper dependencies from this to previous
2021 instructions. Thus we need to pass them to both sched_analyze_1
2022 and sched_analyze_2. We must call sched_analyze_2 first in order
2023 to get the proper antecedent for the read. */
2024 sched_analyze_2 (XEXP (x, 0), insn);
2025 sched_analyze_1 (x, insn);
2029 /* Other cases: walk the insn. */
2030 fmt = GET_RTX_FORMAT (code);
2031 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2034 sched_analyze_2 (XEXP (x, i), insn);
2035 else if (fmt[i] == 'E')
2036 for (j = 0; j < XVECLEN (x, i); j++)
2037 sched_analyze_2 (XVECEXP (x, i, j), insn);
2041 /* Analyze an INSN with pattern X to find all dependencies. */
2044 sched_analyze_insn (x, insn, loop_notes)
2048 register RTX_CODE code = GET_CODE (x);
2050 int maxreg = max_reg_num ();
2053 if (code == SET || code == CLOBBER)
2054 sched_analyze_1 (x, insn);
2055 else if (code == PARALLEL)
2058 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2060 code = GET_CODE (XVECEXP (x, 0, i));
2061 if (code == SET || code == CLOBBER)
2062 sched_analyze_1 (XVECEXP (x, 0, i), insn);
2064 sched_analyze_2 (XVECEXP (x, 0, i), insn);
2068 sched_analyze_2 (x, insn);
2070 /* Mark registers CLOBBERED or used by called function. */
2071 if (GET_CODE (insn) == CALL_INSN)
2072 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
2074 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
2075 sched_analyze_1 (XEXP (link, 0), insn);
2077 sched_analyze_2 (XEXP (link, 0), insn);
2080 /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic block, then
2081 we must be sure that no instructions are scheduled across it.
2082 Otherwise, the reg_n_refs info (which depends on loop_depth) would
2083 become incorrect. */
2087 int max_reg = max_reg_num ();
2090 for (i = 0; i < max_reg; i++)
2093 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
2094 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
2095 reg_last_uses[i] = 0;
2096 if (reg_last_sets[i])
2097 add_dependence (insn, reg_last_sets[i], 0);
2099 reg_pending_sets_all = 1;
2101 flush_pending_lists (insn, 0);
2104 while (XEXP (link, 1))
2105 link = XEXP (link, 1);
2106 XEXP (link, 1) = REG_NOTES (insn);
2107 REG_NOTES (insn) = loop_notes;
2110 /* After reload, it is possible for an instruction to have a REG_DEAD note
2111 for a register that actually dies a few instructions earlier. For
2112 example, this can happen with SECONDARY_MEMORY_NEEDED reloads.
2113 In this case, we must consider the insn to use the register mentioned
2114 in the REG_DEAD note. Otherwise, we may accidentally move this insn
2115 after another insn that sets the register, thus getting obviously invalid
2116 rtl. This confuses reorg which believes that REG_DEAD notes are still
2119 ??? We would get better code if we fixed reload to put the REG_DEAD
2120 notes in the right places, but that may not be worth the effort. */
2122 if (reload_completed)
2126 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2127 if (REG_NOTE_KIND (note) == REG_DEAD)
2128 sched_analyze_2 (XEXP (note, 0), insn);
2131 EXECUTE_IF_SET_AND_RESET_IN_REG_SET (reg_pending_sets, 0, i,
2133 reg_last_sets[i] = insn;
2136 if (reg_pending_sets_all)
2138 for (i = 0; i < maxreg; i++)
2139 reg_last_sets[i] = insn;
2140 reg_pending_sets_all = 0;
2143 /* Handle function calls and function returns created by the epilogue
2145 if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
2150 /* When scheduling instructions, we make sure calls don't lose their
2151 accompanying USE insns by depending them one on another in order.
2153 Also, we must do the same thing for returns created by the epilogue
2154 threading code. Note this code works only in this special case,
2155 because other passes make no guarantee that they will never emit
2156 an instruction between a USE and a RETURN. There is such a guarantee
2157 for USE instructions immediately before a call. */
2159 prev_dep_insn = insn;
2160 dep_insn = PREV_INSN (insn);
2161 while (GET_CODE (dep_insn) == INSN
2162 && GET_CODE (PATTERN (dep_insn)) == USE
2163 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG)
2165 SCHED_GROUP_P (prev_dep_insn) = 1;
2167 /* Make a copy of all dependencies on dep_insn, and add to insn.
2168 This is so that all of the dependencies will apply to the
2171 for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1))
2172 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
2174 prev_dep_insn = dep_insn;
2175 dep_insn = PREV_INSN (dep_insn);
2180 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
2181 for every dependency. */
2184 sched_analyze (head, tail)
2188 register int n_insns = 0;
2190 register int luid = 0;
2193 for (insn = head; ; insn = NEXT_INSN (insn))
2195 INSN_LUID (insn) = luid++;
2197 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
2199 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
2203 else if (GET_CODE (insn) == CALL_INSN)
2208 /* Any instruction using a hard register which may get clobbered
2209 by a call needs to be marked as dependent on this call.
2210 This prevents a use of a hard return reg from being moved
2211 past a void call (i.e. it does not explicitly set the hard
2214 /* If this call is followed by a NOTE_INSN_SETJMP, then assume that
2215 all registers, not just hard registers, may be clobbered by this
2218 /* Insn, being a CALL_INSN, magically depends on
2219 `last_function_call' already. */
2221 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE
2222 && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP)
2224 int max_reg = max_reg_num ();
2225 for (i = 0; i < max_reg; i++)
2227 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
2228 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
2229 reg_last_uses[i] = 0;
2230 if (reg_last_sets[i])
2231 add_dependence (insn, reg_last_sets[i], 0);
2233 reg_pending_sets_all = 1;
2235 /* Add a pair of fake REG_NOTEs which we will later
2236 convert back into a NOTE_INSN_SETJMP note. See
2237 reemit_notes for why we use a pair of of NOTEs. */
2239 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_DEAD,
2242 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_DEAD,
2243 GEN_INT (NOTE_INSN_SETJMP),
2248 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2249 if (call_used_regs[i] || global_regs[i])
2251 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
2252 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
2253 reg_last_uses[i] = 0;
2254 if (reg_last_sets[i])
2255 add_dependence (insn, reg_last_sets[i], REG_DEP_ANTI);
2256 SET_REGNO_REG_SET (reg_pending_sets, i);
2260 /* For each insn which shouldn't cross a call, add a dependence
2261 between that insn and this call insn. */
2262 x = LOG_LINKS (sched_before_next_call);
2265 add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI);
2268 LOG_LINKS (sched_before_next_call) = 0;
2270 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
2273 /* In the absence of interprocedural alias analysis, we must flush
2274 all pending reads and writes, and start new dependencies starting
2275 from here. But only flush writes for constant calls (which may
2276 be passed a pointer to something we haven't written yet). */
2277 flush_pending_lists (insn, CONST_CALL_P (insn));
2279 /* Depend this function call (actually, the user of this
2280 function call) on all hard register clobberage. */
2281 last_function_call = insn;
2285 /* See comments on reemit_notes as to why we do this. */
2286 else if (GET_CODE (insn) == NOTE
2287 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG
2288 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END
2289 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG
2290 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END
2291 || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP
2292 && GET_CODE (PREV_INSN (insn)) != CALL_INSN)))
2294 loop_notes = gen_rtx (EXPR_LIST, REG_DEAD,
2295 GEN_INT (NOTE_BLOCK_NUMBER (insn)), loop_notes);
2296 loop_notes = gen_rtx (EXPR_LIST, REG_DEAD,
2297 GEN_INT (NOTE_LINE_NUMBER (insn)), loop_notes);
2298 CONST_CALL_P (loop_notes) = CONST_CALL_P (insn);
2308 /* Called when we see a set of a register. If death is true, then we are
2309 scanning backwards. Mark that register as unborn. If nobody says
2310 otherwise, that is how things will remain. If death is false, then we
2311 are scanning forwards. Mark that register as being born. */
2314 sched_note_set (b, x, death)
2320 register rtx reg = SET_DEST (x);
2326 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART
2327 || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT)
2329 /* Must treat modification of just one hardware register of a multi-reg
2330 value or just a byte field of a register exactly the same way that
2331 mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg
2332 does not kill the entire register. */
2333 if (GET_CODE (reg) != SUBREG
2334 || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg))
2337 reg = SUBREG_REG (reg);
2340 if (GET_CODE (reg) != REG)
2343 /* Global registers are always live, so the code below does not apply
2346 regno = REGNO (reg);
2347 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
2351 /* If we only set part of the register, then this set does not
2356 /* Try killing this register. */
2357 if (regno < FIRST_PSEUDO_REGISTER)
2359 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2362 CLEAR_REGNO_REG_SET (bb_live_regs, regno + j);
2363 SET_REGNO_REG_SET (bb_dead_regs, regno + j);
2368 CLEAR_REGNO_REG_SET (bb_live_regs, regno);
2369 SET_REGNO_REG_SET (bb_dead_regs, regno);
2374 /* Make the register live again. */
2375 if (regno < FIRST_PSEUDO_REGISTER)
2377 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2380 SET_REGNO_REG_SET (bb_live_regs, regno + j);
2381 CLEAR_REGNO_REG_SET (bb_dead_regs, regno + j);
2386 SET_REGNO_REG_SET (bb_live_regs, regno);
2387 CLEAR_REGNO_REG_SET (bb_dead_regs, regno);
2393 /* Macros and functions for keeping the priority queue sorted, and
2394 dealing with queueing and dequeueing of instructions. */
2396 #define SCHED_SORT(READY, NEW_READY, OLD_READY) \
2397 do { if ((NEW_READY) - (OLD_READY) == 1) \
2398 swap_sort (READY, NEW_READY); \
2399 else if ((NEW_READY) - (OLD_READY) > 1) \
2400 qsort (READY, NEW_READY, sizeof (rtx), rank_for_schedule); } \
2403 /* Returns a positive value if y is preferred; returns a negative value if
2404 x is preferred. Should never return 0, since that will make the sort
2408 rank_for_schedule (x, y)
2414 int tmp_class, tmp2_class;
2417 /* Choose the instruction with the highest priority, if different. */
2418 if (value = INSN_PRIORITY (tmp) - INSN_PRIORITY (tmp2))
2421 if (last_scheduled_insn)
2423 /* Classify the instructions into three classes:
2424 1) Data dependent on last schedule insn.
2425 2) Anti/Output dependent on last scheduled insn.
2426 3) Independent of last scheduled insn, or has latency of one.
2427 Choose the insn from the highest numbered class if different. */
2428 link = find_insn_list (tmp, LOG_LINKS (last_scheduled_insn));
2429 if (link == 0 || insn_cost (tmp, link, last_scheduled_insn) == 1)
2431 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
2436 link = find_insn_list (tmp2, LOG_LINKS (last_scheduled_insn));
2437 if (link == 0 || insn_cost (tmp2, link, last_scheduled_insn) == 1)
2439 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
2444 if (value = tmp_class - tmp2_class)
2448 /* If insns are equally good, sort by INSN_LUID (original insn order),
2449 so that we make the sort stable. This minimizes instruction movement,
2450 thus minimizing sched's effect on debugging and cross-jumping. */
2451 return INSN_LUID (tmp) - INSN_LUID (tmp2);
2454 /* Resort the array A in which only element at index N may be out of order. */
2456 __inline static void
2464 while (i >= 0 && rank_for_schedule (a+i, &insn) >= 0)
2472 static int max_priority;
2474 /* Add INSN to the insn queue so that it fires at least N_CYCLES
2475 before the currently executing insn. */
2477 __inline static void
2478 queue_insn (insn, n_cycles)
2482 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
2483 NEXT_INSN (insn) = insn_queue[next_q];
2484 insn_queue[next_q] = insn;
2488 /* Return nonzero if PAT is the pattern of an insn which makes a
2492 birthing_insn_p (pat)
2497 if (reload_completed == 1)
2500 if (GET_CODE (pat) == SET
2501 && GET_CODE (SET_DEST (pat)) == REG)
2503 rtx dest = SET_DEST (pat);
2504 int i = REGNO (dest);
2506 /* It would be more accurate to use refers_to_regno_p or
2507 reg_mentioned_p to determine when the dest is not live before this
2510 if (REGNO_REG_SET_P (bb_live_regs, i))
2511 return (REG_N_SETS (i) == 1);
2515 if (GET_CODE (pat) == PARALLEL)
2517 for (j = 0; j < XVECLEN (pat, 0); j++)
2518 if (birthing_insn_p (XVECEXP (pat, 0, j)))
2524 /* PREV is an insn that is ready to execute. Adjust its priority if that
2525 will help shorten register lifetimes. */
2527 __inline static void
2528 adjust_priority (prev)
2531 /* Trying to shorten register lives after reload has completed
2532 is useless and wrong. It gives inaccurate schedules. */
2533 if (reload_completed == 0)
2538 /* ??? This code has no effect, because REG_DEAD notes are removed
2539 before we ever get here. */
2540 for (note = REG_NOTES (prev); note; note = XEXP (note, 1))
2541 if (REG_NOTE_KIND (note) == REG_DEAD)
2544 /* Defer scheduling insns which kill registers, since that
2545 shortens register lives. Prefer scheduling insns which
2546 make registers live for the same reason. */
2550 INSN_PRIORITY (prev) >>= 3;
2553 INSN_PRIORITY (prev) >>= 2;
2557 INSN_PRIORITY (prev) >>= 1;
2560 if (birthing_insn_p (PATTERN (prev)))
2562 int max = max_priority;
2564 if (max > INSN_PRIORITY (prev))
2565 INSN_PRIORITY (prev) = max;
2569 #ifdef ADJUST_PRIORITY
2570 ADJUST_PRIORITY (prev);
2575 /* INSN is the "currently executing insn". Launch each insn which was
2576 waiting on INSN (in the backwards dataflow sense). READY is a
2577 vector of insns which are ready to fire. N_READY is the number of
2578 elements in READY. CLOCK is the current virtual cycle. */
2581 schedule_insn (insn, ready, n_ready, clock)
2588 int new_ready = n_ready;
2590 if (MAX_BLOCKAGE > 1)
2591 schedule_unit (insn_unit (insn), insn, clock);
2593 if (LOG_LINKS (insn) == 0)
2596 /* This is used by the function adjust_priority above. */
2598 max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn));
2600 max_priority = INSN_PRIORITY (insn);
2602 for (link = LOG_LINKS (insn); link != 0; link = XEXP (link, 1))
2604 rtx prev = XEXP (link, 0);
2605 int cost = insn_cost (prev, link, insn);
2607 if ((INSN_REF_COUNT (prev) -= 1) != 0)
2609 /* We satisfied one requirement to fire PREV. Record the earliest
2610 time when PREV can fire. No need to do this if the cost is 1,
2611 because PREV can fire no sooner than the next cycle. */
2613 INSN_TICK (prev) = MAX (INSN_TICK (prev), clock + cost);
2617 /* We satisfied the last requirement to fire PREV. Ensure that all
2618 timing requirements are satisfied. */
2619 if (INSN_TICK (prev) - clock > cost)
2620 cost = INSN_TICK (prev) - clock;
2622 /* Adjust the priority of PREV and either put it on the ready
2623 list or queue it. */
2624 adjust_priority (prev);
2626 ready[new_ready++] = prev;
2628 queue_insn (prev, cost);
2635 /* Given N_READY insns in the ready list READY at time CLOCK, queue
2636 those that are blocked due to function unit hazards and rearrange
2637 the remaining ones to minimize subsequent function unit hazards. */
2640 schedule_select (ready, n_ready, clock, file)
2645 int pri = INSN_PRIORITY (ready[0]);
2646 int i, j, k, q, cost, best_cost, best_insn = 0, new_ready = n_ready;
2649 /* Work down the ready list in groups of instructions with the same
2650 priority value. Queue insns in the group that are blocked and
2651 select among those that remain for the one with the largest
2652 potential hazard. */
2653 for (i = 0; i < n_ready; i = j)
2656 for (j = i + 1; j < n_ready; j++)
2657 if ((pri = INSN_PRIORITY (ready[j])) != opri)
2660 /* Queue insns in the group that are blocked. */
2661 for (k = i, q = 0; k < j; k++)
2664 if ((cost = actual_hazard (insn_unit (insn), insn, clock, 0)) != 0)
2668 queue_insn (insn, cost);
2670 fprintf (file, "\n;; blocking insn %d for %d cycles",
2671 INSN_UID (insn), cost);
2676 /* Check the next group if all insns were queued. */
2680 /* If more than one remains, select the first one with the largest
2681 potential hazard. */
2682 else if (j - i - q > 1)
2685 for (k = i; k < j; k++)
2687 if ((insn = ready[k]) == 0)
2689 if ((cost = potential_hazard (insn_unit (insn), insn, 0))
2697 /* We have found a suitable insn to schedule. */
2701 /* Move the best insn to be front of the ready list. */
2706 fprintf (file, ", now");
2707 for (i = 0; i < n_ready; i++)
2709 fprintf (file, " %d", INSN_UID (ready[i]));
2710 fprintf (file, "\n;; insn %d has a greater potential hazard",
2711 INSN_UID (ready[best_insn]));
2713 for (i = best_insn; i > 0; i--)
2716 ready[i-1] = ready[i];
2721 /* Compact the ready list. */
2722 if (new_ready < n_ready)
2723 for (i = j = 0; i < n_ready; i++)
2725 ready[j++] = ready[i];
2730 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
2734 create_reg_dead_note (reg, insn)
2739 /* The number of registers killed after scheduling must be the same as the
2740 number of registers killed before scheduling. The number of REG_DEAD
2741 notes may not be conserved, i.e. two SImode hard register REG_DEAD notes
2742 might become one DImode hard register REG_DEAD note, but the number of
2743 registers killed will be conserved.
2745 We carefully remove REG_DEAD notes from the dead_notes list, so that
2746 there will be none left at the end. If we run out early, then there
2747 is a bug somewhere in flow, combine and/or sched. */
2749 if (dead_notes == 0)
2754 link = rtx_alloc (EXPR_LIST);
2755 PUT_REG_NOTE_KIND (link, REG_DEAD);
2760 /* Number of regs killed by REG. */
2761 int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1
2762 : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)));
2763 /* Number of regs killed by REG_DEAD notes taken off the list. */
2767 reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
2768 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
2769 GET_MODE (XEXP (link, 0))));
2770 while (reg_note_regs < regs_killed)
2772 link = XEXP (link, 1);
2773 reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
2774 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
2775 GET_MODE (XEXP (link, 0))));
2777 dead_notes = XEXP (link, 1);
2779 /* If we took too many regs kills off, put the extra ones back. */
2780 while (reg_note_regs > regs_killed)
2782 rtx temp_reg, temp_link;
2784 temp_reg = gen_rtx (REG, word_mode, 0);
2785 temp_link = rtx_alloc (EXPR_LIST);
2786 PUT_REG_NOTE_KIND (temp_link, REG_DEAD);
2787 XEXP (temp_link, 0) = temp_reg;
2788 XEXP (temp_link, 1) = dead_notes;
2789 dead_notes = temp_link;
2794 XEXP (link, 0) = reg;
2795 XEXP (link, 1) = REG_NOTES (insn);
2796 REG_NOTES (insn) = link;
2799 /* Subroutine on attach_deaths_insn--handles the recursive search
2800 through INSN. If SET_P is true, then x is being modified by the insn. */
2803 attach_deaths (x, insn, set_p)
2810 register enum rtx_code code;
2816 code = GET_CODE (x);
2828 /* Get rid of the easy cases first. */
2833 /* If the register dies in this insn, queue that note, and mark
2834 this register as needing to die. */
2835 /* This code is very similar to mark_used_1 (if set_p is false)
2836 and mark_set_1 (if set_p is true) in flow.c. */
2846 all_needed = some_needed = REGNO_REG_SET_P (old_live_regs, regno);
2847 if (regno < FIRST_PSEUDO_REGISTER)
2851 n = HARD_REGNO_NREGS (regno, GET_MODE (x));
2854 int needed = (REGNO_REG_SET_P (old_live_regs, regno + n));
2855 some_needed |= needed;
2856 all_needed &= needed;
2860 /* If it wasn't live before we started, then add a REG_DEAD note.
2861 We must check the previous lifetime info not the current info,
2862 because we may have to execute this code several times, e.g.
2863 once for a clobber (which doesn't add a note) and later
2864 for a use (which does add a note).
2866 Always make the register live. We must do this even if it was
2867 live before, because this may be an insn which sets and uses
2868 the same register, in which case the register has already been
2869 killed, so we must make it live again.
2871 Global registers are always live, and should never have a REG_DEAD
2872 note added for them, so none of the code below applies to them. */
2874 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
2876 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2877 STACK_POINTER_REGNUM, since these are always considered to be
2878 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2879 if (regno != FRAME_POINTER_REGNUM
2880 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2881 && ! (regno == HARD_FRAME_POINTER_REGNUM)
2883 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2884 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
2886 && regno != STACK_POINTER_REGNUM)
2888 /* ??? It is perhaps a dead_or_set_p bug that it does
2889 not check for REG_UNUSED notes itself. This is necessary
2890 for the case where the SET_DEST is a subreg of regno, as
2891 dead_or_set_p handles subregs specially. */
2892 if (! all_needed && ! dead_or_set_p (insn, x)
2893 && ! find_reg_note (insn, REG_UNUSED, x))
2895 /* Check for the case where the register dying partially
2896 overlaps the register set by this insn. */
2897 if (regno < FIRST_PSEUDO_REGISTER
2898 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
2900 int n = HARD_REGNO_NREGS (regno, GET_MODE (x));
2902 some_needed |= dead_or_set_regno_p (insn, regno + n);
2905 /* If none of the words in X is needed, make a REG_DEAD
2906 note. Otherwise, we must make partial REG_DEAD
2909 create_reg_dead_note (x, insn);
2914 /* Don't make a REG_DEAD note for a part of a
2915 register that is set in the insn. */
2916 for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1;
2918 if (REGNO_REG_SET_P (old_live_regs, regno + i)
2919 && ! dead_or_set_regno_p (insn, regno + i))
2920 create_reg_dead_note (gen_rtx (REG,
2921 reg_raw_mode[regno + i],
2928 if (regno < FIRST_PSEUDO_REGISTER)
2930 int j = HARD_REGNO_NREGS (regno, GET_MODE (x));
2933 CLEAR_REGNO_REG_SET (bb_dead_regs, regno + j);
2934 SET_REGNO_REG_SET (bb_live_regs, regno + j);
2939 CLEAR_REGNO_REG_SET (bb_dead_regs, regno);
2940 SET_REGNO_REG_SET (bb_live_regs, regno);
2947 /* Handle tail-recursive case. */
2948 attach_deaths (XEXP (x, 0), insn, 0);
2952 case STRICT_LOW_PART:
2953 /* These two cases preserve the value of SET_P, so handle them
2955 attach_deaths (XEXP (x, 0), insn, set_p);
2960 /* This case preserves the value of SET_P for the first operand, but
2961 clears it for the other two. */
2962 attach_deaths (XEXP (x, 0), insn, set_p);
2963 attach_deaths (XEXP (x, 1), insn, 0);
2964 attach_deaths (XEXP (x, 2), insn, 0);
2968 /* Other cases: walk the insn. */
2969 fmt = GET_RTX_FORMAT (code);
2970 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2973 attach_deaths (XEXP (x, i), insn, 0);
2974 else if (fmt[i] == 'E')
2975 for (j = 0; j < XVECLEN (x, i); j++)
2976 attach_deaths (XVECEXP (x, i, j), insn, 0);
2981 /* After INSN has executed, add register death notes for each register
2982 that is dead after INSN. */
2985 attach_deaths_insn (insn)
2988 rtx x = PATTERN (insn);
2989 register RTX_CODE code = GET_CODE (x);
2994 attach_deaths (SET_SRC (x), insn, 0);
2996 /* A register might die here even if it is the destination, e.g.
2997 it is the target of a volatile read and is otherwise unused.
2998 Hence we must always call attach_deaths for the SET_DEST. */
2999 attach_deaths (SET_DEST (x), insn, 1);
3001 else if (code == PARALLEL)
3004 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
3006 code = GET_CODE (XVECEXP (x, 0, i));
3009 attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0);
3011 attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1);
3013 /* Flow does not add REG_DEAD notes to registers that die in
3014 clobbers, so we can't either. */
3015 else if (code != CLOBBER)
3016 attach_deaths (XVECEXP (x, 0, i), insn, 0);
3019 /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a
3020 MEM being clobbered, just like flow. */
3021 else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == MEM)
3022 attach_deaths (XEXP (XEXP (x, 0), 0), insn, 0);
3023 /* Otherwise don't add a death note to things being clobbered. */
3024 else if (code != CLOBBER)
3025 attach_deaths (x, insn, 0);
3027 /* Make death notes for things used in the called function. */
3028 if (GET_CODE (insn) == CALL_INSN)
3029 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
3030 attach_deaths (XEXP (XEXP (link, 0), 0), insn,
3031 GET_CODE (XEXP (link, 0)) == CLOBBER);
3034 /* Delete notes beginning with INSN and maybe put them in the chain
3035 of notes ended by NOTE_LIST.
3036 Returns the insn following the notes. */
3039 unlink_notes (insn, tail)
3042 rtx prev = PREV_INSN (insn);
3044 while (insn != tail && GET_CODE (insn) == NOTE)
3046 rtx next = NEXT_INSN (insn);
3047 /* Delete the note from its current position. */
3049 NEXT_INSN (prev) = next;
3051 PREV_INSN (next) = prev;
3053 if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
3054 /* Record line-number notes so they can be reused. */
3055 LINE_NOTE (insn) = insn;
3057 /* Don't save away NOTE_INSN_SETJMPs, because they must remain
3058 immediately after the call they follow. We use a fake
3059 (REG_DEAD (const_int -1)) note to remember them.
3060 Likewise with NOTE_INSN_{LOOP,EHREGION}_{BEG, END}. */
3061 else if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP
3062 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG
3063 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END
3064 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG
3065 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END)
3067 /* Insert the note at the end of the notes list. */
3068 PREV_INSN (insn) = note_list;
3070 NEXT_INSN (note_list) = insn;
3079 /* Constructor for `sometimes' data structure. */
3082 new_sometimes_live (regs_sometimes_live, regno, sometimes_max)
3083 struct sometimes *regs_sometimes_live;
3087 register struct sometimes *p;
3089 /* There should never be a register greater than max_regno here. If there
3090 is, it means that a define_split has created a new pseudo reg. This
3091 is not allowed, since there will not be flow info available for any
3092 new register, so catch the error here. */
3093 if (regno >= max_regno)
3096 p = ®s_sometimes_live[sometimes_max];
3099 p->calls_crossed = 0;
3101 return sometimes_max;
3104 /* Count lengths of all regs we are currently tracking,
3105 and find new registers no longer live. */
3108 finish_sometimes_live (regs_sometimes_live, sometimes_max)
3109 struct sometimes *regs_sometimes_live;
3114 for (i = 0; i < sometimes_max; i++)
3116 register struct sometimes *p = ®s_sometimes_live[i];
3117 int regno = p->regno;
3119 sched_reg_live_length[regno] += p->live_length;
3120 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
3124 /* Search INSN for fake REG_DEAD note pairs for NOTE_INSN_SETJMP,
3125 NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into
3126 NOTEs. The REG_DEAD note following first one is contains the saved
3127 value for NOTE_BLOCK_NUMBER which is useful for
3128 NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction
3129 output by the instruction scheduler. Return the new value of LAST. */
3132 reemit_notes (insn, last)
3138 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
3140 if (REG_NOTE_KIND (note) == REG_DEAD
3141 && GET_CODE (XEXP (note, 0)) == CONST_INT)
3143 if (INTVAL (XEXP (note, 0)) == NOTE_INSN_SETJMP)
3145 CONST_CALL_P (emit_note_after (INTVAL (XEXP (note, 0)), insn))
3146 = CONST_CALL_P (note);
3147 remove_note (insn, note);
3148 note = XEXP (note, 1);
3152 last = emit_note_before (INTVAL (XEXP (note, 0)), last);
3153 remove_note (insn, note);
3154 note = XEXP (note, 1);
3155 NOTE_BLOCK_NUMBER (last) = INTVAL (XEXP (note, 0));
3157 remove_note (insn, note);
3163 /* Use modified list scheduling to rearrange insns in basic block
3164 B. FILE, if nonzero, is where we dump interesting output about
3168 schedule_block (b, file)
3174 int i, j, n_ready = 0, new_ready, n_insns;
3175 int sched_n_insns = 0;
3177 #define NEED_NOTHING 0
3182 /* HEAD and TAIL delimit the region being scheduled. */
3183 rtx head = basic_block_head[b];
3184 rtx tail = basic_block_end[b];
3185 /* PREV_HEAD and NEXT_TAIL are the boundaries of the insns
3186 being scheduled. When the insns have been ordered,
3187 these insns delimit where the new insns are to be
3188 spliced back into the insn chain. */
3192 /* Keep life information accurate. */
3193 register struct sometimes *regs_sometimes_live;
3197 fprintf (file, ";;\t -- basic block number %d from %d to %d --\n",
3198 b, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b]));
3201 reg_last_uses = (rtx *) alloca (i * sizeof (rtx));
3202 bzero ((char *) reg_last_uses, i * sizeof (rtx));
3203 reg_last_sets = (rtx *) alloca (i * sizeof (rtx));
3204 bzero ((char *) reg_last_sets, i * sizeof (rtx));
3205 reg_pending_sets = ALLOCA_REG_SET ();
3206 CLEAR_REG_SET (reg_pending_sets);
3207 reg_pending_sets_all = 0;
3210 /* Remove certain insns at the beginning from scheduling,
3211 by advancing HEAD. */
3213 /* At the start of a function, before reload has run, don't delay getting
3214 parameters from hard registers into pseudo registers. */
3215 if (reload_completed == 0 && b == 0)
3218 && GET_CODE (head) == NOTE
3219 && NOTE_LINE_NUMBER (head) != NOTE_INSN_FUNCTION_BEG)
3220 head = NEXT_INSN (head);
3222 && GET_CODE (head) == INSN
3223 && GET_CODE (PATTERN (head)) == SET)
3225 rtx src = SET_SRC (PATTERN (head));
3226 while (GET_CODE (src) == SUBREG
3227 || GET_CODE (src) == SIGN_EXTEND
3228 || GET_CODE (src) == ZERO_EXTEND
3229 || GET_CODE (src) == SIGN_EXTRACT
3230 || GET_CODE (src) == ZERO_EXTRACT)
3231 src = XEXP (src, 0);
3232 if (GET_CODE (src) != REG
3233 || REGNO (src) >= FIRST_PSEUDO_REGISTER)
3235 /* Keep this insn from ever being scheduled. */
3236 INSN_REF_COUNT (head) = 1;
3237 head = NEXT_INSN (head);
3241 /* Don't include any notes or labels at the beginning of the
3242 basic block, or notes at the ends of basic blocks. */
3243 while (head != tail)
3245 if (GET_CODE (head) == NOTE)
3246 head = NEXT_INSN (head);
3247 else if (GET_CODE (tail) == NOTE)
3248 tail = PREV_INSN (tail);
3249 else if (GET_CODE (head) == CODE_LABEL)
3250 head = NEXT_INSN (head);
3253 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
3254 to schedule this block. */
3256 && (GET_CODE (head) == NOTE || GET_CODE (head) == CODE_LABEL))
3260 /* This short-cut doesn't work. It does not count call insns crossed by
3261 registers in reg_sometimes_live. It does not mark these registers as
3262 dead if they die in this block. It does not mark these registers live
3263 (or create new reg_sometimes_live entries if necessary) if they are born
3266 The easy solution is to just always schedule a block. This block only
3267 has one insn, so this won't slow down this pass by much. */
3273 /* Now HEAD through TAIL are the insns actually to be rearranged;
3274 Let PREV_HEAD and NEXT_TAIL enclose them. */
3275 prev_head = PREV_INSN (head);
3276 next_tail = NEXT_INSN (tail);
3278 /* Initialize basic block data structures. */
3280 pending_read_insns = 0;
3281 pending_read_mems = 0;
3282 pending_write_insns = 0;
3283 pending_write_mems = 0;
3284 pending_lists_length = 0;
3285 last_pending_memory_flush = 0;
3286 last_function_call = 0;
3287 last_scheduled_insn = 0;
3289 LOG_LINKS (sched_before_next_call) = 0;
3291 n_insns = sched_analyze (head, tail);
3294 free_pending_lists ();
3298 /* Allocate vector to hold insns to be rearranged (except those
3299 insns which are controlled by an insn with SCHED_GROUP_P set).
3300 All these insns are included between ORIG_HEAD and ORIG_TAIL,
3301 as those variables ultimately are set up. */
3302 ready = (rtx *) alloca ((n_insns+1) * sizeof (rtx));
3304 /* TAIL is now the last of the insns to be rearranged.
3305 Put those insns into the READY vector. */
3308 /* For all branches, calls, uses, and cc0 setters, force them to remain
3309 in order at the end of the block by adding dependencies and giving
3310 the last a high priority. There may be notes present, and prev_head
3313 Branches must obviously remain at the end. Calls should remain at the
3314 end since moving them results in worse register allocation. Uses remain
3315 at the end to ensure proper register allocation. cc0 setters remaim
3316 at the end because they can't be moved away from their cc0 user. */
3318 while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN
3319 || (GET_CODE (insn) == INSN
3320 && (GET_CODE (PATTERN (insn)) == USE
3322 || sets_cc0_p (PATTERN (insn))
3325 || GET_CODE (insn) == NOTE)
3327 if (GET_CODE (insn) != NOTE)
3332 ready[n_ready++] = insn;
3333 INSN_PRIORITY (insn) = TAIL_PRIORITY - i;
3334 INSN_REF_COUNT (insn) = 0;
3336 else if (! find_insn_list (insn, LOG_LINKS (last)))
3338 add_dependence (last, insn, REG_DEP_ANTI);
3339 INSN_REF_COUNT (insn)++;
3343 /* Skip over insns that are part of a group. */
3344 while (SCHED_GROUP_P (insn))
3346 insn = prev_nonnote_insn (insn);
3351 insn = PREV_INSN (insn);
3352 /* Don't overrun the bounds of the basic block. */
3353 if (insn == prev_head)
3357 /* Assign priorities to instructions. Also check whether they
3358 are in priority order already. If so then I will be nonnegative.
3359 We use this shortcut only before reloading. */
3361 i = reload_completed ? DONE_PRIORITY : MAX_PRIORITY;
3364 for (; insn != prev_head; insn = PREV_INSN (insn))
3366 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3369 if (INSN_REF_COUNT (insn) == 0)
3372 ready[n_ready++] = insn;
3375 /* Make this dependent on the last of the instructions
3376 that must remain in order at the end of the block. */
3377 add_dependence (last, insn, REG_DEP_ANTI);
3378 INSN_REF_COUNT (insn) = 1;
3381 if (SCHED_GROUP_P (insn))
3383 while (SCHED_GROUP_P (insn))
3385 insn = prev_nonnote_insn (insn);
3393 if (INSN_PRIORITY (insn) < i)
3394 i = INSN_PRIORITY (insn);
3395 else if (INSN_PRIORITY (insn) > i)
3402 /* This short-cut doesn't work. It does not count call insns crossed by
3403 registers in reg_sometimes_live. It does not mark these registers as
3404 dead if they die in this block. It does not mark these registers live
3405 (or create new reg_sometimes_live entries if necessary) if they are born
3408 The easy solution is to just always schedule a block. These blocks tend
3409 to be very short, so this doesn't slow down this pass by much. */
3411 /* If existing order is good, don't bother to reorder. */
3412 if (i != DONE_PRIORITY)
3415 fprintf (file, ";; already scheduled\n");
3417 if (reload_completed == 0)
3419 for (i = 0; i < sometimes_max; i++)
3420 regs_sometimes_live[i].live_length += n_insns;
3422 finish_sometimes_live (regs_sometimes_live, sometimes_max);
3424 free_pending_lists ();
3429 /* Scan all the insns to be scheduled, removing NOTE insns
3430 and register death notes.
3431 Line number NOTE insns end up in NOTE_LIST.
3432 Register death notes end up in DEAD_NOTES.
3434 Recreate the register life information for the end of this basic
3437 if (reload_completed == 0)
3439 bcopy ((char *) basic_block_live_at_start[b], (char *) bb_live_regs,
3441 bzero ((char *) bb_dead_regs, regset_bytes);
3445 /* This is the first block in the function. There may be insns
3446 before head that we can't schedule. We still need to examine
3447 them though for accurate register lifetime analysis. */
3449 /* We don't want to remove any REG_DEAD notes as the code below
3452 for (insn = basic_block_head[b]; insn != head;
3453 insn = NEXT_INSN (insn))
3454 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3456 /* See if the register gets born here. */
3457 /* We must check for registers being born before we check for
3458 registers dying. It is possible for a register to be born
3459 and die in the same insn, e.g. reading from a volatile
3460 memory location into an otherwise unused register. Such
3461 a register must be marked as dead after this insn. */
3462 if (GET_CODE (PATTERN (insn)) == SET
3463 || GET_CODE (PATTERN (insn)) == CLOBBER)
3464 sched_note_set (b, PATTERN (insn), 0);
3465 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3468 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3469 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3470 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3471 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3473 /* ??? This code is obsolete and should be deleted. It
3474 is harmless though, so we will leave it in for now. */
3475 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3476 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
3477 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3480 /* Each call clobbers (makes live) all call-clobbered regs
3481 that are not global or fixed. Note that the function-value
3482 reg is a call_clobbered reg. */
3484 if (GET_CODE (insn) == CALL_INSN)
3487 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
3488 if (call_used_regs[j] && ! global_regs[j]
3491 SET_REGNO_REG_SET (bb_live_regs, j);
3492 CLEAR_REGNO_REG_SET (bb_dead_regs, j);
3496 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
3498 if ((REG_NOTE_KIND (link) == REG_DEAD
3499 || REG_NOTE_KIND (link) == REG_UNUSED)
3500 /* Verify that the REG_NOTE has a valid value. */
3501 && GET_CODE (XEXP (link, 0)) == REG)
3503 register int regno = REGNO (XEXP (link, 0));
3505 if (regno < FIRST_PSEUDO_REGISTER)
3507 int j = HARD_REGNO_NREGS (regno,
3508 GET_MODE (XEXP (link, 0)));
3511 CLEAR_REGNO_REG_SET (bb_live_regs, regno + j);
3512 SET_REGNO_REG_SET (bb_dead_regs, regno + j);
3517 CLEAR_REGNO_REG_SET (bb_live_regs, regno);
3518 SET_REGNO_REG_SET (bb_dead_regs, regno);
3526 /* If debugging information is being produced, keep track of the line
3527 number notes for each insn. */
3528 if (write_symbols != NO_DEBUG)
3530 /* We must use the true line number for the first insn in the block
3531 that was computed and saved at the start of this pass. We can't
3532 use the current line number, because scheduling of the previous
3533 block may have changed the current line number. */
3534 rtx line = line_note_head[b];
3536 for (insn = basic_block_head[b];
3538 insn = NEXT_INSN (insn))
3539 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
3542 LINE_NOTE (insn) = line;
3545 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
3547 rtx prev, next, link;
3549 /* Farm out notes. This is needed to keep the debugger from
3550 getting completely deranged. */
3551 if (GET_CODE (insn) == NOTE)
3554 insn = unlink_notes (insn, next_tail);
3559 if (insn == next_tail)
3563 if (reload_completed == 0
3564 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3566 /* See if the register gets born here. */
3567 /* We must check for registers being born before we check for
3568 registers dying. It is possible for a register to be born and
3569 die in the same insn, e.g. reading from a volatile memory
3570 location into an otherwise unused register. Such a register
3571 must be marked as dead after this insn. */
3572 if (GET_CODE (PATTERN (insn)) == SET
3573 || GET_CODE (PATTERN (insn)) == CLOBBER)
3574 sched_note_set (b, PATTERN (insn), 0);
3575 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3578 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3579 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3580 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3581 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3583 /* ??? This code is obsolete and should be deleted. It
3584 is harmless though, so we will leave it in for now. */
3585 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3586 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
3587 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3590 /* Each call clobbers (makes live) all call-clobbered regs that are
3591 not global or fixed. Note that the function-value reg is a
3592 call_clobbered reg. */
3594 if (GET_CODE (insn) == CALL_INSN)
3597 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
3598 if (call_used_regs[j] && ! global_regs[j]
3601 SET_REGNO_REG_SET (bb_live_regs, j);
3602 CLEAR_REGNO_REG_SET (bb_dead_regs, j);
3606 /* Need to know what registers this insn kills. */
3607 for (prev = 0, link = REG_NOTES (insn); link; link = next)
3609 next = XEXP (link, 1);
3610 if ((REG_NOTE_KIND (link) == REG_DEAD
3611 || REG_NOTE_KIND (link) == REG_UNUSED)
3612 /* Verify that the REG_NOTE has a valid value. */
3613 && GET_CODE (XEXP (link, 0)) == REG)
3615 register int regno = REGNO (XEXP (link, 0));
3617 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
3619 if (REG_NOTE_KIND (link) == REG_DEAD)
3622 XEXP (prev, 1) = next;
3624 REG_NOTES (insn) = next;
3625 XEXP (link, 1) = dead_notes;
3631 if (regno < FIRST_PSEUDO_REGISTER)
3633 int j = HARD_REGNO_NREGS (regno,
3634 GET_MODE (XEXP (link, 0)));
3637 CLEAR_REGNO_REG_SET (bb_live_regs, regno + j);
3638 SET_REGNO_REG_SET (bb_dead_regs, regno + j);
3643 CLEAR_REGNO_REG_SET (bb_live_regs, regno);
3644 SET_REGNO_REG_SET (bb_dead_regs, regno);
3653 if (reload_completed == 0)
3655 /* Keep track of register lives. */
3656 old_live_regs = ALLOCA_REG_SET ();
3658 = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes));
3661 /* Start with registers live at end. */
3662 COPY_REG_SET (old_live_regs, bb_live_regs);
3663 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, 0, j,
3666 = new_sometimes_live (regs_sometimes_live,
3671 SCHED_SORT (ready, n_ready, 1);
3675 fprintf (file, ";; ready list initially:\n;; ");
3676 for (i = 0; i < n_ready; i++)
3677 fprintf (file, "%d ", INSN_UID (ready[i]));
3678 fprintf (file, "\n\n");
3680 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
3681 if (INSN_PRIORITY (insn) > 0)
3682 fprintf (file, ";; insn[%4d]: priority = %4d, ref_count = %4d\n",
3683 INSN_UID (insn), INSN_PRIORITY (insn),
3684 INSN_REF_COUNT (insn));
3687 /* Now HEAD and TAIL are going to become disconnected
3688 entirely from the insn chain. */
3691 /* Q_SIZE will always be zero here. */
3692 q_ptr = 0; clock = 0;
3693 bzero ((char *) insn_queue, sizeof (insn_queue));
3695 /* Now, perform list scheduling. */
3697 /* Where we start inserting insns is after TAIL. */
3700 new_needs = (NEXT_INSN (prev_head) == basic_block_head[b]
3701 ? NEED_HEAD : NEED_NOTHING);
3702 if (PREV_INSN (next_tail) == basic_block_end[b])
3703 new_needs |= NEED_TAIL;
3705 new_ready = n_ready;
3706 while (sched_n_insns < n_insns)
3708 q_ptr = NEXT_Q (q_ptr); clock++;
3710 /* Add all pending insns that can be scheduled without stalls to the
3712 for (insn = insn_queue[q_ptr]; insn; insn = NEXT_INSN (insn))
3715 fprintf (file, ";; launching %d before %d with no stalls at T-%d\n",
3716 INSN_UID (insn), INSN_UID (last), clock);
3717 ready[new_ready++] = insn;
3720 insn_queue[q_ptr] = 0;
3722 /* If there are no ready insns, stall until one is ready and add all
3723 of the pending insns at that point to the ready list. */
3726 register int stalls;
3728 for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++)
3729 if (insn = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])
3731 for (; insn; insn = NEXT_INSN (insn))
3734 fprintf (file, ";; launching %d before %d with %d stalls at T-%d\n",
3735 INSN_UID (insn), INSN_UID (last), stalls, clock);
3736 ready[new_ready++] = insn;
3739 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
3743 q_ptr = NEXT_Q_AFTER (q_ptr, stalls); clock += stalls;
3746 /* There should be some instructions waiting to fire. */
3752 fprintf (file, ";; ready list at T-%d:", clock);
3753 for (i = 0; i < new_ready; i++)
3754 fprintf (file, " %d (%x)",
3755 INSN_UID (ready[i]), INSN_PRIORITY (ready[i]));
3758 /* Sort the ready list and choose the best insn to schedule. Select
3759 which insn should issue in this cycle and queue those that are
3760 blocked by function unit hazards.
3762 N_READY holds the number of items that were scheduled the last time,
3763 minus the one instruction scheduled on the last loop iteration; it
3764 is not modified for any other reason in this loop. */
3766 SCHED_SORT (ready, new_ready, n_ready);
3767 if (MAX_BLOCKAGE > 1)
3769 new_ready = schedule_select (ready, new_ready, clock, file);
3773 fprintf (file, "\n");
3774 /* We must set n_ready here, to ensure that sorting always
3775 occurs when we come back to the SCHED_SORT line above. */
3780 n_ready = new_ready;
3781 last_scheduled_insn = insn = ready[0];
3783 /* The first insn scheduled becomes the new tail. */
3789 fprintf (file, ", now");
3790 for (i = 0; i < n_ready; i++)
3791 fprintf (file, " %d", INSN_UID (ready[i]));
3792 fprintf (file, "\n");
3795 if (DONE_PRIORITY_P (insn))
3798 if (reload_completed == 0)
3800 /* Process this insn, and each insn linked to this one which must
3801 be immediately output after this insn. */
3804 /* First we kill registers set by this insn, and then we
3805 make registers used by this insn live. This is the opposite
3806 order used above because we are traversing the instructions
3809 /* Strictly speaking, we should scan REG_UNUSED notes and make
3810 every register mentioned there live, however, we will just
3811 kill them again immediately below, so there doesn't seem to
3812 be any reason why we bother to do this. */
3814 /* See if this is the last notice we must take of a register. */
3815 if (GET_CODE (PATTERN (insn)) == SET
3816 || GET_CODE (PATTERN (insn)) == CLOBBER)
3817 sched_note_set (b, PATTERN (insn), 1);
3818 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3821 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3822 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3823 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3824 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 1);
3827 /* This code keeps life analysis information up to date. */
3828 if (GET_CODE (insn) == CALL_INSN)
3830 register struct sometimes *p;
3832 /* A call kills all call used registers that are not
3833 global or fixed, except for those mentioned in the call
3834 pattern which will be made live again later. */
3835 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3836 if (call_used_regs[i] && ! global_regs[i]
3839 CLEAR_REGNO_REG_SET (bb_live_regs, i);
3840 SET_REGNO_REG_SET (bb_dead_regs, i);
3843 /* Regs live at the time of a call instruction must not
3844 go in a register clobbered by calls. Record this for
3845 all regs now live. Note that insns which are born or
3846 die in a call do not cross a call, so this must be done
3847 after the killings (above) and before the births
3849 p = regs_sometimes_live;
3850 for (i = 0; i < sometimes_max; i++, p++)
3851 if (REGNO_REG_SET_P (bb_live_regs, p->regno))
3852 p->calls_crossed += 1;
3855 /* Make every register used live, and add REG_DEAD notes for
3856 registers which were not live before we started. */
3857 attach_deaths_insn (insn);
3859 /* Find registers now made live by that instruction. */
3860 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, 0, i,
3863 = new_sometimes_live (regs_sometimes_live,
3867 /* Count lengths of all regs we are worrying about now,
3868 and handle registers no longer live. */
3870 for (i = 0; i < sometimes_max; i++)
3872 register struct sometimes *p = ®s_sometimes_live[i];
3873 int regno = p->regno;
3875 p->live_length += 1;
3877 if (REGNO_REG_SET_P (bb_live_regs, p->regno))
3879 /* This is the end of one of this register's lifetime
3880 segments. Save the lifetime info collected so far,
3881 and clear its bit in the old_live_regs entry. */
3882 sched_reg_live_length[regno] += p->live_length;
3883 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
3884 CLEAR_REGNO_REG_SET (old_live_regs, p->regno);
3886 /* Delete the reg_sometimes_live entry for this reg by
3887 copying the last entry over top of it. */
3888 *p = regs_sometimes_live[--sometimes_max];
3889 /* ...and decrement i so that this newly copied entry
3890 will be processed. */
3896 insn = PREV_INSN (insn);
3898 while (SCHED_GROUP_P (link));
3900 /* Set INSN back to the insn we are scheduling now. */
3904 /* Schedule INSN. Remove it from the ready list. */
3909 NEXT_INSN (insn) = last;
3910 PREV_INSN (last) = insn;
3912 /* Everything that precedes INSN now either becomes "ready", if
3913 it can execute immediately before INSN, or "pending", if
3914 there must be a delay. Give INSN high enough priority that
3915 at least one (maybe more) reg-killing insns can be launched
3916 ahead of all others. Mark INSN as scheduled by changing its
3918 INSN_PRIORITY (insn) = LAUNCH_PRIORITY;
3919 new_ready = schedule_insn (insn, ready, n_ready, clock);
3920 INSN_PRIORITY (insn) = DONE_PRIORITY;
3922 /* Schedule all prior insns that must not be moved. */
3923 if (SCHED_GROUP_P (insn))
3925 /* Disable these insns from being launched, in case one of the
3926 insns in the group has a dependency on an earlier one. */
3928 while (SCHED_GROUP_P (link))
3930 /* Disable these insns from being launched by anybody. */
3931 link = PREV_INSN (link);
3932 INSN_REF_COUNT (link) = 0;
3935 /* Now handle each group insn like the main insn was handled
3938 while (SCHED_GROUP_P (link))
3940 link = PREV_INSN (link);
3944 /* ??? Why don't we set LAUNCH_PRIORITY here? */
3945 new_ready = schedule_insn (link, ready, new_ready, clock);
3946 INSN_PRIORITY (link) = DONE_PRIORITY;
3950 /* Put back NOTE_INSN_SETJMP,
3951 NOTE_INSN_{LOOP,EHREGION}_{BEGIN,END} notes. */
3953 /* To prime the loop. We need to handle INSN and all the insns in the
3955 last = NEXT_INSN (insn);
3958 insn = PREV_INSN (last);
3960 /* Maintain a valid chain so emit_note_before works.
3961 This is necessary because PREV_INSN (insn) isn't valid
3962 (if ! SCHED_GROUP_P) and if it points to an insn already
3963 scheduled, a circularity will result. */
3964 if (! SCHED_GROUP_P (insn))
3966 NEXT_INSN (prev_head) = insn;
3967 PREV_INSN (insn) = prev_head;
3970 last = reemit_notes (insn, insn);
3972 while (SCHED_GROUP_P (insn));
3977 if (reload_completed == 0)
3978 finish_sometimes_live (regs_sometimes_live, sometimes_max);
3980 /* HEAD is now the first insn in the chain of insns that
3981 been scheduled by the loop above.
3982 TAIL is the last of those insns. */
3985 /* NOTE_LIST is the end of a chain of notes previously found
3986 among the insns. Insert them at the beginning of the insns. */
3989 rtx note_head = note_list;
3990 while (PREV_INSN (note_head))
3991 note_head = PREV_INSN (note_head);
3993 PREV_INSN (head) = note_list;
3994 NEXT_INSN (note_list) = head;
3998 /* There should be no REG_DEAD notes leftover at the end.
3999 In practice, this can occur as the result of bugs in flow, combine.c,
4000 and/or sched.c. The values of the REG_DEAD notes remaining are
4001 meaningless, because dead_notes is just used as a free list. */
4003 if (dead_notes != 0)
4007 if (new_needs & NEED_HEAD)
4008 basic_block_head[b] = head;
4009 PREV_INSN (head) = prev_head;
4010 NEXT_INSN (prev_head) = head;
4012 if (new_needs & NEED_TAIL)
4013 basic_block_end[b] = tail;
4014 NEXT_INSN (tail) = next_tail;
4015 PREV_INSN (next_tail) = tail;
4017 /* Restore the line-number notes of each insn. */
4018 if (write_symbols != NO_DEBUG)
4020 rtx line, note, prev, new;
4023 head = basic_block_head[b];
4024 next_tail = NEXT_INSN (basic_block_end[b]);
4026 /* Determine the current line-number. We want to know the current
4027 line number of the first insn of the block here, in case it is
4028 different from the true line number that was saved earlier. If
4029 different, then we need a line number note before the first insn
4030 of this block. If it happens to be the same, then we don't want to
4031 emit another line number note here. */
4032 for (line = head; line; line = PREV_INSN (line))
4033 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4036 /* Walk the insns keeping track of the current line-number and inserting
4037 the line-number notes as needed. */
4038 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4039 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4041 /* This used to emit line number notes before every non-deleted note.
4042 However, this confuses a debugger, because line notes not separated
4043 by real instructions all end up at the same address. I can find no
4044 use for line number notes before other notes, so none are emitted. */
4045 else if (GET_CODE (insn) != NOTE
4046 && (note = LINE_NOTE (insn)) != 0
4049 || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
4050 || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
4053 prev = PREV_INSN (insn);
4054 if (LINE_NOTE (note))
4056 /* Re-use the original line-number note. */
4057 LINE_NOTE (note) = 0;
4058 PREV_INSN (note) = prev;
4059 NEXT_INSN (prev) = note;
4060 PREV_INSN (insn) = note;
4061 NEXT_INSN (note) = insn;
4066 new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
4067 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
4068 RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note);
4072 fprintf (file, ";; added %d line-number notes\n", notes);
4077 fprintf (file, ";; total time = %d\n;; new basic block head = %d\n;; new basic block end = %d\n\n",
4078 clock, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b]));
4081 /* Yow! We're done! */
4082 free_pending_lists ();
4087 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
4088 REGNO, returning the rtx of the reference found if any. Otherwise,
4092 regno_use_in (regno, x)
4100 if (GET_CODE (x) == REG && REGNO (x) == regno)
4103 fmt = GET_RTX_FORMAT (GET_CODE (x));
4104 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4108 if (tem = regno_use_in (regno, XEXP (x, i)))
4111 else if (fmt[i] == 'E')
4112 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4113 if (tem = regno_use_in (regno , XVECEXP (x, i, j)))
4120 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
4121 needed for the hard register mentioned in the note. This can happen
4122 if the reference to the hard register in the original insn was split into
4123 several smaller hard register references in the split insns. */
4126 split_hard_reg_notes (note, first, last, orig_insn)
4127 rtx note, first, last, orig_insn;
4129 rtx reg, temp, link;
4130 int n_regs, i, new_reg;
4133 /* Assume that this is a REG_DEAD note. */
4134 if (REG_NOTE_KIND (note) != REG_DEAD)
4137 reg = XEXP (note, 0);
4139 n_regs = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
4141 for (i = 0; i < n_regs; i++)
4143 new_reg = REGNO (reg) + i;
4145 /* Check for references to new_reg in the split insns. */
4146 for (insn = last; ; insn = PREV_INSN (insn))
4148 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4149 && (temp = regno_use_in (new_reg, PATTERN (insn))))
4151 /* Create a new reg dead note here. */
4152 link = rtx_alloc (EXPR_LIST);
4153 PUT_REG_NOTE_KIND (link, REG_DEAD);
4154 XEXP (link, 0) = temp;
4155 XEXP (link, 1) = REG_NOTES (insn);
4156 REG_NOTES (insn) = link;
4158 /* If killed multiple registers here, then add in the excess. */
4159 i += HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) - 1;
4163 /* It isn't mentioned anywhere, so no new reg note is needed for
4171 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
4172 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
4175 new_insn_dead_notes (pat, insn, last, orig_insn)
4176 rtx pat, insn, last, orig_insn;
4180 /* PAT is either a CLOBBER or a SET here. */
4181 dest = XEXP (pat, 0);
4183 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
4184 || GET_CODE (dest) == STRICT_LOW_PART
4185 || GET_CODE (dest) == SIGN_EXTRACT)
4186 dest = XEXP (dest, 0);
4188 if (GET_CODE (dest) == REG)
4190 for (tem = last; tem != insn; tem = PREV_INSN (tem))
4192 if (GET_RTX_CLASS (GET_CODE (tem)) == 'i'
4193 && reg_overlap_mentioned_p (dest, PATTERN (tem))
4194 && (set = single_set (tem)))
4196 rtx tem_dest = SET_DEST (set);
4198 while (GET_CODE (tem_dest) == ZERO_EXTRACT
4199 || GET_CODE (tem_dest) == SUBREG
4200 || GET_CODE (tem_dest) == STRICT_LOW_PART
4201 || GET_CODE (tem_dest) == SIGN_EXTRACT)
4202 tem_dest = XEXP (tem_dest, 0);
4204 if (! rtx_equal_p (tem_dest, dest))
4206 /* Use the same scheme as combine.c, don't put both REG_DEAD
4207 and REG_UNUSED notes on the same insn. */
4208 if (! find_regno_note (tem, REG_UNUSED, REGNO (dest))
4209 && ! find_regno_note (tem, REG_DEAD, REGNO (dest)))
4211 rtx note = rtx_alloc (EXPR_LIST);
4212 PUT_REG_NOTE_KIND (note, REG_DEAD);
4213 XEXP (note, 0) = dest;
4214 XEXP (note, 1) = REG_NOTES (tem);
4215 REG_NOTES (tem) = note;
4217 /* The reg only dies in one insn, the last one that uses
4221 else if (reg_overlap_mentioned_p (dest, SET_SRC (set)))
4222 /* We found an instruction that both uses the register,
4223 and sets it, so no new REG_NOTE is needed for this set. */
4227 /* If this is a set, it must die somewhere, unless it is the dest of
4228 the original insn, and hence is live after the original insn. Abort
4229 if it isn't supposed to be live after the original insn.
4231 If this is a clobber, then just add a REG_UNUSED note. */
4234 int live_after_orig_insn = 0;
4235 rtx pattern = PATTERN (orig_insn);
4238 if (GET_CODE (pat) == CLOBBER)
4240 rtx note = rtx_alloc (EXPR_LIST);
4241 PUT_REG_NOTE_KIND (note, REG_UNUSED);
4242 XEXP (note, 0) = dest;
4243 XEXP (note, 1) = REG_NOTES (insn);
4244 REG_NOTES (insn) = note;
4248 /* The original insn could have multiple sets, so search the
4249 insn for all sets. */
4250 if (GET_CODE (pattern) == SET)
4252 if (reg_overlap_mentioned_p (dest, SET_DEST (pattern)))
4253 live_after_orig_insn = 1;
4255 else if (GET_CODE (pattern) == PARALLEL)
4257 for (i = 0; i < XVECLEN (pattern, 0); i++)
4258 if (GET_CODE (XVECEXP (pattern, 0, i)) == SET
4259 && reg_overlap_mentioned_p (dest,
4260 SET_DEST (XVECEXP (pattern,
4262 live_after_orig_insn = 1;
4265 if (! live_after_orig_insn)
4271 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
4272 registers modified by X. INC is -1 if the containing insn is being deleted,
4273 and is 1 if the containing insn is a newly generated insn. */
4276 update_n_sets (x, inc)
4280 rtx dest = SET_DEST (x);
4282 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
4283 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
4284 dest = SUBREG_REG (dest);
4286 if (GET_CODE (dest) == REG)
4288 int regno = REGNO (dest);
4290 if (regno < FIRST_PSEUDO_REGISTER)
4293 int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest));
4295 for (i = regno; i < endregno; i++)
4296 REG_N_SETS (i) += inc;
4299 REG_N_SETS (regno) += inc;
4303 /* Updates all flow-analysis related quantities (including REG_NOTES) for
4304 the insns from FIRST to LAST inclusive that were created by splitting
4305 ORIG_INSN. NOTES are the original REG_NOTES. */
4308 update_flow_info (notes, first, last, orig_insn)
4315 rtx orig_dest, temp;
4318 /* Get and save the destination set by the original insn. */
4320 orig_dest = single_set (orig_insn);
4322 orig_dest = SET_DEST (orig_dest);
4324 /* Move REG_NOTES from the original insn to where they now belong. */
4326 for (note = notes; note; note = next)
4328 next = XEXP (note, 1);
4329 switch (REG_NOTE_KIND (note))
4333 /* Move these notes from the original insn to the last new insn where
4334 the register is now set. */
4336 for (insn = last; ; insn = PREV_INSN (insn))
4338 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4339 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
4341 /* If this note refers to a multiple word hard register, it
4342 may have been split into several smaller hard register
4343 references, so handle it specially. */
4344 temp = XEXP (note, 0);
4345 if (REG_NOTE_KIND (note) == REG_DEAD
4346 && GET_CODE (temp) == REG
4347 && REGNO (temp) < FIRST_PSEUDO_REGISTER
4348 && HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) > 1)
4349 split_hard_reg_notes (note, first, last, orig_insn);
4352 XEXP (note, 1) = REG_NOTES (insn);
4353 REG_NOTES (insn) = note;
4356 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
4358 /* ??? This won't handle multiple word registers correctly,
4359 but should be good enough for now. */
4360 if (REG_NOTE_KIND (note) == REG_UNUSED
4361 && ! dead_or_set_p (insn, XEXP (note, 0)))
4362 PUT_REG_NOTE_KIND (note, REG_DEAD);
4364 /* The reg only dies in one insn, the last one that uses
4368 /* It must die somewhere, fail it we couldn't find where it died.
4370 If this is a REG_UNUSED note, then it must be a temporary
4371 register that was not needed by this instantiation of the
4372 pattern, so we can safely ignore it. */
4375 /* After reload, REG_DEAD notes come sometimes an
4376 instruction after the register actually dies. */
4377 if (reload_completed && REG_NOTE_KIND (note) == REG_DEAD)
4379 XEXP (note, 1) = REG_NOTES (insn);
4380 REG_NOTES (insn) = note;
4384 if (REG_NOTE_KIND (note) != REG_UNUSED)
4393 /* This note applies to the dest of the original insn. Find the
4394 first new insn that now has the same dest, and move the note
4400 for (insn = first; ; insn = NEXT_INSN (insn))
4402 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4403 && (temp = single_set (insn))
4404 && rtx_equal_p (SET_DEST (temp), orig_dest))
4406 XEXP (note, 1) = REG_NOTES (insn);
4407 REG_NOTES (insn) = note;
4408 /* The reg is only zero before one insn, the first that
4412 /* If this note refers to a multiple word hard
4413 register, it may have been split into several smaller
4414 hard register references. We could split the notes,
4415 but simply dropping them is good enough. */
4416 if (GET_CODE (orig_dest) == REG
4417 && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER
4418 && HARD_REGNO_NREGS (REGNO (orig_dest),
4419 GET_MODE (orig_dest)) > 1)
4421 /* It must be set somewhere, fail if we couldn't find where it
4430 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
4431 set is meaningless. Just drop the note. */
4435 case REG_NO_CONFLICT:
4436 /* These notes apply to the dest of the original insn. Find the last
4437 new insn that now has the same dest, and move the note there. */
4442 for (insn = last; ; insn = PREV_INSN (insn))
4444 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4445 && (temp = single_set (insn))
4446 && rtx_equal_p (SET_DEST (temp), orig_dest))
4448 XEXP (note, 1) = REG_NOTES (insn);
4449 REG_NOTES (insn) = note;
4450 /* Only put this note on one of the new insns. */
4454 /* The original dest must still be set someplace. Abort if we
4455 couldn't find it. */
4458 /* However, if this note refers to a multiple word hard
4459 register, it may have been split into several smaller
4460 hard register references. We could split the notes,
4461 but simply dropping them is good enough. */
4462 if (GET_CODE (orig_dest) == REG
4463 && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER
4464 && HARD_REGNO_NREGS (REGNO (orig_dest),
4465 GET_MODE (orig_dest)) > 1)
4467 /* Likewise for multi-word memory references. */
4468 if (GET_CODE (orig_dest) == MEM
4469 && SIZE_FOR_MODE (orig_dest) > MOVE_MAX)
4477 /* Move a REG_LIBCALL note to the first insn created, and update
4478 the corresponding REG_RETVAL note. */
4479 XEXP (note, 1) = REG_NOTES (first);
4480 REG_NOTES (first) = note;
4482 insn = XEXP (note, 0);
4483 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
4485 XEXP (note, 0) = first;
4488 case REG_EXEC_COUNT:
4489 /* Move a REG_EXEC_COUNT note to the first insn created. */
4490 XEXP (note, 1) = REG_NOTES (first);
4491 REG_NOTES (first) = note;
4495 /* Move a REG_RETVAL note to the last insn created, and update
4496 the corresponding REG_LIBCALL note. */
4497 XEXP (note, 1) = REG_NOTES (last);
4498 REG_NOTES (last) = note;
4500 insn = XEXP (note, 0);
4501 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
4503 XEXP (note, 0) = last;
4508 /* This should be moved to whichever instruction is a JUMP_INSN. */
4510 for (insn = last; ; insn = PREV_INSN (insn))
4512 if (GET_CODE (insn) == JUMP_INSN)
4514 XEXP (note, 1) = REG_NOTES (insn);
4515 REG_NOTES (insn) = note;
4516 /* Only put this note on one of the new insns. */
4519 /* Fail if we couldn't find a JUMP_INSN. */
4526 /* reload sometimes leaves obsolete REG_INC notes around. */
4527 if (reload_completed)
4529 /* This should be moved to whichever instruction now has the
4530 increment operation. */
4534 /* Should be moved to the new insn(s) which use the label. */
4535 for (insn = first; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
4536 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4537 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
4538 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL,
4539 XEXP (note, 0), REG_NOTES (insn));
4544 /* These two notes will never appear until after reorg, so we don't
4545 have to handle them here. */
4551 /* Each new insn created, except the last, has a new set. If the destination
4552 is a register, then this reg is now live across several insns, whereas
4553 previously the dest reg was born and died within the same insn. To
4554 reflect this, we now need a REG_DEAD note on the insn where this
4557 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
4559 for (insn = first; insn != last; insn = NEXT_INSN (insn))
4564 pat = PATTERN (insn);
4565 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
4566 new_insn_dead_notes (pat, insn, last, orig_insn);
4567 else if (GET_CODE (pat) == PARALLEL)
4569 for (i = 0; i < XVECLEN (pat, 0); i++)
4570 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
4571 || GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER)
4572 new_insn_dead_notes (XVECEXP (pat, 0, i), insn, last, orig_insn);
4576 /* If any insn, except the last, uses the register set by the last insn,
4577 then we need a new REG_DEAD note on that insn. In this case, there
4578 would not have been a REG_DEAD note for this register in the original
4579 insn because it was used and set within one insn.
4581 There is no new REG_DEAD note needed if the last insn uses the register
4582 that it is setting. */
4584 set = single_set (last);
4587 rtx dest = SET_DEST (set);
4589 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
4590 || GET_CODE (dest) == STRICT_LOW_PART
4591 || GET_CODE (dest) == SIGN_EXTRACT)
4592 dest = XEXP (dest, 0);
4594 if (GET_CODE (dest) == REG
4595 /* Global registers are always live, so the code below does not
4597 && (REGNO (dest) >= FIRST_PSEUDO_REGISTER
4598 || ! global_regs[REGNO (dest)])
4599 && ! reg_overlap_mentioned_p (dest, SET_SRC (set)))
4601 for (insn = PREV_INSN (last); ; insn = PREV_INSN (insn))
4603 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4604 && reg_mentioned_p (dest, PATTERN (insn))
4605 && (set = single_set (insn)))
4607 rtx insn_dest = SET_DEST (set);
4609 while (GET_CODE (insn_dest) == ZERO_EXTRACT
4610 || GET_CODE (insn_dest) == SUBREG
4611 || GET_CODE (insn_dest) == STRICT_LOW_PART
4612 || GET_CODE (insn_dest) == SIGN_EXTRACT)
4613 insn_dest = XEXP (insn_dest, 0);
4615 if (insn_dest != dest)
4617 note = rtx_alloc (EXPR_LIST);
4618 PUT_REG_NOTE_KIND (note, REG_DEAD);
4619 XEXP (note, 0) = dest;
4620 XEXP (note, 1) = REG_NOTES (insn);
4621 REG_NOTES (insn) = note;
4622 /* The reg only dies in one insn, the last one
4633 /* If the original dest is modifying a multiple register target, and the
4634 original instruction was split such that the original dest is now set
4635 by two or more SUBREG sets, then the split insns no longer kill the
4636 destination of the original insn.
4638 In this case, if there exists an instruction in the same basic block,
4639 before the split insn, which uses the original dest, and this use is
4640 killed by the original insn, then we must remove the REG_DEAD note on
4641 this insn, because it is now superfluous.
4643 This does not apply when a hard register gets split, because the code
4644 knows how to handle overlapping hard registers properly. */
4645 if (orig_dest && GET_CODE (orig_dest) == REG)
4647 int found_orig_dest = 0;
4648 int found_split_dest = 0;
4650 for (insn = first; ; insn = NEXT_INSN (insn))
4652 set = single_set (insn);
4655 if (GET_CODE (SET_DEST (set)) == REG
4656 && REGNO (SET_DEST (set)) == REGNO (orig_dest))
4658 found_orig_dest = 1;
4661 else if (GET_CODE (SET_DEST (set)) == SUBREG
4662 && SUBREG_REG (SET_DEST (set)) == orig_dest)
4664 found_split_dest = 1;
4673 if (found_split_dest)
4675 /* Search backwards from FIRST, looking for the first insn that uses
4676 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
4677 If we find an insn, and it has a REG_DEAD note, then delete the
4680 for (insn = first; insn; insn = PREV_INSN (insn))
4682 if (GET_CODE (insn) == CODE_LABEL
4683 || GET_CODE (insn) == JUMP_INSN)
4685 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4686 && reg_mentioned_p (orig_dest, insn))
4688 note = find_regno_note (insn, REG_DEAD, REGNO (orig_dest));
4690 remove_note (insn, note);
4694 else if (! found_orig_dest)
4696 /* This should never happen. */
4701 /* Update reg_n_sets. This is necessary to prevent local alloc from
4702 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
4703 a reg from set once to set multiple times. */
4706 rtx x = PATTERN (orig_insn);
4707 RTX_CODE code = GET_CODE (x);
4709 if (code == SET || code == CLOBBER)
4710 update_n_sets (x, -1);
4711 else if (code == PARALLEL)
4714 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4716 code = GET_CODE (XVECEXP (x, 0, i));
4717 if (code == SET || code == CLOBBER)
4718 update_n_sets (XVECEXP (x, 0, i), -1);
4722 for (insn = first; ; insn = NEXT_INSN (insn))
4725 code = GET_CODE (x);
4727 if (code == SET || code == CLOBBER)
4728 update_n_sets (x, 1);
4729 else if (code == PARALLEL)
4732 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4734 code = GET_CODE (XVECEXP (x, 0, i));
4735 if (code == SET || code == CLOBBER)
4736 update_n_sets (XVECEXP (x, 0, i), 1);
4746 /* The one entry point in this file. DUMP_FILE is the dump file for
4750 schedule_insns (dump_file)
4753 int max_uid = MAX_INSNS_PER_SPLIT * (get_max_uid () + 1);
4758 /* Taking care of this degenerate case makes the rest of
4759 this code simpler. */
4760 if (n_basic_blocks == 0)
4763 /* Create an insn here so that we can hang dependencies off of it later. */
4764 sched_before_next_call
4765 = gen_rtx (INSN, VOIDmode, 0, NULL_RTX, NULL_RTX,
4766 NULL_RTX, 0, NULL_RTX, 0);
4768 /* Initialize the unused_*_lists. We can't use the ones left over from
4769 the previous function, because gcc has freed that memory. We can use
4770 the ones left over from the first sched pass in the second pass however,
4771 so only clear them on the first sched pass. The first pass is before
4772 reload if flag_schedule_insns is set, otherwise it is afterwards. */
4774 if (reload_completed == 0 || ! flag_schedule_insns)
4776 unused_insn_list = 0;
4777 unused_expr_list = 0;
4780 /* We create no insns here, only reorder them, so we
4781 remember how far we can cut back the stack on exit. */
4783 /* Allocate data for this pass. See comments, above,
4784 for what these vectors do. */
4785 insn_luid = (int *) alloca (max_uid * sizeof (int));
4786 insn_priority = (int *) alloca (max_uid * sizeof (int));
4787 insn_tick = (int *) alloca (max_uid * sizeof (int));
4788 insn_costs = (short *) alloca (max_uid * sizeof (short));
4789 insn_units = (short *) alloca (max_uid * sizeof (short));
4790 insn_blockage = (unsigned int *) alloca (max_uid * sizeof (unsigned int));
4791 insn_ref_count = (int *) alloca (max_uid * sizeof (int));
4793 if (reload_completed == 0)
4795 sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int));
4796 sched_reg_live_length = (int *) alloca (max_regno * sizeof (int));
4797 bb_dead_regs = ALLOCA_REG_SET ();
4798 bb_live_regs = ALLOCA_REG_SET ();
4799 bzero ((char *) sched_reg_n_calls_crossed, max_regno * sizeof (int));
4800 bzero ((char *) sched_reg_live_length, max_regno * sizeof (int));
4801 init_alias_analysis ();
4805 sched_reg_n_calls_crossed = 0;
4806 sched_reg_live_length = 0;
4809 if (! flag_schedule_insns)
4810 init_alias_analysis ();
4813 if (write_symbols != NO_DEBUG)
4817 line_note = (rtx *) alloca (max_uid * sizeof (rtx));
4818 bzero ((char *) line_note, max_uid * sizeof (rtx));
4819 line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx));
4820 bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx));
4822 /* Determine the line-number at the start of each basic block.
4823 This must be computed and saved now, because after a basic block's
4824 predecessor has been scheduled, it is impossible to accurately
4825 determine the correct line number for the first insn of the block. */
4827 for (b = 0; b < n_basic_blocks; b++)
4828 for (line = basic_block_head[b]; line; line = PREV_INSN (line))
4829 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4831 line_note_head[b] = line;
4836 bzero ((char *) insn_luid, max_uid * sizeof (int));
4837 bzero ((char *) insn_priority, max_uid * sizeof (int));
4838 bzero ((char *) insn_tick, max_uid * sizeof (int));
4839 bzero ((char *) insn_costs, max_uid * sizeof (short));
4840 bzero ((char *) insn_units, max_uid * sizeof (short));
4841 bzero ((char *) insn_blockage, max_uid * sizeof (unsigned int));
4842 bzero ((char *) insn_ref_count, max_uid * sizeof (int));
4844 /* Schedule each basic block, block by block. */
4846 /* ??? Add a NOTE after the last insn of the last basic block. It is not
4847 known why this is done. */
4848 /* ??? Perhaps it's done to ensure NEXT_TAIL in schedule_block is a
4851 insn = basic_block_end[n_basic_blocks-1];
4852 if (NEXT_INSN (insn) == 0
4853 || (GET_CODE (insn) != NOTE
4854 && GET_CODE (insn) != CODE_LABEL
4855 /* Don't emit a NOTE if it would end up between an unconditional
4856 jump and a BARRIER. */
4857 && ! (GET_CODE (insn) == JUMP_INSN
4858 && GET_CODE (NEXT_INSN (insn)) == BARRIER)))
4859 emit_note_after (NOTE_INSN_DELETED, basic_block_end[n_basic_blocks-1]);
4861 for (b = 0; b < n_basic_blocks; b++)
4867 for (insn = basic_block_head[b]; ; insn = next)
4872 /* Can't use `next_real_insn' because that
4873 might go across CODE_LABELS and short-out basic blocks. */
4874 next = NEXT_INSN (insn);
4875 if (GET_CODE (insn) != INSN)
4877 if (insn == basic_block_end[b])
4883 /* Don't split no-op move insns. These should silently disappear
4884 later in final. Splitting such insns would break the code
4885 that handles REG_NO_CONFLICT blocks. */
4886 set = single_set (insn);
4887 if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
4889 if (insn == basic_block_end[b])
4892 /* Nops get in the way while scheduling, so delete them now if
4893 register allocation has already been done. It is too risky
4894 to try to do this before register allocation, and there are
4895 unlikely to be very many nops then anyways. */
4896 if (reload_completed)
4898 PUT_CODE (insn, NOTE);
4899 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4900 NOTE_SOURCE_FILE (insn) = 0;
4906 /* Split insns here to get max fine-grain parallelism. */
4907 prev = PREV_INSN (insn);
4908 /* It is probably not worthwhile to try to split again in the
4909 second pass. However, if flag_schedule_insns is not set,
4910 the first and only (if any) scheduling pass is after reload. */
4911 if (reload_completed == 0 || ! flag_schedule_insns)
4913 rtx last, first = PREV_INSN (insn);
4914 rtx notes = REG_NOTES (insn);
4916 last = try_split (PATTERN (insn), insn, 1);
4919 /* try_split returns the NOTE that INSN became. */
4920 first = NEXT_INSN (first);
4921 update_flow_info (notes, first, last, insn);
4923 PUT_CODE (insn, NOTE);
4924 NOTE_SOURCE_FILE (insn) = 0;
4925 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4926 if (insn == basic_block_head[b])
4927 basic_block_head[b] = first;
4928 if (insn == basic_block_end[b])
4930 basic_block_end[b] = last;
4936 if (insn == basic_block_end[b])
4940 schedule_block (b, dump_file);
4947 /* Reposition the prologue and epilogue notes in case we moved the
4948 prologue/epilogue insns. */
4949 if (reload_completed)
4950 reposition_prologue_and_epilogue_notes (get_insns ());
4952 if (write_symbols != NO_DEBUG)
4955 rtx insn = get_insns ();
4956 int active_insn = 0;
4959 /* Walk the insns deleting redundant line-number notes. Many of these
4960 are already present. The remainder tend to occur at basic
4961 block boundaries. */
4962 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
4963 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4965 /* If there are no active insns following, INSN is redundant. */
4966 if (active_insn == 0)
4969 NOTE_SOURCE_FILE (insn) = 0;
4970 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4972 /* If the line number is unchanged, LINE is redundant. */
4974 && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
4975 && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
4978 NOTE_SOURCE_FILE (line) = 0;
4979 NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
4986 else if (! ((GET_CODE (insn) == NOTE
4987 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
4988 || (GET_CODE (insn) == INSN
4989 && (GET_CODE (PATTERN (insn)) == USE
4990 || GET_CODE (PATTERN (insn)) == CLOBBER))))
4993 if (dump_file && notes)
4994 fprintf (dump_file, ";; deleted %d line-number notes\n", notes);
4997 if (reload_completed == 0)
5000 for (regno = 0; regno < max_regno; regno++)
5001 if (sched_reg_live_length[regno])
5005 if (REG_LIVE_LENGTH (regno) > sched_reg_live_length[regno])
5007 ";; register %d life shortened from %d to %d\n",
5008 regno, REG_LIVE_LENGTH (regno),
5009 sched_reg_live_length[regno]);
5010 /* Negative values are special; don't overwrite the current
5011 reg_live_length value if it is negative. */
5012 else if (REG_LIVE_LENGTH (regno) < sched_reg_live_length[regno]
5013 && REG_LIVE_LENGTH (regno) >= 0)
5015 ";; register %d life extended from %d to %d\n",
5016 regno, REG_LIVE_LENGTH (regno),
5017 sched_reg_live_length[regno]);
5019 if (! REG_N_CALLS_CROSSED (regno)
5020 && sched_reg_n_calls_crossed[regno])
5022 ";; register %d now crosses calls\n", regno);
5023 else if (REG_N_CALLS_CROSSED (regno)
5024 && ! sched_reg_n_calls_crossed[regno]
5025 && REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL)
5027 ";; register %d no longer crosses calls\n", regno);
5030 /* Negative values are special; don't overwrite the current
5031 reg_live_length value if it is negative. */
5032 if (REG_LIVE_LENGTH (regno) >= 0)
5033 REG_LIVE_LENGTH (regno) = sched_reg_live_length[regno];
5035 /* We can't change the value of reg_n_calls_crossed to zero for
5036 pseudos which are live in more than one block.
5038 This is because combine might have made an optimization which
5039 invalidated basic_block_live_at_start and reg_n_calls_crossed,
5040 but it does not update them. If we update reg_n_calls_crossed
5041 here, the two variables are now inconsistent, and this might
5042 confuse the caller-save code into saving a register that doesn't
5043 need to be saved. This is only a problem when we zero calls
5044 crossed for a pseudo live in multiple basic blocks.
5046 Alternatively, we could try to correctly update basic block live
5047 at start here in sched, but that seems complicated. */
5048 if (sched_reg_n_calls_crossed[regno]
5049 || REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL)
5050 REG_N_CALLS_CROSSED (regno) = sched_reg_n_calls_crossed[regno];
5054 #endif /* INSN_SCHEDULING */