1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 Enhanced by, and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Instruction scheduling pass.
25 This pass implements list scheduling within basic blocks. It is
26 run after flow analysis, but before register allocation. The
27 scheduler works as follows:
29 We compute insn priorities based on data dependencies. Flow
30 analysis only creates a fraction of the data-dependencies we must
31 observe: namely, only those dependencies which the combiner can be
32 expected to use. For this pass, we must therefore create the
33 remaining dependencies we need to observe: register dependencies,
34 memory dependencies, dependencies to keep function calls in order,
35 and the dependence between a conditional branch and the setting of
36 condition codes are all dealt with here.
38 The scheduler first traverses the data flow graph, starting with
39 the last instruction, and proceeding to the first, assigning
40 values to insn_priority as it goes. This sorts the instructions
41 topologically by data dependence.
43 Once priorities have been established, we order the insns using
44 list scheduling. This works as follows: starting with a list of
45 all the ready insns, and sorted according to priority number, we
46 schedule the insn from the end of the list by placing its
47 predecessors in the list according to their priority order. We
48 consider this insn scheduled by setting the pointer to the "end" of
49 the list to point to the previous insn. When an insn has no
50 predecessors, we either queue it until sufficient time has elapsed
51 or add it to the ready list. As the instructions are scheduled or
52 when stalls are introduced, the queue advances and dumps insns into
53 the ready list. When all insns down to the lowest priority have
54 been scheduled, the critical path of the basic block has been made
55 as short as possible. The remaining insns are then scheduled in
58 Function unit conflicts are resolved during reverse list scheduling
59 by tracking the time when each insn is committed to the schedule
60 and from that, the time the function units it uses must be free.
61 As insns on the ready list are considered for scheduling, those
62 that would result in a blockage of the already committed insns are
63 queued until no blockage will result. Among the remaining insns on
64 the ready list to be considered, the first one with the largest
65 potential for causing a subsequent blockage is chosen.
67 The following list shows the order in which we want to break ties
68 among insns in the ready list:
70 1. choose insn with lowest conflict cost, ties broken by
71 2. choose insn with the longest path to end of bb, ties broken by
72 3. choose insn that kills the most registers, ties broken by
73 4. choose insn that conflicts with the most ready insns, or finally
74 5. choose insn with lowest UID.
76 Memory references complicate matters. Only if we can be certain
77 that memory references are not part of the data dependency graph
78 (via true, anti, or output dependence), can we move operations past
79 memory references. To first approximation, reads can be done
80 independently, while writes introduce dependencies. Better
81 approximations will yield fewer dependencies.
83 Dependencies set up by memory references are treated in exactly the
84 same way as other dependencies, by using LOG_LINKS.
86 Having optimized the critical path, we may have also unduly
87 extended the lifetimes of some registers. If an operation requires
88 that constants be loaded into registers, it is certainly desirable
89 to load those constants as early as necessary, but no earlier.
90 I.e., it will not do to load up a bunch of registers at the
91 beginning of a basic block only to use them at the end, if they
92 could be loaded later, since this may result in excessive register
95 Note that since branches are never in basic blocks, but only end
96 basic blocks, this pass will not do any branch scheduling. But
97 that is ok, since we can use GNU's delayed branch scheduling
98 pass to take care of this case.
100 Also note that no further optimizations based on algebraic identities
101 are performed, so this pass would be a good one to perform instruction
102 splitting, such as breaking up a multiply instruction into shifts
103 and adds where that is profitable.
105 Given the memory aliasing analysis that this pass should perform,
106 it should be possible to remove redundant stores to memory, and to
107 load values from registers instead of hitting memory.
109 This pass must update information that subsequent passes expect to be
110 correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
111 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
114 The information in the line number notes is carefully retained by this
115 pass. All other NOTE insns are grouped in their same relative order at
116 the beginning of basic blocks that have been scheduled. */
121 #include "basic-block.h"
123 #include "hard-reg-set.h"
125 #include "insn-config.h"
126 #include "insn-attr.h"
128 #ifdef INSN_SCHEDULING
129 /* Arrays set up by scheduling for the same respective purposes as
130 similar-named arrays set up by flow analysis. We work with these
131 arrays during the scheduling pass so we can compare values against
134 Values of these arrays are copied at the end of this pass into the
135 arrays set up by flow analysis. */
136 static short *sched_reg_n_deaths;
137 static int *sched_reg_n_calls_crossed;
138 static int *sched_reg_live_length;
140 /* Element N is the next insn that sets (hard or pseudo) register
141 N within the current basic block; or zero, if there is no
142 such insn. Needed for new registers which may be introduced
143 by splitting insns. */
144 static rtx *reg_last_uses;
145 static rtx *reg_last_sets;
146 static regset reg_pending_sets;
147 static int reg_pending_sets_all;
149 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
150 static int *insn_luid;
151 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
153 /* Vector indexed by INSN_UID giving each instruction a priority. */
154 static int *insn_priority;
155 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
157 static short *insn_costs;
158 #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
160 /* Vector indexed by INSN_UID giving an encoding of the function units
162 static short *insn_units;
163 #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)]
165 /* Vector indexed by INSN_UID giving an encoding of the blockage range
166 function. The unit and the range are encoded. */
167 static unsigned int *insn_blockage;
168 #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)]
170 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
171 #define ENCODE_BLOCKAGE(U,R) \
172 ((((U) << UNIT_BITS) << BLOCKAGE_BITS \
173 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
174 | MAX_BLOCKAGE_COST (R))
175 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
176 #define BLOCKAGE_RANGE(B) \
177 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
178 | (B) & BLOCKAGE_MASK)
180 /* Encodings of the `<name>_unit_blockage_range' function. */
181 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
182 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
184 #define DONE_PRIORITY -1
185 #define MAX_PRIORITY 0x7fffffff
186 #define TAIL_PRIORITY 0x7ffffffe
187 #define LAUNCH_PRIORITY 0x7f000001
188 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
189 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
191 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
192 static int *insn_ref_count;
193 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
195 /* Vector indexed by INSN_UID giving line-number note in effect for each
196 insn. For line-number notes, this indicates whether the note may be
198 static rtx *line_note;
199 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
201 /* Vector indexed by basic block number giving the starting line-number
202 for each basic block. */
203 static rtx *line_note_head;
205 /* List of important notes we must keep around. This is a pointer to the
206 last element in the list. */
207 static rtx note_list;
209 /* Regsets telling whether a given register is live or dead before the last
210 scheduled insn. Must scan the instructions once before scheduling to
211 determine what registers are live or dead at the end of the block. */
212 static regset bb_dead_regs;
213 static regset bb_live_regs;
215 /* Regset telling whether a given register is live after the insn currently
216 being scheduled. Before processing an insn, this is equal to bb_live_regs
217 above. This is used so that we can find registers that are newly born/dead
218 after processing an insn. */
219 static regset old_live_regs;
221 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
222 during the initial scan and reused later. If there are not exactly as
223 many REG_DEAD notes in the post scheduled code as there were in the
224 prescheduled code then we trigger an abort because this indicates a bug. */
225 static rtx dead_notes;
229 /* An instruction is ready to be scheduled when all insns following it
230 have already been scheduled. It is important to ensure that all
231 insns which use its result will not be executed until its result
232 has been computed. An insn is maintained in one of four structures:
234 (P) the "Pending" set of insns which cannot be scheduled until
235 their dependencies have been satisfied.
236 (Q) the "Queued" set of insns that can be scheduled when sufficient
238 (R) the "Ready" list of unscheduled, uncommitted insns.
239 (S) the "Scheduled" list of insns.
241 Initially, all insns are either "Pending" or "Ready" depending on
242 whether their dependencies are satisfied.
244 Insns move from the "Ready" list to the "Scheduled" list as they
245 are committed to the schedule. As this occurs, the insns in the
246 "Pending" list have their dependencies satisfied and move to either
247 the "Ready" list or the "Queued" set depending on whether
248 sufficient time has passed to make them ready. As time passes,
249 insns move from the "Queued" set to the "Ready" list. Insns may
250 move from the "Ready" list to the "Queued" set if they are blocked
251 due to a function unit conflict.
253 The "Pending" list (P) are the insns in the LOG_LINKS of the unscheduled
254 insns, i.e., those that are ready, queued, and pending.
255 The "Queued" set (Q) is implemented by the variable `insn_queue'.
256 The "Ready" list (R) is implemented by the variables `ready' and
258 The "Scheduled" list (S) is the new insn chain built by this pass.
260 The transition (R->S) is implemented in the scheduling loop in
261 `schedule_block' when the best insn to schedule is chosen.
262 The transition (R->Q) is implemented in `schedule_select' when an
263 insn is found to to have a function unit conflict with the already
265 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
266 insns move from the ready list to the scheduled list.
267 The transition (Q->R) is implemented at the top of the scheduling
268 loop in `schedule_block' as time passes or stalls are introduced. */
270 /* Implement a circular buffer to delay instructions until sufficient
271 time has passed. INSN_QUEUE_SIZE is a power of two larger than
272 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
273 longest time an isnsn may be queued. */
274 static rtx insn_queue[INSN_QUEUE_SIZE];
275 static int q_ptr = 0;
276 static int q_size = 0;
277 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
278 #define NEXT_Q_AFTER(X,C) (((X)+C) & (INSN_QUEUE_SIZE-1))
280 /* Vector indexed by INSN_UID giving the minimum clock tick at which
281 the insn becomes ready. This is used to note timing constraints for
282 insns in the pending list. */
283 static int *insn_tick;
284 #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)])
286 /* Data structure for keeping track of register information
287 during that register's life. */
291 short offset; short bit;
292 short live_length; short calls_crossed;
295 /* Forward declarations. */
296 static rtx canon_rtx PROTO((rtx));
297 static int rtx_equal_for_memref_p PROTO((rtx, rtx));
298 static rtx find_symbolic_term PROTO((rtx));
299 static int memrefs_conflict_p PROTO((int, rtx, int, rtx,
301 static void add_dependence PROTO((rtx, rtx, enum reg_note));
302 static void remove_dependence PROTO((rtx, rtx));
303 static rtx find_insn_list PROTO((rtx, rtx));
304 static int insn_unit PROTO((rtx));
305 static unsigned int blockage_range PROTO((int, rtx));
306 static void clear_units PROTO((void));
307 static void prepare_unit PROTO((int));
308 static int actual_hazard_this_instance PROTO((int, int, rtx, int, int));
309 static void schedule_unit PROTO((int, rtx, int));
310 static int actual_hazard PROTO((int, rtx, int, int));
311 static int potential_hazard PROTO((int, rtx, int));
312 static int insn_cost PROTO((rtx, rtx, rtx));
313 static int priority PROTO((rtx));
314 static void free_pending_lists PROTO((void));
315 static void add_insn_mem_dependence PROTO((rtx *, rtx *, rtx, rtx));
316 static void flush_pending_lists PROTO((rtx));
317 static void sched_analyze_1 PROTO((rtx, rtx));
318 static void sched_analyze_2 PROTO((rtx, rtx));
319 static void sched_analyze_insn PROTO((rtx, rtx, rtx));
320 static int sched_analyze PROTO((rtx, rtx));
321 static void sched_note_set PROTO((int, rtx, int));
322 static int rank_for_schedule PROTO((rtx *, rtx *));
323 static void swap_sort PROTO((rtx *, int));
324 static void queue_insn PROTO((rtx, int));
325 static int birthing_insn PROTO((rtx));
326 static void adjust_priority PROTO((rtx));
327 static int schedule_insn PROTO((rtx, rtx *, int, int));
328 static int schedule_select PROTO((rtx *, int, int, FILE *));
329 static void create_reg_dead_note PROTO((rtx, rtx));
330 static void attach_deaths PROTO((rtx, rtx, int));
331 static void attach_deaths_insn PROTO((rtx));
332 static rtx unlink_notes PROTO((rtx, rtx));
333 static int new_sometimes_live PROTO((struct sometimes *, int, int,
335 static void finish_sometimes_live PROTO((struct sometimes *, int));
336 static void schedule_block PROTO((int, FILE *));
337 static rtx regno_use_in PROTO((int, rtx));
338 static void split_hard_reg_notes PROTO((rtx, rtx, rtx, rtx));
339 static void new_insn_dead_notes PROTO((rtx, rtx, rtx, rtx));
340 static void update_n_sets PROTO((rtx, int));
341 static void update_flow_info PROTO((rtx, rtx, rtx, rtx));
343 /* Main entry point of this file. */
344 void schedule_insns PROTO((FILE *));
346 #endif /* INSN_SCHEDULING */
348 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
350 /* Vector indexed by N giving the initial (unchanging) value known
351 for pseudo-register N. */
352 static rtx *reg_known_value;
354 /* Vector recording for each reg_known_value whether it is due to a
355 REG_EQUIV note. Future passes (viz., reload) may replace the
356 pseudo with the equivalent expression and so we account for the
357 dependences that would be introduced if that happens. */
358 /* ??? This is a problem only on the Convex. The REG_EQUIV notes created in
359 assign_parms mention the arg pointer, and there are explicit insns in the
360 RTL that modify the arg pointer. Thus we must ensure that such insns don't
361 get scheduled across each other because that would invalidate the REG_EQUIV
362 notes. One could argue that the REG_EQUIV notes are wrong, but solving
363 the problem in the scheduler will likely give better code, so we do it
365 static char *reg_known_equiv_p;
367 /* Indicates number of valid entries in reg_known_value. */
368 static int reg_known_value_size;
374 /* Recursively look for equivalences. */
375 if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
376 && REGNO (x) <= reg_known_value_size)
377 return reg_known_value[REGNO (x)] == x
378 ? x : canon_rtx (reg_known_value[REGNO (x)]);
379 else if (GET_CODE (x) == PLUS)
381 rtx x0 = canon_rtx (XEXP (x, 0));
382 rtx x1 = canon_rtx (XEXP (x, 1));
384 if (x0 != XEXP (x, 0) || x1 != XEXP (x, 1))
386 /* We can tolerate LO_SUMs being offset here; these
387 rtl are used for nothing other than comparisons. */
388 if (GET_CODE (x0) == CONST_INT)
389 return plus_constant_for_output (x1, INTVAL (x0));
390 else if (GET_CODE (x1) == CONST_INT)
391 return plus_constant_for_output (x0, INTVAL (x1));
392 return gen_rtx (PLUS, GET_MODE (x), x0, x1);
395 /* This gives us much better alias analysis when called from
396 the loop optimizer. Note we want to leave the original
397 MEM alone, but need to return the canonicalized MEM with
398 all the flags with their original values. */
399 else if (GET_CODE (x) == MEM)
401 rtx copy = copy_rtx (x);
402 XEXP (copy, 0) = canon_rtx (XEXP (copy, 0));
408 /* Set up all info needed to perform alias analysis on memory references. */
411 init_alias_analysis ()
413 int maxreg = max_reg_num ();
418 reg_known_value_size = maxreg;
421 = (rtx *) oballoc ((maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx))
422 - FIRST_PSEUDO_REGISTER;
423 bzero ((char *) (reg_known_value + FIRST_PSEUDO_REGISTER),
424 (maxreg-FIRST_PSEUDO_REGISTER) * sizeof (rtx));
427 = (char *) oballoc ((maxreg -FIRST_PSEUDO_REGISTER) * sizeof (char))
428 - FIRST_PSEUDO_REGISTER;
429 bzero (reg_known_equiv_p + FIRST_PSEUDO_REGISTER,
430 (maxreg - FIRST_PSEUDO_REGISTER) * sizeof (char));
432 /* Fill in the entries with known constant values. */
433 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
434 if ((set = single_set (insn)) != 0
435 && GET_CODE (SET_DEST (set)) == REG
436 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER
437 && (((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
438 && reg_n_sets[REGNO (SET_DEST (set))] == 1)
439 || (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != 0)
440 && GET_CODE (XEXP (note, 0)) != EXPR_LIST)
442 int regno = REGNO (SET_DEST (set));
443 reg_known_value[regno] = XEXP (note, 0);
444 reg_known_equiv_p[regno] = REG_NOTE_KIND (note) == REG_EQUIV;
447 /* Fill in the remaining entries. */
448 while (--maxreg >= FIRST_PSEUDO_REGISTER)
449 if (reg_known_value[maxreg] == 0)
450 reg_known_value[maxreg] = regno_reg_rtx[maxreg];
453 /* Return 1 if X and Y are identical-looking rtx's.
455 We use the data in reg_known_value above to see if two registers with
456 different numbers are, in fact, equivalent. */
459 rtx_equal_for_memref_p (x, y)
464 register enum rtx_code code;
467 if (x == 0 && y == 0)
469 if (x == 0 || y == 0)
478 /* Rtx's of different codes cannot be equal. */
479 if (code != GET_CODE (y))
482 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
483 (REG:SI x) and (REG:HI x) are NOT equivalent. */
485 if (GET_MODE (x) != GET_MODE (y))
488 /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */
491 return REGNO (x) == REGNO (y);
492 if (code == LABEL_REF)
493 return XEXP (x, 0) == XEXP (y, 0);
494 if (code == SYMBOL_REF)
495 return XSTR (x, 0) == XSTR (y, 0);
497 /* For commutative operations, the RTX match if the operand match in any
498 order. Also handle the simple binary and unary cases without a loop. */
499 if (code == EQ || code == NE || GET_RTX_CLASS (code) == 'c')
500 return ((rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 0))
501 && rtx_equal_for_memref_p (XEXP (x, 1), XEXP (y, 1)))
502 || (rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 1))
503 && rtx_equal_for_memref_p (XEXP (x, 1), XEXP (y, 0))));
504 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == '2')
505 return (rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 0))
506 && rtx_equal_for_memref_p (XEXP (x, 1), XEXP (y, 1)));
507 else if (GET_RTX_CLASS (code) == '1')
508 return rtx_equal_for_memref_p (XEXP (x, 0), XEXP (y, 0));
510 /* Compare the elements. If any pair of corresponding elements
511 fail to match, return 0 for the whole things. */
513 fmt = GET_RTX_FORMAT (code);
514 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
519 if (XWINT (x, i) != XWINT (y, i))
525 if (XINT (x, i) != XINT (y, i))
531 /* Two vectors must have the same length. */
532 if (XVECLEN (x, i) != XVECLEN (y, i))
535 /* And the corresponding elements must match. */
536 for (j = 0; j < XVECLEN (x, i); j++)
537 if (rtx_equal_for_memref_p (XVECEXP (x, i, j), XVECEXP (y, i, j)) == 0)
542 if (rtx_equal_for_memref_p (XEXP (x, i), XEXP (y, i)) == 0)
548 if (strcmp (XSTR (x, i), XSTR (y, i)))
553 /* These are just backpointers, so they don't matter. */
559 /* It is believed that rtx's at this level will never
560 contain anything but integers and other rtx's,
561 except for within LABEL_REFs and SYMBOL_REFs. */
569 /* Given an rtx X, find a SYMBOL_REF or LABEL_REF within
570 X and return it, or return 0 if none found. */
573 find_symbolic_term (x)
577 register enum rtx_code code;
581 if (code == SYMBOL_REF || code == LABEL_REF)
583 if (GET_RTX_CLASS (code) == 'o')
586 fmt = GET_RTX_FORMAT (code);
587 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
593 t = find_symbolic_term (XEXP (x, i));
597 else if (fmt[i] == 'E')
603 /* Return nonzero if X and Y (memory addresses) could reference the
604 same location in memory. C is an offset accumulator. When
605 C is nonzero, we are testing aliases between X and Y + C.
606 XSIZE is the size in bytes of the X reference,
607 similarly YSIZE is the size in bytes for Y.
609 If XSIZE or YSIZE is zero, we do not know the amount of memory being
610 referenced (the reference was BLKmode), so make the most pessimistic
613 We recognize the following cases of non-conflicting memory:
615 (1) addresses involving the frame pointer cannot conflict
616 with addresses involving static variables.
617 (2) static variables with different addresses cannot conflict.
619 Nice to notice that varying addresses cannot conflict with fp if no
620 local variables had their addresses taken, but that's too hard now. */
622 /* ??? In Fortran, references to a array parameter can never conflict with
623 another array parameter. */
626 memrefs_conflict_p (xsize, x, ysize, y, c)
631 if (GET_CODE (x) == HIGH)
633 else if (GET_CODE (x) == LO_SUM)
637 if (GET_CODE (y) == HIGH)
639 else if (GET_CODE (y) == LO_SUM)
644 if (rtx_equal_for_memref_p (x, y))
645 return (xsize == 0 || ysize == 0 ||
646 (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
648 if (y == frame_pointer_rtx || y == hard_frame_pointer_rtx
649 || y == stack_pointer_rtx)
653 y = x; ysize = xsize;
654 x = t; xsize = tsize;
657 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
658 || x == stack_pointer_rtx)
665 if (GET_CODE (y) == PLUS
666 && canon_rtx (XEXP (y, 0)) == x
667 && (y1 = canon_rtx (XEXP (y, 1)))
668 && GET_CODE (y1) == CONST_INT)
671 return (xsize == 0 || ysize == 0
672 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
675 if (GET_CODE (y) == PLUS
676 && (y1 = canon_rtx (XEXP (y, 0)))
683 if (GET_CODE (x) == PLUS)
685 /* The fact that X is canonicalized means that this
686 PLUS rtx is canonicalized. */
687 rtx x0 = XEXP (x, 0);
688 rtx x1 = XEXP (x, 1);
690 if (GET_CODE (y) == PLUS)
692 /* The fact that Y is canonicalized means that this
693 PLUS rtx is canonicalized. */
694 rtx y0 = XEXP (y, 0);
695 rtx y1 = XEXP (y, 1);
697 if (rtx_equal_for_memref_p (x1, y1))
698 return memrefs_conflict_p (xsize, x0, ysize, y0, c);
699 if (rtx_equal_for_memref_p (x0, y0))
700 return memrefs_conflict_p (xsize, x1, ysize, y1, c);
701 if (GET_CODE (x1) == CONST_INT)
702 if (GET_CODE (y1) == CONST_INT)
703 return memrefs_conflict_p (xsize, x0, ysize, y0,
704 c - INTVAL (x1) + INTVAL (y1));
706 return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1));
707 else if (GET_CODE (y1) == CONST_INT)
708 return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1));
710 /* Handle case where we cannot understand iteration operators,
711 but we notice that the base addresses are distinct objects. */
712 x = find_symbolic_term (x);
715 y = find_symbolic_term (y);
718 return rtx_equal_for_memref_p (x, y);
720 else if (GET_CODE (x1) == CONST_INT)
721 return memrefs_conflict_p (xsize, x0, ysize, y, c - INTVAL (x1));
723 else if (GET_CODE (y) == PLUS)
725 /* The fact that Y is canonicalized means that this
726 PLUS rtx is canonicalized. */
727 rtx y0 = XEXP (y, 0);
728 rtx y1 = XEXP (y, 1);
730 if (GET_CODE (y1) == CONST_INT)
731 return memrefs_conflict_p (xsize, x, ysize, y0, c + INTVAL (y1));
736 if (GET_CODE (x) == GET_CODE (y))
737 switch (GET_CODE (x))
741 /* Handle cases where we expect the second operands to be the
742 same, and check only whether the first operand would conflict
745 rtx x1 = canon_rtx (XEXP (x, 1));
746 rtx y1 = canon_rtx (XEXP (y, 1));
747 if (! rtx_equal_for_memref_p (x1, y1))
749 x0 = canon_rtx (XEXP (x, 0));
750 y0 = canon_rtx (XEXP (y, 0));
751 if (rtx_equal_for_memref_p (x0, y0))
752 return (xsize == 0 || ysize == 0
753 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
755 /* Can't properly adjust our sizes. */
756 if (GET_CODE (x1) != CONST_INT)
758 xsize /= INTVAL (x1);
759 ysize /= INTVAL (x1);
761 return memrefs_conflict_p (xsize, x0, ysize, y0, c);
767 if (GET_CODE (x) == CONST_INT && GET_CODE (y) == CONST_INT)
769 c += (INTVAL (y) - INTVAL (x));
770 return (xsize == 0 || ysize == 0
771 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
774 if (GET_CODE (x) == CONST)
776 if (GET_CODE (y) == CONST)
777 return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
778 ysize, canon_rtx (XEXP (y, 0)), c);
780 return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
783 if (GET_CODE (y) == CONST)
784 return memrefs_conflict_p (xsize, x, ysize,
785 canon_rtx (XEXP (y, 0)), c);
788 return (rtx_equal_for_memref_p (x, y)
789 && (xsize == 0 || ysize == 0
790 || (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0)));
797 /* Functions to compute memory dependencies.
799 Since we process the insns in execution order, we can build tables
800 to keep track of what registers are fixed (and not aliased), what registers
801 are varying in known ways, and what registers are varying in unknown
804 If both memory references are volatile, then there must always be a
805 dependence between the two references, since their order can not be
806 changed. A volatile and non-volatile reference can be interchanged
809 A MEM_IN_STRUCT reference at a non-QImode varying address can never
810 conflict with a non-MEM_IN_STRUCT reference at a fixed address. We must
811 allow QImode aliasing because the ANSI C standard allows character
812 pointers to alias anything. We are assuming that characters are
813 always QImode here. */
815 /* Read dependence: X is read after read in MEM takes place. There can
816 only be a dependence here if both reads are volatile. */
819 read_dependence (mem, x)
823 return MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem);
826 /* True dependence: X is read after store in MEM takes place. */
829 true_dependence (mem, x)
833 /* If X is an unchanging read, then it can't possibly conflict with any
834 non-unchanging store. It may conflict with an unchanging write though,
835 because there may be a single store to this address to initialize it.
836 Just fall through to the code below to resolve the case where we have
837 both an unchanging read and an unchanging write. This won't handle all
838 cases optimally, but the possible performance loss should be
841 mem = canon_rtx (mem);
842 if (RTX_UNCHANGING_P (x) && ! RTX_UNCHANGING_P (mem))
845 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
846 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
847 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
848 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
849 && GET_MODE (mem) != QImode
850 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
851 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
852 && GET_MODE (x) != QImode
853 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
856 /* Anti dependence: X is written after read in MEM takes place. */
859 anti_dependence (mem, x)
863 /* If MEM is an unchanging read, then it can't possibly conflict with
864 the store to X, because there is at most one store to MEM, and it must
865 have occurred somewhere before MEM. */
867 mem = canon_rtx (mem);
868 if (RTX_UNCHANGING_P (mem))
871 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
872 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
873 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
874 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
875 && GET_MODE (mem) != QImode
876 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
877 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
878 && GET_MODE (x) != QImode
879 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
882 /* Output dependence: X is written after store in MEM takes place. */
885 output_dependence (mem, x)
890 mem = canon_rtx (mem);
891 return ((MEM_VOLATILE_P (x) && MEM_VOLATILE_P (mem))
892 || (memrefs_conflict_p (SIZE_FOR_MODE (mem), XEXP (mem, 0),
893 SIZE_FOR_MODE (x), XEXP (x, 0), 0)
894 && ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
895 && GET_MODE (mem) != QImode
896 && ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
897 && ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
898 && GET_MODE (x) != QImode
899 && ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
902 /* Helper functions for instruction scheduling. */
904 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
905 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
906 of dependence that this link represents. */
909 add_dependence (insn, elem, dep_type)
912 enum reg_note dep_type;
916 /* Don't depend an insn on itself. */
920 /* If elem is part of a sequence that must be scheduled together, then
921 make the dependence point to the last insn of the sequence.
922 When HAVE_cc0, it is possible for NOTEs to exist between users and
923 setters of the condition codes, so we must skip past notes here.
924 Otherwise, NOTEs are impossible here. */
926 next = NEXT_INSN (elem);
929 while (next && GET_CODE (next) == NOTE)
930 next = NEXT_INSN (next);
933 if (next && SCHED_GROUP_P (next))
935 /* Notes will never intervene here though, so don't bother checking
937 /* We must reject CODE_LABELs, so that we don't get confused by one
938 that has LABEL_PRESERVE_P set, which is represented by the same
939 bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be
941 while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next))
942 && GET_CODE (NEXT_INSN (next)) != CODE_LABEL)
943 next = NEXT_INSN (next);
945 /* Again, don't depend an insn on itself. */
949 /* Make the dependence to NEXT, the last insn of the group, instead
950 of the original ELEM. */
954 /* Check that we don't already have this dependence. */
955 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
956 if (XEXP (link, 0) == elem)
958 /* If this is a more restrictive type of dependence than the existing
959 one, then change the existing dependence to this type. */
960 if ((int) dep_type < (int) REG_NOTE_KIND (link))
961 PUT_REG_NOTE_KIND (link, dep_type);
964 /* Might want to check one level of transitivity to save conses. */
966 link = rtx_alloc (INSN_LIST);
967 /* Insn dependency, not data dependency. */
968 PUT_REG_NOTE_KIND (link, dep_type);
969 XEXP (link, 0) = elem;
970 XEXP (link, 1) = LOG_LINKS (insn);
971 LOG_LINKS (insn) = link;
974 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
975 of INSN. Abort if not found. */
978 remove_dependence (insn, elem)
985 for (prev = 0, link = LOG_LINKS (insn); link;
986 prev = link, link = XEXP (link, 1))
988 if (XEXP (link, 0) == elem)
991 XEXP (prev, 1) = XEXP (link, 1);
993 LOG_LINKS (insn) = XEXP (link, 1);
1003 #ifndef INSN_SCHEDULING
1005 schedule_insns (dump_file)
1014 /* Computation of memory dependencies. */
1016 /* The *_insns and *_mems are paired lists. Each pending memory operation
1017 will have a pointer to the MEM rtx on one list and a pointer to the
1018 containing insn on the other list in the same place in the list. */
1020 /* We can't use add_dependence like the old code did, because a single insn
1021 may have multiple memory accesses, and hence needs to be on the list
1022 once for each memory access. Add_dependence won't let you add an insn
1023 to a list more than once. */
1025 /* An INSN_LIST containing all insns with pending read operations. */
1026 static rtx pending_read_insns;
1028 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
1029 static rtx pending_read_mems;
1031 /* An INSN_LIST containing all insns with pending write operations. */
1032 static rtx pending_write_insns;
1034 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
1035 static rtx pending_write_mems;
1037 /* Indicates the combined length of the two pending lists. We must prevent
1038 these lists from ever growing too large since the number of dependencies
1039 produced is at least O(N*N), and execution time is at least O(4*N*N), as
1040 a function of the length of these pending lists. */
1042 static int pending_lists_length;
1044 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
1046 static rtx unused_insn_list;
1048 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
1050 static rtx unused_expr_list;
1052 /* The last insn upon which all memory references must depend.
1053 This is an insn which flushed the pending lists, creating a dependency
1054 between it and all previously pending memory references. This creates
1055 a barrier (or a checkpoint) which no memory reference is allowed to cross.
1057 This includes all non constant CALL_INSNs. When we do interprocedural
1058 alias analysis, this restriction can be relaxed.
1059 This may also be an INSN that writes memory if the pending lists grow
1062 static rtx last_pending_memory_flush;
1064 /* The last function call we have seen. All hard regs, and, of course,
1065 the last function call, must depend on this. */
1067 static rtx last_function_call;
1069 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
1070 that does not already cross a call. We create dependencies between each
1071 of those insn and the next call insn, to ensure that they won't cross a call
1072 after scheduling is done. */
1074 static rtx sched_before_next_call;
1076 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
1077 so that insns independent of the last scheduled insn will be preferred
1078 over dependent instructions. */
1080 static rtx last_scheduled_insn;
1082 /* Process an insn's memory dependencies. There are four kinds of
1085 (0) read dependence: read follows read
1086 (1) true dependence: read follows write
1087 (2) anti dependence: write follows read
1088 (3) output dependence: write follows write
1090 We are careful to build only dependencies which actually exist, and
1091 use transitivity to avoid building too many links. */
1093 /* Return the INSN_LIST containing INSN in LIST, or NULL
1094 if LIST does not contain INSN. */
1097 find_insn_list (insn, list)
1103 if (XEXP (list, 0) == insn)
1105 list = XEXP (list, 1);
1110 /* Compute the function units used by INSN. This caches the value
1111 returned by function_units_used. A function unit is encoded as the
1112 unit number if the value is non-negative and the compliment of a
1113 mask if the value is negative. A function unit index is the
1114 non-negative encoding. */
1120 register int unit = INSN_UNIT (insn);
1124 recog_memoized (insn);
1126 /* A USE insn, or something else we don't need to understand.
1127 We can't pass these directly to function_units_used because it will
1128 trigger a fatal error for unrecognizable insns. */
1129 if (INSN_CODE (insn) < 0)
1133 unit = function_units_used (insn);
1134 /* Increment non-negative values so we can cache zero. */
1135 if (unit >= 0) unit++;
1137 /* We only cache 16 bits of the result, so if the value is out of
1138 range, don't cache it. */
1139 if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
1141 || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
1142 INSN_UNIT (insn) = unit;
1144 return (unit > 0 ? unit - 1 : unit);
1147 /* Compute the blockage range for executing INSN on UNIT. This caches
1148 the value returned by the blockage_range_function for the unit.
1149 These values are encoded in an int where the upper half gives the
1150 minimum value and the lower half gives the maximum value. */
1152 __inline static unsigned int
1153 blockage_range (unit, insn)
1157 unsigned int blockage = INSN_BLOCKAGE (insn);
1160 if (UNIT_BLOCKED (blockage) != unit + 1)
1162 range = function_units[unit].blockage_range_function (insn);
1163 /* We only cache the blockage range for one unit and then only if
1165 if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
1166 INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
1169 range = BLOCKAGE_RANGE (blockage);
1174 /* A vector indexed by function unit instance giving the last insn to use
1175 the unit. The value of the function unit instance index for unit U
1176 instance I is (U + I * FUNCTION_UNITS_SIZE). */
1177 static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
1179 /* A vector indexed by function unit instance giving the minimum time when
1180 the unit will unblock based on the maximum blockage cost. */
1181 static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
1183 /* A vector indexed by function unit number giving the number of insns
1184 that remain to use the unit. */
1185 static int unit_n_insns[FUNCTION_UNITS_SIZE];
1187 /* Reset the function unit state to the null state. */
1192 bzero ((char *) unit_last_insn, sizeof (unit_last_insn));
1193 bzero ((char *) unit_tick, sizeof (unit_tick));
1194 bzero ((char *) unit_n_insns, sizeof (unit_n_insns));
1197 /* Record an insn as one that will use the units encoded by UNIT. */
1199 __inline static void
1206 unit_n_insns[unit]++;
1208 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1209 if ((unit & 1) != 0)
1213 /* Return the actual hazard cost of executing INSN on the unit UNIT,
1214 instance INSTANCE at time CLOCK if the previous actual hazard cost
1218 actual_hazard_this_instance (unit, instance, insn, clock, cost)
1219 int unit, instance, clock, cost;
1222 int tick = unit_tick[instance];
1224 if (tick - clock > cost)
1226 /* The scheduler is operating in reverse, so INSN is the executing
1227 insn and the unit's last insn is the candidate insn. We want a
1228 more exact measure of the blockage if we execute INSN at CLOCK
1229 given when we committed the execution of the unit's last insn.
1231 The blockage value is given by either the unit's max blockage
1232 constant, blockage range function, or blockage function. Use
1233 the most exact form for the given unit. */
1235 if (function_units[unit].blockage_range_function)
1237 if (function_units[unit].blockage_function)
1238 tick += (function_units[unit].blockage_function
1239 (insn, unit_last_insn[instance])
1240 - function_units[unit].max_blockage);
1242 tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
1243 - function_units[unit].max_blockage);
1245 if (tick - clock > cost)
1246 cost = tick - clock;
1251 /* Record INSN as having begun execution on the units encoded by UNIT at
1254 __inline static void
1255 schedule_unit (unit, insn, clock)
1263 int instance = unit;
1264 #if MAX_MULTIPLICITY > 1
1265 /* Find the first free instance of the function unit and use that
1266 one. We assume that one is free. */
1267 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
1269 if (! actual_hazard_this_instance (unit, instance, insn, clock, 0))
1271 instance += FUNCTION_UNITS_SIZE;
1274 unit_last_insn[instance] = insn;
1275 unit_tick[instance] = (clock + function_units[unit].max_blockage);
1278 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1279 if ((unit & 1) != 0)
1280 schedule_unit (i, insn, clock);
1283 /* Return the actual hazard cost of executing INSN on the units encoded by
1284 UNIT at time CLOCK if the previous actual hazard cost was COST. */
1287 actual_hazard (unit, insn, clock, cost)
1288 int unit, clock, cost;
1295 /* Find the instance of the function unit with the minimum hazard. */
1296 int instance = unit;
1297 int best_cost = actual_hazard_this_instance (unit, instance, insn,
1301 #if MAX_MULTIPLICITY > 1
1302 if (best_cost > cost)
1304 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
1306 instance += FUNCTION_UNITS_SIZE;
1307 this_cost = actual_hazard_this_instance (unit, instance, insn,
1309 if (this_cost < best_cost)
1311 best_cost = this_cost;
1312 if (this_cost <= cost)
1318 cost = MAX (cost, best_cost);
1321 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1322 if ((unit & 1) != 0)
1323 cost = actual_hazard (i, insn, clock, cost);
1328 /* Return the potential hazard cost of executing an instruction on the
1329 units encoded by UNIT if the previous potential hazard cost was COST.
1330 An insn with a large blockage time is chosen in preference to one
1331 with a smaller time; an insn that uses a unit that is more likely
1332 to be used is chosen in preference to one with a unit that is less
1333 used. We are trying to minimize a subsequent actual hazard. */
1336 potential_hazard (unit, insn, cost)
1341 unsigned int minb, maxb;
1345 minb = maxb = function_units[unit].max_blockage;
1348 if (function_units[unit].blockage_range_function)
1350 maxb = minb = blockage_range (unit, insn);
1351 maxb = MAX_BLOCKAGE_COST (maxb);
1352 minb = MIN_BLOCKAGE_COST (minb);
1357 /* Make the number of instructions left dominate. Make the
1358 minimum delay dominate the maximum delay. If all these
1359 are the same, use the unit number to add an arbitrary
1360 ordering. Other terms can be added. */
1361 ncost = minb * 0x40 + maxb;
1362 ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
1369 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
1370 if ((unit & 1) != 0)
1371 cost = potential_hazard (i, insn, cost);
1376 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
1377 This is the number of virtual cycles taken between instruction issue and
1378 instruction results. */
1381 insn_cost (insn, link, used)
1382 rtx insn, link, used;
1384 register int cost = INSN_COST (insn);
1388 recog_memoized (insn);
1390 /* A USE insn, or something else we don't need to understand.
1391 We can't pass these directly to result_ready_cost because it will
1392 trigger a fatal error for unrecognizable insns. */
1393 if (INSN_CODE (insn) < 0)
1395 INSN_COST (insn) = 1;
1400 cost = result_ready_cost (insn);
1405 INSN_COST (insn) = cost;
1409 /* A USE insn should never require the value used to be computed. This
1410 allows the computation of a function's result and parameter values to
1411 overlap the return and call. */
1412 recog_memoized (used);
1413 if (INSN_CODE (used) < 0)
1414 LINK_COST_FREE (link) = 1;
1416 /* If some dependencies vary the cost, compute the adjustment. Most
1417 commonly, the adjustment is complete: either the cost is ignored
1418 (in the case of an output- or anti-dependence), or the cost is
1419 unchanged. These values are cached in the link as LINK_COST_FREE
1420 and LINK_COST_ZERO. */
1422 if (LINK_COST_FREE (link))
1425 else if (! LINK_COST_ZERO (link))
1429 ADJUST_COST (used, link, insn, ncost);
1431 LINK_COST_FREE (link) = ncost = 1;
1433 LINK_COST_ZERO (link) = 1;
1440 /* Compute the priority number for INSN. */
1446 if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1450 int this_priority = INSN_PRIORITY (insn);
1453 if (this_priority > 0)
1454 return this_priority;
1458 /* Nonzero if these insns must be scheduled together. */
1459 if (SCHED_GROUP_P (insn))
1462 while (SCHED_GROUP_P (prev))
1464 prev = PREV_INSN (prev);
1465 INSN_REF_COUNT (prev) += 1;
1469 for (prev = LOG_LINKS (insn); prev; prev = XEXP (prev, 1))
1471 rtx x = XEXP (prev, 0);
1473 /* A dependence pointing to a note or deleted insn is always
1474 obsolete, because sched_analyze_insn will have created any
1475 necessary new dependences which replace it. Notes and deleted
1476 insns can be created when instructions are deleted by insn
1477 splitting, or by register allocation. */
1478 if (GET_CODE (x) == NOTE || INSN_DELETED_P (x))
1480 remove_dependence (insn, x);
1484 /* Clear the link cost adjustment bits. */
1485 LINK_COST_FREE (prev) = 0;
1487 LINK_COST_ZERO (prev) = 0;
1490 /* This priority calculation was chosen because it results in the
1491 least instruction movement, and does not hurt the performance
1492 of the resulting code compared to the old algorithm.
1493 This makes the sched algorithm more stable, which results
1494 in better code, because there is less register pressure,
1495 cross jumping is more likely to work, and debugging is easier.
1497 When all instructions have a latency of 1, there is no need to
1498 move any instructions. Subtracting one here ensures that in such
1499 cases all instructions will end up with a priority of one, and
1500 hence no scheduling will be done.
1502 The original code did not subtract the one, and added the
1503 insn_cost of the current instruction to its priority (e.g.
1504 move the insn_cost call down to the end). */
1506 prev_priority = priority (x) + insn_cost (x, prev, insn) - 1;
1508 if (prev_priority > max_priority)
1509 max_priority = prev_priority;
1510 INSN_REF_COUNT (x) += 1;
1513 prepare_unit (insn_unit (insn));
1514 INSN_PRIORITY (insn) = max_priority;
1515 return INSN_PRIORITY (insn);
1520 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
1521 them to the unused_*_list variables, so that they can be reused. */
1524 free_pending_lists ()
1526 register rtx link, prev_link;
1528 if (pending_read_insns)
1530 prev_link = pending_read_insns;
1531 link = XEXP (prev_link, 1);
1536 link = XEXP (link, 1);
1539 XEXP (prev_link, 1) = unused_insn_list;
1540 unused_insn_list = pending_read_insns;
1541 pending_read_insns = 0;
1544 if (pending_write_insns)
1546 prev_link = pending_write_insns;
1547 link = XEXP (prev_link, 1);
1552 link = XEXP (link, 1);
1555 XEXP (prev_link, 1) = unused_insn_list;
1556 unused_insn_list = pending_write_insns;
1557 pending_write_insns = 0;
1560 if (pending_read_mems)
1562 prev_link = pending_read_mems;
1563 link = XEXP (prev_link, 1);
1568 link = XEXP (link, 1);
1571 XEXP (prev_link, 1) = unused_expr_list;
1572 unused_expr_list = pending_read_mems;
1573 pending_read_mems = 0;
1576 if (pending_write_mems)
1578 prev_link = pending_write_mems;
1579 link = XEXP (prev_link, 1);
1584 link = XEXP (link, 1);
1587 XEXP (prev_link, 1) = unused_expr_list;
1588 unused_expr_list = pending_write_mems;
1589 pending_write_mems = 0;
1593 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
1594 The MEM is a memory reference contained within INSN, which we are saving
1595 so that we can do memory aliasing on it. */
1598 add_insn_mem_dependence (insn_list, mem_list, insn, mem)
1599 rtx *insn_list, *mem_list, insn, mem;
1603 if (unused_insn_list)
1605 link = unused_insn_list;
1606 unused_insn_list = XEXP (link, 1);
1609 link = rtx_alloc (INSN_LIST);
1610 XEXP (link, 0) = insn;
1611 XEXP (link, 1) = *insn_list;
1614 if (unused_expr_list)
1616 link = unused_expr_list;
1617 unused_expr_list = XEXP (link, 1);
1620 link = rtx_alloc (EXPR_LIST);
1621 XEXP (link, 0) = mem;
1622 XEXP (link, 1) = *mem_list;
1625 pending_lists_length++;
1628 /* Make a dependency between every memory reference on the pending lists
1629 and INSN, thus flushing the pending lists. */
1632 flush_pending_lists (insn)
1637 while (pending_read_insns)
1639 add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI);
1641 link = pending_read_insns;
1642 pending_read_insns = XEXP (pending_read_insns, 1);
1643 XEXP (link, 1) = unused_insn_list;
1644 unused_insn_list = link;
1646 link = pending_read_mems;
1647 pending_read_mems = XEXP (pending_read_mems, 1);
1648 XEXP (link, 1) = unused_expr_list;
1649 unused_expr_list = link;
1651 while (pending_write_insns)
1653 add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI);
1655 link = pending_write_insns;
1656 pending_write_insns = XEXP (pending_write_insns, 1);
1657 XEXP (link, 1) = unused_insn_list;
1658 unused_insn_list = link;
1660 link = pending_write_mems;
1661 pending_write_mems = XEXP (pending_write_mems, 1);
1662 XEXP (link, 1) = unused_expr_list;
1663 unused_expr_list = link;
1665 pending_lists_length = 0;
1667 if (last_pending_memory_flush)
1668 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1670 last_pending_memory_flush = insn;
1673 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
1674 by the write to the destination of X, and reads of everything mentioned. */
1677 sched_analyze_1 (x, insn)
1682 register rtx dest = SET_DEST (x);
1687 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
1688 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
1690 if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
1692 /* The second and third arguments are values read by this insn. */
1693 sched_analyze_2 (XEXP (dest, 1), insn);
1694 sched_analyze_2 (XEXP (dest, 2), insn);
1696 dest = SUBREG_REG (dest);
1699 if (GET_CODE (dest) == REG)
1703 regno = REGNO (dest);
1705 /* A hard reg in a wide mode may really be multiple registers.
1706 If so, mark all of them just like the first. */
1707 if (regno < FIRST_PSEUDO_REGISTER)
1709 i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
1714 for (u = reg_last_uses[regno+i]; u; u = XEXP (u, 1))
1715 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1716 reg_last_uses[regno + i] = 0;
1717 if (reg_last_sets[regno + i])
1718 add_dependence (insn, reg_last_sets[regno + i],
1720 reg_pending_sets[(regno + i) / REGSET_ELT_BITS]
1721 |= (REGSET_ELT_TYPE) 1 << ((regno + i) % REGSET_ELT_BITS);
1722 if ((call_used_regs[i] || global_regs[i])
1723 && last_function_call)
1724 /* Function calls clobber all call_used regs. */
1725 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1732 for (u = reg_last_uses[regno]; u; u = XEXP (u, 1))
1733 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1734 reg_last_uses[regno] = 0;
1735 if (reg_last_sets[regno])
1736 add_dependence (insn, reg_last_sets[regno], REG_DEP_OUTPUT);
1737 reg_pending_sets[regno / REGSET_ELT_BITS]
1738 |= (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
1740 /* Pseudos that are REG_EQUIV to something may be replaced
1741 by that during reloading. We need only add dependencies for
1742 the address in the REG_EQUIV note. */
1743 if (! reload_completed
1744 && reg_known_equiv_p[regno]
1745 && GET_CODE (reg_known_value[regno]) == MEM)
1746 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
1748 /* Don't let it cross a call after scheduling if it doesn't
1749 already cross one. */
1750 if (reg_n_calls_crossed[regno] == 0 && last_function_call)
1751 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1754 else if (GET_CODE (dest) == MEM)
1756 /* Writing memory. */
1758 if (pending_lists_length > 32)
1760 /* Flush all pending reads and writes to prevent the pending lists
1761 from getting any larger. Insn scheduling runs too slowly when
1762 these lists get long. The number 32 was chosen because it
1763 seems like a reasonable number. When compiling GCC with itself,
1764 this flush occurs 8 times for sparc, and 10 times for m88k using
1766 flush_pending_lists (insn);
1770 rtx pending, pending_mem;
1772 pending = pending_read_insns;
1773 pending_mem = pending_read_mems;
1776 /* If a dependency already exists, don't create a new one. */
1777 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1778 if (anti_dependence (XEXP (pending_mem, 0), dest))
1779 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
1781 pending = XEXP (pending, 1);
1782 pending_mem = XEXP (pending_mem, 1);
1785 pending = pending_write_insns;
1786 pending_mem = pending_write_mems;
1789 /* If a dependency already exists, don't create a new one. */
1790 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1791 if (output_dependence (XEXP (pending_mem, 0), dest))
1792 add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT);
1794 pending = XEXP (pending, 1);
1795 pending_mem = XEXP (pending_mem, 1);
1798 if (last_pending_memory_flush)
1799 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1801 add_insn_mem_dependence (&pending_write_insns, &pending_write_mems,
1804 sched_analyze_2 (XEXP (dest, 0), insn);
1807 /* Analyze reads. */
1808 if (GET_CODE (x) == SET)
1809 sched_analyze_2 (SET_SRC (x), insn);
1812 /* Analyze the uses of memory and registers in rtx X in INSN. */
1815 sched_analyze_2 (x, insn)
1821 register enum rtx_code code;
1827 code = GET_CODE (x);
1836 /* Ignore constants. Note that we must handle CONST_DOUBLE here
1837 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
1838 this does not mean that this insn is using cc0. */
1846 /* There may be a note before this insn now, but all notes will
1847 be removed before we actually try to schedule the insns, so
1848 it won't cause a problem later. We must avoid it here though. */
1850 /* User of CC0 depends on immediately preceding insn. */
1851 SCHED_GROUP_P (insn) = 1;
1853 /* Make a copy of all dependencies on the immediately previous insn,
1854 and add to this insn. This is so that all the dependencies will
1855 apply to the group. Remove an explicit dependence on this insn
1856 as SCHED_GROUP_P now represents it. */
1858 prev = PREV_INSN (insn);
1859 while (GET_CODE (prev) == NOTE)
1860 prev = PREV_INSN (prev);
1862 if (find_insn_list (prev, LOG_LINKS (insn)))
1863 remove_dependence (insn, prev);
1865 for (link = LOG_LINKS (prev); link; link = XEXP (link, 1))
1866 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
1874 int regno = REGNO (x);
1875 if (regno < FIRST_PSEUDO_REGISTER)
1879 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
1882 reg_last_uses[regno + i]
1883 = gen_rtx (INSN_LIST, VOIDmode,
1884 insn, reg_last_uses[regno + i]);
1885 if (reg_last_sets[regno + i])
1886 add_dependence (insn, reg_last_sets[regno + i], 0);
1887 if ((call_used_regs[regno + i] || global_regs[regno + i])
1888 && last_function_call)
1889 /* Function calls clobber all call_used regs. */
1890 add_dependence (insn, last_function_call, REG_DEP_ANTI);
1895 reg_last_uses[regno]
1896 = gen_rtx (INSN_LIST, VOIDmode, insn, reg_last_uses[regno]);
1897 if (reg_last_sets[regno])
1898 add_dependence (insn, reg_last_sets[regno], 0);
1900 /* Pseudos that are REG_EQUIV to something may be replaced
1901 by that during reloading. We need only add dependencies for
1902 the address in the REG_EQUIV note. */
1903 if (! reload_completed
1904 && reg_known_equiv_p[regno]
1905 && GET_CODE (reg_known_value[regno]) == MEM)
1906 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
1908 /* If the register does not already cross any calls, then add this
1909 insn to the sched_before_next_call list so that it will still
1910 not cross calls after scheduling. */
1911 if (reg_n_calls_crossed[regno] == 0)
1912 add_dependence (sched_before_next_call, insn, REG_DEP_ANTI);
1919 /* Reading memory. */
1921 rtx pending, pending_mem;
1923 pending = pending_read_insns;
1924 pending_mem = pending_read_mems;
1927 /* If a dependency already exists, don't create a new one. */
1928 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1929 if (read_dependence (XEXP (pending_mem, 0), x))
1930 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
1932 pending = XEXP (pending, 1);
1933 pending_mem = XEXP (pending_mem, 1);
1936 pending = pending_write_insns;
1937 pending_mem = pending_write_mems;
1940 /* If a dependency already exists, don't create a new one. */
1941 if (! find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
1942 if (true_dependence (XEXP (pending_mem, 0), x))
1943 add_dependence (insn, XEXP (pending, 0), 0);
1945 pending = XEXP (pending, 1);
1946 pending_mem = XEXP (pending_mem, 1);
1948 if (last_pending_memory_flush)
1949 add_dependence (insn, last_pending_memory_flush, REG_DEP_ANTI);
1951 /* Always add these dependencies to pending_reads, since
1952 this insn may be followed by a write. */
1953 add_insn_mem_dependence (&pending_read_insns, &pending_read_mems,
1956 /* Take advantage of tail recursion here. */
1957 sched_analyze_2 (XEXP (x, 0), insn);
1963 case UNSPEC_VOLATILE:
1968 /* Traditional and volatile asm instructions must be considered to use
1969 and clobber all hard registers, all pseudo-registers and all of
1970 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
1972 Consider for instance a volatile asm that changes the fpu rounding
1973 mode. An insn should not be moved across this even if it only uses
1974 pseudo-regs because it might give an incorrectly rounded result. */
1975 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
1977 int max_reg = max_reg_num ();
1978 for (i = 0; i < max_reg; i++)
1980 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
1981 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
1982 reg_last_uses[i] = 0;
1983 if (reg_last_sets[i])
1984 add_dependence (insn, reg_last_sets[i], 0);
1986 reg_pending_sets_all = 1;
1988 flush_pending_lists (insn);
1991 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
1992 We can not just fall through here since then we would be confused
1993 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
1994 traditional asms unlike their normal usage. */
1996 if (code == ASM_OPERANDS)
1998 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
1999 sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn);
2009 /* These both read and modify the result. We must handle them as writes
2010 to get proper dependencies for following instructions. We must handle
2011 them as reads to get proper dependencies from this to previous
2012 instructions. Thus we need to pass them to both sched_analyze_1
2013 and sched_analyze_2. We must call sched_analyze_2 first in order
2014 to get the proper antecedent for the read. */
2015 sched_analyze_2 (XEXP (x, 0), insn);
2016 sched_analyze_1 (x, insn);
2020 /* Other cases: walk the insn. */
2021 fmt = GET_RTX_FORMAT (code);
2022 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2025 sched_analyze_2 (XEXP (x, i), insn);
2026 else if (fmt[i] == 'E')
2027 for (j = 0; j < XVECLEN (x, i); j++)
2028 sched_analyze_2 (XVECEXP (x, i, j), insn);
2032 /* Analyze an INSN with pattern X to find all dependencies. */
2035 sched_analyze_insn (x, insn, loop_notes)
2039 register RTX_CODE code = GET_CODE (x);
2041 int maxreg = max_reg_num ();
2044 if (code == SET || code == CLOBBER)
2045 sched_analyze_1 (x, insn);
2046 else if (code == PARALLEL)
2049 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2051 code = GET_CODE (XVECEXP (x, 0, i));
2052 if (code == SET || code == CLOBBER)
2053 sched_analyze_1 (XVECEXP (x, 0, i), insn);
2055 sched_analyze_2 (XVECEXP (x, 0, i), insn);
2059 sched_analyze_2 (x, insn);
2061 /* Mark registers CLOBBERED or used by called function. */
2062 if (GET_CODE (insn) == CALL_INSN)
2063 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
2065 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
2066 sched_analyze_1 (XEXP (link, 0), insn);
2068 sched_analyze_2 (XEXP (link, 0), insn);
2071 /* If there is a LOOP_{BEG,END} note in the middle of a basic block, then
2072 we must be sure that no instructions are scheduled across it.
2073 Otherwise, the reg_n_refs info (which depends on loop_depth) would
2074 become incorrect. */
2078 int max_reg = max_reg_num ();
2081 for (i = 0; i < max_reg; i++)
2084 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
2085 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
2086 reg_last_uses[i] = 0;
2087 if (reg_last_sets[i])
2088 add_dependence (insn, reg_last_sets[i], 0);
2090 reg_pending_sets_all = 1;
2092 flush_pending_lists (insn);
2095 while (XEXP (link, 1))
2096 link = XEXP (link, 1);
2097 XEXP (link, 1) = REG_NOTES (insn);
2098 REG_NOTES (insn) = loop_notes;
2101 /* After reload, it is possible for an instruction to have a REG_DEAD note
2102 for a register that actually dies a few instructions earlier. For
2103 example, this can happen with SECONDARY_MEMORY_NEEDED reloads.
2104 In this case, we must consider the insn to use the register mentioned
2105 in the REG_DEAD note. Otherwise, we may accidentally move this insn
2106 after another insn that sets the register, thus getting obviously invalid
2107 rtl. This confuses reorg which believes that REG_DEAD notes are still
2110 ??? We would get better code if we fixed reload to put the REG_DEAD
2111 notes in the right places, but that may not be worth the effort. */
2113 if (reload_completed)
2117 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2118 if (REG_NOTE_KIND (note) == REG_DEAD)
2119 sched_analyze_2 (XEXP (note, 0), insn);
2122 for (i = 0; i < regset_size; i++)
2124 REGSET_ELT_TYPE sets = reg_pending_sets[i];
2128 for (bit = 0; bit < REGSET_ELT_BITS; bit++)
2129 if (sets & ((REGSET_ELT_TYPE) 1 << bit))
2130 reg_last_sets[i * REGSET_ELT_BITS + bit] = insn;
2131 reg_pending_sets[i] = 0;
2134 if (reg_pending_sets_all)
2136 for (i = 0; i < maxreg; i++)
2137 reg_last_sets[i] = insn;
2138 reg_pending_sets_all = 0;
2141 /* Handle function calls and function returns created by the epilogue
2143 if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
2148 /* When scheduling instructions, we make sure calls don't lose their
2149 accompanying USE insns by depending them one on another in order.
2151 Also, we must do the same thing for returns created by the epilogue
2152 threading code. Note this code works only in this special case,
2153 because other passes make no guarantee that they will never emit
2154 an instruction between a USE and a RETURN. There is such a guarantee
2155 for USE instructions immediately before a call. */
2157 prev_dep_insn = insn;
2158 dep_insn = PREV_INSN (insn);
2159 while (GET_CODE (dep_insn) == INSN
2160 && GET_CODE (PATTERN (dep_insn)) == USE
2161 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG)
2163 SCHED_GROUP_P (prev_dep_insn) = 1;
2165 /* Make a copy of all dependencies on dep_insn, and add to insn.
2166 This is so that all of the dependencies will apply to the
2169 for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1))
2170 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
2172 prev_dep_insn = dep_insn;
2173 dep_insn = PREV_INSN (dep_insn);
2178 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
2179 for every dependency. */
2182 sched_analyze (head, tail)
2186 register int n_insns = 0;
2188 register int luid = 0;
2191 for (insn = head; ; insn = NEXT_INSN (insn))
2193 INSN_LUID (insn) = luid++;
2195 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
2197 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
2201 else if (GET_CODE (insn) == CALL_INSN)
2206 /* Any instruction using a hard register which may get clobbered
2207 by a call needs to be marked as dependent on this call.
2208 This prevents a use of a hard return reg from being moved
2209 past a void call (i.e. it does not explicitly set the hard
2212 /* If this call is followed by a NOTE_INSN_SETJMP, then assume that
2213 all registers, not just hard registers, may be clobbered by this
2216 /* Insn, being a CALL_INSN, magically depends on
2217 `last_function_call' already. */
2219 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE
2220 && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP)
2222 int max_reg = max_reg_num ();
2223 for (i = 0; i < max_reg; i++)
2225 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
2226 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
2227 reg_last_uses[i] = 0;
2228 if (reg_last_sets[i])
2229 add_dependence (insn, reg_last_sets[i], 0);
2231 reg_pending_sets_all = 1;
2233 /* Add a fake REG_NOTE which we will later convert
2234 back into a NOTE_INSN_SETJMP note. */
2235 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_DEAD,
2236 GEN_INT (NOTE_INSN_SETJMP),
2241 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2242 if (call_used_regs[i] || global_regs[i])
2244 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
2245 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
2246 reg_last_uses[i] = 0;
2247 if (reg_last_sets[i])
2248 add_dependence (insn, reg_last_sets[i], REG_DEP_ANTI);
2249 reg_pending_sets[i / REGSET_ELT_BITS]
2250 |= (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS);
2254 /* For each insn which shouldn't cross a call, add a dependence
2255 between that insn and this call insn. */
2256 x = LOG_LINKS (sched_before_next_call);
2259 add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI);
2262 LOG_LINKS (sched_before_next_call) = 0;
2264 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
2267 /* We don't need to flush memory for a function call which does
2268 not involve memory. */
2269 if (! CONST_CALL_P (insn))
2271 /* In the absence of interprocedural alias analysis,
2272 we must flush all pending reads and writes, and
2273 start new dependencies starting from here. */
2274 flush_pending_lists (insn);
2277 /* Depend this function call (actually, the user of this
2278 function call) on all hard register clobberage. */
2279 last_function_call = insn;
2282 else if (GET_CODE (insn) == NOTE
2283 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG
2284 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END))
2285 loop_notes = gen_rtx (EXPR_LIST, REG_DEAD,
2286 GEN_INT (NOTE_LINE_NUMBER (insn)), loop_notes);
2293 /* Called when we see a set of a register. If death is true, then we are
2294 scanning backwards. Mark that register as unborn. If nobody says
2295 otherwise, that is how things will remain. If death is false, then we
2296 are scanning forwards. Mark that register as being born. */
2299 sched_note_set (b, x, death)
2305 register rtx reg = SET_DEST (x);
2311 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART
2312 || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT)
2314 /* Must treat modification of just one hardware register of a multi-reg
2315 value or just a byte field of a register exactly the same way that
2316 mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg
2317 does not kill the entire register. */
2318 if (GET_CODE (reg) != SUBREG
2319 || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg))
2322 reg = SUBREG_REG (reg);
2325 if (GET_CODE (reg) != REG)
2328 /* Global registers are always live, so the code below does not apply
2331 regno = REGNO (reg);
2332 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
2334 register int offset = regno / REGSET_ELT_BITS;
2335 register REGSET_ELT_TYPE bit
2336 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
2340 /* If we only set part of the register, then this set does not
2345 /* Try killing this register. */
2346 if (regno < FIRST_PSEUDO_REGISTER)
2348 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2351 offset = (regno + j) / REGSET_ELT_BITS;
2352 bit = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS);
2354 bb_live_regs[offset] &= ~bit;
2355 bb_dead_regs[offset] |= bit;
2360 bb_live_regs[offset] &= ~bit;
2361 bb_dead_regs[offset] |= bit;
2366 /* Make the register live again. */
2367 if (regno < FIRST_PSEUDO_REGISTER)
2369 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2372 offset = (regno + j) / REGSET_ELT_BITS;
2373 bit = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS);
2375 bb_live_regs[offset] |= bit;
2376 bb_dead_regs[offset] &= ~bit;
2381 bb_live_regs[offset] |= bit;
2382 bb_dead_regs[offset] &= ~bit;
2388 /* Macros and functions for keeping the priority queue sorted, and
2389 dealing with queueing and dequeueing of instructions. */
2391 #define SCHED_SORT(READY, NEW_READY, OLD_READY) \
2392 do { if ((NEW_READY) - (OLD_READY) == 1) \
2393 swap_sort (READY, NEW_READY); \
2394 else if ((NEW_READY) - (OLD_READY) > 1) \
2395 qsort (READY, NEW_READY, sizeof (rtx), rank_for_schedule); } \
2398 /* Returns a positive value if y is preferred; returns a negative value if
2399 x is preferred. Should never return 0, since that will make the sort
2403 rank_for_schedule (x, y)
2409 int tmp_class, tmp2_class;
2412 /* Choose the instruction with the highest priority, if different. */
2413 if (value = INSN_PRIORITY (tmp) - INSN_PRIORITY (tmp2))
2416 if (last_scheduled_insn)
2418 /* Classify the instructions into three classes:
2419 1) Data dependent on last schedule insn.
2420 2) Anti/Output dependent on last scheduled insn.
2421 3) Independent of last scheduled insn, or has latency of one.
2422 Choose the insn from the highest numbered class if different. */
2423 link = find_insn_list (tmp, LOG_LINKS (last_scheduled_insn));
2424 if (link == 0 || insn_cost (tmp, link, last_scheduled_insn) == 1)
2426 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
2431 link = find_insn_list (tmp2, LOG_LINKS (last_scheduled_insn));
2432 if (link == 0 || insn_cost (tmp2, link, last_scheduled_insn) == 1)
2434 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
2439 if (value = tmp_class - tmp2_class)
2443 /* If insns are equally good, sort by INSN_LUID (original insn order),
2444 so that we make the sort stable. This minimizes instruction movement,
2445 thus minimizing sched's effect on debugging and cross-jumping. */
2446 return INSN_LUID (tmp) - INSN_LUID (tmp2);
2449 /* Resort the array A in which only element at index N may be out of order. */
2451 __inline static void
2459 while (i >= 0 && rank_for_schedule (a+i, &insn) >= 0)
2467 static int max_priority;
2469 /* Add INSN to the insn queue so that it fires at least N_CYCLES
2470 before the currently executing insn. */
2472 __inline static void
2473 queue_insn (insn, n_cycles)
2477 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
2478 NEXT_INSN (insn) = insn_queue[next_q];
2479 insn_queue[next_q] = insn;
2483 /* Return nonzero if PAT is the pattern of an insn which makes a
2487 birthing_insn_p (pat)
2492 if (reload_completed == 1)
2495 if (GET_CODE (pat) == SET
2496 && GET_CODE (SET_DEST (pat)) == REG)
2498 rtx dest = SET_DEST (pat);
2499 int i = REGNO (dest);
2500 int offset = i / REGSET_ELT_BITS;
2501 REGSET_ELT_TYPE bit = (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS);
2503 /* It would be more accurate to use refers_to_regno_p or
2504 reg_mentioned_p to determine when the dest is not live before this
2507 if (bb_live_regs[offset] & bit)
2508 return (reg_n_sets[i] == 1);
2512 if (GET_CODE (pat) == PARALLEL)
2514 for (j = 0; j < XVECLEN (pat, 0); j++)
2515 if (birthing_insn_p (XVECEXP (pat, 0, j)))
2521 /* PREV is an insn that is ready to execute. Adjust its priority if that
2522 will help shorten register lifetimes. */
2524 __inline static void
2525 adjust_priority (prev)
2528 /* Trying to shorten register lives after reload has completed
2529 is useless and wrong. It gives inaccurate schedules. */
2530 if (reload_completed == 0)
2535 /* ??? This code has no effect, because REG_DEAD notes are removed
2536 before we ever get here. */
2537 for (note = REG_NOTES (prev); note; note = XEXP (note, 1))
2538 if (REG_NOTE_KIND (note) == REG_DEAD)
2541 /* Defer scheduling insns which kill registers, since that
2542 shortens register lives. Prefer scheduling insns which
2543 make registers live for the same reason. */
2547 INSN_PRIORITY (prev) >>= 3;
2550 INSN_PRIORITY (prev) >>= 2;
2554 INSN_PRIORITY (prev) >>= 1;
2557 if (birthing_insn_p (PATTERN (prev)))
2559 int max = max_priority;
2561 if (max > INSN_PRIORITY (prev))
2562 INSN_PRIORITY (prev) = max;
2566 #ifdef ADJUST_PRIORITY
2567 ADJUST_PRIORITY (prev);
2572 /* INSN is the "currently executing insn". Launch each insn which was
2573 waiting on INSN (in the backwards dataflow sense). READY is a
2574 vector of insns which are ready to fire. N_READY is the number of
2575 elements in READY. CLOCK is the current virtual cycle. */
2578 schedule_insn (insn, ready, n_ready, clock)
2585 int new_ready = n_ready;
2587 if (MAX_BLOCKAGE > 1)
2588 schedule_unit (insn_unit (insn), insn, clock);
2590 if (LOG_LINKS (insn) == 0)
2593 /* This is used by the function adjust_priority above. */
2595 max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn));
2597 max_priority = INSN_PRIORITY (insn);
2599 for (link = LOG_LINKS (insn); link != 0; link = XEXP (link, 1))
2601 rtx prev = XEXP (link, 0);
2602 int cost = insn_cost (prev, link, insn);
2604 if ((INSN_REF_COUNT (prev) -= 1) != 0)
2606 /* We satisfied one requirement to fire PREV. Record the earliest
2607 time when PREV can fire. No need to do this if the cost is 1,
2608 because PREV can fire no sooner than the next cycle. */
2610 INSN_TICK (prev) = MAX (INSN_TICK (prev), clock + cost);
2614 /* We satisfied the last requirement to fire PREV. Ensure that all
2615 timing requirements are satisfied. */
2616 if (INSN_TICK (prev) - clock > cost)
2617 cost = INSN_TICK (prev) - clock;
2619 /* Adjust the priority of PREV and either put it on the ready
2620 list or queue it. */
2621 adjust_priority (prev);
2623 ready[new_ready++] = prev;
2625 queue_insn (prev, cost);
2632 /* Given N_READY insns in the ready list READY at time CLOCK, queue
2633 those that are blocked due to function unit hazards and rearrange
2634 the remaining ones to minimize subsequent function unit hazards. */
2637 schedule_select (ready, n_ready, clock, file)
2642 int pri = INSN_PRIORITY (ready[0]);
2643 int i, j, k, q, cost, best_cost, best_insn = 0, new_ready = n_ready;
2646 /* Work down the ready list in groups of instructions with the same
2647 priority value. Queue insns in the group that are blocked and
2648 select among those that remain for the one with the largest
2649 potential hazard. */
2650 for (i = 0; i < n_ready; i = j)
2653 for (j = i + 1; j < n_ready; j++)
2654 if ((pri = INSN_PRIORITY (ready[j])) != opri)
2657 /* Queue insns in the group that are blocked. */
2658 for (k = i, q = 0; k < j; k++)
2661 if ((cost = actual_hazard (insn_unit (insn), insn, clock, 0)) != 0)
2665 queue_insn (insn, cost);
2667 fprintf (file, "\n;; blocking insn %d for %d cycles",
2668 INSN_UID (insn), cost);
2673 /* Check the next group if all insns were queued. */
2677 /* If more than one remains, select the first one with the largest
2678 potential hazard. */
2679 else if (j - i - q > 1)
2682 for (k = i; k < j; k++)
2684 if ((insn = ready[k]) == 0)
2686 if ((cost = potential_hazard (insn_unit (insn), insn, 0))
2694 /* We have found a suitable insn to schedule. */
2698 /* Move the best insn to be front of the ready list. */
2703 fprintf (file, ", now");
2704 for (i = 0; i < n_ready; i++)
2706 fprintf (file, " %d", INSN_UID (ready[i]));
2707 fprintf (file, "\n;; insn %d has a greater potential hazard",
2708 INSN_UID (ready[best_insn]));
2710 for (i = best_insn; i > 0; i--)
2713 ready[i-1] = ready[i];
2718 /* Compact the ready list. */
2719 if (new_ready < n_ready)
2720 for (i = j = 0; i < n_ready; i++)
2722 ready[j++] = ready[i];
2727 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
2731 create_reg_dead_note (reg, insn)
2736 /* The number of registers killed after scheduling must be the same as the
2737 number of registers killed before scheduling. The number of REG_DEAD
2738 notes may not be conserved, i.e. two SImode hard register REG_DEAD notes
2739 might become one DImode hard register REG_DEAD note, but the number of
2740 registers killed will be conserved.
2742 We carefully remove REG_DEAD notes from the dead_notes list, so that
2743 there will be none left at the end. If we run out early, then there
2744 is a bug somewhere in flow, combine and/or sched. */
2746 if (dead_notes == 0)
2751 link = rtx_alloc (EXPR_LIST);
2752 PUT_REG_NOTE_KIND (link, REG_DEAD);
2757 /* Number of regs killed by REG. */
2758 int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1
2759 : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)));
2760 /* Number of regs killed by REG_DEAD notes taken off the list. */
2764 reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
2765 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
2766 GET_MODE (XEXP (link, 0))));
2767 while (reg_note_regs < regs_killed)
2769 link = XEXP (link, 1);
2770 reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
2771 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
2772 GET_MODE (XEXP (link, 0))));
2774 dead_notes = XEXP (link, 1);
2776 /* If we took too many regs kills off, put the extra ones back. */
2777 while (reg_note_regs > regs_killed)
2779 rtx temp_reg, temp_link;
2781 temp_reg = gen_rtx (REG, word_mode, 0);
2782 temp_link = rtx_alloc (EXPR_LIST);
2783 PUT_REG_NOTE_KIND (temp_link, REG_DEAD);
2784 XEXP (temp_link, 0) = temp_reg;
2785 XEXP (temp_link, 1) = dead_notes;
2786 dead_notes = temp_link;
2791 XEXP (link, 0) = reg;
2792 XEXP (link, 1) = REG_NOTES (insn);
2793 REG_NOTES (insn) = link;
2796 /* Subroutine on attach_deaths_insn--handles the recursive search
2797 through INSN. If SET_P is true, then x is being modified by the insn. */
2800 attach_deaths (x, insn, set_p)
2807 register enum rtx_code code;
2813 code = GET_CODE (x);
2825 /* Get rid of the easy cases first. */
2830 /* If the register dies in this insn, queue that note, and mark
2831 this register as needing to die. */
2832 /* This code is very similar to mark_used_1 (if set_p is false)
2833 and mark_set_1 (if set_p is true) in flow.c. */
2835 register int regno = REGNO (x);
2836 register int offset = regno / REGSET_ELT_BITS;
2837 register REGSET_ELT_TYPE bit
2838 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
2839 REGSET_ELT_TYPE all_needed = (old_live_regs[offset] & bit);
2840 REGSET_ELT_TYPE some_needed = (old_live_regs[offset] & bit);
2845 if (regno < FIRST_PSEUDO_REGISTER)
2849 n = HARD_REGNO_NREGS (regno, GET_MODE (x));
2852 some_needed |= (old_live_regs[(regno + n) / REGSET_ELT_BITS]
2853 & ((REGSET_ELT_TYPE) 1
2854 << ((regno + n) % REGSET_ELT_BITS)));
2855 all_needed &= (old_live_regs[(regno + n) / REGSET_ELT_BITS]
2856 & ((REGSET_ELT_TYPE) 1
2857 << ((regno + n) % REGSET_ELT_BITS)));
2861 /* If it wasn't live before we started, then add a REG_DEAD note.
2862 We must check the previous lifetime info not the current info,
2863 because we may have to execute this code several times, e.g.
2864 once for a clobber (which doesn't add a note) and later
2865 for a use (which does add a note).
2867 Always make the register live. We must do this even if it was
2868 live before, because this may be an insn which sets and uses
2869 the same register, in which case the register has already been
2870 killed, so we must make it live again.
2872 Global registers are always live, and should never have a REG_DEAD
2873 note added for them, so none of the code below applies to them. */
2875 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
2877 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2878 STACK_POINTER_REGNUM, since these are always considered to be
2879 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2880 if (regno != FRAME_POINTER_REGNUM
2881 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2882 && ! (regno == HARD_FRAME_POINTER_REGNUM)
2884 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2885 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
2887 && regno != STACK_POINTER_REGNUM)
2889 /* ??? It is perhaps a dead_or_set_p bug that it does
2890 not check for REG_UNUSED notes itself. This is necessary
2891 for the case where the SET_DEST is a subreg of regno, as
2892 dead_or_set_p handles subregs specially. */
2893 if (! all_needed && ! dead_or_set_p (insn, x)
2894 && ! find_reg_note (insn, REG_UNUSED, x))
2896 /* Check for the case where the register dying partially
2897 overlaps the register set by this insn. */
2898 if (regno < FIRST_PSEUDO_REGISTER
2899 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
2901 int n = HARD_REGNO_NREGS (regno, GET_MODE (x));
2903 some_needed |= dead_or_set_regno_p (insn, regno + n);
2906 /* If none of the words in X is needed, make a REG_DEAD
2907 note. Otherwise, we must make partial REG_DEAD
2910 create_reg_dead_note (x, insn);
2915 /* Don't make a REG_DEAD note for a part of a
2916 register that is set in the insn. */
2917 for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1;
2919 if ((old_live_regs[(regno + i) / REGSET_ELT_BITS]
2920 & ((REGSET_ELT_TYPE) 1
2921 << ((regno +i) % REGSET_ELT_BITS))) == 0
2922 && ! dead_or_set_regno_p (insn, regno + i))
2923 create_reg_dead_note (gen_rtx (REG,
2924 reg_raw_mode[regno + i],
2931 if (regno < FIRST_PSEUDO_REGISTER)
2933 int j = HARD_REGNO_NREGS (regno, GET_MODE (x));
2936 offset = (regno + j) / REGSET_ELT_BITS;
2938 = (REGSET_ELT_TYPE) 1 << ((regno + j) % REGSET_ELT_BITS);
2940 bb_dead_regs[offset] &= ~bit;
2941 bb_live_regs[offset] |= bit;
2946 bb_dead_regs[offset] &= ~bit;
2947 bb_live_regs[offset] |= bit;
2954 /* Handle tail-recursive case. */
2955 attach_deaths (XEXP (x, 0), insn, 0);
2959 case STRICT_LOW_PART:
2960 /* These two cases preserve the value of SET_P, so handle them
2962 attach_deaths (XEXP (x, 0), insn, set_p);
2967 /* This case preserves the value of SET_P for the first operand, but
2968 clears it for the other two. */
2969 attach_deaths (XEXP (x, 0), insn, set_p);
2970 attach_deaths (XEXP (x, 1), insn, 0);
2971 attach_deaths (XEXP (x, 2), insn, 0);
2975 /* Other cases: walk the insn. */
2976 fmt = GET_RTX_FORMAT (code);
2977 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2980 attach_deaths (XEXP (x, i), insn, 0);
2981 else if (fmt[i] == 'E')
2982 for (j = 0; j < XVECLEN (x, i); j++)
2983 attach_deaths (XVECEXP (x, i, j), insn, 0);
2988 /* After INSN has executed, add register death notes for each register
2989 that is dead after INSN. */
2992 attach_deaths_insn (insn)
2995 rtx x = PATTERN (insn);
2996 register RTX_CODE code = GET_CODE (x);
3001 attach_deaths (SET_SRC (x), insn, 0);
3003 /* A register might die here even if it is the destination, e.g.
3004 it is the target of a volatile read and is otherwise unused.
3005 Hence we must always call attach_deaths for the SET_DEST. */
3006 attach_deaths (SET_DEST (x), insn, 1);
3008 else if (code == PARALLEL)
3011 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
3013 code = GET_CODE (XVECEXP (x, 0, i));
3016 attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0);
3018 attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1);
3020 /* Flow does not add REG_DEAD notes to registers that die in
3021 clobbers, so we can't either. */
3022 else if (code != CLOBBER)
3023 attach_deaths (XVECEXP (x, 0, i), insn, 0);
3026 /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a
3027 MEM being clobbered, just like flow. */
3028 else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == MEM)
3029 attach_deaths (XEXP (XEXP (x, 0), 0), insn, 0);
3030 /* Otherwise don't add a death note to things being clobbered. */
3031 else if (code != CLOBBER)
3032 attach_deaths (x, insn, 0);
3034 /* Make death notes for things used in the called function. */
3035 if (GET_CODE (insn) == CALL_INSN)
3036 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
3037 attach_deaths (XEXP (XEXP (link, 0), 0), insn,
3038 GET_CODE (XEXP (link, 0)) == CLOBBER);
3041 /* Delete notes beginning with INSN and maybe put them in the chain
3042 of notes ended by NOTE_LIST.
3043 Returns the insn following the notes. */
3046 unlink_notes (insn, tail)
3049 rtx prev = PREV_INSN (insn);
3051 while (insn != tail && GET_CODE (insn) == NOTE)
3053 rtx next = NEXT_INSN (insn);
3054 /* Delete the note from its current position. */
3056 NEXT_INSN (prev) = next;
3058 PREV_INSN (next) = prev;
3060 if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
3061 /* Record line-number notes so they can be reused. */
3062 LINE_NOTE (insn) = insn;
3064 /* Don't save away NOTE_INSN_SETJMPs, because they must remain
3065 immediately after the call they follow. We use a fake
3066 (REG_DEAD (const_int -1)) note to remember them.
3067 Likewise with NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END. */
3068 else if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP
3069 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG
3070 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END)
3072 /* Insert the note at the end of the notes list. */
3073 PREV_INSN (insn) = note_list;
3075 NEXT_INSN (note_list) = insn;
3084 /* Constructor for `sometimes' data structure. */
3087 new_sometimes_live (regs_sometimes_live, offset, bit, sometimes_max)
3088 struct sometimes *regs_sometimes_live;
3092 register struct sometimes *p;
3093 register int regno = offset * REGSET_ELT_BITS + bit;
3095 /* There should never be a register greater than max_regno here. If there
3096 is, it means that a define_split has created a new pseudo reg. This
3097 is not allowed, since there will not be flow info available for any
3098 new register, so catch the error here. */
3099 if (regno >= max_regno)
3102 p = ®s_sometimes_live[sometimes_max];
3106 p->calls_crossed = 0;
3108 return sometimes_max;
3111 /* Count lengths of all regs we are currently tracking,
3112 and find new registers no longer live. */
3115 finish_sometimes_live (regs_sometimes_live, sometimes_max)
3116 struct sometimes *regs_sometimes_live;
3121 for (i = 0; i < sometimes_max; i++)
3123 register struct sometimes *p = ®s_sometimes_live[i];
3126 regno = p->offset * REGSET_ELT_BITS + p->bit;
3128 sched_reg_live_length[regno] += p->live_length;
3129 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
3133 /* Search INSN for fake REG_DEAD notes for NOTE_INSN_SETJMP,
3134 NOTE_INSN_LOOP_BEG, and NOTE_INSN_LOOP_END; and convert them back
3135 into NOTEs. LAST is the last instruction output by the instruction
3136 scheduler. Return the new value of LAST. */
3139 reemit_notes (insn, last)
3145 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
3147 if (REG_NOTE_KIND (note) == REG_DEAD
3148 && GET_CODE (XEXP (note, 0)) == CONST_INT)
3150 if (INTVAL (XEXP (note, 0)) == NOTE_INSN_SETJMP)
3151 emit_note_after (INTVAL (XEXP (note, 0)), insn);
3153 last = emit_note_before (INTVAL (XEXP (note, 0)), last);
3154 remove_note (insn, note);
3160 /* Use modified list scheduling to rearrange insns in basic block
3161 B. FILE, if nonzero, is where we dump interesting output about
3165 schedule_block (b, file)
3171 int i, j, n_ready = 0, new_ready, n_insns = 0;
3172 int sched_n_insns = 0;
3174 #define NEED_NOTHING 0
3179 /* HEAD and TAIL delimit the region being scheduled. */
3180 rtx head = basic_block_head[b];
3181 rtx tail = basic_block_end[b];
3182 /* PREV_HEAD and NEXT_TAIL are the boundaries of the insns
3183 being scheduled. When the insns have been ordered,
3184 these insns delimit where the new insns are to be
3185 spliced back into the insn chain. */
3189 /* Keep life information accurate. */
3190 register struct sometimes *regs_sometimes_live;
3194 fprintf (file, ";;\t -- basic block number %d from %d to %d --\n",
3195 b, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b]));
3198 reg_last_uses = (rtx *) alloca (i * sizeof (rtx));
3199 bzero ((char *) reg_last_uses, i * sizeof (rtx));
3200 reg_last_sets = (rtx *) alloca (i * sizeof (rtx));
3201 bzero ((char *) reg_last_sets, i * sizeof (rtx));
3202 reg_pending_sets = (regset) alloca (regset_bytes);
3203 bzero ((char *) reg_pending_sets, regset_bytes);
3204 reg_pending_sets_all = 0;
3207 /* Remove certain insns at the beginning from scheduling,
3208 by advancing HEAD. */
3210 /* At the start of a function, before reload has run, don't delay getting
3211 parameters from hard registers into pseudo registers. */
3212 if (reload_completed == 0 && b == 0)
3215 && GET_CODE (head) == NOTE
3216 && NOTE_LINE_NUMBER (head) != NOTE_INSN_FUNCTION_BEG)
3217 head = NEXT_INSN (head);
3219 && GET_CODE (head) == INSN
3220 && GET_CODE (PATTERN (head)) == SET)
3222 rtx src = SET_SRC (PATTERN (head));
3223 while (GET_CODE (src) == SUBREG
3224 || GET_CODE (src) == SIGN_EXTEND
3225 || GET_CODE (src) == ZERO_EXTEND
3226 || GET_CODE (src) == SIGN_EXTRACT
3227 || GET_CODE (src) == ZERO_EXTRACT)
3228 src = XEXP (src, 0);
3229 if (GET_CODE (src) != REG
3230 || REGNO (src) >= FIRST_PSEUDO_REGISTER)
3232 /* Keep this insn from ever being scheduled. */
3233 INSN_REF_COUNT (head) = 1;
3234 head = NEXT_INSN (head);
3238 /* Don't include any notes or labels at the beginning of the
3239 basic block, or notes at the ends of basic blocks. */
3240 while (head != tail)
3242 if (GET_CODE (head) == NOTE)
3243 head = NEXT_INSN (head);
3244 else if (GET_CODE (tail) == NOTE)
3245 tail = PREV_INSN (tail);
3246 else if (GET_CODE (head) == CODE_LABEL)
3247 head = NEXT_INSN (head);
3250 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
3251 to schedule this block. */
3253 && (GET_CODE (head) == NOTE || GET_CODE (head) == CODE_LABEL))
3257 /* This short-cut doesn't work. It does not count call insns crossed by
3258 registers in reg_sometimes_live. It does not mark these registers as
3259 dead if they die in this block. It does not mark these registers live
3260 (or create new reg_sometimes_live entries if necessary) if they are born
3263 The easy solution is to just always schedule a block. This block only
3264 has one insn, so this won't slow down this pass by much. */
3270 /* Now HEAD through TAIL are the insns actually to be rearranged;
3271 Let PREV_HEAD and NEXT_TAIL enclose them. */
3272 prev_head = PREV_INSN (head);
3273 next_tail = NEXT_INSN (tail);
3275 /* Initialize basic block data structures. */
3277 pending_read_insns = 0;
3278 pending_read_mems = 0;
3279 pending_write_insns = 0;
3280 pending_write_mems = 0;
3281 pending_lists_length = 0;
3282 last_pending_memory_flush = 0;
3283 last_function_call = 0;
3284 last_scheduled_insn = 0;
3286 LOG_LINKS (sched_before_next_call) = 0;
3288 n_insns += sched_analyze (head, tail);
3291 free_pending_lists ();
3295 /* Allocate vector to hold insns to be rearranged (except those
3296 insns which are controlled by an insn with SCHED_GROUP_P set).
3297 All these insns are included between ORIG_HEAD and ORIG_TAIL,
3298 as those variables ultimately are set up. */
3299 ready = (rtx *) alloca ((n_insns+1) * sizeof (rtx));
3301 /* TAIL is now the last of the insns to be rearranged.
3302 Put those insns into the READY vector. */
3305 /* For all branches, calls, uses, and cc0 setters, force them to remain
3306 in order at the end of the block by adding dependencies and giving
3307 the last a high priority. There may be notes present, and prev_head
3310 Branches must obviously remain at the end. Calls should remain at the
3311 end since moving them results in worse register allocation. Uses remain
3312 at the end to ensure proper register allocation. cc0 setters remaim
3313 at the end because they can't be moved away from their cc0 user. */
3315 while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN
3316 || (GET_CODE (insn) == INSN
3317 && (GET_CODE (PATTERN (insn)) == USE
3319 || sets_cc0_p (PATTERN (insn))
3322 || GET_CODE (insn) == NOTE)
3324 if (GET_CODE (insn) != NOTE)
3329 ready[n_ready++] = insn;
3330 INSN_PRIORITY (insn) = TAIL_PRIORITY - i;
3331 INSN_REF_COUNT (insn) = 0;
3333 else if (! find_insn_list (insn, LOG_LINKS (last)))
3335 add_dependence (last, insn, REG_DEP_ANTI);
3336 INSN_REF_COUNT (insn)++;
3340 /* Skip over insns that are part of a group. */
3341 while (SCHED_GROUP_P (insn))
3343 insn = prev_nonnote_insn (insn);
3348 insn = PREV_INSN (insn);
3349 /* Don't overrun the bounds of the basic block. */
3350 if (insn == prev_head)
3354 /* Assign priorities to instructions. Also check whether they
3355 are in priority order already. If so then I will be nonnegative.
3356 We use this shortcut only before reloading. */
3358 i = reload_completed ? DONE_PRIORITY : MAX_PRIORITY;
3361 for (; insn != prev_head; insn = PREV_INSN (insn))
3363 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3366 if (INSN_REF_COUNT (insn) == 0)
3369 ready[n_ready++] = insn;
3372 /* Make this dependent on the last of the instructions
3373 that must remain in order at the end of the block. */
3374 add_dependence (last, insn, REG_DEP_ANTI);
3375 INSN_REF_COUNT (insn) = 1;
3378 if (SCHED_GROUP_P (insn))
3380 while (SCHED_GROUP_P (insn))
3382 insn = PREV_INSN (insn);
3383 while (GET_CODE (insn) == NOTE)
3384 insn = PREV_INSN (insn);
3392 if (INSN_PRIORITY (insn) < i)
3393 i = INSN_PRIORITY (insn);
3394 else if (INSN_PRIORITY (insn) > i)
3401 /* This short-cut doesn't work. It does not count call insns crossed by
3402 registers in reg_sometimes_live. It does not mark these registers as
3403 dead if they die in this block. It does not mark these registers live
3404 (or create new reg_sometimes_live entries if necessary) if they are born
3407 The easy solution is to just always schedule a block. These blocks tend
3408 to be very short, so this doesn't slow down this pass by much. */
3410 /* If existing order is good, don't bother to reorder. */
3411 if (i != DONE_PRIORITY)
3414 fprintf (file, ";; already scheduled\n");
3416 if (reload_completed == 0)
3418 for (i = 0; i < sometimes_max; i++)
3419 regs_sometimes_live[i].live_length += n_insns;
3421 finish_sometimes_live (regs_sometimes_live, sometimes_max);
3423 free_pending_lists ();
3428 /* Scan all the insns to be scheduled, removing NOTE insns
3429 and register death notes.
3430 Line number NOTE insns end up in NOTE_LIST.
3431 Register death notes end up in DEAD_NOTES.
3433 Recreate the register life information for the end of this basic
3436 if (reload_completed == 0)
3438 bcopy ((char *) basic_block_live_at_start[b], (char *) bb_live_regs,
3440 bzero ((char *) bb_dead_regs, regset_bytes);
3444 /* This is the first block in the function. There may be insns
3445 before head that we can't schedule. We still need to examine
3446 them though for accurate register lifetime analysis. */
3448 /* We don't want to remove any REG_DEAD notes as the code below
3451 for (insn = basic_block_head[b]; insn != head;
3452 insn = NEXT_INSN (insn))
3453 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3455 /* See if the register gets born here. */
3456 /* We must check for registers being born before we check for
3457 registers dying. It is possible for a register to be born
3458 and die in the same insn, e.g. reading from a volatile
3459 memory location into an otherwise unused register. Such
3460 a register must be marked as dead after this insn. */
3461 if (GET_CODE (PATTERN (insn)) == SET
3462 || GET_CODE (PATTERN (insn)) == CLOBBER)
3463 sched_note_set (b, PATTERN (insn), 0);
3464 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3467 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3468 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3469 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3470 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3472 /* ??? This code is obsolete and should be deleted. It
3473 is harmless though, so we will leave it in for now. */
3474 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3475 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
3476 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3479 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
3481 if ((REG_NOTE_KIND (link) == REG_DEAD
3482 || REG_NOTE_KIND (link) == REG_UNUSED)
3483 /* Verify that the REG_NOTE has a valid value. */
3484 && GET_CODE (XEXP (link, 0)) == REG)
3486 register int regno = REGNO (XEXP (link, 0));
3487 register int offset = regno / REGSET_ELT_BITS;
3488 register REGSET_ELT_TYPE bit
3489 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
3491 if (regno < FIRST_PSEUDO_REGISTER)
3493 int j = HARD_REGNO_NREGS (regno,
3494 GET_MODE (XEXP (link, 0)));
3497 offset = (regno + j) / REGSET_ELT_BITS;
3498 bit = ((REGSET_ELT_TYPE) 1
3499 << ((regno + j) % REGSET_ELT_BITS));
3501 bb_live_regs[offset] &= ~bit;
3502 bb_dead_regs[offset] |= bit;
3507 bb_live_regs[offset] &= ~bit;
3508 bb_dead_regs[offset] |= bit;
3516 /* If debugging information is being produced, keep track of the line
3517 number notes for each insn. */
3518 if (write_symbols != NO_DEBUG)
3520 /* We must use the true line number for the first insn in the block
3521 that was computed and saved at the start of this pass. We can't
3522 use the current line number, because scheduling of the previous
3523 block may have changed the current line number. */
3524 rtx line = line_note_head[b];
3526 for (insn = basic_block_head[b];
3528 insn = NEXT_INSN (insn))
3529 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
3532 LINE_NOTE (insn) = line;
3535 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
3537 rtx prev, next, link;
3539 /* Farm out notes. This is needed to keep the debugger from
3540 getting completely deranged. */
3541 if (GET_CODE (insn) == NOTE)
3544 insn = unlink_notes (insn, next_tail);
3549 if (insn == next_tail)
3553 if (reload_completed == 0
3554 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3556 /* See if the register gets born here. */
3557 /* We must check for registers being born before we check for
3558 registers dying. It is possible for a register to be born and
3559 die in the same insn, e.g. reading from a volatile memory
3560 location into an otherwise unused register. Such a register
3561 must be marked as dead after this insn. */
3562 if (GET_CODE (PATTERN (insn)) == SET
3563 || GET_CODE (PATTERN (insn)) == CLOBBER)
3564 sched_note_set (b, PATTERN (insn), 0);
3565 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3568 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3569 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3570 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3571 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3573 /* ??? This code is obsolete and should be deleted. It
3574 is harmless though, so we will leave it in for now. */
3575 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3576 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
3577 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 0);
3580 /* Need to know what registers this insn kills. */
3581 for (prev = 0, link = REG_NOTES (insn); link; link = next)
3583 next = XEXP (link, 1);
3584 if ((REG_NOTE_KIND (link) == REG_DEAD
3585 || REG_NOTE_KIND (link) == REG_UNUSED)
3586 /* Verify that the REG_NOTE has a valid value. */
3587 && GET_CODE (XEXP (link, 0)) == REG)
3589 register int regno = REGNO (XEXP (link, 0));
3590 register int offset = regno / REGSET_ELT_BITS;
3591 register REGSET_ELT_TYPE bit
3592 = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
3594 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
3596 if (REG_NOTE_KIND (link) == REG_DEAD)
3599 XEXP (prev, 1) = next;
3601 REG_NOTES (insn) = next;
3602 XEXP (link, 1) = dead_notes;
3608 if (regno < FIRST_PSEUDO_REGISTER)
3610 int j = HARD_REGNO_NREGS (regno,
3611 GET_MODE (XEXP (link, 0)));
3614 offset = (regno + j) / REGSET_ELT_BITS;
3615 bit = ((REGSET_ELT_TYPE) 1
3616 << ((regno + j) % REGSET_ELT_BITS));
3618 bb_live_regs[offset] &= ~bit;
3619 bb_dead_regs[offset] |= bit;
3624 bb_live_regs[offset] &= ~bit;
3625 bb_dead_regs[offset] |= bit;
3634 if (reload_completed == 0)
3636 /* Keep track of register lives. */
3637 old_live_regs = (regset) alloca (regset_bytes);
3639 = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes));
3642 /* Start with registers live at end. */
3643 for (j = 0; j < regset_size; j++)
3645 REGSET_ELT_TYPE live = bb_live_regs[j];
3646 old_live_regs[j] = live;
3650 for (bit = 0; bit < REGSET_ELT_BITS; bit++)
3651 if (live & ((REGSET_ELT_TYPE) 1 << bit))
3652 sometimes_max = new_sometimes_live (regs_sometimes_live, j,
3653 bit, sometimes_max);
3658 SCHED_SORT (ready, n_ready, 1);
3662 fprintf (file, ";; ready list initially:\n;; ");
3663 for (i = 0; i < n_ready; i++)
3664 fprintf (file, "%d ", INSN_UID (ready[i]));
3665 fprintf (file, "\n\n");
3667 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
3668 if (INSN_PRIORITY (insn) > 0)
3669 fprintf (file, ";; insn[%4d]: priority = %4d, ref_count = %4d\n",
3670 INSN_UID (insn), INSN_PRIORITY (insn),
3671 INSN_REF_COUNT (insn));
3674 /* Now HEAD and TAIL are going to become disconnected
3675 entirely from the insn chain. */
3678 /* Q_SIZE will always be zero here. */
3679 q_ptr = 0; clock = 0;
3680 bzero ((char *) insn_queue, sizeof (insn_queue));
3682 /* Now, perform list scheduling. */
3684 /* Where we start inserting insns is after TAIL. */
3687 new_needs = (NEXT_INSN (prev_head) == basic_block_head[b]
3688 ? NEED_HEAD : NEED_NOTHING);
3689 if (PREV_INSN (next_tail) == basic_block_end[b])
3690 new_needs |= NEED_TAIL;
3692 new_ready = n_ready;
3693 while (sched_n_insns < n_insns)
3695 q_ptr = NEXT_Q (q_ptr); clock++;
3697 /* Add all pending insns that can be scheduled without stalls to the
3699 for (insn = insn_queue[q_ptr]; insn; insn = NEXT_INSN (insn))
3702 fprintf (file, ";; launching %d before %d with no stalls at T-%d\n",
3703 INSN_UID (insn), INSN_UID (last), clock);
3704 ready[new_ready++] = insn;
3707 insn_queue[q_ptr] = 0;
3709 /* If there are no ready insns, stall until one is ready and add all
3710 of the pending insns at that point to the ready list. */
3713 register int stalls;
3715 for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++)
3716 if (insn = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])
3718 for (; insn; insn = NEXT_INSN (insn))
3721 fprintf (file, ";; launching %d before %d with %d stalls at T-%d\n",
3722 INSN_UID (insn), INSN_UID (last), stalls, clock);
3723 ready[new_ready++] = insn;
3726 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
3730 q_ptr = NEXT_Q_AFTER (q_ptr, stalls); clock += stalls;
3733 /* There should be some instructions waiting to fire. */
3739 fprintf (file, ";; ready list at T-%d:", clock);
3740 for (i = 0; i < new_ready; i++)
3741 fprintf (file, " %d (%x)",
3742 INSN_UID (ready[i]), INSN_PRIORITY (ready[i]));
3745 /* Sort the ready list and choose the best insn to schedule. Select
3746 which insn should issue in this cycle and queue those that are
3747 blocked by function unit hazards.
3749 N_READY holds the number of items that were scheduled the last time,
3750 minus the one instruction scheduled on the last loop iteration; it
3751 is not modified for any other reason in this loop. */
3753 SCHED_SORT (ready, new_ready, n_ready);
3754 if (MAX_BLOCKAGE > 1)
3756 new_ready = schedule_select (ready, new_ready, clock, file);
3760 fprintf (file, "\n");
3761 /* We must set n_ready here, to ensure that sorting always
3762 occurs when we come back to the SCHED_SORT line above. */
3767 n_ready = new_ready;
3768 last_scheduled_insn = insn = ready[0];
3770 /* The first insn scheduled becomes the new tail. */
3776 fprintf (file, ", now");
3777 for (i = 0; i < n_ready; i++)
3778 fprintf (file, " %d", INSN_UID (ready[i]));
3779 fprintf (file, "\n");
3782 if (DONE_PRIORITY_P (insn))
3785 if (reload_completed == 0)
3787 /* Process this insn, and each insn linked to this one which must
3788 be immediately output after this insn. */
3791 /* First we kill registers set by this insn, and then we
3792 make registers used by this insn live. This is the opposite
3793 order used above because we are traversing the instructions
3796 /* Strictly speaking, we should scan REG_UNUSED notes and make
3797 every register mentioned there live, however, we will just
3798 kill them again immediately below, so there doesn't seem to
3799 be any reason why we bother to do this. */
3801 /* See if this is the last notice we must take of a register. */
3802 if (GET_CODE (PATTERN (insn)) == SET
3803 || GET_CODE (PATTERN (insn)) == CLOBBER)
3804 sched_note_set (b, PATTERN (insn), 1);
3805 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3808 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
3809 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
3810 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
3811 sched_note_set (b, XVECEXP (PATTERN (insn), 0, j), 1);
3814 /* This code keeps life analysis information up to date. */
3815 if (GET_CODE (insn) == CALL_INSN)
3817 register struct sometimes *p;
3819 /* A call kills all call used and global registers, except
3820 for those mentioned in the call pattern which will be
3821 made live again later. */
3822 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3823 if (call_used_regs[i] || global_regs[i])
3825 register int offset = i / REGSET_ELT_BITS;
3826 register REGSET_ELT_TYPE bit
3827 = (REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS);
3829 bb_live_regs[offset] &= ~bit;
3830 bb_dead_regs[offset] |= bit;
3833 /* Regs live at the time of a call instruction must not
3834 go in a register clobbered by calls. Record this for
3835 all regs now live. Note that insns which are born or
3836 die in a call do not cross a call, so this must be done
3837 after the killings (above) and before the births
3839 p = regs_sometimes_live;
3840 for (i = 0; i < sometimes_max; i++, p++)
3841 if (bb_live_regs[p->offset]
3842 & ((REGSET_ELT_TYPE) 1 << p->bit))
3843 p->calls_crossed += 1;
3846 /* Make every register used live, and add REG_DEAD notes for
3847 registers which were not live before we started. */
3848 attach_deaths_insn (insn);
3850 /* Find registers now made live by that instruction. */
3851 for (i = 0; i < regset_size; i++)
3853 REGSET_ELT_TYPE diff = bb_live_regs[i] & ~old_live_regs[i];
3857 old_live_regs[i] |= diff;
3858 for (bit = 0; bit < REGSET_ELT_BITS; bit++)
3859 if (diff & ((REGSET_ELT_TYPE) 1 << bit))
3861 = new_sometimes_live (regs_sometimes_live, i, bit,
3866 /* Count lengths of all regs we are worrying about now,
3867 and handle registers no longer live. */
3869 for (i = 0; i < sometimes_max; i++)
3871 register struct sometimes *p = ®s_sometimes_live[i];
3872 int regno = p->offset*REGSET_ELT_BITS + p->bit;
3874 p->live_length += 1;
3876 if ((bb_live_regs[p->offset]
3877 & ((REGSET_ELT_TYPE) 1 << p->bit)) == 0)
3879 /* This is the end of one of this register's lifetime
3880 segments. Save the lifetime info collected so far,
3881 and clear its bit in the old_live_regs entry. */
3882 sched_reg_live_length[regno] += p->live_length;
3883 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
3884 old_live_regs[p->offset]
3885 &= ~((REGSET_ELT_TYPE) 1 << p->bit);
3887 /* Delete the reg_sometimes_live entry for this reg by
3888 copying the last entry over top of it. */
3889 *p = regs_sometimes_live[--sometimes_max];
3890 /* ...and decrement i so that this newly copied entry
3891 will be processed. */
3897 insn = PREV_INSN (insn);
3899 while (SCHED_GROUP_P (link));
3901 /* Set INSN back to the insn we are scheduling now. */
3905 /* Schedule INSN. Remove it from the ready list. */
3910 NEXT_INSN (insn) = last;
3911 PREV_INSN (last) = insn;
3913 /* Maintain a valid chain so emit_note_before works.
3914 This is necessary because PREV_INSN (insn) isn't valid and
3915 if it points to an insn already scheduled, a circularity
3917 NEXT_INSN (prev_head) = insn;
3918 PREV_INSN (insn) = prev_head;
3922 /* Check to see if we need to re-emit any notes here. */
3923 last = reemit_notes (insn, last);
3925 /* Everything that precedes INSN now either becomes "ready", if
3926 it can execute immediately before INSN, or "pending", if
3927 there must be a delay. Give INSN high enough priority that
3928 at least one (maybe more) reg-killing insns can be launched
3929 ahead of all others. Mark INSN as scheduled by changing its
3931 INSN_PRIORITY (insn) = LAUNCH_PRIORITY;
3932 new_ready = schedule_insn (insn, ready, n_ready, clock);
3933 INSN_PRIORITY (insn) = DONE_PRIORITY;
3935 /* Schedule all prior insns that must not be moved. */
3936 if (SCHED_GROUP_P (insn))
3938 /* Disable these insns from being launched, in case one of the
3939 insns in the group has a dependency on an earlier one. */
3941 while (SCHED_GROUP_P (link))
3943 /* Disable these insns from being launched by anybody. */
3944 link = PREV_INSN (link);
3945 INSN_REF_COUNT (link) = 0;
3948 /* Now handle each group insn like the main insn was handled
3950 while (SCHED_GROUP_P (insn))
3952 insn = PREV_INSN (insn);
3955 NEXT_INSN (insn) = last;
3956 PREV_INSN (last) = insn;
3958 /* Maintain a valid chain so emit_note_before works.
3959 This is necessary because PREV_INSN (insn) isn't valid and
3960 if it points to an insn already scheduled, a circularity
3962 NEXT_INSN (prev_head) = insn;
3963 PREV_INSN (insn) = prev_head;
3967 last = reemit_notes (insn, last);
3969 /* ??? Why don't we set LAUNCH_PRIORITY here? */
3970 new_ready = schedule_insn (insn, ready, new_ready, clock);
3971 INSN_PRIORITY (insn) = DONE_PRIORITY;
3978 if (reload_completed == 0)
3979 finish_sometimes_live (regs_sometimes_live, sometimes_max);
3981 /* HEAD is now the first insn in the chain of insns that
3982 been scheduled by the loop above.
3983 TAIL is the last of those insns. */
3986 /* NOTE_LIST is the end of a chain of notes previously found
3987 among the insns. Insert them at the beginning of the insns. */
3990 rtx note_head = note_list;
3991 while (PREV_INSN (note_head))
3992 note_head = PREV_INSN (note_head);
3994 PREV_INSN (head) = note_list;
3995 NEXT_INSN (note_list) = head;
3999 /* There should be no REG_DEAD notes leftover at the end.
4000 In practice, this can occur as the result of bugs in flow, combine.c,
4001 and/or sched.c. The values of the REG_DEAD notes remaining are
4002 meaningless, because dead_notes is just used as a free list. */
4004 if (dead_notes != 0)
4008 if (new_needs & NEED_HEAD)
4009 basic_block_head[b] = head;
4010 PREV_INSN (head) = prev_head;
4011 NEXT_INSN (prev_head) = head;
4013 if (new_needs & NEED_TAIL)
4014 basic_block_end[b] = tail;
4015 NEXT_INSN (tail) = next_tail;
4016 PREV_INSN (next_tail) = tail;
4018 /* Restore the line-number notes of each insn. */
4019 if (write_symbols != NO_DEBUG)
4021 rtx line, note, prev, new;
4024 head = basic_block_head[b];
4025 next_tail = NEXT_INSN (basic_block_end[b]);
4027 /* Determine the current line-number. We want to know the current
4028 line number of the first insn of the block here, in case it is
4029 different from the true line number that was saved earlier. If
4030 different, then we need a line number note before the first insn
4031 of this block. If it happens to be the same, then we don't want to
4032 emit another line number note here. */
4033 for (line = head; line; line = PREV_INSN (line))
4034 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4037 /* Walk the insns keeping track of the current line-number and inserting
4038 the line-number notes as needed. */
4039 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4040 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4042 /* This used to emit line number notes before every non-deleted note.
4043 However, this confuses a debugger, because line notes not separated
4044 by real instructions all end up at the same address. I can find no
4045 use for line number notes before other notes, so none are emitted. */
4046 else if (GET_CODE (insn) != NOTE
4047 && (note = LINE_NOTE (insn)) != 0
4050 || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
4051 || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
4054 prev = PREV_INSN (insn);
4055 if (LINE_NOTE (note))
4057 /* Re-use the original line-number note. */
4058 LINE_NOTE (note) = 0;
4059 PREV_INSN (note) = prev;
4060 NEXT_INSN (prev) = note;
4061 PREV_INSN (insn) = note;
4062 NEXT_INSN (note) = insn;
4067 new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
4068 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
4069 RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note);
4073 fprintf (file, ";; added %d line-number notes\n", notes);
4078 fprintf (file, ";; total time = %d\n;; new basic block head = %d\n;; new basic block end = %d\n\n",
4079 clock, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b]));
4082 /* Yow! We're done! */
4083 free_pending_lists ();
4088 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
4089 REGNO, returning the rtx of the reference found if any. Otherwise,
4093 regno_use_in (regno, x)
4101 if (GET_CODE (x) == REG && REGNO (x) == regno)
4104 fmt = GET_RTX_FORMAT (GET_CODE (x));
4105 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4109 if (tem = regno_use_in (regno, XEXP (x, i)))
4112 else if (fmt[i] == 'E')
4113 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4114 if (tem = regno_use_in (regno , XVECEXP (x, i, j)))
4121 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
4122 needed for the hard register mentioned in the note. This can happen
4123 if the reference to the hard register in the original insn was split into
4124 several smaller hard register references in the split insns. */
4127 split_hard_reg_notes (note, first, last, orig_insn)
4128 rtx note, first, last, orig_insn;
4130 rtx reg, temp, link;
4131 int n_regs, i, new_reg;
4134 /* Assume that this is a REG_DEAD note. */
4135 if (REG_NOTE_KIND (note) != REG_DEAD)
4138 reg = XEXP (note, 0);
4140 n_regs = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
4142 for (i = 0; i < n_regs; i++)
4144 new_reg = REGNO (reg) + i;
4146 /* Check for references to new_reg in the split insns. */
4147 for (insn = last; ; insn = PREV_INSN (insn))
4149 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4150 && (temp = regno_use_in (new_reg, PATTERN (insn))))
4152 /* Create a new reg dead note here. */
4153 link = rtx_alloc (EXPR_LIST);
4154 PUT_REG_NOTE_KIND (link, REG_DEAD);
4155 XEXP (link, 0) = temp;
4156 XEXP (link, 1) = REG_NOTES (insn);
4157 REG_NOTES (insn) = link;
4159 /* If killed multiple registers here, then add in the excess. */
4160 i += HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) - 1;
4164 /* It isn't mentioned anywhere, so no new reg note is needed for
4172 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
4173 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
4176 new_insn_dead_notes (pat, insn, last, orig_insn)
4177 rtx pat, insn, last, orig_insn;
4181 /* PAT is either a CLOBBER or a SET here. */
4182 dest = XEXP (pat, 0);
4184 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
4185 || GET_CODE (dest) == STRICT_LOW_PART
4186 || GET_CODE (dest) == SIGN_EXTRACT)
4187 dest = XEXP (dest, 0);
4189 if (GET_CODE (dest) == REG)
4191 for (tem = last; tem != insn; tem = PREV_INSN (tem))
4193 if (GET_RTX_CLASS (GET_CODE (tem)) == 'i'
4194 && reg_overlap_mentioned_p (dest, PATTERN (tem))
4195 && (set = single_set (tem)))
4197 rtx tem_dest = SET_DEST (set);
4199 while (GET_CODE (tem_dest) == ZERO_EXTRACT
4200 || GET_CODE (tem_dest) == SUBREG
4201 || GET_CODE (tem_dest) == STRICT_LOW_PART
4202 || GET_CODE (tem_dest) == SIGN_EXTRACT)
4203 tem_dest = XEXP (tem_dest, 0);
4205 if (! rtx_equal_p (tem_dest, dest))
4207 /* Use the same scheme as combine.c, don't put both REG_DEAD
4208 and REG_UNUSED notes on the same insn. */
4209 if (! find_regno_note (tem, REG_UNUSED, REGNO (dest))
4210 && ! find_regno_note (tem, REG_DEAD, REGNO (dest)))
4212 rtx note = rtx_alloc (EXPR_LIST);
4213 PUT_REG_NOTE_KIND (note, REG_DEAD);
4214 XEXP (note, 0) = dest;
4215 XEXP (note, 1) = REG_NOTES (tem);
4216 REG_NOTES (tem) = note;
4218 /* The reg only dies in one insn, the last one that uses
4222 else if (reg_overlap_mentioned_p (dest, SET_SRC (set)))
4223 /* We found an instruction that both uses the register,
4224 and sets it, so no new REG_NOTE is needed for this set. */
4228 /* If this is a set, it must die somewhere, unless it is the dest of
4229 the original insn, and hence is live after the original insn. Abort
4230 if it isn't supposed to be live after the original insn.
4232 If this is a clobber, then just add a REG_UNUSED note. */
4235 int live_after_orig_insn = 0;
4236 rtx pattern = PATTERN (orig_insn);
4239 if (GET_CODE (pat) == CLOBBER)
4241 rtx note = rtx_alloc (EXPR_LIST);
4242 PUT_REG_NOTE_KIND (note, REG_UNUSED);
4243 XEXP (note, 0) = dest;
4244 XEXP (note, 1) = REG_NOTES (insn);
4245 REG_NOTES (insn) = note;
4249 /* The original insn could have multiple sets, so search the
4250 insn for all sets. */
4251 if (GET_CODE (pattern) == SET)
4253 if (reg_overlap_mentioned_p (dest, SET_DEST (pattern)))
4254 live_after_orig_insn = 1;
4256 else if (GET_CODE (pattern) == PARALLEL)
4258 for (i = 0; i < XVECLEN (pattern, 0); i++)
4259 if (GET_CODE (XVECEXP (pattern, 0, i)) == SET
4260 && reg_overlap_mentioned_p (dest,
4261 SET_DEST (XVECEXP (pattern,
4263 live_after_orig_insn = 1;
4266 if (! live_after_orig_insn)
4272 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
4273 registers modified by X. INC is -1 if the containing insn is being deleted,
4274 and is 1 if the containing insn is a newly generated insn. */
4277 update_n_sets (x, inc)
4281 rtx dest = SET_DEST (x);
4283 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
4284 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
4285 dest = SUBREG_REG (dest);
4287 if (GET_CODE (dest) == REG)
4289 int regno = REGNO (dest);
4291 if (regno < FIRST_PSEUDO_REGISTER)
4294 int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest));
4296 for (i = regno; i < endregno; i++)
4297 reg_n_sets[i] += inc;
4300 reg_n_sets[regno] += inc;
4304 /* Updates all flow-analysis related quantities (including REG_NOTES) for
4305 the insns from FIRST to LAST inclusive that were created by splitting
4306 ORIG_INSN. NOTES are the original REG_NOTES. */
4309 update_flow_info (notes, first, last, orig_insn)
4316 rtx orig_dest, temp;
4319 /* Get and save the destination set by the original insn. */
4321 orig_dest = single_set (orig_insn);
4323 orig_dest = SET_DEST (orig_dest);
4325 /* Move REG_NOTES from the original insn to where they now belong. */
4327 for (note = notes; note; note = next)
4329 next = XEXP (note, 1);
4330 switch (REG_NOTE_KIND (note))
4334 /* Move these notes from the original insn to the last new insn where
4335 the register is now set. */
4337 for (insn = last; ; insn = PREV_INSN (insn))
4339 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4340 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
4342 /* If this note refers to a multiple word hard register, it
4343 may have been split into several smaller hard register
4344 references, so handle it specially. */
4345 temp = XEXP (note, 0);
4346 if (REG_NOTE_KIND (note) == REG_DEAD
4347 && GET_CODE (temp) == REG
4348 && REGNO (temp) < FIRST_PSEUDO_REGISTER
4349 && HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) > 1)
4350 split_hard_reg_notes (note, first, last, orig_insn);
4353 XEXP (note, 1) = REG_NOTES (insn);
4354 REG_NOTES (insn) = note;
4357 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
4359 /* ??? This won't handle multiple word registers correctly,
4360 but should be good enough for now. */
4361 if (REG_NOTE_KIND (note) == REG_UNUSED
4362 && ! dead_or_set_p (insn, XEXP (note, 0)))
4363 PUT_REG_NOTE_KIND (note, REG_DEAD);
4365 /* The reg only dies in one insn, the last one that uses
4369 /* It must die somewhere, fail it we couldn't find where it died.
4371 If this is a REG_UNUSED note, then it must be a temporary
4372 register that was not needed by this instantiation of the
4373 pattern, so we can safely ignore it. */
4376 if (REG_NOTE_KIND (note) != REG_UNUSED)
4385 /* This note applies to the dest of the original insn. Find the
4386 first new insn that now has the same dest, and move the note
4392 for (insn = first; ; insn = NEXT_INSN (insn))
4394 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4395 && (temp = single_set (insn))
4396 && rtx_equal_p (SET_DEST (temp), orig_dest))
4398 XEXP (note, 1) = REG_NOTES (insn);
4399 REG_NOTES (insn) = note;
4400 /* The reg is only zero before one insn, the first that
4404 /* It must be set somewhere, fail if we couldn't find where it
4413 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
4414 set is meaningless. Just drop the note. */
4418 case REG_NO_CONFLICT:
4419 /* These notes apply to the dest of the original insn. Find the last
4420 new insn that now has the same dest, and move the note there. */
4425 for (insn = last; ; insn = PREV_INSN (insn))
4427 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4428 && (temp = single_set (insn))
4429 && rtx_equal_p (SET_DEST (temp), orig_dest))
4431 XEXP (note, 1) = REG_NOTES (insn);
4432 REG_NOTES (insn) = note;
4433 /* Only put this note on one of the new insns. */
4437 /* The original dest must still be set someplace. Abort if we
4438 couldn't find it. */
4445 /* Move a REG_LIBCALL note to the first insn created, and update
4446 the corresponding REG_RETVAL note. */
4447 XEXP (note, 1) = REG_NOTES (first);
4448 REG_NOTES (first) = note;
4450 insn = XEXP (note, 0);
4451 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
4453 XEXP (note, 0) = first;
4457 /* Move a REG_RETVAL note to the last insn created, and update
4458 the corresponding REG_LIBCALL note. */
4459 XEXP (note, 1) = REG_NOTES (last);
4460 REG_NOTES (last) = note;
4462 insn = XEXP (note, 0);
4463 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
4465 XEXP (note, 0) = last;
4469 /* This should be moved to whichever instruction is a JUMP_INSN. */
4471 for (insn = last; ; insn = PREV_INSN (insn))
4473 if (GET_CODE (insn) == JUMP_INSN)
4475 XEXP (note, 1) = REG_NOTES (insn);
4476 REG_NOTES (insn) = note;
4477 /* Only put this note on one of the new insns. */
4480 /* Fail if we couldn't find a JUMP_INSN. */
4487 /* This should be moved to whichever instruction now has the
4488 increment operation. */
4492 /* Should be moved to the new insn(s) which use the label. */
4493 for (insn = first; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
4494 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4495 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
4496 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL,
4497 XEXP (note, 0), REG_NOTES (insn));
4502 /* These two notes will never appear until after reorg, so we don't
4503 have to handle them here. */
4509 /* Each new insn created, except the last, has a new set. If the destination
4510 is a register, then this reg is now live across several insns, whereas
4511 previously the dest reg was born and died within the same insn. To
4512 reflect this, we now need a REG_DEAD note on the insn where this
4515 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
4517 for (insn = first; insn != last; insn = NEXT_INSN (insn))
4522 pat = PATTERN (insn);
4523 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
4524 new_insn_dead_notes (pat, insn, last, orig_insn);
4525 else if (GET_CODE (pat) == PARALLEL)
4527 for (i = 0; i < XVECLEN (pat, 0); i++)
4528 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
4529 || GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER)
4530 new_insn_dead_notes (XVECEXP (pat, 0, i), insn, last, orig_insn);
4534 /* If any insn, except the last, uses the register set by the last insn,
4535 then we need a new REG_DEAD note on that insn. In this case, there
4536 would not have been a REG_DEAD note for this register in the original
4537 insn because it was used and set within one insn.
4539 There is no new REG_DEAD note needed if the last insn uses the register
4540 that it is setting. */
4542 set = single_set (last);
4545 rtx dest = SET_DEST (set);
4547 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
4548 || GET_CODE (dest) == STRICT_LOW_PART
4549 || GET_CODE (dest) == SIGN_EXTRACT)
4550 dest = XEXP (dest, 0);
4552 if (GET_CODE (dest) == REG
4553 && ! reg_overlap_mentioned_p (dest, SET_SRC (set)))
4555 for (insn = PREV_INSN (last); ; insn = PREV_INSN (insn))
4557 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4558 && reg_mentioned_p (dest, PATTERN (insn))
4559 && (set = single_set (insn)))
4561 rtx insn_dest = SET_DEST (set);
4563 while (GET_CODE (insn_dest) == ZERO_EXTRACT
4564 || GET_CODE (insn_dest) == SUBREG
4565 || GET_CODE (insn_dest) == STRICT_LOW_PART
4566 || GET_CODE (insn_dest) == SIGN_EXTRACT)
4567 insn_dest = XEXP (insn_dest, 0);
4569 if (insn_dest != dest)
4571 note = rtx_alloc (EXPR_LIST);
4572 PUT_REG_NOTE_KIND (note, REG_DEAD);
4573 XEXP (note, 0) = dest;
4574 XEXP (note, 1) = REG_NOTES (insn);
4575 REG_NOTES (insn) = note;
4576 /* The reg only dies in one insn, the last one
4587 /* If the original dest is modifying a multiple register target, and the
4588 original instruction was split such that the original dest is now set
4589 by two or more SUBREG sets, then the split insns no longer kill the
4590 destination of the original insn.
4592 In this case, if there exists an instruction in the same basic block,
4593 before the split insn, which uses the original dest, and this use is
4594 killed by the original insn, then we must remove the REG_DEAD note on
4595 this insn, because it is now superfluous.
4597 This does not apply when a hard register gets split, because the code
4598 knows how to handle overlapping hard registers properly. */
4599 if (orig_dest && GET_CODE (orig_dest) == REG)
4601 int found_orig_dest = 0;
4602 int found_split_dest = 0;
4604 for (insn = first; ; insn = NEXT_INSN (insn))
4606 set = single_set (insn);
4609 if (GET_CODE (SET_DEST (set)) == REG
4610 && REGNO (SET_DEST (set)) == REGNO (orig_dest))
4612 found_orig_dest = 1;
4615 else if (GET_CODE (SET_DEST (set)) == SUBREG
4616 && SUBREG_REG (SET_DEST (set)) == orig_dest)
4618 found_split_dest = 1;
4627 if (found_split_dest)
4629 /* Search backwards from FIRST, looking for the first insn that uses
4630 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
4631 If we find an insn, and it has a REG_DEAD note, then delete the
4634 for (insn = first; insn; insn = PREV_INSN (insn))
4636 if (GET_CODE (insn) == CODE_LABEL
4637 || GET_CODE (insn) == JUMP_INSN)
4639 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
4640 && reg_mentioned_p (orig_dest, insn))
4642 note = find_regno_note (insn, REG_DEAD, REGNO (orig_dest));
4644 remove_note (insn, note);
4648 else if (! found_orig_dest)
4650 /* This should never happen. */
4655 /* Update reg_n_sets. This is necessary to prevent local alloc from
4656 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
4657 a reg from set once to set multiple times. */
4660 rtx x = PATTERN (orig_insn);
4661 RTX_CODE code = GET_CODE (x);
4663 if (code == SET || code == CLOBBER)
4664 update_n_sets (x, -1);
4665 else if (code == PARALLEL)
4668 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4670 code = GET_CODE (XVECEXP (x, 0, i));
4671 if (code == SET || code == CLOBBER)
4672 update_n_sets (XVECEXP (x, 0, i), -1);
4676 for (insn = first; ; insn = NEXT_INSN (insn))
4679 code = GET_CODE (x);
4681 if (code == SET || code == CLOBBER)
4682 update_n_sets (x, 1);
4683 else if (code == PARALLEL)
4686 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4688 code = GET_CODE (XVECEXP (x, 0, i));
4689 if (code == SET || code == CLOBBER)
4690 update_n_sets (XVECEXP (x, 0, i), 1);
4700 /* The one entry point in this file. DUMP_FILE is the dump file for
4704 schedule_insns (dump_file)
4707 int max_uid = MAX_INSNS_PER_SPLIT * (get_max_uid () + 1);
4711 /* Taking care of this degenerate case makes the rest of
4712 this code simpler. */
4713 if (n_basic_blocks == 0)
4716 /* Create an insn here so that we can hang dependencies off of it later. */
4717 sched_before_next_call
4718 = gen_rtx (INSN, VOIDmode, 0, NULL_RTX, NULL_RTX,
4719 NULL_RTX, 0, NULL_RTX, 0);
4721 /* Initialize the unused_*_lists. We can't use the ones left over from
4722 the previous function, because gcc has freed that memory. We can use
4723 the ones left over from the first sched pass in the second pass however,
4724 so only clear them on the first sched pass. The first pass is before
4725 reload if flag_schedule_insns is set, otherwise it is afterwards. */
4727 if (reload_completed == 0 || ! flag_schedule_insns)
4729 unused_insn_list = 0;
4730 unused_expr_list = 0;
4733 /* We create no insns here, only reorder them, so we
4734 remember how far we can cut back the stack on exit. */
4736 /* Allocate data for this pass. See comments, above,
4737 for what these vectors do. */
4738 insn_luid = (int *) alloca (max_uid * sizeof (int));
4739 insn_priority = (int *) alloca (max_uid * sizeof (int));
4740 insn_tick = (int *) alloca (max_uid * sizeof (int));
4741 insn_costs = (short *) alloca (max_uid * sizeof (short));
4742 insn_units = (short *) alloca (max_uid * sizeof (short));
4743 insn_blockage = (unsigned int *) alloca (max_uid * sizeof (unsigned int));
4744 insn_ref_count = (int *) alloca (max_uid * sizeof (int));
4746 if (reload_completed == 0)
4748 sched_reg_n_deaths = (short *) alloca (max_regno * sizeof (short));
4749 sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int));
4750 sched_reg_live_length = (int *) alloca (max_regno * sizeof (int));
4751 bb_dead_regs = (regset) alloca (regset_bytes);
4752 bb_live_regs = (regset) alloca (regset_bytes);
4753 bzero ((char *) sched_reg_n_calls_crossed, max_regno * sizeof (int));
4754 bzero ((char *) sched_reg_live_length, max_regno * sizeof (int));
4755 bcopy ((char *) reg_n_deaths, (char *) sched_reg_n_deaths,
4756 max_regno * sizeof (short));
4757 init_alias_analysis ();
4761 sched_reg_n_deaths = 0;
4762 sched_reg_n_calls_crossed = 0;
4763 sched_reg_live_length = 0;
4766 if (! flag_schedule_insns)
4767 init_alias_analysis ();
4770 if (write_symbols != NO_DEBUG)
4774 line_note = (rtx *) alloca (max_uid * sizeof (rtx));
4775 bzero ((char *) line_note, max_uid * sizeof (rtx));
4776 line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx));
4777 bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx));
4779 /* Determine the line-number at the start of each basic block.
4780 This must be computed and saved now, because after a basic block's
4781 predecessor has been scheduled, it is impossible to accurately
4782 determine the correct line number for the first insn of the block. */
4784 for (b = 0; b < n_basic_blocks; b++)
4785 for (line = basic_block_head[b]; line; line = PREV_INSN (line))
4786 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4788 line_note_head[b] = line;
4793 bzero ((char *) insn_luid, max_uid * sizeof (int));
4794 bzero ((char *) insn_priority, max_uid * sizeof (int));
4795 bzero ((char *) insn_tick, max_uid * sizeof (int));
4796 bzero ((char *) insn_costs, max_uid * sizeof (short));
4797 bzero ((char *) insn_units, max_uid * sizeof (short));
4798 bzero ((char *) insn_blockage, max_uid * sizeof (unsigned int));
4799 bzero ((char *) insn_ref_count, max_uid * sizeof (int));
4801 /* Schedule each basic block, block by block. */
4803 /* ??? Add a NOTE after the last insn of the last basic block. It is not
4804 known why this is done. */
4806 insn = basic_block_end[n_basic_blocks-1];
4807 if (NEXT_INSN (insn) == 0
4808 || (GET_CODE (insn) != NOTE
4809 && GET_CODE (insn) != CODE_LABEL
4810 /* Don't emit a NOTE if it would end up between an unconditional
4811 jump and a BARRIER. */
4812 && ! (GET_CODE (insn) == JUMP_INSN
4813 && GET_CODE (NEXT_INSN (insn)) == BARRIER)))
4814 emit_note_after (NOTE_INSN_DELETED, basic_block_end[n_basic_blocks-1]);
4816 for (b = 0; b < n_basic_blocks; b++)
4822 for (insn = basic_block_head[b]; ; insn = next)
4827 /* Can't use `next_real_insn' because that
4828 might go across CODE_LABELS and short-out basic blocks. */
4829 next = NEXT_INSN (insn);
4830 if (GET_CODE (insn) != INSN)
4832 if (insn == basic_block_end[b])
4838 /* Don't split no-op move insns. These should silently disappear
4839 later in final. Splitting such insns would break the code
4840 that handles REG_NO_CONFLICT blocks. */
4841 set = single_set (insn);
4842 if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
4844 if (insn == basic_block_end[b])
4847 /* Nops get in the way while scheduling, so delete them now if
4848 register allocation has already been done. It is too risky
4849 to try to do this before register allocation, and there are
4850 unlikely to be very many nops then anyways. */
4851 if (reload_completed)
4853 PUT_CODE (insn, NOTE);
4854 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4855 NOTE_SOURCE_FILE (insn) = 0;
4861 /* Split insns here to get max fine-grain parallelism. */
4862 prev = PREV_INSN (insn);
4863 if (reload_completed == 0)
4865 rtx last, first = PREV_INSN (insn);
4866 rtx notes = REG_NOTES (insn);
4868 last = try_split (PATTERN (insn), insn, 1);
4871 /* try_split returns the NOTE that INSN became. */
4872 first = NEXT_INSN (first);
4873 update_flow_info (notes, first, last, insn);
4875 PUT_CODE (insn, NOTE);
4876 NOTE_SOURCE_FILE (insn) = 0;
4877 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4878 if (insn == basic_block_head[b])
4879 basic_block_head[b] = first;
4880 if (insn == basic_block_end[b])
4882 basic_block_end[b] = last;
4888 if (insn == basic_block_end[b])
4892 schedule_block (b, dump_file);
4899 /* Reposition the prologue and epilogue notes in case we moved the
4900 prologue/epilogue insns. */
4901 if (reload_completed)
4902 reposition_prologue_and_epilogue_notes (get_insns ());
4904 if (write_symbols != NO_DEBUG)
4907 rtx insn = get_insns ();
4908 int active_insn = 0;
4911 /* Walk the insns deleting redundant line-number notes. Many of these
4912 are already present. The remainder tend to occur at basic
4913 block boundaries. */
4914 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
4915 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4917 /* If there are no active insns following, INSN is redundant. */
4918 if (active_insn == 0)
4921 NOTE_SOURCE_FILE (insn) = 0;
4922 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4924 /* If the line number is unchanged, LINE is redundant. */
4926 && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
4927 && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
4930 NOTE_SOURCE_FILE (line) = 0;
4931 NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
4938 else if (! ((GET_CODE (insn) == NOTE
4939 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
4940 || (GET_CODE (insn) == INSN
4941 && (GET_CODE (PATTERN (insn)) == USE
4942 || GET_CODE (PATTERN (insn)) == CLOBBER))))
4945 if (dump_file && notes)
4946 fprintf (dump_file, ";; deleted %d line-number notes\n", notes);
4949 if (reload_completed == 0)
4952 for (regno = 0; regno < max_regno; regno++)
4953 if (sched_reg_live_length[regno])
4957 if (reg_live_length[regno] > sched_reg_live_length[regno])
4959 ";; register %d life shortened from %d to %d\n",
4960 regno, reg_live_length[regno],
4961 sched_reg_live_length[regno]);
4962 /* Negative values are special; don't overwrite the current
4963 reg_live_length value if it is negative. */
4964 else if (reg_live_length[regno] < sched_reg_live_length[regno]
4965 && reg_live_length[regno] >= 0)
4967 ";; register %d life extended from %d to %d\n",
4968 regno, reg_live_length[regno],
4969 sched_reg_live_length[regno]);
4971 if (! reg_n_calls_crossed[regno]
4972 && sched_reg_n_calls_crossed[regno])
4974 ";; register %d now crosses calls\n", regno);
4975 else if (reg_n_calls_crossed[regno]
4976 && ! sched_reg_n_calls_crossed[regno]
4977 && reg_basic_block[regno] != REG_BLOCK_GLOBAL)
4979 ";; register %d no longer crosses calls\n", regno);
4982 /* Negative values are special; don't overwrite the current
4983 reg_live_length value if it is negative. */
4984 if (reg_live_length[regno] >= 0)
4985 reg_live_length[regno] = sched_reg_live_length[regno];
4987 /* We can't change the value of reg_n_calls_crossed to zero for
4988 pseudos which are live in more than one block.
4990 This is because combine might have made an optimization which
4991 invalidated basic_block_live_at_start and reg_n_calls_crossed,
4992 but it does not update them. If we update reg_n_calls_crossed
4993 here, the two variables are now inconsistent, and this might
4994 confuse the caller-save code into saving a register that doesn't
4995 need to be saved. This is only a problem when we zero calls
4996 crossed for a pseudo live in multiple basic blocks.
4998 Alternatively, we could try to correctly update basic block live
4999 at start here in sched, but that seems complicated. */
5000 if (sched_reg_n_calls_crossed[regno]
5001 || reg_basic_block[regno] != REG_BLOCK_GLOBAL)
5002 reg_n_calls_crossed[regno] = sched_reg_n_calls_crossed[regno];
5006 #endif /* INSN_SCHEDULING */