1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999
5 Free Software Foundation, Inc.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
50 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
63 /* ---------------------------------------------------------------------
64 Expressions (and "meta" expressions) used for structuring the
65 rtl representation of a program.
66 --------------------------------------------------------------------- */
68 /* an expression code name unknown to the reader */
69 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
71 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
73 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
75 /* ---------------------------------------------------------------------
76 Expressions used in constructing lists.
77 --------------------------------------------------------------------- */
79 /* a linked list of expressions */
80 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
82 /* a linked list of instructions.
83 The insns are represented in print by their uids. */
84 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
86 /* ----------------------------------------------------------------------
87 Expression types for machine descriptions.
88 These do not appear in actual rtl code in the compiler.
89 ---------------------------------------------------------------------- */
91 /* Appears only in machine descriptions.
92 Means use the function named by the second arg (the string)
93 as a predicate; if matched, store the structure that was matched
94 in the operand table at index specified by the first arg (the integer).
95 If the second arg is the null string, the structure is just stored.
97 A third string argument indicates to the register allocator restrictions
98 on where the operand can be allocated.
100 If the target needs no restriction on any instruction this field should
103 The string is prepended by:
104 '=' to indicate the operand is only written to.
105 '+' to indicate the operand is both read and written to.
107 Each character in the string represents an allocable class for an operand.
108 'g' indicates the operand can be any valid class.
109 'i' indicates the operand can be immediate (in the instruction) data.
110 'r' indicates the operand can be in a register.
111 'm' indicates the operand can be in memory.
112 'o' a subset of the 'm' class. Those memory addressing modes that
113 can be offset at compile time (have a constant added to them).
115 Other characters indicate target dependent operand classes and
116 are described in each target's machine description.
118 For instructions with more than one operand, sets of classes can be
119 separated by a comma to indicate the appropriate multi-operand constraints.
120 There must be a 1 to 1 correspondence between these sets of classes in
121 all operands for an instruction.
123 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
125 /* Appears only in machine descriptions.
126 Means match a SCRATCH or a register. When used to generate rtl, a
127 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
128 the desired mode and the first argument is the operand number.
129 The second argument is the constraint. */
130 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
132 /* Appears only in machine descriptions.
133 Means match only something equal to what is stored in the operand table
134 at the index specified by the argument. */
135 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
137 /* Appears only in machine descriptions.
138 Means apply a predicate, AND match recursively the operands of the rtx.
139 Operand 0 is the operand-number, as in match_operand.
140 Operand 1 is a predicate to apply (as a string, a function name).
141 Operand 2 is a vector of expressions, each of which must match
142 one subexpression of the rtx this construct is matching. */
143 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
145 /* Appears only in machine descriptions.
146 Means to match a PARALLEL of arbitrary length. The predicate is applied
147 to the PARALLEL and the initial expressions in the PARALLEL are matched.
148 Operand 0 is the operand-number, as in match_operand.
149 Operand 1 is a predicate to apply to the PARALLEL.
150 Operand 2 is a vector of expressions, each of which must match the
151 corresponding element in the PARALLEL. */
152 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
154 /* Appears only in machine descriptions.
155 Means match only something equal to what is stored in the operand table
156 at the index specified by the argument. For MATCH_OPERATOR. */
157 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
159 /* Appears only in machine descriptions.
160 Means match only something equal to what is stored in the operand table
161 at the index specified by the argument. For MATCH_PARALLEL. */
162 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
164 /* Appears only in machine descriptions.
165 Should be used only in attribute tests.
166 The predicate in operand 0 is applied to the whole insn being checked. */
167 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "s", 'm')
169 /* Appears only in machine descriptions.
170 Operand 0 is the operand number, as in match_operand.
171 Operand 1 is the predicate to apply to the insn. */
172 DEF_RTL_EXPR(MATCH_INSN2, "match_insn2", "is", 'm')
174 /* Appears only in machine descriptions.
175 Defines the pattern for one kind of instruction.
177 0: names this instruction.
178 If the name is the null string, the instruction is in the
179 machine description just to be recognized, and will never be emitted by
180 the tree to rtl expander.
182 2: is a string which is a C expression
183 giving an additional condition for recognizing this pattern.
184 A null string means no extra condition.
185 3: is the action to execute if this pattern is matched.
186 If this assembler code template starts with a * then it is a fragment of
187 C code to run to decide on a template to use. Otherwise, it is the
189 4: optionally, a vector of attributes for this insn.
191 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
193 /* Definition of a peephole optimization.
194 1st operand: vector of insn patterns to match
195 2nd operand: C expression that must be true
196 3rd operand: template or C code to produce assembler output.
197 4: optionally, a vector of attributes for this insn.
199 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
201 /* Definition of a split operation.
202 1st operand: insn pattern to match
203 2nd operand: C expression that must be true
204 3rd operand: vector of insn patterns to place into a SEQUENCE
205 4th operand: optionally, some C code to execute before generating the
206 insns. This might, for example, create some RTX's and store them in
207 elements of `recog_operand' for use by the vector of insn-patterns.
208 (`operands' is an alias here for `recog_operand'). */
209 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
211 /* Definition of an RTL peephole operation.
212 Follows the same arguments as define_split. */
213 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
215 /* Definition of a combiner pattern.
216 Operands not defined yet. */
217 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
219 /* Define how to generate multiple insns for a standard insn name.
220 1st operand: the insn name.
221 2nd operand: vector of insn-patterns.
222 Use match_operand to substitute an element of `recog_operand'.
223 3rd operand: C expression that must be true for this to be available.
224 This may not test any operands.
225 4th operand: Extra C code to execute before generating the insns.
226 This might, for example, create some RTX's and store them in
227 elements of `recog_operand' for use by the vector of insn-patterns.
228 (`operands' is an alias here for `recog_operand'). */
229 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
231 /* Define a requirement for delay slots.
232 1st operand: Condition involving insn attributes that, if true,
233 indicates that the insn requires the number of delay slots
235 2nd operand: Vector whose length is the three times the number of delay
237 Each entry gives three conditions, each involving attributes.
238 The first must be true for an insn to occupy that delay slot
239 location. The second is true for all insns that can be
240 annulled if the branch is true and the third is true for all
241 insns that can be annulled if the branch is false.
243 Multiple DEFINE_DELAYs may be present. They indicate differing
244 requirements for delay slots. */
245 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
247 /* Define a set of insns that requires a function unit. This means that
248 these insns produce their result after a delay and that there may be
249 restrictions on the number of insns of this type that can be scheduled
252 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
253 Each gives a set of operations and associated delays. The first three
254 operands must be the same for each operation for the same function unit.
256 All delays are specified in cycles.
258 1st operand: Name of function unit (mostly for documentation)
259 2nd operand: Number of identical function units in CPU
260 3rd operand: Total number of simultaneous insns that can execute on this
261 function unit; 0 if unlimited.
262 4th operand: Condition involving insn attribute, that, if true, specifies
263 those insns that this expression applies to.
264 5th operand: Constant delay after which insn result will be
266 6th operand: Delay until next insn can be scheduled on the function unit
267 executing this operation. The meaning depends on whether or
268 not the next operand is supplied.
269 7th operand: If this operand is not specified, the 6th operand gives the
270 number of cycles after the instruction matching the 4th
271 operand begins using the function unit until a subsequent
272 insn can begin. A value of zero should be used for a
273 unit with no issue constraints. If only one operation can
274 be executed a time and the unit is busy for the entire time,
275 the 3rd operand should be specified as 1, the 6th operand
276 should be specified as 0, and the 7th operand should not
279 If this operand is specified, it is a list of attribute
280 expressions. If an insn for which any of these expressions
281 is true is currently executing on the function unit, the
282 issue delay will be given by the 6th operand. Otherwise,
283 the insn can be immediately scheduled (subject to the limit
284 on the number of simultaneous operations executing on the
286 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
288 /* Define attribute computation for `asm' instructions. */
289 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
291 /* SEQUENCE appears in the result of a `gen_...' function
292 for a DEFINE_EXPAND that wants to make several insns.
293 Its elements are the bodies of the insns that should be made.
294 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
295 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
297 /* Refers to the address of its argument.
298 This appears only in machine descriptions, indicating that
299 any expression that would be acceptable as the operand of MEM
300 should be matched. */
301 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
303 /* ----------------------------------------------------------------------
304 Expressions used for insn attributes. These also do not appear in
305 actual rtl code in the compiler.
306 ---------------------------------------------------------------------- */
308 /* Definition of an insn attribute.
309 1st operand: name of the attribute
310 2nd operand: comma-separated list of possible attribute values
311 3rd operand: expression for the default value of the attribute. */
312 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
314 /* Marker for the name of an attribute. */
315 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
317 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
318 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
321 (set_attr "name" "value") is equivalent to
322 (set (attr "name") (const_string "value")) */
323 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
325 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
326 specify that attribute values are to be assigned according to the
329 The following three expressions are equivalent:
331 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
332 (eq_attrq "alternative" "2") (const_string "a2")]
333 (const_string "a3")))
334 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
335 (const_string "a3")])
336 (set_attr "att" "a1,a2,a3")
338 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
340 /* A conditional expression true if the value of the specified attribute of
341 the current insn equals the specified value. The first operand is the
342 attribute name and the second is the comparison value. */
343 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
345 /* A conditional expression which is true if the specified flag is
346 true for the insn being scheduled in reorg.
348 genattr.c defines the following flags which can be tested by
349 (attr_flag "foo") expressions in eligible_for_delay.
351 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
353 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
355 /* ----------------------------------------------------------------------
356 Expression types used for things in the instruction chain.
358 All formats must start with "iuu" to handle the chain.
359 Each insn expression holds an rtl instruction and its semantics
360 during back-end processing.
361 See macros's in "rtl.h" for the meaning of each rtx->fld[].
363 ---------------------------------------------------------------------- */
365 /* An instruction that cannot jump. */
366 DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
368 /* An instruction that can possibly jump.
369 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
370 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
372 /* An instruction that can possibly call a subroutine
373 but which will not change which instruction comes next
374 in the current function.
375 Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
376 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
377 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
379 /* A marker that indicates that control will not flow through. */
380 DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
382 /* Holds a label that is followed by instructions.
384 3: is a number that is unique in the entire compilation.
385 4: is the user-given name of the label, if any.
386 5: is used in jump.c for the use-count of the label.
387 6: is used in flow.c to point to the chain of label_ref's to this label. */
388 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis00", 'x')
390 /* Say where in the code a source line starts, for symbol table's sake.
391 Contains a filename and a line number. Line numbers <= 0 are special:
392 0 is used in a dummy placed at the front of every function
393 just so there will never be a need to delete the first insn;
394 -1 indicates a dummy; insns to be deleted by flow analysis and combining
395 are really changed to NOTEs with a number of -1.
396 -2 means beginning of a name binding contour; output N_LBRAC.
397 -3 means end of a contour; output N_RBRAC. */
398 DEF_RTL_EXPR(NOTE, "note", "iuu0n", 'x')
400 /* ----------------------------------------------------------------------
401 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
402 ---------------------------------------------------------------------- */
404 /* Several operations to be done in parallel. */
405 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
407 /* A string that is passed through to the assembler as input.
408 One can obviously pass comments through by using the
409 assembler comment syntax.
410 These occur in an insn all by themselves as the PATTERN.
411 They also appear inside an ASM_OPERANDS
412 as a convenient way to hold a string. */
413 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
415 /* An assembler instruction with operands.
416 1st operand is the instruction template.
417 2nd operand is the constraint for the output.
418 3rd operand is the number of the output this expression refers to.
419 When an insn stores more than one value, a separate ASM_OPERANDS
420 is made for each output; this integer distinguishes them.
421 4th is a vector of values of input operands.
422 5th is a vector of modes and constraints for the input operands.
423 Each element is an ASM_INPUT containing a constraint string
424 and whose mode indicates the mode of the input operand.
425 6th is the name of the containing source file.
426 7th is the source line number. */
427 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
429 /* A machine-specific operation.
430 1st operand is a vector of operands being used by the operation so that
431 any needed reloads can be done.
432 2nd operand is a unique value saying which of a number of machine-specific
433 operations is to be performed.
434 (Note that the vector must be the first operand because of the way that
435 genrecog.c record positions within an insn.)
436 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
437 or inside an expression. */
438 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
440 /* Similar, but a volatile operation and one which may trap. */
441 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
443 /* Vector of addresses, stored as full words. */
444 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
445 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
447 /* Vector of address differences X0 - BASE, X1 - BASE, ...
448 First operand is BASE; the vector contains the X's.
449 The machine mode of this rtx says how much space to leave
450 for each difference and is adjusted by branch shortening if
451 CASE_VECTOR_SHORTEN_MODE is defined.
452 The third and fourth operands store the target labels with the
453 minimum and maximum addresses respectively.
454 The fifth operand stores flags for use by branch shortening.
455 Set at the start of shorten_branches:
456 min_align: the minimum alignment for any of the target labels.
457 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
458 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
459 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
460 min_after_base: true iff minimum address target label is after BASE.
461 max_after_base: true iff maximum address target label is after BASE.
462 Set by the actual branch shortening process:
463 offset_unsigned: true iff offsets have to be treated as unsigned.
464 scale: scaling that is necessary to make offsets fit into the mode.
466 The third, fourth and fifth operands are only valid when
467 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
470 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
472 /* ----------------------------------------------------------------------
473 At the top level of an instruction (perhaps under PARALLEL).
474 ---------------------------------------------------------------------- */
477 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
478 Operand 2 is the value stored there.
479 ALL assignment must use SET.
480 Instructions that do multiple assignments must use multiple SET,
482 DEF_RTL_EXPR(SET, "set", "ee", 'x')
484 /* Indicate something is used in a way that we don't want to explain.
485 For example, subroutine calls will use the register
486 in which the static chain is passed. */
487 DEF_RTL_EXPR(USE, "use", "e", 'x')
489 /* Indicate something is clobbered in a way that we don't want to explain.
490 For example, subroutine calls will clobber some physical registers
491 (the ones that are by convention not saved). */
492 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
494 /* Call a subroutine.
495 Operand 1 is the address to call.
496 Operand 2 is the number of arguments. */
498 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
500 /* Return from a subroutine. */
502 DEF_RTL_EXPR(RETURN, "return", "", 'x')
505 Operand 1 is the condition.
506 Operand 2 is the trap code.
507 For an unconditional trap, make the condition (const_int 1). */
508 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
510 /* ----------------------------------------------------------------------
511 Primitive values for use in expressions.
512 ---------------------------------------------------------------------- */
514 /* numeric integer constant */
515 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
517 /* numeric floating point constant.
518 Operand 0 ('e') is the MEM that stores this constant in memory, or
519 various other things (see comments at immed_double_const in
521 Operand 1 ('0') is a chain of all CONST_DOUBLEs in use in the
523 Remaining operands hold the actual value. They are all 'w' and
524 there may be from 1 to 4; see rtl.c. */
525 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
527 /* String constant. Used only for attributes right now. */
528 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
530 /* This is used to encapsulate an expression whose value is constant
531 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
532 recognized as a constant operand rather than by arithmetic instructions. */
533 DEF_RTL_EXPR(CONST, "const", "e", 'o')
535 /* A unary `__builtin_constant_p' expression. This RTL code may only be used
536 as an operand of a CONST. This pattern is only emitted during RTL
537 generation and then only if optimize > 0. It is converted by the first
538 CSE pass into the appropriate CONST_INT. */
539 DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
541 /* program counter. Ordinary jumps are represented
542 by a SET whose first operand is (PC). */
543 DEF_RTL_EXPR(PC, "pc", "", 'o')
545 /* A register. The "operand" is the register number, accessed with
546 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
547 than a hardware register is being referred to. The second operand
548 doesn't really exist. Unfortunately, however, the compiler
549 implicitly assumes that a REG can be transformed in place into a
550 MEM, and therefore that a REG is at least as big as a MEM. To
551 avoid this memory overhead, which is likely to be substantial,
552 search for uses of PUT_CODE that turn REGs into MEMs, and fix them
553 somehow. Then, the trailing `0' can be removed here. */
554 DEF_RTL_EXPR(REG, "reg", "i0", 'o')
556 /* A scratch register. This represents a register used only within a
557 single insn. It will be turned into a REG during register allocation
558 or reload unless the constraint indicates that the register won't be
559 needed, in which case it can remain a SCRATCH. This code is
560 marked as having one operand so it can be turned into a REG. */
561 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
563 /* One word of a multi-word value.
564 The first operand is the complete value; the second says which word.
565 The WORDS_BIG_ENDIAN flag controls whether word number 0
566 (as numbered in a SUBREG) is the most or least significant word.
568 This is also used to refer to a value in a different machine mode.
569 For example, it can be used to refer to a SImode value as if it were
570 Qimode, or vice versa. Then the word number is always 0. */
571 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
573 /* This one-argument rtx is used for move instructions
574 that are guaranteed to alter only the low part of a destination.
575 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
576 has an unspecified effect on the high part of REG,
577 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
578 is guaranteed to alter only the bits of REG that are in HImode.
580 The actual instruction used is probably the same in both cases,
581 but the register constraints may be tighter when STRICT_LOW_PART
584 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
586 /* (CONCAT a b) represents the virtual concatenation of a and b
587 to make a value that has as many bits as a and b put together.
588 This is used for complex values. Normally it appears only
589 in DECL_RTLs and during RTL generation, but not in the insn chain. */
590 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
592 /* A memory location; operand is the address. Can be nested inside a
593 VOLATILE. The second operand is the alias set to which this MEM
594 belongs. We use `0' instead of `i' for this field so that the
595 field need not be specified in machine descriptions. */
596 DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
598 /* Reference to an assembler label in the code for this function.
599 The operand is a CODE_LABEL found in the insn chain.
600 The unprinted fields 1 and 2 are used in flow.c for the
601 LABEL_NEXTREF and CONTAINING_INSN. */
602 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
604 /* Reference to a named label: the string that is the first operand,
605 with `_' added implicitly in front.
606 Exception: if the first character explicitly given is `*',
607 to give it to the assembler, remove the `*' and do not add `_'. */
608 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
610 /* The condition code register is represented, in our imagination,
611 as a register holding a value that can be compared to zero.
612 In fact, the machine has already compared them and recorded the
613 results; but instructions that look at the condition code
614 pretend to be looking at the entire value and comparing it. */
615 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
617 /* Reference to the address of a register. Removed by purge_addressof after
618 CSE has elided as many as possible.
619 1st operand: the register we may need the address of.
620 2nd operand: the original pseudo regno we were generated for.
621 3rd operand: the decl for the object in the register, for
624 DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
626 /* =====================================================================
627 A QUEUED expression really points to a member of the queue of instructions
628 to be output later for postincrement/postdecrement.
629 QUEUED expressions never become part of instructions.
630 When a QUEUED expression would be put into an instruction,
631 instead either the incremented variable or a copy of its previous
635 0. the variable to be incremented (a REG rtx).
636 1. the incrementing instruction, or 0 if it hasn't been output yet.
637 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
638 3. the body to use for the incrementing instruction
639 4. the next QUEUED expression in the queue.
640 ====================================================================== */
642 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
644 /* ----------------------------------------------------------------------
645 Expressions for operators in an rtl pattern
646 ---------------------------------------------------------------------- */
648 /* if_then_else. This is used in representing ordinary
649 conditional jump instructions.
654 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
656 /* General conditional. The first operand is a vector composed of pairs of
657 expressions. The first element of each pair is evaluated, in turn.
658 The value of the conditional is the second expression of the first pair
659 whose first expression evaluates non-zero. If none of the expressions is
660 true, the second operand will be used as the value of the conditional.
662 This should be replaced with use of IF_THEN_ELSE. */
663 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
665 /* Comparison, produces a condition code result. */
666 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
669 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
671 /* Operand 0 minus operand 1. */
672 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
674 /* Minus operand 0. */
675 DEF_RTL_EXPR(NEG, "neg", "e", '1')
677 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
679 /* Operand 0 divided by operand 1. */
680 DEF_RTL_EXPR(DIV, "div", "ee", '2')
681 /* Remainder of operand 0 divided by operand 1. */
682 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
684 /* Unsigned divide and remainder. */
685 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
686 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
688 /* Bitwise operations. */
689 DEF_RTL_EXPR(AND, "and", "ee", 'c')
691 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
693 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
695 DEF_RTL_EXPR(NOT, "not", "e", '1')
698 0: value to be shifted.
699 1: number of bits. */
700 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
701 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
703 /* Right shift operations, for machines where these are not the same
704 as left shifting with a negative argument. */
706 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2')
707 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2')
708 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2')
710 /* Minimum and maximum values of two operands. We need both signed and
711 unsigned forms. (We cannot use MIN for SMIN because it conflicts
712 with a macro of the same name.) */
714 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
715 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
716 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
717 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
719 /* These unary operations are used to represent incrementation
720 and decrementation as they occur in memory addresses.
721 The amount of increment or decrement are not represented
722 because they can be understood from the machine-mode of the
723 containing MEM. These operations exist in only two cases:
724 1. pushes onto the stack.
725 2. created automatically by the life_analysis pass in flow.c. */
726 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
727 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
728 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
729 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
731 /* These binary operations are used to represent generic address
732 side-effects in memory addresses, except for simple incrementation
733 or decrementation which use the above operations. They are
734 created automatically by the life_analysis pass in flow.c.
735 (Note that these operators are currently placeholders.) */
736 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'x')
737 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'x')
739 /* Comparison operations. The ordered comparisons exist in two
740 flavors, signed and unsigned. */
741 DEF_RTL_EXPR(NE, "ne", "ee", '<')
742 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
743 DEF_RTL_EXPR(GE, "ge", "ee", '<')
744 DEF_RTL_EXPR(GT, "gt", "ee", '<')
745 DEF_RTL_EXPR(LE, "le", "ee", '<')
746 DEF_RTL_EXPR(LT, "lt", "ee", '<')
747 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
748 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
749 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
750 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
752 /* Represents the result of sign-extending the sole operand.
753 The machine modes of the operand and of the SIGN_EXTEND expression
754 determine how much sign-extension is going on. */
755 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
757 /* Similar for zero-extension (such as unsigned short to int). */
758 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
760 /* Similar but here the operand has a wider mode. */
761 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
763 /* Similar for extending floating-point values (such as SFmode to DFmode). */
764 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
765 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
767 /* Conversion of fixed point operand to floating point value. */
768 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
770 /* With fixed-point machine mode:
771 Conversion of floating point operand to fixed point value.
772 Value is defined only when the operand's value is an integer.
773 With floating-point machine mode (and operand with same mode):
774 Operand is rounded toward zero to produce an integer value
775 represented in floating point. */
776 DEF_RTL_EXPR(FIX, "fix", "e", '1')
778 /* Conversion of unsigned fixed point operand to floating point value. */
779 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
781 /* With fixed-point machine mode:
782 Conversion of floating point operand to *unsigned* fixed point value.
783 Value is defined only when the operand's value is an integer. */
784 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
787 DEF_RTL_EXPR(ABS, "abs", "e", '1')
790 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
792 /* Find first bit that is set.
793 Value is 1 + number of trailing zeros in the arg.,
795 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
797 /* Reference to a signed bit-field of specified size and position.
798 Operand 0 is the memory unit (usually SImode or QImode) which
799 contains the field's first bit. Operand 1 is the width, in bits.
800 Operand 2 is the number of bits in the memory unit before the
801 first bit of this field.
802 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
803 operand 2 counts from the msb of the memory unit.
804 Otherwise, the first bit is the lsb and operand 2 counts from
805 the lsb of the memory unit. */
806 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
808 /* Similar for unsigned bit-field. */
809 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
811 /* For RISC machines. These save memory when splitting insns. */
813 /* HIGH are the high-order bits of a constant expression. */
814 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
816 /* LO_SUM is the sum of a register and the low-order bits
817 of a constant expression. */
818 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
820 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_START insn.
821 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
822 the registers that can be substituted within this range. Operand 3 is the
823 number of calls in the range. Operand 4 is the number of insns in the
824 range. Operand 5 is the unique range number for this range. Operand 6 is
825 the basic block # of the start of the live range. Operand 7 is the basic
826 block # of the end of the live range. Operand 8 is the loop depth. Operand
827 9 is a bitmap of the registers live at the start of the range. Operand 10
828 is a bitmap of the registers live at the end of the range. Operand 11 is
829 marker number for the start of the range. Operand 12 is the marker number
830 for the end of the range. */
831 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
833 /* Registers that can be substituted within the range. Operand 0 is the
834 original pseudo register number. Operand 1 will be filled in with the
835 pseudo register the value is copied for the duration of the range. Operand
836 2 is the number of references within the range to the register. Operand 3
837 is the number of sets or clobbers of the register in the range. Operand 4
838 is the number of deaths the register has. Operand 5 is the copy flags that
839 give the status of whether a copy is needed from the original register to
840 the new register at the beginning of the range, or whether a copy from the
841 new register back to the original at the end of the range. Operand 6 is the
842 live length. Operand 7 is the number of calls that this register is live
843 across. Operand 8 is the symbol node of the variable if the register is a
844 user variable. Operand 9 is the block node that the variable is declared
845 in if the register is a user variable. */
846 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
848 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
849 the different ranges a variable is in where it is copied to a different
850 pseudo register. Operand 1 is the block that the variable is declared in.
851 Operand 2 is the number of distinct ranges. */
852 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
854 /* Information about the registers that are live at the current point. Operand
855 0 is the live bitmap. Operand 1 is the original block number. */
856 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
858 /* A placeholder for a CALL_INSN which may be turned into a normal call,
859 a sibling (tail) call or tail recursion.
861 Immediately after RTL generation, this placeholder will be replaced
862 by the insns to perform the call, sibcall or tail recursion.
864 This RTX has 4 operands. The first three are lists of instructions to
865 perform the call as a normal call, sibling call and tail recursion
866 respectively. The latter two lists may be NULL, the first may never
869 The last operand is the tail recursion CODE_LABEL, which may be NULL if no
870 potential tail recursive calls were found.
872 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
873 after we select a call method. */
874 DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
OSDN Git Service
