1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
50 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
59 "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
64 /* ---------------------------------------------------------------------
65 Expressions (and "meta" expressions) used for structuring the
66 rtl representation of a program.
67 --------------------------------------------------------------------- */
69 /* an expression code name unknown to the reader */
70 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
72 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
74 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
79 DEF_RTL_EXPR(INCLUDE, "include", "s", 'x')
81 /* ---------------------------------------------------------------------
82 Expressions used in constructing lists.
83 --------------------------------------------------------------------- */
85 /* a linked list of expressions */
86 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
88 /* a linked list of instructions.
89 The insns are represented in print by their uids. */
90 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
92 /* ----------------------------------------------------------------------
93 Expression types for machine descriptions.
94 These do not appear in actual rtl code in the compiler.
95 ---------------------------------------------------------------------- */
97 /* Appears only in machine descriptions.
98 Means use the function named by the second arg (the string)
99 as a predicate; if matched, store the structure that was matched
100 in the operand table at index specified by the first arg (the integer).
101 If the second arg is the null string, the structure is just stored.
103 A third string argument indicates to the register allocator restrictions
104 on where the operand can be allocated.
106 If the target needs no restriction on any instruction this field should
109 The string is prepended by:
110 '=' to indicate the operand is only written to.
111 '+' to indicate the operand is both read and written to.
113 Each character in the string represents an allocable class for an operand.
114 'g' indicates the operand can be any valid class.
115 'i' indicates the operand can be immediate (in the instruction) data.
116 'r' indicates the operand can be in a register.
117 'm' indicates the operand can be in memory.
118 'o' a subset of the 'm' class. Those memory addressing modes that
119 can be offset at compile time (have a constant added to them).
121 Other characters indicate target dependent operand classes and
122 are described in each target's machine description.
124 For instructions with more than one operand, sets of classes can be
125 separated by a comma to indicate the appropriate multi-operand constraints.
126 There must be a 1 to 1 correspondence between these sets of classes in
127 all operands for an instruction.
129 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
131 /* Appears only in machine descriptions.
132 Means match a SCRATCH or a register. When used to generate rtl, a
133 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
134 the desired mode and the first argument is the operand number.
135 The second argument is the constraint. */
136 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
138 /* Appears only in machine descriptions.
139 Means match only something equal to what is stored in the operand table
140 at the index specified by the argument. */
141 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
143 /* Appears only in machine descriptions.
144 Means apply a predicate, AND match recursively the operands of the rtx.
145 Operand 0 is the operand-number, as in match_operand.
146 Operand 1 is a predicate to apply (as a string, a function name).
147 Operand 2 is a vector of expressions, each of which must match
148 one subexpression of the rtx this construct is matching. */
149 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
151 /* Appears only in machine descriptions.
152 Means to match a PARALLEL of arbitrary length. The predicate is applied
153 to the PARALLEL and the initial expressions in the PARALLEL are matched.
154 Operand 0 is the operand-number, as in match_operand.
155 Operand 1 is a predicate to apply to the PARALLEL.
156 Operand 2 is a vector of expressions, each of which must match the
157 corresponding element in the PARALLEL. */
158 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
160 /* Appears only in machine descriptions.
161 Means match only something equal to what is stored in the operand table
162 at the index specified by the argument. For MATCH_OPERATOR. */
163 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
165 /* Appears only in machine descriptions.
166 Means match only something equal to what is stored in the operand table
167 at the index specified by the argument. For MATCH_PARALLEL. */
168 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
170 /* Appears only in machine descriptions.
171 Operand 0 is the operand number, as in match_operand.
172 Operand 1 is the predicate to apply to the insn. */
173 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
175 /* Appears only in machine descriptions.
176 Defines the pattern for one kind of instruction.
178 0: names this instruction.
179 If the name is the null string, the instruction is in the
180 machine description just to be recognized, and will never be emitted by
181 the tree to rtl expander.
183 2: is a string which is a C expression
184 giving an additional condition for recognizing this pattern.
185 A null string means no extra condition.
186 3: is the action to execute if this pattern is matched.
187 If this assembler code template starts with a * then it is a fragment of
188 C code to run to decide on a template to use. Otherwise, it is the
190 4: optionally, a vector of attributes for this insn.
192 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x')
194 /* Definition of a peephole optimization.
195 1st operand: vector of insn patterns to match
196 2nd operand: C expression that must be true
197 3rd operand: template or C code to produce assembler output.
198 4: optionally, a vector of attributes for this insn.
200 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x')
202 /* Definition of a split operation.
203 1st operand: insn pattern to match
204 2nd operand: C expression that must be true
205 3rd operand: vector of insn patterns to place into a SEQUENCE
206 4th operand: optionally, some C code to execute before generating the
207 insns. This might, for example, create some RTX's and store them in
208 elements of `recog_data.operand' for use by the vector of
210 (`operands' is an alias here for `recog_data.operand'). */
211 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
213 /* Definition of an insn and associated split.
214 This is the concatenation, with a few modifications, of a define_insn
215 and a define_split which share the same pattern.
217 0: names this instruction.
218 If the name is the null string, the instruction is in the
219 machine description just to be recognized, and will never be emitted by
220 the tree to rtl expander.
222 2: is a string which is a C expression
223 giving an additional condition for recognizing this pattern.
224 A null string means no extra condition.
225 3: is the action to execute if this pattern is matched.
226 If this assembler code template starts with a * then it is a fragment of
227 C code to run to decide on a template to use. Otherwise, it is the
229 4: C expression that must be true for split. This may start with "&&"
230 in which case the split condition is the logical and of the insn
231 condition and what follows the "&&" of this operand.
232 5: vector of insn patterns to place into a SEQUENCE
233 6: optionally, some C code to execute before generating the
234 insns. This might, for example, create some RTX's and store them in
235 elements of `recog_data.operand' for use by the vector of
237 (`operands' is an alias here for `recog_data.operand').
238 7: optionally, a vector of attributes for this insn. */
239 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x')
241 /* Definition of an RTL peephole operation.
242 Follows the same arguments as define_split. */
243 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
245 /* Define how to generate multiple insns for a standard insn name.
246 1st operand: the insn name.
247 2nd operand: vector of insn-patterns.
248 Use match_operand to substitute an element of `recog_data.operand'.
249 3rd operand: C expression that must be true for this to be available.
250 This may not test any operands.
251 4th operand: Extra C code to execute before generating the insns.
252 This might, for example, create some RTX's and store them in
253 elements of `recog_data.operand' for use by the vector of
255 (`operands' is an alias here for `recog_data.operand'). */
256 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
258 /* Define a requirement for delay slots.
259 1st operand: Condition involving insn attributes that, if true,
260 indicates that the insn requires the number of delay slots
262 2nd operand: Vector whose length is the three times the number of delay
264 Each entry gives three conditions, each involving attributes.
265 The first must be true for an insn to occupy that delay slot
266 location. The second is true for all insns that can be
267 annulled if the branch is true and the third is true for all
268 insns that can be annulled if the branch is false.
270 Multiple DEFINE_DELAYs may be present. They indicate differing
271 requirements for delay slots. */
272 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
274 /* Define a set of insns that requires a function unit. This means that
275 these insns produce their result after a delay and that there may be
276 restrictions on the number of insns of this type that can be scheduled
279 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
280 Each gives a set of operations and associated delays. The first three
281 operands must be the same for each operation for the same function unit.
283 All delays are specified in cycles.
285 1st operand: Name of function unit (mostly for documentation)
286 2nd operand: Number of identical function units in CPU
287 3rd operand: Total number of simultaneous insns that can execute on this
288 function unit; 0 if unlimited.
289 4th operand: Condition involving insn attribute, that, if true, specifies
290 those insns that this expression applies to.
291 5th operand: Constant delay after which insn result will be
293 6th operand: Delay until next insn can be scheduled on the function unit
294 executing this operation. The meaning depends on whether or
295 not the next operand is supplied.
296 7th operand: If this operand is not specified, the 6th operand gives the
297 number of cycles after the instruction matching the 4th
298 operand begins using the function unit until a subsequent
299 insn can begin. A value of zero should be used for a
300 unit with no issue constraints. If only one operation can
301 be executed a time and the unit is busy for the entire time,
302 the 3rd operand should be specified as 1, the 6th operand
303 should be specified as 0, and the 7th operand should not
306 If this operand is specified, it is a list of attribute
307 expressions. If an insn for which any of these expressions
308 is true is currently executing on the function unit, the
309 issue delay will be given by the 6th operand. Otherwise,
310 the insn can be immediately scheduled (subject to the limit
311 on the number of simultaneous operations executing on the
313 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
315 /* Define attribute computation for `asm' instructions. */
316 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
318 /* Definition of a conditional execution meta operation. Automatically
319 generates new instances of DEFINE_INSN, selected by having attribute
320 "predicable" true. The new pattern will contain a COND_EXEC and the
321 predicate at top-level.
324 0: The predicate pattern. The top-level form should match a
325 relational operator. Operands should have only one alternative.
326 1: A C expression giving an additional condition for recognizing
327 the generated pattern.
328 2: A template or C code to produce assembler output. */
329 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
331 /* SEQUENCE appears in the result of a `gen_...' function
332 for a DEFINE_EXPAND that wants to make several insns.
333 Its elements are the bodies of the insns that should be made.
334 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
335 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
337 /* Refers to the address of its argument. This is only used in alias.c. */
338 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
340 /* ----------------------------------------------------------------------
341 Constructions for CPU pipeline description described by NDFAs.
342 These do not appear in actual rtl code in the compiler.
343 ---------------------------------------------------------------------- */
345 /* (define_cpu_unit string [string]) describes cpu functional
346 units (separated by comma).
348 1st operand: Names of cpu functional units.
349 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
351 All define_reservations, define_cpu_units, and
352 define_query_cpu_units should have unique names which may not be
354 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x')
356 /* (define_query_cpu_unit string [string]) describes cpu functional
357 units analogously to define_cpu_unit. The reservation of such
358 units can be queried for automaton state. */
359 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x')
361 /* (exclusion_set string string) means that each CPU functional unit
362 in the first string can not be reserved simultaneously with any
363 unit whose name is in the second string and vise versa. CPU units
364 in the string are separated by commas. For example, it is useful
365 for description CPU with fully pipelined floating point functional
366 unit which can execute simultaneously only single floating point
367 insns or only double floating point insns. All CPU functional
368 units in a set should belong to the same automaton. */
369 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x')
371 /* (presence_set string string) means that each CPU functional unit in
372 the first string can not be reserved unless at least one of pattern
373 of units whose names are in the second string is reserved. This is
374 an asymmetric relation. CPU units or unit patterns in the strings
375 are separated by commas. Pattern is one unit name or unit names
376 separated by white-spaces.
378 For example, it is useful for description that slot1 is reserved
379 after slot0 reservation for a VLIW processor. We could describe it
380 by the following construction
382 (presence_set "slot1" "slot0")
384 Or slot1 is reserved only after slot0 and unit b0 reservation. In
385 this case we could write
387 (presence_set "slot1" "slot0 b0")
389 All CPU functional units in a set should belong to the same
391 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x')
393 /* (final_presence_set string string) is analogous to `presence_set'.
394 The difference between them is when checking is done. When an
395 instruction is issued in given automaton state reflecting all
396 current and planned unit reservations, the automaton state is
397 changed. The first state is a source state, the second one is a
398 result state. Checking for `presence_set' is done on the source
399 state reservation, checking for `final_presence_set' is done on the
400 result reservation. This construction is useful to describe a
401 reservation which is actually two subsequent reservations. For
404 (presence_set "slot1" "slot0")
406 the following insn will be never issued (because slot1 requires
407 slot0 which is absent in the source state).
409 (define_reservation "insn_and_nop" "slot0 + slot1")
411 but it can be issued if we use analogous `final_presence_set'. */
412 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", 'x')
414 /* (absence_set string string) means that each CPU functional unit in
415 the first string can be reserved only if each pattern of units
416 whose names are in the second string is not reserved. This is an
417 asymmetric relation (actually exclusion set is analogous to this
418 one but it is symmetric). CPU units or unit patterns in the string
419 are separated by commas. Pattern is one unit name or unit names
420 separated by white-spaces.
422 For example, it is useful for description that slot0 can not be
423 reserved after slot1 or slot2 reservation for a VLIW processor. We
424 could describe it by the following construction
426 (absence_set "slot2" "slot0, slot1")
428 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
429 slot1 and unit b1 are reserved . In this case we could write
431 (absence_set "slot2" "slot0 b0, slot1 b1")
433 All CPU functional units in a set should to belong the same
435 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x')
437 /* (final_absence_set string string) is analogous to `absence_set' but
438 checking is done on the result (state) reservation. See comments
439 for `final_presence_set'. */
440 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", 'x')
442 /* (define_bypass number out_insn_names in_insn_names) names bypass
443 with given latency (the first number) from insns given by the first
444 string (see define_insn_reservation) into insns given by the second
445 string. Insn names in the strings are separated by commas. The
446 third operand is optional name of function which is additional
447 guard for the bypass. The function will get the two insns as
448 parameters. If the function returns zero the bypass will be
449 ignored for this case. Additional guard is necessary to recognize
450 complicated bypasses, e.g. when consumer is load address. */
451 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", 'x')
453 /* (define_automaton string) describes names of automata generated and
454 used for pipeline hazards recognition. The names are separated by
455 comma. Actually it is possibly to generate the single automaton
456 but unfortunately it can be very large. If we use more one
457 automata, the summary size of the automata usually is less than the
458 single one. The automaton name is used in define_cpu_unit and
459 define_query_cpu_unit. All automata should have unique names. */
460 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", 'x')
462 /* (automata_option string) describes option for generation of
463 automata. Currently there are the following options:
465 o "no-minimization" which makes no minimization of automata. This
466 is only worth to do when we are debugging the description and
467 need to look more accurately at reservations of states.
469 o "time" which means printing additional time statistics about
470 generation of automata.
472 o "v" which means generation of file describing the result
473 automata. The file has suffix `.dfa' and can be used for the
474 description verification and debugging.
476 o "w" which means generation of warning instead of error for
479 o "ndfa" which makes nondeterministic finite state automata.
481 o "progress" which means output of a progress bar showing how many
482 states were generated so far for automaton being processed. */
483 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", 'x')
485 /* (define_reservation string string) names reservation (the first
486 string) of cpu functional units (the 2nd string). Sometimes unit
487 reservations for different insns contain common parts. In such
488 case, you can describe common part and use its name (the 1st
489 parameter) in regular expression in define_insn_reservation. All
490 define_reservations, define_cpu_units, and define_query_cpu_units
491 should have unique names which may not be "nothing". */
492 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", 'x')
494 /* (define_insn_reservation name default_latency condition regexpr)
495 describes reservation of cpu functional units (the 3nd operand) for
496 instruction which is selected by the condition (the 2nd parameter).
497 The first parameter is used for output of debugging information.
498 The reservations are described by a regular expression according
499 the following syntax:
501 regexp = regexp "," oneof
504 oneof = oneof "|" allof
507 allof = allof "+" repeat
510 repeat = element "*" number
513 element = cpu_function_unit_name
519 1. "," is used for describing start of the next cycle in
522 2. "|" is used for describing the reservation described by the
523 first regular expression *or* the reservation described by the
524 second regular expression *or* etc.
526 3. "+" is used for describing the reservation described by the
527 first regular expression *and* the reservation described by the
528 second regular expression *and* etc.
530 4. "*" is used for convenience and simply means sequence in
531 which the regular expression are repeated NUMBER times with
532 cycle advancing (see ",").
534 5. cpu functional unit name which means its reservation.
536 6. reservation name -- see define_reservation.
538 7. string "nothing" means no units reservation. */
540 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", 'x')
542 /* ----------------------------------------------------------------------
543 Expressions used for insn attributes. These also do not appear in
544 actual rtl code in the compiler.
545 ---------------------------------------------------------------------- */
547 /* Definition of an insn attribute.
548 1st operand: name of the attribute
549 2nd operand: comma-separated list of possible attribute values
550 3rd operand: expression for the default value of the attribute. */
551 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
553 /* Marker for the name of an attribute. */
554 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
556 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
557 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
560 (set_attr "name" "value") is equivalent to
561 (set (attr "name") (const_string "value")) */
562 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
564 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
565 specify that attribute values are to be assigned according to the
568 The following three expressions are equivalent:
570 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
571 (eq_attrq "alternative" "2") (const_string "a2")]
572 (const_string "a3")))
573 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
574 (const_string "a3")])
575 (set_attr "att" "a1,a2,a3")
577 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
579 /* A conditional expression true if the value of the specified attribute of
580 the current insn equals the specified value. The first operand is the
581 attribute name and the second is the comparison value. */
582 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
584 /* A special case of the above representing a set of alternatives. The first
585 operand is bitmap of the set, the second one is the default value. */
586 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", 'x')
588 /* A conditional expression which is true if the specified flag is
589 true for the insn being scheduled in reorg.
591 genattr.c defines the following flags which can be tested by
592 (attr_flag "foo") expressions in eligible_for_delay.
594 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
596 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
598 /* ----------------------------------------------------------------------
599 Expression types used for things in the instruction chain.
601 All formats must start with "iuu" to handle the chain.
602 Each insn expression holds an rtl instruction and its semantics
603 during back-end processing.
604 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
606 ---------------------------------------------------------------------- */
608 /* An instruction that cannot jump. */
609 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", 'i')
611 /* An instruction that can possibly jump.
612 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
613 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", 'i')
615 /* An instruction that can possibly call a subroutine
616 but which will not change which instruction comes next
617 in the current function.
618 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
619 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
620 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", 'i')
622 /* A marker that indicates that control will not flow through. */
623 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", 'x')
625 /* Holds a label that is followed by instructions.
627 4: is used in jump.c for the use-count of the label.
628 5: is used in flow.c to point to the chain of label_ref's to this label.
629 6: is a number that is unique in the entire compilation.
630 7: is the user-given name of the label, if any. */
631 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", 'x')
633 /* Say where in the code a source line starts, for symbol table's sake.
635 4: filename, if line number > 0, note-specific data otherwise.
636 5: line number if > 0, enum note_insn otherwise.
637 6: unique number if line number == note_insn_deleted_label. */
638 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", 'x')
640 /* ----------------------------------------------------------------------
641 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
642 ---------------------------------------------------------------------- */
644 /* Conditionally execute code.
645 Operand 0 is the condition that if true, the code is executed.
646 Operand 1 is the code to be executed (typically a SET).
648 Semantics are that there are no side effects if the condition
649 is false. This pattern is created automatically by the if_convert
650 pass run after reload or by target-specific splitters. */
651 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
653 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
654 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
656 /* A string that is passed through to the assembler as input.
657 One can obviously pass comments through by using the
658 assembler comment syntax.
659 These occur in an insn all by themselves as the PATTERN.
660 They also appear inside an ASM_OPERANDS
661 as a convenient way to hold a string. */
662 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
664 /* An assembler instruction with operands.
665 1st operand is the instruction template.
666 2nd operand is the constraint for the output.
667 3rd operand is the number of the output this expression refers to.
668 When an insn stores more than one value, a separate ASM_OPERANDS
669 is made for each output; this integer distinguishes them.
670 4th is a vector of values of input operands.
671 5th is a vector of modes and constraints for the input operands.
672 Each element is an ASM_INPUT containing a constraint string
673 and whose mode indicates the mode of the input operand.
674 6th is the name of the containing source file.
675 7th is the source line number. */
676 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
678 /* A machine-specific operation.
679 1st operand is a vector of operands being used by the operation so that
680 any needed reloads can be done.
681 2nd operand is a unique value saying which of a number of machine-specific
682 operations is to be performed.
683 (Note that the vector must be the first operand because of the way that
684 genrecog.c record positions within an insn.)
685 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
686 or inside an expression. */
687 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
689 /* Similar, but a volatile operation and one which may trap. */
690 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
692 /* Vector of addresses, stored as full words. */
693 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
694 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
696 /* Vector of address differences X0 - BASE, X1 - BASE, ...
697 First operand is BASE; the vector contains the X's.
698 The machine mode of this rtx says how much space to leave
699 for each difference and is adjusted by branch shortening if
700 CASE_VECTOR_SHORTEN_MODE is defined.
701 The third and fourth operands store the target labels with the
702 minimum and maximum addresses respectively.
703 The fifth operand stores flags for use by branch shortening.
704 Set at the start of shorten_branches:
705 min_align: the minimum alignment for any of the target labels.
706 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
707 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
708 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
709 min_after_base: true iff minimum address target label is after BASE.
710 max_after_base: true iff maximum address target label is after BASE.
711 Set by the actual branch shortening process:
712 offset_unsigned: true iff offsets have to be treated as unsigned.
713 scale: scaling that is necessary to make offsets fit into the mode.
715 The third, fourth and fifth operands are only valid when
716 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
719 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
721 /* Memory prefetch, with attributes supported on some targets.
722 Operand 1 is the address of the memory to fetch.
723 Operand 2 is 1 for a write access, 0 otherwise.
724 Operand 3 is the level of temporal locality; 0 means there is no
725 temporal locality and 1, 2, and 3 are for increasing levels of temporal
728 The attributes specified by operands 2 and 3 are ignored for targets
729 whose prefetch instructions do not support them. */
730 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x')
732 /* ----------------------------------------------------------------------
733 At the top level of an instruction (perhaps under PARALLEL).
734 ---------------------------------------------------------------------- */
737 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
738 Operand 2 is the value stored there.
739 ALL assignment must use SET.
740 Instructions that do multiple assignments must use multiple SET,
742 DEF_RTL_EXPR(SET, "set", "ee", 'x')
744 /* Indicate something is used in a way that we don't want to explain.
745 For example, subroutine calls will use the register
746 in which the static chain is passed. */
747 DEF_RTL_EXPR(USE, "use", "e", 'x')
749 /* Indicate something is clobbered in a way that we don't want to explain.
750 For example, subroutine calls will clobber some physical registers
751 (the ones that are by convention not saved). */
752 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
754 /* Call a subroutine.
755 Operand 1 is the address to call.
756 Operand 2 is the number of arguments. */
758 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
760 /* Return from a subroutine. */
762 DEF_RTL_EXPR(RETURN, "return", "", 'x')
765 Operand 1 is the condition.
766 Operand 2 is the trap code.
767 For an unconditional trap, make the condition (const_int 1). */
768 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
770 /* Placeholder for _Unwind_Resume before we know if a function call
771 or a branch is needed. Operand 1 is the exception region from
772 which control is flowing. */
773 DEF_RTL_EXPR(RESX, "resx", "i", 'x')
775 /* ----------------------------------------------------------------------
776 Primitive values for use in expressions.
777 ---------------------------------------------------------------------- */
779 /* numeric integer constant */
780 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
782 /* numeric floating point constant.
783 Operands hold the value. They are all 'w' and there may be from 2 to 6;
785 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
787 /* Describes a vector constant. */
788 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x')
790 /* String constant. Used only for attributes right now. */
791 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
793 /* This is used to encapsulate an expression whose value is constant
794 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
795 recognized as a constant operand rather than by arithmetic instructions. */
797 DEF_RTL_EXPR(CONST, "const", "e", 'o')
799 /* program counter. Ordinary jumps are represented
800 by a SET whose first operand is (PC). */
801 DEF_RTL_EXPR(PC, "pc", "", 'o')
803 /* Used in the cselib routines to describe a value. */
804 DEF_RTL_EXPR(VALUE, "value", "0", 'o')
806 /* A register. The "operand" is the register number, accessed with
807 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
808 than a hardware register is being referred to. The second operand
809 holds the original register number - this will be different for a
810 pseudo register that got turned into a hard register.
811 This rtx needs to have as many (or more) fields as a MEM, since we
812 can change REG rtx's into MEMs during reload. */
813 DEF_RTL_EXPR(REG, "reg", "i00", 'o')
815 /* A scratch register. This represents a register used only within a
816 single insn. It will be turned into a REG during register allocation
817 or reload unless the constraint indicates that the register won't be
818 needed, in which case it can remain a SCRATCH. This code is
819 marked as having one operand so it can be turned into a REG. */
820 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
822 /* One word of a multi-word value.
823 The first operand is the complete value; the second says which word.
824 The WORDS_BIG_ENDIAN flag controls whether word number 0
825 (as numbered in a SUBREG) is the most or least significant word.
827 This is also used to refer to a value in a different machine mode.
828 For example, it can be used to refer to a SImode value as if it were
829 Qimode, or vice versa. Then the word number is always 0. */
830 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
832 /* This one-argument rtx is used for move instructions
833 that are guaranteed to alter only the low part of a destination.
834 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
835 has an unspecified effect on the high part of REG,
836 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
837 is guaranteed to alter only the bits of REG that are in HImode.
839 The actual instruction used is probably the same in both cases,
840 but the register constraints may be tighter when STRICT_LOW_PART
843 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
845 /* (CONCAT a b) represents the virtual concatenation of a and b
846 to make a value that has as many bits as a and b put together.
847 This is used for complex values. Normally it appears only
848 in DECL_RTLs and during RTL generation, but not in the insn chain. */
849 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
851 /* A memory location; operand is the address. The second operand is the
852 alias set to which this MEM belongs. We use `0' instead of `w' for this
853 field so that the field need not be specified in machine descriptions. */
854 DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
856 /* Reference to an assembler label in the code for this function.
857 The operand is a CODE_LABEL found in the insn chain.
858 The unprinted fields 1 and 2 are used in flow.c for the
859 LABEL_NEXTREF and CONTAINING_INSN. */
860 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
862 /* Reference to a named label:
863 Operand 0: label name
864 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
865 Operand 2: tree from which this symbol is derived, or null.
866 This is either a DECL node, or some kind of constant. */
867 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", 'o')
869 /* The condition code register is represented, in our imagination,
870 as a register holding a value that can be compared to zero.
871 In fact, the machine has already compared them and recorded the
872 results; but instructions that look at the condition code
873 pretend to be looking at the entire value and comparing it. */
874 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
876 /* Reference to the address of a register. Removed by purge_addressof after
877 CSE has elided as many as possible.
878 1st operand: the register we may need the address of.
879 2nd operand: the original pseudo regno we were generated for.
880 3rd operand: the decl for the object in the register, for
883 DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
885 /* =====================================================================
886 A QUEUED expression really points to a member of the queue of instructions
887 to be output later for postincrement/postdecrement.
888 QUEUED expressions never become part of instructions.
889 When a QUEUED expression would be put into an instruction,
890 instead either the incremented variable or a copy of its previous
894 0. the variable to be incremented (a REG rtx).
895 1. the incrementing instruction, or 0 if it hasn't been output yet.
896 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
897 3. the body to use for the incrementing instruction
898 4. the next QUEUED expression in the queue.
899 ====================================================================== */
901 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
903 /* ----------------------------------------------------------------------
904 Expressions for operators in an rtl pattern
905 ---------------------------------------------------------------------- */
907 /* if_then_else. This is used in representing ordinary
908 conditional jump instructions.
913 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
915 /* General conditional. The first operand is a vector composed of pairs of
916 expressions. The first element of each pair is evaluated, in turn.
917 The value of the conditional is the second expression of the first pair
918 whose first expression evaluates nonzero. If none of the expressions is
919 true, the second operand will be used as the value of the conditional.
921 This should be replaced with use of IF_THEN_ELSE. */
922 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
924 /* Comparison, produces a condition code result. */
925 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
928 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
930 /* Operand 0 minus operand 1. */
931 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
933 /* Minus operand 0. */
934 DEF_RTL_EXPR(NEG, "neg", "e", '1')
936 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
938 /* Operand 0 divided by operand 1. */
939 DEF_RTL_EXPR(DIV, "div", "ee", '2')
940 /* Remainder of operand 0 divided by operand 1. */
941 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
943 /* Unsigned divide and remainder. */
944 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
945 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
947 /* Bitwise operations. */
948 DEF_RTL_EXPR(AND, "and", "ee", 'c')
950 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
952 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
954 DEF_RTL_EXPR(NOT, "not", "e", '1')
957 0: value to be shifted.
958 1: number of bits. */
959 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
960 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
961 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
962 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
963 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
965 /* Minimum and maximum values of two operands. We need both signed and
966 unsigned forms. (We cannot use MIN for SMIN because it conflicts
967 with a macro of the same name.) */
969 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
970 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
971 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
972 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
974 /* These unary operations are used to represent incrementation
975 and decrementation as they occur in memory addresses.
976 The amount of increment or decrement are not represented
977 because they can be understood from the machine-mode of the
978 containing MEM. These operations exist in only two cases:
979 1. pushes onto the stack.
980 2. created automatically by the life_analysis pass in flow.c. */
981 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
982 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
983 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
984 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
986 /* These binary operations are used to represent generic address
987 side-effects in memory addresses, except for simple incrementation
988 or decrementation which use the above operations. They are
989 created automatically by the life_analysis pass in flow.c.
990 The first operand is a REG which is used as the address.
991 The second operand is an expression that is assigned to the
992 register, either before (PRE_MODIFY) or after (POST_MODIFY)
993 evaluating the address.
994 Currently, the compiler can only handle second operands of the
995 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
996 the first operand of the PLUS has to be the same register as
997 the first operand of the *_MODIFY. */
998 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
999 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
1001 /* Comparison operations. The ordered comparisons exist in two
1002 flavors, signed and unsigned. */
1003 DEF_RTL_EXPR(NE, "ne", "ee", '<')
1004 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
1005 DEF_RTL_EXPR(GE, "ge", "ee", '<')
1006 DEF_RTL_EXPR(GT, "gt", "ee", '<')
1007 DEF_RTL_EXPR(LE, "le", "ee", '<')
1008 DEF_RTL_EXPR(LT, "lt", "ee", '<')
1009 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
1010 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
1011 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
1012 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
1014 /* Additional floating point unordered comparison flavors. */
1015 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
1016 DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
1018 /* These are equivalent to unordered or ... */
1019 DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
1020 DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
1021 DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
1022 DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
1023 DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
1025 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
1026 DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
1028 /* Represents the result of sign-extending the sole operand.
1029 The machine modes of the operand and of the SIGN_EXTEND expression
1030 determine how much sign-extension is going on. */
1031 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
1033 /* Similar for zero-extension (such as unsigned short to int). */
1034 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
1036 /* Similar but here the operand has a wider mode. */
1037 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
1039 /* Similar for extending floating-point values (such as SFmode to DFmode). */
1040 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
1041 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
1043 /* Conversion of fixed point operand to floating point value. */
1044 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
1046 /* With fixed-point machine mode:
1047 Conversion of floating point operand to fixed point value.
1048 Value is defined only when the operand's value is an integer.
1049 With floating-point machine mode (and operand with same mode):
1050 Operand is rounded toward zero to produce an integer value
1051 represented in floating point. */
1052 DEF_RTL_EXPR(FIX, "fix", "e", '1')
1054 /* Conversion of unsigned fixed point operand to floating point value. */
1055 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
1057 /* With fixed-point machine mode:
1058 Conversion of floating point operand to *unsigned* fixed point value.
1059 Value is defined only when the operand's value is an integer. */
1060 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
1062 /* Absolute value */
1063 DEF_RTL_EXPR(ABS, "abs", "e", '1')
1066 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
1068 /* Find first bit that is set.
1069 Value is 1 + number of trailing zeros in the arg.,
1070 or 0 if arg is 0. */
1071 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
1073 /* Count leading zeros. */
1074 DEF_RTL_EXPR(CLZ, "clz", "e", '1')
1076 /* Count trailing zeros. */
1077 DEF_RTL_EXPR(CTZ, "ctz", "e", '1')
1079 /* Population count (number of 1 bits). */
1080 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", '1')
1082 /* Population parity (number of 1 bits modulo 2). */
1083 DEF_RTL_EXPR(PARITY, "parity", "e", '1')
1085 /* Reference to a signed bit-field of specified size and position.
1086 Operand 0 is the memory unit (usually SImode or QImode) which
1087 contains the field's first bit. Operand 1 is the width, in bits.
1088 Operand 2 is the number of bits in the memory unit before the
1089 first bit of this field.
1090 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
1091 operand 2 counts from the msb of the memory unit.
1092 Otherwise, the first bit is the lsb and operand 2 counts from
1093 the lsb of the memory unit. */
1094 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
1096 /* Similar for unsigned bit-field. */
1097 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
1099 /* For RISC machines. These save memory when splitting insns. */
1101 /* HIGH are the high-order bits of a constant expression. */
1102 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
1104 /* LO_SUM is the sum of a register and the low-order bits
1105 of a constant expression. */
1106 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
1108 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
1109 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
1110 the registers that can be substituted within this range. Operand 3 is the
1111 number of calls in the range. Operand 4 is the number of insns in the
1112 range. Operand 5 is the unique range number for this range. Operand 6 is
1113 the basic block # of the start of the live range. Operand 7 is the basic
1114 block # of the end of the live range. Operand 8 is the loop depth. Operand
1115 9 is a bitmap of the registers live at the start of the range. Operand 10
1116 is a bitmap of the registers live at the end of the range. Operand 11 is
1117 marker number for the start of the range. Operand 12 is the marker number
1118 for the end of the range. */
1119 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
1121 /* Registers that can be substituted within the range. Operand 0 is the
1122 original pseudo register number. Operand 1 will be filled in with the
1123 pseudo register the value is copied for the duration of the range. Operand
1124 2 is the number of references within the range to the register. Operand 3
1125 is the number of sets or clobbers of the register in the range. Operand 4
1126 is the number of deaths the register has. Operand 5 is the copy flags that
1127 give the status of whether a copy is needed from the original register to
1128 the new register at the beginning of the range, or whether a copy from the
1129 new register back to the original at the end of the range. Operand 6 is the
1130 live length. Operand 7 is the number of calls that this register is live
1131 across. Operand 8 is the symbol node of the variable if the register is a
1132 user variable. Operand 9 is the block node that the variable is declared
1133 in if the register is a user variable. */
1134 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
1136 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
1137 the different ranges a variable is in where it is copied to a different
1138 pseudo register. Operand 1 is the block that the variable is declared in.
1139 Operand 2 is the number of distinct ranges. */
1140 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
1142 /* Information about the registers that are live at the current point. Operand
1143 0 is the live bitmap. Operand 1 is the original block number. */
1144 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
1146 /* A unary `__builtin_constant_p' expression. These are only emitted
1147 during RTL generation, and then only if optimize > 0. They are
1148 eliminated by the first CSE pass. */
1149 DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
1151 /* A placeholder for a CALL_INSN which may be turned into a normal call,
1152 a sibling (tail) call or tail recursion.
1154 Immediately after RTL generation, this placeholder will be replaced
1155 by the insns to perform the call, sibcall or tail recursion.
1157 This RTX has 4 operands. The first three are lists of instructions to
1158 perform the call as a normal call, sibling call and tail recursion
1159 respectively. The latter two lists may be NULL, the first may never
1162 The last operand is the tail recursion CODE_LABEL, which may be NULL if no
1163 potential tail recursive calls were found.
1165 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
1166 after we select a call method.
1168 This method of tail-call elimination is intended to be replaced by
1169 tree-based optimizations once front-end conversions are complete. */
1170 DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
1172 /* Describes a merge operation between two vector values.
1173 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
1174 that specifies where the parts of the result are taken from. Set bits
1175 indicate operand 0, clear bits indicate operand 1. The parts are defined
1176 by the mode of the vectors. */
1177 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", '3')
1179 /* Describes an operation that selects parts of a vector.
1180 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
1181 a CONST_INT for each of the subparts of the result vector, giving the
1182 number of the source subpart that should be stored into it. */
1183 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", '2')
1185 /* Describes a vector concat operation. Operands 0 and 1 are the source
1186 vectors, the result is a vector that is as long as operands 0 and 1
1187 combined and is the concatenation of the two source vectors. */
1188 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", '2')
1190 /* Describes an operation that converts a small vector into a larger one by
1191 duplicating the input values. The output vector mode must have the same
1192 submodes as the input vector mode, and the number of output parts must be
1193 an integer multiple of the number of input parts. */
1194 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", '1')
1196 /* Addition with signed saturation */
1197 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
1199 /* Addition with unsigned saturation */
1200 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
1202 /* Operand 0 minus operand 1, with signed saturation. */
1203 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
1205 /* Operand 0 minus operand 1, with unsigned saturation. */
1206 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
1208 /* Signed saturating truncate. */
1209 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
1211 /* Unsigned saturating truncate. */
1212 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
1214 /* Information about the variable and its location. */
1215 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", 'x')
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