1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* ---------------------------------------------------------------------
85 Expressions used in constructing lists.
86 --------------------------------------------------------------------- */
88 /* a linked list of expressions */
89 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
91 /* a linked list of instructions.
92 The insns are represented in print by their uids. */
93 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
95 /* SEQUENCE appears in the result of a `gen_...' function
96 for a DEFINE_EXPAND that wants to make several insns.
97 Its elements are the bodies of the insns that should be made.
98 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
99 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
101 /* Refers to the address of its argument. This is only used in alias.c. */
102 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
104 /* ----------------------------------------------------------------------
105 Expression types used for things in the instruction chain.
107 All formats must start with "iuu" to handle the chain.
108 Each insn expression holds an rtl instruction and its semantics
109 during back-end processing.
110 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
112 ---------------------------------------------------------------------- */
114 /* An instruction that cannot jump. */
115 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
117 /* An instruction that can possibly jump.
118 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
119 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
121 /* An instruction that can possibly call a subroutine
122 but which will not change which instruction comes next
123 in the current function.
124 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
125 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
126 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
128 /* A marker that indicates that control will not flow through. */
129 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
131 /* Holds a label that is followed by instructions.
133 4: is used in jump.c for the use-count of the label.
134 5: is used in flow.c to point to the chain of label_ref's to this label.
135 6: is a number that is unique in the entire compilation.
136 7: is the user-given name of the label, if any. */
137 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
139 #ifdef USE_MAPPED_LOCATION
140 /* Say where in the code a source line starts, for symbol table's sake.
142 4: unused if line number > 0, note-specific data otherwise.
143 5: line number if > 0, enum note_insn otherwise.
144 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
146 /* Say where in the code a source line starts, for symbol table's sake.
148 4: filename, if line number > 0, note-specific data otherwise.
149 5: line number if > 0, enum note_insn otherwise.
150 6: unique number if line number == note_insn_deleted_label. */
152 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
154 /* ----------------------------------------------------------------------
155 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
156 ---------------------------------------------------------------------- */
158 /* Conditionally execute code.
159 Operand 0 is the condition that if true, the code is executed.
160 Operand 1 is the code to be executed (typically a SET).
162 Semantics are that there are no side effects if the condition
163 is false. This pattern is created automatically by the if_convert
164 pass run after reload or by target-specific splitters. */
165 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
167 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
168 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
170 /* A string that is passed through to the assembler as input.
171 One can obviously pass comments through by using the
172 assembler comment syntax.
173 These occur in an insn all by themselves as the PATTERN.
174 They also appear inside an ASM_OPERANDS
175 as a convenient way to hold a string. */
176 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
178 #ifdef USE_MAPPED_LOCATION
179 /* An assembler instruction with operands.
180 1st operand is the instruction template.
181 2nd operand is the constraint for the output.
182 3rd operand is the number of the output this expression refers to.
183 When an insn stores more than one value, a separate ASM_OPERANDS
184 is made for each output; this integer distinguishes them.
185 4th is a vector of values of input operands.
186 5th is a vector of modes and constraints for the input operands.
187 Each element is an ASM_INPUT containing a constraint string
188 and whose mode indicates the mode of the input operand.
189 6th is the source line number. */
190 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
192 /* An assembler instruction with operands.
193 1st operand is the instruction template.
194 2nd operand is the constraint for the output.
195 3rd operand is the number of the output this expression refers to.
196 When an insn stores more than one value, a separate ASM_OPERANDS
197 is made for each output; this integer distinguishes them.
198 4th is a vector of values of input operands.
199 5th is a vector of modes and constraints for the input operands.
200 Each element is an ASM_INPUT containing a constraint string
201 and whose mode indicates the mode of the input operand.
202 6th is the name of the containing source file.
203 7th is the source line number. */
204 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
207 /* A machine-specific operation.
208 1st operand is a vector of operands being used by the operation so that
209 any needed reloads can be done.
210 2nd operand is a unique value saying which of a number of machine-specific
211 operations is to be performed.
212 (Note that the vector must be the first operand because of the way that
213 genrecog.c record positions within an insn.)
214 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
215 or inside an expression. */
216 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
218 /* Similar, but a volatile operation and one which may trap. */
219 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
221 /* Vector of addresses, stored as full words. */
222 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
223 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
225 /* Vector of address differences X0 - BASE, X1 - BASE, ...
226 First operand is BASE; the vector contains the X's.
227 The machine mode of this rtx says how much space to leave
228 for each difference and is adjusted by branch shortening if
229 CASE_VECTOR_SHORTEN_MODE is defined.
230 The third and fourth operands store the target labels with the
231 minimum and maximum addresses respectively.
232 The fifth operand stores flags for use by branch shortening.
233 Set at the start of shorten_branches:
234 min_align: the minimum alignment for any of the target labels.
235 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
236 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
237 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
238 min_after_base: true iff minimum address target label is after BASE.
239 max_after_base: true iff maximum address target label is after BASE.
240 Set by the actual branch shortening process:
241 offset_unsigned: true iff offsets have to be treated as unsigned.
242 scale: scaling that is necessary to make offsets fit into the mode.
244 The third, fourth and fifth operands are only valid when
245 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
248 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
250 /* Memory prefetch, with attributes supported on some targets.
251 Operand 1 is the address of the memory to fetch.
252 Operand 2 is 1 for a write access, 0 otherwise.
253 Operand 3 is the level of temporal locality; 0 means there is no
254 temporal locality and 1, 2, and 3 are for increasing levels of temporal
257 The attributes specified by operands 2 and 3 are ignored for targets
258 whose prefetch instructions do not support them. */
259 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
261 /* ----------------------------------------------------------------------
262 At the top level of an instruction (perhaps under PARALLEL).
263 ---------------------------------------------------------------------- */
266 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
267 Operand 2 is the value stored there.
268 ALL assignment must use SET.
269 Instructions that do multiple assignments must use multiple SET,
271 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
273 /* Indicate something is used in a way that we don't want to explain.
274 For example, subroutine calls will use the register
275 in which the static chain is passed. */
276 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
278 /* Indicate something is clobbered in a way that we don't want to explain.
279 For example, subroutine calls will clobber some physical registers
280 (the ones that are by convention not saved). */
281 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
283 /* Call a subroutine.
284 Operand 1 is the address to call.
285 Operand 2 is the number of arguments. */
287 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
289 /* Return from a subroutine. */
291 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
294 Operand 1 is the condition.
295 Operand 2 is the trap code.
296 For an unconditional trap, make the condition (const_int 1). */
297 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
299 /* Placeholder for _Unwind_Resume before we know if a function call
300 or a branch is needed. Operand 1 is the exception region from
301 which control is flowing. */
302 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
304 /* ----------------------------------------------------------------------
305 Primitive values for use in expressions.
306 ---------------------------------------------------------------------- */
308 /* numeric integer constant */
309 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
311 /* numeric floating point constant.
312 Operands hold the value. They are all 'w' and there may be from 2 to 6;
314 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
316 /* Describes a vector constant. */
317 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA)
319 /* String constant. Used for attributes in machine descriptions and
320 for special cases in DWARF2 debug output. NOT used for source-
321 language string constants. */
322 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
324 /* This is used to encapsulate an expression whose value is constant
325 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
326 recognized as a constant operand rather than by arithmetic instructions. */
328 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
330 /* program counter. Ordinary jumps are represented
331 by a SET whose first operand is (PC). */
332 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
334 /* Used in the cselib routines to describe a value. */
335 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
337 /* A register. The "operand" is the register number, accessed with
338 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
339 than a hardware register is being referred to. The second operand
340 holds the original register number - this will be different for a
341 pseudo register that got turned into a hard register.
342 This rtx needs to have as many (or more) fields as a MEM, since we
343 can change REG rtx's into MEMs during reload. */
344 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
346 /* A scratch register. This represents a register used only within a
347 single insn. It will be turned into a REG during register allocation
348 or reload unless the constraint indicates that the register won't be
349 needed, in which case it can remain a SCRATCH. This code is
350 marked as having one operand so it can be turned into a REG. */
351 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
353 /* One word of a multi-word value.
354 The first operand is the complete value; the second says which word.
355 The WORDS_BIG_ENDIAN flag controls whether word number 0
356 (as numbered in a SUBREG) is the most or least significant word.
358 This is also used to refer to a value in a different machine mode.
359 For example, it can be used to refer to a SImode value as if it were
360 Qimode, or vice versa. Then the word number is always 0. */
361 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
363 /* This one-argument rtx is used for move instructions
364 that are guaranteed to alter only the low part of a destination.
365 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
366 has an unspecified effect on the high part of REG,
367 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
368 is guaranteed to alter only the bits of REG that are in HImode.
370 The actual instruction used is probably the same in both cases,
371 but the register constraints may be tighter when STRICT_LOW_PART
374 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
376 /* (CONCAT a b) represents the virtual concatenation of a and b
377 to make a value that has as many bits as a and b put together.
378 This is used for complex values. Normally it appears only
379 in DECL_RTLs and during RTL generation, but not in the insn chain. */
380 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
382 /* A memory location; operand is the address. The second operand is the
383 alias set to which this MEM belongs. We use `0' instead of `w' for this
384 field so that the field need not be specified in machine descriptions. */
385 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
387 /* Reference to an assembler label in the code for this function.
388 The operand is a CODE_LABEL found in the insn chain.
389 The unprinted fields 1 and 2 are used in flow.c for the
390 LABEL_NEXTREF and CONTAINING_INSN. */
391 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", RTX_CONST_OBJ)
393 /* Reference to a named label:
394 Operand 0: label name
395 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
396 Operand 2: tree from which this symbol is derived, or null.
397 This is either a DECL node, or some kind of constant. */
398 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
400 /* The condition code register is represented, in our imagination,
401 as a register holding a value that can be compared to zero.
402 In fact, the machine has already compared them and recorded the
403 results; but instructions that look at the condition code
404 pretend to be looking at the entire value and comparing it. */
405 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
407 /* ----------------------------------------------------------------------
408 Expressions for operators in an rtl pattern
409 ---------------------------------------------------------------------- */
411 /* if_then_else. This is used in representing ordinary
412 conditional jump instructions.
417 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
419 /* Comparison, produces a condition code result. */
420 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
423 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
425 /* Operand 0 minus operand 1. */
426 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
428 /* Minus operand 0. */
429 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
431 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
433 /* Operand 0 divided by operand 1. */
434 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
435 /* Remainder of operand 0 divided by operand 1. */
436 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
438 /* Unsigned divide and remainder. */
439 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
440 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
442 /* Bitwise operations. */
443 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
445 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
447 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
449 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
452 0: value to be shifted.
453 1: number of bits. */
454 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
455 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
456 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
457 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
458 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
460 /* Minimum and maximum values of two operands. We need both signed and
461 unsigned forms. (We cannot use MIN for SMIN because it conflicts
462 with a macro of the same name.) */
464 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
465 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
466 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
467 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
469 /* These unary operations are used to represent incrementation
470 and decrementation as they occur in memory addresses.
471 The amount of increment or decrement are not represented
472 because they can be understood from the machine-mode of the
473 containing MEM. These operations exist in only two cases:
474 1. pushes onto the stack.
475 2. created automatically by the life_analysis pass in flow.c. */
476 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
477 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
478 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
479 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
481 /* These binary operations are used to represent generic address
482 side-effects in memory addresses, except for simple incrementation
483 or decrementation which use the above operations. They are
484 created automatically by the life_analysis pass in flow.c.
485 The first operand is a REG which is used as the address.
486 The second operand is an expression that is assigned to the
487 register, either before (PRE_MODIFY) or after (POST_MODIFY)
488 evaluating the address.
489 Currently, the compiler can only handle second operands of the
490 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
491 the first operand of the PLUS has to be the same register as
492 the first operand of the *_MODIFY. */
493 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
494 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
496 /* Comparison operations. The ordered comparisons exist in two
497 flavors, signed and unsigned. */
498 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
499 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
500 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
501 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
502 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
503 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
504 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
505 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
506 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
507 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
509 /* Additional floating point unordered comparison flavors. */
510 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
511 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
513 /* These are equivalent to unordered or ... */
514 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
515 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
516 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
517 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
518 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
520 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
521 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
523 /* Represents the result of sign-extending the sole operand.
524 The machine modes of the operand and of the SIGN_EXTEND expression
525 determine how much sign-extension is going on. */
526 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
528 /* Similar for zero-extension (such as unsigned short to int). */
529 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
531 /* Similar but here the operand has a wider mode. */
532 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
534 /* Similar for extending floating-point values (such as SFmode to DFmode). */
535 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
536 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
538 /* Conversion of fixed point operand to floating point value. */
539 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
541 /* With fixed-point machine mode:
542 Conversion of floating point operand to fixed point value.
543 Value is defined only when the operand's value is an integer.
544 With floating-point machine mode (and operand with same mode):
545 Operand is rounded toward zero to produce an integer value
546 represented in floating point. */
547 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
549 /* Conversion of unsigned fixed point operand to floating point value. */
550 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
552 /* With fixed-point machine mode:
553 Conversion of floating point operand to *unsigned* fixed point value.
554 Value is defined only when the operand's value is an integer. */
555 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
558 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
561 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
563 /* Find first bit that is set.
564 Value is 1 + number of trailing zeros in the arg.,
566 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
568 /* Count leading zeros. */
569 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
571 /* Count trailing zeros. */
572 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
574 /* Population count (number of 1 bits). */
575 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
577 /* Population parity (number of 1 bits modulo 2). */
578 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
580 /* Reference to a signed bit-field of specified size and position.
581 Operand 0 is the memory unit (usually SImode or QImode) which
582 contains the field's first bit. Operand 1 is the width, in bits.
583 Operand 2 is the number of bits in the memory unit before the
584 first bit of this field.
585 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
586 operand 2 counts from the msb of the memory unit.
587 Otherwise, the first bit is the lsb and operand 2 counts from
588 the lsb of the memory unit. */
589 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
591 /* Similar for unsigned bit-field. */
592 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
594 /* For RISC machines. These save memory when splitting insns. */
596 /* HIGH are the high-order bits of a constant expression. */
597 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
599 /* LO_SUM is the sum of a register and the low-order bits
600 of a constant expression. */
601 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
603 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
604 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
605 the registers that can be substituted within this range. Operand 3 is the
606 number of calls in the range. Operand 4 is the number of insns in the
607 range. Operand 5 is the unique range number for this range. Operand 6 is
608 the basic block # of the start of the live range. Operand 7 is the basic
609 block # of the end of the live range. Operand 8 is the loop depth. Operand
610 9 is a bitmap of the registers live at the start of the range. Operand 10
611 is a bitmap of the registers live at the end of the range. Operand 11 is
612 marker number for the start of the range. Operand 12 is the marker number
613 for the end of the range. */
614 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", RTX_EXTRA)
616 /* Registers that can be substituted within the range. Operand 0 is the
617 original pseudo register number. Operand 1 will be filled in with the
618 pseudo register the value is copied for the duration of the range. Operand
619 2 is the number of references within the range to the register. Operand 3
620 is the number of sets or clobbers of the register in the range. Operand 4
621 is the number of deaths the register has. Operand 5 is the copy flags that
622 give the status of whether a copy is needed from the original register to
623 the new register at the beginning of the range, or whether a copy from the
624 new register back to the original at the end of the range. Operand 6 is the
625 live length. Operand 7 is the number of calls that this register is live
626 across. Operand 8 is the symbol node of the variable if the register is a
627 user variable. Operand 9 is the block node that the variable is declared
628 in if the register is a user variable. */
629 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", RTX_EXTRA)
631 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
632 the different ranges a variable is in where it is copied to a different
633 pseudo register. Operand 1 is the block that the variable is declared in.
634 Operand 2 is the number of distinct ranges. */
635 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", RTX_EXTRA)
637 /* Information about the registers that are live at the current point. Operand
638 0 is the live bitmap. Operand 1 is the original block number. */
639 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", RTX_EXTRA)
641 /* Describes a merge operation between two vector values.
642 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
643 that specifies where the parts of the result are taken from. Set bits
644 indicate operand 0, clear bits indicate operand 1. The parts are defined
645 by the mode of the vectors. */
646 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
648 /* Describes an operation that selects parts of a vector.
649 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
650 a CONST_INT for each of the subparts of the result vector, giving the
651 number of the source subpart that should be stored into it. */
652 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
654 /* Describes a vector concat operation. Operands 0 and 1 are the source
655 vectors, the result is a vector that is as long as operands 0 and 1
656 combined and is the concatenation of the two source vectors. */
657 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
659 /* Describes an operation that converts a small vector into a larger one by
660 duplicating the input values. The output vector mode must have the same
661 submodes as the input vector mode, and the number of output parts must be
662 an integer multiple of the number of input parts. */
663 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
665 /* Addition with signed saturation */
666 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
668 /* Addition with unsigned saturation */
669 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
671 /* Operand 0 minus operand 1, with signed saturation. */
672 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
674 /* Operand 0 minus operand 1, with unsigned saturation. */
675 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
677 /* Signed saturating truncate. */
678 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
680 /* Unsigned saturating truncate. */
681 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
683 /* Information about the variable and its location. */
684 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
686 /* All expressions from this point forward appear only in machine
688 #ifdef GENERATOR_FILE
690 /* Include a secondary machine-description file at this point. */
691 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
693 /* Pattern-matching operators: */
695 /* Use the function named by the second arg (the string)
696 as a predicate; if matched, store the structure that was matched
697 in the operand table at index specified by the first arg (the integer).
698 If the second arg is the null string, the structure is just stored.
700 A third string argument indicates to the register allocator restrictions
701 on where the operand can be allocated.
703 If the target needs no restriction on any instruction this field should
706 The string is prepended by:
707 '=' to indicate the operand is only written to.
708 '+' to indicate the operand is both read and written to.
710 Each character in the string represents an allocable class for an operand.
711 'g' indicates the operand can be any valid class.
712 'i' indicates the operand can be immediate (in the instruction) data.
713 'r' indicates the operand can be in a register.
714 'm' indicates the operand can be in memory.
715 'o' a subset of the 'm' class. Those memory addressing modes that
716 can be offset at compile time (have a constant added to them).
718 Other characters indicate target dependent operand classes and
719 are described in each target's machine description.
721 For instructions with more than one operand, sets of classes can be
722 separated by a comma to indicate the appropriate multi-operand constraints.
723 There must be a 1 to 1 correspondence between these sets of classes in
724 all operands for an instruction.
726 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
728 /* Match a SCRATCH or a register. When used to generate rtl, a
729 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
730 the desired mode and the first argument is the operand number.
731 The second argument is the constraint. */
732 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
734 /* Apply a predicate, AND match recursively the operands of the rtx.
735 Operand 0 is the operand-number, as in match_operand.
736 Operand 1 is a predicate to apply (as a string, a function name).
737 Operand 2 is a vector of expressions, each of which must match
738 one subexpression of the rtx this construct is matching. */
739 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
741 /* Match a PARALLEL of arbitrary length. The predicate is applied
742 to the PARALLEL and the initial expressions in the PARALLEL are matched.
743 Operand 0 is the operand-number, as in match_operand.
744 Operand 1 is a predicate to apply to the PARALLEL.
745 Operand 2 is a vector of expressions, each of which must match the
746 corresponding element in the PARALLEL. */
747 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
749 /* Match only something equal to what is stored in the operand table
750 at the index specified by the argument. Use with MATCH_OPERAND. */
751 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
753 /* Match only something equal to what is stored in the operand table
754 at the index specified by the argument. Use with MATCH_OPERATOR. */
755 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
757 /* Match only something equal to what is stored in the operand table
758 at the index specified by the argument. Use with MATCH_PARALLEL. */
759 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
761 /* Appears only in define_predicate/define_special_predicate
762 expressions. Evaluates true only if the operand has an RTX code
763 from the set given by the argument (a comma-separated list). */
764 DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH)
766 /* Appears only in define_predicate/define_special_predicate
767 expressions. The argument is a C expression to be injected at this
768 point in the predicate formula. */
769 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
771 /* Insn (and related) definitions. */
773 /* Definition of the pattern for one kind of instruction.
775 0: names this instruction.
776 If the name is the null string, the instruction is in the
777 machine description just to be recognized, and will never be emitted by
778 the tree to rtl expander.
780 2: is a string which is a C expression
781 giving an additional condition for recognizing this pattern.
782 A null string means no extra condition.
783 3: is the action to execute if this pattern is matched.
784 If this assembler code template starts with a * then it is a fragment of
785 C code to run to decide on a template to use. Otherwise, it is the
787 4: optionally, a vector of attributes for this insn.
789 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
791 /* Definition of a peephole optimization.
792 1st operand: vector of insn patterns to match
793 2nd operand: C expression that must be true
794 3rd operand: template or C code to produce assembler output.
795 4: optionally, a vector of attributes for this insn.
797 This form is deprecated; use define_peephole2 instead. */
798 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
800 /* Definition of a split operation.
801 1st operand: insn pattern to match
802 2nd operand: C expression that must be true
803 3rd operand: vector of insn patterns to place into a SEQUENCE
804 4th operand: optionally, some C code to execute before generating the
805 insns. This might, for example, create some RTX's and store them in
806 elements of `recog_data.operand' for use by the vector of
808 (`operands' is an alias here for `recog_data.operand'). */
809 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
811 /* Definition of an insn and associated split.
812 This is the concatenation, with a few modifications, of a define_insn
813 and a define_split which share the same pattern.
815 0: names this instruction.
816 If the name is the null string, the instruction is in the
817 machine description just to be recognized, and will never be emitted by
818 the tree to rtl expander.
820 2: is a string which is a C expression
821 giving an additional condition for recognizing this pattern.
822 A null string means no extra condition.
823 3: is the action to execute if this pattern is matched.
824 If this assembler code template starts with a * then it is a fragment of
825 C code to run to decide on a template to use. Otherwise, it is the
827 4: C expression that must be true for split. This may start with "&&"
828 in which case the split condition is the logical and of the insn
829 condition and what follows the "&&" of this operand.
830 5: vector of insn patterns to place into a SEQUENCE
831 6: optionally, some C code to execute before generating the
832 insns. This might, for example, create some RTX's and store them in
833 elements of `recog_data.operand' for use by the vector of
835 (`operands' is an alias here for `recog_data.operand').
836 7: optionally, a vector of attributes for this insn. */
837 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
839 /* Definition of an RTL peephole operation.
840 Follows the same arguments as define_split. */
841 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
843 /* Define how to generate multiple insns for a standard insn name.
844 1st operand: the insn name.
845 2nd operand: vector of insn-patterns.
846 Use match_operand to substitute an element of `recog_data.operand'.
847 3rd operand: C expression that must be true for this to be available.
848 This may not test any operands.
849 4th operand: Extra C code to execute before generating the insns.
850 This might, for example, create some RTX's and store them in
851 elements of `recog_data.operand' for use by the vector of
853 (`operands' is an alias here for `recog_data.operand'). */
854 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
856 /* Define a requirement for delay slots.
857 1st operand: Condition involving insn attributes that, if true,
858 indicates that the insn requires the number of delay slots
860 2nd operand: Vector whose length is the three times the number of delay
862 Each entry gives three conditions, each involving attributes.
863 The first must be true for an insn to occupy that delay slot
864 location. The second is true for all insns that can be
865 annulled if the branch is true and the third is true for all
866 insns that can be annulled if the branch is false.
868 Multiple DEFINE_DELAYs may be present. They indicate differing
869 requirements for delay slots. */
870 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
872 /* Define attribute computation for `asm' instructions. */
873 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
875 /* Definition of a conditional execution meta operation. Automatically
876 generates new instances of DEFINE_INSN, selected by having attribute
877 "predicable" true. The new pattern will contain a COND_EXEC and the
878 predicate at top-level.
881 0: The predicate pattern. The top-level form should match a
882 relational operator. Operands should have only one alternative.
883 1: A C expression giving an additional condition for recognizing
884 the generated pattern.
885 2: A template or C code to produce assembler output. */
886 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
888 /* Definition of an operand predicate. The difference between
889 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
890 not warn about a match_operand with no mode if it has a predicate
891 defined with DEFINE_SPECIAL_PREDICATE.
894 0: The name of the predicate.
895 1: A boolean expression which computes whether or not the predicate
896 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
897 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
898 can calculate the set of RTX codes that can possibly match.
899 2: A C function body which must return true for the predicate to match.
900 Optional. Use this when the test is too complicated to fit into a
901 match_test expression. */
902 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
903 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
905 /* Constructions for CPU pipeline description described by NDFAs. */
907 /* (define_cpu_unit string [string]) describes cpu functional
908 units (separated by comma).
910 1st operand: Names of cpu functional units.
911 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
913 All define_reservations, define_cpu_units, and
914 define_query_cpu_units should have unique names which may not be
916 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
918 /* (define_query_cpu_unit string [string]) describes cpu functional
919 units analogously to define_cpu_unit. The reservation of such
920 units can be queried for automaton state. */
921 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
923 /* (exclusion_set string string) means that each CPU functional unit
924 in the first string can not be reserved simultaneously with any
925 unit whose name is in the second string and vise versa. CPU units
926 in the string are separated by commas. For example, it is useful
927 for description CPU with fully pipelined floating point functional
928 unit which can execute simultaneously only single floating point
929 insns or only double floating point insns. All CPU functional
930 units in a set should belong to the same automaton. */
931 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
933 /* (presence_set string string) means that each CPU functional unit in
934 the first string can not be reserved unless at least one of pattern
935 of units whose names are in the second string is reserved. This is
936 an asymmetric relation. CPU units or unit patterns in the strings
937 are separated by commas. Pattern is one unit name or unit names
938 separated by white-spaces.
940 For example, it is useful for description that slot1 is reserved
941 after slot0 reservation for a VLIW processor. We could describe it
942 by the following construction
944 (presence_set "slot1" "slot0")
946 Or slot1 is reserved only after slot0 and unit b0 reservation. In
947 this case we could write
949 (presence_set "slot1" "slot0 b0")
951 All CPU functional units in a set should belong to the same
953 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
955 /* (final_presence_set string string) is analogous to `presence_set'.
956 The difference between them is when checking is done. When an
957 instruction is issued in given automaton state reflecting all
958 current and planned unit reservations, the automaton state is
959 changed. The first state is a source state, the second one is a
960 result state. Checking for `presence_set' is done on the source
961 state reservation, checking for `final_presence_set' is done on the
962 result reservation. This construction is useful to describe a
963 reservation which is actually two subsequent reservations. For
966 (presence_set "slot1" "slot0")
968 the following insn will be never issued (because slot1 requires
969 slot0 which is absent in the source state).
971 (define_reservation "insn_and_nop" "slot0 + slot1")
973 but it can be issued if we use analogous `final_presence_set'. */
974 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
976 /* (absence_set string string) means that each CPU functional unit in
977 the first string can be reserved only if each pattern of units
978 whose names are in the second string is not reserved. This is an
979 asymmetric relation (actually exclusion set is analogous to this
980 one but it is symmetric). CPU units or unit patterns in the string
981 are separated by commas. Pattern is one unit name or unit names
982 separated by white-spaces.
984 For example, it is useful for description that slot0 can not be
985 reserved after slot1 or slot2 reservation for a VLIW processor. We
986 could describe it by the following construction
988 (absence_set "slot2" "slot0, slot1")
990 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
991 slot1 and unit b1 are reserved . In this case we could write
993 (absence_set "slot2" "slot0 b0, slot1 b1")
995 All CPU functional units in a set should to belong the same
997 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
999 /* (final_absence_set string string) is analogous to `absence_set' but
1000 checking is done on the result (state) reservation. See comments
1001 for `final_presence_set'. */
1002 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1004 /* (define_bypass number out_insn_names in_insn_names) names bypass
1005 with given latency (the first number) from insns given by the first
1006 string (see define_insn_reservation) into insns given by the second
1007 string. Insn names in the strings are separated by commas. The
1008 third operand is optional name of function which is additional
1009 guard for the bypass. The function will get the two insns as
1010 parameters. If the function returns zero the bypass will be
1011 ignored for this case. Additional guard is necessary to recognize
1012 complicated bypasses, e.g. when consumer is load address. */
1013 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1015 /* (define_automaton string) describes names of automata generated and
1016 used for pipeline hazards recognition. The names are separated by
1017 comma. Actually it is possibly to generate the single automaton
1018 but unfortunately it can be very large. If we use more one
1019 automata, the summary size of the automata usually is less than the
1020 single one. The automaton name is used in define_cpu_unit and
1021 define_query_cpu_unit. All automata should have unique names. */
1022 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1024 /* (automata_option string) describes option for generation of
1025 automata. Currently there are the following options:
1027 o "no-minimization" which makes no minimization of automata. This
1028 is only worth to do when we are debugging the description and
1029 need to look more accurately at reservations of states.
1031 o "time" which means printing additional time statistics about
1032 generation of automata.
1034 o "v" which means generation of file describing the result
1035 automata. The file has suffix `.dfa' and can be used for the
1036 description verification and debugging.
1038 o "w" which means generation of warning instead of error for
1039 non-critical errors.
1041 o "ndfa" which makes nondeterministic finite state automata.
1043 o "progress" which means output of a progress bar showing how many
1044 states were generated so far for automaton being processed. */
1045 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1047 /* (define_reservation string string) names reservation (the first
1048 string) of cpu functional units (the 2nd string). Sometimes unit
1049 reservations for different insns contain common parts. In such
1050 case, you can describe common part and use its name (the 1st
1051 parameter) in regular expression in define_insn_reservation. All
1052 define_reservations, define_cpu_units, and define_query_cpu_units
1053 should have unique names which may not be "nothing". */
1054 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1056 /* (define_insn_reservation name default_latency condition regexpr)
1057 describes reservation of cpu functional units (the 3nd operand) for
1058 instruction which is selected by the condition (the 2nd parameter).
1059 The first parameter is used for output of debugging information.
1060 The reservations are described by a regular expression according
1061 the following syntax:
1063 regexp = regexp "," oneof
1066 oneof = oneof "|" allof
1069 allof = allof "+" repeat
1072 repeat = element "*" number
1075 element = cpu_function_unit_name
1081 1. "," is used for describing start of the next cycle in
1084 2. "|" is used for describing the reservation described by the
1085 first regular expression *or* the reservation described by the
1086 second regular expression *or* etc.
1088 3. "+" is used for describing the reservation described by the
1089 first regular expression *and* the reservation described by the
1090 second regular expression *and* etc.
1092 4. "*" is used for convenience and simply means sequence in
1093 which the regular expression are repeated NUMBER times with
1094 cycle advancing (see ",").
1096 5. cpu functional unit name which means its reservation.
1098 6. reservation name -- see define_reservation.
1100 7. string "nothing" means no units reservation. */
1102 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1104 /* Expressions used for insn attributes. */
1106 /* Definition of an insn attribute.
1107 1st operand: name of the attribute
1108 2nd operand: comma-separated list of possible attribute values
1109 3rd operand: expression for the default value of the attribute. */
1110 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1112 /* Marker for the name of an attribute. */
1113 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1115 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1116 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1119 (set_attr "name" "value") is equivalent to
1120 (set (attr "name") (const_string "value")) */
1121 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1123 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1124 specify that attribute values are to be assigned according to the
1125 alternative matched.
1127 The following three expressions are equivalent:
1129 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1130 (eq_attrq "alternative" "2") (const_string "a2")]
1131 (const_string "a3")))
1132 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1133 (const_string "a3")])
1134 (set_attr "att" "a1,a2,a3")
1136 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1138 /* A conditional expression true if the value of the specified attribute of
1139 the current insn equals the specified value. The first operand is the
1140 attribute name and the second is the comparison value. */
1141 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1143 /* A special case of the above representing a set of alternatives. The first
1144 operand is bitmap of the set, the second one is the default value. */
1145 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1147 /* A conditional expression which is true if the specified flag is
1148 true for the insn being scheduled in reorg.
1150 genattr.c defines the following flags which can be tested by
1151 (attr_flag "foo") expressions in eligible_for_delay.
1153 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1155 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1157 /* General conditional. The first operand is a vector composed of pairs of
1158 expressions. The first element of each pair is evaluated, in turn.
1159 The value of the conditional is the second expression of the first pair
1160 whose first expression evaluates nonzero. If none of the expressions is
1161 true, the second operand will be used as the value of the conditional. */
1162 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1164 #endif /* GENERATOR_FILE */
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