1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
5 Free Software Foundation, Inc.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
50 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
63 /* ---------------------------------------------------------------------
64 Expressions (and "meta" expressions) used for structuring the
65 rtl representation of a program.
66 --------------------------------------------------------------------- */
68 /* an expression code name unknown to the reader */
69 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
71 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
73 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
75 /* ---------------------------------------------------------------------
76 Expressions used in constructing lists.
77 --------------------------------------------------------------------- */
79 /* a linked list of expressions */
80 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
82 /* a linked list of instructions.
83 The insns are represented in print by their uids. */
84 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
86 /* ----------------------------------------------------------------------
87 Expression types for machine descriptions.
88 These do not appear in actual rtl code in the compiler.
89 ---------------------------------------------------------------------- */
91 /* Appears only in machine descriptions.
92 Means use the function named by the second arg (the string)
93 as a predicate; if matched, store the structure that was matched
94 in the operand table at index specified by the first arg (the integer).
95 If the second arg is the null string, the structure is just stored.
97 A third string argument indicates to the register allocator restrictions
98 on where the operand can be allocated.
100 If the target needs no restriction on any instruction this field should
103 The string is prepended by:
104 '=' to indicate the operand is only written to.
105 '+' to indicate the operand is both read and written to.
107 Each character in the string represents an allocable class for an operand.
108 'g' indicates the operand can be any valid class.
109 'i' indicates the operand can be immediate (in the instruction) data.
110 'r' indicates the operand can be in a register.
111 'm' indicates the operand can be in memory.
112 'o' a subset of the 'm' class. Those memory addressing modes that
113 can be offset at compile time (have a constant added to them).
115 Other characters indicate target dependent operand classes and
116 are described in each target's machine description.
118 For instructions with more than one operand, sets of classes can be
119 separated by a comma to indicate the appropriate multi-operand constraints.
120 There must be a 1 to 1 correspondence between these sets of classes in
121 all operands for an instruction.
123 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
125 /* Appears only in machine descriptions.
126 Means match a SCRATCH or a register. When used to generate rtl, a
127 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
128 the desired mode and the first argument is the operand number.
129 The second argument is the constraint. */
130 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
132 /* Appears only in machine descriptions.
133 Means match only something equal to what is stored in the operand table
134 at the index specified by the argument. */
135 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
137 /* Appears only in machine descriptions.
138 Means apply a predicate, AND match recursively the operands of the rtx.
139 Operand 0 is the operand-number, as in match_operand.
140 Operand 1 is a predicate to apply (as a string, a function name).
141 Operand 2 is a vector of expressions, each of which must match
142 one subexpression of the rtx this construct is matching. */
143 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
145 /* Appears only in machine descriptions.
146 Means to match a PARALLEL of arbitrary length. The predicate is applied
147 to the PARALLEL and the initial expressions in the PARALLEL are matched.
148 Operand 0 is the operand-number, as in match_operand.
149 Operand 1 is a predicate to apply to the PARALLEL.
150 Operand 2 is a vector of expressions, each of which must match the
151 corresponding element in the PARALLEL. */
152 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
154 /* Appears only in machine descriptions.
155 Means match only something equal to what is stored in the operand table
156 at the index specified by the argument. For MATCH_OPERATOR. */
157 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
159 /* Appears only in machine descriptions.
160 Means match only something equal to what is stored in the operand table
161 at the index specified by the argument. For MATCH_PARALLEL. */
162 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
164 /* Appears only in machine descriptions.
165 Operand 0 is the operand number, as in match_operand.
166 Operand 1 is the predicate to apply to the insn. */
167 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
169 /* Appears only in machine descriptions.
170 Defines the pattern for one kind of instruction.
172 0: names this instruction.
173 If the name is the null string, the instruction is in the
174 machine description just to be recognized, and will never be emitted by
175 the tree to rtl expander.
177 2: is a string which is a C expression
178 giving an additional condition for recognizing this pattern.
179 A null string means no extra condition.
180 3: is the action to execute if this pattern is matched.
181 If this assembler code template starts with a * then it is a fragment of
182 C code to run to decide on a template to use. Otherwise, it is the
184 4: optionally, a vector of attributes for this insn.
186 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
188 /* Definition of a peephole optimization.
189 1st operand: vector of insn patterns to match
190 2nd operand: C expression that must be true
191 3rd operand: template or C code to produce assembler output.
192 4: optionally, a vector of attributes for this insn.
194 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
196 /* Definition of a split operation.
197 1st operand: insn pattern to match
198 2nd operand: C expression that must be true
199 3rd operand: vector of insn patterns to place into a SEQUENCE
200 4th operand: optionally, some C code to execute before generating the
201 insns. This might, for example, create some RTX's and store them in
202 elements of `recog_operand' for use by the vector of insn-patterns.
203 (`operands' is an alias here for `recog_operand'). */
204 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
206 /* Definition of an insn and associated split.
207 This is the concatenation, with a few modifications, of a define_insn
208 and a define_split which share the same pattern.
210 0: names this instruction.
211 If the name is the null string, the instruction is in the
212 machine description just to be recognized, and will never be emitted by
213 the tree to rtl expander.
215 2: is a string which is a C expression
216 giving an additional condition for recognizing this pattern.
217 A null string means no extra condition.
218 3: is the action to execute if this pattern is matched.
219 If this assembler code template starts with a * then it is a fragment of
220 C code to run to decide on a template to use. Otherwise, it is the
222 4: C expression that must be true for split. This may start with "&&"
223 in which case the split condition is the logical and of the insn
224 condition and what follows the "&&" of this operand.
225 5: vector of insn patterns to place into a SEQUENCE
226 6: optionally, some C code to execute before generating the
227 insns. This might, for example, create some RTX's and store them in
228 elements of `recog_operand' for use by the vector of insn-patterns.
229 (`operands' is an alias here for `recog_operand').
230 7: optionally, a vector of attributes for this insn. */
231 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsssESV", 'x')
233 /* Definition of an RTL peephole operation.
234 Follows the same arguments as define_split. */
235 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
237 /* Definition of a combiner pattern.
238 Operands not defined yet. */
239 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
241 /* Define how to generate multiple insns for a standard insn name.
242 1st operand: the insn name.
243 2nd operand: vector of insn-patterns.
244 Use match_operand to substitute an element of `recog_operand'.
245 3rd operand: C expression that must be true for this to be available.
246 This may not test any operands.
247 4th operand: Extra C code to execute before generating the insns.
248 This might, for example, create some RTX's and store them in
249 elements of `recog_operand' for use by the vector of insn-patterns.
250 (`operands' is an alias here for `recog_operand'). */
251 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
253 /* Define a requirement for delay slots.
254 1st operand: Condition involving insn attributes that, if true,
255 indicates that the insn requires the number of delay slots
257 2nd operand: Vector whose length is the three times the number of delay
259 Each entry gives three conditions, each involving attributes.
260 The first must be true for an insn to occupy that delay slot
261 location. The second is true for all insns that can be
262 annulled if the branch is true and the third is true for all
263 insns that can be annulled if the branch is false.
265 Multiple DEFINE_DELAYs may be present. They indicate differing
266 requirements for delay slots. */
267 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
269 /* Define a set of insns that requires a function unit. This means that
270 these insns produce their result after a delay and that there may be
271 restrictions on the number of insns of this type that can be scheduled
274 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
275 Each gives a set of operations and associated delays. The first three
276 operands must be the same for each operation for the same function unit.
278 All delays are specified in cycles.
280 1st operand: Name of function unit (mostly for documentation)
281 2nd operand: Number of identical function units in CPU
282 3rd operand: Total number of simultaneous insns that can execute on this
283 function unit; 0 if unlimited.
284 4th operand: Condition involving insn attribute, that, if true, specifies
285 those insns that this expression applies to.
286 5th operand: Constant delay after which insn result will be
288 6th operand: Delay until next insn can be scheduled on the function unit
289 executing this operation. The meaning depends on whether or
290 not the next operand is supplied.
291 7th operand: If this operand is not specified, the 6th operand gives the
292 number of cycles after the instruction matching the 4th
293 operand begins using the function unit until a subsequent
294 insn can begin. A value of zero should be used for a
295 unit with no issue constraints. If only one operation can
296 be executed a time and the unit is busy for the entire time,
297 the 3rd operand should be specified as 1, the 6th operand
298 should be specified as 0, and the 7th operand should not
301 If this operand is specified, it is a list of attribute
302 expressions. If an insn for which any of these expressions
303 is true is currently executing on the function unit, the
304 issue delay will be given by the 6th operand. Otherwise,
305 the insn can be immediately scheduled (subject to the limit
306 on the number of simultaneous operations executing on the
308 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
310 /* Define attribute computation for `asm' instructions. */
311 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
313 /* Definition of a conditional execution meta operation. Automatically
314 generates new instances of DEFINE_INSN, selected by having attribute
315 "predicable" true. The new pattern will contain a COND_EXEC and the
316 predicate at top-level.
319 0: The predicate pattern. The top-level form should match a
320 relational operator. Operands should have only one alternative.
321 1: A C expression giving an additional condition for recognizing
322 the generated pattern.
323 2: A template or C code to produce assembler output. */
324 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
326 /* SEQUENCE appears in the result of a `gen_...' function
327 for a DEFINE_EXPAND that wants to make several insns.
328 Its elements are the bodies of the insns that should be made.
329 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
330 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
332 /* Refers to the address of its argument. This is only used in alias.c. */
333 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
335 /* ----------------------------------------------------------------------
336 Expressions used for insn attributes. These also do not appear in
337 actual rtl code in the compiler.
338 ---------------------------------------------------------------------- */
340 /* Definition of an insn attribute.
341 1st operand: name of the attribute
342 2nd operand: comma-separated list of possible attribute values
343 3rd operand: expression for the default value of the attribute. */
344 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
346 /* Marker for the name of an attribute. */
347 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
349 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
350 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
353 (set_attr "name" "value") is equivalent to
354 (set (attr "name") (const_string "value")) */
355 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
357 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
358 specify that attribute values are to be assigned according to the
361 The following three expressions are equivalent:
363 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
364 (eq_attrq "alternative" "2") (const_string "a2")]
365 (const_string "a3")))
366 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
367 (const_string "a3")])
368 (set_attr "att" "a1,a2,a3")
370 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
372 /* A conditional expression true if the value of the specified attribute of
373 the current insn equals the specified value. The first operand is the
374 attribute name and the second is the comparison value. */
375 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
377 /* A conditional expression which is true if the specified flag is
378 true for the insn being scheduled in reorg.
380 genattr.c defines the following flags which can be tested by
381 (attr_flag "foo") expressions in eligible_for_delay.
383 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
385 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
387 /* ----------------------------------------------------------------------
388 Expression types used for things in the instruction chain.
390 All formats must start with "iuu" to handle the chain.
391 Each insn expression holds an rtl instruction and its semantics
392 during back-end processing.
393 See macros's in "rtl.h" for the meaning of each rtx->fld[].
395 ---------------------------------------------------------------------- */
397 /* An instruction that cannot jump. */
398 DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
400 /* An instruction that can possibly jump.
401 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
402 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
404 /* An instruction that can possibly call a subroutine
405 but which will not change which instruction comes next
406 in the current function.
407 Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
408 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
409 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
411 /* A marker that indicates that control will not flow through. */
412 DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
414 /* Holds a label that is followed by instructions.
416 3: is a number that is unique in the entire compilation.
417 4: is the user-given name of the label, if any.
418 5: is used in jump.c for the use-count of the label.
419 6: is used in flow.c to point to the chain of label_ref's to this label.
420 7: is the alternate label name. */
421 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis00s", 'x')
423 /* Say where in the code a source line starts, for symbol table's sake.
424 Contains a filename and a line number. Line numbers <= 0 are special:
425 0 is used in a dummy placed at the front of every function
426 just so there will never be a need to delete the first insn;
427 -1 indicates a dummy; insns to be deleted by flow analysis and combining
428 are really changed to NOTEs with a number of -1.
429 -2 means beginning of a name binding contour; output N_LBRAC.
430 -3 means end of a contour; output N_RBRAC. */
431 DEF_RTL_EXPR(NOTE, "note", "iuu0n", 'x')
433 /* ----------------------------------------------------------------------
434 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
435 ---------------------------------------------------------------------- */
437 /* Conditionally execute code.
438 Operand 0 is the condition that if true, the code is executed.
439 Operand 1 is the code to be executed (typically a SET).
441 Semantics are that there are no side effects if the condition
442 is false. This pattern is created automatically by the if_convert
443 pass run after reload or by target-specific splitters. */
444 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
446 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
447 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
449 /* A string that is passed through to the assembler as input.
450 One can obviously pass comments through by using the
451 assembler comment syntax.
452 These occur in an insn all by themselves as the PATTERN.
453 They also appear inside an ASM_OPERANDS
454 as a convenient way to hold a string. */
455 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
457 /* An assembler instruction with operands.
458 1st operand is the instruction template.
459 2nd operand is the constraint for the output.
460 3rd operand is the number of the output this expression refers to.
461 When an insn stores more than one value, a separate ASM_OPERANDS
462 is made for each output; this integer distinguishes them.
463 4th is a vector of values of input operands.
464 5th is a vector of modes and constraints for the input operands.
465 Each element is an ASM_INPUT containing a constraint string
466 and whose mode indicates the mode of the input operand.
467 6th is the name of the containing source file.
468 7th is the source line number. */
469 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
471 /* A machine-specific operation.
472 1st operand is a vector of operands being used by the operation so that
473 any needed reloads can be done.
474 2nd operand is a unique value saying which of a number of machine-specific
475 operations is to be performed.
476 (Note that the vector must be the first operand because of the way that
477 genrecog.c record positions within an insn.)
478 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
479 or inside an expression. */
480 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
482 /* Similar, but a volatile operation and one which may trap. */
483 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
485 /* Vector of addresses, stored as full words. */
486 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
487 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
489 /* Vector of address differences X0 - BASE, X1 - BASE, ...
490 First operand is BASE; the vector contains the X's.
491 The machine mode of this rtx says how much space to leave
492 for each difference and is adjusted by branch shortening if
493 CASE_VECTOR_SHORTEN_MODE is defined.
494 The third and fourth operands store the target labels with the
495 minimum and maximum addresses respectively.
496 The fifth operand stores flags for use by branch shortening.
497 Set at the start of shorten_branches:
498 min_align: the minimum alignment for any of the target labels.
499 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
500 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
501 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
502 min_after_base: true iff minimum address target label is after BASE.
503 max_after_base: true iff maximum address target label is after BASE.
504 Set by the actual branch shortening process:
505 offset_unsigned: true iff offsets have to be treated as unsigned.
506 scale: scaling that is necessary to make offsets fit into the mode.
508 The third, fourth and fifth operands are only valid when
509 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
512 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
514 /* ----------------------------------------------------------------------
515 At the top level of an instruction (perhaps under PARALLEL).
516 ---------------------------------------------------------------------- */
519 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
520 Operand 2 is the value stored there.
521 ALL assignment must use SET.
522 Instructions that do multiple assignments must use multiple SET,
524 DEF_RTL_EXPR(SET, "set", "ee", 'x')
526 /* Indicate something is used in a way that we don't want to explain.
527 For example, subroutine calls will use the register
528 in which the static chain is passed. */
529 DEF_RTL_EXPR(USE, "use", "e", 'x')
531 /* Indicate something is clobbered in a way that we don't want to explain.
532 For example, subroutine calls will clobber some physical registers
533 (the ones that are by convention not saved). */
534 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
536 /* Call a subroutine.
537 Operand 1 is the address to call.
538 Operand 2 is the number of arguments. */
540 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
542 /* Return from a subroutine. */
544 DEF_RTL_EXPR(RETURN, "return", "", 'x')
547 Operand 1 is the condition.
548 Operand 2 is the trap code.
549 For an unconditional trap, make the condition (const_int 1). */
550 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
552 /* ----------------------------------------------------------------------
553 Primitive values for use in expressions.
554 ---------------------------------------------------------------------- */
556 /* numeric integer constant */
557 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
559 /* numeric floating point constant.
560 Operand 0 ('e') is the MEM that stores this constant in memory, or
561 various other things (see comments at immed_double_const in
563 Operand 1 ('0') is a chain of all CONST_DOUBLEs in use in the
565 Remaining operands hold the actual value. They are all 'w' and
566 there may be from 1 to 4; see rtl.c. */
567 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
569 /* String constant. Used only for attributes right now. */
570 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
572 /* This is used to encapsulate an expression whose value is constant
573 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
574 recognized as a constant operand rather than by arithmetic instructions. */
576 DEF_RTL_EXPR(CONST, "const", "e", 'o')
578 /* program counter. Ordinary jumps are represented
579 by a SET whose first operand is (PC). */
580 DEF_RTL_EXPR(PC, "pc", "", 'o')
582 /* Used in the cselib routines to describe a value. */
583 DEF_RTL_EXPR(VALUE, "value", "0", 'o')
585 /* A register. The "operand" is the register number, accessed with
586 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
587 than a hardware register is being referred to. The second operand
588 doesn't really exist. Unfortunately, however, the compiler
589 implicitly assumes that a REG can be transformed in place into a
590 MEM, and therefore that a REG is at least as big as a MEM. To
591 avoid this memory overhead, which is likely to be substantial,
592 search for uses of PUT_CODE that turn REGs into MEMs, and fix them
593 somehow. Then, the trailing `0' can be removed here. */
594 DEF_RTL_EXPR(REG, "reg", "i0", 'o')
596 /* A scratch register. This represents a register used only within a
597 single insn. It will be turned into a REG during register allocation
598 or reload unless the constraint indicates that the register won't be
599 needed, in which case it can remain a SCRATCH. This code is
600 marked as having one operand so it can be turned into a REG. */
601 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
603 /* One word of a multi-word value.
604 The first operand is the complete value; the second says which word.
605 The WORDS_BIG_ENDIAN flag controls whether word number 0
606 (as numbered in a SUBREG) is the most or least significant word.
608 This is also used to refer to a value in a different machine mode.
609 For example, it can be used to refer to a SImode value as if it were
610 Qimode, or vice versa. Then the word number is always 0. */
611 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
613 /* This one-argument rtx is used for move instructions
614 that are guaranteed to alter only the low part of a destination.
615 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
616 has an unspecified effect on the high part of REG,
617 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
618 is guaranteed to alter only the bits of REG that are in HImode.
620 The actual instruction used is probably the same in both cases,
621 but the register constraints may be tighter when STRICT_LOW_PART
624 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
626 /* (CONCAT a b) represents the virtual concatenation of a and b
627 to make a value that has as many bits as a and b put together.
628 This is used for complex values. Normally it appears only
629 in DECL_RTLs and during RTL generation, but not in the insn chain. */
630 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
632 /* A memory location; operand is the address. Can be nested inside a
633 VOLATILE. The second operand is the alias set to which this MEM
634 belongs. We use `0' instead of `i' for this field so that the
635 field need not be specified in machine descriptions. */
636 DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
638 /* Reference to an assembler label in the code for this function.
639 The operand is a CODE_LABEL found in the insn chain.
640 The unprinted fields 1 and 2 are used in flow.c for the
641 LABEL_NEXTREF and CONTAINING_INSN. */
642 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
644 /* Reference to a named label: the string that is the first operand,
645 with `_' added implicitly in front.
646 Exception: if the first character explicitly given is `*',
647 to give it to the assembler, remove the `*' and do not add `_'. */
648 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
650 /* The condition code register is represented, in our imagination,
651 as a register holding a value that can be compared to zero.
652 In fact, the machine has already compared them and recorded the
653 results; but instructions that look at the condition code
654 pretend to be looking at the entire value and comparing it. */
655 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
657 /* Reference to the address of a register. Removed by purge_addressof after
658 CSE has elided as many as possible.
659 1st operand: the register we may need the address of.
660 2nd operand: the original pseudo regno we were generated for.
661 3rd operand: the decl for the object in the register, for
664 DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
666 /* =====================================================================
667 A QUEUED expression really points to a member of the queue of instructions
668 to be output later for postincrement/postdecrement.
669 QUEUED expressions never become part of instructions.
670 When a QUEUED expression would be put into an instruction,
671 instead either the incremented variable or a copy of its previous
675 0. the variable to be incremented (a REG rtx).
676 1. the incrementing instruction, or 0 if it hasn't been output yet.
677 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
678 3. the body to use for the incrementing instruction
679 4. the next QUEUED expression in the queue.
680 ====================================================================== */
682 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
684 /* ----------------------------------------------------------------------
685 Expressions for operators in an rtl pattern
686 ---------------------------------------------------------------------- */
688 /* if_then_else. This is used in representing ordinary
689 conditional jump instructions.
694 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
696 /* General conditional. The first operand is a vector composed of pairs of
697 expressions. The first element of each pair is evaluated, in turn.
698 The value of the conditional is the second expression of the first pair
699 whose first expression evaluates non-zero. If none of the expressions is
700 true, the second operand will be used as the value of the conditional.
702 This should be replaced with use of IF_THEN_ELSE. */
703 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
705 /* Comparison, produces a condition code result. */
706 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
709 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
711 /* Operand 0 minus operand 1. */
712 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
714 /* Minus operand 0. */
715 DEF_RTL_EXPR(NEG, "neg", "e", '1')
717 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
719 /* Operand 0 divided by operand 1. */
720 DEF_RTL_EXPR(DIV, "div", "ee", '2')
721 /* Remainder of operand 0 divided by operand 1. */
722 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
724 /* Unsigned divide and remainder. */
725 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
726 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
728 /* Bitwise operations. */
729 DEF_RTL_EXPR(AND, "and", "ee", 'c')
731 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
733 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
735 DEF_RTL_EXPR(NOT, "not", "e", '1')
738 0: value to be shifted.
739 1: number of bits. */
740 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
741 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
742 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
743 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
744 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
746 /* Minimum and maximum values of two operands. We need both signed and
747 unsigned forms. (We cannot use MIN for SMIN because it conflicts
748 with a macro of the same name.) */
750 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
751 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
752 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
753 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
755 /* These unary operations are used to represent incrementation
756 and decrementation as they occur in memory addresses.
757 The amount of increment or decrement are not represented
758 because they can be understood from the machine-mode of the
759 containing MEM. These operations exist in only two cases:
760 1. pushes onto the stack.
761 2. created automatically by the life_analysis pass in flow.c. */
762 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
763 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
764 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
765 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
767 /* These binary operations are used to represent generic address
768 side-effects in memory addresses, except for simple incrementation
769 or decrementation which use the above operations. They are
770 created automatically by the life_analysis pass in flow.c.
771 (Note that these operators are currently placeholders.) */
772 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'x')
773 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'x')
775 /* Comparison operations. The ordered comparisons exist in two
776 flavors, signed and unsigned. */
777 DEF_RTL_EXPR(NE, "ne", "ee", '<')
778 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
779 DEF_RTL_EXPR(GE, "ge", "ee", '<')
780 DEF_RTL_EXPR(GT, "gt", "ee", '<')
781 DEF_RTL_EXPR(LE, "le", "ee", '<')
782 DEF_RTL_EXPR(LT, "lt", "ee", '<')
783 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
784 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
785 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
786 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
788 /* Additional floating point unordered comparision flavors. */
789 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
790 DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
792 /* These are equivalent to unordered or ... */
793 DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
794 DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
795 DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
796 DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
797 DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
799 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
800 DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
802 /* Represents the result of sign-extending the sole operand.
803 The machine modes of the operand and of the SIGN_EXTEND expression
804 determine how much sign-extension is going on. */
805 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
807 /* Similar for zero-extension (such as unsigned short to int). */
808 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
810 /* Similar but here the operand has a wider mode. */
811 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
813 /* Similar for extending floating-point values (such as SFmode to DFmode). */
814 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
815 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
817 /* Conversion of fixed point operand to floating point value. */
818 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
820 /* With fixed-point machine mode:
821 Conversion of floating point operand to fixed point value.
822 Value is defined only when the operand's value is an integer.
823 With floating-point machine mode (and operand with same mode):
824 Operand is rounded toward zero to produce an integer value
825 represented in floating point. */
826 DEF_RTL_EXPR(FIX, "fix", "e", '1')
828 /* Conversion of unsigned fixed point operand to floating point value. */
829 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
831 /* With fixed-point machine mode:
832 Conversion of floating point operand to *unsigned* fixed point value.
833 Value is defined only when the operand's value is an integer. */
834 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
837 DEF_RTL_EXPR(ABS, "abs", "e", '1')
840 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
842 /* Find first bit that is set.
843 Value is 1 + number of trailing zeros in the arg.,
845 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
847 /* Reference to a signed bit-field of specified size and position.
848 Operand 0 is the memory unit (usually SImode or QImode) which
849 contains the field's first bit. Operand 1 is the width, in bits.
850 Operand 2 is the number of bits in the memory unit before the
851 first bit of this field.
852 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
853 operand 2 counts from the msb of the memory unit.
854 Otherwise, the first bit is the lsb and operand 2 counts from
855 the lsb of the memory unit. */
856 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
858 /* Similar for unsigned bit-field. */
859 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
861 /* For RISC machines. These save memory when splitting insns. */
863 /* HIGH are the high-order bits of a constant expression. */
864 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
866 /* LO_SUM is the sum of a register and the low-order bits
867 of a constant expression. */
868 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
870 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
871 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
872 the registers that can be substituted within this range. Operand 3 is the
873 number of calls in the range. Operand 4 is the number of insns in the
874 range. Operand 5 is the unique range number for this range. Operand 6 is
875 the basic block # of the start of the live range. Operand 7 is the basic
876 block # of the end of the live range. Operand 8 is the loop depth. Operand
877 9 is a bitmap of the registers live at the start of the range. Operand 10
878 is a bitmap of the registers live at the end of the range. Operand 11 is
879 marker number for the start of the range. Operand 12 is the marker number
880 for the end of the range. */
881 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
883 /* Registers that can be substituted within the range. Operand 0 is the
884 original pseudo register number. Operand 1 will be filled in with the
885 pseudo register the value is copied for the duration of the range. Operand
886 2 is the number of references within the range to the register. Operand 3
887 is the number of sets or clobbers of the register in the range. Operand 4
888 is the number of deaths the register has. Operand 5 is the copy flags that
889 give the status of whether a copy is needed from the original register to
890 the new register at the beginning of the range, or whether a copy from the
891 new register back to the original at the end of the range. Operand 6 is the
892 live length. Operand 7 is the number of calls that this register is live
893 across. Operand 8 is the symbol node of the variable if the register is a
894 user variable. Operand 9 is the block node that the variable is declared
895 in if the register is a user variable. */
896 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
898 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
899 the different ranges a variable is in where it is copied to a different
900 pseudo register. Operand 1 is the block that the variable is declared in.
901 Operand 2 is the number of distinct ranges. */
902 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
904 /* Information about the registers that are live at the current point. Operand
905 0 is the live bitmap. Operand 1 is the original block number. */
906 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
908 /* A unary `__builtin_constant_p' expression. These are only emitted
909 during RTL generation, and then only if optimize > 0. They are
910 eliminated by the first CSE pass. */
911 DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
913 /* A placeholder for a CALL_INSN which may be turned into a normal call,
914 a sibling (tail) call or tail recursion.
916 Immediately after RTL generation, this placeholder will be replaced
917 by the insns to perform the call, sibcall or tail recursion.
919 This RTX has 4 operands. The first three are lists of instructions to
920 perform the call as a normal call, sibling call and tail recursion
921 respectively. The latter two lists may be NULL, the first may never
924 The last operand is the tail recursion CODE_LABEL, which may be NULL if no
925 potential tail recursive calls were found.
927 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
928 after we select a call method.
930 This method of tail-call elimination is intended to be replaced by
931 tree-based optimizations once front-end conversions are complete. */
932 DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
934 /* The SSA phi operator.
936 The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT
937 containing the block number of the predecessor through which control
938 has passed when the register at element 2N is used.
940 Note that PHI may only appear at the beginning of a basic block.
942 ??? There may be multiple PHI insns, but they are all evaluated
943 in parallel. This probably ought to be changed to use a real
944 PARALLEL, as that would be less confusing and more in the spirit
945 of canonical RTL. It is, however, easier to manipulate this way. */
946 DEF_RTL_EXPR(PHI, "phi", "E", 'x')
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