1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 2, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 /* Expression definitions and descriptions for all targets are in this file.
27 Some will not be used for some targets.
29 The fields in the cpp macro call "DEF_RTL_EXPR()"
30 are used to create declarations in the C source of the compiler.
34 1. The internal name of the rtx used in the C source.
35 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
36 By convention these are in UPPER_CASE.
38 2. The name of the rtx in the external ASCII format read by
39 read_rtx(), and printed by print_rtx().
40 These names are stored in rtx_name[].
41 By convention these are the internal (field 1) names in lower_case.
43 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
44 These formats are stored in rtx_format[].
45 The meaning of the formats is documented in front of this array in rtl.c
47 4. The class of the rtx. These are stored in rtx_class and are accessed
48 via the GET_RTX_CLASS macro. They are defined as follows:
51 an rtx code that can be used to represent a constant object
54 an rtx code that can be used to represent an object (e.g, REG, MEM)
56 an rtx code for a comparison (e.g, LT, GT)
58 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
60 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
62 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
64 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
66 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
68 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
70 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
72 an rtx code for something that matches in insns (e.g, MATCH_DUP)
74 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
78 All of the expressions that appear only in machine descriptions,
79 not in RTL used by the compiler itself, are at the end of the file. */
81 /* Unknown, or no such operation; the enumeration constant should have
83 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
85 /* ---------------------------------------------------------------------
86 Expressions used in constructing lists.
87 --------------------------------------------------------------------- */
89 /* a linked list of expressions */
90 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
92 /* a linked list of instructions.
93 The insns are represented in print by their uids. */
94 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
96 /* SEQUENCE appears in the result of a `gen_...' function
97 for a DEFINE_EXPAND that wants to make several insns.
98 Its elements are the bodies of the insns that should be made.
99 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
100 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
102 /* Refers to the address of its argument. This is only used in alias.c. */
103 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
105 /* ----------------------------------------------------------------------
106 Expression types used for things in the instruction chain.
108 All formats must start with "iuu" to handle the chain.
109 Each insn expression holds an rtl instruction and its semantics
110 during back-end processing.
111 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
113 ---------------------------------------------------------------------- */
115 /* An instruction that cannot jump. */
116 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
118 /* An instruction that can possibly jump.
119 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
120 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
122 /* An instruction that can possibly call a subroutine
123 but which will not change which instruction comes next
124 in the current function.
125 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
126 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
127 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
129 /* A marker that indicates that control will not flow through. */
130 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
132 /* Holds a label that is followed by instructions.
134 4: is used in jump.c for the use-count of the label.
135 5: is used in flow.c to point to the chain of label_ref's to this label.
136 6: is a number that is unique in the entire compilation.
137 7: is the user-given name of the label, if any. */
138 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
140 #ifdef USE_MAPPED_LOCATION
141 /* Say where in the code a source line starts, for symbol table's sake.
143 4: unused if line number > 0, note-specific data otherwise.
144 5: line number if > 0, enum note_insn otherwise.
145 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
147 /* Say where in the code a source line starts, for symbol table's sake.
149 4: filename, if line number > 0, note-specific data otherwise.
150 5: line number if > 0, enum note_insn otherwise.
151 6: unique number if line number == note_insn_deleted_label. */
153 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
155 /* ----------------------------------------------------------------------
156 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
157 ---------------------------------------------------------------------- */
159 /* Conditionally execute code.
160 Operand 0 is the condition that if true, the code is executed.
161 Operand 1 is the code to be executed (typically a SET).
163 Semantics are that there are no side effects if the condition
164 is false. This pattern is created automatically by the if_convert
165 pass run after reload or by target-specific splitters. */
166 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
168 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
169 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
171 #ifdef USE_MAPPED_LOCATION
172 /* A string that is passed through to the assembler as input.
173 One can obviously pass comments through by using the
174 assembler comment syntax.
175 These occur in an insn all by themselves as the PATTERN.
176 They also appear inside an ASM_OPERANDS
177 as a convenient way to hold a string. */
178 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
180 /* An assembler instruction with operands.
181 1st operand is the instruction template.
182 2nd operand is the constraint for the output.
183 3rd operand is the number of the output this expression refers to.
184 When an insn stores more than one value, a separate ASM_OPERANDS
185 is made for each output; this integer distinguishes them.
186 4th is a vector of values of input operands.
187 5th is a vector of modes and constraints for the input operands.
188 Each element is an ASM_INPUT containing a constraint string
189 and whose mode indicates the mode of the input operand.
190 6th is the source line number. */
191 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
193 /* A string that is passed through to the assembler as input.
194 One can obviously pass comments through by using the
195 assembler comment syntax.
196 These occur in an insn all by themselves as the PATTERN.
197 They also appear inside an ASM_OPERANDS
198 as a convenient way to hold a string. */
199 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "ssi", RTX_EXTRA)
201 /* An assembler instruction with operands.
202 1st operand is the instruction template.
203 2nd operand is the constraint for the output.
204 3rd operand is the number of the output this expression refers to.
205 When an insn stores more than one value, a separate ASM_OPERANDS
206 is made for each output; this integer distinguishes them.
207 4th is a vector of values of input operands.
208 5th is a vector of modes and constraints for the input operands.
209 Each element is an ASM_INPUT containing a constraint string
210 and whose mode indicates the mode of the input operand.
211 6th is the name of the containing source file.
212 7th is the source line number. */
213 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
216 /* A machine-specific operation.
217 1st operand is a vector of operands being used by the operation so that
218 any needed reloads can be done.
219 2nd operand is a unique value saying which of a number of machine-specific
220 operations is to be performed.
221 (Note that the vector must be the first operand because of the way that
222 genrecog.c record positions within an insn.)
223 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
224 or inside an expression. */
225 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
227 /* Similar, but a volatile operation and one which may trap. */
228 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
230 /* Vector of addresses, stored as full words. */
231 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
232 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
234 /* Vector of address differences X0 - BASE, X1 - BASE, ...
235 First operand is BASE; the vector contains the X's.
236 The machine mode of this rtx says how much space to leave
237 for each difference and is adjusted by branch shortening if
238 CASE_VECTOR_SHORTEN_MODE is defined.
239 The third and fourth operands store the target labels with the
240 minimum and maximum addresses respectively.
241 The fifth operand stores flags for use by branch shortening.
242 Set at the start of shorten_branches:
243 min_align: the minimum alignment for any of the target labels.
244 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
245 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
246 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
247 min_after_base: true iff minimum address target label is after BASE.
248 max_after_base: true iff maximum address target label is after BASE.
249 Set by the actual branch shortening process:
250 offset_unsigned: true iff offsets have to be treated as unsigned.
251 scale: scaling that is necessary to make offsets fit into the mode.
253 The third, fourth and fifth operands are only valid when
254 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
257 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
259 /* Memory prefetch, with attributes supported on some targets.
260 Operand 1 is the address of the memory to fetch.
261 Operand 2 is 1 for a write access, 0 otherwise.
262 Operand 3 is the level of temporal locality; 0 means there is no
263 temporal locality and 1, 2, and 3 are for increasing levels of temporal
266 The attributes specified by operands 2 and 3 are ignored for targets
267 whose prefetch instructions do not support them. */
268 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
270 /* ----------------------------------------------------------------------
271 At the top level of an instruction (perhaps under PARALLEL).
272 ---------------------------------------------------------------------- */
275 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
276 Operand 2 is the value stored there.
277 ALL assignment must use SET.
278 Instructions that do multiple assignments must use multiple SET,
280 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
282 /* Indicate something is used in a way that we don't want to explain.
283 For example, subroutine calls will use the register
284 in which the static chain is passed. */
285 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
287 /* Indicate something is clobbered in a way that we don't want to explain.
288 For example, subroutine calls will clobber some physical registers
289 (the ones that are by convention not saved). */
290 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
292 /* Call a subroutine.
293 Operand 1 is the address to call.
294 Operand 2 is the number of arguments. */
296 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
298 /* Return from a subroutine. */
300 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
303 Operand 1 is the condition.
304 Operand 2 is the trap code.
305 For an unconditional trap, make the condition (const_int 1). */
306 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
308 /* Placeholder for _Unwind_Resume before we know if a function call
309 or a branch is needed. Operand 1 is the exception region from
310 which control is flowing. */
311 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
313 /* ----------------------------------------------------------------------
314 Primitive values for use in expressions.
315 ---------------------------------------------------------------------- */
317 /* numeric integer constant */
318 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
320 /* numeric floating point constant.
321 Operands hold the value. They are all 'w' and there may be from 2 to 6;
323 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
325 /* Describes a vector constant. */
326 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
328 /* String constant. Used for attributes in machine descriptions and
329 for special cases in DWARF2 debug output. NOT used for source-
330 language string constants. */
331 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
333 /* This is used to encapsulate an expression whose value is constant
334 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
335 recognized as a constant operand rather than by arithmetic instructions. */
337 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
339 /* program counter. Ordinary jumps are represented
340 by a SET whose first operand is (PC). */
341 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
343 /* Used in the cselib routines to describe a value. Objects of this
344 kind are only allocated in cselib.c, in an alloc pool instead of
345 in GC memory. The only operand of a VALUE is a cselib_val_struct. */
346 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
348 /* A register. The "operand" is the register number, accessed with
349 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
350 than a hardware register is being referred to. The second operand
351 holds the original register number - this will be different for a
352 pseudo register that got turned into a hard register. The third
353 operand points to a reg_attrs structure.
354 This rtx needs to have as many (or more) fields as a MEM, since we
355 can change REG rtx's into MEMs during reload. */
356 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
358 /* A scratch register. This represents a register used only within a
359 single insn. It will be turned into a REG during register allocation
360 or reload unless the constraint indicates that the register won't be
361 needed, in which case it can remain a SCRATCH. This code is
362 marked as having one operand so it can be turned into a REG. */
363 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
365 /* One word of a multi-word value.
366 The first operand is the complete value; the second says which word.
367 The WORDS_BIG_ENDIAN flag controls whether word number 0
368 (as numbered in a SUBREG) is the most or least significant word.
370 This is also used to refer to a value in a different machine mode.
371 For example, it can be used to refer to a SImode value as if it were
372 Qimode, or vice versa. Then the word number is always 0. */
373 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
375 /* This one-argument rtx is used for move instructions
376 that are guaranteed to alter only the low part of a destination.
377 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
378 has an unspecified effect on the high part of REG,
379 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
380 is guaranteed to alter only the bits of REG that are in HImode.
382 The actual instruction used is probably the same in both cases,
383 but the register constraints may be tighter when STRICT_LOW_PART
386 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
388 /* (CONCAT a b) represents the virtual concatenation of a and b
389 to make a value that has as many bits as a and b put together.
390 This is used for complex values. Normally it appears only
391 in DECL_RTLs and during RTL generation, but not in the insn chain. */
392 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
394 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
395 all An to make a value. This is an extension of CONCAT to larger
396 number of components. Like CONCAT, it should not appear in the
397 insn chain. Every element of the CONCATN is the same size. */
398 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
400 /* A memory location; operand is the address. The second operand is the
401 alias set to which this MEM belongs. We use `0' instead of `w' for this
402 field so that the field need not be specified in machine descriptions. */
403 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
405 /* Reference to an assembler label in the code for this function.
406 The operand is a CODE_LABEL found in the insn chain. */
407 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
409 /* Reference to a named label:
410 Operand 0: label name
411 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
412 Operand 2: tree from which this symbol is derived, or null.
413 This is either a DECL node, or some kind of constant. */
414 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
416 /* The condition code register is represented, in our imagination,
417 as a register holding a value that can be compared to zero.
418 In fact, the machine has already compared them and recorded the
419 results; but instructions that look at the condition code
420 pretend to be looking at the entire value and comparing it. */
421 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
423 /* ----------------------------------------------------------------------
424 Expressions for operators in an rtl pattern
425 ---------------------------------------------------------------------- */
427 /* if_then_else. This is used in representing ordinary
428 conditional jump instructions.
433 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
435 /* Comparison, produces a condition code result. */
436 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
439 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
441 /* Operand 0 minus operand 1. */
442 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
444 /* Minus operand 0. */
445 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
447 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
449 /* Operand 0 divided by operand 1. */
450 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
451 /* Remainder of operand 0 divided by operand 1. */
452 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
454 /* Unsigned divide and remainder. */
455 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
456 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
458 /* Bitwise operations. */
459 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
460 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
461 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
462 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
465 0: value to be shifted.
466 1: number of bits. */
467 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
468 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
469 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
470 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
471 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
473 /* Minimum and maximum values of two operands. We need both signed and
474 unsigned forms. (We cannot use MIN for SMIN because it conflicts
475 with a macro of the same name.) The signed variants should be used
476 with floating point. Further, if both operands are zeros, or if either
477 operand is NaN, then it is unspecified which of the two operands is
478 returned as the result. */
480 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
481 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
482 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
483 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
485 /* These unary operations are used to represent incrementation
486 and decrementation as they occur in memory addresses.
487 The amount of increment or decrement are not represented
488 because they can be understood from the machine-mode of the
489 containing MEM. These operations exist in only two cases:
490 1. pushes onto the stack.
491 2. created automatically by the life_analysis pass in flow.c. */
492 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
493 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
494 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
495 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
497 /* These binary operations are used to represent generic address
498 side-effects in memory addresses, except for simple incrementation
499 or decrementation which use the above operations. They are
500 created automatically by the life_analysis pass in flow.c.
501 The first operand is a REG which is used as the address.
502 The second operand is an expression that is assigned to the
503 register, either before (PRE_MODIFY) or after (POST_MODIFY)
504 evaluating the address.
505 Currently, the compiler can only handle second operands of the
506 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
507 the first operand of the PLUS has to be the same register as
508 the first operand of the *_MODIFY. */
509 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
510 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
512 /* Comparison operations. The ordered comparisons exist in two
513 flavors, signed and unsigned. */
514 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
515 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
516 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
517 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
518 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
519 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
520 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
521 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
522 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
523 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
525 /* Additional floating point unordered comparison flavors. */
526 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
527 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
529 /* These are equivalent to unordered or ... */
530 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
531 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
532 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
533 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
534 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
536 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
537 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
539 /* Represents the result of sign-extending the sole operand.
540 The machine modes of the operand and of the SIGN_EXTEND expression
541 determine how much sign-extension is going on. */
542 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
544 /* Similar for zero-extension (such as unsigned short to int). */
545 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
547 /* Similar but here the operand has a wider mode. */
548 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
550 /* Similar for extending floating-point values (such as SFmode to DFmode). */
551 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
552 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
554 /* Conversion of fixed point operand to floating point value. */
555 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
557 /* With fixed-point machine mode:
558 Conversion of floating point operand to fixed point value.
559 Value is defined only when the operand's value is an integer.
560 With floating-point machine mode (and operand with same mode):
561 Operand is rounded toward zero to produce an integer value
562 represented in floating point. */
563 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
565 /* Conversion of unsigned fixed point operand to floating point value. */
566 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
568 /* With fixed-point machine mode:
569 Conversion of floating point operand to *unsigned* fixed point value.
570 Value is defined only when the operand's value is an integer. */
571 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
574 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
577 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
580 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
582 /* Find first bit that is set.
583 Value is 1 + number of trailing zeros in the arg.,
585 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
587 /* Count leading zeros. */
588 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
590 /* Count trailing zeros. */
591 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
593 /* Population count (number of 1 bits). */
594 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
596 /* Population parity (number of 1 bits modulo 2). */
597 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
599 /* Reference to a signed bit-field of specified size and position.
600 Operand 0 is the memory unit (usually SImode or QImode) which
601 contains the field's first bit. Operand 1 is the width, in bits.
602 Operand 2 is the number of bits in the memory unit before the
603 first bit of this field.
604 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
605 operand 2 counts from the msb of the memory unit.
606 Otherwise, the first bit is the lsb and operand 2 counts from
607 the lsb of the memory unit.
608 This kind of expression can not appear as an lvalue in RTL. */
609 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
611 /* Similar for unsigned bit-field.
612 But note! This kind of expression _can_ appear as an lvalue. */
613 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
615 /* For RISC machines. These save memory when splitting insns. */
617 /* HIGH are the high-order bits of a constant expression. */
618 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
620 /* LO_SUM is the sum of a register and the low-order bits
621 of a constant expression. */
622 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
624 /* Describes a merge operation between two vector values.
625 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
626 that specifies where the parts of the result are taken from. Set bits
627 indicate operand 0, clear bits indicate operand 1. The parts are defined
628 by the mode of the vectors. */
629 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
631 /* Describes an operation that selects parts of a vector.
632 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
633 a CONST_INT for each of the subparts of the result vector, giving the
634 number of the source subpart that should be stored into it. */
635 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
637 /* Describes a vector concat operation. Operands 0 and 1 are the source
638 vectors, the result is a vector that is as long as operands 0 and 1
639 combined and is the concatenation of the two source vectors. */
640 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
642 /* Describes an operation that converts a small vector into a larger one by
643 duplicating the input values. The output vector mode must have the same
644 submodes as the input vector mode, and the number of output parts must be
645 an integer multiple of the number of input parts. */
646 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
648 /* Addition with signed saturation */
649 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
651 /* Addition with unsigned saturation */
652 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
654 /* Operand 0 minus operand 1, with signed saturation. */
655 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
657 /* Negation with signed saturation. */
658 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
660 /* Absolute value with signed saturation. */
661 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
663 /* Shift left with signed saturation. */
664 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
666 /* Operand 0 minus operand 1, with unsigned saturation. */
667 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
669 /* Signed saturating truncate. */
670 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
672 /* Unsigned saturating truncate. */
673 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
675 /* Information about the variable and its location. */
676 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
678 /* All expressions from this point forward appear only in machine
680 #ifdef GENERATOR_FILE
682 /* Include a secondary machine-description file at this point. */
683 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
685 /* Pattern-matching operators: */
687 /* Use the function named by the second arg (the string)
688 as a predicate; if matched, store the structure that was matched
689 in the operand table at index specified by the first arg (the integer).
690 If the second arg is the null string, the structure is just stored.
692 A third string argument indicates to the register allocator restrictions
693 on where the operand can be allocated.
695 If the target needs no restriction on any instruction this field should
698 The string is prepended by:
699 '=' to indicate the operand is only written to.
700 '+' to indicate the operand is both read and written to.
702 Each character in the string represents an allocable class for an operand.
703 'g' indicates the operand can be any valid class.
704 'i' indicates the operand can be immediate (in the instruction) data.
705 'r' indicates the operand can be in a register.
706 'm' indicates the operand can be in memory.
707 'o' a subset of the 'm' class. Those memory addressing modes that
708 can be offset at compile time (have a constant added to them).
710 Other characters indicate target dependent operand classes and
711 are described in each target's machine description.
713 For instructions with more than one operand, sets of classes can be
714 separated by a comma to indicate the appropriate multi-operand constraints.
715 There must be a 1 to 1 correspondence between these sets of classes in
716 all operands for an instruction.
718 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
720 /* Match a SCRATCH or a register. When used to generate rtl, a
721 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
722 the desired mode and the first argument is the operand number.
723 The second argument is the constraint. */
724 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
726 /* Apply a predicate, AND match recursively the operands of the rtx.
727 Operand 0 is the operand-number, as in match_operand.
728 Operand 1 is a predicate to apply (as a string, a function name).
729 Operand 2 is a vector of expressions, each of which must match
730 one subexpression of the rtx this construct is matching. */
731 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
733 /* Match a PARALLEL of arbitrary length. The predicate is applied
734 to the PARALLEL and the initial expressions in the PARALLEL are matched.
735 Operand 0 is the operand-number, as in match_operand.
736 Operand 1 is a predicate to apply to the PARALLEL.
737 Operand 2 is a vector of expressions, each of which must match the
738 corresponding element in the PARALLEL. */
739 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
741 /* Match only something equal to what is stored in the operand table
742 at the index specified by the argument. Use with MATCH_OPERAND. */
743 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
745 /* Match only something equal to what is stored in the operand table
746 at the index specified by the argument. Use with MATCH_OPERATOR. */
747 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
749 /* Match only something equal to what is stored in the operand table
750 at the index specified by the argument. Use with MATCH_PARALLEL. */
751 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
753 /* Appears only in define_predicate/define_special_predicate
754 expressions. Evaluates true only if the operand has an RTX code
755 from the set given by the argument (a comma-separated list). If the
756 second argument is present and nonempty, it is a sequence of digits
757 and/or letters which indicates the subexpression to test, using the
758 same syntax as genextract/genrecog's location strings: 0-9 for
759 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
760 the result of the one before it. */
761 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
763 /* Appears only in define_predicate/define_special_predicate
764 expressions. The argument is a C expression to be injected at this
765 point in the predicate formula. */
766 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
768 /* Insn (and related) definitions. */
770 /* Definition of the pattern for one kind of instruction.
772 0: names this instruction.
773 If the name is the null string, the instruction is in the
774 machine description just to be recognized, and will never be emitted by
775 the tree to rtl expander.
777 2: is a string which is a C expression
778 giving an additional condition for recognizing this pattern.
779 A null string means no extra condition.
780 3: is the action to execute if this pattern is matched.
781 If this assembler code template starts with a * then it is a fragment of
782 C code to run to decide on a template to use. Otherwise, it is the
784 4: optionally, a vector of attributes for this insn.
786 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
788 /* Definition of a peephole optimization.
789 1st operand: vector of insn patterns to match
790 2nd operand: C expression that must be true
791 3rd operand: template or C code to produce assembler output.
792 4: optionally, a vector of attributes for this insn.
794 This form is deprecated; use define_peephole2 instead. */
795 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
797 /* Definition of a split operation.
798 1st operand: insn pattern to match
799 2nd operand: C expression that must be true
800 3rd operand: vector of insn patterns to place into a SEQUENCE
801 4th operand: optionally, some C code to execute before generating the
802 insns. This might, for example, create some RTX's and store them in
803 elements of `recog_data.operand' for use by the vector of
805 (`operands' is an alias here for `recog_data.operand'). */
806 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
808 /* Definition of an insn and associated split.
809 This is the concatenation, with a few modifications, of a define_insn
810 and a define_split which share the same pattern.
812 0: names this instruction.
813 If the name is the null string, the instruction is in the
814 machine description just to be recognized, and will never be emitted by
815 the tree to rtl expander.
817 2: is a string which is a C expression
818 giving an additional condition for recognizing this pattern.
819 A null string means no extra condition.
820 3: is the action to execute if this pattern is matched.
821 If this assembler code template starts with a * then it is a fragment of
822 C code to run to decide on a template to use. Otherwise, it is the
824 4: C expression that must be true for split. This may start with "&&"
825 in which case the split condition is the logical and of the insn
826 condition and what follows the "&&" of this operand.
827 5: vector of insn patterns to place into a SEQUENCE
828 6: optionally, some C code to execute before generating the
829 insns. This might, for example, create some RTX's and store them in
830 elements of `recog_data.operand' for use by the vector of
832 (`operands' is an alias here for `recog_data.operand').
833 7: optionally, a vector of attributes for this insn. */
834 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
836 /* Definition of an RTL peephole operation.
837 Follows the same arguments as define_split. */
838 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
840 /* Define how to generate multiple insns for a standard insn name.
841 1st operand: the insn name.
842 2nd operand: vector of insn-patterns.
843 Use match_operand to substitute an element of `recog_data.operand'.
844 3rd operand: C expression that must be true for this to be available.
845 This may not test any operands.
846 4th operand: Extra C code to execute before generating the insns.
847 This might, for example, create some RTX's and store them in
848 elements of `recog_data.operand' for use by the vector of
850 (`operands' is an alias here for `recog_data.operand'). */
851 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
853 /* Define a requirement for delay slots.
854 1st operand: Condition involving insn attributes that, if true,
855 indicates that the insn requires the number of delay slots
857 2nd operand: Vector whose length is the three times the number of delay
859 Each entry gives three conditions, each involving attributes.
860 The first must be true for an insn to occupy that delay slot
861 location. The second is true for all insns that can be
862 annulled if the branch is true and the third is true for all
863 insns that can be annulled if the branch is false.
865 Multiple DEFINE_DELAYs may be present. They indicate differing
866 requirements for delay slots. */
867 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
869 /* Define attribute computation for `asm' instructions. */
870 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
872 /* Definition of a conditional execution meta operation. Automatically
873 generates new instances of DEFINE_INSN, selected by having attribute
874 "predicable" true. The new pattern will contain a COND_EXEC and the
875 predicate at top-level.
878 0: The predicate pattern. The top-level form should match a
879 relational operator. Operands should have only one alternative.
880 1: A C expression giving an additional condition for recognizing
881 the generated pattern.
882 2: A template or C code to produce assembler output. */
883 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
885 /* Definition of an operand predicate. The difference between
886 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
887 not warn about a match_operand with no mode if it has a predicate
888 defined with DEFINE_SPECIAL_PREDICATE.
891 0: The name of the predicate.
892 1: A boolean expression which computes whether or not the predicate
893 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
894 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
895 can calculate the set of RTX codes that can possibly match.
896 2: A C function body which must return true for the predicate to match.
897 Optional. Use this when the test is too complicated to fit into a
898 match_test expression. */
899 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
900 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
902 /* Definition of a register operand constraint. This simply maps the
903 constraint string to a register class.
906 0: The name of the constraint (often, but not always, a single letter).
907 1: A C expression which evaluates to the appropriate register class for
908 this constraint. If this is not just a constant, it should look only
909 at -m switches and the like.
910 2: A docstring for this constraint, in Texinfo syntax; not currently
911 used, in future will be incorporated into the manual's list of
912 machine-specific operand constraints. */
913 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
915 /* Definition of a non-register operand constraint. These look at the
916 operand and decide whether it fits the constraint.
918 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
919 It is appropriate for constant-only constraints, and most others.
921 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
922 to match, if it doesn't already, by converting the operand to the form
923 (mem (reg X)) where X is a base register. It is suitable for constraints
924 that describe a subset of all memory references.
926 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
927 to match, if it doesn't already, by converting the operand to the form
928 (reg X) where X is a base register. It is suitable for constraints that
929 describe a subset of all address references.
931 When in doubt, use plain DEFINE_CONSTRAINT.
934 0: The name of the constraint (often, but not always, a single letter).
935 1: A docstring for this constraint, in Texinfo syntax; not currently
936 used, in future will be incorporated into the manual's list of
937 machine-specific operand constraints.
938 2: A boolean expression which computes whether or not the constraint
939 matches. It should follow the same rules as a define_predicate
940 expression, including the bit about specifying the set of RTX codes
941 that could possibly match. MATCH_TEST subexpressions may make use of
943 `op' - the RTL object defining the operand.
944 `mode' - the mode of `op'.
945 `ival' - INTVAL(op), if op is a CONST_INT.
946 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
947 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
948 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
950 Do not use ival/hval/lval/rval if op is not the appropriate kind of
952 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
953 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
954 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
957 /* Constructions for CPU pipeline description described by NDFAs. */
959 /* (define_cpu_unit string [string]) describes cpu functional
960 units (separated by comma).
962 1st operand: Names of cpu functional units.
963 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
965 All define_reservations, define_cpu_units, and
966 define_query_cpu_units should have unique names which may not be
968 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
970 /* (define_query_cpu_unit string [string]) describes cpu functional
971 units analogously to define_cpu_unit. The reservation of such
972 units can be queried for automaton state. */
973 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
975 /* (exclusion_set string string) means that each CPU functional unit
976 in the first string can not be reserved simultaneously with any
977 unit whose name is in the second string and vise versa. CPU units
978 in the string are separated by commas. For example, it is useful
979 for description CPU with fully pipelined floating point functional
980 unit which can execute simultaneously only single floating point
981 insns or only double floating point insns. All CPU functional
982 units in a set should belong to the same automaton. */
983 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
985 /* (presence_set string string) means that each CPU functional unit in
986 the first string can not be reserved unless at least one of pattern
987 of units whose names are in the second string is reserved. This is
988 an asymmetric relation. CPU units or unit patterns in the strings
989 are separated by commas. Pattern is one unit name or unit names
990 separated by white-spaces.
992 For example, it is useful for description that slot1 is reserved
993 after slot0 reservation for a VLIW processor. We could describe it
994 by the following construction
996 (presence_set "slot1" "slot0")
998 Or slot1 is reserved only after slot0 and unit b0 reservation. In
999 this case we could write
1001 (presence_set "slot1" "slot0 b0")
1003 All CPU functional units in a set should belong to the same
1005 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1007 /* (final_presence_set string string) is analogous to `presence_set'.
1008 The difference between them is when checking is done. When an
1009 instruction is issued in given automaton state reflecting all
1010 current and planned unit reservations, the automaton state is
1011 changed. The first state is a source state, the second one is a
1012 result state. Checking for `presence_set' is done on the source
1013 state reservation, checking for `final_presence_set' is done on the
1014 result reservation. This construction is useful to describe a
1015 reservation which is actually two subsequent reservations. For
1018 (presence_set "slot1" "slot0")
1020 the following insn will be never issued (because slot1 requires
1021 slot0 which is absent in the source state).
1023 (define_reservation "insn_and_nop" "slot0 + slot1")
1025 but it can be issued if we use analogous `final_presence_set'. */
1026 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1028 /* (absence_set string string) means that each CPU functional unit in
1029 the first string can be reserved only if each pattern of units
1030 whose names are in the second string is not reserved. This is an
1031 asymmetric relation (actually exclusion set is analogous to this
1032 one but it is symmetric). CPU units or unit patterns in the string
1033 are separated by commas. Pattern is one unit name or unit names
1034 separated by white-spaces.
1036 For example, it is useful for description that slot0 can not be
1037 reserved after slot1 or slot2 reservation for a VLIW processor. We
1038 could describe it by the following construction
1040 (absence_set "slot2" "slot0, slot1")
1042 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1043 slot1 and unit b1 are reserved . In this case we could write
1045 (absence_set "slot2" "slot0 b0, slot1 b1")
1047 All CPU functional units in a set should to belong the same
1049 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1051 /* (final_absence_set string string) is analogous to `absence_set' but
1052 checking is done on the result (state) reservation. See comments
1053 for `final_presence_set'. */
1054 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1056 /* (define_bypass number out_insn_names in_insn_names) names bypass
1057 with given latency (the first number) from insns given by the first
1058 string (see define_insn_reservation) into insns given by the second
1059 string. Insn names in the strings are separated by commas. The
1060 third operand is optional name of function which is additional
1061 guard for the bypass. The function will get the two insns as
1062 parameters. If the function returns zero the bypass will be
1063 ignored for this case. Additional guard is necessary to recognize
1064 complicated bypasses, e.g. when consumer is load address. */
1065 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1067 /* (define_automaton string) describes names of automata generated and
1068 used for pipeline hazards recognition. The names are separated by
1069 comma. Actually it is possibly to generate the single automaton
1070 but unfortunately it can be very large. If we use more one
1071 automata, the summary size of the automata usually is less than the
1072 single one. The automaton name is used in define_cpu_unit and
1073 define_query_cpu_unit. All automata should have unique names. */
1074 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1076 /* (automata_option string) describes option for generation of
1077 automata. Currently there are the following options:
1079 o "no-minimization" which makes no minimization of automata. This
1080 is only worth to do when we are debugging the description and
1081 need to look more accurately at reservations of states.
1083 o "time" which means printing additional time statistics about
1084 generation of automata.
1086 o "v" which means generation of file describing the result
1087 automata. The file has suffix `.dfa' and can be used for the
1088 description verification and debugging.
1090 o "w" which means generation of warning instead of error for
1091 non-critical errors.
1093 o "ndfa" which makes nondeterministic finite state automata.
1095 o "progress" which means output of a progress bar showing how many
1096 states were generated so far for automaton being processed. */
1097 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1099 /* (define_reservation string string) names reservation (the first
1100 string) of cpu functional units (the 2nd string). Sometimes unit
1101 reservations for different insns contain common parts. In such
1102 case, you can describe common part and use its name (the 1st
1103 parameter) in regular expression in define_insn_reservation. All
1104 define_reservations, define_cpu_units, and define_query_cpu_units
1105 should have unique names which may not be "nothing". */
1106 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1108 /* (define_insn_reservation name default_latency condition regexpr)
1109 describes reservation of cpu functional units (the 3nd operand) for
1110 instruction which is selected by the condition (the 2nd parameter).
1111 The first parameter is used for output of debugging information.
1112 The reservations are described by a regular expression according
1113 the following syntax:
1115 regexp = regexp "," oneof
1118 oneof = oneof "|" allof
1121 allof = allof "+" repeat
1124 repeat = element "*" number
1127 element = cpu_function_unit_name
1133 1. "," is used for describing start of the next cycle in
1136 2. "|" is used for describing the reservation described by the
1137 first regular expression *or* the reservation described by the
1138 second regular expression *or* etc.
1140 3. "+" is used for describing the reservation described by the
1141 first regular expression *and* the reservation described by the
1142 second regular expression *and* etc.
1144 4. "*" is used for convenience and simply means sequence in
1145 which the regular expression are repeated NUMBER times with
1146 cycle advancing (see ",").
1148 5. cpu functional unit name which means its reservation.
1150 6. reservation name -- see define_reservation.
1152 7. string "nothing" means no units reservation. */
1154 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1156 /* Expressions used for insn attributes. */
1158 /* Definition of an insn attribute.
1159 1st operand: name of the attribute
1160 2nd operand: comma-separated list of possible attribute values
1161 3rd operand: expression for the default value of the attribute. */
1162 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1164 /* Marker for the name of an attribute. */
1165 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1167 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1168 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1171 (set_attr "name" "value") is equivalent to
1172 (set (attr "name") (const_string "value")) */
1173 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1175 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1176 specify that attribute values are to be assigned according to the
1177 alternative matched.
1179 The following three expressions are equivalent:
1181 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1182 (eq_attrq "alternative" "2") (const_string "a2")]
1183 (const_string "a3")))
1184 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1185 (const_string "a3")])
1186 (set_attr "att" "a1,a2,a3")
1188 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1190 /* A conditional expression true if the value of the specified attribute of
1191 the current insn equals the specified value. The first operand is the
1192 attribute name and the second is the comparison value. */
1193 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1195 /* A special case of the above representing a set of alternatives. The first
1196 operand is bitmap of the set, the second one is the default value. */
1197 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1199 /* A conditional expression which is true if the specified flag is
1200 true for the insn being scheduled in reorg.
1202 genattr.c defines the following flags which can be tested by
1203 (attr_flag "foo") expressions in eligible_for_delay.
1205 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1207 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1209 /* General conditional. The first operand is a vector composed of pairs of
1210 expressions. The first element of each pair is evaluated, in turn.
1211 The value of the conditional is the second expression of the first pair
1212 whose first expression evaluates nonzero. If none of the expressions is
1213 true, the second operand will be used as the value of the conditional. */
1214 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1216 #endif /* GENERATOR_FILE */
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