1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
79 /* ---------------------------------------------------------------------
80 Expressions (and "meta" expressions) used for structuring the
81 rtl representation of a program.
82 --------------------------------------------------------------------- */
84 /* an expression code name unknown to the reader */
85 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
87 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
89 DEF_RTL_EXPR(NIL, "nil", "*", RTX_EXTRA)
94 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
96 /* ---------------------------------------------------------------------
97 Expressions used in constructing lists.
98 --------------------------------------------------------------------- */
100 /* a linked list of expressions */
101 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
103 /* a linked list of instructions.
104 The insns are represented in print by their uids. */
105 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
107 /* ----------------------------------------------------------------------
108 Expression types for machine descriptions.
109 These do not appear in actual rtl code in the compiler.
110 ---------------------------------------------------------------------- */
112 /* Appears only in machine descriptions.
113 Means use the function named by the second arg (the string)
114 as a predicate; if matched, store the structure that was matched
115 in the operand table at index specified by the first arg (the integer).
116 If the second arg is the null string, the structure is just stored.
118 A third string argument indicates to the register allocator restrictions
119 on where the operand can be allocated.
121 If the target needs no restriction on any instruction this field should
124 The string is prepended by:
125 '=' to indicate the operand is only written to.
126 '+' to indicate the operand is both read and written to.
128 Each character in the string represents an allocable class for an operand.
129 'g' indicates the operand can be any valid class.
130 'i' indicates the operand can be immediate (in the instruction) data.
131 'r' indicates the operand can be in a register.
132 'm' indicates the operand can be in memory.
133 'o' a subset of the 'm' class. Those memory addressing modes that
134 can be offset at compile time (have a constant added to them).
136 Other characters indicate target dependent operand classes and
137 are described in each target's machine description.
139 For instructions with more than one operand, sets of classes can be
140 separated by a comma to indicate the appropriate multi-operand constraints.
141 There must be a 1 to 1 correspondence between these sets of classes in
142 all operands for an instruction.
144 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
146 /* Appears only in machine descriptions.
147 Means match a SCRATCH or a register. When used to generate rtl, a
148 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
149 the desired mode and the first argument is the operand number.
150 The second argument is the constraint. */
151 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
153 /* Appears only in machine descriptions.
154 Means match only something equal to what is stored in the operand table
155 at the index specified by the argument. */
156 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
158 /* Appears only in machine descriptions.
159 Means apply a predicate, AND match recursively the operands of the rtx.
160 Operand 0 is the operand-number, as in match_operand.
161 Operand 1 is a predicate to apply (as a string, a function name).
162 Operand 2 is a vector of expressions, each of which must match
163 one subexpression of the rtx this construct is matching. */
164 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
166 /* Appears only in machine descriptions.
167 Means to match a PARALLEL of arbitrary length. The predicate is applied
168 to the PARALLEL and the initial expressions in the PARALLEL are matched.
169 Operand 0 is the operand-number, as in match_operand.
170 Operand 1 is a predicate to apply to the PARALLEL.
171 Operand 2 is a vector of expressions, each of which must match the
172 corresponding element in the PARALLEL. */
173 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
175 /* Appears only in machine descriptions.
176 Means match only something equal to what is stored in the operand table
177 at the index specified by the argument. For MATCH_OPERATOR. */
178 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
180 /* Appears only in machine descriptions.
181 Means match only something equal to what is stored in the operand table
182 at the index specified by the argument. For MATCH_PARALLEL. */
183 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
185 /* Appears only in define_predicate/define_special predicate
186 expressions in a machine description. Evaluates true only if the
187 operand has an RTX code from the set given by the argument (a
188 comma-separated list). */
189 DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH)
191 /* Appears only in define_predicate/define_special_predicate expressions
192 in a machine description. The argument is a C expression to be injected
193 at this point in the predicate formula. */
194 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
196 /* Appears only in machine descriptions.
197 Defines the pattern for one kind of instruction.
199 0: names this instruction.
200 If the name is the null string, the instruction is in the
201 machine description just to be recognized, and will never be emitted by
202 the tree to rtl expander.
204 2: is a string which is a C expression
205 giving an additional condition for recognizing this pattern.
206 A null string means no extra condition.
207 3: is the action to execute if this pattern is matched.
208 If this assembler code template starts with a * then it is a fragment of
209 C code to run to decide on a template to use. Otherwise, it is the
211 4: optionally, a vector of attributes for this insn.
213 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
215 /* Definition of a peephole optimization.
216 1st operand: vector of insn patterns to match
217 2nd operand: C expression that must be true
218 3rd operand: template or C code to produce assembler output.
219 4: optionally, a vector of attributes for this insn.
221 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
223 /* Definition of a split operation.
224 1st operand: insn pattern to match
225 2nd operand: C expression that must be true
226 3rd operand: vector of insn patterns to place into a SEQUENCE
227 4th operand: optionally, some C code to execute before generating the
228 insns. This might, for example, create some RTX's and store them in
229 elements of `recog_data.operand' for use by the vector of
231 (`operands' is an alias here for `recog_data.operand'). */
232 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
234 /* Definition of an insn and associated split.
235 This is the concatenation, with a few modifications, of a define_insn
236 and a define_split which share the same pattern.
238 0: names this instruction.
239 If the name is the null string, the instruction is in the
240 machine description just to be recognized, and will never be emitted by
241 the tree to rtl expander.
243 2: is a string which is a C expression
244 giving an additional condition for recognizing this pattern.
245 A null string means no extra condition.
246 3: is the action to execute if this pattern is matched.
247 If this assembler code template starts with a * then it is a fragment of
248 C code to run to decide on a template to use. Otherwise, it is the
250 4: C expression that must be true for split. This may start with "&&"
251 in which case the split condition is the logical and of the insn
252 condition and what follows the "&&" of this operand.
253 5: vector of insn patterns to place into a SEQUENCE
254 6: optionally, some C code to execute before generating the
255 insns. This might, for example, create some RTX's and store them in
256 elements of `recog_data.operand' for use by the vector of
258 (`operands' is an alias here for `recog_data.operand').
259 7: optionally, a vector of attributes for this insn. */
260 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
262 /* Definition of an RTL peephole operation.
263 Follows the same arguments as define_split. */
264 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
266 /* Define how to generate multiple insns for a standard insn name.
267 1st operand: the insn name.
268 2nd operand: vector of insn-patterns.
269 Use match_operand to substitute an element of `recog_data.operand'.
270 3rd operand: C expression that must be true for this to be available.
271 This may not test any operands.
272 4th operand: Extra C code to execute before generating the insns.
273 This might, for example, create some RTX's and store them in
274 elements of `recog_data.operand' for use by the vector of
276 (`operands' is an alias here for `recog_data.operand'). */
277 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
279 /* Define a requirement for delay slots.
280 1st operand: Condition involving insn attributes that, if true,
281 indicates that the insn requires the number of delay slots
283 2nd operand: Vector whose length is the three times the number of delay
285 Each entry gives three conditions, each involving attributes.
286 The first must be true for an insn to occupy that delay slot
287 location. The second is true for all insns that can be
288 annulled if the branch is true and the third is true for all
289 insns that can be annulled if the branch is false.
291 Multiple DEFINE_DELAYs may be present. They indicate differing
292 requirements for delay slots. */
293 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
295 /* Define attribute computation for `asm' instructions. */
296 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
298 /* Definition of a conditional execution meta operation. Automatically
299 generates new instances of DEFINE_INSN, selected by having attribute
300 "predicable" true. The new pattern will contain a COND_EXEC and the
301 predicate at top-level.
304 0: The predicate pattern. The top-level form should match a
305 relational operator. Operands should have only one alternative.
306 1: A C expression giving an additional condition for recognizing
307 the generated pattern.
308 2: A template or C code to produce assembler output. */
309 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
311 /* Definition of an operand predicate. The difference between
312 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
313 not warn about a match_operand with no mode if it has a predicate
314 defined with DEFINE_SPECIAL_PREDICATE.
317 0: The name of the predicate.
318 1: A boolean expression which computes whether or not the predicate
319 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
320 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
321 can calculate the set of RTX codes that can possibly match.
322 2: A C function body which must return true for the predicate to match.
323 Optional. Use this when the test is too complicated to fit into a
324 match_test expression. */
325 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
326 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
328 /* SEQUENCE appears in the result of a `gen_...' function
329 for a DEFINE_EXPAND that wants to make several insns.
330 Its elements are the bodies of the insns that should be made.
331 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
332 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
334 /* Refers to the address of its argument. This is only used in alias.c. */
335 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
337 /* ----------------------------------------------------------------------
338 Constructions for CPU pipeline description described by NDFAs.
339 These do not appear in actual rtl code in the compiler.
340 ---------------------------------------------------------------------- */
342 /* (define_cpu_unit string [string]) describes cpu functional
343 units (separated by comma).
345 1st operand: Names of cpu functional units.
346 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
348 All define_reservations, define_cpu_units, and
349 define_query_cpu_units should have unique names which may not be
351 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
353 /* (define_query_cpu_unit string [string]) describes cpu functional
354 units analogously to define_cpu_unit. The reservation of such
355 units can be queried for automaton state. */
356 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
358 /* (exclusion_set string string) means that each CPU functional unit
359 in the first string can not be reserved simultaneously with any
360 unit whose name is in the second string and vise versa. CPU units
361 in the string are separated by commas. For example, it is useful
362 for description CPU with fully pipelined floating point functional
363 unit which can execute simultaneously only single floating point
364 insns or only double floating point insns. All CPU functional
365 units in a set should belong to the same automaton. */
366 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
368 /* (presence_set string string) means that each CPU functional unit in
369 the first string can not be reserved unless at least one of pattern
370 of units whose names are in the second string is reserved. This is
371 an asymmetric relation. CPU units or unit patterns in the strings
372 are separated by commas. Pattern is one unit name or unit names
373 separated by white-spaces.
375 For example, it is useful for description that slot1 is reserved
376 after slot0 reservation for a VLIW processor. We could describe it
377 by the following construction
379 (presence_set "slot1" "slot0")
381 Or slot1 is reserved only after slot0 and unit b0 reservation. In
382 this case we could write
384 (presence_set "slot1" "slot0 b0")
386 All CPU functional units in a set should belong to the same
388 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
390 /* (final_presence_set string string) is analogous to `presence_set'.
391 The difference between them is when checking is done. When an
392 instruction is issued in given automaton state reflecting all
393 current and planned unit reservations, the automaton state is
394 changed. The first state is a source state, the second one is a
395 result state. Checking for `presence_set' is done on the source
396 state reservation, checking for `final_presence_set' is done on the
397 result reservation. This construction is useful to describe a
398 reservation which is actually two subsequent reservations. For
401 (presence_set "slot1" "slot0")
403 the following insn will be never issued (because slot1 requires
404 slot0 which is absent in the source state).
406 (define_reservation "insn_and_nop" "slot0 + slot1")
408 but it can be issued if we use analogous `final_presence_set'. */
409 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
411 /* (absence_set string string) means that each CPU functional unit in
412 the first string can be reserved only if each pattern of units
413 whose names are in the second string is not reserved. This is an
414 asymmetric relation (actually exclusion set is analogous to this
415 one but it is symmetric). CPU units or unit patterns in the string
416 are separated by commas. Pattern is one unit name or unit names
417 separated by white-spaces.
419 For example, it is useful for description that slot0 can not be
420 reserved after slot1 or slot2 reservation for a VLIW processor. We
421 could describe it by the following construction
423 (absence_set "slot2" "slot0, slot1")
425 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
426 slot1 and unit b1 are reserved . In this case we could write
428 (absence_set "slot2" "slot0 b0, slot1 b1")
430 All CPU functional units in a set should to belong the same
432 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
434 /* (final_absence_set string string) is analogous to `absence_set' but
435 checking is done on the result (state) reservation. See comments
436 for `final_presence_set'. */
437 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
439 /* (define_bypass number out_insn_names in_insn_names) names bypass
440 with given latency (the first number) from insns given by the first
441 string (see define_insn_reservation) into insns given by the second
442 string. Insn names in the strings are separated by commas. The
443 third operand is optional name of function which is additional
444 guard for the bypass. The function will get the two insns as
445 parameters. If the function returns zero the bypass will be
446 ignored for this case. Additional guard is necessary to recognize
447 complicated bypasses, e.g. when consumer is load address. */
448 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
450 /* (define_automaton string) describes names of automata generated and
451 used for pipeline hazards recognition. The names are separated by
452 comma. Actually it is possibly to generate the single automaton
453 but unfortunately it can be very large. If we use more one
454 automata, the summary size of the automata usually is less than the
455 single one. The automaton name is used in define_cpu_unit and
456 define_query_cpu_unit. All automata should have unique names. */
457 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
459 /* (automata_option string) describes option for generation of
460 automata. Currently there are the following options:
462 o "no-minimization" which makes no minimization of automata. This
463 is only worth to do when we are debugging the description and
464 need to look more accurately at reservations of states.
466 o "time" which means printing additional time statistics about
467 generation of automata.
469 o "v" which means generation of file describing the result
470 automata. The file has suffix `.dfa' and can be used for the
471 description verification and debugging.
473 o "w" which means generation of warning instead of error for
476 o "ndfa" which makes nondeterministic finite state automata.
478 o "progress" which means output of a progress bar showing how many
479 states were generated so far for automaton being processed. */
480 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
482 /* (define_reservation string string) names reservation (the first
483 string) of cpu functional units (the 2nd string). Sometimes unit
484 reservations for different insns contain common parts. In such
485 case, you can describe common part and use its name (the 1st
486 parameter) in regular expression in define_insn_reservation. All
487 define_reservations, define_cpu_units, and define_query_cpu_units
488 should have unique names which may not be "nothing". */
489 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
491 /* (define_insn_reservation name default_latency condition regexpr)
492 describes reservation of cpu functional units (the 3nd operand) for
493 instruction which is selected by the condition (the 2nd parameter).
494 The first parameter is used for output of debugging information.
495 The reservations are described by a regular expression according
496 the following syntax:
498 regexp = regexp "," oneof
501 oneof = oneof "|" allof
504 allof = allof "+" repeat
507 repeat = element "*" number
510 element = cpu_function_unit_name
516 1. "," is used for describing start of the next cycle in
519 2. "|" is used for describing the reservation described by the
520 first regular expression *or* the reservation described by the
521 second regular expression *or* etc.
523 3. "+" is used for describing the reservation described by the
524 first regular expression *and* the reservation described by the
525 second regular expression *and* etc.
527 4. "*" is used for convenience and simply means sequence in
528 which the regular expression are repeated NUMBER times with
529 cycle advancing (see ",").
531 5. cpu functional unit name which means its reservation.
533 6. reservation name -- see define_reservation.
535 7. string "nothing" means no units reservation. */
537 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
539 /* ----------------------------------------------------------------------
540 Expressions used for insn attributes. These also do not appear in
541 actual rtl code in the compiler.
542 ---------------------------------------------------------------------- */
544 /* Definition of an insn attribute.
545 1st operand: name of the attribute
546 2nd operand: comma-separated list of possible attribute values
547 3rd operand: expression for the default value of the attribute. */
548 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
550 /* Marker for the name of an attribute. */
551 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
553 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
554 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
557 (set_attr "name" "value") is equivalent to
558 (set (attr "name") (const_string "value")) */
559 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
561 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
562 specify that attribute values are to be assigned according to the
565 The following three expressions are equivalent:
567 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
568 (eq_attrq "alternative" "2") (const_string "a2")]
569 (const_string "a3")))
570 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
571 (const_string "a3")])
572 (set_attr "att" "a1,a2,a3")
574 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
576 /* A conditional expression true if the value of the specified attribute of
577 the current insn equals the specified value. The first operand is the
578 attribute name and the second is the comparison value. */
579 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
581 /* A special case of the above representing a set of alternatives. The first
582 operand is bitmap of the set, the second one is the default value. */
583 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
585 /* A conditional expression which is true if the specified flag is
586 true for the insn being scheduled in reorg.
588 genattr.c defines the following flags which can be tested by
589 (attr_flag "foo") expressions in eligible_for_delay.
591 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
593 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
595 /* ----------------------------------------------------------------------
596 Expression types used for things in the instruction chain.
598 All formats must start with "iuu" to handle the chain.
599 Each insn expression holds an rtl instruction and its semantics
600 during back-end processing.
601 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
603 ---------------------------------------------------------------------- */
605 /* An instruction that cannot jump. */
606 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
608 /* An instruction that can possibly jump.
609 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
610 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
612 /* An instruction that can possibly call a subroutine
613 but which will not change which instruction comes next
614 in the current function.
615 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
616 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
617 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
619 /* A marker that indicates that control will not flow through. */
620 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
622 /* Holds a label that is followed by instructions.
624 4: is used in jump.c for the use-count of the label.
625 5: is used in flow.c to point to the chain of label_ref's to this label.
626 6: is a number that is unique in the entire compilation.
627 7: is the user-given name of the label, if any. */
628 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
630 #ifdef USE_MAPPED_LOCATION
631 /* Say where in the code a source line starts, for symbol table's sake.
633 4: unused if line number > 0, note-specific data otherwise.
634 5: line number if > 0, enum note_insn otherwise.
635 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
637 /* Say where in the code a source line starts, for symbol table's sake.
639 4: filename, if line number > 0, note-specific data otherwise.
640 5: line number if > 0, enum note_insn otherwise.
641 6: unique number if line number == note_insn_deleted_label. */
643 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
645 /* ----------------------------------------------------------------------
646 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
647 ---------------------------------------------------------------------- */
649 /* Conditionally execute code.
650 Operand 0 is the condition that if true, the code is executed.
651 Operand 1 is the code to be executed (typically a SET).
653 Semantics are that there are no side effects if the condition
654 is false. This pattern is created automatically by the if_convert
655 pass run after reload or by target-specific splitters. */
656 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
658 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
659 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
661 /* A string that is passed through to the assembler as input.
662 One can obviously pass comments through by using the
663 assembler comment syntax.
664 These occur in an insn all by themselves as the PATTERN.
665 They also appear inside an ASM_OPERANDS
666 as a convenient way to hold a string. */
667 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
669 #ifdef USE_MAPPED_LOCATION
670 /* An assembler instruction with operands.
671 1st operand is the instruction template.
672 2nd operand is the constraint for the output.
673 3rd operand is the number of the output this expression refers to.
674 When an insn stores more than one value, a separate ASM_OPERANDS
675 is made for each output; this integer distinguishes them.
676 4th is a vector of values of input operands.
677 5th is a vector of modes and constraints for the input operands.
678 Each element is an ASM_INPUT containing a constraint string
679 and whose mode indicates the mode of the input operand.
680 6th is the source line number. */
681 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
683 /* An assembler instruction with operands.
684 1st operand is the instruction template.
685 2nd operand is the constraint for the output.
686 3rd operand is the number of the output this expression refers to.
687 When an insn stores more than one value, a separate ASM_OPERANDS
688 is made for each output; this integer distinguishes them.
689 4th is a vector of values of input operands.
690 5th is a vector of modes and constraints for the input operands.
691 Each element is an ASM_INPUT containing a constraint string
692 and whose mode indicates the mode of the input operand.
693 6th is the name of the containing source file.
694 7th is the source line number. */
695 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
698 /* A machine-specific operation.
699 1st operand is a vector of operands being used by the operation so that
700 any needed reloads can be done.
701 2nd operand is a unique value saying which of a number of machine-specific
702 operations is to be performed.
703 (Note that the vector must be the first operand because of the way that
704 genrecog.c record positions within an insn.)
705 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
706 or inside an expression. */
707 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
709 /* Similar, but a volatile operation and one which may trap. */
710 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
712 /* Vector of addresses, stored as full words. */
713 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
714 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
716 /* Vector of address differences X0 - BASE, X1 - BASE, ...
717 First operand is BASE; the vector contains the X's.
718 The machine mode of this rtx says how much space to leave
719 for each difference and is adjusted by branch shortening if
720 CASE_VECTOR_SHORTEN_MODE is defined.
721 The third and fourth operands store the target labels with the
722 minimum and maximum addresses respectively.
723 The fifth operand stores flags for use by branch shortening.
724 Set at the start of shorten_branches:
725 min_align: the minimum alignment for any of the target labels.
726 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
727 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
728 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
729 min_after_base: true iff minimum address target label is after BASE.
730 max_after_base: true iff maximum address target label is after BASE.
731 Set by the actual branch shortening process:
732 offset_unsigned: true iff offsets have to be treated as unsigned.
733 scale: scaling that is necessary to make offsets fit into the mode.
735 The third, fourth and fifth operands are only valid when
736 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
739 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
741 /* Memory prefetch, with attributes supported on some targets.
742 Operand 1 is the address of the memory to fetch.
743 Operand 2 is 1 for a write access, 0 otherwise.
744 Operand 3 is the level of temporal locality; 0 means there is no
745 temporal locality and 1, 2, and 3 are for increasing levels of temporal
748 The attributes specified by operands 2 and 3 are ignored for targets
749 whose prefetch instructions do not support them. */
750 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
752 /* ----------------------------------------------------------------------
753 At the top level of an instruction (perhaps under PARALLEL).
754 ---------------------------------------------------------------------- */
757 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
758 Operand 2 is the value stored there.
759 ALL assignment must use SET.
760 Instructions that do multiple assignments must use multiple SET,
762 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
764 /* Indicate something is used in a way that we don't want to explain.
765 For example, subroutine calls will use the register
766 in which the static chain is passed. */
767 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
769 /* Indicate something is clobbered in a way that we don't want to explain.
770 For example, subroutine calls will clobber some physical registers
771 (the ones that are by convention not saved). */
772 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
774 /* Call a subroutine.
775 Operand 1 is the address to call.
776 Operand 2 is the number of arguments. */
778 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
780 /* Return from a subroutine. */
782 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
785 Operand 1 is the condition.
786 Operand 2 is the trap code.
787 For an unconditional trap, make the condition (const_int 1). */
788 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
790 /* Placeholder for _Unwind_Resume before we know if a function call
791 or a branch is needed. Operand 1 is the exception region from
792 which control is flowing. */
793 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
795 /* ----------------------------------------------------------------------
796 Primitive values for use in expressions.
797 ---------------------------------------------------------------------- */
799 /* numeric integer constant */
800 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
802 /* numeric floating point constant.
803 Operands hold the value. They are all 'w' and there may be from 2 to 6;
805 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
807 /* Describes a vector constant. */
808 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA)
810 /* String constant. Used only for attributes right now. */
811 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
813 /* This is used to encapsulate an expression whose value is constant
814 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
815 recognized as a constant operand rather than by arithmetic instructions. */
817 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
819 /* program counter. Ordinary jumps are represented
820 by a SET whose first operand is (PC). */
821 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
823 /* Used in the cselib routines to describe a value. */
824 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
826 /* A register. The "operand" is the register number, accessed with
827 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
828 than a hardware register is being referred to. The second operand
829 holds the original register number - this will be different for a
830 pseudo register that got turned into a hard register.
831 This rtx needs to have as many (or more) fields as a MEM, since we
832 can change REG rtx's into MEMs during reload. */
833 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
835 /* A scratch register. This represents a register used only within a
836 single insn. It will be turned into a REG during register allocation
837 or reload unless the constraint indicates that the register won't be
838 needed, in which case it can remain a SCRATCH. This code is
839 marked as having one operand so it can be turned into a REG. */
840 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
842 /* One word of a multi-word value.
843 The first operand is the complete value; the second says which word.
844 The WORDS_BIG_ENDIAN flag controls whether word number 0
845 (as numbered in a SUBREG) is the most or least significant word.
847 This is also used to refer to a value in a different machine mode.
848 For example, it can be used to refer to a SImode value as if it were
849 Qimode, or vice versa. Then the word number is always 0. */
850 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
852 /* This one-argument rtx is used for move instructions
853 that are guaranteed to alter only the low part of a destination.
854 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
855 has an unspecified effect on the high part of REG,
856 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
857 is guaranteed to alter only the bits of REG that are in HImode.
859 The actual instruction used is probably the same in both cases,
860 but the register constraints may be tighter when STRICT_LOW_PART
863 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
865 /* (CONCAT a b) represents the virtual concatenation of a and b
866 to make a value that has as many bits as a and b put together.
867 This is used for complex values. Normally it appears only
868 in DECL_RTLs and during RTL generation, but not in the insn chain. */
869 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
871 /* A memory location; operand is the address. The second operand is the
872 alias set to which this MEM belongs. We use `0' instead of `w' for this
873 field so that the field need not be specified in machine descriptions. */
874 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
876 /* Reference to an assembler label in the code for this function.
877 The operand is a CODE_LABEL found in the insn chain.
878 The unprinted fields 1 and 2 are used in flow.c for the
879 LABEL_NEXTREF and CONTAINING_INSN. */
880 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", RTX_CONST_OBJ)
882 /* Reference to a named label:
883 Operand 0: label name
884 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
885 Operand 2: tree from which this symbol is derived, or null.
886 This is either a DECL node, or some kind of constant. */
887 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
889 /* The condition code register is represented, in our imagination,
890 as a register holding a value that can be compared to zero.
891 In fact, the machine has already compared them and recorded the
892 results; but instructions that look at the condition code
893 pretend to be looking at the entire value and comparing it. */
894 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
896 /* ----------------------------------------------------------------------
897 Expressions for operators in an rtl pattern
898 ---------------------------------------------------------------------- */
900 /* if_then_else. This is used in representing ordinary
901 conditional jump instructions.
906 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
908 /* General conditional. The first operand is a vector composed of pairs of
909 expressions. The first element of each pair is evaluated, in turn.
910 The value of the conditional is the second expression of the first pair
911 whose first expression evaluates nonzero. If none of the expressions is
912 true, the second operand will be used as the value of the conditional.
914 This should be replaced with use of IF_THEN_ELSE. */
915 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
917 /* Comparison, produces a condition code result. */
918 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
921 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
923 /* Operand 0 minus operand 1. */
924 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
926 /* Minus operand 0. */
927 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
929 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
931 /* Operand 0 divided by operand 1. */
932 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
933 /* Remainder of operand 0 divided by operand 1. */
934 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
936 /* Unsigned divide and remainder. */
937 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
938 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
940 /* Bitwise operations. */
941 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
943 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
945 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
947 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
950 0: value to be shifted.
951 1: number of bits. */
952 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
953 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
954 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
955 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
956 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
958 /* Minimum and maximum values of two operands. We need both signed and
959 unsigned forms. (We cannot use MIN for SMIN because it conflicts
960 with a macro of the same name.) */
962 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
963 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
964 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
965 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
967 /* These unary operations are used to represent incrementation
968 and decrementation as they occur in memory addresses.
969 The amount of increment or decrement are not represented
970 because they can be understood from the machine-mode of the
971 containing MEM. These operations exist in only two cases:
972 1. pushes onto the stack.
973 2. created automatically by the life_analysis pass in flow.c. */
974 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
975 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
976 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
977 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
979 /* These binary operations are used to represent generic address
980 side-effects in memory addresses, except for simple incrementation
981 or decrementation which use the above operations. They are
982 created automatically by the life_analysis pass in flow.c.
983 The first operand is a REG which is used as the address.
984 The second operand is an expression that is assigned to the
985 register, either before (PRE_MODIFY) or after (POST_MODIFY)
986 evaluating the address.
987 Currently, the compiler can only handle second operands of the
988 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
989 the first operand of the PLUS has to be the same register as
990 the first operand of the *_MODIFY. */
991 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
992 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
994 /* Comparison operations. The ordered comparisons exist in two
995 flavors, signed and unsigned. */
996 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
997 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
998 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
999 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
1000 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
1001 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
1002 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
1003 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
1004 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
1005 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
1007 /* Additional floating point unordered comparison flavors. */
1008 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
1009 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
1011 /* These are equivalent to unordered or ... */
1012 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
1013 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
1014 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
1015 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
1016 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
1018 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
1019 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
1021 /* Represents the result of sign-extending the sole operand.
1022 The machine modes of the operand and of the SIGN_EXTEND expression
1023 determine how much sign-extension is going on. */
1024 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
1026 /* Similar for zero-extension (such as unsigned short to int). */
1027 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
1029 /* Similar but here the operand has a wider mode. */
1030 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
1032 /* Similar for extending floating-point values (such as SFmode to DFmode). */
1033 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
1034 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
1036 /* Conversion of fixed point operand to floating point value. */
1037 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
1039 /* With fixed-point machine mode:
1040 Conversion of floating point operand to fixed point value.
1041 Value is defined only when the operand's value is an integer.
1042 With floating-point machine mode (and operand with same mode):
1043 Operand is rounded toward zero to produce an integer value
1044 represented in floating point. */
1045 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
1047 /* Conversion of unsigned fixed point operand to floating point value. */
1048 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
1050 /* With fixed-point machine mode:
1051 Conversion of floating point operand to *unsigned* fixed point value.
1052 Value is defined only when the operand's value is an integer. */
1053 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
1055 /* Absolute value */
1056 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
1059 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
1061 /* Find first bit that is set.
1062 Value is 1 + number of trailing zeros in the arg.,
1063 or 0 if arg is 0. */
1064 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
1066 /* Count leading zeros. */
1067 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
1069 /* Count trailing zeros. */
1070 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
1072 /* Population count (number of 1 bits). */
1073 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
1075 /* Population parity (number of 1 bits modulo 2). */
1076 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
1078 /* Reference to a signed bit-field of specified size and position.
1079 Operand 0 is the memory unit (usually SImode or QImode) which
1080 contains the field's first bit. Operand 1 is the width, in bits.
1081 Operand 2 is the number of bits in the memory unit before the
1082 first bit of this field.
1083 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
1084 operand 2 counts from the msb of the memory unit.
1085 Otherwise, the first bit is the lsb and operand 2 counts from
1086 the lsb of the memory unit. */
1087 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
1089 /* Similar for unsigned bit-field. */
1090 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
1092 /* For RISC machines. These save memory when splitting insns. */
1094 /* HIGH are the high-order bits of a constant expression. */
1095 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
1097 /* LO_SUM is the sum of a register and the low-order bits
1098 of a constant expression. */
1099 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
1101 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
1102 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
1103 the registers that can be substituted within this range. Operand 3 is the
1104 number of calls in the range. Operand 4 is the number of insns in the
1105 range. Operand 5 is the unique range number for this range. Operand 6 is
1106 the basic block # of the start of the live range. Operand 7 is the basic
1107 block # of the end of the live range. Operand 8 is the loop depth. Operand
1108 9 is a bitmap of the registers live at the start of the range. Operand 10
1109 is a bitmap of the registers live at the end of the range. Operand 11 is
1110 marker number for the start of the range. Operand 12 is the marker number
1111 for the end of the range. */
1112 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", RTX_EXTRA)
1114 /* Registers that can be substituted within the range. Operand 0 is the
1115 original pseudo register number. Operand 1 will be filled in with the
1116 pseudo register the value is copied for the duration of the range. Operand
1117 2 is the number of references within the range to the register. Operand 3
1118 is the number of sets or clobbers of the register in the range. Operand 4
1119 is the number of deaths the register has. Operand 5 is the copy flags that
1120 give the status of whether a copy is needed from the original register to
1121 the new register at the beginning of the range, or whether a copy from the
1122 new register back to the original at the end of the range. Operand 6 is the
1123 live length. Operand 7 is the number of calls that this register is live
1124 across. Operand 8 is the symbol node of the variable if the register is a
1125 user variable. Operand 9 is the block node that the variable is declared
1126 in if the register is a user variable. */
1127 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", RTX_EXTRA)
1129 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
1130 the different ranges a variable is in where it is copied to a different
1131 pseudo register. Operand 1 is the block that the variable is declared in.
1132 Operand 2 is the number of distinct ranges. */
1133 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", RTX_EXTRA)
1135 /* Information about the registers that are live at the current point. Operand
1136 0 is the live bitmap. Operand 1 is the original block number. */
1137 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", RTX_EXTRA)
1139 /* Describes a merge operation between two vector values.
1140 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
1141 that specifies where the parts of the result are taken from. Set bits
1142 indicate operand 0, clear bits indicate operand 1. The parts are defined
1143 by the mode of the vectors. */
1144 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
1146 /* Describes an operation that selects parts of a vector.
1147 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
1148 a CONST_INT for each of the subparts of the result vector, giving the
1149 number of the source subpart that should be stored into it. */
1150 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
1152 /* Describes a vector concat operation. Operands 0 and 1 are the source
1153 vectors, the result is a vector that is as long as operands 0 and 1
1154 combined and is the concatenation of the two source vectors. */
1155 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
1157 /* Describes an operation that converts a small vector into a larger one by
1158 duplicating the input values. The output vector mode must have the same
1159 submodes as the input vector mode, and the number of output parts must be
1160 an integer multiple of the number of input parts. */
1161 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
1163 /* Addition with signed saturation */
1164 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
1166 /* Addition with unsigned saturation */
1167 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
1169 /* Operand 0 minus operand 1, with signed saturation. */
1170 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
1172 /* Operand 0 minus operand 1, with unsigned saturation. */
1173 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
1175 /* Signed saturating truncate. */
1176 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
1178 /* Unsigned saturating truncate. */
1179 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
1181 /* Information about the variable and its location. */
1182 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
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