1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* ---------------------------------------------------------------------
85 Expressions used in constructing lists.
86 --------------------------------------------------------------------- */
88 /* a linked list of expressions */
89 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
91 /* a linked list of instructions.
92 The insns are represented in print by their uids. */
93 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
95 /* SEQUENCE appears in the result of a `gen_...' function
96 for a DEFINE_EXPAND that wants to make several insns.
97 Its elements are the bodies of the insns that should be made.
98 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
99 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
101 /* Refers to the address of its argument. This is only used in alias.c. */
102 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
104 /* ----------------------------------------------------------------------
105 Expression types used for things in the instruction chain.
107 All formats must start with "iuu" to handle the chain.
108 Each insn expression holds an rtl instruction and its semantics
109 during back-end processing.
110 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
112 ---------------------------------------------------------------------- */
114 /* An instruction that cannot jump. */
115 DEF_RTL_EXPR(INSN, "insn", "iuuBieie", RTX_INSN)
117 /* An instruction that can possibly jump.
118 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
119 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieie0", RTX_INSN)
121 /* An instruction that can possibly call a subroutine
122 but which will not change which instruction comes next
123 in the current function.
124 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
125 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
126 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieiee", RTX_INSN)
128 /* A marker that indicates that control will not flow through. */
129 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
131 /* Holds a label that is followed by instructions.
133 4: is used in jump.c for the use-count of the label.
134 5: is used in the sh backend.
135 6: is a number that is unique in the entire compilation.
136 7: is the user-given name of the label, if any. */
137 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
139 /* Say where in the code a source line starts, for symbol table's sake.
141 4: note-specific data
143 6: unique number if insn_note == note_insn_deleted_label. */
144 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
146 /* ----------------------------------------------------------------------
147 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
148 ---------------------------------------------------------------------- */
150 /* Conditionally execute code.
151 Operand 0 is the condition that if true, the code is executed.
152 Operand 1 is the code to be executed (typically a SET).
154 Semantics are that there are no side effects if the condition
155 is false. This pattern is created automatically by the if_convert
156 pass run after reload or by target-specific splitters. */
157 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
159 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
160 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
162 #ifdef USE_MAPPED_LOCATION
163 /* A string that is passed through to the assembler as input.
164 One can obviously pass comments through by using the
165 assembler comment syntax.
166 These occur in an insn all by themselves as the PATTERN.
167 They also appear inside an ASM_OPERANDS
168 as a convenient way to hold a string. */
169 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
171 /* An assembler instruction with operands.
172 1st operand is the instruction template.
173 2nd operand is the constraint for the output.
174 3rd operand is the number of the output this expression refers to.
175 When an insn stores more than one value, a separate ASM_OPERANDS
176 is made for each output; this integer distinguishes them.
177 4th is a vector of values of input operands.
178 5th is a vector of modes and constraints for the input operands.
179 Each element is an ASM_INPUT containing a constraint string
180 and whose mode indicates the mode of the input operand.
181 6th is the source line number. */
182 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
184 /* A string that is passed through to the assembler as input.
185 One can obviously pass comments through by using the
186 assembler comment syntax.
187 These occur in an insn all by themselves as the PATTERN.
188 They also appear inside an ASM_OPERANDS
189 as a convenient way to hold a string. */
190 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "ssi", RTX_EXTRA)
192 /* An assembler instruction with operands.
193 1st operand is the instruction template.
194 2nd operand is the constraint for the output.
195 3rd operand is the number of the output this expression refers to.
196 When an insn stores more than one value, a separate ASM_OPERANDS
197 is made for each output; this integer distinguishes them.
198 4th is a vector of values of input operands.
199 5th is a vector of modes and constraints for the input operands.
200 Each element is an ASM_INPUT containing a constraint string
201 and whose mode indicates the mode of the input operand.
202 6th is the name of the containing source file.
203 7th is the source line number. */
204 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
207 /* A machine-specific operation.
208 1st operand is a vector of operands being used by the operation so that
209 any needed reloads can be done.
210 2nd operand is a unique value saying which of a number of machine-specific
211 operations is to be performed.
212 (Note that the vector must be the first operand because of the way that
213 genrecog.c record positions within an insn.)
215 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
216 or inside an expression.
217 UNSPEC by itself or as a component of a PARALLEL
218 is currently considered not deletable.
220 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
221 of a PARALLEL with USE.
223 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
225 /* Similar, but a volatile operation and one which may trap. */
226 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
228 /* Vector of addresses, stored as full words. */
229 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
230 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
232 /* Vector of address differences X0 - BASE, X1 - BASE, ...
233 First operand is BASE; the vector contains the X's.
234 The machine mode of this rtx says how much space to leave
235 for each difference and is adjusted by branch shortening if
236 CASE_VECTOR_SHORTEN_MODE is defined.
237 The third and fourth operands store the target labels with the
238 minimum and maximum addresses respectively.
239 The fifth operand stores flags for use by branch shortening.
240 Set at the start of shorten_branches:
241 min_align: the minimum alignment for any of the target labels.
242 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
243 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
244 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
245 min_after_base: true iff minimum address target label is after BASE.
246 max_after_base: true iff maximum address target label is after BASE.
247 Set by the actual branch shortening process:
248 offset_unsigned: true iff offsets have to be treated as unsigned.
249 scale: scaling that is necessary to make offsets fit into the mode.
251 The third, fourth and fifth operands are only valid when
252 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
255 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
257 /* Memory prefetch, with attributes supported on some targets.
258 Operand 1 is the address of the memory to fetch.
259 Operand 2 is 1 for a write access, 0 otherwise.
260 Operand 3 is the level of temporal locality; 0 means there is no
261 temporal locality and 1, 2, and 3 are for increasing levels of temporal
264 The attributes specified by operands 2 and 3 are ignored for targets
265 whose prefetch instructions do not support them. */
266 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
268 /* ----------------------------------------------------------------------
269 At the top level of an instruction (perhaps under PARALLEL).
270 ---------------------------------------------------------------------- */
273 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
274 Operand 2 is the value stored there.
275 ALL assignment must use SET.
276 Instructions that do multiple assignments must use multiple SET,
278 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
280 /* Indicate something is used in a way that we don't want to explain.
281 For example, subroutine calls will use the register
282 in which the static chain is passed.
284 USE can not appear as an operand of other rtx except for PARALLEL.
285 USE is not deletable, as it indicates that the operand
286 is used in some unknown way. */
287 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
289 /* Indicate something is clobbered in a way that we don't want to explain.
290 For example, subroutine calls will clobber some physical registers
291 (the ones that are by convention not saved).
293 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
294 CLOBBER of a hard register appearing by itself (not within PARALLEL)
295 is considered undeletable before reload. */
296 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
298 /* Call a subroutine.
299 Operand 1 is the address to call.
300 Operand 2 is the number of arguments. */
302 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
304 /* Return from a subroutine. */
306 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
309 Operand 1 is the condition.
310 Operand 2 is the trap code.
311 For an unconditional trap, make the condition (const_int 1). */
312 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
314 /* Placeholder for _Unwind_Resume before we know if a function call
315 or a branch is needed. Operand 1 is the exception region from
316 which control is flowing. */
317 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
319 /* ----------------------------------------------------------------------
320 Primitive values for use in expressions.
321 ---------------------------------------------------------------------- */
323 /* numeric integer constant */
324 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
326 /* numeric floating point constant.
327 Operands hold the value. They are all 'w' and there may be from 2 to 6;
329 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
331 /* Describes a vector constant. */
332 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
334 /* String constant. Used for attributes in machine descriptions and
335 for special cases in DWARF2 debug output. NOT used for source-
336 language string constants. */
337 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
339 /* This is used to encapsulate an expression whose value is constant
340 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
341 recognized as a constant operand rather than by arithmetic instructions. */
343 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
345 /* program counter. Ordinary jumps are represented
346 by a SET whose first operand is (PC). */
347 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
349 /* Used in the cselib routines to describe a value. Objects of this
350 kind are only allocated in cselib.c, in an alloc pool instead of
351 in GC memory. The only operand of a VALUE is a cselib_val_struct. */
352 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
354 /* A register. The "operand" is the register number, accessed with
355 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
356 than a hardware register is being referred to. The second operand
357 holds the original register number - this will be different for a
358 pseudo register that got turned into a hard register. The third
359 operand points to a reg_attrs structure.
360 This rtx needs to have as many (or more) fields as a MEM, since we
361 can change REG rtx's into MEMs during reload. */
362 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
364 /* A scratch register. This represents a register used only within a
365 single insn. It will be turned into a REG during register allocation
366 or reload unless the constraint indicates that the register won't be
367 needed, in which case it can remain a SCRATCH. This code is
368 marked as having one operand so it can be turned into a REG. */
369 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
371 /* One word of a multi-word value.
372 The first operand is the complete value; the second says which word.
373 The WORDS_BIG_ENDIAN flag controls whether word number 0
374 (as numbered in a SUBREG) is the most or least significant word.
376 This is also used to refer to a value in a different machine mode.
377 For example, it can be used to refer to a SImode value as if it were
378 Qimode, or vice versa. Then the word number is always 0. */
379 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
381 /* This one-argument rtx is used for move instructions
382 that are guaranteed to alter only the low part of a destination.
383 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
384 has an unspecified effect on the high part of REG,
385 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
386 is guaranteed to alter only the bits of REG that are in HImode.
388 The actual instruction used is probably the same in both cases,
389 but the register constraints may be tighter when STRICT_LOW_PART
392 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
394 /* (CONCAT a b) represents the virtual concatenation of a and b
395 to make a value that has as many bits as a and b put together.
396 This is used for complex values. Normally it appears only
397 in DECL_RTLs and during RTL generation, but not in the insn chain. */
398 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
400 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
401 all An to make a value. This is an extension of CONCAT to larger
402 number of components. Like CONCAT, it should not appear in the
403 insn chain. Every element of the CONCATN is the same size. */
404 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
406 /* A memory location; operand is the address. The second operand is the
407 alias set to which this MEM belongs. We use `0' instead of `w' for this
408 field so that the field need not be specified in machine descriptions. */
409 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
411 /* Reference to an assembler label in the code for this function.
412 The operand is a CODE_LABEL found in the insn chain. */
413 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
415 /* Reference to a named label:
416 Operand 0: label name
417 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
418 Operand 2: tree from which this symbol is derived, or null.
419 This is either a DECL node, or some kind of constant. */
420 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
422 /* The condition code register is represented, in our imagination,
423 as a register holding a value that can be compared to zero.
424 In fact, the machine has already compared them and recorded the
425 results; but instructions that look at the condition code
426 pretend to be looking at the entire value and comparing it. */
427 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
429 /* ----------------------------------------------------------------------
430 Expressions for operators in an rtl pattern
431 ---------------------------------------------------------------------- */
433 /* if_then_else. This is used in representing ordinary
434 conditional jump instructions.
439 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
441 /* Comparison, produces a condition code result. */
442 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
445 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
447 /* Operand 0 minus operand 1. */
448 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
450 /* Minus operand 0. */
451 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
453 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
455 /* Operand 0 divided by operand 1. */
456 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
457 /* Remainder of operand 0 divided by operand 1. */
458 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
460 /* Unsigned divide and remainder. */
461 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
462 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
464 /* Bitwise operations. */
465 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
466 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
467 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
468 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
471 0: value to be shifted.
472 1: number of bits. */
473 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
474 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
475 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
476 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
477 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
479 /* Minimum and maximum values of two operands. We need both signed and
480 unsigned forms. (We cannot use MIN for SMIN because it conflicts
481 with a macro of the same name.) The signed variants should be used
482 with floating point. Further, if both operands are zeros, or if either
483 operand is NaN, then it is unspecified which of the two operands is
484 returned as the result. */
486 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
487 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
488 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
489 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
491 /* These unary operations are used to represent incrementation
492 and decrementation as they occur in memory addresses.
493 The amount of increment or decrement are not represented
494 because they can be understood from the machine-mode of the
495 containing MEM. These operations exist in only two cases:
496 1. pushes onto the stack.
497 2. created automatically by the life_analysis pass in flow.c. */
498 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
499 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
500 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
501 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
503 /* These binary operations are used to represent generic address
504 side-effects in memory addresses, except for simple incrementation
505 or decrementation which use the above operations. They are
506 created automatically by the life_analysis pass in flow.c.
507 The first operand is a REG which is used as the address.
508 The second operand is an expression that is assigned to the
509 register, either before (PRE_MODIFY) or after (POST_MODIFY)
510 evaluating the address.
511 Currently, the compiler can only handle second operands of the
512 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
513 the first operand of the PLUS has to be the same register as
514 the first operand of the *_MODIFY. */
515 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
516 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
518 /* Comparison operations. The ordered comparisons exist in two
519 flavors, signed and unsigned. */
520 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
521 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
522 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
523 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
524 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
525 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
526 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
527 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
528 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
529 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
531 /* Additional floating point unordered comparison flavors. */
532 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
533 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
535 /* These are equivalent to unordered or ... */
536 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
537 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
538 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
539 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
540 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
542 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
543 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
545 /* Represents the result of sign-extending the sole operand.
546 The machine modes of the operand and of the SIGN_EXTEND expression
547 determine how much sign-extension is going on. */
548 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
550 /* Similar for zero-extension (such as unsigned short to int). */
551 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
553 /* Similar but here the operand has a wider mode. */
554 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
556 /* Similar for extending floating-point values (such as SFmode to DFmode). */
557 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
558 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
560 /* Conversion of fixed point operand to floating point value. */
561 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
563 /* With fixed-point machine mode:
564 Conversion of floating point operand to fixed point value.
565 Value is defined only when the operand's value is an integer.
566 With floating-point machine mode (and operand with same mode):
567 Operand is rounded toward zero to produce an integer value
568 represented in floating point. */
569 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
571 /* Conversion of unsigned fixed point operand to floating point value. */
572 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
574 /* With fixed-point machine mode:
575 Conversion of floating point operand to *unsigned* fixed point value.
576 Value is defined only when the operand's value is an integer. */
577 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
580 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
583 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
586 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
588 /* Find first bit that is set.
589 Value is 1 + number of trailing zeros in the arg.,
591 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
593 /* Count leading zeros. */
594 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
596 /* Count trailing zeros. */
597 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
599 /* Population count (number of 1 bits). */
600 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
602 /* Population parity (number of 1 bits modulo 2). */
603 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
605 /* Reference to a signed bit-field of specified size and position.
606 Operand 0 is the memory unit (usually SImode or QImode) which
607 contains the field's first bit. Operand 1 is the width, in bits.
608 Operand 2 is the number of bits in the memory unit before the
609 first bit of this field.
610 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
611 operand 2 counts from the msb of the memory unit.
612 Otherwise, the first bit is the lsb and operand 2 counts from
613 the lsb of the memory unit.
614 This kind of expression can not appear as an lvalue in RTL. */
615 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
617 /* Similar for unsigned bit-field.
618 But note! This kind of expression _can_ appear as an lvalue. */
619 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
621 /* For RISC machines. These save memory when splitting insns. */
623 /* HIGH are the high-order bits of a constant expression. */
624 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
626 /* LO_SUM is the sum of a register and the low-order bits
627 of a constant expression. */
628 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
630 /* Describes a merge operation between two vector values.
631 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
632 that specifies where the parts of the result are taken from. Set bits
633 indicate operand 0, clear bits indicate operand 1. The parts are defined
634 by the mode of the vectors. */
635 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
637 /* Describes an operation that selects parts of a vector.
638 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
639 a CONST_INT for each of the subparts of the result vector, giving the
640 number of the source subpart that should be stored into it. */
641 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
643 /* Describes a vector concat operation. Operands 0 and 1 are the source
644 vectors, the result is a vector that is as long as operands 0 and 1
645 combined and is the concatenation of the two source vectors. */
646 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
648 /* Describes an operation that converts a small vector into a larger one by
649 duplicating the input values. The output vector mode must have the same
650 submodes as the input vector mode, and the number of output parts must be
651 an integer multiple of the number of input parts. */
652 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
654 /* Addition with signed saturation */
655 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
657 /* Addition with unsigned saturation */
658 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
660 /* Operand 0 minus operand 1, with signed saturation. */
661 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
663 /* Negation with signed saturation. */
664 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
666 /* Absolute value with signed saturation. */
667 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
669 /* Shift left with signed saturation. */
670 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
672 /* Operand 0 minus operand 1, with unsigned saturation. */
673 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
675 /* Signed saturating truncate. */
676 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
678 /* Unsigned saturating truncate. */
679 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
681 /* Information about the variable and its location. */
682 /* Changed 'te' to 'tei'; the 'i' field is for recording
683 initialization status of variables. */
684 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
686 /* All expressions from this point forward appear only in machine
688 #ifdef GENERATOR_FILE
690 /* Include a secondary machine-description file at this point. */
691 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
693 /* Pattern-matching operators: */
695 /* Use the function named by the second arg (the string)
696 as a predicate; if matched, store the structure that was matched
697 in the operand table at index specified by the first arg (the integer).
698 If the second arg is the null string, the structure is just stored.
700 A third string argument indicates to the register allocator restrictions
701 on where the operand can be allocated.
703 If the target needs no restriction on any instruction this field should
706 The string is prepended by:
707 '=' to indicate the operand is only written to.
708 '+' to indicate the operand is both read and written to.
710 Each character in the string represents an allocable class for an operand.
711 'g' indicates the operand can be any valid class.
712 'i' indicates the operand can be immediate (in the instruction) data.
713 'r' indicates the operand can be in a register.
714 'm' indicates the operand can be in memory.
715 'o' a subset of the 'm' class. Those memory addressing modes that
716 can be offset at compile time (have a constant added to them).
718 Other characters indicate target dependent operand classes and
719 are described in each target's machine description.
721 For instructions with more than one operand, sets of classes can be
722 separated by a comma to indicate the appropriate multi-operand constraints.
723 There must be a 1 to 1 correspondence between these sets of classes in
724 all operands for an instruction.
726 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
728 /* Match a SCRATCH or a register. When used to generate rtl, a
729 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
730 the desired mode and the first argument is the operand number.
731 The second argument is the constraint. */
732 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
734 /* Apply a predicate, AND match recursively the operands of the rtx.
735 Operand 0 is the operand-number, as in match_operand.
736 Operand 1 is a predicate to apply (as a string, a function name).
737 Operand 2 is a vector of expressions, each of which must match
738 one subexpression of the rtx this construct is matching. */
739 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
741 /* Match a PARALLEL of arbitrary length. The predicate is applied
742 to the PARALLEL and the initial expressions in the PARALLEL are matched.
743 Operand 0 is the operand-number, as in match_operand.
744 Operand 1 is a predicate to apply to the PARALLEL.
745 Operand 2 is a vector of expressions, each of which must match the
746 corresponding element in the PARALLEL. */
747 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
749 /* Match only something equal to what is stored in the operand table
750 at the index specified by the argument. Use with MATCH_OPERAND. */
751 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
753 /* Match only something equal to what is stored in the operand table
754 at the index specified by the argument. Use with MATCH_OPERATOR. */
755 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
757 /* Match only something equal to what is stored in the operand table
758 at the index specified by the argument. Use with MATCH_PARALLEL. */
759 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
761 /* Appears only in define_predicate/define_special_predicate
762 expressions. Evaluates true only if the operand has an RTX code
763 from the set given by the argument (a comma-separated list). If the
764 second argument is present and nonempty, it is a sequence of digits
765 and/or letters which indicates the subexpression to test, using the
766 same syntax as genextract/genrecog's location strings: 0-9 for
767 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
768 the result of the one before it. */
769 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
771 /* Appears only in define_predicate/define_special_predicate
772 expressions. The argument is a C expression to be injected at this
773 point in the predicate formula. */
774 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
776 /* Insn (and related) definitions. */
778 /* Definition of the pattern for one kind of instruction.
780 0: names this instruction.
781 If the name is the null string, the instruction is in the
782 machine description just to be recognized, and will never be emitted by
783 the tree to rtl expander.
785 2: is a string which is a C expression
786 giving an additional condition for recognizing this pattern.
787 A null string means no extra condition.
788 3: is the action to execute if this pattern is matched.
789 If this assembler code template starts with a * then it is a fragment of
790 C code to run to decide on a template to use. Otherwise, it is the
792 4: optionally, a vector of attributes for this insn.
794 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
796 /* Definition of a peephole optimization.
797 1st operand: vector of insn patterns to match
798 2nd operand: C expression that must be true
799 3rd operand: template or C code to produce assembler output.
800 4: optionally, a vector of attributes for this insn.
802 This form is deprecated; use define_peephole2 instead. */
803 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
805 /* Definition of a split operation.
806 1st operand: insn pattern to match
807 2nd operand: C expression that must be true
808 3rd operand: vector of insn patterns to place into a SEQUENCE
809 4th operand: optionally, some C code to execute before generating the
810 insns. This might, for example, create some RTX's and store them in
811 elements of `recog_data.operand' for use by the vector of
813 (`operands' is an alias here for `recog_data.operand'). */
814 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
816 /* Definition of an insn and associated split.
817 This is the concatenation, with a few modifications, of a define_insn
818 and a define_split which share the same pattern.
820 0: names this instruction.
821 If the name is the null string, the instruction is in the
822 machine description just to be recognized, and will never be emitted by
823 the tree to rtl expander.
825 2: is a string which is a C expression
826 giving an additional condition for recognizing this pattern.
827 A null string means no extra condition.
828 3: is the action to execute if this pattern is matched.
829 If this assembler code template starts with a * then it is a fragment of
830 C code to run to decide on a template to use. Otherwise, it is the
832 4: C expression that must be true for split. This may start with "&&"
833 in which case the split condition is the logical and of the insn
834 condition and what follows the "&&" of this operand.
835 5: vector of insn patterns to place into a SEQUENCE
836 6: optionally, some C code to execute before generating the
837 insns. This might, for example, create some RTX's and store them in
838 elements of `recog_data.operand' for use by the vector of
840 (`operands' is an alias here for `recog_data.operand').
841 7: optionally, a vector of attributes for this insn. */
842 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
844 /* Definition of an RTL peephole operation.
845 Follows the same arguments as define_split. */
846 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
848 /* Define how to generate multiple insns for a standard insn name.
849 1st operand: the insn name.
850 2nd operand: vector of insn-patterns.
851 Use match_operand to substitute an element of `recog_data.operand'.
852 3rd operand: C expression that must be true for this to be available.
853 This may not test any operands.
854 4th operand: Extra C code to execute before generating the insns.
855 This might, for example, create some RTX's and store them in
856 elements of `recog_data.operand' for use by the vector of
858 (`operands' is an alias here for `recog_data.operand'). */
859 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
861 /* Define a requirement for delay slots.
862 1st operand: Condition involving insn attributes that, if true,
863 indicates that the insn requires the number of delay slots
865 2nd operand: Vector whose length is the three times the number of delay
867 Each entry gives three conditions, each involving attributes.
868 The first must be true for an insn to occupy that delay slot
869 location. The second is true for all insns that can be
870 annulled if the branch is true and the third is true for all
871 insns that can be annulled if the branch is false.
873 Multiple DEFINE_DELAYs may be present. They indicate differing
874 requirements for delay slots. */
875 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
877 /* Define attribute computation for `asm' instructions. */
878 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
880 /* Definition of a conditional execution meta operation. Automatically
881 generates new instances of DEFINE_INSN, selected by having attribute
882 "predicable" true. The new pattern will contain a COND_EXEC and the
883 predicate at top-level.
886 0: The predicate pattern. The top-level form should match a
887 relational operator. Operands should have only one alternative.
888 1: A C expression giving an additional condition for recognizing
889 the generated pattern.
890 2: A template or C code to produce assembler output. */
891 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
893 /* Definition of an operand predicate. The difference between
894 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
895 not warn about a match_operand with no mode if it has a predicate
896 defined with DEFINE_SPECIAL_PREDICATE.
899 0: The name of the predicate.
900 1: A boolean expression which computes whether or not the predicate
901 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
902 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
903 can calculate the set of RTX codes that can possibly match.
904 2: A C function body which must return true for the predicate to match.
905 Optional. Use this when the test is too complicated to fit into a
906 match_test expression. */
907 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
908 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
910 /* Definition of a register operand constraint. This simply maps the
911 constraint string to a register class.
914 0: The name of the constraint (often, but not always, a single letter).
915 1: A C expression which evaluates to the appropriate register class for
916 this constraint. If this is not just a constant, it should look only
917 at -m switches and the like.
918 2: A docstring for this constraint, in Texinfo syntax; not currently
919 used, in future will be incorporated into the manual's list of
920 machine-specific operand constraints. */
921 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
923 /* Definition of a non-register operand constraint. These look at the
924 operand and decide whether it fits the constraint.
926 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
927 It is appropriate for constant-only constraints, and most others.
929 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
930 to match, if it doesn't already, by converting the operand to the form
931 (mem (reg X)) where X is a base register. It is suitable for constraints
932 that describe a subset of all memory references.
934 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
935 to match, if it doesn't already, by converting the operand to the form
936 (reg X) where X is a base register. It is suitable for constraints that
937 describe a subset of all address references.
939 When in doubt, use plain DEFINE_CONSTRAINT.
942 0: The name of the constraint (often, but not always, a single letter).
943 1: A docstring for this constraint, in Texinfo syntax; not currently
944 used, in future will be incorporated into the manual's list of
945 machine-specific operand constraints.
946 2: A boolean expression which computes whether or not the constraint
947 matches. It should follow the same rules as a define_predicate
948 expression, including the bit about specifying the set of RTX codes
949 that could possibly match. MATCH_TEST subexpressions may make use of
951 `op' - the RTL object defining the operand.
952 `mode' - the mode of `op'.
953 `ival' - INTVAL(op), if op is a CONST_INT.
954 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
955 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
956 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
958 Do not use ival/hval/lval/rval if op is not the appropriate kind of
960 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
961 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
962 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
965 /* Constructions for CPU pipeline description described by NDFAs. */
967 /* (define_cpu_unit string [string]) describes cpu functional
968 units (separated by comma).
970 1st operand: Names of cpu functional units.
971 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
973 All define_reservations, define_cpu_units, and
974 define_query_cpu_units should have unique names which may not be
976 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
978 /* (define_query_cpu_unit string [string]) describes cpu functional
979 units analogously to define_cpu_unit. The reservation of such
980 units can be queried for automaton state. */
981 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
983 /* (exclusion_set string string) means that each CPU functional unit
984 in the first string can not be reserved simultaneously with any
985 unit whose name is in the second string and vise versa. CPU units
986 in the string are separated by commas. For example, it is useful
987 for description CPU with fully pipelined floating point functional
988 unit which can execute simultaneously only single floating point
989 insns or only double floating point insns. All CPU functional
990 units in a set should belong to the same automaton. */
991 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
993 /* (presence_set string string) means that each CPU functional unit in
994 the first string can not be reserved unless at least one of pattern
995 of units whose names are in the second string is reserved. This is
996 an asymmetric relation. CPU units or unit patterns in the strings
997 are separated by commas. Pattern is one unit name or unit names
998 separated by white-spaces.
1000 For example, it is useful for description that slot1 is reserved
1001 after slot0 reservation for a VLIW processor. We could describe it
1002 by the following construction
1004 (presence_set "slot1" "slot0")
1006 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1007 this case we could write
1009 (presence_set "slot1" "slot0 b0")
1011 All CPU functional units in a set should belong to the same
1013 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1015 /* (final_presence_set string string) is analogous to `presence_set'.
1016 The difference between them is when checking is done. When an
1017 instruction is issued in given automaton state reflecting all
1018 current and planned unit reservations, the automaton state is
1019 changed. The first state is a source state, the second one is a
1020 result state. Checking for `presence_set' is done on the source
1021 state reservation, checking for `final_presence_set' is done on the
1022 result reservation. This construction is useful to describe a
1023 reservation which is actually two subsequent reservations. For
1026 (presence_set "slot1" "slot0")
1028 the following insn will be never issued (because slot1 requires
1029 slot0 which is absent in the source state).
1031 (define_reservation "insn_and_nop" "slot0 + slot1")
1033 but it can be issued if we use analogous `final_presence_set'. */
1034 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1036 /* (absence_set string string) means that each CPU functional unit in
1037 the first string can be reserved only if each pattern of units
1038 whose names are in the second string is not reserved. This is an
1039 asymmetric relation (actually exclusion set is analogous to this
1040 one but it is symmetric). CPU units or unit patterns in the string
1041 are separated by commas. Pattern is one unit name or unit names
1042 separated by white-spaces.
1044 For example, it is useful for description that slot0 can not be
1045 reserved after slot1 or slot2 reservation for a VLIW processor. We
1046 could describe it by the following construction
1048 (absence_set "slot2" "slot0, slot1")
1050 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1051 slot1 and unit b1 are reserved . In this case we could write
1053 (absence_set "slot2" "slot0 b0, slot1 b1")
1055 All CPU functional units in a set should to belong the same
1057 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1059 /* (final_absence_set string string) is analogous to `absence_set' but
1060 checking is done on the result (state) reservation. See comments
1061 for `final_presence_set'. */
1062 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1064 /* (define_bypass number out_insn_names in_insn_names) names bypass
1065 with given latency (the first number) from insns given by the first
1066 string (see define_insn_reservation) into insns given by the second
1067 string. Insn names in the strings are separated by commas. The
1068 third operand is optional name of function which is additional
1069 guard for the bypass. The function will get the two insns as
1070 parameters. If the function returns zero the bypass will be
1071 ignored for this case. Additional guard is necessary to recognize
1072 complicated bypasses, e.g. when consumer is load address. */
1073 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1075 /* (define_automaton string) describes names of automata generated and
1076 used for pipeline hazards recognition. The names are separated by
1077 comma. Actually it is possibly to generate the single automaton
1078 but unfortunately it can be very large. If we use more one
1079 automata, the summary size of the automata usually is less than the
1080 single one. The automaton name is used in define_cpu_unit and
1081 define_query_cpu_unit. All automata should have unique names. */
1082 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1084 /* (automata_option string) describes option for generation of
1085 automata. Currently there are the following options:
1087 o "no-minimization" which makes no minimization of automata. This
1088 is only worth to do when we are debugging the description and
1089 need to look more accurately at reservations of states.
1091 o "time" which means printing additional time statistics about
1092 generation of automata.
1094 o "v" which means generation of file describing the result
1095 automata. The file has suffix `.dfa' and can be used for the
1096 description verification and debugging.
1098 o "w" which means generation of warning instead of error for
1099 non-critical errors.
1101 o "ndfa" which makes nondeterministic finite state automata.
1103 o "progress" which means output of a progress bar showing how many
1104 states were generated so far for automaton being processed. */
1105 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1107 /* (define_reservation string string) names reservation (the first
1108 string) of cpu functional units (the 2nd string). Sometimes unit
1109 reservations for different insns contain common parts. In such
1110 case, you can describe common part and use its name (the 1st
1111 parameter) in regular expression in define_insn_reservation. All
1112 define_reservations, define_cpu_units, and define_query_cpu_units
1113 should have unique names which may not be "nothing". */
1114 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1116 /* (define_insn_reservation name default_latency condition regexpr)
1117 describes reservation of cpu functional units (the 3nd operand) for
1118 instruction which is selected by the condition (the 2nd parameter).
1119 The first parameter is used for output of debugging information.
1120 The reservations are described by a regular expression according
1121 the following syntax:
1123 regexp = regexp "," oneof
1126 oneof = oneof "|" allof
1129 allof = allof "+" repeat
1132 repeat = element "*" number
1135 element = cpu_function_unit_name
1141 1. "," is used for describing start of the next cycle in
1144 2. "|" is used for describing the reservation described by the
1145 first regular expression *or* the reservation described by the
1146 second regular expression *or* etc.
1148 3. "+" is used for describing the reservation described by the
1149 first regular expression *and* the reservation described by the
1150 second regular expression *and* etc.
1152 4. "*" is used for convenience and simply means sequence in
1153 which the regular expression are repeated NUMBER times with
1154 cycle advancing (see ",").
1156 5. cpu functional unit name which means its reservation.
1158 6. reservation name -- see define_reservation.
1160 7. string "nothing" means no units reservation. */
1162 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1164 /* Expressions used for insn attributes. */
1166 /* Definition of an insn attribute.
1167 1st operand: name of the attribute
1168 2nd operand: comma-separated list of possible attribute values
1169 3rd operand: expression for the default value of the attribute. */
1170 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1172 /* Marker for the name of an attribute. */
1173 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1175 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1176 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1179 (set_attr "name" "value") is equivalent to
1180 (set (attr "name") (const_string "value")) */
1181 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1183 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1184 specify that attribute values are to be assigned according to the
1185 alternative matched.
1187 The following three expressions are equivalent:
1189 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1190 (eq_attrq "alternative" "2") (const_string "a2")]
1191 (const_string "a3")))
1192 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1193 (const_string "a3")])
1194 (set_attr "att" "a1,a2,a3")
1196 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1198 /* A conditional expression true if the value of the specified attribute of
1199 the current insn equals the specified value. The first operand is the
1200 attribute name and the second is the comparison value. */
1201 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1203 /* A special case of the above representing a set of alternatives. The first
1204 operand is bitmap of the set, the second one is the default value. */
1205 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1207 /* A conditional expression which is true if the specified flag is
1208 true for the insn being scheduled in reorg.
1210 genattr.c defines the following flags which can be tested by
1211 (attr_flag "foo") expressions in eligible_for_delay.
1213 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1215 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1217 /* General conditional. The first operand is a vector composed of pairs of
1218 expressions. The first element of each pair is evaluated, in turn.
1219 The value of the conditional is the second expression of the first pair
1220 whose first expression evaluates nonzero. If none of the expressions is
1221 true, the second operand will be used as the value of the conditional. */
1222 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1224 #endif /* GENERATOR_FILE */