1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Instruction reorganization pass.
25 This pass runs after register allocation and final jump
26 optimization. It should be the last pass to run before peephole.
27 It serves primarily to fill delay slots of insns, typically branch
28 and call insns. Other insns typically involve more complicated
29 interactions of data dependencies and resource constraints, and
30 are better handled by scheduling before register allocation (by the
31 function `schedule_insns').
33 The Branch Penalty is the number of extra cycles that are needed to
34 execute a branch insn. On an ideal machine, branches take a single
35 cycle, and the Branch Penalty is 0. Several RISC machines approach
36 branch delays differently:
38 The MIPS and AMD 29000 have a single branch delay slot. Most insns
39 (except other branches) can be used to fill this slot. When the
40 slot is filled, two insns execute in two cycles, reducing the
41 branch penalty to zero.
43 The Motorola 88000 conditionally exposes its branch delay slot,
44 so code is shorter when it is turned off, but will run faster
45 when useful insns are scheduled there.
47 The IBM ROMP has two forms of branch and call insns, both with and
48 without a delay slot. Much like the 88k, insns not using the delay
49 slot can be shorted (2 bytes vs. 4 bytes), but will run slowed.
51 The SPARC always has a branch delay slot, but its effects can be
52 annulled when the branch is not taken. This means that failing to
53 find other sources of insns, we can hoist an insn from the branch
54 target that would only be safe to execute knowing that the branch
57 The HP-PA always has a branch delay slot. For unconditional branches
58 its effects can be annulled when the branch is taken. The effects
59 of the delay slot in a conditional branch can be nullified for forward
60 taken branches, or for untaken backward branches. This means
61 we can hoist insns from the fall-through path for forward branches or
62 steal insns from the target of backward branches.
64 Three techniques for filling delay slots have been implemented so far:
66 (1) `fill_simple_delay_slots' is the simplest, most efficient way
67 to fill delay slots. This pass first looks for insns which come
68 from before the branch and which are safe to execute after the
69 branch. Then it searches after the insn requiring delay slots or,
70 in the case of a branch, for insns that are after the point at
71 which the branch merges into the fallthrough code, if such a point
72 exists. When such insns are found, the branch penalty decreases
73 and no code expansion takes place.
75 (2) `fill_eager_delay_slots' is more complicated: it is used for
76 scheduling conditional jumps, or for scheduling jumps which cannot
77 be filled using (1). A machine need not have annulled jumps to use
78 this strategy, but it helps (by keeping more options open).
79 `fill_eager_delay_slots' tries to guess the direction the branch
80 will go; if it guesses right 100% of the time, it can reduce the
81 branch penalty as much as `fill_simple_delay_slots' does. If it
82 guesses wrong 100% of the time, it might as well schedule nops (or
83 on the m88k, unexpose the branch slot). When
84 `fill_eager_delay_slots' takes insns from the fall-through path of
85 the jump, usually there is no code expansion; when it takes insns
86 from the branch target, there is code expansion if it is not the
87 only way to reach that target.
89 (3) `relax_delay_slots' uses a set of rules to simplify code that
90 has been reorganized by (1) and (2). It finds cases where
91 conditional test can be eliminated, jumps can be threaded, extra
92 insns can be eliminated, etc. It is the job of (1) and (2) to do a
93 good job of scheduling locally; `relax_delay_slots' takes care of
94 making the various individual schedules work well together. It is
95 especially tuned to handle the control flow interactions of branch
96 insns. It does nothing for insns with delay slots that do not
99 On machines that use CC0, we are very conservative. We will not make
100 a copy of an insn involving CC0 since we want to maintain a 1-1
101 correspondence between the insn that sets and uses CC0. The insns are
102 allowed to be separated by placing an insn that sets CC0 (but not an insn
103 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
104 delay slot. In that case, we point each insn at the other with REG_CC_USER
105 and REG_CC_SETTER notes. Note that these restrictions affect very few
106 machines because most RISC machines with delay slots will not use CC0
107 (the RT is the only known exception at this point).
111 The Acorn Risc Machine can conditionally execute most insns, so
112 it is profitable to move single insns into a position to execute
113 based on the condition code of the previous insn.
115 The HP-PA can conditionally nullify insns, providing a similar
116 effect to the ARM, differing mostly in which insn is "in charge". */
122 #include "insn-config.h"
123 #include "conditions.h"
124 #include "hard-reg-set.h"
125 #include "basic-block.h"
127 #include "insn-flags.h"
132 #include "insn-attr.h"
134 /* Import list of registers used as spill regs from reload. */
135 extern HARD_REG_SET used_spill_regs;
137 /* Import highest label used in function at end of reload. */
138 extern int max_label_num_after_reload;
143 #define obstack_chunk_alloc xmalloc
144 #define obstack_chunk_free free
146 #ifndef ANNUL_IFTRUE_SLOTS
147 #define eligible_for_annul_true(INSN, SLOTS, TRIAL, FLAGS) 0
149 #ifndef ANNUL_IFFALSE_SLOTS
150 #define eligible_for_annul_false(INSN, SLOTS, TRIAL, FLAGS) 0
153 /* Insns which have delay slots that have not yet been filled. */
155 static struct obstack unfilled_slots_obstack;
156 static rtx *unfilled_firstobj;
158 /* Define macros to refer to the first and last slot containing unfilled
159 insns. These are used because the list may move and its address
160 should be recomputed at each use. */
162 #define unfilled_slots_base \
163 ((rtx *) obstack_base (&unfilled_slots_obstack))
165 #define unfilled_slots_next \
166 ((rtx *) obstack_next_free (&unfilled_slots_obstack))
168 /* This structure is used to indicate which hardware resources are set or
169 needed by insns so far. */
173 char memory; /* Insn sets or needs a memory location. */
174 char unch_memory; /* Insn sets of needs a "unchanging" MEM. */
175 char volatil; /* Insn sets or needs a volatile memory loc. */
176 char cc; /* Insn sets or needs the condition codes. */
177 HARD_REG_SET regs; /* Which registers are set or needed. */
180 /* Macro to clear all resources. */
181 #define CLEAR_RESOURCE(RES) \
182 do { (RES)->memory = (RES)->unch_memory = (RES)->volatil = (RES)->cc = 0; \
183 CLEAR_HARD_REG_SET ((RES)->regs); } while (0)
185 /* Indicates what resources are required at the beginning of the epilogue. */
186 static struct resources start_of_epilogue_needs;
188 /* Indicates what resources are required at function end. */
189 static struct resources end_of_function_needs;
191 /* Points to the label before the end of the function. */
192 static rtx end_of_function_label;
194 /* This structure is used to record liveness information at the targets or
195 fallthrough insns of branches. We will most likely need the information
196 at targets again, so save them in a hash table rather than recomputing them
201 int uid; /* INSN_UID of target. */
202 struct target_info *next; /* Next info for same hash bucket. */
203 HARD_REG_SET live_regs; /* Registers live at target. */
204 int block; /* Basic block number containing target. */
205 int bb_tick; /* Generation count of basic block info. */
208 #define TARGET_HASH_PRIME 257
210 /* Define the hash table itself. */
211 static struct target_info **target_hash_table;
213 /* For each basic block, we maintain a generation number of its basic
214 block info, which is updated each time we move an insn from the
215 target of a jump. This is the generation number indexed by block
218 static int *bb_ticks;
220 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
221 not always monotonically increase. */
222 static int *uid_to_ruid;
224 /* Highest valid index in `uid_to_ruid'. */
227 static void mark_referenced_resources PROTO((rtx, struct resources *, int));
228 static void mark_set_resources PROTO((rtx, struct resources *, int, int));
229 static int stop_search_p PROTO((rtx, int));
230 static int resource_conflicts_p PROTO((struct resources *,
231 struct resources *));
232 static int insn_references_resource_p PROTO((rtx, struct resources *, int));
233 static int insn_sets_resource_p PROTO((rtx, struct resources *, int));
234 static rtx find_end_label PROTO((void));
235 static rtx emit_delay_sequence PROTO((rtx, rtx, int));
236 static rtx add_to_delay_list PROTO((rtx, rtx));
237 static void delete_from_delay_slot PROTO((rtx));
238 static void delete_scheduled_jump PROTO((rtx));
239 static void note_delay_statistics PROTO((int, int));
240 static rtx optimize_skip PROTO((rtx));
241 static int get_jump_flags PROTO((rtx, rtx));
242 static int rare_destination PROTO((rtx));
243 static int mostly_true_jump PROTO((rtx, rtx));
244 static rtx get_branch_condition PROTO((rtx, rtx));
245 static int condition_dominates_p PROTO((rtx, rtx));
246 static rtx steal_delay_list_from_target PROTO((rtx, rtx, rtx, rtx,
250 int, int *, int *, rtx *));
251 static rtx steal_delay_list_from_fallthrough PROTO((rtx, rtx, rtx, rtx,
256 static void try_merge_delay_insns PROTO((rtx, rtx));
257 static rtx redundant_insn PROTO((rtx, rtx, rtx));
258 static int own_thread_p PROTO((rtx, rtx, int));
259 static int find_basic_block PROTO((rtx));
260 static void update_block PROTO((rtx, rtx));
261 static int reorg_redirect_jump PROTO((rtx, rtx));
262 static void update_reg_dead_notes PROTO((rtx, rtx));
263 static void fix_reg_dead_note PROTO((rtx, rtx));
264 static void update_reg_unused_notes PROTO((rtx, rtx));
265 static void update_live_status PROTO((rtx, rtx));
266 static rtx next_insn_no_annul PROTO((rtx));
267 static void mark_target_live_regs PROTO((rtx, struct resources *));
268 static void fill_simple_delay_slots PROTO((int));
269 static rtx fill_slots_from_thread PROTO((rtx, rtx, rtx, rtx, int, int,
271 static void fill_eager_delay_slots PROTO((void));
272 static void relax_delay_slots PROTO((rtx));
273 static void make_return_insns PROTO((rtx));
274 static int redirect_with_delay_slots_safe_p PROTO ((rtx, rtx, rtx));
275 static int redirect_with_delay_list_safe_p PROTO ((rtx, rtx, rtx));
277 /* Given X, some rtl, and RES, a pointer to a `struct resource', mark
278 which resources are references by the insn. If INCLUDE_CALLED_ROUTINE
279 is TRUE, resources used by the called routine will be included for
283 mark_referenced_resources (x, res, include_delayed_effects)
285 register struct resources *res;
286 register int include_delayed_effects;
288 register enum rtx_code code = GET_CODE (x);
290 register char *format_ptr;
292 /* Handle leaf items for which we set resource flags. Also, special-case
293 CALL, SET and CLOBBER operators. */
305 if (GET_CODE (SUBREG_REG (x)) != REG)
306 mark_referenced_resources (SUBREG_REG (x), res, 0);
309 int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
310 int last_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
311 for (i = regno; i < last_regno; i++)
312 SET_HARD_REG_BIT (res->regs, i);
317 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
318 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
322 /* If this memory shouldn't change, it really isn't referencing
324 if (RTX_UNCHANGING_P (x))
325 res->unch_memory = 1;
328 res->volatil = MEM_VOLATILE_P (x);
330 /* Mark registers used to access memory. */
331 mark_referenced_resources (XEXP (x, 0), res, 0);
338 case UNSPEC_VOLATILE:
341 /* Traditional asm's are always volatile. */
346 res->volatil = MEM_VOLATILE_P (x);
348 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
349 We can not just fall through here since then we would be confused
350 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
351 traditional asms unlike their normal usage. */
353 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
354 mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, 0);
358 /* The first operand will be a (MEM (xxx)) but doesn't really reference
359 memory. The second operand may be referenced, though. */
360 mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, 0);
361 mark_referenced_resources (XEXP (x, 1), res, 0);
365 /* Usually, the first operand of SET is set, not referenced. But
366 registers used to access memory are referenced. SET_DEST is
367 also referenced if it is a ZERO_EXTRACT or SIGN_EXTRACT. */
369 mark_referenced_resources (SET_SRC (x), res, 0);
372 if (GET_CODE (x) == SIGN_EXTRACT || GET_CODE (x) == ZERO_EXTRACT)
373 mark_referenced_resources (x, res, 0);
374 else if (GET_CODE (x) == SUBREG)
376 if (GET_CODE (x) == MEM)
377 mark_referenced_resources (XEXP (x, 0), res, 0);
384 if (include_delayed_effects)
386 /* A CALL references memory, the frame pointer if it exists, the
387 stack pointer, any global registers and any registers given in
388 USE insns immediately in front of the CALL.
390 However, we may have moved some of the parameter loading insns
391 into the delay slot of this CALL. If so, the USE's for them
392 don't count and should be skipped. */
393 rtx insn = PREV_INSN (x);
396 rtx next = NEXT_INSN (x);
399 /* If we are part of a delay slot sequence, point at the SEQUENCE. */
400 if (NEXT_INSN (insn) != x)
402 next = NEXT_INSN (NEXT_INSN (insn));
403 sequence = PATTERN (NEXT_INSN (insn));
404 seq_size = XVECLEN (sequence, 0);
405 if (GET_CODE (sequence) != SEQUENCE)
410 SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM);
411 if (frame_pointer_needed)
413 SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM);
414 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
415 SET_HARD_REG_BIT (res->regs, HARD_FRAME_POINTER_REGNUM);
419 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
421 SET_HARD_REG_BIT (res->regs, i);
423 /* Check for a NOTE_INSN_SETJMP. If it exists, then we must
424 assume that this call can need any register.
426 This is done to be more conservative about how we handle setjmp.
427 We assume that they both use and set all registers. Using all
428 registers ensures that a register will not be considered dead
429 just because it crosses a setjmp call. A register should be
430 considered dead only if the setjmp call returns non-zero. */
431 if (next && GET_CODE (next) == NOTE
432 && NOTE_LINE_NUMBER (next) == NOTE_INSN_SETJMP)
433 SET_HARD_REG_SET (res->regs);
438 for (link = CALL_INSN_FUNCTION_USAGE (x);
440 link = XEXP (link, 1))
441 if (GET_CODE (XEXP (link, 0)) == USE)
443 for (i = 1; i < seq_size; i++)
445 rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i));
446 if (GET_CODE (slot_pat) == SET
447 && rtx_equal_p (SET_DEST (slot_pat),
448 SET_DEST (XEXP (link, 0))))
452 mark_referenced_resources (SET_DEST (XEXP (link, 0)),
458 /* ... fall through to other INSN processing ... */
463 #ifdef INSN_REFERENCES_ARE_DELAYED
464 if (! include_delayed_effects
465 && INSN_REFERENCES_ARE_DELAYED (x))
469 /* No special processing, just speed up. */
470 mark_referenced_resources (PATTERN (x), res, include_delayed_effects);
477 /* Process each sub-expression and flag what it needs. */
478 format_ptr = GET_RTX_FORMAT (code);
479 for (i = 0; i < GET_RTX_LENGTH (code); i++)
480 switch (*format_ptr++)
483 mark_referenced_resources (XEXP (x, i), res, include_delayed_effects);
487 for (j = 0; j < XVECLEN (x, i); j++)
488 mark_referenced_resources (XVECEXP (x, i, j), res,
489 include_delayed_effects);
494 /* Given X, a part of an insn, and a pointer to a `struct resource', RES,
495 indicate which resources are modified by the insn. If INCLUDE_CALLED_ROUTINE
496 is nonzero, also mark resources potentially set by the called routine.
498 If IN_DEST is nonzero, it means we are inside a SET. Otherwise,
499 objects are being referenced instead of set.
501 We never mark the insn as modifying the condition code unless it explicitly
502 SETs CC0 even though this is not totally correct. The reason for this is
503 that we require a SET of CC0 to immediately precede the reference to CC0.
504 So if some other insn sets CC0 as a side-effect, we know it cannot affect
505 our computation and thus may be placed in a delay slot. */
508 mark_set_resources (x, res, in_dest, include_delayed_effects)
510 register struct resources *res;
512 int include_delayed_effects;
514 register enum rtx_code code;
516 register char *format_ptr;
534 /* These don't set any resources. */
543 /* Called routine modifies the condition code, memory, any registers
544 that aren't saved across calls, global registers and anything
545 explicitly CLOBBERed immediately after the CALL_INSN. */
547 if (include_delayed_effects)
549 rtx next = NEXT_INSN (x);
550 rtx prev = PREV_INSN (x);
553 res->cc = res->memory = 1;
554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
555 if (call_used_regs[i] || global_regs[i])
556 SET_HARD_REG_BIT (res->regs, i);
558 /* If X is part of a delay slot sequence, then NEXT should be
559 the first insn after the sequence. */
560 if (NEXT_INSN (prev) != x)
561 next = NEXT_INSN (NEXT_INSN (prev));
563 for (link = CALL_INSN_FUNCTION_USAGE (x);
564 link; link = XEXP (link, 1))
565 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
566 mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, 0);
568 /* Check for a NOTE_INSN_SETJMP. If it exists, then we must
569 assume that this call can clobber any register. */
570 if (next && GET_CODE (next) == NOTE
571 && NOTE_LINE_NUMBER (next) == NOTE_INSN_SETJMP)
572 SET_HARD_REG_SET (res->regs);
575 /* ... and also what it's RTL says it modifies, if anything. */
580 /* An insn consisting of just a CLOBBER (or USE) is just for flow
581 and doesn't actually do anything, so we ignore it. */
583 #ifdef INSN_SETS_ARE_DELAYED
584 if (! include_delayed_effects
585 && INSN_SETS_ARE_DELAYED (x))
590 if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER)
595 /* If the source of a SET is a CALL, this is actually done by
596 the called routine. So only include it if we are to include the
597 effects of the calling routine. */
599 mark_set_resources (SET_DEST (x), res,
600 (include_delayed_effects
601 || GET_CODE (SET_SRC (x)) != CALL),
604 mark_set_resources (SET_SRC (x), res, 0, 0);
608 mark_set_resources (XEXP (x, 0), res, 1, 0);
612 for (i = 0; i < XVECLEN (x, 0); i++)
613 if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0))
614 && INSN_FROM_TARGET_P (XVECEXP (x, 0, i))))
615 mark_set_resources (XVECEXP (x, 0, i), res, 0,
616 include_delayed_effects);
623 mark_set_resources (XEXP (x, 0), res, 1, 0);
627 mark_set_resources (XEXP (x, 0), res, in_dest, 0);
628 mark_set_resources (XEXP (x, 1), res, 0, 0);
629 mark_set_resources (XEXP (x, 2), res, 0, 0);
636 res->unch_memory = RTX_UNCHANGING_P (x);
637 res->volatil = MEM_VOLATILE_P (x);
640 mark_set_resources (XEXP (x, 0), res, 0, 0);
646 if (GET_CODE (SUBREG_REG (x)) != REG)
647 mark_set_resources (SUBREG_REG (x), res,
648 in_dest, include_delayed_effects);
651 int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
652 int last_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
653 for (i = regno; i < last_regno; i++)
654 SET_HARD_REG_BIT (res->regs, i);
661 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
662 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
669 /* Process each sub-expression and flag what it needs. */
670 format_ptr = GET_RTX_FORMAT (code);
671 for (i = 0; i < GET_RTX_LENGTH (code); i++)
672 switch (*format_ptr++)
675 mark_set_resources (XEXP (x, i), res, in_dest, include_delayed_effects);
679 for (j = 0; j < XVECLEN (x, i); j++)
680 mark_set_resources (XVECEXP (x, i, j), res, in_dest,
681 include_delayed_effects);
686 /* Return TRUE if this insn should stop the search for insn to fill delay
687 slots. LABELS_P indicates that labels should terminate the search.
688 In all cases, jumps terminate the search. */
691 stop_search_p (insn, labels_p)
698 switch (GET_CODE (insn))
712 /* OK unless it contains a delay slot or is an `asm' insn of some type.
713 We don't know anything about these. */
714 return (GET_CODE (PATTERN (insn)) == SEQUENCE
715 || GET_CODE (PATTERN (insn)) == ASM_INPUT
716 || asm_noperands (PATTERN (insn)) >= 0);
723 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
724 resource set contains a volatile memory reference. Otherwise, return FALSE. */
727 resource_conflicts_p (res1, res2)
728 struct resources *res1, *res2;
730 if ((res1->cc && res2->cc) || (res1->memory && res2->memory)
731 || (res1->unch_memory && res2->unch_memory)
732 || res1->volatil || res2->volatil)
736 return (res1->regs & res2->regs) != HARD_CONST (0);
741 for (i = 0; i < HARD_REG_SET_LONGS; i++)
742 if ((res1->regs[i] & res2->regs[i]) != 0)
749 /* Return TRUE if any resource marked in RES, a `struct resources', is
750 referenced by INSN. If INCLUDE_CALLED_ROUTINE is set, return if the called
751 routine is using those resources.
753 We compute this by computing all the resources referenced by INSN and
754 seeing if this conflicts with RES. It might be faster to directly check
755 ourselves, and this is the way it used to work, but it means duplicating
756 a large block of complex code. */
759 insn_references_resource_p (insn, res, include_delayed_effects)
761 register struct resources *res;
762 int include_delayed_effects;
764 struct resources insn_res;
766 CLEAR_RESOURCE (&insn_res);
767 mark_referenced_resources (insn, &insn_res, include_delayed_effects);
768 return resource_conflicts_p (&insn_res, res);
771 /* Return TRUE if INSN modifies resources that are marked in RES.
772 INCLUDE_CALLED_ROUTINE is set if the actions of that routine should be
773 included. CC0 is only modified if it is explicitly set; see comments
774 in front of mark_set_resources for details. */
777 insn_sets_resource_p (insn, res, include_delayed_effects)
779 register struct resources *res;
780 int include_delayed_effects;
782 struct resources insn_sets;
784 CLEAR_RESOURCE (&insn_sets);
785 mark_set_resources (insn, &insn_sets, 0, include_delayed_effects);
786 return resource_conflicts_p (&insn_sets, res);
789 /* Find a label at the end of the function or before a RETURN. If there is
797 /* If we found one previously, return it. */
798 if (end_of_function_label)
799 return end_of_function_label;
801 /* Otherwise, see if there is a label at the end of the function. If there
802 is, it must be that RETURN insns aren't needed, so that is our return
803 label and we don't have to do anything else. */
805 insn = get_last_insn ();
806 while (GET_CODE (insn) == NOTE
807 || (GET_CODE (insn) == INSN
808 && (GET_CODE (PATTERN (insn)) == USE
809 || GET_CODE (PATTERN (insn)) == CLOBBER)))
810 insn = PREV_INSN (insn);
812 /* When a target threads its epilogue we might already have a
813 suitable return insn. If so put a label before it for the
814 end_of_function_label. */
815 if (GET_CODE (insn) == BARRIER
816 && GET_CODE (PREV_INSN (insn)) == JUMP_INSN
817 && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN)
819 rtx temp = PREV_INSN (PREV_INSN (insn));
820 end_of_function_label = gen_label_rtx ();
821 LABEL_NUSES (end_of_function_label) = 0;
823 /* Put the label before an USE insns that may proceed the RETURN insn. */
824 while (GET_CODE (temp) == USE)
825 temp = PREV_INSN (temp);
827 emit_label_after (end_of_function_label, temp);
830 else if (GET_CODE (insn) == CODE_LABEL)
831 end_of_function_label = insn;
834 /* Otherwise, make a new label and emit a RETURN and BARRIER,
836 end_of_function_label = gen_label_rtx ();
837 LABEL_NUSES (end_of_function_label) = 0;
838 emit_label (end_of_function_label);
842 /* The return we make may have delay slots too. */
843 rtx insn = gen_return ();
844 insn = emit_jump_insn (insn);
846 if (num_delay_slots (insn) > 0)
847 obstack_ptr_grow (&unfilled_slots_obstack, insn);
852 /* Show one additional use for this label so it won't go away until
854 ++LABEL_NUSES (end_of_function_label);
856 return end_of_function_label;
859 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
860 the pattern of INSN with the SEQUENCE.
862 Chain the insns so that NEXT_INSN of each insn in the sequence points to
863 the next and NEXT_INSN of the last insn in the sequence points to
864 the first insn after the sequence. Similarly for PREV_INSN. This makes
865 it easier to scan all insns.
867 Returns the SEQUENCE that replaces INSN. */
870 emit_delay_sequence (insn, list, length)
879 /* Allocate the the rtvec to hold the insns and the SEQUENCE. */
880 rtvec seqv = rtvec_alloc (length + 1);
881 rtx seq = gen_rtx_SEQUENCE (VOIDmode, seqv);
882 rtx seq_insn = make_insn_raw (seq);
883 rtx first = get_insns ();
884 rtx last = get_last_insn ();
886 /* Make a copy of the insn having delay slots. */
887 rtx delay_insn = copy_rtx (insn);
889 /* If INSN is followed by a BARRIER, delete the BARRIER since it will only
890 confuse further processing. Update LAST in case it was the last insn.
891 We will put the BARRIER back in later. */
892 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == BARRIER)
894 delete_insn (NEXT_INSN (insn));
895 last = get_last_insn ();
899 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
900 NEXT_INSN (seq_insn) = NEXT_INSN (insn);
901 PREV_INSN (seq_insn) = PREV_INSN (insn);
904 PREV_INSN (NEXT_INSN (seq_insn)) = seq_insn;
907 NEXT_INSN (PREV_INSN (seq_insn)) = seq_insn;
909 /* Note the calls to set_new_first_and_last_insn must occur after
910 SEQ_INSN has been completely spliced into the insn stream.
912 Otherwise CUR_INSN_UID will get set to an incorrect value because
913 set_new_first_and_last_insn will not find SEQ_INSN in the chain. */
915 set_new_first_and_last_insn (first, seq_insn);
918 set_new_first_and_last_insn (seq_insn, last);
920 /* Build our SEQUENCE and rebuild the insn chain. */
921 XVECEXP (seq, 0, 0) = delay_insn;
922 INSN_DELETED_P (delay_insn) = 0;
923 PREV_INSN (delay_insn) = PREV_INSN (seq_insn);
925 for (li = list; li; li = XEXP (li, 1), i++)
927 rtx tem = XEXP (li, 0);
930 /* Show that this copy of the insn isn't deleted. */
931 INSN_DELETED_P (tem) = 0;
933 XVECEXP (seq, 0, i) = tem;
934 PREV_INSN (tem) = XVECEXP (seq, 0, i - 1);
935 NEXT_INSN (XVECEXP (seq, 0, i - 1)) = tem;
937 /* Remove any REG_DEAD notes because we can't rely on them now
938 that the insn has been moved. */
939 for (note = REG_NOTES (tem); note; note = XEXP (note, 1))
940 if (REG_NOTE_KIND (note) == REG_DEAD)
941 XEXP (note, 0) = const0_rtx;
944 NEXT_INSN (XVECEXP (seq, 0, length)) = NEXT_INSN (seq_insn);
946 /* If the previous insn is a SEQUENCE, update the NEXT_INSN pointer on the
947 last insn in that SEQUENCE to point to us. Similarly for the first
948 insn in the following insn if it is a SEQUENCE. */
950 if (PREV_INSN (seq_insn) && GET_CODE (PREV_INSN (seq_insn)) == INSN
951 && GET_CODE (PATTERN (PREV_INSN (seq_insn))) == SEQUENCE)
952 NEXT_INSN (XVECEXP (PATTERN (PREV_INSN (seq_insn)), 0,
953 XVECLEN (PATTERN (PREV_INSN (seq_insn)), 0) - 1))
956 if (NEXT_INSN (seq_insn) && GET_CODE (NEXT_INSN (seq_insn)) == INSN
957 && GET_CODE (PATTERN (NEXT_INSN (seq_insn))) == SEQUENCE)
958 PREV_INSN (XVECEXP (PATTERN (NEXT_INSN (seq_insn)), 0, 0)) = seq_insn;
960 /* If there used to be a BARRIER, put it back. */
962 emit_barrier_after (seq_insn);
970 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
971 be in the order in which the insns are to be executed. */
974 add_to_delay_list (insn, delay_list)
978 /* If we have an empty list, just make a new list element. If
979 INSN has it's block number recorded, clear it since we may
980 be moving the insn to a new block. */
984 struct target_info *tinfo;
986 for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME];
987 tinfo; tinfo = tinfo->next)
988 if (tinfo->uid == INSN_UID (insn))
994 return gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX);
997 /* Otherwise this must be an INSN_LIST. Add INSN to the end of the
999 XEXP (delay_list, 1) = add_to_delay_list (insn, XEXP (delay_list, 1));
1004 /* Delete INSN from the the delay slot of the insn that it is in. This may
1005 produce an insn without anything in its delay slots. */
1008 delete_from_delay_slot (insn)
1011 rtx trial, seq_insn, seq, prev;
1015 /* We first must find the insn containing the SEQUENCE with INSN in its
1016 delay slot. Do this by finding an insn, TRIAL, where
1017 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
1020 PREV_INSN (NEXT_INSN (trial)) == trial;
1021 trial = NEXT_INSN (trial))
1024 seq_insn = PREV_INSN (NEXT_INSN (trial));
1025 seq = PATTERN (seq_insn);
1027 /* Create a delay list consisting of all the insns other than the one
1028 we are deleting (unless we were the only one). */
1029 if (XVECLEN (seq, 0) > 2)
1030 for (i = 1; i < XVECLEN (seq, 0); i++)
1031 if (XVECEXP (seq, 0, i) != insn)
1032 delay_list = add_to_delay_list (XVECEXP (seq, 0, i), delay_list);
1034 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
1035 list, and rebuild the delay list if non-empty. */
1036 prev = PREV_INSN (seq_insn);
1037 trial = XVECEXP (seq, 0, 0);
1038 delete_insn (seq_insn);
1039 add_insn_after (trial, prev);
1041 if (GET_CODE (trial) == JUMP_INSN
1042 && (simplejump_p (trial) || GET_CODE (PATTERN (trial)) == RETURN))
1043 emit_barrier_after (trial);
1045 /* If there are any delay insns, remit them. Otherwise clear the
1048 trial = emit_delay_sequence (trial, delay_list, XVECLEN (seq, 0) - 2);
1050 INSN_ANNULLED_BRANCH_P (trial) = 0;
1052 INSN_FROM_TARGET_P (insn) = 0;
1054 /* Show we need to fill this insn again. */
1055 obstack_ptr_grow (&unfilled_slots_obstack, trial);
1058 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
1059 the insn that sets CC0 for it and delete it too. */
1062 delete_scheduled_jump (insn)
1065 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
1066 delete the insn that sets the condition code, but it is hard to find it.
1067 Since this case is rare anyway, don't bother trying; there would likely
1068 be other insns that became dead anyway, which we wouldn't know to
1072 if (reg_mentioned_p (cc0_rtx, insn))
1074 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
1076 /* If a reg-note was found, it points to an insn to set CC0. This
1077 insn is in the delay list of some other insn. So delete it from
1078 the delay list it was in. */
1081 if (! FIND_REG_INC_NOTE (XEXP (note, 0), NULL_RTX)
1082 && sets_cc0_p (PATTERN (XEXP (note, 0))) == 1)
1083 delete_from_delay_slot (XEXP (note, 0));
1087 /* The insn setting CC0 is our previous insn, but it may be in
1088 a delay slot. It will be the last insn in the delay slot, if
1090 rtx trial = previous_insn (insn);
1091 if (GET_CODE (trial) == NOTE)
1092 trial = prev_nonnote_insn (trial);
1093 if (sets_cc0_p (PATTERN (trial)) != 1
1094 || FIND_REG_INC_NOTE (trial, 0))
1096 if (PREV_INSN (NEXT_INSN (trial)) == trial)
1097 delete_insn (trial);
1099 delete_from_delay_slot (trial);
1107 /* Counters for delay-slot filling. */
1109 #define NUM_REORG_FUNCTIONS 2
1110 #define MAX_DELAY_HISTOGRAM 3
1111 #define MAX_REORG_PASSES 2
1113 static int num_insns_needing_delays[NUM_REORG_FUNCTIONS][MAX_REORG_PASSES];
1115 static int num_filled_delays[NUM_REORG_FUNCTIONS][MAX_DELAY_HISTOGRAM+1][MAX_REORG_PASSES];
1117 static int reorg_pass_number;
1120 note_delay_statistics (slots_filled, index)
1121 int slots_filled, index;
1123 num_insns_needing_delays[index][reorg_pass_number]++;
1124 if (slots_filled > MAX_DELAY_HISTOGRAM)
1125 slots_filled = MAX_DELAY_HISTOGRAM;
1126 num_filled_delays[index][slots_filled][reorg_pass_number]++;
1129 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
1131 /* Optimize the following cases:
1133 1. When a conditional branch skips over only one instruction,
1134 use an annulling branch and put that insn in the delay slot.
1135 Use either a branch that annuls when the condition if true or
1136 invert the test with a branch that annuls when the condition is
1137 false. This saves insns, since otherwise we must copy an insn
1140 (orig) (skip) (otherwise)
1141 Bcc.n L1 Bcc',a L1 Bcc,a L1'
1148 2. When a conditional branch skips over only one instruction,
1149 and after that, it unconditionally branches somewhere else,
1150 perform the similar optimization. This saves executing the
1151 second branch in the case where the inverted condition is true.
1158 INSN is a JUMP_INSN.
1160 This should be expanded to skip over N insns, where N is the number
1161 of delay slots required. */
1164 optimize_skip (insn)
1167 register rtx trial = next_nonnote_insn (insn);
1168 rtx next_trial = next_active_insn (trial);
1173 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1176 || GET_CODE (trial) != INSN
1177 || GET_CODE (PATTERN (trial)) == SEQUENCE
1178 || recog_memoized (trial) < 0
1179 || (! eligible_for_annul_false (insn, 0, trial, flags)
1180 && ! eligible_for_annul_true (insn, 0, trial, flags)))
1183 /* There are two cases where we are just executing one insn (we assume
1184 here that a branch requires only one insn; this should be generalized
1185 at some point): Where the branch goes around a single insn or where
1186 we have one insn followed by a branch to the same label we branch to.
1187 In both of these cases, inverting the jump and annulling the delay
1188 slot give the same effect in fewer insns. */
1189 if ((next_trial == next_active_insn (JUMP_LABEL (insn)))
1191 && GET_CODE (next_trial) == JUMP_INSN
1192 && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)
1193 && (simplejump_p (next_trial)
1194 || GET_CODE (PATTERN (next_trial)) == RETURN)))
1196 if (eligible_for_annul_false (insn, 0, trial, flags))
1198 if (invert_jump (insn, JUMP_LABEL (insn)))
1199 INSN_FROM_TARGET_P (trial) = 1;
1200 else if (! eligible_for_annul_true (insn, 0, trial, flags))
1204 delay_list = add_to_delay_list (trial, NULL_RTX);
1205 next_trial = next_active_insn (trial);
1206 update_block (trial, trial);
1207 delete_insn (trial);
1209 /* Also, if we are targeting an unconditional
1210 branch, thread our jump to the target of that branch. Don't
1211 change this into a RETURN here, because it may not accept what
1212 we have in the delay slot. We'll fix this up later. */
1213 if (next_trial && GET_CODE (next_trial) == JUMP_INSN
1214 && (simplejump_p (next_trial)
1215 || GET_CODE (PATTERN (next_trial)) == RETURN))
1217 target_label = JUMP_LABEL (next_trial);
1218 if (target_label == 0)
1219 target_label = find_end_label ();
1221 /* Recompute the flags based on TARGET_LABEL since threading
1222 the jump to TARGET_LABEL may change the direction of the
1223 jump (which may change the circumstances in which the
1224 delay slot is nullified). */
1225 flags = get_jump_flags (insn, target_label);
1226 if (eligible_for_annul_true (insn, 0, trial, flags))
1227 reorg_redirect_jump (insn, target_label);
1230 INSN_ANNULLED_BRANCH_P (insn) = 1;
1238 /* Encode and return branch direction and prediction information for
1239 INSN assuming it will jump to LABEL.
1241 Non conditional branches return no direction information and
1242 are predicted as very likely taken. */
1245 get_jump_flags (insn, label)
1250 /* get_jump_flags can be passed any insn with delay slots, these may
1251 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
1252 direction information, and only if they are conditional jumps.
1254 If LABEL is zero, then there is no way to determine the branch
1256 if (GET_CODE (insn) == JUMP_INSN
1257 && (condjump_p (insn) || condjump_in_parallel_p (insn))
1258 && INSN_UID (insn) <= max_uid
1260 && INSN_UID (label) <= max_uid)
1262 = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)])
1263 ? ATTR_FLAG_forward : ATTR_FLAG_backward;
1264 /* No valid direction information. */
1268 /* If insn is a conditional branch call mostly_true_jump to get
1269 determine the branch prediction.
1271 Non conditional branches are predicted as very likely taken. */
1272 if (GET_CODE (insn) == JUMP_INSN
1273 && (condjump_p (insn) || condjump_in_parallel_p (insn)))
1277 prediction = mostly_true_jump (insn, get_branch_condition (insn, label));
1281 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1284 flags |= ATTR_FLAG_likely;
1287 flags |= ATTR_FLAG_unlikely;
1290 flags |= (ATTR_FLAG_very_unlikely | ATTR_FLAG_unlikely);
1298 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1303 /* Return 1 if INSN is a destination that will be branched to rarely (the
1304 return point of a function); return 2 if DEST will be branched to very
1305 rarely (a call to a function that doesn't return). Otherwise,
1309 rare_destination (insn)
1315 for (; insn; insn = next)
1317 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
1318 insn = XVECEXP (PATTERN (insn), 0, 0);
1320 next = NEXT_INSN (insn);
1322 switch (GET_CODE (insn))
1327 /* A BARRIER can either be after a JUMP_INSN or a CALL_INSN. We
1328 don't scan past JUMP_INSNs, so any barrier we find here must
1329 have been after a CALL_INSN and hence mean the call doesn't
1333 if (GET_CODE (PATTERN (insn)) == RETURN)
1335 else if (simplejump_p (insn)
1336 && jump_count++ < 10)
1337 next = JUMP_LABEL (insn);
1346 /* If we got here it means we hit the end of the function. So this
1347 is an unlikely destination. */
1352 /* Return truth value of the statement that this branch
1353 is mostly taken. If we think that the branch is extremely likely
1354 to be taken, we return 2. If the branch is slightly more likely to be
1355 taken, return 1. If the branch is slightly less likely to be taken,
1356 return 0 and if the branch is highly unlikely to be taken, return -1.
1358 CONDITION, if non-zero, is the condition that JUMP_INSN is testing. */
1361 mostly_true_jump (jump_insn, condition)
1362 rtx jump_insn, condition;
1364 rtx target_label = JUMP_LABEL (jump_insn);
1366 int rare_dest = rare_destination (target_label);
1367 int rare_fallthrough = rare_destination (NEXT_INSN (jump_insn));
1369 /* If branch probabilities are available, then use that number since it
1370 always gives a correct answer. */
1371 if (flag_branch_probabilities)
1373 rtx note = find_reg_note (jump_insn, REG_BR_PROB, 0);;
1376 int prob = XINT (note, 0);
1378 if (prob >= REG_BR_PROB_BASE * 9 / 10)
1380 else if (prob >= REG_BR_PROB_BASE / 2)
1382 else if (prob >= REG_BR_PROB_BASE / 10)
1389 /* If this is a branch outside a loop, it is highly unlikely. */
1390 if (GET_CODE (PATTERN (jump_insn)) == SET
1391 && GET_CODE (SET_SRC (PATTERN (jump_insn))) == IF_THEN_ELSE
1392 && ((GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 1)) == LABEL_REF
1393 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 1)))
1394 || (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 2)) == LABEL_REF
1395 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 2)))))
1400 /* If this is the test of a loop, it is very likely true. We scan
1401 backwards from the target label. If we find a NOTE_INSN_LOOP_BEG
1402 before the next real insn, we assume the branch is to the top of
1404 for (insn = PREV_INSN (target_label);
1405 insn && GET_CODE (insn) == NOTE;
1406 insn = PREV_INSN (insn))
1407 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1410 /* If this is a jump to the test of a loop, it is likely true. We scan
1411 forwards from the target label. If we find a NOTE_INSN_LOOP_VTOP
1412 before the next real insn, we assume the branch is to the loop branch
1414 for (insn = NEXT_INSN (target_label);
1415 insn && GET_CODE (insn) == NOTE;
1416 insn = PREV_INSN (insn))
1417 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_VTOP)
1421 /* Look at the relative rarities of the fallthrough and destination. If
1422 they differ, we can predict the branch that way. */
1424 switch (rare_fallthrough - rare_dest)
1438 /* If we couldn't figure out what this jump was, assume it won't be
1439 taken. This should be rare. */
1443 /* EQ tests are usually false and NE tests are usually true. Also,
1444 most quantities are positive, so we can make the appropriate guesses
1445 about signed comparisons against zero. */
1446 switch (GET_CODE (condition))
1449 /* Unconditional branch. */
1457 if (XEXP (condition, 1) == const0_rtx)
1462 if (XEXP (condition, 1) == const0_rtx)
1470 /* Predict backward branches usually take, forward branches usually not. If
1471 we don't know whether this is forward or backward, assume the branch
1472 will be taken, since most are. */
1473 return (target_label == 0 || INSN_UID (jump_insn) > max_uid
1474 || INSN_UID (target_label) > max_uid
1475 || (uid_to_ruid[INSN_UID (jump_insn)]
1476 > uid_to_ruid[INSN_UID (target_label)]));;
1479 /* Return the condition under which INSN will branch to TARGET. If TARGET
1480 is zero, return the condition under which INSN will return. If INSN is
1481 an unconditional branch, return const_true_rtx. If INSN isn't a simple
1482 type of jump, or it doesn't go to TARGET, return 0. */
1485 get_branch_condition (insn, target)
1489 rtx pat = PATTERN (insn);
1492 if (condjump_in_parallel_p (insn))
1493 pat = XVECEXP (pat, 0, 0);
1495 if (GET_CODE (pat) == RETURN)
1496 return target == 0 ? const_true_rtx : 0;
1498 else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
1501 src = SET_SRC (pat);
1502 if (GET_CODE (src) == LABEL_REF && XEXP (src, 0) == target)
1503 return const_true_rtx;
1505 else if (GET_CODE (src) == IF_THEN_ELSE
1506 && ((target == 0 && GET_CODE (XEXP (src, 1)) == RETURN)
1507 || (GET_CODE (XEXP (src, 1)) == LABEL_REF
1508 && XEXP (XEXP (src, 1), 0) == target))
1509 && XEXP (src, 2) == pc_rtx)
1510 return XEXP (src, 0);
1512 else if (GET_CODE (src) == IF_THEN_ELSE
1513 && ((target == 0 && GET_CODE (XEXP (src, 2)) == RETURN)
1514 || (GET_CODE (XEXP (src, 2)) == LABEL_REF
1515 && XEXP (XEXP (src, 2), 0) == target))
1516 && XEXP (src, 1) == pc_rtx)
1517 return gen_rtx_fmt_ee (reverse_condition (GET_CODE (XEXP (src, 0))),
1518 GET_MODE (XEXP (src, 0)),
1519 XEXP (XEXP (src, 0), 0), XEXP (XEXP (src, 0), 1));
1524 /* Return non-zero if CONDITION is more strict than the condition of
1525 INSN, i.e., if INSN will always branch if CONDITION is true. */
1528 condition_dominates_p (condition, insn)
1532 rtx other_condition = get_branch_condition (insn, JUMP_LABEL (insn));
1533 enum rtx_code code = GET_CODE (condition);
1534 enum rtx_code other_code;
1536 if (rtx_equal_p (condition, other_condition)
1537 || other_condition == const_true_rtx)
1540 else if (condition == const_true_rtx || other_condition == 0)
1543 other_code = GET_CODE (other_condition);
1544 if (GET_RTX_LENGTH (code) != 2 || GET_RTX_LENGTH (other_code) != 2
1545 || ! rtx_equal_p (XEXP (condition, 0), XEXP (other_condition, 0))
1546 || ! rtx_equal_p (XEXP (condition, 1), XEXP (other_condition, 1)))
1549 return comparison_dominates_p (code, other_code);
1552 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1553 any insns already in the delay slot of JUMP. */
1556 redirect_with_delay_slots_safe_p (jump, newlabel, seq)
1557 rtx jump, newlabel, seq;
1560 rtx pat = PATTERN (seq);
1562 /* Make sure all the delay slots of this jump would still
1563 be valid after threading the jump. If they are still
1564 valid, then return non-zero. */
1566 flags = get_jump_flags (jump, newlabel);
1567 for (i = 1; i < XVECLEN (pat, 0); i++)
1569 #ifdef ANNUL_IFFALSE_SLOTS
1570 (INSN_ANNULLED_BRANCH_P (jump)
1571 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1572 ? eligible_for_annul_false (jump, i - 1,
1573 XVECEXP (pat, 0, i), flags) :
1575 #ifdef ANNUL_IFTRUE_SLOTS
1576 (INSN_ANNULLED_BRANCH_P (jump)
1577 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1578 ? eligible_for_annul_true (jump, i - 1,
1579 XVECEXP (pat, 0, i), flags) :
1581 eligible_for_delay (jump, i -1, XVECEXP (pat, 0, i), flags)))
1584 return (i == XVECLEN (pat, 0));
1587 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1588 any insns we wish to place in the delay slot of JUMP. */
1591 redirect_with_delay_list_safe_p (jump, newlabel, delay_list)
1592 rtx jump, newlabel, delay_list;
1597 /* Make sure all the insns in DELAY_LIST would still be
1598 valid after threading the jump. If they are still
1599 valid, then return non-zero. */
1601 flags = get_jump_flags (jump, newlabel);
1602 for (li = delay_list, i = 0; li; li = XEXP (li, 1), i++)
1604 #ifdef ANNUL_IFFALSE_SLOTS
1605 (INSN_ANNULLED_BRANCH_P (jump)
1606 && INSN_FROM_TARGET_P (XEXP (li, 0)))
1607 ? eligible_for_annul_false (jump, i, XEXP (li, 0), flags) :
1609 #ifdef ANNUL_IFTRUE_SLOTS
1610 (INSN_ANNULLED_BRANCH_P (jump)
1611 && ! INSN_FROM_TARGET_P (XEXP (li, 0)))
1612 ? eligible_for_annul_true (jump, i, XEXP (li, 0), flags) :
1614 eligible_for_delay (jump, i, XEXP (li, 0), flags)))
1617 return (li == NULL);
1621 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1622 the condition tested by INSN is CONDITION and the resources shown in
1623 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1624 from SEQ's delay list, in addition to whatever insns it may execute
1625 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1626 needed while searching for delay slot insns. Return the concatenated
1627 delay list if possible, otherwise, return 0.
1629 SLOTS_TO_FILL is the total number of slots required by INSN, and
1630 PSLOTS_FILLED points to the number filled so far (also the number of
1631 insns in DELAY_LIST). It is updated with the number that have been
1632 filled from the SEQUENCE, if any.
1634 PANNUL_P points to a non-zero value if we already know that we need
1635 to annul INSN. If this routine determines that annulling is needed,
1636 it may set that value non-zero.
1638 PNEW_THREAD points to a location that is to receive the place at which
1639 execution should continue. */
1642 steal_delay_list_from_target (insn, condition, seq, delay_list,
1643 sets, needed, other_needed,
1644 slots_to_fill, pslots_filled, pannul_p,
1646 rtx insn, condition;
1649 struct resources *sets, *needed, *other_needed;
1656 int slots_remaining = slots_to_fill - *pslots_filled;
1657 int total_slots_filled = *pslots_filled;
1658 rtx new_delay_list = 0;
1659 int must_annul = *pannul_p;
1662 /* We can't do anything if there are more delay slots in SEQ than we
1663 can handle, or if we don't know that it will be a taken branch.
1664 We know that it will be a taken branch if it is either an unconditional
1665 branch or a conditional branch with a stricter branch condition.
1667 Also, exit if the branch has more than one set, since then it is computing
1668 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1669 ??? It may be possible to move other sets into INSN in addition to
1670 moving the instructions in the delay slots. */
1672 if (XVECLEN (seq, 0) - 1 > slots_remaining
1673 || ! condition_dominates_p (condition, XVECEXP (seq, 0, 0))
1674 || ! single_set (XVECEXP (seq, 0, 0)))
1677 for (i = 1; i < XVECLEN (seq, 0); i++)
1679 rtx trial = XVECEXP (seq, 0, i);
1682 if (insn_references_resource_p (trial, sets, 0)
1683 || insn_sets_resource_p (trial, needed, 0)
1684 || insn_sets_resource_p (trial, sets, 0)
1686 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1688 || find_reg_note (trial, REG_CC_USER, NULL_RTX)
1690 /* If TRIAL is from the fallthrough code of an annulled branch insn
1691 in SEQ, we cannot use it. */
1692 || (INSN_ANNULLED_BRANCH_P (XVECEXP (seq, 0, 0))
1693 && ! INSN_FROM_TARGET_P (trial)))
1696 /* If this insn was already done (usually in a previous delay slot),
1697 pretend we put it in our delay slot. */
1698 if (redundant_insn (trial, insn, new_delay_list))
1701 /* We will end up re-vectoring this branch, so compute flags
1702 based on jumping to the new label. */
1703 flags = get_jump_flags (insn, JUMP_LABEL (XVECEXP (seq, 0, 0)));
1706 && ((condition == const_true_rtx
1707 || (! insn_sets_resource_p (trial, other_needed, 0)
1708 && ! may_trap_p (PATTERN (trial)))))
1709 ? eligible_for_delay (insn, total_slots_filled, trial, flags)
1711 eligible_for_annul_false (insn, total_slots_filled, trial, flags)))
1713 temp = copy_rtx (trial);
1714 INSN_FROM_TARGET_P (temp) = 1;
1715 new_delay_list = add_to_delay_list (temp, new_delay_list);
1716 total_slots_filled++;
1718 if (--slots_remaining == 0)
1725 /* Show the place to which we will be branching. */
1726 *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));
1728 /* Add any new insns to the delay list and update the count of the
1729 number of slots filled. */
1730 *pslots_filled = total_slots_filled;
1731 *pannul_p = must_annul;
1733 if (delay_list == 0)
1734 return new_delay_list;
1736 for (temp = new_delay_list; temp; temp = XEXP (temp, 1))
1737 delay_list = add_to_delay_list (XEXP (temp, 0), delay_list);
1742 /* Similar to steal_delay_list_from_target except that SEQ is on the
1743 fallthrough path of INSN. Here we only do something if the delay insn
1744 of SEQ is an unconditional branch. In that case we steal its delay slot
1745 for INSN since unconditional branches are much easier to fill. */
1748 steal_delay_list_from_fallthrough (insn, condition, seq,
1749 delay_list, sets, needed, other_needed,
1750 slots_to_fill, pslots_filled, pannul_p)
1751 rtx insn, condition;
1754 struct resources *sets, *needed, *other_needed;
1762 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1764 /* We can't do anything if SEQ's delay insn isn't an
1765 unconditional branch. */
1767 if (! simplejump_p (XVECEXP (seq, 0, 0))
1768 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN)
1771 for (i = 1; i < XVECLEN (seq, 0); i++)
1773 rtx trial = XVECEXP (seq, 0, i);
1775 /* If TRIAL sets CC0, stealing it will move it too far from the use
1777 if (insn_references_resource_p (trial, sets, 0)
1778 || insn_sets_resource_p (trial, needed, 0)
1779 || insn_sets_resource_p (trial, sets, 0)
1781 || sets_cc0_p (PATTERN (trial))
1787 /* If this insn was already done, we don't need it. */
1788 if (redundant_insn (trial, insn, delay_list))
1790 delete_from_delay_slot (trial);
1795 && ((condition == const_true_rtx
1796 || (! insn_sets_resource_p (trial, other_needed, 0)
1797 && ! may_trap_p (PATTERN (trial)))))
1798 ? eligible_for_delay (insn, *pslots_filled, trial, flags)
1800 eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
1802 delete_from_delay_slot (trial);
1803 delay_list = add_to_delay_list (trial, delay_list);
1805 if (++(*pslots_filled) == slots_to_fill)
1815 /* Try merging insns starting at THREAD which match exactly the insns in
1818 If all insns were matched and the insn was previously annulling, the
1819 annul bit will be cleared.
1821 For each insn that is merged, if the branch is or will be non-annulling,
1822 we delete the merged insn. */
1825 try_merge_delay_insns (insn, thread)
1828 rtx trial, next_trial;
1829 rtx delay_insn = XVECEXP (PATTERN (insn), 0, 0);
1830 int annul_p = INSN_ANNULLED_BRANCH_P (delay_insn);
1831 int slot_number = 1;
1832 int num_slots = XVECLEN (PATTERN (insn), 0);
1833 rtx next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1834 struct resources set, needed;
1835 rtx merged_insns = 0;
1839 flags = get_jump_flags (delay_insn, JUMP_LABEL (delay_insn));
1841 CLEAR_RESOURCE (&needed);
1842 CLEAR_RESOURCE (&set);
1844 /* If this is not an annulling branch, take into account anything needed in
1845 NEXT_TO_MATCH. This prevents two increments from being incorrectly
1846 folded into one. If we are annulling, this would be the correct
1847 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1848 will essentially disable this optimization. This method is somewhat of
1849 a kludge, but I don't see a better way.) */
1851 mark_referenced_resources (next_to_match, &needed, 1);
1853 for (trial = thread; !stop_search_p (trial, 1); trial = next_trial)
1855 rtx pat = PATTERN (trial);
1856 rtx oldtrial = trial;
1858 next_trial = next_nonnote_insn (trial);
1860 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1861 if (GET_CODE (trial) == INSN
1862 && (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER))
1865 if (GET_CODE (next_to_match) == GET_CODE (trial)
1867 /* We can't share an insn that sets cc0. */
1868 && ! sets_cc0_p (pat)
1870 && ! insn_references_resource_p (trial, &set, 1)
1871 && ! insn_sets_resource_p (trial, &set, 1)
1872 && ! insn_sets_resource_p (trial, &needed, 1)
1873 && (trial = try_split (pat, trial, 0)) != 0
1874 /* Update next_trial, in case try_split succeeded. */
1875 && (next_trial = next_nonnote_insn (trial))
1876 /* Likewise THREAD. */
1877 && (thread = oldtrial == thread ? trial : thread)
1878 && rtx_equal_p (PATTERN (next_to_match), PATTERN (trial))
1879 /* Have to test this condition if annul condition is different
1880 from (and less restrictive than) non-annulling one. */
1881 && eligible_for_delay (delay_insn, slot_number - 1, trial, flags))
1886 update_block (trial, thread);
1887 if (trial == thread)
1888 thread = next_active_insn (thread);
1890 delete_insn (trial);
1891 INSN_FROM_TARGET_P (next_to_match) = 0;
1894 merged_insns = gen_rtx_INSN_LIST (VOIDmode, trial, merged_insns);
1896 if (++slot_number == num_slots)
1899 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1901 mark_referenced_resources (next_to_match, &needed, 1);
1904 mark_set_resources (trial, &set, 0, 1);
1905 mark_referenced_resources (trial, &needed, 1);
1908 /* See if we stopped on a filled insn. If we did, try to see if its
1909 delay slots match. */
1910 if (slot_number != num_slots
1911 && trial && GET_CODE (trial) == INSN
1912 && GET_CODE (PATTERN (trial)) == SEQUENCE
1913 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (PATTERN (trial), 0, 0)))
1915 rtx pat = PATTERN (trial);
1916 rtx filled_insn = XVECEXP (pat, 0, 0);
1918 /* Account for resources set/needed by the filled insn. */
1919 mark_set_resources (filled_insn, &set, 0, 1);
1920 mark_referenced_resources (filled_insn, &needed, 1);
1922 for (i = 1; i < XVECLEN (pat, 0); i++)
1924 rtx dtrial = XVECEXP (pat, 0, i);
1926 if (! insn_references_resource_p (dtrial, &set, 1)
1927 && ! insn_sets_resource_p (dtrial, &set, 1)
1928 && ! insn_sets_resource_p (dtrial, &needed, 1)
1930 && ! sets_cc0_p (PATTERN (dtrial))
1932 && rtx_equal_p (PATTERN (next_to_match), PATTERN (dtrial))
1933 && eligible_for_delay (delay_insn, slot_number - 1, dtrial, flags))
1937 update_block (dtrial, thread);
1938 delete_from_delay_slot (dtrial);
1939 INSN_FROM_TARGET_P (next_to_match) = 0;
1942 merged_insns = gen_rtx_INSN_LIST (SImode, dtrial,
1945 if (++slot_number == num_slots)
1948 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1953 /* If all insns in the delay slot have been matched and we were previously
1954 annulling the branch, we need not any more. In that case delete all the
1955 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn the
1956 the delay list so that we know that it isn't only being used at the
1958 if (slot_number == num_slots && annul_p)
1960 for (; merged_insns; merged_insns = XEXP (merged_insns, 1))
1962 if (GET_MODE (merged_insns) == SImode)
1964 update_block (XEXP (merged_insns, 0), thread);
1965 delete_from_delay_slot (XEXP (merged_insns, 0));
1969 update_block (XEXP (merged_insns, 0), thread);
1970 delete_insn (XEXP (merged_insns, 0));
1974 INSN_ANNULLED_BRANCH_P (delay_insn) = 0;
1976 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1977 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) = 0;
1981 /* See if INSN is redundant with an insn in front of TARGET. Often this
1982 is called when INSN is a candidate for a delay slot of TARGET.
1983 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1984 of INSN. Often INSN will be redundant with an insn in a delay slot of
1985 some previous insn. This happens when we have a series of branches to the
1986 same label; in that case the first insn at the target might want to go
1987 into each of the delay slots.
1989 If we are not careful, this routine can take up a significant fraction
1990 of the total compilation time (4%), but only wins rarely. Hence we
1991 speed this routine up by making two passes. The first pass goes back
1992 until it hits a label and sees if it find an insn with an identical
1993 pattern. Only in this (relatively rare) event does it check for
1996 We do not split insns we encounter. This could cause us not to find a
1997 redundant insn, but the cost of splitting seems greater than the possible
1998 gain in rare cases. */
2001 redundant_insn (insn, target, delay_list)
2006 rtx target_main = target;
2007 rtx ipat = PATTERN (insn);
2009 struct resources needed, set;
2012 /* If INSN has any REG_UNUSED notes, it can't match anything since we
2013 are allowed to not actually assign to such a register. */
2014 if (find_reg_note (insn, REG_UNUSED, NULL_RTX) != 0)
2017 /* Scan backwards looking for a match. */
2018 for (trial = PREV_INSN (target); trial; trial = PREV_INSN (trial))
2020 if (GET_CODE (trial) == CODE_LABEL)
2023 if (GET_RTX_CLASS (GET_CODE (trial)) != 'i')
2026 pat = PATTERN (trial);
2027 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2030 if (GET_CODE (pat) == SEQUENCE)
2032 /* Stop for a CALL and its delay slots because it is difficult to
2033 track its resource needs correctly. */
2034 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
2037 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
2038 slots because it is difficult to track its resource needs
2041 #ifdef INSN_SETS_ARE_DELAYED
2042 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2046 #ifdef INSN_REFERENCES_ARE_DELAYED
2047 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2051 /* See if any of the insns in the delay slot match, updating
2052 resource requirements as we go. */
2053 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
2054 if (GET_CODE (XVECEXP (pat, 0, i)) == GET_CODE (insn)
2055 && rtx_equal_p (PATTERN (XVECEXP (pat, 0, i)), ipat)
2056 && ! find_reg_note (XVECEXP (pat, 0, i), REG_UNUSED, NULL_RTX))
2059 /* If found a match, exit this loop early. */
2064 else if (GET_CODE (trial) == GET_CODE (insn) && rtx_equal_p (pat, ipat)
2065 && ! find_reg_note (trial, REG_UNUSED, NULL_RTX))
2069 /* If we didn't find an insn that matches, return 0. */
2073 /* See what resources this insn sets and needs. If they overlap, or
2074 if this insn references CC0, it can't be redundant. */
2076 CLEAR_RESOURCE (&needed);
2077 CLEAR_RESOURCE (&set);
2078 mark_set_resources (insn, &set, 0, 1);
2079 mark_referenced_resources (insn, &needed, 1);
2081 /* If TARGET is a SEQUENCE, get the main insn. */
2082 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
2083 target_main = XVECEXP (PATTERN (target), 0, 0);
2085 if (resource_conflicts_p (&needed, &set)
2087 || reg_mentioned_p (cc0_rtx, ipat)
2089 /* The insn requiring the delay may not set anything needed or set by
2091 || insn_sets_resource_p (target_main, &needed, 1)
2092 || insn_sets_resource_p (target_main, &set, 1))
2095 /* Insns we pass may not set either NEEDED or SET, so merge them for
2097 needed.memory |= set.memory;
2098 needed.unch_memory |= set.unch_memory;
2099 IOR_HARD_REG_SET (needed.regs, set.regs);
2101 /* This insn isn't redundant if it conflicts with an insn that either is
2102 or will be in a delay slot of TARGET. */
2106 if (insn_sets_resource_p (XEXP (delay_list, 0), &needed, 1))
2108 delay_list = XEXP (delay_list, 1);
2111 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
2112 for (i = 1; i < XVECLEN (PATTERN (target), 0); i++)
2113 if (insn_sets_resource_p (XVECEXP (PATTERN (target), 0, i), &needed, 1))
2116 /* Scan backwards until we reach a label or an insn that uses something
2117 INSN sets or sets something insn uses or sets. */
2119 for (trial = PREV_INSN (target);
2120 trial && GET_CODE (trial) != CODE_LABEL;
2121 trial = PREV_INSN (trial))
2123 if (GET_CODE (trial) != INSN && GET_CODE (trial) != CALL_INSN
2124 && GET_CODE (trial) != JUMP_INSN)
2127 pat = PATTERN (trial);
2128 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2131 if (GET_CODE (pat) == SEQUENCE)
2133 /* If this is a CALL_INSN and its delay slots, it is hard to track
2134 the resource needs properly, so give up. */
2135 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
2138 /* If this this is an INSN or JUMP_INSN with delayed effects, it
2139 is hard to track the resource needs properly, so give up. */
2141 #ifdef INSN_SETS_ARE_DELAYED
2142 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2146 #ifdef INSN_REFERENCES_ARE_DELAYED
2147 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
2151 /* See if any of the insns in the delay slot match, updating
2152 resource requirements as we go. */
2153 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
2155 rtx candidate = XVECEXP (pat, 0, i);
2157 /* If an insn will be annulled if the branch is false, it isn't
2158 considered as a possible duplicate insn. */
2159 if (rtx_equal_p (PATTERN (candidate), ipat)
2160 && ! (INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2161 && INSN_FROM_TARGET_P (candidate)))
2163 /* Show that this insn will be used in the sequel. */
2164 INSN_FROM_TARGET_P (candidate) = 0;
2168 /* Unless this is an annulled insn from the target of a branch,
2169 we must stop if it sets anything needed or set by INSN. */
2170 if ((! INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2171 || ! INSN_FROM_TARGET_P (candidate))
2172 && insn_sets_resource_p (candidate, &needed, 1))
2177 /* If the insn requiring the delay slot conflicts with INSN, we
2179 if (insn_sets_resource_p (XVECEXP (pat, 0, 0), &needed, 1))
2184 /* See if TRIAL is the same as INSN. */
2185 pat = PATTERN (trial);
2186 if (rtx_equal_p (pat, ipat))
2189 /* Can't go any further if TRIAL conflicts with INSN. */
2190 if (insn_sets_resource_p (trial, &needed, 1))
2198 /* Return 1 if THREAD can only be executed in one way. If LABEL is non-zero,
2199 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
2200 is non-zero, we are allowed to fall into this thread; otherwise, we are
2203 If LABEL is used more than one or we pass a label other than LABEL before
2204 finding an active insn, we do not own this thread. */
2207 own_thread_p (thread, label, allow_fallthrough)
2210 int allow_fallthrough;
2215 /* We don't own the function end. */
2219 /* Get the first active insn, or THREAD, if it is an active insn. */
2220 active_insn = next_active_insn (PREV_INSN (thread));
2222 for (insn = thread; insn != active_insn; insn = NEXT_INSN (insn))
2223 if (GET_CODE (insn) == CODE_LABEL
2224 && (insn != label || LABEL_NUSES (insn) != 1))
2227 if (allow_fallthrough)
2230 /* Ensure that we reach a BARRIER before any insn or label. */
2231 for (insn = prev_nonnote_insn (thread);
2232 insn == 0 || GET_CODE (insn) != BARRIER;
2233 insn = prev_nonnote_insn (insn))
2235 || GET_CODE (insn) == CODE_LABEL
2236 || (GET_CODE (insn) == INSN
2237 && GET_CODE (PATTERN (insn)) != USE
2238 && GET_CODE (PATTERN (insn)) != CLOBBER))
2244 /* Find the number of the basic block that starts closest to INSN. Return -1
2245 if we couldn't find such a basic block. */
2248 find_basic_block (insn)
2253 /* Scan backwards to the previous BARRIER. Then see if we can find a
2254 label that starts a basic block. Return the basic block number. */
2256 for (insn = prev_nonnote_insn (insn);
2257 insn && GET_CODE (insn) != BARRIER;
2258 insn = prev_nonnote_insn (insn))
2261 /* The start of the function is basic block zero. */
2265 /* See if any of the upcoming CODE_LABELs start a basic block. If we reach
2266 anything other than a CODE_LABEL or note, we can't find this code. */
2267 for (insn = next_nonnote_insn (insn);
2268 insn && GET_CODE (insn) == CODE_LABEL;
2269 insn = next_nonnote_insn (insn))
2271 for (i = 0; i < n_basic_blocks; i++)
2272 if (insn == basic_block_head[i])
2279 /* Called when INSN is being moved from a location near the target of a jump.
2280 We leave a marker of the form (use (INSN)) immediately in front
2281 of WHERE for mark_target_live_regs. These markers will be deleted when
2284 We used to try to update the live status of registers if WHERE is at
2285 the start of a basic block, but that can't work since we may remove a
2286 BARRIER in relax_delay_slots. */
2289 update_block (insn, where)
2295 /* Ignore if this was in a delay slot and it came from the target of
2297 if (INSN_FROM_TARGET_P (insn))
2300 emit_insn_before (gen_rtx_USE (VOIDmode, insn), where);
2302 /* INSN might be making a value live in a block where it didn't use to
2303 be. So recompute liveness information for this block. */
2305 b = find_basic_block (insn);
2310 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
2311 the basic block containing the jump. */
2314 reorg_redirect_jump (jump, nlabel)
2318 int b = find_basic_block (jump);
2323 return redirect_jump (jump, nlabel);
2326 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
2327 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
2328 that reference values used in INSN. If we find one, then we move the
2329 REG_DEAD note to INSN.
2331 This is needed to handle the case where an later insn (after INSN) has a
2332 REG_DEAD note for a register used by INSN, and this later insn subsequently
2333 gets moved before a CODE_LABEL because it is a redundant insn. In this
2334 case, mark_target_live_regs may be confused into thinking the register
2335 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
2338 update_reg_dead_notes (insn, delayed_insn)
2339 rtx insn, delayed_insn;
2343 for (p = next_nonnote_insn (insn); p != delayed_insn;
2344 p = next_nonnote_insn (p))
2345 for (link = REG_NOTES (p); link; link = next)
2347 next = XEXP (link, 1);
2349 if (REG_NOTE_KIND (link) != REG_DEAD
2350 || GET_CODE (XEXP (link, 0)) != REG)
2353 if (reg_referenced_p (XEXP (link, 0), PATTERN (insn)))
2355 /* Move the REG_DEAD note from P to INSN. */
2356 remove_note (p, link);
2357 XEXP (link, 1) = REG_NOTES (insn);
2358 REG_NOTES (insn) = link;
2363 /* Called when an insn redundant with start_insn is deleted. If there
2364 is a REG_DEAD note for the target of start_insn between start_insn
2365 and stop_insn, then the REG_DEAD note needs to be deleted since the
2366 value no longer dies there.
2368 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
2369 confused into thinking the register is dead. */
2372 fix_reg_dead_note (start_insn, stop_insn)
2373 rtx start_insn, stop_insn;
2377 for (p = next_nonnote_insn (start_insn); p != stop_insn;
2378 p = next_nonnote_insn (p))
2379 for (link = REG_NOTES (p); link; link = next)
2381 next = XEXP (link, 1);
2383 if (REG_NOTE_KIND (link) != REG_DEAD
2384 || GET_CODE (XEXP (link, 0)) != REG)
2387 if (reg_set_p (XEXP (link, 0), PATTERN (start_insn)))
2389 remove_note (p, link);
2395 /* Delete any REG_UNUSED notes that exist on INSN but not on REDUNDANT_INSN.
2397 This handles the case of udivmodXi4 instructions which optimize their
2398 output depending on whether any REG_UNUSED notes are present.
2399 we must make sure that INSN calculates as many results as REDUNDANT_INSN
2403 update_reg_unused_notes (insn, redundant_insn)
2404 rtx insn, redundant_insn;
2408 for (link = REG_NOTES (insn); link; link = next)
2410 next = XEXP (link, 1);
2412 if (REG_NOTE_KIND (link) != REG_UNUSED
2413 || GET_CODE (XEXP (link, 0)) != REG)
2416 if (! find_regno_note (redundant_insn, REG_UNUSED,
2417 REGNO (XEXP (link, 0))))
2418 remove_note (insn, link);
2422 /* Marks registers possibly live at the current place being scanned by
2423 mark_target_live_regs. Used only by next two function. */
2425 static HARD_REG_SET current_live_regs;
2427 /* Marks registers for which we have seen a REG_DEAD note but no assignment.
2428 Also only used by the next two functions. */
2430 static HARD_REG_SET pending_dead_regs;
2432 /* Utility function called from mark_target_live_regs via note_stores.
2433 It deadens any CLOBBERed registers and livens any SET registers. */
2436 update_live_status (dest, x)
2440 int first_regno, last_regno;
2443 if (GET_CODE (dest) != REG
2444 && (GET_CODE (dest) != SUBREG || GET_CODE (SUBREG_REG (dest)) != REG))
2447 if (GET_CODE (dest) == SUBREG)
2448 first_regno = REGNO (SUBREG_REG (dest)) + SUBREG_WORD (dest);
2450 first_regno = REGNO (dest);
2452 last_regno = first_regno + HARD_REGNO_NREGS (first_regno, GET_MODE (dest));
2454 if (GET_CODE (x) == CLOBBER)
2455 for (i = first_regno; i < last_regno; i++)
2456 CLEAR_HARD_REG_BIT (current_live_regs, i);
2458 for (i = first_regno; i < last_regno; i++)
2460 SET_HARD_REG_BIT (current_live_regs, i);
2461 CLEAR_HARD_REG_BIT (pending_dead_regs, i);
2465 /* Similar to next_insn, but ignores insns in the delay slots of
2466 an annulled branch. */
2469 next_insn_no_annul (insn)
2474 /* If INSN is an annulled branch, skip any insns from the target
2476 if (INSN_ANNULLED_BRANCH_P (insn)
2477 && NEXT_INSN (PREV_INSN (insn)) != insn)
2478 while (INSN_FROM_TARGET_P (NEXT_INSN (insn)))
2479 insn = NEXT_INSN (insn);
2481 insn = NEXT_INSN (insn);
2482 if (insn && GET_CODE (insn) == INSN
2483 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2484 insn = XVECEXP (PATTERN (insn), 0, 0);
2490 /* A subroutine of mark_target_live_regs. Search forward from TARGET
2491 looking for registers that are set before they are used. These are dead.
2492 Stop after passing a few conditional jumps, and/or a small
2493 number of unconditional branches. */
2496 find_dead_or_set_registers (target, res, jump_target, jump_count, set, needed)
2498 struct resources *res;
2501 struct resources set, needed;
2503 HARD_REG_SET scratch;
2508 for (insn = target; insn; insn = next)
2510 rtx this_jump_insn = insn;
2512 next = NEXT_INSN (insn);
2513 switch (GET_CODE (insn))
2516 /* After a label, any pending dead registers that weren't yet
2517 used can be made dead. */
2518 AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs);
2519 AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs);
2520 CLEAR_HARD_REG_SET (pending_dead_regs);
2522 if (CODE_LABEL_NUMBER (insn) < max_label_num_after_reload)
2524 /* All spill registers are dead at a label, so kill all of the
2525 ones that aren't needed also. */
2526 COPY_HARD_REG_SET (scratch, used_spill_regs);
2527 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2528 AND_COMPL_HARD_REG_SET (res->regs, scratch);
2537 if (GET_CODE (PATTERN (insn)) == USE)
2539 /* If INSN is a USE made by update_block, we care about the
2540 underlying insn. Any registers set by the underlying insn
2541 are live since the insn is being done somewhere else. */
2542 if (GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2543 mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, 1);
2545 /* All other USE insns are to be ignored. */
2548 else if (GET_CODE (PATTERN (insn)) == CLOBBER)
2550 else if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2552 /* An unconditional jump can be used to fill the delay slot
2553 of a call, so search for a JUMP_INSN in any position. */
2554 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
2556 this_jump_insn = XVECEXP (PATTERN (insn), 0, i);
2557 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2566 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2568 if (jump_count++ < 10)
2570 if (simplejump_p (this_jump_insn)
2571 || GET_CODE (PATTERN (this_jump_insn)) == RETURN)
2573 next = JUMP_LABEL (this_jump_insn);
2578 *jump_target = JUMP_LABEL (this_jump_insn);
2581 else if (condjump_p (this_jump_insn)
2582 || condjump_in_parallel_p (this_jump_insn))
2584 struct resources target_set, target_res;
2585 struct resources fallthrough_res;
2587 /* We can handle conditional branches here by following
2588 both paths, and then IOR the results of the two paths
2589 together, which will give us registers that are dead
2590 on both paths. Since this is expensive, we give it
2591 a much higher cost than unconditional branches. The
2592 cost was chosen so that we will follow at most 1
2593 conditional branch. */
2596 if (jump_count >= 10)
2599 mark_referenced_resources (insn, &needed, 1);
2601 /* For an annulled branch, mark_set_resources ignores slots
2602 filled by instructions from the target. This is correct
2603 if the branch is not taken. Since we are following both
2604 paths from the branch, we must also compute correct info
2605 if the branch is taken. We do this by inverting all of
2606 the INSN_FROM_TARGET_P bits, calling mark_set_resources,
2607 and then inverting the INSN_FROM_TARGET_P bits again. */
2609 if (GET_CODE (PATTERN (insn)) == SEQUENCE
2610 && INSN_ANNULLED_BRANCH_P (this_jump_insn))
2612 for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
2613 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i))
2614 = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i));
2617 mark_set_resources (insn, &target_set, 0, 1);
2619 for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
2620 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i))
2621 = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i));
2623 mark_set_resources (insn, &set, 0, 1);
2627 mark_set_resources (insn, &set, 0, 1);
2632 COPY_HARD_REG_SET (scratch, target_set.regs);
2633 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2634 AND_COMPL_HARD_REG_SET (target_res.regs, scratch);
2636 fallthrough_res = *res;
2637 COPY_HARD_REG_SET (scratch, set.regs);
2638 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2639 AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch);
2641 find_dead_or_set_registers (JUMP_LABEL (this_jump_insn),
2642 &target_res, 0, jump_count,
2643 target_set, needed);
2644 find_dead_or_set_registers (next,
2645 &fallthrough_res, 0, jump_count,
2647 IOR_HARD_REG_SET (fallthrough_res.regs, target_res.regs);
2648 AND_HARD_REG_SET (res->regs, fallthrough_res.regs);
2656 /* Don't try this optimization if we expired our jump count
2657 above, since that would mean there may be an infinite loop
2658 in the function being compiled. */
2664 mark_referenced_resources (insn, &needed, 1);
2665 mark_set_resources (insn, &set, 0, 1);
2667 COPY_HARD_REG_SET (scratch, set.regs);
2668 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2669 AND_COMPL_HARD_REG_SET (res->regs, scratch);
2675 /* Set the resources that are live at TARGET.
2677 If TARGET is zero, we refer to the end of the current function and can
2678 return our precomputed value.
2680 Otherwise, we try to find out what is live by consulting the basic block
2681 information. This is tricky, because we must consider the actions of
2682 reload and jump optimization, which occur after the basic block information
2685 Accordingly, we proceed as follows::
2687 We find the previous BARRIER and look at all immediately following labels
2688 (with no intervening active insns) to see if any of them start a basic
2689 block. If we hit the start of the function first, we use block 0.
2691 Once we have found a basic block and a corresponding first insns, we can
2692 accurately compute the live status from basic_block_live_regs and
2693 reg_renumber. (By starting at a label following a BARRIER, we are immune
2694 to actions taken by reload and jump.) Then we scan all insns between
2695 that point and our target. For each CLOBBER (or for call-clobbered regs
2696 when we pass a CALL_INSN), mark the appropriate registers are dead. For
2697 a SET, mark them as live.
2699 We have to be careful when using REG_DEAD notes because they are not
2700 updated by such things as find_equiv_reg. So keep track of registers
2701 marked as dead that haven't been assigned to, and mark them dead at the
2702 next CODE_LABEL since reload and jump won't propagate values across labels.
2704 If we cannot find the start of a basic block (should be a very rare
2705 case, if it can happen at all), mark everything as potentially live.
2707 Next, scan forward from TARGET looking for things set or clobbered
2708 before they are used. These are not live.
2710 Because we can be called many times on the same target, save our results
2711 in a hash table indexed by INSN_UID. */
2714 mark_target_live_regs (target, res)
2716 struct resources *res;
2720 struct target_info *tinfo;
2724 HARD_REG_SET scratch;
2725 struct resources set, needed;
2727 /* Handle end of function. */
2730 *res = end_of_function_needs;
2734 /* We have to assume memory is needed, but the CC isn't. */
2736 res->volatil = res->unch_memory = 0;
2739 /* See if we have computed this value already. */
2740 for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2741 tinfo; tinfo = tinfo->next)
2742 if (tinfo->uid == INSN_UID (target))
2745 /* Start by getting the basic block number. If we have saved information,
2746 we can get it from there unless the insn at the start of the basic block
2747 has been deleted. */
2748 if (tinfo && tinfo->block != -1
2749 && ! INSN_DELETED_P (basic_block_head[tinfo->block]))
2753 b = find_basic_block (target);
2757 /* If the information is up-to-date, use it. Otherwise, we will
2759 if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b])
2761 COPY_HARD_REG_SET (res->regs, tinfo->live_regs);
2767 /* Allocate a place to put our results and chain it into the
2769 tinfo = (struct target_info *) oballoc (sizeof (struct target_info));
2770 tinfo->uid = INSN_UID (target);
2772 tinfo->next = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2773 target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo;
2776 CLEAR_HARD_REG_SET (pending_dead_regs);
2778 /* If we found a basic block, get the live registers from it and update
2779 them with anything set or killed between its start and the insn before
2780 TARGET. Otherwise, we must assume everything is live. */
2783 regset regs_live = basic_block_live_at_start[b];
2786 rtx start_insn, stop_insn;
2788 /* Compute hard regs live at start of block -- this is the real hard regs
2789 marked live, plus live pseudo regs that have been renumbered to
2792 REG_SET_TO_HARD_REG_SET (current_live_regs, regs_live);
2794 EXECUTE_IF_SET_IN_REG_SET
2795 (regs_live, FIRST_PSEUDO_REGISTER, i,
2797 if ((regno = reg_renumber[i]) >= 0)
2799 j < regno + HARD_REGNO_NREGS (regno,
2800 PSEUDO_REGNO_MODE (i));
2802 SET_HARD_REG_BIT (current_live_regs, j);
2805 /* Get starting and ending insn, handling the case where each might
2807 start_insn = (b == 0 ? get_insns () : basic_block_head[b]);
2810 if (GET_CODE (start_insn) == INSN
2811 && GET_CODE (PATTERN (start_insn)) == SEQUENCE)
2812 start_insn = XVECEXP (PATTERN (start_insn), 0, 0);
2814 if (GET_CODE (stop_insn) == INSN
2815 && GET_CODE (PATTERN (stop_insn)) == SEQUENCE)
2816 stop_insn = next_insn (PREV_INSN (stop_insn));
2818 for (insn = start_insn; insn != stop_insn;
2819 insn = next_insn_no_annul (insn))
2822 rtx real_insn = insn;
2824 /* If this insn is from the target of a branch, it isn't going to
2825 be used in the sequel. If it is used in both cases, this
2826 test will not be true. */
2827 if (INSN_FROM_TARGET_P (insn))
2830 /* If this insn is a USE made by update_block, we care about the
2832 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
2833 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2834 real_insn = XEXP (PATTERN (insn), 0);
2836 if (GET_CODE (real_insn) == CALL_INSN)
2838 /* CALL clobbers all call-used regs that aren't fixed except
2839 sp, ap, and fp. Do this before setting the result of the
2841 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2842 if (call_used_regs[i]
2843 && i != STACK_POINTER_REGNUM && i != FRAME_POINTER_REGNUM
2844 && i != ARG_POINTER_REGNUM
2845 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2846 && i != HARD_FRAME_POINTER_REGNUM
2848 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2849 && ! (i == ARG_POINTER_REGNUM && fixed_regs[i])
2851 #ifdef PIC_OFFSET_TABLE_REGNUM
2852 && ! (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
2855 CLEAR_HARD_REG_BIT (current_live_regs, i);
2857 /* A CALL_INSN sets any global register live, since it may
2858 have been modified by the call. */
2859 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2861 SET_HARD_REG_BIT (current_live_regs, i);
2864 /* Mark anything killed in an insn to be deadened at the next
2865 label. Ignore USE insns; the only REG_DEAD notes will be for
2866 parameters. But they might be early. A CALL_INSN will usually
2867 clobber registers used for parameters. It isn't worth bothering
2868 with the unlikely case when it won't. */
2869 if ((GET_CODE (real_insn) == INSN
2870 && GET_CODE (PATTERN (real_insn)) != USE
2871 && GET_CODE (PATTERN (real_insn)) != CLOBBER)
2872 || GET_CODE (real_insn) == JUMP_INSN
2873 || GET_CODE (real_insn) == CALL_INSN)
2875 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2876 if (REG_NOTE_KIND (link) == REG_DEAD
2877 && GET_CODE (XEXP (link, 0)) == REG
2878 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2880 int first_regno = REGNO (XEXP (link, 0));
2883 + HARD_REGNO_NREGS (first_regno,
2884 GET_MODE (XEXP (link, 0))));
2886 for (i = first_regno; i < last_regno; i++)
2887 SET_HARD_REG_BIT (pending_dead_regs, i);
2890 note_stores (PATTERN (real_insn), update_live_status);
2892 /* If any registers were unused after this insn, kill them.
2893 These notes will always be accurate. */
2894 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2895 if (REG_NOTE_KIND (link) == REG_UNUSED
2896 && GET_CODE (XEXP (link, 0)) == REG
2897 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2899 int first_regno = REGNO (XEXP (link, 0));
2902 + HARD_REGNO_NREGS (first_regno,
2903 GET_MODE (XEXP (link, 0))));
2905 for (i = first_regno; i < last_regno; i++)
2906 CLEAR_HARD_REG_BIT (current_live_regs, i);
2910 else if (GET_CODE (real_insn) == CODE_LABEL)
2912 /* A label clobbers the pending dead registers since neither
2913 reload nor jump will propagate a value across a label. */
2914 AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs);
2915 CLEAR_HARD_REG_SET (pending_dead_regs);
2918 /* The beginning of the epilogue corresponds to the end of the
2919 RTL chain when there are no epilogue insns. Certain resources
2920 are implicitly required at that point. */
2921 else if (GET_CODE (real_insn) == NOTE
2922 && NOTE_LINE_NUMBER (real_insn) == NOTE_INSN_EPILOGUE_BEG)
2923 IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs);
2926 COPY_HARD_REG_SET (res->regs, current_live_regs);
2928 tinfo->bb_tick = bb_ticks[b];
2931 /* We didn't find the start of a basic block. Assume everything
2932 in use. This should happen only extremely rarely. */
2933 SET_HARD_REG_SET (res->regs);
2935 CLEAR_RESOURCE (&set);
2936 CLEAR_RESOURCE (&needed);
2938 jump_insn = find_dead_or_set_registers (target, res, &jump_target, 0,
2941 /* If we hit an unconditional branch, we have another way of finding out
2942 what is live: we can see what is live at the branch target and include
2943 anything used but not set before the branch. The only things that are
2944 live are those that are live using the above test and the test below. */
2948 struct resources new_resources;
2949 rtx stop_insn = next_active_insn (jump_insn);
2951 mark_target_live_regs (next_active_insn (jump_target), &new_resources);
2952 CLEAR_RESOURCE (&set);
2953 CLEAR_RESOURCE (&needed);
2955 /* Include JUMP_INSN in the needed registers. */
2956 for (insn = target; insn != stop_insn; insn = next_active_insn (insn))
2958 mark_referenced_resources (insn, &needed, 1);
2960 COPY_HARD_REG_SET (scratch, needed.regs);
2961 AND_COMPL_HARD_REG_SET (scratch, set.regs);
2962 IOR_HARD_REG_SET (new_resources.regs, scratch);
2964 mark_set_resources (insn, &set, 0, 1);
2967 AND_HARD_REG_SET (res->regs, new_resources.regs);
2970 COPY_HARD_REG_SET (tinfo->live_regs, res->regs);
2973 /* Scan a function looking for insns that need a delay slot and find insns to
2974 put into the delay slot.
2976 NON_JUMPS_P is non-zero if we are to only try to fill non-jump insns (such
2977 as calls). We do these first since we don't want jump insns (that are
2978 easier to fill) to get the only insns that could be used for non-jump insns.
2979 When it is zero, only try to fill JUMP_INSNs.
2981 When slots are filled in this manner, the insns (including the
2982 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
2983 it is possible to tell whether a delay slot has really been filled
2984 or not. `final' knows how to deal with this, by communicating
2985 through FINAL_SEQUENCE. */
2988 fill_simple_delay_slots (non_jumps_p)
2991 register rtx insn, pat, trial, next_trial;
2993 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
2994 struct resources needed, set;
2995 int slots_to_fill, slots_filled;
2998 for (i = 0; i < num_unfilled_slots; i++)
3001 /* Get the next insn to fill. If it has already had any slots assigned,
3002 we can't do anything with it. Maybe we'll improve this later. */
3004 insn = unfilled_slots_base[i];
3006 || INSN_DELETED_P (insn)
3007 || (GET_CODE (insn) == INSN
3008 && GET_CODE (PATTERN (insn)) == SEQUENCE)
3009 || (GET_CODE (insn) == JUMP_INSN && non_jumps_p)
3010 || (GET_CODE (insn) != JUMP_INSN && ! non_jumps_p))
3013 if (GET_CODE (insn) == JUMP_INSN)
3014 flags = get_jump_flags (insn, JUMP_LABEL (insn));
3016 flags = get_jump_flags (insn, NULL_RTX);
3017 slots_to_fill = num_delay_slots (insn);
3018 if (slots_to_fill == 0)
3021 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
3022 says how many. After initialization, first try optimizing
3025 nop add %o7,.-L1,%o7
3029 If this case applies, the delay slot of the call is filled with
3030 the unconditional jump. This is done first to avoid having the
3031 delay slot of the call filled in the backward scan. Also, since
3032 the unconditional jump is likely to also have a delay slot, that
3033 insn must exist when it is subsequently scanned.
3035 This is tried on each insn with delay slots as some machines
3036 have insns which perform calls, but are not represented as
3042 if ((trial = next_active_insn (insn))
3043 && GET_CODE (trial) == JUMP_INSN
3044 && simplejump_p (trial)
3045 && eligible_for_delay (insn, slots_filled, trial, flags)
3046 && no_labels_between_p (insn, trial))
3050 delay_list = add_to_delay_list (trial, delay_list);
3052 /* TRIAL may have had its delay slot filled, then unfilled. When
3053 the delay slot is unfilled, TRIAL is placed back on the unfilled
3054 slots obstack. Unfortunately, it is placed on the end of the
3055 obstack, not in its original location. Therefore, we must search
3056 from entry i + 1 to the end of the unfilled slots obstack to
3057 try and find TRIAL. */
3058 tmp = &unfilled_slots_base[i + 1];
3059 while (*tmp != trial && tmp != unfilled_slots_next)
3062 /* Remove the unconditional jump from consideration for delay slot
3063 filling and unthread it. */
3067 rtx next = NEXT_INSN (trial);
3068 rtx prev = PREV_INSN (trial);
3070 NEXT_INSN (prev) = next;
3072 PREV_INSN (next) = prev;
3076 /* Now, scan backwards from the insn to search for a potential
3077 delay-slot candidate. Stop searching when a label or jump is hit.
3079 For each candidate, if it is to go into the delay slot (moved
3080 forward in execution sequence), it must not need or set any resources
3081 that were set by later insns and must not set any resources that
3082 are needed for those insns.
3084 The delay slot insn itself sets resources unless it is a call
3085 (in which case the called routine, not the insn itself, is doing
3088 if (slots_filled < slots_to_fill)
3090 CLEAR_RESOURCE (&needed);
3091 CLEAR_RESOURCE (&set);
3092 mark_set_resources (insn, &set, 0, 0);
3093 mark_referenced_resources (insn, &needed, 0);
3095 for (trial = prev_nonnote_insn (insn); ! stop_search_p (trial, 1);
3098 next_trial = prev_nonnote_insn (trial);
3100 /* This must be an INSN or CALL_INSN. */
3101 pat = PATTERN (trial);
3103 /* USE and CLOBBER at this level was just for flow; ignore it. */
3104 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3107 /* Check for resource conflict first, to avoid unnecessary
3109 if (! insn_references_resource_p (trial, &set, 1)
3110 && ! insn_sets_resource_p (trial, &set, 1)
3111 && ! insn_sets_resource_p (trial, &needed, 1)
3113 /* Can't separate set of cc0 from its use. */
3114 && ! (reg_mentioned_p (cc0_rtx, pat)
3115 && ! sets_cc0_p (cc0_rtx, pat))
3119 trial = try_split (pat, trial, 1);
3120 next_trial = prev_nonnote_insn (trial);
3121 if (eligible_for_delay (insn, slots_filled, trial, flags))
3123 /* In this case, we are searching backward, so if we
3124 find insns to put on the delay list, we want
3125 to put them at the head, rather than the
3126 tail, of the list. */
3128 update_reg_dead_notes (trial, insn);
3129 delay_list = gen_rtx_INSN_LIST (VOIDmode,
3131 update_block (trial, trial);
3132 delete_insn (trial);
3133 if (slots_to_fill == ++slots_filled)
3139 mark_set_resources (trial, &set, 0, 1);
3140 mark_referenced_resources (trial, &needed, 1);
3144 /* If all needed slots haven't been filled, we come here. */
3146 /* Try to optimize case of jumping around a single insn. */
3147 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
3148 if (slots_filled != slots_to_fill
3150 && GET_CODE (insn) == JUMP_INSN
3151 && (condjump_p (insn) || condjump_in_parallel_p (insn)))
3153 delay_list = optimize_skip (insn);
3159 /* Try to get insns from beyond the insn needing the delay slot.
3160 These insns can neither set or reference resources set in insns being
3161 skipped, cannot set resources in the insn being skipped, and, if this
3162 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
3163 call might not return).
3165 There used to be code which continued past the target label if
3166 we saw all uses of the target label. This code did not work,
3167 because it failed to account for some instructions which were
3168 both annulled and marked as from the target. This can happen as a
3169 result of optimize_skip. Since this code was redundant with
3170 fill_eager_delay_slots anyways, it was just deleted. */
3172 if (slots_filled != slots_to_fill
3173 && (GET_CODE (insn) != JUMP_INSN
3174 || ((condjump_p (insn) || condjump_in_parallel_p (insn))
3175 && ! simplejump_p (insn)
3176 && JUMP_LABEL (insn) != 0)))
3179 int maybe_never = 0;
3180 struct resources needed_at_jump;
3182 CLEAR_RESOURCE (&needed);
3183 CLEAR_RESOURCE (&set);
3185 if (GET_CODE (insn) == CALL_INSN)
3187 mark_set_resources (insn, &set, 0, 1);
3188 mark_referenced_resources (insn, &needed, 1);
3193 mark_set_resources (insn, &set, 0, 1);
3194 mark_referenced_resources (insn, &needed, 1);
3195 if (GET_CODE (insn) == JUMP_INSN)
3196 target = JUMP_LABEL (insn);
3199 for (trial = next_nonnote_insn (insn); trial; trial = next_trial)
3201 rtx pat, trial_delay;
3203 next_trial = next_nonnote_insn (trial);
3205 if (GET_CODE (trial) == CODE_LABEL
3206 || GET_CODE (trial) == BARRIER)
3209 /* We must have an INSN, JUMP_INSN, or CALL_INSN. */
3210 pat = PATTERN (trial);
3212 /* Stand-alone USE and CLOBBER are just for flow. */
3213 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3216 /* If this already has filled delay slots, get the insn needing
3218 if (GET_CODE (pat) == SEQUENCE)
3219 trial_delay = XVECEXP (pat, 0, 0);
3221 trial_delay = trial;
3223 /* If this is a jump insn to our target, indicate that we have
3224 seen another jump to it. If we aren't handling a conditional
3225 jump, stop our search. Otherwise, compute the needs at its
3226 target and add them to NEEDED. */
3227 if (GET_CODE (trial_delay) == JUMP_INSN)
3231 else if (JUMP_LABEL (trial_delay) != target)
3233 mark_target_live_regs
3234 (next_active_insn (JUMP_LABEL (trial_delay)),
3236 needed.memory |= needed_at_jump.memory;
3237 needed.unch_memory |= needed_at_jump.unch_memory;
3238 IOR_HARD_REG_SET (needed.regs, needed_at_jump.regs);
3242 /* See if we have a resource problem before we try to
3245 && GET_CODE (pat) != SEQUENCE
3246 && ! insn_references_resource_p (trial, &set, 1)
3247 && ! insn_sets_resource_p (trial, &set, 1)
3248 && ! insn_sets_resource_p (trial, &needed, 1)
3250 && ! (reg_mentioned_p (cc0_rtx, pat) && ! sets_cc0_p (pat))
3252 && ! (maybe_never && may_trap_p (pat))
3253 && (trial = try_split (pat, trial, 0))
3254 && eligible_for_delay (insn, slots_filled, trial, flags))
3256 next_trial = next_nonnote_insn (trial);
3257 delay_list = add_to_delay_list (trial, delay_list);
3260 if (reg_mentioned_p (cc0_rtx, pat))
3261 link_cc0_insns (trial);
3264 delete_insn (trial);
3265 if (slots_to_fill == ++slots_filled)
3270 mark_set_resources (trial, &set, 0, 1);
3271 mark_referenced_resources (trial, &needed, 1);
3273 /* Ensure we don't put insns between the setting of cc and the
3274 comparison by moving a setting of cc into an earlier delay
3275 slot since these insns could clobber the condition code. */
3278 /* If this is a call or jump, we might not get here. */
3279 if (GET_CODE (trial_delay) == CALL_INSN
3280 || GET_CODE (trial_delay) == JUMP_INSN)
3284 /* If there are slots left to fill and our search was stopped by an
3285 unconditional branch, try the insn at the branch target. We can
3286 redirect the branch if it works.
3288 Don't do this if the insn at the branch target is a branch. */
3289 if (slots_to_fill != slots_filled
3291 && GET_CODE (trial) == JUMP_INSN
3292 && simplejump_p (trial)
3293 && (target == 0 || JUMP_LABEL (trial) == target)
3294 && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0
3295 && ! (GET_CODE (next_trial) == INSN
3296 && GET_CODE (PATTERN (next_trial)) == SEQUENCE)
3297 && GET_CODE (next_trial) != JUMP_INSN
3298 && ! insn_references_resource_p (next_trial, &set, 1)
3299 && ! insn_sets_resource_p (next_trial, &set, 1)
3300 && ! insn_sets_resource_p (next_trial, &needed, 1)
3302 && ! reg_mentioned_p (cc0_rtx, PATTERN (next_trial))
3304 && ! (maybe_never && may_trap_p (PATTERN (next_trial)))
3305 && (next_trial = try_split (PATTERN (next_trial), next_trial, 0))
3306 && eligible_for_delay (insn, slots_filled, next_trial, flags))
3308 rtx new_label = next_active_insn (next_trial);
3311 new_label = get_label_before (new_label);
3313 new_label = find_end_label ();
3316 = add_to_delay_list (copy_rtx (next_trial), delay_list);
3318 reorg_redirect_jump (trial, new_label);
3320 /* If we merged because we both jumped to the same place,
3321 redirect the original insn also. */
3323 reorg_redirect_jump (insn, new_label);
3327 /* If this is an unconditional jump, then try to get insns from the
3328 target of the jump. */
3329 if (GET_CODE (insn) == JUMP_INSN
3330 && simplejump_p (insn)
3331 && slots_filled != slots_to_fill)
3333 = fill_slots_from_thread (insn, const_true_rtx,
3334 next_active_insn (JUMP_LABEL (insn)),
3336 own_thread_p (JUMP_LABEL (insn),
3337 JUMP_LABEL (insn), 0),
3338 slots_to_fill, &slots_filled);
3341 unfilled_slots_base[i]
3342 = emit_delay_sequence (insn, delay_list, slots_filled);
3344 if (slots_to_fill == slots_filled)
3345 unfilled_slots_base[i] = 0;
3347 note_delay_statistics (slots_filled, 0);
3350 #ifdef DELAY_SLOTS_FOR_EPILOGUE
3351 /* See if the epilogue needs any delay slots. Try to fill them if so.
3352 The only thing we can do is scan backwards from the end of the
3353 function. If we did this in a previous pass, it is incorrect to do it
3355 if (current_function_epilogue_delay_list)
3358 slots_to_fill = DELAY_SLOTS_FOR_EPILOGUE;
3359 if (slots_to_fill == 0)
3363 CLEAR_RESOURCE (&set);
3365 /* The frame pointer and stack pointer are needed at the beginning of
3366 the epilogue, so instructions setting them can not be put in the
3367 epilogue delay slot. However, everything else needed at function
3368 end is safe, so we don't want to use end_of_function_needs here. */
3369 CLEAR_RESOURCE (&needed);
3370 if (frame_pointer_needed)
3372 SET_HARD_REG_BIT (needed.regs, FRAME_POINTER_REGNUM);
3373 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3374 SET_HARD_REG_BIT (needed.regs, HARD_FRAME_POINTER_REGNUM);
3376 #ifdef EXIT_IGNORE_STACK
3377 if (! EXIT_IGNORE_STACK)
3379 SET_HARD_REG_BIT (needed.regs, STACK_POINTER_REGNUM);
3382 SET_HARD_REG_BIT (needed.regs, STACK_POINTER_REGNUM);
3384 #ifdef EPILOGUE_USES
3385 for (i = 0; i <FIRST_PSEUDO_REGISTER; i++)
3387 if (EPILOGUE_USES (i))
3388 SET_HARD_REG_BIT (needed.regs, i);
3392 for (trial = get_last_insn (); ! stop_search_p (trial, 1);
3393 trial = PREV_INSN (trial))
3395 if (GET_CODE (trial) == NOTE)
3397 pat = PATTERN (trial);
3398 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3401 if (! insn_references_resource_p (trial, &set, 1)
3402 && ! insn_sets_resource_p (trial, &needed, 1)
3403 && ! insn_sets_resource_p (trial, &set, 1)
3405 /* Don't want to mess with cc0 here. */
3406 && ! reg_mentioned_p (cc0_rtx, pat)
3410 trial = try_split (pat, trial, 1);
3411 if (ELIGIBLE_FOR_EPILOGUE_DELAY (trial, slots_filled))
3413 /* Here as well we are searching backward, so put the
3414 insns we find on the head of the list. */
3416 current_function_epilogue_delay_list
3417 = gen_rtx_INSN_LIST (VOIDmode, trial,
3418 current_function_epilogue_delay_list);
3419 mark_referenced_resources (trial, &end_of_function_needs, 1);
3420 update_block (trial, trial);
3421 delete_insn (trial);
3423 /* Clear deleted bit so final.c will output the insn. */
3424 INSN_DELETED_P (trial) = 0;
3426 if (slots_to_fill == ++slots_filled)
3432 mark_set_resources (trial, &set, 0, 1);
3433 mark_referenced_resources (trial, &needed, 1);
3436 note_delay_statistics (slots_filled, 0);
3440 /* Try to find insns to place in delay slots.
3442 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
3443 or is an unconditional branch if CONDITION is const_true_rtx.
3444 *PSLOTS_FILLED is updated with the number of slots that we have filled.
3446 THREAD is a flow-of-control, either the insns to be executed if the
3447 branch is true or if the branch is false, THREAD_IF_TRUE says which.
3449 OPPOSITE_THREAD is the thread in the opposite direction. It is used
3450 to see if any potential delay slot insns set things needed there.
3452 LIKELY is non-zero if it is extremely likely that the branch will be
3453 taken and THREAD_IF_TRUE is set. This is used for the branch at the
3454 end of a loop back up to the top.
3456 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
3457 thread. I.e., it is the fallthrough code of our jump or the target of the
3458 jump when we are the only jump going there.
3460 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
3461 case, we can only take insns from the head of the thread for our delay
3462 slot. We then adjust the jump to point after the insns we have taken. */
3465 fill_slots_from_thread (insn, condition, thread, opposite_thread, likely,
3466 thread_if_true, own_thread,
3467 slots_to_fill, pslots_filled)
3470 rtx thread, opposite_thread;
3474 int slots_to_fill, *pslots_filled;
3478 struct resources opposite_needed, set, needed;
3484 /* Validate our arguments. */
3485 if ((condition == const_true_rtx && ! thread_if_true)
3486 || (! own_thread && ! thread_if_true))
3489 flags = get_jump_flags (insn, JUMP_LABEL (insn));
3491 /* If our thread is the end of subroutine, we can't get any delay
3496 /* If this is an unconditional branch, nothing is needed at the
3497 opposite thread. Otherwise, compute what is needed there. */
3498 if (condition == const_true_rtx)
3499 CLEAR_RESOURCE (&opposite_needed);
3501 mark_target_live_regs (opposite_thread, &opposite_needed);
3503 /* If the insn at THREAD can be split, do it here to avoid having to
3504 update THREAD and NEW_THREAD if it is done in the loop below. Also
3505 initialize NEW_THREAD. */
3507 new_thread = thread = try_split (PATTERN (thread), thread, 0);
3509 /* Scan insns at THREAD. We are looking for an insn that can be removed
3510 from THREAD (it neither sets nor references resources that were set
3511 ahead of it and it doesn't set anything needs by the insns ahead of
3512 it) and that either can be placed in an annulling insn or aren't
3513 needed at OPPOSITE_THREAD. */
3515 CLEAR_RESOURCE (&needed);
3516 CLEAR_RESOURCE (&set);
3518 /* If we do not own this thread, we must stop as soon as we find
3519 something that we can't put in a delay slot, since all we can do
3520 is branch into THREAD at a later point. Therefore, labels stop
3521 the search if this is not the `true' thread. */
3523 for (trial = thread;
3524 ! stop_search_p (trial, ! thread_if_true) && (! lose || own_thread);
3525 trial = next_nonnote_insn (trial))
3529 /* If we have passed a label, we no longer own this thread. */
3530 if (GET_CODE (trial) == CODE_LABEL)
3536 pat = PATTERN (trial);
3537 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3540 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
3541 don't separate or copy insns that set and use CC0. */
3542 if (! insn_references_resource_p (trial, &set, 1)
3543 && ! insn_sets_resource_p (trial, &set, 1)
3544 && ! insn_sets_resource_p (trial, &needed, 1)
3546 && ! (reg_mentioned_p (cc0_rtx, pat)
3547 && (! own_thread || ! sets_cc0_p (pat)))
3553 /* If TRIAL is redundant with some insn before INSN, we don't
3554 actually need to add it to the delay list; we can merely pretend
3556 if ((prior_insn = redundant_insn (trial, insn, delay_list)))
3558 fix_reg_dead_note (prior_insn, insn);
3561 update_block (trial, thread);
3562 if (trial == thread)
3564 thread = next_active_insn (thread);
3565 if (new_thread == trial)
3566 new_thread = thread;
3569 delete_insn (trial);
3573 update_reg_unused_notes (prior_insn, trial);
3574 new_thread = next_active_insn (trial);
3580 /* There are two ways we can win: If TRIAL doesn't set anything
3581 needed at the opposite thread and can't trap, or if it can
3582 go into an annulled delay slot. */
3583 if (condition == const_true_rtx
3584 || (! insn_sets_resource_p (trial, &opposite_needed, 1)
3585 && ! may_trap_p (pat)))
3588 trial = try_split (pat, trial, 0);
3589 if (new_thread == old_trial)
3591 if (thread == old_trial)
3593 pat = PATTERN (trial);
3594 if (eligible_for_delay (insn, *pslots_filled, trial, flags))
3598 #ifdef ANNUL_IFTRUE_SLOTS
3601 #ifdef ANNUL_IFFALSE_SLOTS
3607 trial = try_split (pat, trial, 0);
3608 if (new_thread == old_trial)
3610 if (thread == old_trial)
3612 pat = PATTERN (trial);
3614 ? eligible_for_annul_false (insn, *pslots_filled, trial, flags)
3615 : eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
3623 if (reg_mentioned_p (cc0_rtx, pat))
3624 link_cc0_insns (trial);
3627 /* If we own this thread, delete the insn. If this is the
3628 destination of a branch, show that a basic block status
3629 may have been updated. In any case, mark the new
3630 starting point of this thread. */
3633 update_block (trial, thread);
3634 if (trial == thread)
3636 thread = next_active_insn (thread);
3637 if (new_thread == trial)
3638 new_thread = thread;
3640 delete_insn (trial);
3643 new_thread = next_active_insn (trial);
3645 temp = own_thread ? trial : copy_rtx (trial);
3647 INSN_FROM_TARGET_P (temp) = 1;
3649 delay_list = add_to_delay_list (temp, delay_list);
3651 if (slots_to_fill == ++(*pslots_filled))
3653 /* Even though we have filled all the slots, we
3654 may be branching to a location that has a
3655 redundant insn. Skip any if so. */
3656 while (new_thread && ! own_thread
3657 && ! insn_sets_resource_p (new_thread, &set, 1)
3658 && ! insn_sets_resource_p (new_thread, &needed, 1)
3659 && ! insn_references_resource_p (new_thread,
3661 && redundant_insn (new_thread, insn, delay_list))
3662 new_thread = next_active_insn (new_thread);
3671 /* This insn can't go into a delay slot. */
3673 mark_set_resources (trial, &set, 0, 1);
3674 mark_referenced_resources (trial, &needed, 1);
3676 /* Ensure we don't put insns between the setting of cc and the comparison
3677 by moving a setting of cc into an earlier delay slot since these insns
3678 could clobber the condition code. */
3681 /* If this insn is a register-register copy and the next insn has
3682 a use of our destination, change it to use our source. That way,
3683 it will become a candidate for our delay slot the next time
3684 through this loop. This case occurs commonly in loops that
3687 We could check for more complex cases than those tested below,
3688 but it doesn't seem worth it. It might also be a good idea to try
3689 to swap the two insns. That might do better.
3691 We can't do this if the next insn modifies our destination, because
3692 that would make the replacement into the insn invalid. We also can't
3693 do this if it modifies our source, because it might be an earlyclobber
3694 operand. This latter test also prevents updating the contents of
3697 if (GET_CODE (trial) == INSN && GET_CODE (pat) == SET
3698 && GET_CODE (SET_SRC (pat)) == REG
3699 && GET_CODE (SET_DEST (pat)) == REG)
3701 rtx next = next_nonnote_insn (trial);
3703 if (next && GET_CODE (next) == INSN
3704 && GET_CODE (PATTERN (next)) != USE
3705 && ! reg_set_p (SET_DEST (pat), next)
3706 && ! reg_set_p (SET_SRC (pat), next)
3707 && reg_referenced_p (SET_DEST (pat), PATTERN (next)))
3708 validate_replace_rtx (SET_DEST (pat), SET_SRC (pat), next);
3712 /* If we stopped on a branch insn that has delay slots, see if we can
3713 steal some of the insns in those slots. */
3714 if (trial && GET_CODE (trial) == INSN
3715 && GET_CODE (PATTERN (trial)) == SEQUENCE
3716 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN)
3718 /* If this is the `true' thread, we will want to follow the jump,
3719 so we can only do this if we have taken everything up to here. */
3720 if (thread_if_true && trial == new_thread)
3722 = steal_delay_list_from_target (insn, condition, PATTERN (trial),
3723 delay_list, &set, &needed,
3724 &opposite_needed, slots_to_fill,
3725 pslots_filled, &must_annul,
3727 else if (! thread_if_true)
3729 = steal_delay_list_from_fallthrough (insn, condition,
3731 delay_list, &set, &needed,
3732 &opposite_needed, slots_to_fill,
3733 pslots_filled, &must_annul);
3736 /* If we haven't found anything for this delay slot and it is very
3737 likely that the branch will be taken, see if the insn at our target
3738 increments or decrements a register with an increment that does not
3739 depend on the destination register. If so, try to place the opposite
3740 arithmetic insn after the jump insn and put the arithmetic insn in the
3741 delay slot. If we can't do this, return. */
3742 if (delay_list == 0 && likely && new_thread
3743 && GET_CODE (new_thread) == INSN
3744 && GET_CODE (PATTERN (new_thread)) != ASM_INPUT
3745 && asm_noperands (PATTERN (new_thread)) < 0)
3747 rtx pat = PATTERN (new_thread);
3752 pat = PATTERN (trial);
3754 if (GET_CODE (trial) != INSN || GET_CODE (pat) != SET
3755 || ! eligible_for_delay (insn, 0, trial, flags))
3758 dest = SET_DEST (pat), src = SET_SRC (pat);
3759 if ((GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
3760 && rtx_equal_p (XEXP (src, 0), dest)
3761 && ! reg_overlap_mentioned_p (dest, XEXP (src, 1)))
3763 rtx other = XEXP (src, 1);
3767 /* If this is a constant adjustment, use the same code with
3768 the negated constant. Otherwise, reverse the sense of the
3770 if (GET_CODE (other) == CONST_INT)
3771 new_arith = gen_rtx_fmt_ee (GET_CODE (src), GET_MODE (src), dest,
3772 negate_rtx (GET_MODE (src), other));
3774 new_arith = gen_rtx_fmt_ee (GET_CODE (src) == PLUS ? MINUS : PLUS,
3775 GET_MODE (src), dest, other);
3777 ninsn = emit_insn_after (gen_rtx_SET (VOIDmode, dest, new_arith),
3780 if (recog_memoized (ninsn) < 0
3781 || (insn_extract (ninsn),
3782 ! constrain_operands (INSN_CODE (ninsn), 1)))
3784 delete_insn (ninsn);
3790 update_block (trial, thread);
3791 if (trial == thread)
3793 thread = next_active_insn (thread);
3794 if (new_thread == trial)
3795 new_thread = thread;
3797 delete_insn (trial);
3800 new_thread = next_active_insn (trial);
3802 ninsn = own_thread ? trial : copy_rtx (trial);
3804 INSN_FROM_TARGET_P (ninsn) = 1;
3806 delay_list = add_to_delay_list (ninsn, NULL_RTX);
3811 if (delay_list && must_annul)
3812 INSN_ANNULLED_BRANCH_P (insn) = 1;
3814 /* If we are to branch into the middle of this thread, find an appropriate
3815 label or make a new one if none, and redirect INSN to it. If we hit the
3816 end of the function, use the end-of-function label. */
3817 if (new_thread != thread)
3821 if (! thread_if_true)
3824 if (new_thread && GET_CODE (new_thread) == JUMP_INSN
3825 && (simplejump_p (new_thread)
3826 || GET_CODE (PATTERN (new_thread)) == RETURN)
3827 && redirect_with_delay_list_safe_p (insn,
3828 JUMP_LABEL (new_thread),
3830 new_thread = follow_jumps (JUMP_LABEL (new_thread));
3832 if (new_thread == 0)
3833 label = find_end_label ();
3834 else if (GET_CODE (new_thread) == CODE_LABEL)
3837 label = get_label_before (new_thread);
3839 reorg_redirect_jump (insn, label);
3845 /* Make another attempt to find insns to place in delay slots.
3847 We previously looked for insns located in front of the delay insn
3848 and, for non-jump delay insns, located behind the delay insn.
3850 Here only try to schedule jump insns and try to move insns from either
3851 the target or the following insns into the delay slot. If annulling is
3852 supported, we will be likely to do this. Otherwise, we can do this only
3856 fill_eager_delay_slots ()
3860 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
3862 for (i = 0; i < num_unfilled_slots; i++)
3865 rtx target_label, insn_at_target, fallthrough_insn;
3868 int own_fallthrough;
3869 int prediction, slots_to_fill, slots_filled;
3871 insn = unfilled_slots_base[i];
3873 || INSN_DELETED_P (insn)
3874 || GET_CODE (insn) != JUMP_INSN
3875 || ! (condjump_p (insn) || condjump_in_parallel_p (insn)))
3878 slots_to_fill = num_delay_slots (insn);
3879 if (slots_to_fill == 0)
3883 target_label = JUMP_LABEL (insn);
3884 condition = get_branch_condition (insn, target_label);
3889 /* Get the next active fallthrough and target insns and see if we own
3890 them. Then see whether the branch is likely true. We don't need
3891 to do a lot of this for unconditional branches. */
3893 insn_at_target = next_active_insn (target_label);
3894 own_target = own_thread_p (target_label, target_label, 0);
3896 if (condition == const_true_rtx)
3898 own_fallthrough = 0;
3899 fallthrough_insn = 0;
3904 fallthrough_insn = next_active_insn (insn);
3905 own_fallthrough = own_thread_p (NEXT_INSN (insn), NULL_RTX, 1);
3906 prediction = mostly_true_jump (insn, condition);
3909 /* If this insn is expected to branch, first try to get insns from our
3910 target, then our fallthrough insns. If it is not, expected to branch,
3911 try the other order. */
3916 = fill_slots_from_thread (insn, condition, insn_at_target,
3917 fallthrough_insn, prediction == 2, 1,
3919 slots_to_fill, &slots_filled);
3921 if (delay_list == 0 && own_fallthrough)
3923 /* Even though we didn't find anything for delay slots,
3924 we might have found a redundant insn which we deleted
3925 from the thread that was filled. So we have to recompute
3926 the next insn at the target. */
3927 target_label = JUMP_LABEL (insn);
3928 insn_at_target = next_active_insn (target_label);
3931 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3932 insn_at_target, 0, 0,
3934 slots_to_fill, &slots_filled);
3939 if (own_fallthrough)
3941 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3942 insn_at_target, 0, 0,
3944 slots_to_fill, &slots_filled);
3946 if (delay_list == 0)
3948 = fill_slots_from_thread (insn, condition, insn_at_target,
3949 next_active_insn (insn), 0, 1,
3951 slots_to_fill, &slots_filled);
3955 unfilled_slots_base[i]
3956 = emit_delay_sequence (insn, delay_list, slots_filled);
3958 if (slots_to_fill == slots_filled)
3959 unfilled_slots_base[i] = 0;
3961 note_delay_statistics (slots_filled, 1);
3965 /* Once we have tried two ways to fill a delay slot, make a pass over the
3966 code to try to improve the results and to do such things as more jump
3970 relax_delay_slots (first)
3973 register rtx insn, next, pat;
3974 register rtx trial, delay_insn, target_label;
3976 /* Look at every JUMP_INSN and see if we can improve it. */
3977 for (insn = first; insn; insn = next)
3981 next = next_active_insn (insn);
3983 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3984 the next insn, or jumps to a label that is not the last of a
3985 group of consecutive labels. */
3986 if (GET_CODE (insn) == JUMP_INSN
3987 && (condjump_p (insn) || condjump_in_parallel_p (insn))
3988 && (target_label = JUMP_LABEL (insn)) != 0)
3990 target_label = follow_jumps (target_label);
3991 target_label = prev_label (next_active_insn (target_label));
3993 if (target_label == 0)
3994 target_label = find_end_label ();
3996 if (next_active_insn (target_label) == next
3997 && ! condjump_in_parallel_p (insn))
4003 if (target_label != JUMP_LABEL (insn))
4004 reorg_redirect_jump (insn, target_label);
4006 /* See if this jump branches around a unconditional jump.
4007 If so, invert this jump and point it to the target of the
4009 if (next && GET_CODE (next) == JUMP_INSN
4010 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
4011 && next_active_insn (target_label) == next_active_insn (next)
4012 && no_labels_between_p (insn, next))
4014 rtx label = JUMP_LABEL (next);
4016 /* Be careful how we do this to avoid deleting code or
4017 labels that are momentarily dead. See similar optimization
4020 We also need to ensure we properly handle the case when
4021 invert_jump fails. */
4023 ++LABEL_NUSES (target_label);
4025 ++LABEL_NUSES (label);
4027 if (invert_jump (insn, label))
4034 --LABEL_NUSES (label);
4036 if (--LABEL_NUSES (target_label) == 0)
4037 delete_insn (target_label);
4043 /* If this is an unconditional jump and the previous insn is a
4044 conditional jump, try reversing the condition of the previous
4045 insn and swapping our targets. The next pass might be able to
4048 Don't do this if we expect the conditional branch to be true, because
4049 we would then be making the more common case longer. */
4051 if (GET_CODE (insn) == JUMP_INSN
4052 && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN)
4053 && (other = prev_active_insn (insn)) != 0
4054 && (condjump_p (other) || condjump_in_parallel_p (other))
4055 && no_labels_between_p (other, insn)
4056 && 0 < mostly_true_jump (other,
4057 get_branch_condition (other,
4058 JUMP_LABEL (other))))
4060 rtx other_target = JUMP_LABEL (other);
4061 target_label = JUMP_LABEL (insn);
4063 /* Increment the count of OTHER_TARGET, so it doesn't get deleted
4064 as we move the label. */
4066 ++LABEL_NUSES (other_target);
4068 if (invert_jump (other, target_label))
4069 reorg_redirect_jump (insn, other_target);
4072 --LABEL_NUSES (other_target);
4075 /* Now look only at cases where we have filled a delay slot. */
4076 if (GET_CODE (insn) != INSN
4077 || GET_CODE (PATTERN (insn)) != SEQUENCE)
4080 pat = PATTERN (insn);
4081 delay_insn = XVECEXP (pat, 0, 0);
4083 /* See if the first insn in the delay slot is redundant with some
4084 previous insn. Remove it from the delay slot if so; then set up
4085 to reprocess this insn. */
4086 if (redundant_insn (XVECEXP (pat, 0, 1), delay_insn, 0))
4088 delete_from_delay_slot (XVECEXP (pat, 0, 1));
4089 next = prev_active_insn (next);
4093 /* Now look only at the cases where we have a filled JUMP_INSN. */
4094 if (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
4095 || ! (condjump_p (XVECEXP (PATTERN (insn), 0, 0))
4096 || condjump_in_parallel_p (XVECEXP (PATTERN (insn), 0, 0))))
4099 target_label = JUMP_LABEL (delay_insn);
4103 /* If this jump goes to another unconditional jump, thread it, but
4104 don't convert a jump into a RETURN here. */
4105 trial = follow_jumps (target_label);
4106 /* We use next_real_insn instead of next_active_insn, so that
4107 the special USE insns emitted by reorg won't be ignored.
4108 If they are ignored, then they will get deleted if target_label
4109 is now unreachable, and that would cause mark_target_live_regs
4111 trial = prev_label (next_real_insn (trial));
4112 if (trial == 0 && target_label != 0)
4113 trial = find_end_label ();
4115 if (trial != target_label
4116 && redirect_with_delay_slots_safe_p (delay_insn, trial, insn))
4118 reorg_redirect_jump (delay_insn, trial);
4119 target_label = trial;
4122 /* If the first insn at TARGET_LABEL is redundant with a previous
4123 insn, redirect the jump to the following insn process again. */
4124 trial = next_active_insn (target_label);
4125 if (trial && GET_CODE (PATTERN (trial)) != SEQUENCE
4126 && redundant_insn (trial, insn, 0))
4130 /* Figure out where to emit the special USE insn so we don't
4131 later incorrectly compute register live/death info. */
4132 tmp = next_active_insn (trial);
4134 tmp = find_end_label ();
4136 /* Insert the special USE insn and update dataflow info. */
4137 update_block (trial, tmp);
4139 /* Now emit a label before the special USE insn, and
4140 redirect our jump to the new label. */
4141 target_label = get_label_before (PREV_INSN (tmp));
4142 reorg_redirect_jump (delay_insn, target_label);
4147 /* Similarly, if it is an unconditional jump with one insn in its
4148 delay list and that insn is redundant, thread the jump. */
4149 if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE
4150 && XVECLEN (PATTERN (trial), 0) == 2
4151 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN
4152 && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0))
4153 || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN)
4154 && redundant_insn (XVECEXP (PATTERN (trial), 0, 1), insn, 0))
4156 target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0));
4157 if (target_label == 0)
4158 target_label = find_end_label ();
4160 if (redirect_with_delay_slots_safe_p (delay_insn, target_label,
4163 reorg_redirect_jump (delay_insn, target_label);
4170 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
4171 && prev_active_insn (target_label) == insn
4172 && ! condjump_in_parallel_p (delay_insn)
4174 /* If the last insn in the delay slot sets CC0 for some insn,
4175 various code assumes that it is in a delay slot. We could
4176 put it back where it belonged and delete the register notes,
4177 but it doesn't seem worthwhile in this uncommon case. */
4178 && ! find_reg_note (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1),
4179 REG_CC_USER, NULL_RTX)
4185 /* All this insn does is execute its delay list and jump to the
4186 following insn. So delete the jump and just execute the delay
4189 We do this by deleting the INSN containing the SEQUENCE, then
4190 re-emitting the insns separately, and then deleting the jump.
4191 This allows the count of the jump target to be properly
4194 /* Clear the from target bit, since these insns are no longer
4196 for (i = 0; i < XVECLEN (pat, 0); i++)
4197 INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)) = 0;
4199 trial = PREV_INSN (insn);
4201 emit_insn_after (pat, trial);
4202 delete_scheduled_jump (delay_insn);
4206 /* See if this is an unconditional jump around a single insn which is
4207 identical to the one in its delay slot. In this case, we can just
4208 delete the branch and the insn in its delay slot. */
4209 if (next && GET_CODE (next) == INSN
4210 && prev_label (next_active_insn (next)) == target_label
4211 && simplejump_p (insn)
4212 && XVECLEN (pat, 0) == 2
4213 && rtx_equal_p (PATTERN (next), PATTERN (XVECEXP (pat, 0, 1))))
4219 /* See if this jump (with its delay slots) branches around another
4220 jump (without delay slots). If so, invert this jump and point
4221 it to the target of the second jump. We cannot do this for
4222 annulled jumps, though. Again, don't convert a jump to a RETURN
4224 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
4225 && next && GET_CODE (next) == JUMP_INSN
4226 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
4227 && next_active_insn (target_label) == next_active_insn (next)
4228 && no_labels_between_p (insn, next))
4230 rtx label = JUMP_LABEL (next);
4231 rtx old_label = JUMP_LABEL (delay_insn);
4234 label = find_end_label ();
4236 if (redirect_with_delay_slots_safe_p (delay_insn, label, insn))
4238 /* Be careful how we do this to avoid deleting code or labels
4239 that are momentarily dead. See similar optimization in
4242 ++LABEL_NUSES (old_label);
4244 if (invert_jump (delay_insn, label))
4248 /* Must update the INSN_FROM_TARGET_P bits now that
4249 the branch is reversed, so that mark_target_live_regs
4250 will handle the delay slot insn correctly. */
4251 for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
4253 rtx slot = XVECEXP (PATTERN (insn), 0, i);
4254 INSN_FROM_TARGET_P (slot) = ! INSN_FROM_TARGET_P (slot);
4261 if (old_label && --LABEL_NUSES (old_label) == 0)
4262 delete_insn (old_label);
4267 /* If we own the thread opposite the way this insn branches, see if we
4268 can merge its delay slots with following insns. */
4269 if (INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
4270 && own_thread_p (NEXT_INSN (insn), 0, 1))
4271 try_merge_delay_insns (insn, next);
4272 else if (! INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
4273 && own_thread_p (target_label, target_label, 0))
4274 try_merge_delay_insns (insn, next_active_insn (target_label));
4276 /* If we get here, we haven't deleted INSN. But we may have deleted
4277 NEXT, so recompute it. */
4278 next = next_active_insn (insn);
4284 /* Look for filled jumps to the end of function label. We can try to convert
4285 them into RETURN insns if the insns in the delay slot are valid for the
4289 make_return_insns (first)
4292 rtx insn, jump_insn, pat;
4293 rtx real_return_label = end_of_function_label;
4296 /* See if there is a RETURN insn in the function other than the one we
4297 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
4298 into a RETURN to jump to it. */
4299 for (insn = first; insn; insn = NEXT_INSN (insn))
4300 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) == RETURN)
4302 real_return_label = get_label_before (insn);
4306 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
4307 was equal to END_OF_FUNCTION_LABEL. */
4308 LABEL_NUSES (real_return_label)++;
4310 /* Clear the list of insns to fill so we can use it. */
4311 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
4313 for (insn = first; insn; insn = NEXT_INSN (insn))
4317 /* Only look at filled JUMP_INSNs that go to the end of function
4319 if (GET_CODE (insn) != INSN
4320 || GET_CODE (PATTERN (insn)) != SEQUENCE
4321 || GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
4322 || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label)
4325 pat = PATTERN (insn);
4326 jump_insn = XVECEXP (pat, 0, 0);
4328 /* If we can't make the jump into a RETURN, try to redirect it to the best
4329 RETURN and go on to the next insn. */
4330 if (! reorg_redirect_jump (jump_insn, NULL_RTX))
4332 /* Make sure redirecting the jump will not invalidate the delay
4334 if (redirect_with_delay_slots_safe_p (jump_insn,
4337 reorg_redirect_jump (jump_insn, real_return_label);
4341 /* See if this RETURN can accept the insns current in its delay slot.
4342 It can if it has more or an equal number of slots and the contents
4343 of each is valid. */
4345 flags = get_jump_flags (jump_insn, JUMP_LABEL (jump_insn));
4346 slots = num_delay_slots (jump_insn);
4347 if (slots >= XVECLEN (pat, 0) - 1)
4349 for (i = 1; i < XVECLEN (pat, 0); i++)
4351 #ifdef ANNUL_IFFALSE_SLOTS
4352 (INSN_ANNULLED_BRANCH_P (jump_insn)
4353 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
4354 ? eligible_for_annul_false (jump_insn, i - 1,
4355 XVECEXP (pat, 0, i), flags) :
4357 #ifdef ANNUL_IFTRUE_SLOTS
4358 (INSN_ANNULLED_BRANCH_P (jump_insn)
4359 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
4360 ? eligible_for_annul_true (jump_insn, i - 1,
4361 XVECEXP (pat, 0, i), flags) :
4363 eligible_for_delay (jump_insn, i -1, XVECEXP (pat, 0, i), flags)))
4369 if (i == XVECLEN (pat, 0))
4372 /* We have to do something with this insn. If it is an unconditional
4373 RETURN, delete the SEQUENCE and output the individual insns,
4374 followed by the RETURN. Then set things up so we try to find
4375 insns for its delay slots, if it needs some. */
4376 if (GET_CODE (PATTERN (jump_insn)) == RETURN)
4378 rtx prev = PREV_INSN (insn);
4381 for (i = 1; i < XVECLEN (pat, 0); i++)
4382 prev = emit_insn_after (PATTERN (XVECEXP (pat, 0, i)), prev);
4384 insn = emit_jump_insn_after (PATTERN (jump_insn), prev);
4385 emit_barrier_after (insn);
4388 obstack_ptr_grow (&unfilled_slots_obstack, insn);
4391 /* It is probably more efficient to keep this with its current
4392 delay slot as a branch to a RETURN. */
4393 reorg_redirect_jump (jump_insn, real_return_label);
4396 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
4397 new delay slots we have created. */
4398 if (--LABEL_NUSES (real_return_label) == 0)
4399 delete_insn (real_return_label);
4401 fill_simple_delay_slots (1);
4402 fill_simple_delay_slots (0);
4406 /* Try to find insns to place in delay slots. */
4409 dbr_schedule (first, file)
4413 rtx insn, next, epilogue_insn = 0;
4416 int old_flag_no_peephole = flag_no_peephole;
4418 /* Execute `final' once in prescan mode to delete any insns that won't be
4419 used. Don't let final try to do any peephole optimization--it will
4420 ruin dataflow information for this pass. */
4422 flag_no_peephole = 1;
4423 final (first, 0, NO_DEBUG, 1, 1);
4424 flag_no_peephole = old_flag_no_peephole;
4427 /* If the current function has no insns other than the prologue and
4428 epilogue, then do not try to fill any delay slots. */
4429 if (n_basic_blocks == 0)
4432 /* Find the highest INSN_UID and allocate and initialize our map from
4433 INSN_UID's to position in code. */
4434 for (max_uid = 0, insn = first; insn; insn = NEXT_INSN (insn))
4436 if (INSN_UID (insn) > max_uid)
4437 max_uid = INSN_UID (insn);
4438 if (GET_CODE (insn) == NOTE
4439 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG)
4440 epilogue_insn = insn;
4443 uid_to_ruid = (int *) alloca ((max_uid + 1) * sizeof (int *));
4444 for (i = 0, insn = first; insn; i++, insn = NEXT_INSN (insn))
4445 uid_to_ruid[INSN_UID (insn)] = i;
4447 /* Initialize the list of insns that need filling. */
4448 if (unfilled_firstobj == 0)
4450 gcc_obstack_init (&unfilled_slots_obstack);
4451 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4454 for (insn = next_active_insn (first); insn; insn = next_active_insn (insn))
4458 INSN_ANNULLED_BRANCH_P (insn) = 0;
4459 INSN_FROM_TARGET_P (insn) = 0;
4461 /* Skip vector tables. We can't get attributes for them. */
4462 if (GET_CODE (insn) == JUMP_INSN
4463 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
4464 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
4467 if (num_delay_slots (insn) > 0)
4468 obstack_ptr_grow (&unfilled_slots_obstack, insn);
4470 /* Ensure all jumps go to the last of a set of consecutive labels. */
4471 if (GET_CODE (insn) == JUMP_INSN
4472 && (condjump_p (insn) || condjump_in_parallel_p (insn))
4473 && JUMP_LABEL (insn) != 0
4474 && ((target = prev_label (next_active_insn (JUMP_LABEL (insn))))
4475 != JUMP_LABEL (insn)))
4476 redirect_jump (insn, target);
4479 /* Indicate what resources are required to be valid at the end of the current
4480 function. The condition code never is and memory always is. If the
4481 frame pointer is needed, it is and so is the stack pointer unless
4482 EXIT_IGNORE_STACK is non-zero. If the frame pointer is not needed, the
4483 stack pointer is. Registers used to return the function value are
4484 needed. Registers holding global variables are needed. */
4486 end_of_function_needs.cc = 0;
4487 end_of_function_needs.memory = 1;
4488 end_of_function_needs.unch_memory = 0;
4489 CLEAR_HARD_REG_SET (end_of_function_needs.regs);
4491 if (frame_pointer_needed)
4493 SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM);
4494 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
4495 SET_HARD_REG_BIT (end_of_function_needs.regs, HARD_FRAME_POINTER_REGNUM);
4497 #ifdef EXIT_IGNORE_STACK
4498 if (! EXIT_IGNORE_STACK)
4500 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4503 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4505 if (current_function_return_rtx != 0)
4506 mark_referenced_resources (current_function_return_rtx,
4507 &end_of_function_needs, 1);
4509 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4511 #ifdef EPILOGUE_USES
4512 || EPILOGUE_USES (i)
4515 SET_HARD_REG_BIT (end_of_function_needs.regs, i);
4517 /* The registers required to be live at the end of the function are
4518 represented in the flow information as being dead just prior to
4519 reaching the end of the function. For example, the return of a value
4520 might be represented by a USE of the return register immediately
4521 followed by an unconditional jump to the return label where the
4522 return label is the end of the RTL chain. The end of the RTL chain
4523 is then taken to mean that the return register is live.
4525 This sequence is no longer maintained when epilogue instructions are
4526 added to the RTL chain. To reconstruct the original meaning, the
4527 start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the
4528 point where these registers become live (start_of_epilogue_needs).
4529 If epilogue instructions are present, the registers set by those
4530 instructions won't have been processed by flow. Thus, those
4531 registers are additionally required at the end of the RTL chain
4532 (end_of_function_needs). */
4534 start_of_epilogue_needs = end_of_function_needs;
4536 while ((epilogue_insn = next_nonnote_insn (epilogue_insn)))
4537 mark_set_resources (epilogue_insn, &end_of_function_needs, 0, 1);
4539 /* Show we haven't computed an end-of-function label yet. */
4540 end_of_function_label = 0;
4542 /* Allocate and initialize the tables used by mark_target_live_regs. */
4544 = (struct target_info **) alloca ((TARGET_HASH_PRIME
4545 * sizeof (struct target_info *)));
4546 bzero ((char *) target_hash_table,
4547 TARGET_HASH_PRIME * sizeof (struct target_info *));
4549 bb_ticks = (int *) alloca (n_basic_blocks * sizeof (int));
4550 bzero ((char *) bb_ticks, n_basic_blocks * sizeof (int));
4552 /* Initialize the statistics for this function. */
4553 bzero ((char *) num_insns_needing_delays, sizeof num_insns_needing_delays);
4554 bzero ((char *) num_filled_delays, sizeof num_filled_delays);
4556 /* Now do the delay slot filling. Try everything twice in case earlier
4557 changes make more slots fillable. */
4559 for (reorg_pass_number = 0;
4560 reorg_pass_number < MAX_REORG_PASSES;
4561 reorg_pass_number++)
4563 fill_simple_delay_slots (1);
4564 fill_simple_delay_slots (0);
4565 fill_eager_delay_slots ();
4566 relax_delay_slots (first);
4569 /* Delete any USE insns made by update_block; subsequent passes don't need
4570 them or know how to deal with them. */
4571 for (insn = first; insn; insn = next)
4573 next = NEXT_INSN (insn);
4575 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
4576 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
4577 next = delete_insn (insn);
4580 /* If we made an end of function label, indicate that it is now
4581 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
4582 If it is now unused, delete it. */
4583 if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0)
4584 delete_insn (end_of_function_label);
4587 if (HAVE_return && end_of_function_label != 0)
4588 make_return_insns (first);
4591 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
4593 /* It is not clear why the line below is needed, but it does seem to be. */
4594 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4596 /* Reposition the prologue and epilogue notes in case we moved the
4597 prologue/epilogue insns. */
4598 reposition_prologue_and_epilogue_notes (first);
4602 register int i, j, need_comma;
4604 for (reorg_pass_number = 0;
4605 reorg_pass_number < MAX_REORG_PASSES;
4606 reorg_pass_number++)
4608 fprintf (file, ";; Reorg pass #%d:\n", reorg_pass_number + 1);
4609 for (i = 0; i < NUM_REORG_FUNCTIONS; i++)
4612 fprintf (file, ";; Reorg function #%d\n", i);
4614 fprintf (file, ";; %d insns needing delay slots\n;; ",
4615 num_insns_needing_delays[i][reorg_pass_number]);
4617 for (j = 0; j < MAX_DELAY_HISTOGRAM; j++)
4618 if (num_filled_delays[i][j][reorg_pass_number])
4621 fprintf (file, ", ");
4623 fprintf (file, "%d got %d delays",
4624 num_filled_delays[i][j][reorg_pass_number], j);
4626 fprintf (file, "\n");
4631 /* For all JUMP insns, fill in branch prediction notes, so that during
4632 assembler output a target can set branch prediction bits in the code.
4633 We have to do this now, as up until this point the destinations of
4634 JUMPS can be moved around and changed, but past right here that cannot
4636 for (insn = first; insn; insn = NEXT_INSN (insn))
4640 if (GET_CODE (insn) != JUMP_INSN)
4643 pred_flags = get_jump_flags (insn, JUMP_LABEL (insn));
4644 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_BR_PRED,
4645 GEN_INT (pred_flags),
4649 #endif /* DELAY_SLOTS */