1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992, 1993 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS and AMD 29000 have a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The Motorola 88000 conditionally exposes its branch delay slot,
43 so code is shorter when it is turned off, but will run faster
44 when useful insns are scheduled there.
46 The IBM ROMP has two forms of branch and call insns, both with and
47 without a delay slot. Much like the 88k, insns not using the delay
48 slot can be shorted (2 bytes vs. 4 bytes), but will run slowed.
50 The SPARC always has a branch delay slot, but its effects can be
51 annulled when the branch is not taken. This means that failing to
52 find other sources of insns, we can hoist an insn from the branch
53 target that would only be safe to execute knowing that the branch
56 The HP-PA always has a branch delay slot. For unconditional branches
57 its effects can be annulled when the branch is taken. The effects
58 of the delay slot in a conditional branch can be nullified for forward
59 taken branches, or for untaken backward branches. This means
60 we can hoist insns from the fall-through path for forward branches or
61 steal insns from the target of backward branches.
63 Three techniques for filling delay slots have been implemented so far:
65 (1) `fill_simple_delay_slots' is the simplest, most efficient way
66 to fill delay slots. This pass first looks for insns which come
67 from before the branch and which are safe to execute after the
68 branch. Then it searches after the insn requiring delay slots or,
69 in the case of a branch, for insns that are after the point at
70 which the branch merges into the fallthrough code, if such a point
71 exists. When such insns are found, the branch penalty decreases
72 and no code expansion takes place.
74 (2) `fill_eager_delay_slots' is more complicated: it is used for
75 scheduling conditional jumps, or for scheduling jumps which cannot
76 be filled using (1). A machine need not have annulled jumps to use
77 this strategy, but it helps (by keeping more options open).
78 `fill_eager_delay_slots' tries to guess the direction the branch
79 will go; if it guesses right 100% of the time, it can reduce the
80 branch penalty as much as `fill_simple_delay_slots' does. If it
81 guesses wrong 100% of the time, it might as well schedule nops (or
82 on the m88k, unexpose the branch slot). When
83 `fill_eager_delay_slots' takes insns from the fall-through path of
84 the jump, usually there is no code expansion; when it takes insns
85 from the branch target, there is code expansion if it is not the
86 only way to reach that target.
88 (3) `relax_delay_slots' uses a set of rules to simplify code that
89 has been reorganized by (1) and (2). It finds cases where
90 conditional test can be eliminated, jumps can be threaded, extra
91 insns can be eliminated, etc. It is the job of (1) and (2) to do a
92 good job of scheduling locally; `relax_delay_slots' takes care of
93 making the various individual schedules work well together. It is
94 especially tuned to handle the control flow interactions of branch
95 insns. It does nothing for insns with delay slots that do not
98 On machines that use CC0, we are very conservative. We will not make
99 a copy of an insn involving CC0 since we want to maintain a 1-1
100 correspondence between the insn that sets and uses CC0. The insns are
101 allowed to be separated by placing an insn that sets CC0 (but not an insn
102 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
103 delay slot. In that case, we point each insn at the other with REG_CC_USER
104 and REG_CC_SETTER notes. Note that these restrictions affect very few
105 machines because most RISC machines with delay slots will not use CC0
106 (the RT is the only known exception at this point).
110 The Acorn Risc Machine can conditionally execute most insns, so
111 it is profitable to move single insns into a position to execute
112 based on the condition code of the previous insn.
114 The HP-PA can conditionally nullify insns, providing a similar
115 effect to the ARM, differing mostly in which insn is "in charge". */
120 #include "insn-config.h"
121 #include "conditions.h"
122 #include "hard-reg-set.h"
123 #include "basic-block.h"
125 #include "insn-flags.h"
130 #include "insn-attr.h"
134 #define obstack_chunk_alloc xmalloc
135 #define obstack_chunk_free free
137 #ifndef ANNUL_IFTRUE_SLOTS
138 #define eligible_for_annul_true(INSN, SLOTS, TRIAL, FLAGS) 0
140 #ifndef ANNUL_IFFALSE_SLOTS
141 #define eligible_for_annul_false(INSN, SLOTS, TRIAL, FLAGS) 0
144 /* Insns which have delay slots that have not yet been filled. */
146 static struct obstack unfilled_slots_obstack;
147 static rtx *unfilled_firstobj;
149 /* Define macros to refer to the first and last slot containing unfilled
150 insns. These are used because the list may move and its address
151 should be recomputed at each use. */
153 #define unfilled_slots_base \
154 ((rtx *) obstack_base (&unfilled_slots_obstack))
156 #define unfilled_slots_next \
157 ((rtx *) obstack_next_free (&unfilled_slots_obstack))
159 /* This structure is used to indicate which hardware resources are set or
160 needed by insns so far. */
164 char memory; /* Insn sets or needs a memory location. */
165 char volatil; /* Insn sets or needs a volatile memory loc. */
166 char cc; /* Insn sets or needs the condition codes. */
167 HARD_REG_SET regs; /* Which registers are set or needed. */
170 /* Macro to clear all resources. */
171 #define CLEAR_RESOURCE(RES) \
172 do { (RES)->memory = (RES)->volatil = (RES)->cc = 0; \
173 CLEAR_HARD_REG_SET ((RES)->regs); } while (0)
175 /* Indicates what resources are required at the beginning of the epilogue. */
176 static struct resources start_of_epilogue_needs;
178 /* Indicates what resources are required at function end. */
179 static struct resources end_of_function_needs;
181 /* Points to the label before the end of the function. */
182 static rtx end_of_function_label;
184 /* This structure is used to record liveness information at the targets or
185 fallthrough insns of branches. We will most likely need the information
186 at targets again, so save them in a hash table rather than recomputing them
191 int uid; /* INSN_UID of target. */
192 struct target_info *next; /* Next info for same hash bucket. */
193 HARD_REG_SET live_regs; /* Registers live at target. */
194 int block; /* Basic block number containing target. */
195 int bb_tick; /* Generation count of basic block info. */
198 #define TARGET_HASH_PRIME 257
200 /* Define the hash table itself. */
201 static struct target_info **target_hash_table;
203 /* For each basic block, we maintain a generation number of its basic
204 block info, which is updated each time we move an insn from the
205 target of a jump. This is the generation number indexed by block
208 static int *bb_ticks;
210 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
211 not always monotonically increase. */
212 static int *uid_to_ruid;
214 /* Highest valid index in `uid_to_ruid'. */
217 static void mark_referenced_resources PROTO((rtx, struct resources *, int));
218 static void mark_set_resources PROTO((rtx, struct resources *, int, int));
219 static int stop_search_p PROTO((rtx, int));
220 static int resource_conflicts_p PROTO((struct resources *,
221 struct resources *));
222 static int insn_references_resource_p PROTO((rtx, struct resources *, int));
223 static int insn_sets_resources_p PROTO((rtx, struct resources *, int));
224 static rtx find_end_label PROTO((void));
225 static rtx emit_delay_sequence PROTO((rtx, rtx, int, int));
226 static rtx add_to_delay_list PROTO((rtx, rtx));
227 static void delete_from_delay_slot PROTO((rtx));
228 static void delete_scheduled_jump PROTO((rtx));
229 static void note_delay_statistics PROTO((int, int));
230 static rtx optimize_skip PROTO((rtx));
231 static int get_jump_flags PROTO((rtx, rtx));
232 static int rare_destination PROTO((rtx));
233 static int mostly_true_jump PROTO((rtx, rtx));
234 static rtx get_branch_condition PROTO((rtx, rtx));
235 static int condition_dominates_p PROTO((rtx, rtx));
236 static rtx steal_delay_list_from_target PROTO((rtx, rtx, rtx, rtx,
240 int, int *, int *, rtx *));
241 static rtx steal_delay_list_from_fallthrough PROTO((rtx, rtx, rtx, rtx,
246 static void try_merge_delay_insns PROTO((rtx, rtx));
247 static int redundant_insn_p PROTO((rtx, rtx, rtx));
248 static int own_thread_p PROTO((rtx, rtx, int));
249 static int find_basic_block PROTO((rtx));
250 static void update_block PROTO((rtx, rtx));
251 static int reorg_redirect_jump PROTO((rtx, rtx));
252 static void update_reg_dead_notes PROTO((rtx, rtx));
253 static void update_live_status PROTO((rtx, rtx));
254 static rtx next_insn_no_annul PROTO((rtx));
255 static void mark_target_live_regs PROTO((rtx, struct resources *));
256 static void fill_simple_delay_slots PROTO((rtx, int));
257 static rtx fill_slots_from_thread PROTO((rtx, rtx, rtx, rtx, int, int,
258 int, int, int, int *));
259 static void fill_eager_delay_slots PROTO((rtx));
260 static void relax_delay_slots PROTO((rtx));
261 static void make_return_insns PROTO((rtx));
263 /* Given X, some rtl, and RES, a pointer to a `struct resource', mark
264 which resources are references by the insn. If INCLUDE_CALLED_ROUTINE
265 is TRUE, resources used by the called routine will be included for
269 mark_referenced_resources (x, res, include_delayed_effects)
271 register struct resources *res;
272 register int include_delayed_effects;
274 register enum rtx_code code = GET_CODE (x);
276 register char *format_ptr;
278 /* Handle leaf items for which we set resource flags. Also, special-case
279 CALL, SET and CLOBBER operators. */
291 if (GET_CODE (SUBREG_REG (x)) != REG)
292 mark_referenced_resources (SUBREG_REG (x), res, 0);
295 int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
296 int last_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
297 for (i = regno; i < last_regno; i++)
298 SET_HARD_REG_BIT (res->regs, i);
303 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
304 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
308 /* If this memory shouldn't change, it really isn't referencing
310 if (! RTX_UNCHANGING_P (x))
312 res->volatil = MEM_VOLATILE_P (x);
314 /* Mark registers used to access memory. */
315 mark_referenced_resources (XEXP (x, 0), res, 0);
322 case UNSPEC_VOLATILE:
324 /* Traditional asm's are always volatile. */
329 res->volatil = MEM_VOLATILE_P (x);
331 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
332 We can not just fall through here since then we would be confused
333 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
334 traditional asms unlike their normal usage. */
336 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
337 mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, 0);
341 /* The first operand will be a (MEM (xxx)) but doesn't really reference
342 memory. The second operand may be referenced, though. */
343 mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, 0);
344 mark_referenced_resources (XEXP (x, 1), res, 0);
348 /* Usually, the first operand of SET is set, not referenced. But
349 registers used to access memory are referenced. SET_DEST is
350 also referenced if it is a ZERO_EXTRACT or SIGN_EXTRACT. */
352 mark_referenced_resources (SET_SRC (x), res, 0);
355 if (GET_CODE (x) == SIGN_EXTRACT || GET_CODE (x) == ZERO_EXTRACT)
356 mark_referenced_resources (x, res, 0);
357 else if (GET_CODE (x) == SUBREG)
359 if (GET_CODE (x) == MEM)
360 mark_referenced_resources (XEXP (x, 0), res, 0);
367 if (include_delayed_effects)
369 /* A CALL references memory, the frame pointer if it exists, the
370 stack pointer, any global registers and any registers given in
371 USE insns immediately in front of the CALL.
373 However, we may have moved some of the parameter loading insns
374 into the delay slot of this CALL. If so, the USE's for them
375 don't count and should be skipped. */
376 rtx insn = PREV_INSN (x);
381 /* If we are part of a delay slot sequence, point at the SEQUENCE. */
382 if (NEXT_INSN (insn) != x)
384 sequence = PATTERN (NEXT_INSN (insn));
385 seq_size = XVECLEN (sequence, 0);
386 if (GET_CODE (sequence) != SEQUENCE)
391 SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM);
392 if (frame_pointer_needed)
394 SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM);
395 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
396 SET_HARD_REG_BIT (res->regs, HARD_FRAME_POINTER_REGNUM);
400 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
402 SET_HARD_REG_BIT (res->regs, i);
404 /* Skip any labels between the CALL_INSN and possible USE insns. */
405 while (GET_CODE (insn) == CODE_LABEL)
406 insn = PREV_INSN (insn);
408 for ( ; (insn && GET_CODE (insn) == INSN
409 && GET_CODE (PATTERN (insn)) == USE);
410 insn = PREV_INSN (insn))
412 for (i = 1; i < seq_size; i++)
414 rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i));
415 if (GET_CODE (slot_pat) == SET
416 && rtx_equal_p (SET_DEST (slot_pat),
417 XEXP (PATTERN (insn), 0)))
421 mark_referenced_resources (XEXP (PATTERN (insn), 0), res, 0);
425 /* ... fall through to other INSN processing ... */
430 #ifdef INSN_REFERENCES_ARE_DELAYED
431 if (! include_delayed_effects
432 && INSN_REFERENCES_ARE_DELAYED (x))
436 /* No special processing, just speed up. */
437 mark_referenced_resources (PATTERN (x), res, include_delayed_effects);
441 /* Process each sub-expression and flag what it needs. */
442 format_ptr = GET_RTX_FORMAT (code);
443 for (i = 0; i < GET_RTX_LENGTH (code); i++)
444 switch (*format_ptr++)
447 mark_referenced_resources (XEXP (x, i), res, include_delayed_effects);
451 for (j = 0; j < XVECLEN (x, i); j++)
452 mark_referenced_resources (XVECEXP (x, i, j), res,
453 include_delayed_effects);
458 /* Given X, a part of an insn, and a pointer to a `struct resource', RES,
459 indicate which resources are modified by the insn. If INCLUDE_CALLED_ROUTINE
460 is nonzero, also mark resources potentially set by the called routine.
462 If IN_DEST is nonzero, it means we are inside a SET. Otherwise,
463 objects are being referenced instead of set.
465 We never mark the insn as modifying the condition code unless it explicitly
466 SETs CC0 even though this is not totally correct. The reason for this is
467 that we require a SET of CC0 to immediately precede the reference to CC0.
468 So if some other insn sets CC0 as a side-effect, we know it cannot affect
469 our computation and thus may be placed in a delay slot. */
472 mark_set_resources (x, res, in_dest, include_delayed_effects)
474 register struct resources *res;
476 int include_delayed_effects;
478 register enum rtx_code code;
480 register char *format_ptr;
498 /* These don't set any resources. */
507 /* Called routine modifies the condition code, memory, any registers
508 that aren't saved across calls, global registers and anything
509 explicitly CLOBBERed immediately after the CALL_INSN. */
511 if (include_delayed_effects)
513 rtx next = NEXT_INSN (x);
514 rtx prev = PREV_INSN (x);
516 res->cc = res->memory = 1;
517 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
518 if (call_used_regs[i] || global_regs[i])
519 SET_HARD_REG_BIT (res->regs, i);
521 /* If X is part of a delay slot sequence, then NEXT should be
522 the first insn after the sequence. */
523 if (NEXT_INSN (prev) != x)
524 next = NEXT_INSN (NEXT_INSN (prev));
526 /* Skip any possible labels between the CALL_INSN and CLOBBERs. */
527 while (GET_CODE (next) == CODE_LABEL)
528 next = NEXT_INSN (next);
530 for (; (next && GET_CODE (next) == INSN
531 && GET_CODE (PATTERN (next)) == CLOBBER);
532 next = NEXT_INSN (next))
533 mark_set_resources (XEXP (PATTERN (next), 0), res, 1, 0);
535 /* Check for a NOTE_INSN_SETJMP. If it exists, then we must
536 assume that this call can clobber any register. */
537 if (next && GET_CODE (next) == NOTE
538 && NOTE_LINE_NUMBER (next) == NOTE_INSN_SETJMP)
539 SET_HARD_REG_SET (res->regs);
542 /* ... and also what it's RTL says it modifies, if anything. */
547 /* An insn consisting of just a CLOBBER (or USE) is just for flow
548 and doesn't actually do anything, so we ignore it. */
550 #ifdef INSN_SETS_ARE_DELAYED
551 if (! include_delayed_effects
552 && INSN_SETS_ARE_DELAYED (x))
557 if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER)
562 /* If the source of a SET is a CALL, this is actually done by
563 the called routine. So only include it if we are to include the
564 effects of the calling routine. */
566 mark_set_resources (SET_DEST (x), res,
567 (include_delayed_effects
568 || GET_CODE (SET_SRC (x)) != CALL),
571 mark_set_resources (SET_SRC (x), res, 0, 0);
575 mark_set_resources (XEXP (x, 0), res, 1, 0);
579 for (i = 0; i < XVECLEN (x, 0); i++)
580 if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0))
581 && INSN_FROM_TARGET_P (XVECEXP (x, 0, i))))
582 mark_set_resources (XVECEXP (x, 0, i), res, 0,
583 include_delayed_effects);
590 mark_set_resources (XEXP (x, 0), res, 1, 0);
594 mark_set_resources (XEXP (x, 0), res, in_dest, 0);
595 mark_set_resources (XEXP (x, 1), res, 0, 0);
596 mark_set_resources (XEXP (x, 2), res, 0, 0);
603 res->volatil = MEM_VOLATILE_P (x);
606 mark_set_resources (XEXP (x, 0), res, 0, 0);
611 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
612 SET_HARD_REG_BIT (res->regs, REGNO (x) + i);
616 /* Process each sub-expression and flag what it needs. */
617 format_ptr = GET_RTX_FORMAT (code);
618 for (i = 0; i < GET_RTX_LENGTH (code); i++)
619 switch (*format_ptr++)
622 mark_set_resources (XEXP (x, i), res, in_dest, include_delayed_effects);
626 for (j = 0; j < XVECLEN (x, i); j++)
627 mark_set_resources (XVECEXP (x, i, j), res, in_dest,
628 include_delayed_effects);
633 /* Return TRUE if this insn should stop the search for insn to fill delay
634 slots. LABELS_P indicates that labels should terminate the search.
635 In all cases, jumps terminate the search. */
638 stop_search_p (insn, labels_p)
645 switch (GET_CODE (insn))
659 /* OK unless it contains a delay slot or is an `asm' insn of some type.
660 We don't know anything about these. */
661 return (GET_CODE (PATTERN (insn)) == SEQUENCE
662 || GET_CODE (PATTERN (insn)) == ASM_INPUT
663 || asm_noperands (PATTERN (insn)) >= 0);
670 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
671 resource set contains a volatile memory reference. Otherwise, return FALSE. */
674 resource_conflicts_p (res1, res2)
675 struct resources *res1, *res2;
677 if ((res1->cc && res2->cc) || (res1->memory && res2->memory)
678 || res1->volatil || res2->volatil)
682 return (res1->regs & res2->regs) != HARD_CONST (0);
687 for (i = 0; i < HARD_REG_SET_LONGS; i++)
688 if ((res1->regs[i] & res2->regs[i]) != 0)
695 /* Return TRUE if any resource marked in RES, a `struct resources', is
696 referenced by INSN. If INCLUDE_CALLED_ROUTINE is set, return if the called
697 routine is using those resources.
699 We compute this by computing all the resources referenced by INSN and
700 seeing if this conflicts with RES. It might be faster to directly check
701 ourselves, and this is the way it used to work, but it means duplicating
702 a large block of complex code. */
705 insn_references_resource_p (insn, res, include_delayed_effects)
707 register struct resources *res;
708 int include_delayed_effects;
710 struct resources insn_res;
712 CLEAR_RESOURCE (&insn_res);
713 mark_referenced_resources (insn, &insn_res, include_delayed_effects);
714 return resource_conflicts_p (&insn_res, res);
717 /* Return TRUE if INSN modifies resources that are marked in RES.
718 INCLUDE_CALLED_ROUTINE is set if the actions of that routine should be
719 included. CC0 is only modified if it is explicitly set; see comments
720 in front of mark_set_resources for details. */
723 insn_sets_resource_p (insn, res, include_delayed_effects)
725 register struct resources *res;
726 int include_delayed_effects;
728 struct resources insn_sets;
730 CLEAR_RESOURCE (&insn_sets);
731 mark_set_resources (insn, &insn_sets, 0, include_delayed_effects);
732 return resource_conflicts_p (&insn_sets, res);
735 /* Find a label at the end of the function or before a RETURN. If there is
743 /* If we found one previously, return it. */
744 if (end_of_function_label)
745 return end_of_function_label;
747 /* Otherwise, see if there is a label at the end of the function. If there
748 is, it must be that RETURN insns aren't needed, so that is our return
749 label and we don't have to do anything else. */
751 insn = get_last_insn ();
752 while (GET_CODE (insn) == NOTE
753 || (GET_CODE (insn) == INSN
754 && (GET_CODE (PATTERN (insn)) == USE
755 || GET_CODE (PATTERN (insn)) == CLOBBER)))
756 insn = PREV_INSN (insn);
758 /* When a target threads its epilogue we might already have a
759 suitable return insn. If so put a label before it for the
760 end_of_function_label. */
761 if (GET_CODE (insn) == BARRIER
762 && GET_CODE (PREV_INSN (insn)) == JUMP_INSN
763 && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN)
765 rtx temp = PREV_INSN (PREV_INSN (insn));
766 end_of_function_label = gen_label_rtx ();
767 LABEL_NUSES (end_of_function_label) = 0;
769 /* Put the label before an USE insns that may proceed the RETURN insn. */
770 while (GET_CODE (temp) == USE)
771 temp = PREV_INSN (temp);
773 emit_label_after (end_of_function_label, temp);
776 else if (GET_CODE (insn) == CODE_LABEL)
777 end_of_function_label = insn;
780 /* Otherwise, make a new label and emit a RETURN and BARRIER,
782 end_of_function_label = gen_label_rtx ();
783 LABEL_NUSES (end_of_function_label) = 0;
784 emit_label (end_of_function_label);
788 /* The return we make may have delay slots too. */
789 rtx insn = gen_return ();
790 insn = emit_jump_insn (insn);
792 if (num_delay_slots (insn) > 0)
793 obstack_ptr_grow (&unfilled_slots_obstack, insn);
798 /* Show one additional use for this label so it won't go away until
800 ++LABEL_NUSES (end_of_function_label);
802 return end_of_function_label;
805 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
806 the pattern of INSN with the SEQUENCE.
808 Chain the insns so that NEXT_INSN of each insn in the sequence points to
809 the next and NEXT_INSN of the last insn in the sequence points to
810 the first insn after the sequence. Similarly for PREV_INSN. This makes
811 it easier to scan all insns.
813 Returns the SEQUENCE that replaces INSN. */
816 emit_delay_sequence (insn, list, length, avail)
826 /* Allocate the the rtvec to hold the insns and the SEQUENCE. */
827 rtvec seqv = rtvec_alloc (length + 1);
828 rtx seq = gen_rtx (SEQUENCE, VOIDmode, seqv);
829 rtx seq_insn = make_insn_raw (seq);
830 rtx first = get_insns ();
831 rtx last = get_last_insn ();
833 /* Make a copy of the insn having delay slots. */
834 rtx delay_insn = copy_rtx (insn);
836 /* If INSN is followed by a BARRIER, delete the BARRIER since it will only
837 confuse further processing. Update LAST in case it was the last insn.
838 We will put the BARRIER back in later. */
839 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == BARRIER)
841 delete_insn (NEXT_INSN (insn));
842 last = get_last_insn ();
846 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
847 NEXT_INSN (seq_insn) = NEXT_INSN (insn);
848 PREV_INSN (seq_insn) = PREV_INSN (insn);
851 set_new_first_and_last_insn (first, seq_insn);
853 PREV_INSN (NEXT_INSN (seq_insn)) = seq_insn;
856 set_new_first_and_last_insn (seq_insn, last);
858 NEXT_INSN (PREV_INSN (seq_insn)) = seq_insn;
860 /* Build our SEQUENCE and rebuild the insn chain. */
861 XVECEXP (seq, 0, 0) = delay_insn;
862 INSN_DELETED_P (delay_insn) = 0;
863 PREV_INSN (delay_insn) = PREV_INSN (seq_insn);
865 for (li = list; li; li = XEXP (li, 1), i++)
867 rtx tem = XEXP (li, 0);
870 /* Show that this copy of the insn isn't deleted. */
871 INSN_DELETED_P (tem) = 0;
873 XVECEXP (seq, 0, i) = tem;
874 PREV_INSN (tem) = XVECEXP (seq, 0, i - 1);
875 NEXT_INSN (XVECEXP (seq, 0, i - 1)) = tem;
877 /* Remove any REG_DEAD notes because we can't rely on them now
878 that the insn has been moved. */
879 for (note = REG_NOTES (tem); note; note = XEXP (note, 1))
880 if (REG_NOTE_KIND (note) == REG_DEAD)
881 XEXP (note, 0) = const0_rtx;
884 NEXT_INSN (XVECEXP (seq, 0, length)) = NEXT_INSN (seq_insn);
886 /* If the previous insn is a SEQUENCE, update the NEXT_INSN pointer on the
887 last insn in that SEQUENCE to point to us. Similarly for the first
888 insn in the following insn if it is a SEQUENCE. */
890 if (PREV_INSN (seq_insn) && GET_CODE (PREV_INSN (seq_insn)) == INSN
891 && GET_CODE (PATTERN (PREV_INSN (seq_insn))) == SEQUENCE)
892 NEXT_INSN (XVECEXP (PATTERN (PREV_INSN (seq_insn)), 0,
893 XVECLEN (PATTERN (PREV_INSN (seq_insn)), 0) - 1))
896 if (NEXT_INSN (seq_insn) && GET_CODE (NEXT_INSN (seq_insn)) == INSN
897 && GET_CODE (PATTERN (NEXT_INSN (seq_insn))) == SEQUENCE)
898 PREV_INSN (XVECEXP (PATTERN (NEXT_INSN (seq_insn)), 0, 0)) = seq_insn;
900 /* If there used to be a BARRIER, put it back. */
902 emit_barrier_after (seq_insn);
910 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
911 be in the order in which the insns are to be executed. */
914 add_to_delay_list (insn, delay_list)
918 /* If we have an empty list, just make a new list element. If
919 INSN has it's block number recorded, clear it since we may
920 be moving the insn to a new block. */
924 struct target_info *tinfo;
926 for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME];
927 tinfo; tinfo = tinfo->next)
928 if (tinfo->uid == INSN_UID (insn))
934 return gen_rtx (INSN_LIST, VOIDmode, insn, NULL_RTX);
937 /* Otherwise this must be an INSN_LIST. Add INSN to the end of the
939 XEXP (delay_list, 1) = add_to_delay_list (insn, XEXP (delay_list, 1));
944 /* Delete INSN from the the delay slot of the insn that it is in. This may
945 produce an insn without anything in its delay slots. */
948 delete_from_delay_slot (insn)
951 rtx trial, seq_insn, seq, prev;
955 /* We first must find the insn containing the SEQUENCE with INSN in its
956 delay slot. Do this by finding an insn, TRIAL, where
957 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
960 PREV_INSN (NEXT_INSN (trial)) == trial;
961 trial = NEXT_INSN (trial))
964 seq_insn = PREV_INSN (NEXT_INSN (trial));
965 seq = PATTERN (seq_insn);
967 /* Create a delay list consisting of all the insns other than the one
968 we are deleting (unless we were the only one). */
969 if (XVECLEN (seq, 0) > 2)
970 for (i = 1; i < XVECLEN (seq, 0); i++)
971 if (XVECEXP (seq, 0, i) != insn)
972 delay_list = add_to_delay_list (XVECEXP (seq, 0, i), delay_list);
974 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
975 list, and rebuild the delay list if non-empty. */
976 prev = PREV_INSN (seq_insn);
977 trial = XVECEXP (seq, 0, 0);
978 delete_insn (seq_insn);
979 add_insn_after (trial, prev);
981 if (GET_CODE (trial) == JUMP_INSN
982 && (simplejump_p (trial) || GET_CODE (PATTERN (trial)) == RETURN))
983 emit_barrier_after (trial);
985 /* If there are any delay insns, remit them. Otherwise clear the
988 trial = emit_delay_sequence (trial, delay_list, XVECLEN (seq, 0) - 2, 0);
990 INSN_ANNULLED_BRANCH_P (trial) = 0;
992 INSN_FROM_TARGET_P (insn) = 0;
994 /* Show we need to fill this insn again. */
995 obstack_ptr_grow (&unfilled_slots_obstack, trial);
998 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
999 the insn that sets CC0 for it and delete it too. */
1002 delete_scheduled_jump (insn)
1005 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
1006 delete the insn that sets the condition code, but it is hard to find it.
1007 Since this case is rare anyway, don't bother trying; there would likely
1008 be other insns that became dead anyway, which we wouldn't know to
1012 if (reg_mentioned_p (cc0_rtx, insn))
1014 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
1016 /* If a reg-note was found, it points to an insn to set CC0. This
1017 insn is in the delay list of some other insn. So delete it from
1018 the delay list it was in. */
1021 if (! FIND_REG_INC_NOTE (XEXP (note, 0), NULL_RTX)
1022 && sets_cc0_p (PATTERN (XEXP (note, 0))) == 1)
1023 delete_from_delay_slot (XEXP (note, 0));
1027 /* The insn setting CC0 is our previous insn, but it may be in
1028 a delay slot. It will be the last insn in the delay slot, if
1030 rtx trial = previous_insn (insn);
1031 if (GET_CODE (trial) == NOTE)
1032 trial = prev_nonnote_insn (trial);
1033 if (sets_cc0_p (PATTERN (trial)) != 1
1034 || FIND_REG_INC_NOTE (trial, 0))
1036 if (PREV_INSN (NEXT_INSN (trial)) == trial)
1037 delete_insn (trial);
1039 delete_from_delay_slot (trial);
1047 /* Counters for delay-slot filling. */
1049 #define NUM_REORG_FUNCTIONS 2
1050 #define MAX_DELAY_HISTOGRAM 3
1051 #define MAX_REORG_PASSES 2
1053 static int num_insns_needing_delays[NUM_REORG_FUNCTIONS][MAX_REORG_PASSES];
1055 static int num_filled_delays[NUM_REORG_FUNCTIONS][MAX_DELAY_HISTOGRAM+1][MAX_REORG_PASSES];
1057 static int reorg_pass_number;
1060 note_delay_statistics (slots_filled, index)
1061 int slots_filled, index;
1063 num_insns_needing_delays[index][reorg_pass_number]++;
1064 if (slots_filled > MAX_DELAY_HISTOGRAM)
1065 slots_filled = MAX_DELAY_HISTOGRAM;
1066 num_filled_delays[index][slots_filled][reorg_pass_number]++;
1069 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
1071 /* Optimize the following cases:
1073 1. When a conditional branch skips over only one instruction,
1074 use an annulling branch and put that insn in the delay slot.
1075 Use either a branch that annuls when the condition if true or
1076 invert the test with a branch that annuls when the condition is
1077 false. This saves insns, since otherwise we must copy an insn
1080 (orig) (skip) (otherwise)
1081 Bcc.n L1 Bcc',a L1 Bcc,a L1'
1088 2. When a conditional branch skips over only one instruction,
1089 and after that, it unconditionally branches somewhere else,
1090 perform the similar optimization. This saves executing the
1091 second branch in the case where the inverted condition is true.
1098 INSN is a JUMP_INSN.
1100 This should be expanded to skip over N insns, where N is the number
1101 of delay slots required. */
1104 optimize_skip (insn)
1107 register rtx trial = next_nonnote_insn (insn);
1108 rtx next_trial = next_active_insn (trial);
1113 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1116 || GET_CODE (trial) != INSN
1117 || GET_CODE (PATTERN (trial)) == SEQUENCE
1118 || recog_memoized (trial) < 0
1119 || (! eligible_for_annul_false (insn, 0, trial, flags)
1120 && ! eligible_for_annul_true (insn, 0, trial, flags)))
1123 /* There are two cases where we are just executing one insn (we assume
1124 here that a branch requires only one insn; this should be generalized
1125 at some point): Where the branch goes around a single insn or where
1126 we have one insn followed by a branch to the same label we branch to.
1127 In both of these cases, inverting the jump and annulling the delay
1128 slot give the same effect in fewer insns. */
1129 if ((next_trial == next_active_insn (JUMP_LABEL (insn)))
1131 && GET_CODE (next_trial) == JUMP_INSN
1132 && JUMP_LABEL (insn) == JUMP_LABEL (next_trial)
1133 && (simplejump_p (next_trial)
1134 || GET_CODE (PATTERN (next_trial)) == RETURN)))
1136 if (eligible_for_annul_false (insn, 0, trial, flags))
1138 if (invert_jump (insn, JUMP_LABEL (insn)))
1139 INSN_FROM_TARGET_P (trial) = 1;
1140 else if (! eligible_for_annul_true (insn, 0, trial, flags))
1144 delay_list = add_to_delay_list (trial, NULL_RTX);
1145 next_trial = next_active_insn (trial);
1146 update_block (trial, trial);
1147 delete_insn (trial);
1149 /* Also, if we are targeting an unconditional
1150 branch, thread our jump to the target of that branch. Don't
1151 change this into a RETURN here, because it may not accept what
1152 we have in the delay slot. We'll fix this up later. */
1153 if (next_trial && GET_CODE (next_trial) == JUMP_INSN
1154 && (simplejump_p (next_trial)
1155 || GET_CODE (PATTERN (next_trial)) == RETURN))
1157 target_label = JUMP_LABEL (next_trial);
1158 if (target_label == 0)
1159 target_label = find_end_label ();
1160 reorg_redirect_jump (insn, target_label);
1163 INSN_ANNULLED_BRANCH_P (insn) = 1;
1171 /* Encode and return branch direction and prediction information for
1172 INSN assuming it will jump to LABEL.
1174 Non conditional branches return no direction information and
1175 are predicted as very likely taken. */
1177 get_jump_flags (insn, label)
1182 /* get_jump_flags can be passed any insn with delay slots, these may
1183 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
1184 direction information, and only if they are conditional jumps.
1186 If LABEL is zero, then there is no way to determine the branch
1188 if (GET_CODE (insn) == JUMP_INSN
1189 && condjump_p (insn)
1190 && INSN_UID (insn) <= max_uid
1192 && INSN_UID (label) <= max_uid)
1194 = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)])
1195 ? ATTR_FLAG_forward : ATTR_FLAG_backward;
1196 /* No valid direction information. */
1200 /* If insn is a conditional branch call mostly_true_jump to get
1201 determine the branch prediction.
1203 Non conditional branches are predicted as very likely taken. */
1204 if (GET_CODE (insn) == JUMP_INSN
1205 && condjump_p (insn))
1209 prediction = mostly_true_jump (insn, get_branch_condition (insn, label));
1213 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1216 flags |= ATTR_FLAG_likely;
1219 flags |= ATTR_FLAG_unlikely;
1222 flags |= (ATTR_FLAG_very_unlikely | ATTR_FLAG_unlikely);
1230 flags |= (ATTR_FLAG_very_likely | ATTR_FLAG_likely);
1235 /* Return 1 if DEST is a destination that will be branched to rarely (the
1236 return point of a function); return 2 if DEST will be branched to very
1237 rarely (a call to a function that doesn't return). Otherwise,
1241 rare_destination (insn)
1246 for (; insn; insn = NEXT_INSN (insn))
1248 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
1249 insn = XVECEXP (PATTERN (insn), 0, 0);
1251 switch (GET_CODE (insn))
1256 /* A BARRIER can either be after a JUMP_INSN or a CALL_INSN. We
1257 don't scan past JUMP_INSNs, so any barrier we find here must
1258 have been after a CALL_INSN and hence mean the call doesn't
1262 if (GET_CODE (PATTERN (insn)) == RETURN)
1264 else if (simplejump_p (insn)
1265 && jump_count++ < 10)
1266 insn = JUMP_LABEL (insn);
1272 /* If we got here it means we hit the end of the function. So this
1273 is an unlikely destination. */
1278 /* Return truth value of the statement that this branch
1279 is mostly taken. If we think that the branch is extremely likely
1280 to be taken, we return 2. If the branch is slightly more likely to be
1281 taken, return 1. If the branch is slightly less likely to be taken,
1282 return 0 and if the branch is highly unlikely to be taken, return -1.
1284 CONDITION, if non-zero, is the condition that JUMP_INSN is testing. */
1287 mostly_true_jump (jump_insn, condition)
1288 rtx jump_insn, condition;
1290 rtx target_label = JUMP_LABEL (jump_insn);
1292 int rare_dest = rare_destination (target_label);
1293 int rare_fallthrough = rare_destination (NEXT_INSN (jump_insn));
1295 /* If this is a branch outside a loop, it is highly unlikely. */
1296 if (GET_CODE (PATTERN (jump_insn)) == SET
1297 && GET_CODE (SET_SRC (PATTERN (jump_insn))) == IF_THEN_ELSE
1298 && ((GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 1)) == LABEL_REF
1299 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 1)))
1300 || (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 2)) == LABEL_REF
1301 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn)), 2)))))
1306 /* If this is the test of a loop, it is very likely true. We scan
1307 backwards from the target label. If we find a NOTE_INSN_LOOP_BEG
1308 before the next real insn, we assume the branch is to the top of
1310 for (insn = PREV_INSN (target_label);
1311 insn && GET_CODE (insn) == NOTE;
1312 insn = PREV_INSN (insn))
1313 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1316 /* If this is a jump to the test of a loop, it is likely true. We scan
1317 forwards from the target label. If we find a NOTE_INSN_LOOP_VTOP
1318 before the next real insn, we assume the branch is to the loop branch
1320 for (insn = NEXT_INSN (target_label);
1321 insn && GET_CODE (insn) == NOTE;
1322 insn = PREV_INSN (insn))
1323 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_VTOP)
1327 /* Look at the relative rarities of the fallthough and destination. If
1328 they differ, we can predict the branch that way. */
1330 switch (rare_fallthrough - rare_dest)
1344 /* If we couldn't figure out what this jump was, assume it won't be
1345 taken. This should be rare. */
1349 /* EQ tests are usually false and NE tests are usually true. Also,
1350 most quantities are positive, so we can make the appropriate guesses
1351 about signed comparisons against zero. */
1352 switch (GET_CODE (condition))
1355 /* Unconditional branch. */
1363 if (XEXP (condition, 1) == const0_rtx)
1368 if (XEXP (condition, 1) == const0_rtx)
1373 /* Predict backward branches usually take, forward branches usually not. If
1374 we don't know whether this is forward or backward, assume the branch
1375 will be taken, since most are. */
1376 return (target_label == 0 || INSN_UID (jump_insn) > max_uid
1377 || INSN_UID (target_label) > max_uid
1378 || (uid_to_ruid[INSN_UID (jump_insn)]
1379 > uid_to_ruid[INSN_UID (target_label)]));;
1382 /* Return the condition under which INSN will branch to TARGET. If TARGET
1383 is zero, return the condition under which INSN will return. If INSN is
1384 an unconditional branch, return const_true_rtx. If INSN isn't a simple
1385 type of jump, or it doesn't go to TARGET, return 0. */
1388 get_branch_condition (insn, target)
1392 rtx pat = PATTERN (insn);
1395 if (GET_CODE (pat) == RETURN)
1396 return target == 0 ? const_true_rtx : 0;
1398 else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
1401 src = SET_SRC (pat);
1402 if (GET_CODE (src) == LABEL_REF && XEXP (src, 0) == target)
1403 return const_true_rtx;
1405 else if (GET_CODE (src) == IF_THEN_ELSE
1406 && ((target == 0 && GET_CODE (XEXP (src, 1)) == RETURN)
1407 || (GET_CODE (XEXP (src, 1)) == LABEL_REF
1408 && XEXP (XEXP (src, 1), 0) == target))
1409 && XEXP (src, 2) == pc_rtx)
1410 return XEXP (src, 0);
1412 else if (GET_CODE (src) == IF_THEN_ELSE
1413 && ((target == 0 && GET_CODE (XEXP (src, 2)) == RETURN)
1414 || (GET_CODE (XEXP (src, 2)) == LABEL_REF
1415 && XEXP (XEXP (src, 2), 0) == target))
1416 && XEXP (src, 1) == pc_rtx)
1417 return gen_rtx (reverse_condition (GET_CODE (XEXP (src, 0))),
1418 GET_MODE (XEXP (src, 0)),
1419 XEXP (XEXP (src, 0), 0), XEXP (XEXP (src, 0), 1));
1424 /* Return non-zero if CONDITION is more strict than the condition of
1425 INSN, i.e., if INSN will always branch if CONDITION is true. */
1428 condition_dominates_p (condition, insn)
1432 rtx other_condition = get_branch_condition (insn, JUMP_LABEL (insn));
1433 enum rtx_code code = GET_CODE (condition);
1434 enum rtx_code other_code;
1436 if (rtx_equal_p (condition, other_condition)
1437 || other_condition == const_true_rtx)
1440 else if (condition == const_true_rtx || other_condition == 0)
1443 other_code = GET_CODE (other_condition);
1444 if (GET_RTX_LENGTH (code) != 2 || GET_RTX_LENGTH (other_code) != 2
1445 || ! rtx_equal_p (XEXP (condition, 0), XEXP (other_condition, 0))
1446 || ! rtx_equal_p (XEXP (condition, 1), XEXP (other_condition, 1)))
1449 return comparison_dominates_p (code, other_code);
1452 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1453 any insns already in the delay slot of JUMP. */
1456 redirect_with_delay_slots_safe_p (jump, newlabel, seq)
1457 rtx jump, newlabel, seq;
1459 int flags, slots, i;
1460 rtx pat = PATTERN (seq);
1462 /* Make sure all the delay slots of this jump would still
1463 be valid after threading the jump. If they are still
1464 valid, then return non-zero. */
1466 flags = get_jump_flags (jump, newlabel);
1467 for (i = 1; i < XVECLEN (pat, 0); i++)
1469 #ifdef ANNUL_IFFALSE_SLOTS
1470 (INSN_ANNULLED_BRANCH_P (jump)
1471 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1472 ? eligible_for_annul_false (jump, i - 1,
1473 XVECEXP (pat, 0, i), flags) :
1475 #ifdef ANNUL_IFTRUE_SLOTS
1476 (INSN_ANNULLED_BRANCH_P (jump)
1477 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
1478 ? eligible_for_annul_true (jump, i - 1,
1479 XVECEXP (pat, 0, i), flags) :
1481 eligible_for_delay (jump, i -1, XVECEXP (pat, 0, i), flags)))
1484 return (i == XVECLEN (pat, 0));
1488 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1489 the condition tested by INSN is CONDITION and the resources shown in
1490 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1491 from SEQ's delay list, in addition to whatever insns it may execute
1492 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1493 needed while searching for delay slot insns. Return the concatenated
1494 delay list if possible, otherwise, return 0.
1496 SLOTS_TO_FILL is the total number of slots required by INSN, and
1497 PSLOTS_FILLED points to the number filled so far (also the number of
1498 insns in DELAY_LIST). It is updated with the number that have been
1499 filled from the SEQUENCE, if any.
1501 PANNUL_P points to a non-zero value if we already know that we need
1502 to annul INSN. If this routine determines that annulling is needed,
1503 it may set that value non-zero.
1505 PNEW_THREAD points to a location that is to receive the place at which
1506 execution should continue. */
1509 steal_delay_list_from_target (insn, condition, seq, delay_list,
1510 sets, needed, other_needed,
1511 slots_to_fill, pslots_filled, pannul_p,
1513 rtx insn, condition;
1516 struct resources *sets, *needed, *other_needed;
1523 int slots_remaining = slots_to_fill - *pslots_filled;
1524 int total_slots_filled = *pslots_filled;
1525 rtx new_delay_list = 0;
1526 int must_annul = *pannul_p;
1529 /* We can't do anything if there are more delay slots in SEQ than we
1530 can handle, or if we don't know that it will be a taken branch.
1532 We know that it will be a taken branch if it is either an unconditional
1533 branch or a conditional branch with a stricter branch condition. */
1535 if (XVECLEN (seq, 0) - 1 > slots_remaining
1536 || ! condition_dominates_p (condition, XVECEXP (seq, 0, 0)))
1539 for (i = 1; i < XVECLEN (seq, 0); i++)
1541 rtx trial = XVECEXP (seq, 0, i);
1544 if (insn_references_resource_p (trial, sets, 0)
1545 || insn_sets_resource_p (trial, needed, 0)
1546 || insn_sets_resource_p (trial, sets, 0)
1548 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1550 || find_reg_note (trial, REG_CC_USER, NULL_RTX)
1552 /* If TRIAL is from the fallthrough code of an annulled branch insn
1553 in SEQ, we cannot use it. */
1554 || (INSN_ANNULLED_BRANCH_P (XVECEXP (seq, 0, 0))
1555 && ! INSN_FROM_TARGET_P (trial)))
1558 /* If this insn was already done (usually in a previous delay slot),
1559 pretend we put it in our delay slot. */
1560 if (redundant_insn_p (trial, insn, new_delay_list))
1563 /* We will end up re-vectoring this branch, so compute flags
1564 based on jumping to the new label. */
1565 flags = get_jump_flags (insn, JUMP_LABEL (XVECEXP (seq, 0, 0)));
1568 && ((condition == const_true_rtx
1569 || (! insn_sets_resource_p (trial, other_needed, 0)
1570 && ! may_trap_p (PATTERN (trial)))))
1571 ? eligible_for_delay (insn, total_slots_filled, trial, flags)
1573 eligible_for_annul_false (insn, total_slots_filled, trial, flags)))
1575 temp = copy_rtx (trial);
1576 INSN_FROM_TARGET_P (temp) = 1;
1577 new_delay_list = add_to_delay_list (temp, new_delay_list);
1578 total_slots_filled++;
1580 if (--slots_remaining == 0)
1587 /* Show the place to which we will be branching. */
1588 *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0)));
1590 /* Add any new insns to the delay list and update the count of the
1591 number of slots filled. */
1592 *pslots_filled = total_slots_filled;
1593 *pannul_p = must_annul;
1595 if (delay_list == 0)
1596 return new_delay_list;
1598 for (temp = new_delay_list; temp; temp = XEXP (temp, 1))
1599 delay_list = add_to_delay_list (XEXP (temp, 0), delay_list);
1604 /* Similar to steal_delay_list_from_target except that SEQ is on the
1605 fallthrough path of INSN. Here we only do something if the delay insn
1606 of SEQ is an unconditional branch. In that case we steal its delay slot
1607 for INSN since unconditional branches are much easier to fill. */
1610 steal_delay_list_from_fallthrough (insn, condition, seq,
1611 delay_list, sets, needed, other_needed,
1612 slots_to_fill, pslots_filled, pannul_p)
1613 rtx insn, condition;
1616 struct resources *sets, *needed, *other_needed;
1624 flags = get_jump_flags (insn, JUMP_LABEL (insn));
1626 /* We can't do anything if SEQ's delay insn isn't an
1627 unconditional branch. */
1629 if (! simplejump_p (XVECEXP (seq, 0, 0))
1630 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN)
1633 for (i = 1; i < XVECLEN (seq, 0); i++)
1635 rtx trial = XVECEXP (seq, 0, i);
1637 /* If TRIAL sets CC0, stealing it will move it too far from the use
1639 if (insn_references_resource_p (trial, sets, 0)
1640 || insn_sets_resource_p (trial, needed, 0)
1641 || insn_sets_resource_p (trial, sets, 0)
1643 || sets_cc0_p (PATTERN (trial))
1649 /* If this insn was already done, we don't need it. */
1650 if (redundant_insn_p (trial, insn, delay_list))
1652 delete_from_delay_slot (trial);
1657 && ((condition == const_true_rtx
1658 || (! insn_sets_resource_p (trial, other_needed, 0)
1659 && ! may_trap_p (PATTERN (trial)))))
1660 ? eligible_for_delay (insn, *pslots_filled, trial, flags)
1662 eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
1664 delete_from_delay_slot (trial);
1665 delay_list = add_to_delay_list (trial, delay_list);
1667 if (++(*pslots_filled) == slots_to_fill)
1677 /* Try merging insns starting at THREAD which match exactly the insns in
1680 If all insns were matched and the insn was previously annulling, the
1681 annul bit will be cleared.
1683 For each insn that is merged, if the branch is or will be non-annulling,
1684 we delete the merged insn. */
1687 try_merge_delay_insns (insn, thread)
1690 rtx trial, next_trial;
1691 rtx delay_insn = XVECEXP (PATTERN (insn), 0, 0);
1692 int annul_p = INSN_ANNULLED_BRANCH_P (delay_insn);
1693 int slot_number = 1;
1694 int num_slots = XVECLEN (PATTERN (insn), 0);
1695 rtx next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1696 struct resources set, needed;
1697 rtx merged_insns = 0;
1701 flags = get_jump_flags (delay_insn, JUMP_LABEL (delay_insn));
1703 CLEAR_RESOURCE (&needed);
1704 CLEAR_RESOURCE (&set);
1706 /* If this is not an annulling branch, take into account anything needed in
1707 NEXT_TO_MATCH. This prevents two increments from being incorrectly
1708 folded into one. If we are annulling, this would be the correct
1709 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1710 will essentially disable this optimization. This method is somewhat of
1711 a kludge, but I don't see a better way.) */
1713 mark_referenced_resources (next_to_match, &needed, 1);
1715 for (trial = thread; !stop_search_p (trial, 1); trial = next_trial)
1717 rtx pat = PATTERN (trial);
1719 next_trial = next_nonnote_insn (trial);
1721 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1722 if (GET_CODE (trial) == INSN
1723 && (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER))
1726 if (GET_CODE (next_to_match) == GET_CODE (trial)
1728 /* We can't share an insn that sets cc0. */
1729 && ! sets_cc0_p (pat)
1731 && ! insn_references_resource_p (trial, &set, 1)
1732 && ! insn_sets_resource_p (trial, &set, 1)
1733 && ! insn_sets_resource_p (trial, &needed, 1)
1734 && (trial = try_split (pat, trial, 0)) != 0
1735 && rtx_equal_p (PATTERN (next_to_match), PATTERN (trial))
1736 /* Have to test this condition if annul condition is different
1737 from (and less restrictive than) non-annulling one. */
1738 && eligible_for_delay (delay_insn, slot_number - 1, trial, flags))
1740 next_trial = next_nonnote_insn (trial);
1744 update_block (trial, thread);
1745 delete_insn (trial);
1746 INSN_FROM_TARGET_P (next_to_match) = 0;
1749 merged_insns = gen_rtx (INSN_LIST, VOIDmode, trial, merged_insns);
1751 if (++slot_number == num_slots)
1754 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1756 mark_referenced_resources (next_to_match, &needed, 1);
1759 mark_set_resources (trial, &set, 0, 1);
1760 mark_referenced_resources (trial, &needed, 1);
1763 /* See if we stopped on a filled insn. If we did, try to see if its
1764 delay slots match. */
1765 if (slot_number != num_slots
1766 && trial && GET_CODE (trial) == INSN
1767 && GET_CODE (PATTERN (trial)) == SEQUENCE
1768 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (PATTERN (trial), 0, 0)))
1770 rtx pat = PATTERN (trial);
1772 for (i = 1; i < XVECLEN (pat, 0); i++)
1774 rtx dtrial = XVECEXP (pat, 0, i);
1776 if (! insn_references_resource_p (dtrial, &set, 1)
1777 && ! insn_sets_resource_p (dtrial, &set, 1)
1778 && ! insn_sets_resource_p (dtrial, &needed, 1)
1780 && ! sets_cc0_p (PATTERN (dtrial))
1782 && rtx_equal_p (PATTERN (next_to_match), PATTERN (dtrial))
1783 && eligible_for_delay (delay_insn, slot_number - 1, dtrial, flags))
1787 update_block (dtrial, thread);
1788 delete_from_delay_slot (dtrial);
1789 INSN_FROM_TARGET_P (next_to_match) = 0;
1792 merged_insns = gen_rtx (INSN_LIST, SImode, dtrial,
1795 if (++slot_number == num_slots)
1798 next_to_match = XVECEXP (PATTERN (insn), 0, slot_number);
1803 /* If all insns in the delay slot have been matched and we were previously
1804 annulling the branch, we need not any more. In that case delete all the
1805 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn the
1806 the delay list so that we know that it isn't only being used at the
1808 if (next_to_match == 0 && annul_p)
1810 for (; merged_insns; merged_insns = XEXP (merged_insns, 1))
1812 if (GET_MODE (merged_insns) == SImode)
1814 update_block (XEXP (merged_insns, 0), thread);
1815 delete_from_delay_slot (XEXP (merged_insns, 0));
1819 update_block (XEXP (merged_insns, 0), thread);
1820 delete_insn (XEXP (merged_insns, 0));
1824 INSN_ANNULLED_BRANCH_P (delay_insn) = 0;
1826 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1827 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) = 0;
1831 /* See if INSN is redundant with an insn in front of TARGET. Often this
1832 is called when INSN is a candidate for a delay slot of TARGET.
1833 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1834 of INSN. Often INSN will be redundant with an insn in a delay slot of
1835 some previous insn. This happens when we have a series of branches to the
1836 same label; in that case the first insn at the target might want to go
1837 into each of the delay slots.
1839 If we are not careful, this routine can take up a significant fraction
1840 of the total compilation time (4%), but only wins rarely. Hence we
1841 speed this routine up by making two passes. The first pass goes back
1842 until it hits a label and sees if it find an insn with an identical
1843 pattern. Only in this (relatively rare) event does it check for
1846 We do not split insns we encounter. This could cause us not to find a
1847 redundant insn, but the cost of splitting seems greater than the possible
1848 gain in rare cases. */
1851 redundant_insn_p (insn, target, delay_list)
1856 rtx target_main = target;
1857 rtx ipat = PATTERN (insn);
1859 struct resources needed, set;
1862 /* Scan backwards looking for a match. */
1863 for (trial = PREV_INSN (target); trial; trial = PREV_INSN (trial))
1865 if (GET_CODE (trial) == CODE_LABEL)
1868 if (GET_RTX_CLASS (GET_CODE (trial)) != 'i')
1871 pat = PATTERN (trial);
1872 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
1875 if (GET_CODE (pat) == SEQUENCE)
1877 /* Stop for a CALL and its delay slots because it is difficult to
1878 track its resource needs correctly. */
1879 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
1882 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1883 slots because it is difficult to track its resource needs
1886 #ifdef INSN_SETS_ARE_DELAYED
1887 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
1891 #ifdef INSN_REFERENCES_ARE_DELAYED
1892 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
1896 /* See if any of the insns in the delay slot match, updating
1897 resource requirements as we go. */
1898 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
1899 if (GET_CODE (XVECEXP (pat, 0, i)) == GET_CODE (insn)
1900 && rtx_equal_p (PATTERN (XVECEXP (pat, 0, i)), ipat))
1903 /* If found a match, exit this loop early. */
1908 else if (GET_CODE (trial) == GET_CODE (insn) && rtx_equal_p (pat, ipat))
1912 /* If we didn't find an insn that matches, return 0. */
1916 /* See what resources this insn sets and needs. If they overlap, or
1917 if this insn references CC0, it can't be redundant. */
1919 CLEAR_RESOURCE (&needed);
1920 CLEAR_RESOURCE (&set);
1921 mark_set_resources (insn, &set, 0, 1);
1922 mark_referenced_resources (insn, &needed, 1);
1924 /* If TARGET is a SEQUENCE, get the main insn. */
1925 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
1926 target_main = XVECEXP (PATTERN (target), 0, 0);
1928 if (resource_conflicts_p (&needed, &set)
1930 || reg_mentioned_p (cc0_rtx, ipat)
1932 /* The insn requiring the delay may not set anything needed or set by
1934 || insn_sets_resource_p (target_main, &needed, 1)
1935 || insn_sets_resource_p (target_main, &set, 1))
1938 /* Insns we pass may not set either NEEDED or SET, so merge them for
1940 needed.memory |= set.memory;
1941 IOR_HARD_REG_SET (needed.regs, set.regs);
1943 /* This insn isn't redundant if it conflicts with an insn that either is
1944 or will be in a delay slot of TARGET. */
1948 if (insn_sets_resource_p (XEXP (delay_list, 0), &needed, 1))
1950 delay_list = XEXP (delay_list, 1);
1953 if (GET_CODE (target) == INSN && GET_CODE (PATTERN (target)) == SEQUENCE)
1954 for (i = 1; i < XVECLEN (PATTERN (target), 0); i++)
1955 if (insn_sets_resource_p (XVECEXP (PATTERN (target), 0, i), &needed, 1))
1958 /* Scan backwards until we reach a label or an insn that uses something
1959 INSN sets or sets something insn uses or sets. */
1961 for (trial = PREV_INSN (target);
1962 trial && GET_CODE (trial) != CODE_LABEL;
1963 trial = PREV_INSN (trial))
1965 if (GET_CODE (trial) != INSN && GET_CODE (trial) != CALL_INSN
1966 && GET_CODE (trial) != JUMP_INSN)
1969 pat = PATTERN (trial);
1970 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
1973 if (GET_CODE (pat) == SEQUENCE)
1975 /* If this is a CALL_INSN and its delay slots, it is hard to track
1976 the resource needs properly, so give up. */
1977 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL_INSN)
1980 /* If this this is an INSN or JUMP_INSN with delayed effects, it
1981 is hard to track the resource needs properly, so give up. */
1983 #ifdef INSN_SETS_ARE_DELAYED
1984 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat, 0, 0)))
1988 #ifdef INSN_REFERENCES_ARE_DELAYED
1989 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat, 0, 0)))
1993 /* See if any of the insns in the delay slot match, updating
1994 resource requirements as we go. */
1995 for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
1997 rtx candidate = XVECEXP (pat, 0, i);
1999 /* If an insn will be annulled if the branch is false, it isn't
2000 considered as a possible duplicate insn. */
2001 if (rtx_equal_p (PATTERN (candidate), ipat)
2002 && ! (INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2003 && INSN_FROM_TARGET_P (candidate)))
2005 /* Show that this insn will be used in the sequel. */
2006 INSN_FROM_TARGET_P (candidate) = 0;
2010 /* Unless this is an annulled insn from the target of a branch,
2011 we must stop if it sets anything needed or set by INSN. */
2012 if ((! INSN_ANNULLED_BRANCH_P (XVECEXP (pat, 0, 0))
2013 || ! INSN_FROM_TARGET_P (candidate))
2014 && insn_sets_resource_p (candidate, &needed, 1))
2019 /* If the insn requiring the delay slot conflicts with INSN, we
2021 if (insn_sets_resource_p (XVECEXP (pat, 0, 0), &needed, 1))
2026 /* See if TRIAL is the same as INSN. */
2027 pat = PATTERN (trial);
2028 if (rtx_equal_p (pat, ipat))
2031 /* Can't go any further if TRIAL conflicts with INSN. */
2032 if (insn_sets_resource_p (trial, &needed, 1))
2040 /* Return 1 if THREAD can only be executed in one way. If LABEL is non-zero,
2041 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
2042 is non-zero, we are allowed to fall into this thread; otherwise, we are
2045 If LABEL is used more than one or we pass a label other than LABEL before
2046 finding an active insn, we do not own this thread. */
2049 own_thread_p (thread, label, allow_fallthrough)
2052 int allow_fallthrough;
2057 /* We don't own the function end. */
2061 /* Get the first active insn, or THREAD, if it is an active insn. */
2062 active_insn = next_active_insn (PREV_INSN (thread));
2064 for (insn = thread; insn != active_insn; insn = NEXT_INSN (insn))
2065 if (GET_CODE (insn) == CODE_LABEL
2066 && (insn != label || LABEL_NUSES (insn) != 1))
2069 if (allow_fallthrough)
2072 /* Ensure that we reach a BARRIER before any insn or label. */
2073 for (insn = prev_nonnote_insn (thread);
2074 insn == 0 || GET_CODE (insn) != BARRIER;
2075 insn = prev_nonnote_insn (insn))
2077 || GET_CODE (insn) == CODE_LABEL
2078 || (GET_CODE (insn) == INSN
2079 && GET_CODE (PATTERN (insn)) != USE
2080 && GET_CODE (PATTERN (insn)) != CLOBBER))
2086 /* Find the number of the basic block that starts closest to INSN. Return -1
2087 if we couldn't find such a basic block. */
2090 find_basic_block (insn)
2095 /* Scan backwards to the previous BARRIER. Then see if we can find a
2096 label that starts a basic block. Return the basic block number. */
2098 for (insn = prev_nonnote_insn (insn);
2099 insn && GET_CODE (insn) != BARRIER;
2100 insn = prev_nonnote_insn (insn))
2103 /* The start of the function is basic block zero. */
2107 /* See if any of the upcoming CODE_LABELs start a basic block. If we reach
2108 anything other than a CODE_LABEL or note, we can't find this code. */
2109 for (insn = next_nonnote_insn (insn);
2110 insn && GET_CODE (insn) == CODE_LABEL;
2111 insn = next_nonnote_insn (insn))
2113 for (i = 0; i < n_basic_blocks; i++)
2114 if (insn == basic_block_head[i])
2121 /* Called when INSN is being moved from a location near the target of a jump.
2122 We leave a marker of the form (use (INSN)) immediately in front
2123 of WHERE for mark_target_live_regs. These markers will be deleted when
2126 We used to try to update the live status of registers if WHERE is at
2127 the start of a basic block, but that can't work since we may remove a
2128 BARRIER in relax_delay_slots. */
2131 update_block (insn, where)
2137 /* Ignore if this was in a delay slot and it came from the target of
2139 if (INSN_FROM_TARGET_P (insn))
2142 emit_insn_before (gen_rtx (USE, VOIDmode, insn), where);
2144 /* INSN might be making a value live in a block where it didn't use to
2145 be. So recompute liveness information for this block. */
2147 b = find_basic_block (insn);
2152 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
2153 the basic block containing the jump. */
2156 reorg_redirect_jump (jump, nlabel)
2160 int b = find_basic_block (jump);
2165 return redirect_jump (jump, nlabel);
2168 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
2169 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
2170 that reference values used in INSN. If we find one, then we move the
2171 REG_DEAD note to INSN.
2173 This is needed to handle the case where an later insn (after INSN) has a
2174 REG_DEAD note for a register used by INSN, and this later insn subsequently
2175 gets moved before a CODE_LABEL because it is a redundant insn. In this
2176 case, mark_target_live_regs may be confused into thinking the register
2177 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
2180 update_reg_dead_notes (insn, delayed_insn)
2181 rtx insn, delayed_insn;
2185 for (p = next_nonnote_insn (insn); p != delayed_insn;
2186 p = next_nonnote_insn (p))
2187 for (link = REG_NOTES (p); link; link = next)
2189 next = XEXP (link, 1);
2191 if (REG_NOTE_KIND (link) != REG_DEAD
2192 || GET_CODE (XEXP (link, 0)) != REG)
2195 if (reg_referenced_p (XEXP (link, 0), PATTERN (insn)))
2197 /* Move the REG_DEAD note from P to INSN. */
2198 remove_note (p, link);
2199 XEXP (link, 1) = REG_NOTES (insn);
2200 REG_NOTES (insn) = link;
2205 /* Marks registers possibly live at the current place being scanned by
2206 mark_target_live_regs. Used only by next two function. */
2208 static HARD_REG_SET current_live_regs;
2210 /* Marks registers for which we have seen a REG_DEAD note but no assignment.
2211 Also only used by the next two functions. */
2213 static HARD_REG_SET pending_dead_regs;
2215 /* Utility function called from mark_target_live_regs via note_stores.
2216 It deadens any CLOBBERed registers and livens any SET registers. */
2219 update_live_status (dest, x)
2223 int first_regno, last_regno;
2226 if (GET_CODE (dest) != REG
2227 && (GET_CODE (dest) != SUBREG || GET_CODE (SUBREG_REG (dest)) != REG))
2230 if (GET_CODE (dest) == SUBREG)
2231 first_regno = REGNO (SUBREG_REG (dest)) + SUBREG_WORD (dest);
2233 first_regno = REGNO (dest);
2235 last_regno = first_regno + HARD_REGNO_NREGS (first_regno, GET_MODE (dest));
2237 if (GET_CODE (x) == CLOBBER)
2238 for (i = first_regno; i < last_regno; i++)
2239 CLEAR_HARD_REG_BIT (current_live_regs, i);
2241 for (i = first_regno; i < last_regno; i++)
2243 SET_HARD_REG_BIT (current_live_regs, i);
2244 CLEAR_HARD_REG_BIT (pending_dead_regs, i);
2248 /* Similar to next_insn, but ignores insns in the delay slots of
2249 an annulled branch. */
2252 next_insn_no_annul (insn)
2257 /* If INSN is an annulled branch, skip any insns from the target
2259 if (INSN_ANNULLED_BRANCH_P (insn)
2260 && NEXT_INSN (PREV_INSN (insn)) != insn)
2261 while (INSN_FROM_TARGET_P (NEXT_INSN (insn)))
2262 insn = NEXT_INSN (insn);
2264 insn = NEXT_INSN (insn);
2265 if (insn && GET_CODE (insn) == INSN
2266 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2267 insn = XVECEXP (PATTERN (insn), 0, 0);
2273 /* Set the resources that are live at TARGET.
2275 If TARGET is zero, we refer to the end of the current function and can
2276 return our precomputed value.
2278 Otherwise, we try to find out what is live by consulting the basic block
2279 information. This is tricky, because we must consider the actions of
2280 reload and jump optimization, which occur after the basic block information
2283 Accordingly, we proceed as follows::
2285 We find the previous BARRIER and look at all immediately following labels
2286 (with no intervening active insns) to see if any of them start a basic
2287 block. If we hit the start of the function first, we use block 0.
2289 Once we have found a basic block and a corresponding first insns, we can
2290 accurately compute the live status from basic_block_live_regs and
2291 reg_renumber. (By starting at a label following a BARRIER, we are immune
2292 to actions taken by reload and jump.) Then we scan all insns between
2293 that point and our target. For each CLOBBER (or for call-clobbered regs
2294 when we pass a CALL_INSN), mark the appropriate registers are dead. For
2295 a SET, mark them as live.
2297 We have to be careful when using REG_DEAD notes because they are not
2298 updated by such things as find_equiv_reg. So keep track of registers
2299 marked as dead that haven't been assigned to, and mark them dead at the
2300 next CODE_LABEL since reload and jump won't propagate values across labels.
2302 If we cannot find the start of a basic block (should be a very rare
2303 case, if it can happen at all), mark everything as potentially live.
2305 Next, scan forward from TARGET looking for things set or clobbered
2306 before they are used. These are not live.
2308 Because we can be called many times on the same target, save our results
2309 in a hash table indexed by INSN_UID. */
2312 mark_target_live_regs (target, res)
2314 struct resources *res;
2318 struct target_info *tinfo;
2322 HARD_REG_SET scratch;
2323 struct resources set, needed;
2326 /* Handle end of function. */
2329 *res = end_of_function_needs;
2333 /* We have to assume memory is needed, but the CC isn't. */
2338 /* See if we have computed this value already. */
2339 for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2340 tinfo; tinfo = tinfo->next)
2341 if (tinfo->uid == INSN_UID (target))
2344 /* Start by getting the basic block number. If we have saved information,
2345 we can get it from there unless the insn at the start of the basic block
2346 has been deleted. */
2347 if (tinfo && tinfo->block != -1
2348 && ! INSN_DELETED_P (basic_block_head[tinfo->block]))
2352 b = find_basic_block (target);
2356 /* If the information is up-to-date, use it. Otherwise, we will
2358 if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b])
2360 COPY_HARD_REG_SET (res->regs, tinfo->live_regs);
2366 /* Allocate a place to put our results and chain it into the
2368 tinfo = (struct target_info *) oballoc (sizeof (struct target_info));
2369 tinfo->uid = INSN_UID (target);
2371 tinfo->next = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME];
2372 target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo;
2375 CLEAR_HARD_REG_SET (pending_dead_regs);
2377 /* If we found a basic block, get the live registers from it and update
2378 them with anything set or killed between its start and the insn before
2379 TARGET. Otherwise, we must assume everything is live. */
2382 regset regs_live = basic_block_live_at_start[b];
2384 REGSET_ELT_TYPE bit;
2386 rtx start_insn, stop_insn;
2388 /* Compute hard regs live at start of block -- this is the real hard regs
2389 marked live, plus live pseudo regs that have been renumbered to
2393 current_live_regs = *regs_live;
2395 COPY_HARD_REG_SET (current_live_regs, regs_live);
2398 for (offset = 0, i = 0; offset < regset_size; offset++)
2400 if (regs_live[offset] == 0)
2401 i += REGSET_ELT_BITS;
2403 for (bit = 1; bit && i < max_regno; bit <<= 1, i++)
2404 if ((regs_live[offset] & bit)
2405 && (regno = reg_renumber[i]) >= 0)
2407 j < regno + HARD_REGNO_NREGS (regno,
2408 PSEUDO_REGNO_MODE (i));
2410 SET_HARD_REG_BIT (current_live_regs, j);
2413 /* Get starting and ending insn, handling the case where each might
2415 start_insn = (b == 0 ? get_insns () : basic_block_head[b]);
2418 if (GET_CODE (start_insn) == INSN
2419 && GET_CODE (PATTERN (start_insn)) == SEQUENCE)
2420 start_insn = XVECEXP (PATTERN (start_insn), 0, 0);
2422 if (GET_CODE (stop_insn) == INSN
2423 && GET_CODE (PATTERN (stop_insn)) == SEQUENCE)
2424 stop_insn = next_insn (PREV_INSN (stop_insn));
2426 for (insn = start_insn; insn != stop_insn;
2427 insn = next_insn_no_annul (insn))
2430 rtx real_insn = insn;
2432 /* If this insn is from the target of a branch, it isn't going to
2433 be used in the sequel. If it is used in both cases, this
2434 test will not be true. */
2435 if (INSN_FROM_TARGET_P (insn))
2438 /* If this insn is a USE made by update_block, we care about the
2440 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
2441 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2442 real_insn = XEXP (PATTERN (insn), 0);
2444 if (GET_CODE (real_insn) == CALL_INSN)
2446 /* CALL clobbers all call-used regs that aren't fixed except
2447 sp, ap, and fp. Do this before setting the result of the
2449 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2450 if (call_used_regs[i]
2451 && i != STACK_POINTER_REGNUM && i != FRAME_POINTER_REGNUM
2452 && i != ARG_POINTER_REGNUM
2453 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2454 && i != HARD_FRAME_POINTER_REGNUM
2456 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2457 && ! (i == ARG_POINTER_REGNUM && fixed_regs[i])
2459 #ifdef PIC_OFFSET_TABLE_REGNUM
2460 && ! (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
2463 CLEAR_HARD_REG_BIT (current_live_regs, i);
2465 /* A CALL_INSN sets any global register live, since it may
2466 have been modified by the call. */
2467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2469 SET_HARD_REG_BIT (current_live_regs, i);
2472 /* Mark anything killed in an insn to be deadened at the next
2473 label. Ignore USE insns; the only REG_DEAD notes will be for
2474 parameters. But they might be early. A CALL_INSN will usually
2475 clobber registers used for parameters. It isn't worth bothering
2476 with the unlikely case when it won't. */
2477 if ((GET_CODE (real_insn) == INSN
2478 && GET_CODE (PATTERN (real_insn)) != USE
2479 && GET_CODE (PATTERN (real_insn)) != CLOBBER)
2480 || GET_CODE (real_insn) == JUMP_INSN
2481 || GET_CODE (real_insn) == CALL_INSN)
2483 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2484 if (REG_NOTE_KIND (link) == REG_DEAD
2485 && GET_CODE (XEXP (link, 0)) == REG
2486 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2488 int first_regno = REGNO (XEXP (link, 0));
2491 + HARD_REGNO_NREGS (first_regno,
2492 GET_MODE (XEXP (link, 0))));
2494 for (i = first_regno; i < last_regno; i++)
2495 SET_HARD_REG_BIT (pending_dead_regs, i);
2498 note_stores (PATTERN (real_insn), update_live_status);
2500 /* If any registers were unused after this insn, kill them.
2501 These notes will always be accurate. */
2502 for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1))
2503 if (REG_NOTE_KIND (link) == REG_UNUSED
2504 && GET_CODE (XEXP (link, 0)) == REG
2505 && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER)
2507 int first_regno = REGNO (XEXP (link, 0));
2510 + HARD_REGNO_NREGS (first_regno,
2511 GET_MODE (XEXP (link, 0))));
2513 for (i = first_regno; i < last_regno; i++)
2514 CLEAR_HARD_REG_BIT (current_live_regs, i);
2518 else if (GET_CODE (real_insn) == CODE_LABEL)
2520 /* A label clobbers the pending dead registers since neither
2521 reload nor jump will propagate a value across a label. */
2522 AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs);
2523 CLEAR_HARD_REG_SET (pending_dead_regs);
2526 /* The beginning of the epilogue corresponds to the end of the
2527 RTL chain when there are no epilogue insns. Certain resources
2528 are implicitly required at that point. */
2529 else if (GET_CODE (real_insn) == NOTE
2530 && NOTE_LINE_NUMBER (real_insn) == NOTE_INSN_EPILOGUE_BEG)
2531 IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs);
2534 COPY_HARD_REG_SET (res->regs, current_live_regs);
2536 tinfo->bb_tick = bb_ticks[b];
2539 /* We didn't find the start of a basic block. Assume everything
2540 in use. This should happen only extremely rarely. */
2541 SET_HARD_REG_SET (res->regs);
2543 /* Now step forward from TARGET looking for registers that are set before
2544 they are used. These are dead. If we pass a label, any pending dead
2545 registers that weren't yet used can be made dead. Stop when we pass a
2546 conditional JUMP_INSN; follow the first few unconditional branches. */
2548 CLEAR_RESOURCE (&set);
2549 CLEAR_RESOURCE (&needed);
2551 for (insn = target; insn; insn = next)
2553 rtx this_jump_insn = insn;
2555 next = NEXT_INSN (insn);
2556 switch (GET_CODE (insn))
2559 AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs);
2560 AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs);
2561 CLEAR_HARD_REG_SET (pending_dead_regs);
2569 if (GET_CODE (PATTERN (insn)) == USE)
2571 /* If INSN is a USE made by update_block, we care about the
2572 underlying insn. Any registers set by the underlying insn
2573 are live since the insn is being done somewhere else. */
2574 if (GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
2575 mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, 1);
2577 /* All other USE insns are to be ignored. */
2580 else if (GET_CODE (PATTERN (insn)) == CLOBBER)
2582 else if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2584 /* An unconditional jump can be used to fill the delay slot
2585 of a call, so search for a JUMP_INSN in any position. */
2586 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
2588 this_jump_insn = XVECEXP (PATTERN (insn), 0, i);
2589 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2595 if (GET_CODE (this_jump_insn) == JUMP_INSN)
2597 if (jump_count++ < 10
2598 && (simplejump_p (this_jump_insn)
2599 || GET_CODE (PATTERN (this_jump_insn)) == RETURN))
2601 next = next_active_insn (JUMP_LABEL (this_jump_insn));
2605 jump_target = JUMP_LABEL (this_jump_insn);
2612 mark_referenced_resources (insn, &needed, 1);
2613 mark_set_resources (insn, &set, 0, 1);
2615 COPY_HARD_REG_SET (scratch, set.regs);
2616 AND_COMPL_HARD_REG_SET (scratch, needed.regs);
2617 AND_COMPL_HARD_REG_SET (res->regs, scratch);
2620 /* If we hit an unconditional branch, we have another way of finding out
2621 what is live: we can see what is live at the branch target and include
2622 anything used but not set before the branch. The only things that are
2623 live are those that are live using the above test and the test below.
2625 Don't try this if we expired our jump count above, since that would
2626 mean there may be an infinite loop in the function being compiled. */
2628 if (jump_insn && jump_count < 10)
2630 struct resources new_resources;
2631 rtx stop_insn = next_active_insn (jump_insn);
2633 mark_target_live_regs (next_active_insn (jump_target), &new_resources);
2634 CLEAR_RESOURCE (&set);
2635 CLEAR_RESOURCE (&needed);
2637 /* Include JUMP_INSN in the needed registers. */
2638 for (insn = target; insn != stop_insn; insn = next_active_insn (insn))
2640 mark_referenced_resources (insn, &needed, 1);
2642 COPY_HARD_REG_SET (scratch, needed.regs);
2643 AND_COMPL_HARD_REG_SET (scratch, set.regs);
2644 IOR_HARD_REG_SET (new_resources.regs, scratch);
2646 mark_set_resources (insn, &set, 0, 1);
2649 AND_HARD_REG_SET (res->regs, new_resources.regs);
2652 COPY_HARD_REG_SET (tinfo->live_regs, res->regs);
2655 /* Scan a function looking for insns that need a delay slot and find insns to
2656 put into the delay slot.
2658 NON_JUMPS_P is non-zero if we are to only try to fill non-jump insns (such
2659 as calls). We do these first since we don't want jump insns (that are
2660 easier to fill) to get the only insns that could be used for non-jump insns.
2661 When it is zero, only try to fill JUMP_INSNs.
2663 When slots are filled in this manner, the insns (including the
2664 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
2665 it is possible to tell whether a delay slot has really been filled
2666 or not. `final' knows how to deal with this, by communicating
2667 through FINAL_SEQUENCE. */
2670 fill_simple_delay_slots (first, non_jumps_p)
2674 register rtx insn, pat, trial, next_trial;
2676 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
2677 struct resources needed, set;
2678 register int slots_to_fill, slots_filled;
2681 for (i = 0; i < num_unfilled_slots; i++)
2684 /* Get the next insn to fill. If it has already had any slots assigned,
2685 we can't do anything with it. Maybe we'll improve this later. */
2687 insn = unfilled_slots_base[i];
2689 || INSN_DELETED_P (insn)
2690 || (GET_CODE (insn) == INSN
2691 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2692 || (GET_CODE (insn) == JUMP_INSN && non_jumps_p)
2693 || (GET_CODE (insn) != JUMP_INSN && ! non_jumps_p))
2696 if (GET_CODE (insn) == JUMP_INSN)
2697 flags = get_jump_flags (insn, JUMP_LABEL (insn));
2699 flags = get_jump_flags (insn, NULL_RTX);
2700 slots_to_fill = num_delay_slots (insn);
2701 if (slots_to_fill == 0)
2704 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
2705 says how many. After initialization, first try optimizing
2708 nop add %o7,.-L1,%o7
2712 If this case applies, the delay slot of the call is filled with
2713 the unconditional jump. This is done first to avoid having the
2714 delay slot of the call filled in the backward scan. Also, since
2715 the unconditional jump is likely to also have a delay slot, that
2716 insn must exist when it is subsequently scanned.
2718 This is tried on each insn with delay slots as some machines
2719 have insns which perform calls, but are not represented as
2725 if ((trial = next_active_insn (insn))
2726 && GET_CODE (trial) == JUMP_INSN
2727 && simplejump_p (trial)
2728 && eligible_for_delay (insn, slots_filled, trial, flags)
2729 && no_labels_between_p (insn, trial))
2732 delay_list = add_to_delay_list (trial, delay_list);
2733 /* Remove the unconditional jump from consideration for delay slot
2734 filling and unthread it. */
2735 if (unfilled_slots_base[i + 1] == trial)
2736 unfilled_slots_base[i + 1] = 0;
2738 rtx next = NEXT_INSN (trial);
2739 rtx prev = PREV_INSN (trial);
2741 NEXT_INSN (prev) = next;
2743 PREV_INSN (next) = prev;
2747 /* Now, scan backwards from the insn to search for a potential
2748 delay-slot candidate. Stop searching when a label or jump is hit.
2750 For each candidate, if it is to go into the delay slot (moved
2751 forward in execution sequence), it must not need or set any resources
2752 that were set by later insns and must not set any resources that
2753 are needed for those insns.
2755 The delay slot insn itself sets resources unless it is a call
2756 (in which case the called routine, not the insn itself, is doing
2759 if (slots_filled < slots_to_fill)
2761 CLEAR_RESOURCE (&needed);
2762 CLEAR_RESOURCE (&set);
2763 mark_set_resources (insn, &set, 0, 0);
2764 mark_referenced_resources (insn, &needed, 0);
2766 for (trial = prev_nonnote_insn (insn); ! stop_search_p (trial, 1);
2769 next_trial = prev_nonnote_insn (trial);
2771 /* This must be an INSN or CALL_INSN. */
2772 pat = PATTERN (trial);
2774 /* USE and CLOBBER at this level was just for flow; ignore it. */
2775 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2778 /* Check for resource conflict first, to avoid unnecessary
2780 if (! insn_references_resource_p (trial, &set, 1)
2781 && ! insn_sets_resource_p (trial, &set, 1)
2782 && ! insn_sets_resource_p (trial, &needed, 1)
2784 /* Can't separate set of cc0 from its use. */
2785 && ! (reg_mentioned_p (cc0_rtx, pat)
2786 && ! sets_cc0_p (cc0_rtx, pat))
2790 trial = try_split (pat, trial, 1);
2791 next_trial = prev_nonnote_insn (trial);
2792 if (eligible_for_delay (insn, slots_filled, trial, flags))
2794 /* In this case, we are searching backward, so if we
2795 find insns to put on the delay list, we want
2796 to put them at the head, rather than the
2797 tail, of the list. */
2799 update_reg_dead_notes (trial, insn);
2800 delay_list = gen_rtx (INSN_LIST, VOIDmode,
2802 update_block (trial, trial);
2803 delete_insn (trial);
2804 if (slots_to_fill == ++slots_filled)
2810 mark_set_resources (trial, &set, 0, 1);
2811 mark_referenced_resources (trial, &needed, 1);
2815 /* If all needed slots haven't been filled, we come here. */
2817 /* Try to optimize case of jumping around a single insn. */
2818 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
2819 if (slots_filled != slots_to_fill
2821 && GET_CODE (insn) == JUMP_INSN && condjump_p (insn))
2823 delay_list = optimize_skip (insn);
2829 /* Try to get insns from beyond the insn needing the delay slot.
2830 These insns can neither set or reference resources set in insns being
2831 skipped, cannot set resources in the insn being skipped, and, if this
2832 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2833 call might not return).
2835 If this is a conditional jump, see if it merges back to us early
2836 enough for us to pick up insns from the merge point. Don't do
2837 this if there is another branch to our label unless we pass all of
2840 Another similar merge is if we jump to the same place that a
2841 later unconditional jump branches to. In that case, we don't
2842 care about the number of uses of our label. */
2844 if (slots_filled != slots_to_fill
2845 && (GET_CODE (insn) != JUMP_INSN
2846 || (condjump_p (insn) && ! simplejump_p (insn)
2847 && JUMP_LABEL (insn) != 0)))
2850 int maybe_never = 0;
2851 int passed_label = 0;
2853 struct resources needed_at_jump;
2855 CLEAR_RESOURCE (&needed);
2856 CLEAR_RESOURCE (&set);
2858 if (GET_CODE (insn) == CALL_INSN)
2860 mark_set_resources (insn, &set, 0, 1);
2861 mark_referenced_resources (insn, &needed, 1);
2866 mark_set_resources (insn, &set, 0, 1);
2867 mark_referenced_resources (insn, &needed, 1);
2868 if (GET_CODE (insn) == JUMP_INSN)
2870 /* Get our target and show how many more uses we want to
2871 see before we hit the label. */
2872 target = JUMP_LABEL (insn);
2873 target_uses = LABEL_NUSES (target) - 1;
2878 for (trial = next_nonnote_insn (insn); trial; trial = next_trial)
2880 rtx pat, trial_delay;
2882 next_trial = next_nonnote_insn (trial);
2884 if (GET_CODE (trial) == CODE_LABEL)
2888 /* If this is our target, see if we have seen all its uses.
2889 If so, indicate we have passed our target and ignore it.
2890 All other labels cause us to stop our search. */
2891 if (trial == target && target_uses == 0)
2899 else if (GET_CODE (trial) == BARRIER)
2902 /* We must have an INSN, JUMP_INSN, or CALL_INSN. */
2903 pat = PATTERN (trial);
2905 /* Stand-alone USE and CLOBBER are just for flow. */
2906 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
2909 /* If this already has filled delay slots, get the insn needing
2911 if (GET_CODE (pat) == SEQUENCE)
2912 trial_delay = XVECEXP (pat, 0, 0);
2914 trial_delay = trial;
2916 /* If this is a jump insn to our target, indicate that we have
2917 seen another jump to it. If we aren't handling a conditional
2918 jump, stop our search. Otherwise, compute the needs at its
2919 target and add them to NEEDED. */
2920 if (GET_CODE (trial_delay) == JUMP_INSN)
2924 else if (JUMP_LABEL (trial_delay) == target)
2928 mark_target_live_regs
2929 (next_active_insn (JUMP_LABEL (trial_delay)),
2931 needed.memory |= needed_at_jump.memory;
2932 IOR_HARD_REG_SET (needed.regs, needed_at_jump.regs);
2936 /* See if we have a resource problem before we try to
2939 && GET_CODE (pat) != SEQUENCE
2940 && ! insn_references_resource_p (trial, &set, 1)
2941 && ! insn_sets_resource_p (trial, &set, 1)
2942 && ! insn_sets_resource_p (trial, &needed, 1)
2944 && ! (reg_mentioned_p (cc0_rtx, pat) && ! sets_cc0_p (pat))
2946 && ! (maybe_never && may_trap_p (pat))
2947 && (trial = try_split (pat, trial, 0))
2948 && eligible_for_delay (insn, slots_filled, trial, flags))
2950 next_trial = next_nonnote_insn (trial);
2951 delay_list = add_to_delay_list (trial, delay_list);
2954 if (reg_mentioned_p (cc0_rtx, pat))
2955 link_cc0_insns (trial);
2959 update_block (trial, trial);
2960 delete_insn (trial);
2961 if (slots_to_fill == ++slots_filled)
2966 mark_set_resources (trial, &set, 0, 1);
2967 mark_referenced_resources (trial, &needed, 1);
2969 /* Ensure we don't put insns between the setting of cc and the
2970 comparison by moving a setting of cc into an earlier delay
2971 slot since these insns could clobber the condition code. */
2974 /* If this is a call or jump, we might not get here. */
2975 if (GET_CODE (trial) == CALL_INSN
2976 || GET_CODE (trial) == JUMP_INSN)
2980 /* If there are slots left to fill and our search was stopped by an
2981 unconditional branch, try the insn at the branch target. We can
2982 redirect the branch if it works. */
2983 if (slots_to_fill != slots_filled
2985 && GET_CODE (trial) == JUMP_INSN
2986 && simplejump_p (trial)
2987 && (target == 0 || JUMP_LABEL (trial) == target)
2988 && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0
2989 && ! (GET_CODE (next_trial) == INSN
2990 && GET_CODE (PATTERN (next_trial)) == SEQUENCE)
2991 && ! insn_references_resource_p (next_trial, &set, 1)
2992 && ! insn_sets_resource_p (next_trial, &set, 1)
2993 && ! insn_sets_resource_p (next_trial, &needed, 1)
2995 && ! reg_mentioned_p (cc0_rtx, PATTERN (next_trial))
2997 && ! (maybe_never && may_trap_p (PATTERN (next_trial)))
2998 && (next_trial = try_split (PATTERN (next_trial), next_trial, 0))
2999 && eligible_for_delay (insn, slots_filled, next_trial, flags))
3001 rtx new_label = next_active_insn (next_trial);
3004 new_label = get_label_before (new_label);
3007 = add_to_delay_list (copy_rtx (next_trial), delay_list);
3009 reorg_redirect_jump (trial, new_label);
3011 /* If we merged because we both jumped to the same place,
3012 redirect the original insn also. */
3014 reorg_redirect_jump (insn, new_label);
3019 unfilled_slots_base[i]
3020 = emit_delay_sequence (insn, delay_list,
3021 slots_filled, slots_to_fill);
3023 if (slots_to_fill == slots_filled)
3024 unfilled_slots_base[i] = 0;
3026 note_delay_statistics (slots_filled, 0);
3029 #ifdef DELAY_SLOTS_FOR_EPILOGUE
3030 /* See if the epilogue needs any delay slots. Try to fill them if so.
3031 The only thing we can do is scan backwards from the end of the
3032 function. If we did this in a previous pass, it is incorrect to do it
3034 if (current_function_epilogue_delay_list)
3037 slots_to_fill = DELAY_SLOTS_FOR_EPILOGUE;
3038 if (slots_to_fill == 0)
3042 CLEAR_RESOURCE (&needed);
3043 CLEAR_RESOURCE (&set);
3045 for (trial = get_last_insn (); ! stop_search_p (trial, 1);
3046 trial = PREV_INSN (trial))
3048 if (GET_CODE (trial) == NOTE)
3050 pat = PATTERN (trial);
3051 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3054 if (! insn_references_resource_p (trial, &set, 1)
3055 && ! insn_sets_resource_p (trial, &needed, 1)
3057 /* Don't want to mess with cc0 here. */
3058 && ! reg_mentioned_p (cc0_rtx, pat)
3062 trial = try_split (pat, trial, 1);
3063 if (ELIGIBLE_FOR_EPILOGUE_DELAY (trial, slots_filled))
3065 /* Here as well we are searching backward, so put the
3066 insns we find on the head of the list. */
3068 current_function_epilogue_delay_list
3069 = gen_rtx (INSN_LIST, VOIDmode, trial,
3070 current_function_epilogue_delay_list);
3071 mark_referenced_resources (trial, &end_of_function_needs, 1);
3072 update_block (trial, trial);
3073 delete_insn (trial);
3075 /* Clear deleted bit so final.c will output the insn. */
3076 INSN_DELETED_P (trial) = 0;
3078 if (slots_to_fill == ++slots_filled)
3084 mark_set_resources (trial, &set, 0, 1);
3085 mark_referenced_resources (trial, &needed, 1);
3088 note_delay_statistics (slots_filled, 0);
3092 /* Try to find insns to place in delay slots.
3094 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
3095 or is an unconditional branch if CONDITION is const_true_rtx.
3096 *PSLOTS_FILLED is updated with the number of slots that we have filled.
3098 THREAD is a flow-of-control, either the insns to be executed if the
3099 branch is true or if the branch is false, THREAD_IF_TRUE says which.
3101 OPPOSITE_THREAD is the thread in the opposite direction. It is used
3102 to see if any potential delay slot insns set things needed there.
3104 LIKELY is non-zero if it is extremely likely that the branch will be
3105 taken and THREAD_IF_TRUE is set. This is used for the branch at the
3106 end of a loop back up to the top.
3108 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
3109 thread. I.e., it is the fallthrough code of our jump or the target of the
3110 jump when we are the only jump going there.
3112 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
3113 case, we can only take insns from the head of the thread for our delay
3114 slot. We then adjust the jump to point after the insns we have taken. */
3117 fill_slots_from_thread (insn, condition, thread, opposite_thread, likely,
3118 thread_if_true, own_thread, own_opposite_thread,
3119 slots_to_fill, pslots_filled)
3122 rtx thread, opposite_thread;
3125 int own_thread, own_opposite_thread;
3126 int slots_to_fill, *pslots_filled;
3130 struct resources opposite_needed, set, needed;
3136 /* Validate our arguments. */
3137 if ((condition == const_true_rtx && ! thread_if_true)
3138 || (! own_thread && ! thread_if_true))
3141 flags = get_jump_flags (insn, JUMP_LABEL (insn));
3143 /* If our thread is the end of subroutine, we can't get any delay
3148 /* If this is an unconditional branch, nothing is needed at the
3149 opposite thread. Otherwise, compute what is needed there. */
3150 if (condition == const_true_rtx)
3151 CLEAR_RESOURCE (&opposite_needed);
3153 mark_target_live_regs (opposite_thread, &opposite_needed);
3155 /* If the insn at THREAD can be split, do it here to avoid having to
3156 update THREAD and NEW_THREAD if it is done in the loop below. Also
3157 initialize NEW_THREAD. */
3159 new_thread = thread = try_split (PATTERN (thread), thread, 0);
3161 /* Scan insns at THREAD. We are looking for an insn that can be removed
3162 from THREAD (it neither sets nor references resources that were set
3163 ahead of it and it doesn't set anything needs by the insns ahead of
3164 it) and that either can be placed in an annulling insn or aren't
3165 needed at OPPOSITE_THREAD. */
3167 CLEAR_RESOURCE (&needed);
3168 CLEAR_RESOURCE (&set);
3170 /* If we do not own this thread, we must stop as soon as we find
3171 something that we can't put in a delay slot, since all we can do
3172 is branch into THREAD at a later point. Therefore, labels stop
3173 the search if this is not the `true' thread. */
3175 for (trial = thread;
3176 ! stop_search_p (trial, ! thread_if_true) && (! lose || own_thread);
3177 trial = next_nonnote_insn (trial))
3181 /* If we have passed a label, we no longer own this thread. */
3182 if (GET_CODE (trial) == CODE_LABEL)
3188 pat = PATTERN (trial);
3189 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
3192 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
3193 don't separate or copy insns that set and use CC0. */
3194 if (! insn_references_resource_p (trial, &set, 1)
3195 && ! insn_sets_resource_p (trial, &set, 1)
3196 && ! insn_sets_resource_p (trial, &needed, 1)
3198 && ! (reg_mentioned_p (cc0_rtx, pat)
3199 && (! own_thread || ! sets_cc0_p (pat)))
3203 /* If TRIAL is redundant with some insn before INSN, we don't
3204 actually need to add it to the delay list; we can merely pretend
3206 if (redundant_insn_p (trial, insn, delay_list))
3210 update_block (trial, thread);
3211 delete_insn (trial);
3214 new_thread = next_active_insn (trial);
3219 /* There are two ways we can win: If TRIAL doesn't set anything
3220 needed at the opposite thread and can't trap, or if it can
3221 go into an annulled delay slot. */
3222 if (condition == const_true_rtx
3223 || (! insn_sets_resource_p (trial, &opposite_needed, 1)
3224 && ! may_trap_p (pat)))
3227 trial = try_split (pat, trial, 0);
3228 if (new_thread == old_trial)
3230 pat = PATTERN (trial);
3231 if (eligible_for_delay (insn, *pslots_filled, trial, flags))
3235 #ifdef ANNUL_IFTRUE_SLOTS
3238 #ifdef ANNUL_IFFALSE_SLOTS
3244 trial = try_split (pat, trial, 0);
3245 if (new_thread == old_trial)
3247 pat = PATTERN (trial);
3249 ? eligible_for_annul_false (insn, *pslots_filled, trial, flags)
3250 : eligible_for_annul_true (insn, *pslots_filled, trial, flags)))
3258 if (reg_mentioned_p (cc0_rtx, pat))
3259 link_cc0_insns (trial);
3262 /* If we own this thread, delete the insn. If this is the
3263 destination of a branch, show that a basic block status
3264 may have been updated. In any case, mark the new
3265 starting point of this thread. */
3268 update_block (trial, thread);
3269 delete_insn (trial);
3272 new_thread = next_active_insn (trial);
3274 temp = own_thread ? trial : copy_rtx (trial);
3276 INSN_FROM_TARGET_P (temp) = 1;
3278 delay_list = add_to_delay_list (temp, delay_list);
3280 if (slots_to_fill == ++(*pslots_filled))
3282 /* Even though we have filled all the slots, we
3283 may be branching to a location that has a
3284 redundant insn. Skip any if so. */
3285 while (new_thread && ! own_thread
3286 && ! insn_sets_resource_p (new_thread, &set, 1)
3287 && ! insn_sets_resource_p (new_thread, &needed, 1)
3288 && ! insn_references_resource_p (new_thread,
3290 && redundant_insn_p (new_thread, insn,
3292 new_thread = next_active_insn (new_thread);
3301 /* This insn can't go into a delay slot. */
3303 mark_set_resources (trial, &set, 0, 1);
3304 mark_referenced_resources (trial, &needed, 1);
3306 /* Ensure we don't put insns between the setting of cc and the comparison
3307 by moving a setting of cc into an earlier delay slot since these insns
3308 could clobber the condition code. */
3311 /* If this insn is a register-register copy and the next insn has
3312 a use of our destination, change it to use our source. That way,
3313 it will become a candidate for our delay slot the next time
3314 through this loop. This case occurs commonly in loops that
3317 We could check for more complex cases than those tested below,
3318 but it doesn't seem worth it. It might also be a good idea to try
3319 to swap the two insns. That might do better.
3321 We can't do this if the next insn modifies our destination, because
3322 that would make the replacement into the insn invalid. We also can't
3323 do this if it modifies our source, because it might be an earlyclobber
3324 operand. This latter test also prevents updating the contents of
3327 if (GET_CODE (trial) == INSN && GET_CODE (pat) == SET
3328 && GET_CODE (SET_SRC (pat)) == REG
3329 && GET_CODE (SET_DEST (pat)) == REG)
3331 rtx next = next_nonnote_insn (trial);
3333 if (next && GET_CODE (next) == INSN
3334 && GET_CODE (PATTERN (next)) != USE
3335 && ! reg_set_p (SET_DEST (pat), next)
3336 && ! reg_set_p (SET_SRC (pat), next)
3337 && reg_referenced_p (SET_DEST (pat), PATTERN (next)))
3338 validate_replace_rtx (SET_DEST (pat), SET_SRC (pat), next);
3342 /* If we stopped on a branch insn that has delay slots, see if we can
3343 steal some of the insns in those slots. */
3344 if (trial && GET_CODE (trial) == INSN
3345 && GET_CODE (PATTERN (trial)) == SEQUENCE
3346 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN)
3348 /* If this is the `true' thread, we will want to follow the jump,
3349 so we can only do this if we have taken everything up to here. */
3350 if (thread_if_true && trial == new_thread)
3352 = steal_delay_list_from_target (insn, condition, PATTERN (trial),
3353 delay_list, &set, &needed,
3354 &opposite_needed, slots_to_fill,
3355 pslots_filled, &must_annul,
3357 else if (! thread_if_true)
3359 = steal_delay_list_from_fallthrough (insn, condition,
3361 delay_list, &set, &needed,
3362 &opposite_needed, slots_to_fill,
3363 pslots_filled, &must_annul);
3366 /* If we haven't found anything for this delay slot and it is very
3367 likely that the branch will be taken, see if the insn at our target
3368 increments or decrements a register with an increment that does not
3369 depend on the destination register. If so, try to place the opposite
3370 arithmetic insn after the jump insn and put the arithmetic insn in the
3371 delay slot. If we can't do this, return. */
3372 if (delay_list == 0 && likely && new_thread && GET_CODE (new_thread) == INSN)
3374 rtx pat = PATTERN (new_thread);
3379 pat = PATTERN (trial);
3381 if (GET_CODE (trial) != INSN || GET_CODE (pat) != SET
3382 || ! eligible_for_delay (insn, 0, trial, flags))
3385 dest = SET_DEST (pat), src = SET_SRC (pat);
3386 if ((GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
3387 && rtx_equal_p (XEXP (src, 0), dest)
3388 && ! reg_overlap_mentioned_p (dest, XEXP (src, 1)))
3390 rtx other = XEXP (src, 1);
3394 /* If this is a constant adjustment, use the same code with
3395 the negated constant. Otherwise, reverse the sense of the
3397 if (GET_CODE (other) == CONST_INT)
3398 new_arith = gen_rtx (GET_CODE (src), GET_MODE (src), dest,
3399 negate_rtx (GET_MODE (src), other));
3401 new_arith = gen_rtx (GET_CODE (src) == PLUS ? MINUS : PLUS,
3402 GET_MODE (src), dest, other);
3404 ninsn = emit_insn_after (gen_rtx (SET, VOIDmode, dest, new_arith),
3407 if (recog_memoized (ninsn) < 0
3408 || (insn_extract (ninsn),
3409 ! constrain_operands (INSN_CODE (ninsn), 1)))
3411 delete_insn (ninsn);
3417 update_block (trial, thread);
3418 delete_insn (trial);
3421 new_thread = next_active_insn (trial);
3423 ninsn = own_thread ? trial : copy_rtx (trial);
3425 INSN_FROM_TARGET_P (ninsn) = 1;
3427 delay_list = add_to_delay_list (ninsn, NULL_RTX);
3432 if (delay_list && must_annul)
3433 INSN_ANNULLED_BRANCH_P (insn) = 1;
3435 /* If we are to branch into the middle of this thread, find an appropriate
3436 label or make a new one if none, and redirect INSN to it. If we hit the
3437 end of the function, use the end-of-function label. */
3438 if (new_thread != thread)
3442 if (! thread_if_true)
3445 if (new_thread && GET_CODE (new_thread) == JUMP_INSN
3446 && (simplejump_p (new_thread)
3447 || GET_CODE (PATTERN (new_thread)) == RETURN))
3448 new_thread = follow_jumps (JUMP_LABEL (new_thread));
3450 if (new_thread == 0)
3451 label = find_end_label ();
3452 else if (GET_CODE (new_thread) == CODE_LABEL)
3455 label = get_label_before (new_thread);
3457 reorg_redirect_jump (insn, label);
3463 /* Make another attempt to find insns to place in delay slots.
3465 We previously looked for insns located in front of the delay insn
3466 and, for non-jump delay insns, located behind the delay insn.
3468 Here only try to schedule jump insns and try to move insns from either
3469 the target or the following insns into the delay slot. If annulling is
3470 supported, we will be likely to do this. Otherwise, we can do this only
3474 fill_eager_delay_slots (first)
3479 int num_unfilled_slots = unfilled_slots_next - unfilled_slots_base;
3481 for (i = 0; i < num_unfilled_slots; i++)
3484 rtx target_label, insn_at_target, fallthrough_insn;
3487 int own_fallthrough;
3488 int prediction, slots_to_fill, slots_filled;
3490 insn = unfilled_slots_base[i];
3492 || INSN_DELETED_P (insn)
3493 || GET_CODE (insn) != JUMP_INSN
3494 || ! condjump_p (insn))
3497 slots_to_fill = num_delay_slots (insn);
3498 if (slots_to_fill == 0)
3502 target_label = JUMP_LABEL (insn);
3503 condition = get_branch_condition (insn, target_label);
3508 /* Get the next active fallthough and target insns and see if we own
3509 them. Then see whether the branch is likely true. We don't need
3510 to do a lot of this for unconditional branches. */
3512 insn_at_target = next_active_insn (target_label);
3513 own_target = own_thread_p (target_label, target_label, 0);
3515 if (condition == const_true_rtx)
3517 own_fallthrough = 0;
3518 fallthrough_insn = 0;
3523 fallthrough_insn = next_active_insn (insn);
3524 own_fallthrough = own_thread_p (NEXT_INSN (insn), NULL_RTX, 1);
3525 prediction = mostly_true_jump (insn, condition);
3528 /* If this insn is expected to branch, first try to get insns from our
3529 target, then our fallthrough insns. If it is not, expected to branch,
3530 try the other order. */
3535 = fill_slots_from_thread (insn, condition, insn_at_target,
3536 fallthrough_insn, prediction == 2, 1,
3537 own_target, own_fallthrough,
3538 slots_to_fill, &slots_filled);
3540 if (delay_list == 0 && own_fallthrough)
3542 /* Even though we didn't find anything for delay slots,
3543 we might have found a redundant insn which we deleted
3544 from the thread that was filled. So we have to recompute
3545 the next insn at the target. */
3546 target_label = JUMP_LABEL (insn);
3547 insn_at_target = next_active_insn (target_label);
3550 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3551 insn_at_target, 0, 0,
3552 own_fallthrough, own_target,
3553 slots_to_fill, &slots_filled);
3558 if (own_fallthrough)
3560 = fill_slots_from_thread (insn, condition, fallthrough_insn,
3561 insn_at_target, 0, 0,
3562 own_fallthrough, own_target,
3563 slots_to_fill, &slots_filled);
3565 if (delay_list == 0)
3567 = fill_slots_from_thread (insn, condition, insn_at_target,
3568 next_active_insn (insn), 0, 1,
3569 own_target, own_fallthrough,
3570 slots_to_fill, &slots_filled);
3574 unfilled_slots_base[i]
3575 = emit_delay_sequence (insn, delay_list,
3576 slots_filled, slots_to_fill);
3578 if (slots_to_fill == slots_filled)
3579 unfilled_slots_base[i] = 0;
3581 note_delay_statistics (slots_filled, 1);
3585 /* Once we have tried two ways to fill a delay slot, make a pass over the
3586 code to try to improve the results and to do such things as more jump
3590 relax_delay_slots (first)
3593 register rtx insn, next, pat;
3594 register rtx trial, delay_insn, target_label;
3596 /* Look at every JUMP_INSN and see if we can improve it. */
3597 for (insn = first; insn; insn = next)
3601 next = next_active_insn (insn);
3603 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3604 the next insn, or jumps to a label that is not the last of a
3605 group of consecutive labels. */
3606 if (GET_CODE (insn) == JUMP_INSN
3607 && condjump_p (insn)
3608 && (target_label = JUMP_LABEL (insn)) != 0)
3610 target_label = follow_jumps (target_label);
3611 target_label = prev_label (next_active_insn (target_label));
3613 if (target_label == 0)
3614 target_label = find_end_label ();
3616 if (next_active_insn (target_label) == next)
3622 if (target_label != JUMP_LABEL (insn))
3623 reorg_redirect_jump (insn, target_label);
3625 /* See if this jump branches around a unconditional jump.
3626 If so, invert this jump and point it to the target of the
3628 if (next && GET_CODE (next) == JUMP_INSN
3629 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
3630 && next_active_insn (target_label) == next_active_insn (next)
3631 && no_labels_between_p (insn, next))
3633 rtx label = JUMP_LABEL (next);
3635 /* Be careful how we do this to avoid deleting code or
3636 labels that are momentarily dead. See similar optimization
3639 We also need to ensure we properly handle the case when
3640 invert_jump fails. */
3642 ++LABEL_NUSES (target_label);
3644 ++LABEL_NUSES (label);
3646 if (invert_jump (insn, label))
3653 --LABEL_NUSES (label);
3655 if (--LABEL_NUSES (target_label) == 0)
3656 delete_insn (target_label);
3662 /* If this is an unconditional jump and the previous insn is a
3663 conditional jump, try reversing the condition of the previous
3664 insn and swapping our targets. The next pass might be able to
3667 Don't do this if we expect the conditional branch to be true, because
3668 we would then be making the more common case longer. */
3670 if (GET_CODE (insn) == JUMP_INSN
3671 && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN)
3672 && (other = prev_active_insn (insn)) != 0
3673 && condjump_p (other)
3674 && no_labels_between_p (other, insn)
3675 && 0 < mostly_true_jump (other,
3676 get_branch_condition (other,
3677 JUMP_LABEL (other))))
3679 rtx other_target = JUMP_LABEL (other);
3680 target_label = JUMP_LABEL (insn);
3682 /* Increment the count of OTHER_TARGET, so it doesn't get deleted
3683 as we move the label. */
3685 ++LABEL_NUSES (other_target);
3687 if (invert_jump (other, target_label))
3688 reorg_redirect_jump (insn, other_target);
3691 --LABEL_NUSES (other_target);
3694 /* Now look only at cases where we have filled a delay slot. */
3695 if (GET_CODE (insn) != INSN
3696 || GET_CODE (PATTERN (insn)) != SEQUENCE)
3699 pat = PATTERN (insn);
3700 delay_insn = XVECEXP (pat, 0, 0);
3702 /* See if the first insn in the delay slot is redundant with some
3703 previous insn. Remove it from the delay slot if so; then set up
3704 to reprocess this insn. */
3705 if (redundant_insn_p (XVECEXP (pat, 0, 1), delay_insn, 0))
3707 delete_from_delay_slot (XVECEXP (pat, 0, 1));
3708 next = prev_active_insn (next);
3712 /* Now look only at the cases where we have a filled JUMP_INSN. */
3713 if (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
3714 || ! condjump_p (XVECEXP (PATTERN (insn), 0, 0)))
3717 target_label = JUMP_LABEL (delay_insn);
3721 /* If this jump goes to another unconditional jump, thread it, but
3722 don't convert a jump into a RETURN here. */
3723 trial = follow_jumps (target_label);
3724 trial = prev_label (next_active_insn (trial));
3725 if (trial == 0 && target_label != 0)
3726 trial = find_end_label ();
3728 if (trial != target_label
3729 && redirect_with_delay_slots_safe_p (delay_insn, trial, insn))
3731 reorg_redirect_jump (delay_insn, trial);
3732 target_label = trial;
3735 /* If the first insn at TARGET_LABEL is redundant with a previous
3736 insn, redirect the jump to the following insn process again. */
3737 trial = next_active_insn (target_label);
3738 if (trial && GET_CODE (PATTERN (trial)) != SEQUENCE
3739 && redundant_insn_p (trial, insn, 0))
3741 trial = next_active_insn (trial);
3743 target_label = find_end_label ();
3745 target_label = get_label_before (trial);
3746 reorg_redirect_jump (delay_insn, target_label);
3751 /* Similarly, if it is an unconditional jump with one insn in its
3752 delay list and that insn is redundant, thread the jump. */
3753 if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE
3754 && XVECLEN (PATTERN (trial), 0) == 2
3755 && GET_CODE (XVECEXP (PATTERN (trial), 0, 0)) == JUMP_INSN
3756 && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0))
3757 || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN)
3758 && redundant_insn_p (XVECEXP (PATTERN (trial), 0, 1), insn, 0))
3760 target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0));
3761 if (target_label == 0)
3762 target_label = find_end_label ();
3764 if (redirect_with_delay_slots_safe_p (delay_insn, target_label,
3767 reorg_redirect_jump (delay_insn, target_label);
3774 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
3775 && prev_active_insn (target_label) == insn
3777 /* If the last insn in the delay slot sets CC0 for some insn,
3778 various code assumes that it is in a delay slot. We could
3779 put it back where it belonged and delete the register notes,
3780 but it doesn't seem worthwhile in this uncommon case. */
3781 && ! find_reg_note (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1),
3782 REG_CC_USER, NULL_RTX)
3788 /* All this insn does is execute its delay list and jump to the
3789 following insn. So delete the jump and just execute the delay
3792 We do this by deleting the INSN containing the SEQUENCE, then
3793 re-emitting the insns separately, and then deleting the jump.
3794 This allows the count of the jump target to be properly
3797 /* Clear the from target bit, since these insns are no longer
3799 for (i = 0; i < XVECLEN (pat, 0); i++)
3800 INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)) = 0;
3802 trial = PREV_INSN (insn);
3804 emit_insn_after (pat, trial);
3805 delete_scheduled_jump (delay_insn);
3809 /* See if this is an unconditional jump around a single insn which is
3810 identical to the one in its delay slot. In this case, we can just
3811 delete the branch and the insn in its delay slot. */
3812 if (next && GET_CODE (next) == INSN
3813 && prev_label (next_active_insn (next)) == target_label
3814 && simplejump_p (insn)
3815 && XVECLEN (pat, 0) == 2
3816 && rtx_equal_p (PATTERN (next), PATTERN (XVECEXP (pat, 0, 1))))
3822 /* See if this jump (with its delay slots) branches around another
3823 jump (without delay slots). If so, invert this jump and point
3824 it to the target of the second jump. We cannot do this for
3825 annulled jumps, though. Again, don't convert a jump to a RETURN
3827 if (! INSN_ANNULLED_BRANCH_P (delay_insn)
3828 && next && GET_CODE (next) == JUMP_INSN
3829 && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN)
3830 && next_active_insn (target_label) == next_active_insn (next)
3831 && no_labels_between_p (insn, next))
3833 rtx label = JUMP_LABEL (next);
3834 rtx old_label = JUMP_LABEL (delay_insn);
3837 label = find_end_label ();
3839 if (redirect_with_delay_slots_safe_p (delay_insn, label, insn))
3841 /* Be careful how we do this to avoid deleting code or labels
3842 that are momentarily dead. See similar optimization in
3845 ++LABEL_NUSES (old_label);
3847 if (invert_jump (delay_insn, label))
3853 if (old_label && --LABEL_NUSES (old_label) == 0)
3854 delete_insn (old_label);
3859 /* If we own the thread opposite the way this insn branches, see if we
3860 can merge its delay slots with following insns. */
3861 if (INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
3862 && own_thread_p (NEXT_INSN (insn), 0, 1))
3863 try_merge_delay_insns (insn, next);
3864 else if (! INSN_FROM_TARGET_P (XVECEXP (pat, 0, 1))
3865 && own_thread_p (target_label, target_label, 0))
3866 try_merge_delay_insns (insn, next_active_insn (target_label));
3868 /* If we get here, we haven't deleted INSN. But we may have deleted
3869 NEXT, so recompute it. */
3870 next = next_active_insn (insn);
3876 /* Look for filled jumps to the end of function label. We can try to convert
3877 them into RETURN insns if the insns in the delay slot are valid for the
3881 make_return_insns (first)
3884 rtx insn, jump_insn, pat;
3885 rtx real_return_label = end_of_function_label;
3888 /* See if there is a RETURN insn in the function other than the one we
3889 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3890 into a RETURN to jump to it. */
3891 for (insn = first; insn; insn = NEXT_INSN (insn))
3892 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) == RETURN)
3894 real_return_label = get_label_before (insn);
3898 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3899 was equal to END_OF_FUNCTION_LABEL. */
3900 LABEL_NUSES (real_return_label)++;
3902 /* Clear the list of insns to fill so we can use it. */
3903 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
3905 for (insn = first; insn; insn = NEXT_INSN (insn))
3909 /* Only look at filled JUMP_INSNs that go to the end of function
3911 if (GET_CODE (insn) != INSN
3912 || GET_CODE (PATTERN (insn)) != SEQUENCE
3913 || GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) != JUMP_INSN
3914 || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label)
3917 pat = PATTERN (insn);
3918 jump_insn = XVECEXP (pat, 0, 0);
3920 /* If we can't make the jump into a RETURN, redirect it to the best
3921 RETURN and go on to the next insn. */
3922 if (! reorg_redirect_jump (jump_insn, NULL_RTX))
3924 reorg_redirect_jump (jump_insn, real_return_label);
3928 /* See if this RETURN can accept the insns current in its delay slot.
3929 It can if it has more or an equal number of slots and the contents
3930 of each is valid. */
3932 flags = get_jump_flags (jump_insn, JUMP_LABEL (jump_insn));
3933 slots = num_delay_slots (jump_insn);
3934 if (slots >= XVECLEN (pat, 0) - 1)
3936 for (i = 1; i < XVECLEN (pat, 0); i++)
3938 #ifdef ANNUL_IFFALSE_SLOTS
3939 (INSN_ANNULLED_BRANCH_P (jump_insn)
3940 && INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
3941 ? eligible_for_annul_false (jump_insn, i - 1,
3942 XVECEXP (pat, 0, i), flags) :
3944 #ifdef ANNUL_IFTRUE_SLOTS
3945 (INSN_ANNULLED_BRANCH_P (jump_insn)
3946 && ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
3947 ? eligible_for_annul_true (jump_insn, i - 1,
3948 XVECEXP (pat, 0, i), flags) :
3950 eligible_for_delay (jump_insn, i -1, XVECEXP (pat, 0, i), flags)))
3956 if (i == XVECLEN (pat, 0))
3959 /* We have to do something with this insn. If it is an unconditional
3960 RETURN, delete the SEQUENCE and output the individual insns,
3961 followed by the RETURN. Then set things up so we try to find
3962 insns for its delay slots, if it needs some. */
3963 if (GET_CODE (PATTERN (jump_insn)) == RETURN)
3965 rtx prev = PREV_INSN (insn);
3968 for (i = 1; i < XVECLEN (pat, 0); i++)
3969 prev = emit_insn_after (PATTERN (XVECEXP (pat, 0, i)), prev);
3971 insn = emit_jump_insn_after (PATTERN (jump_insn), prev);
3972 emit_barrier_after (insn);
3975 obstack_ptr_grow (&unfilled_slots_obstack, insn);
3978 /* It is probably more efficient to keep this with its current
3979 delay slot as a branch to a RETURN. */
3980 reorg_redirect_jump (jump_insn, real_return_label);
3983 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3984 new delay slots we have created. */
3985 if (--LABEL_NUSES (real_return_label) == 0)
3986 delete_insn (real_return_label);
3988 fill_simple_delay_slots (first, 1);
3989 fill_simple_delay_slots (first, 0);
3993 /* Try to find insns to place in delay slots. */
3996 dbr_schedule (first, file)
4000 rtx insn, next, epilogue_insn = 0;
4003 int old_flag_no_peephole = flag_no_peephole;
4005 /* Execute `final' once in prescan mode to delete any insns that won't be
4006 used. Don't let final try to do any peephole optimization--it will
4007 ruin dataflow information for this pass. */
4009 flag_no_peephole = 1;
4010 final (first, 0, NO_DEBUG, 1, 1);
4011 flag_no_peephole = old_flag_no_peephole;
4014 /* If the current function has no insns other than the prologue and
4015 epilogue, then do not try to fill any delay slots. */
4016 if (n_basic_blocks == 0)
4019 /* Find the highest INSN_UID and allocate and initialize our map from
4020 INSN_UID's to position in code. */
4021 for (max_uid = 0, insn = first; insn; insn = NEXT_INSN (insn))
4023 if (INSN_UID (insn) > max_uid)
4024 max_uid = INSN_UID (insn);
4025 if (GET_CODE (insn) == NOTE
4026 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG)
4027 epilogue_insn = insn;
4030 uid_to_ruid = (int *) alloca ((max_uid + 1) * sizeof (int *));
4031 for (i = 0, insn = first; insn; i++, insn = NEXT_INSN (insn))
4032 uid_to_ruid[INSN_UID (insn)] = i;
4034 /* Initialize the list of insns that need filling. */
4035 if (unfilled_firstobj == 0)
4037 gcc_obstack_init (&unfilled_slots_obstack);
4038 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4041 for (insn = next_active_insn (first); insn; insn = next_active_insn (insn))
4045 INSN_ANNULLED_BRANCH_P (insn) = 0;
4046 INSN_FROM_TARGET_P (insn) = 0;
4048 /* Skip vector tables. We can't get attributes for them. */
4049 if (GET_CODE (insn) == JUMP_INSN
4050 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
4051 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
4054 if (num_delay_slots (insn) > 0)
4055 obstack_ptr_grow (&unfilled_slots_obstack, insn);
4057 /* Ensure all jumps go to the last of a set of consecutive labels. */
4058 if (GET_CODE (insn) == JUMP_INSN && condjump_p (insn)
4059 && JUMP_LABEL (insn) != 0
4060 && ((target = prev_label (next_active_insn (JUMP_LABEL (insn))))
4061 != JUMP_LABEL (insn)))
4062 redirect_jump (insn, target);
4065 /* Indicate what resources are required to be valid at the end of the current
4066 function. The condition code never is and memory always is. If the
4067 frame pointer is needed, it is and so is the stack pointer unless
4068 EXIT_IGNORE_STACK is non-zero. If the frame pointer is not needed, the
4069 stack pointer is. Registers used to return the function value are
4070 needed. Registers holding global variables are needed. */
4072 end_of_function_needs.cc = 0;
4073 end_of_function_needs.memory = 1;
4074 CLEAR_HARD_REG_SET (end_of_function_needs.regs);
4076 if (frame_pointer_needed)
4078 SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM);
4079 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
4080 SET_HARD_REG_BIT (end_of_function_needs.regs, HARD_FRAME_POINTER_REGNUM);
4082 #ifdef EXIT_IGNORE_STACK
4083 if (! EXIT_IGNORE_STACK)
4085 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4088 SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM);
4090 if (current_function_return_rtx != 0
4091 && GET_CODE (current_function_return_rtx) == REG)
4092 mark_referenced_resources (current_function_return_rtx,
4093 &end_of_function_needs, 1);
4095 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4097 SET_HARD_REG_BIT (end_of_function_needs.regs, i);
4099 /* The registers required to be live at the end of the function are
4100 represented in the flow information as being dead just prior to
4101 reaching the end of the function. For example, the return of a value
4102 might be represented by a USE of the return register immediately
4103 followed by an unconditional jump to the return label where the
4104 return label is the end of the RTL chain. The end of the RTL chain
4105 is then taken to mean that the return register is live.
4107 This sequence is no longer maintained when epilogue instructions are
4108 added to the RTL chain. To reconstruct the original meaning, the
4109 start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the
4110 point where these registers become live (start_of_epilogue_needs).
4111 If epilogue instructions are present, the registers set by those
4112 instructions won't have been processed by flow. Thus, those
4113 registers are additionally required at the end of the RTL chain
4114 (end_of_function_needs). */
4116 start_of_epilogue_needs = end_of_function_needs;
4118 while (epilogue_insn = next_nonnote_insn (epilogue_insn))
4119 mark_set_resources (epilogue_insn, &end_of_function_needs, 0, 1);
4121 /* Show we haven't computed an end-of-function label yet. */
4122 end_of_function_label = 0;
4124 /* Allocate and initialize the tables used by mark_target_live_regs. */
4126 = (struct target_info **) alloca ((TARGET_HASH_PRIME
4127 * sizeof (struct target_info *)));
4128 bzero (target_hash_table, TARGET_HASH_PRIME * sizeof (struct target_info *));
4130 bb_ticks = (int *) alloca (n_basic_blocks * sizeof (int));
4131 bzero (bb_ticks, n_basic_blocks * sizeof (int));
4133 /* Initialize the statistics for this function. */
4134 bzero (num_insns_needing_delays, sizeof num_insns_needing_delays);
4135 bzero (num_filled_delays, sizeof num_filled_delays);
4137 /* Now do the delay slot filling. Try everything twice in case earlier
4138 changes make more slots fillable. */
4140 for (reorg_pass_number = 0;
4141 reorg_pass_number < MAX_REORG_PASSES;
4142 reorg_pass_number++)
4144 fill_simple_delay_slots (first, 1);
4145 fill_simple_delay_slots (first, 0);
4146 fill_eager_delay_slots (first);
4147 relax_delay_slots (first);
4150 /* Delete any USE insns made by update_block; subsequent passes don't need
4151 them or know how to deal with them. */
4152 for (insn = first; insn; insn = next)
4154 next = NEXT_INSN (insn);
4156 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE
4157 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn), 0))) == 'i')
4158 next = delete_insn (insn);
4161 /* If we made an end of function label, indicate that it is now
4162 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
4163 If it is now unused, delete it. */
4164 if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0)
4165 delete_insn (end_of_function_label);
4168 if (HAVE_return && end_of_function_label != 0)
4169 make_return_insns (first);
4172 obstack_free (&unfilled_slots_obstack, unfilled_firstobj);
4174 /* It is not clear why the line below is needed, but it does seem to be. */
4175 unfilled_firstobj = (rtx *) obstack_alloc (&unfilled_slots_obstack, 0);
4177 /* Reposition the prologue and epilogue notes in case we moved the
4178 prologue/epilogue insns. */
4179 reposition_prologue_and_epilogue_notes (first);
4183 register int i, j, need_comma;
4185 for (reorg_pass_number = 0;
4186 reorg_pass_number < MAX_REORG_PASSES;
4187 reorg_pass_number++)
4189 fprintf (file, ";; Reorg pass #%d:\n", reorg_pass_number + 1);
4190 for (i = 0; i < NUM_REORG_FUNCTIONS; i++)
4193 fprintf (file, ";; Reorg function #%d\n", i);
4195 fprintf (file, ";; %d insns needing delay slots\n;; ",
4196 num_insns_needing_delays[i][reorg_pass_number]);
4198 for (j = 0; j < MAX_DELAY_HISTOGRAM; j++)
4199 if (num_filled_delays[i][j][reorg_pass_number])
4202 fprintf (file, ", ");
4204 fprintf (file, "%d got %d delays",
4205 num_filled_delays[i][j][reorg_pass_number], j);
4207 fprintf (file, "\n");
4212 #endif /* DELAY_SLOTS */