1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-99, 2000 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table * reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void maybe_fix_stack_asms PARAMS ((void));
370 static void copy_reloads PARAMS ((struct insn_chain *));
371 static void calculate_needs_all_insns PARAMS ((int));
372 static int find_reg PARAMS ((struct insn_chain *, int,
374 static void find_reload_regs PARAMS ((struct insn_chain *, FILE *));
375 static void select_reload_regs PARAMS ((FILE *));
376 static void delete_caller_save_insns PARAMS ((void));
378 static void spill_failure PARAMS ((rtx, enum reg_class));
379 static void count_spilled_pseudo PARAMS ((int, int, int));
380 static void delete_dead_insn PARAMS ((rtx));
381 static void alter_reg PARAMS ((int, int));
382 static void set_label_offsets PARAMS ((rtx, rtx, int));
383 static void check_eliminable_occurrences PARAMS ((rtx));
384 static void elimination_effects PARAMS ((rtx, enum machine_mode));
385 static int eliminate_regs_in_insn PARAMS ((rtx, int));
386 static void update_eliminable_offsets PARAMS ((void));
387 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
388 static void set_initial_elim_offsets PARAMS ((void));
389 static void verify_initial_elim_offsets PARAMS ((void));
390 static void set_initial_label_offsets PARAMS ((void));
391 static void set_offsets_for_label PARAMS ((rtx));
392 static void init_elim_table PARAMS ((void));
393 static void update_eliminables PARAMS ((HARD_REG_SET *));
394 static void spill_hard_reg PARAMS ((int, FILE *, int));
395 static int finish_spills PARAMS ((int, FILE *));
396 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PARAMS ((rtx));
398 static void count_pseudo PARAMS ((int));
399 static void order_regs_for_reload PARAMS ((struct insn_chain *));
400 static void reload_as_needed PARAMS ((int));
401 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
402 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
403 static void mark_reload_reg_in_use PARAMS ((int, int, enum reload_type,
405 static void clear_reload_reg_in_use PARAMS ((int, int, enum reload_type,
407 static int reload_reg_free_p PARAMS ((int, int, enum reload_type));
408 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
409 rtx, rtx, int, int));
410 static int reload_reg_reaches_end_p PARAMS ((int, int, enum reload_type));
411 static int allocate_reload_reg PARAMS ((struct insn_chain *, int, int));
412 static void failed_reload PARAMS ((rtx, int));
413 static int set_reload_reg PARAMS ((int, int));
414 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
415 static void choose_reload_regs PARAMS ((struct insn_chain *));
416 static void merge_assigned_reloads PARAMS ((rtx));
417 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
418 struct reload *, rtx, int));
419 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
420 struct reload *, int));
421 static void do_input_reload PARAMS ((struct insn_chain *,
422 struct reload *, int));
423 static void do_output_reload PARAMS ((struct insn_chain *,
424 struct reload *, int));
425 static void emit_reload_insns PARAMS ((struct insn_chain *));
426 static void delete_output_reload PARAMS ((rtx, int, int));
427 static void delete_address_reloads PARAMS ((rtx, rtx));
428 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
429 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
430 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
431 static void reload_cse_regs_1 PARAMS ((rtx));
432 static void reload_cse_invalidate_regno PARAMS ((int, enum machine_mode, int));
433 static int reload_cse_mem_conflict_p PARAMS ((rtx, rtx));
434 static void reload_cse_invalidate_mem PARAMS ((rtx));
435 static void reload_cse_invalidate_rtx PARAMS ((rtx, rtx, void *));
436 static int reload_cse_regno_equal_p PARAMS ((int, rtx, enum machine_mode));
437 static int reload_cse_noop_set_p PARAMS ((rtx, rtx));
438 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
439 static int reload_cse_simplify_operands PARAMS ((rtx));
440 static void reload_cse_check_clobber PARAMS ((rtx, rtx, void *));
441 static void reload_cse_record_set PARAMS ((rtx, rtx));
442 static void reload_combine PARAMS ((void));
443 static void reload_combine_note_use PARAMS ((rtx *, rtx));
444 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
445 static void reload_cse_move2add PARAMS ((rtx));
446 static void move2add_note_store PARAMS ((rtx, rtx, void *));
448 static void add_auto_inc_notes PARAMS ((rtx, rtx));
450 static rtx gen_mode_int PARAMS ((enum machine_mode,
452 static void failed_reload PARAMS ((rtx, int));
453 static int set_reload_reg PARAMS ((int, int));
454 extern void dump_needs PARAMS ((struct insn_chain *, FILE *));
456 /* Initialize the reload pass once per compilation. */
463 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
464 Set spill_indirect_levels to the number of levels such addressing is
465 permitted, zero if it is not permitted at all. */
468 = gen_rtx_MEM (Pmode,
471 LAST_VIRTUAL_REGISTER + 1),
473 spill_indirect_levels = 0;
475 while (memory_address_p (QImode, tem))
477 spill_indirect_levels++;
478 tem = gen_rtx_MEM (Pmode, tem);
481 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
483 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
484 indirect_symref_ok = memory_address_p (QImode, tem);
486 /* See if reg+reg is a valid (and offsettable) address. */
488 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
490 tem = gen_rtx_PLUS (Pmode,
491 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
492 gen_rtx_REG (Pmode, i));
494 /* This way, we make sure that reg+reg is an offsettable address. */
495 tem = plus_constant (tem, 4);
497 if (memory_address_p (QImode, tem))
499 double_reg_address_ok = 1;
504 /* Initialize obstack for our rtl allocation. */
505 gcc_obstack_init (&reload_obstack);
506 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
508 INIT_REG_SET (&spilled_pseudos);
509 INIT_REG_SET (&pseudos_counted);
512 /* List of insn chains that are currently unused. */
513 static struct insn_chain *unused_insn_chains = 0;
515 /* Allocate an empty insn_chain structure. */
519 struct insn_chain *c;
521 if (unused_insn_chains == 0)
523 c = (struct insn_chain *)
524 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
525 INIT_REG_SET (&c->live_throughout);
526 INIT_REG_SET (&c->dead_or_set);
530 c = unused_insn_chains;
531 unused_insn_chains = c->next;
533 c->is_caller_save_insn = 0;
534 c->need_operand_change = 0;
540 /* Small utility function to set all regs in hard reg set TO which are
541 allocated to pseudos in regset FROM. */
543 compute_use_by_pseudos (to, from)
548 EXECUTE_IF_SET_IN_REG_SET
549 (from, FIRST_PSEUDO_REGISTER, regno,
551 int r = reg_renumber[regno];
555 /* reload_combine uses the information from
556 BASIC_BLOCK->global_live_at_start, which might still
557 contain registers that have not actually been allocated
558 since they have an equivalence. */
559 if (! reload_completed)
564 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
566 SET_HARD_REG_BIT (*to, r + nregs);
571 /* Global variables used by reload and its subroutines. */
573 /* Set during calculate_needs if an insn needs register elimination. */
574 static int something_needs_elimination;
575 /* Set during calculate_needs if an insn needs an operand changed. */
576 int something_needs_operands_changed;
578 /* Nonzero means we couldn't get enough spill regs. */
581 /* Main entry point for the reload pass.
583 FIRST is the first insn of the function being compiled.
585 GLOBAL nonzero means we were called from global_alloc
586 and should attempt to reallocate any pseudoregs that we
587 displace from hard regs we will use for reloads.
588 If GLOBAL is zero, we do not have enough information to do that,
589 so any pseudo reg that is spilled must go to the stack.
591 DUMPFILE is the global-reg debugging dump file stream, or 0.
592 If it is nonzero, messages are written to it to describe
593 which registers are seized as reload regs, which pseudo regs
594 are spilled from them, and where the pseudo regs are reallocated to.
596 Return value is nonzero if reload failed
597 and we must not do any more for this function. */
600 reload (first, global, dumpfile)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
635 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
653 if (! call_used_regs[i] && ! fixed_regs[i])
654 regs_ever_live[i] = 1;
657 /* Find all the pseudo registers that didn't get hard regs
658 but do have known equivalent constants or memory slots.
659 These include parameters (known equivalent to parameter slots)
660 and cse'd or loop-moved constant memory addresses.
662 Record constant equivalents in reg_equiv_constant
663 so they will be substituted by find_reloads.
664 Record memory equivalents in reg_mem_equiv so they can
665 be substituted eventually by altering the REG-rtx's. */
667 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
672 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
673 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
674 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
675 pseudo_forbidden_regs
676 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
678 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
680 CLEAR_HARD_REG_SET (bad_spill_regs_global);
682 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
683 Also find all paradoxical subregs and find largest such for each pseudo.
684 On machines with small register classes, record hard registers that
685 are used for user variables. These can never be used for spills.
686 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
687 caller-saved registers must be marked live. */
689 num_eliminable_invariants = 0;
690 for (insn = first; insn; insn = NEXT_INSN (insn))
692 rtx set = single_set (insn);
694 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
695 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
697 if (! call_used_regs[i])
698 regs_ever_live[i] = 1;
700 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
702 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
704 #ifdef LEGITIMATE_PIC_OPERAND_P
705 && (! function_invariant_p (XEXP (note, 0))
707 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
711 rtx x = XEXP (note, 0);
712 i = REGNO (SET_DEST (set));
713 if (i > LAST_VIRTUAL_REGISTER)
715 if (GET_CODE (x) == MEM)
717 /* If the operand is a PLUS, the MEM may be shared,
718 so make sure we have an unshared copy here. */
719 if (GET_CODE (XEXP (x, 0)) == PLUS)
722 reg_equiv_memory_loc[i] = x;
724 else if (function_invariant_p (x))
726 if (GET_CODE (x) == PLUS)
728 /* This is PLUS of frame pointer and a constant,
729 and might be shared. Unshare it. */
730 reg_equiv_constant[i] = copy_rtx (x);
731 num_eliminable_invariants++;
733 else if (x == frame_pointer_rtx
734 || x == arg_pointer_rtx)
736 reg_equiv_constant[i] = x;
737 num_eliminable_invariants++;
739 else if (LEGITIMATE_CONSTANT_P (x))
740 reg_equiv_constant[i] = x;
742 reg_equiv_memory_loc[i]
743 = force_const_mem (GET_MODE (SET_DEST (set)), x);
748 /* If this register is being made equivalent to a MEM
749 and the MEM is not SET_SRC, the equivalencing insn
750 is one with the MEM as a SET_DEST and it occurs later.
751 So don't mark this insn now. */
752 if (GET_CODE (x) != MEM
753 || rtx_equal_p (SET_SRC (set), x))
755 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
760 /* If this insn is setting a MEM from a register equivalent to it,
761 this is the equivalencing insn. */
762 else if (set && GET_CODE (SET_DEST (set)) == MEM
763 && GET_CODE (SET_SRC (set)) == REG
764 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
765 && rtx_equal_p (SET_DEST (set),
766 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
767 reg_equiv_init[REGNO (SET_SRC (set))]
768 = gen_rtx_INSN_LIST (VOIDmode, insn,
769 reg_equiv_init[REGNO (SET_SRC (set))]);
771 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
772 scan_paradoxical_subregs (PATTERN (insn));
777 num_labels = max_label_num () - get_first_label_num ();
779 /* Allocate the tables used to store offset information at labels. */
780 /* We used to use alloca here, but the size of what it would try to
781 allocate would occasionally cause it to exceed the stack limit and
782 cause a core dump. */
783 real_known_ptr = xmalloc (num_labels);
785 = (int (*)[NUM_ELIMINABLE_REGS])
786 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
788 offsets_known_at = real_known_ptr - get_first_label_num ();
790 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
792 /* Alter each pseudo-reg rtx to contain its hard reg number.
793 Assign stack slots to the pseudos that lack hard regs or equivalents.
794 Do not touch virtual registers. */
796 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
806 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
807 || GET_CODE (insn) == CALL_INSN)
808 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
810 maybe_fix_stack_asms ();
812 insns_need_reload = 0;
813 something_needs_elimination = 0;
815 /* Initialize to -1, which means take the first spill register. */
818 /* Spill any hard regs that we know we can't eliminate. */
819 CLEAR_HARD_REG_SET (used_spill_regs);
820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
821 if (! ep->can_eliminate)
822 spill_hard_reg (ep->from, dumpfile, 1);
824 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
825 if (frame_pointer_needed)
826 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
828 finish_spills (global, dumpfile);
830 /* From now on, we may need to generate moves differently. We may also
831 allow modifications of insns which cause them to not be recognized.
832 Any such modifications will be cleaned up during reload itself. */
833 reload_in_progress = 1;
835 /* This loop scans the entire function each go-round
836 and repeats until one repetition spills no additional hard regs. */
839 int something_changed;
842 HOST_WIDE_INT starting_frame_size;
844 /* Round size of stack frame to stack_alignment_needed. This must be done
845 here because the stack size may be a part of the offset computation
846 for register elimination, and there might have been new stack slots
847 created in the last iteration of this loop. */
848 if (cfun->stack_alignment_needed)
849 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
851 starting_frame_size = get_frame_size ();
853 set_initial_elim_offsets ();
854 set_initial_label_offsets ();
856 /* For each pseudo register that has an equivalent location defined,
857 try to eliminate any eliminable registers (such as the frame pointer)
858 assuming initial offsets for the replacement register, which
861 If the resulting location is directly addressable, substitute
862 the MEM we just got directly for the old REG.
864 If it is not addressable but is a constant or the sum of a hard reg
865 and constant, it is probably not addressable because the constant is
866 out of range, in that case record the address; we will generate
867 hairy code to compute the address in a register each time it is
868 needed. Similarly if it is a hard register, but one that is not
869 valid as an address register.
871 If the location is not addressable, but does not have one of the
872 above forms, assign a stack slot. We have to do this to avoid the
873 potential of producing lots of reloads if, e.g., a location involves
874 a pseudo that didn't get a hard register and has an equivalent memory
875 location that also involves a pseudo that didn't get a hard register.
877 Perhaps at some point we will improve reload_when_needed handling
878 so this problem goes away. But that's very hairy. */
880 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
881 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
883 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
885 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
887 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
888 else if (CONSTANT_P (XEXP (x, 0))
889 || (GET_CODE (XEXP (x, 0)) == REG
890 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
891 || (GET_CODE (XEXP (x, 0)) == PLUS
892 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
893 && (REGNO (XEXP (XEXP (x, 0), 0))
894 < FIRST_PSEUDO_REGISTER)
895 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
896 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
899 /* Make a new stack slot. Then indicate that something
900 changed so we go back and recompute offsets for
901 eliminable registers because the allocation of memory
902 below might change some offset. reg_equiv_{mem,address}
903 will be set up for this pseudo on the next pass around
905 reg_equiv_memory_loc[i] = 0;
906 reg_equiv_init[i] = 0;
911 if (caller_save_needed)
914 /* If we allocated another stack slot, redo elimination bookkeeping. */
915 if (starting_frame_size != get_frame_size ())
918 if (caller_save_needed)
920 save_call_clobbered_regs ();
921 /* That might have allocated new insn_chain structures. */
922 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
925 calculate_needs_all_insns (global);
927 CLEAR_REG_SET (&spilled_pseudos);
930 something_changed = 0;
932 /* If we allocated any new memory locations, make another pass
933 since it might have changed elimination offsets. */
934 if (starting_frame_size != get_frame_size ())
935 something_changed = 1;
938 HARD_REG_SET to_spill;
939 CLEAR_HARD_REG_SET (to_spill);
940 update_eliminables (&to_spill);
941 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
942 if (TEST_HARD_REG_BIT (to_spill, i))
944 spill_hard_reg (i, dumpfile, 1);
947 /* Regardless of the state of spills, if we previously had
948 a register that we thought we could eliminate, but no can
949 not eliminate, we must run another pass.
951 Consider pseudos which have an entry in reg_equiv_* which
952 reference an eliminable register. We must make another pass
953 to update reg_equiv_* so that we do not substitute in the
954 old value from when we thought the elimination could be
956 something_changed = 1;
960 select_reload_regs (dumpfile);
964 if (insns_need_reload != 0 || did_spill)
965 something_changed |= finish_spills (global, dumpfile);
967 if (! something_changed)
970 if (caller_save_needed)
971 delete_caller_save_insns ();
973 obstack_free (&reload_obstack, reload_firstobj);
976 /* If global-alloc was run, notify it of any register eliminations we have
979 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
980 if (ep->can_eliminate)
981 mark_elimination (ep->from, ep->to);
983 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
984 If that insn didn't set the register (i.e., it copied the register to
985 memory), just delete that insn instead of the equivalencing insn plus
986 anything now dead. If we call delete_dead_insn on that insn, we may
987 delete the insn that actually sets the register if the register dies
988 there and that is incorrect. */
990 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
992 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
995 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
997 rtx equiv_insn = XEXP (list, 0);
998 if (GET_CODE (equiv_insn) == NOTE)
1000 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1001 delete_dead_insn (equiv_insn);
1004 PUT_CODE (equiv_insn, NOTE);
1005 NOTE_SOURCE_FILE (equiv_insn) = 0;
1006 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1012 /* Use the reload registers where necessary
1013 by generating move instructions to move the must-be-register
1014 values into or out of the reload registers. */
1016 if (insns_need_reload != 0 || something_needs_elimination
1017 || something_needs_operands_changed)
1019 int old_frame_size = get_frame_size ();
1021 reload_as_needed (global);
1023 if (old_frame_size != get_frame_size ())
1027 verify_initial_elim_offsets ();
1030 /* If we were able to eliminate the frame pointer, show that it is no
1031 longer live at the start of any basic block. If it ls live by
1032 virtue of being in a pseudo, that pseudo will be marked live
1033 and hence the frame pointer will be known to be live via that
1036 if (! frame_pointer_needed)
1037 for (i = 0; i < n_basic_blocks; i++)
1038 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1039 HARD_FRAME_POINTER_REGNUM);
1041 /* Come here (with failure set nonzero) if we can't get enough spill regs
1042 and we decide not to abort about it. */
1045 CLEAR_REG_SET (&spilled_pseudos);
1046 reload_in_progress = 0;
1048 /* Now eliminate all pseudo regs by modifying them into
1049 their equivalent memory references.
1050 The REG-rtx's for the pseudos are modified in place,
1051 so all insns that used to refer to them now refer to memory.
1053 For a reg that has a reg_equiv_address, all those insns
1054 were changed by reloading so that no insns refer to it any longer;
1055 but the DECL_RTL of a variable decl may refer to it,
1056 and if so this causes the debugging info to mention the variable. */
1058 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1063 int is_readonly = 0;
1065 if (reg_equiv_memory_loc[i])
1067 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1068 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1069 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1072 if (reg_equiv_mem[i])
1073 addr = XEXP (reg_equiv_mem[i], 0);
1075 if (reg_equiv_address[i])
1076 addr = reg_equiv_address[i];
1080 if (reg_renumber[i] < 0)
1082 rtx reg = regno_reg_rtx[i];
1083 PUT_CODE (reg, MEM);
1084 XEXP (reg, 0) = addr;
1085 REG_USERVAR_P (reg) = 0;
1086 RTX_UNCHANGING_P (reg) = is_readonly;
1087 MEM_IN_STRUCT_P (reg) = in_struct;
1088 MEM_SCALAR_P (reg) = is_scalar;
1089 /* We have no alias information about this newly created
1091 MEM_ALIAS_SET (reg) = 0;
1093 else if (reg_equiv_mem[i])
1094 XEXP (reg_equiv_mem[i], 0) = addr;
1098 /* We must set reload_completed now since the cleanup_subreg_operands call
1099 below will re-recognize each insn and reload may have generated insns
1100 which are only valid during and after reload. */
1101 reload_completed = 1;
1103 /* Make a pass over all the insns and delete all USEs which we inserted
1104 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1105 notes. Delete all CLOBBER insns that don't refer to the return value
1106 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1107 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1108 and regenerate REG_INC notes that may have been moved around. */
1110 for (insn = first; insn; insn = NEXT_INSN (insn))
1111 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1115 if ((GET_CODE (PATTERN (insn)) == USE
1116 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1117 || (GET_CODE (PATTERN (insn)) == CLOBBER
1118 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1119 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1121 PUT_CODE (insn, NOTE);
1122 NOTE_SOURCE_FILE (insn) = 0;
1123 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1127 pnote = ®_NOTES (insn);
1130 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1131 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1132 || REG_NOTE_KIND (*pnote) == REG_INC
1133 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1134 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1135 *pnote = XEXP (*pnote, 1);
1137 pnote = &XEXP (*pnote, 1);
1141 add_auto_inc_notes (insn, PATTERN (insn));
1144 /* And simplify (subreg (reg)) if it appears as an operand. */
1145 cleanup_subreg_operands (insn);
1148 /* If we are doing stack checking, give a warning if this function's
1149 frame size is larger than we expect. */
1150 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1152 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1153 static int verbose_warned = 0;
1155 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1156 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1157 size += UNITS_PER_WORD;
1159 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1161 warning ("frame size too large for reliable stack checking");
1162 if (! verbose_warned)
1164 warning ("try reducing the number of local variables");
1170 /* Indicate that we no longer have known memory locations or constants. */
1171 if (reg_equiv_constant)
1172 free (reg_equiv_constant);
1173 reg_equiv_constant = 0;
1174 if (reg_equiv_memory_loc)
1175 free (reg_equiv_memory_loc);
1176 reg_equiv_memory_loc = 0;
1179 free (real_known_ptr);
1183 free (reg_equiv_mem);
1184 free (reg_equiv_init);
1185 free (reg_equiv_address);
1186 free (reg_max_ref_width);
1187 free (reg_old_renumber);
1188 free (pseudo_previous_regs);
1189 free (pseudo_forbidden_regs);
1191 CLEAR_HARD_REG_SET (used_spill_regs);
1192 for (i = 0; i < n_spills; i++)
1193 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1195 /* Free all the insn_chain structures at once. */
1196 obstack_free (&reload_obstack, reload_startobj);
1197 unused_insn_chains = 0;
1202 /* Yet another special case. Unfortunately, reg-stack forces people to
1203 write incorrect clobbers in asm statements. These clobbers must not
1204 cause the register to appear in bad_spill_regs, otherwise we'll call
1205 fatal_insn later. We clear the corresponding regnos in the live
1206 register sets to avoid this.
1207 The whole thing is rather sick, I'm afraid. */
1209 maybe_fix_stack_asms ()
1212 const char *constraints[MAX_RECOG_OPERANDS];
1213 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1214 struct insn_chain *chain;
1216 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1219 HARD_REG_SET clobbered, allowed;
1222 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1223 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1225 pat = PATTERN (chain->insn);
1226 if (GET_CODE (pat) != PARALLEL)
1229 CLEAR_HARD_REG_SET (clobbered);
1230 CLEAR_HARD_REG_SET (allowed);
1232 /* First, make a mask of all stack regs that are clobbered. */
1233 for (i = 0; i < XVECLEN (pat, 0); i++)
1235 rtx t = XVECEXP (pat, 0, i);
1236 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1237 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1240 /* Get the operand values and constraints out of the insn. */
1241 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1242 constraints, operand_mode);
1244 /* For every operand, see what registers are allowed. */
1245 for (i = 0; i < noperands; i++)
1247 const char *p = constraints[i];
1248 /* For every alternative, we compute the class of registers allowed
1249 for reloading in CLS, and merge its contents into the reg set
1251 int cls = (int) NO_REGS;
1257 if (c == '\0' || c == ',' || c == '#')
1259 /* End of one alternative - mark the regs in the current
1260 class, and reset the class. */
1261 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1266 } while (c != '\0' && c != ',');
1274 case '=': case '+': case '*': case '%': case '?': case '!':
1275 case '0': case '1': case '2': case '3': case '4': case 'm':
1276 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1277 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1278 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1280 #ifdef EXTRA_CONSTRAINT
1281 case 'Q': case 'R': case 'S': case 'T': case 'U':
1286 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1291 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1295 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1300 /* Those of the registers which are clobbered, but allowed by the
1301 constraints, must be usable as reload registers. So clear them
1302 out of the life information. */
1303 AND_HARD_REG_SET (allowed, clobbered);
1304 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1305 if (TEST_HARD_REG_BIT (allowed, i))
1307 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1308 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1315 /* Copy the global variables n_reloads and rld into the corresponding elts
1318 copy_reloads (chain)
1319 struct insn_chain *chain;
1321 chain->n_reloads = n_reloads;
1323 = (struct reload *) obstack_alloc (&reload_obstack,
1324 n_reloads * sizeof (struct reload));
1325 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1326 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1329 /* Walk the chain of insns, and determine for each whether it needs reloads
1330 and/or eliminations. Build the corresponding insns_need_reload list, and
1331 set something_needs_elimination as appropriate. */
1333 calculate_needs_all_insns (global)
1336 struct insn_chain **pprev_reload = &insns_need_reload;
1337 struct insn_chain *chain;
1339 something_needs_elimination = 0;
1341 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1342 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1344 rtx insn = chain->insn;
1346 /* Clear out the shortcuts. */
1347 chain->n_reloads = 0;
1348 chain->need_elim = 0;
1349 chain->need_reload = 0;
1350 chain->need_operand_change = 0;
1352 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1353 include REG_LABEL), we need to see what effects this has on the
1354 known offsets at labels. */
1356 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1357 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1358 && REG_NOTES (insn) != 0))
1359 set_label_offsets (insn, insn, 0);
1361 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1363 rtx old_body = PATTERN (insn);
1364 int old_code = INSN_CODE (insn);
1365 rtx old_notes = REG_NOTES (insn);
1366 int did_elimination = 0;
1367 int operands_changed = 0;
1368 rtx set = single_set (insn);
1370 /* Skip insns that only set an equivalence. */
1371 if (set && GET_CODE (SET_DEST (set)) == REG
1372 && reg_renumber[REGNO (SET_DEST (set))] < 0
1373 && reg_equiv_constant[REGNO (SET_DEST (set))])
1376 /* If needed, eliminate any eliminable registers. */
1377 if (num_eliminable || num_eliminable_invariants)
1378 did_elimination = eliminate_regs_in_insn (insn, 0);
1380 /* Analyze the instruction. */
1381 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1382 global, spill_reg_order);
1384 /* If a no-op set needs more than one reload, this is likely
1385 to be something that needs input address reloads. We
1386 can't get rid of this cleanly later, and it is of no use
1387 anyway, so discard it now.
1388 We only do this when expensive_optimizations is enabled,
1389 since this complements reload inheritance / output
1390 reload deletion, and it can make debugging harder. */
1391 if (flag_expensive_optimizations && n_reloads > 1)
1393 rtx set = single_set (insn);
1395 && SET_SRC (set) == SET_DEST (set)
1396 && GET_CODE (SET_SRC (set)) == REG
1397 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1399 PUT_CODE (insn, NOTE);
1400 NOTE_SOURCE_FILE (insn) = 0;
1401 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1406 update_eliminable_offsets ();
1408 /* Remember for later shortcuts which insns had any reloads or
1409 register eliminations. */
1410 chain->need_elim = did_elimination;
1411 chain->need_reload = n_reloads > 0;
1412 chain->need_operand_change = operands_changed;
1414 /* Discard any register replacements done. */
1415 if (did_elimination)
1417 obstack_free (&reload_obstack, reload_insn_firstobj);
1418 PATTERN (insn) = old_body;
1419 INSN_CODE (insn) = old_code;
1420 REG_NOTES (insn) = old_notes;
1421 something_needs_elimination = 1;
1424 something_needs_operands_changed |= operands_changed;
1428 copy_reloads (chain);
1429 *pprev_reload = chain;
1430 pprev_reload = &chain->next_need_reload;
1437 /* Comparison function for qsort to decide which of two reloads
1438 should be handled first. *P1 and *P2 are the reload numbers. */
1441 reload_reg_class_lower (r1p, r2p)
1445 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
1448 /* Consider required reloads before optional ones. */
1449 t = rld[r1].optional - rld[r2].optional;
1453 /* Count all solitary classes before non-solitary ones. */
1454 t = ((reg_class_size[(int) rld[r2].class] == 1)
1455 - (reg_class_size[(int) rld[r1].class] == 1));
1459 /* Aside from solitaires, consider all multi-reg groups first. */
1460 t = rld[r2].nregs - rld[r1].nregs;
1464 /* Consider reloads in order of increasing reg-class number. */
1465 t = (int) rld[r1].class - (int) rld[r2].class;
1469 /* If reloads are equally urgent, sort by reload number,
1470 so that the results of qsort leave nothing to chance. */
1474 /* The cost of spilling each hard reg. */
1475 static int spill_cost[FIRST_PSEUDO_REGISTER];
1477 /* When spilling multiple hard registers, we use SPILL_COST for the first
1478 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1479 only the first hard reg for a multi-reg pseudo. */
1480 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1482 /* Update the spill cost arrays, considering that pseudo REG is live. */
1487 int n_refs = REG_N_REFS (reg);
1488 int r = reg_renumber[reg];
1491 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1492 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1495 SET_REGNO_REG_SET (&pseudos_counted, reg);
1500 spill_add_cost[r] += n_refs;
1502 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1504 spill_cost[r + nregs] += n_refs;
1507 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1508 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1510 order_regs_for_reload (chain)
1511 struct insn_chain *chain;
1515 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
1517 memset (spill_cost, 0, sizeof spill_cost);
1518 memset (spill_add_cost, 0, sizeof spill_add_cost);
1520 /* Count number of uses of each hard reg by pseudo regs allocated to it
1521 and then order them by decreasing use. */
1523 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1525 /* Test the various reasons why we can't use a register for
1526 spilling in this insn. */
1528 || REGNO_REG_SET_P (&chain->live_throughout, i)
1529 || REGNO_REG_SET_P (&chain->dead_or_set, i))
1530 SET_HARD_REG_BIT (bad_spill_regs, i);
1532 /* Now find out which pseudos are allocated to it, and update
1534 CLEAR_REG_SET (&pseudos_counted);
1536 EXECUTE_IF_SET_IN_REG_SET
1537 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1541 EXECUTE_IF_SET_IN_REG_SET
1542 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1546 CLEAR_REG_SET (&pseudos_counted);
1549 /* Vector of reload-numbers showing the order in which the reloads should
1551 static short reload_order[MAX_RELOADS];
1553 /* This is used to keep track of the spill regs used in one insn. */
1554 static HARD_REG_SET used_spill_regs_local;
1556 /* We decided to spill hard register SPILLED, which has a size of
1557 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1558 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1559 update SPILL_COST/SPILL_ADD_COST. */
1561 count_spilled_pseudo (spilled, spilled_nregs, reg)
1562 int spilled, spilled_nregs, reg;
1564 int r = reg_renumber[reg];
1565 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1567 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1568 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1571 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1573 spill_add_cost[r] -= REG_N_REFS (reg);
1575 spill_cost[r + nregs] -= REG_N_REFS (reg);
1578 /* Find reload register to use for reload number ORDER. */
1581 find_reg (chain, order, dumpfile)
1582 struct insn_chain *chain;
1586 int rnum = reload_order[order];
1587 struct reload *rl = rld + rnum;
1588 int best_cost = INT_MAX;
1591 HARD_REG_SET not_usable;
1592 HARD_REG_SET used_by_other_reload;
1594 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1595 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1596 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1598 CLEAR_HARD_REG_SET (used_by_other_reload);
1599 for (i = 0; i < order; i++)
1601 int other = reload_order[i];
1602 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1603 for (j = 0; j < rld[other].nregs; j++)
1604 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1607 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1610 if (! TEST_HARD_REG_BIT (not_usable, regno)
1611 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1612 && HARD_REGNO_MODE_OK (regno, rl->mode))
1614 int this_cost = spill_cost[regno];
1616 int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1618 for (j = 1; j < this_nregs; j++)
1620 this_cost += spill_add_cost[regno + j];
1621 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1622 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1627 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1629 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1631 if (this_cost < best_cost
1632 /* Among registers with equal cost, prefer caller-saved ones, or
1633 use REG_ALLOC_ORDER if it is defined. */
1634 || (this_cost == best_cost
1635 #ifdef REG_ALLOC_ORDER
1636 && (inv_reg_alloc_order[regno]
1637 < inv_reg_alloc_order[best_reg])
1639 && call_used_regs[regno]
1640 && ! call_used_regs[best_reg]
1645 best_cost = this_cost;
1652 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1653 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1654 rl->regno = best_reg;
1656 EXECUTE_IF_SET_IN_REG_SET
1657 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1659 count_spilled_pseudo (best_reg, rl->nregs, j);
1661 EXECUTE_IF_SET_IN_REG_SET
1662 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1664 count_spilled_pseudo (best_reg, rl->nregs, j);
1667 for (i = 0; i < rl->nregs; i++)
1669 if (spill_cost[best_reg + i] != 0
1670 || spill_add_cost[best_reg + i] != 0)
1672 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1677 /* Find more reload regs to satisfy the remaining need of an insn, which
1679 Do it by ascending class number, since otherwise a reg
1680 might be spilled for a big class and might fail to count
1681 for a smaller class even though it belongs to that class. */
1684 find_reload_regs (chain, dumpfile)
1685 struct insn_chain *chain;
1690 /* In order to be certain of getting the registers we need,
1691 we must sort the reloads into order of increasing register class.
1692 Then our grabbing of reload registers will parallel the process
1693 that provided the reload registers. */
1694 for (i = 0; i < chain->n_reloads; i++)
1696 /* Show whether this reload already has a hard reg. */
1697 if (chain->rld[i].reg_rtx)
1699 int regno = REGNO (chain->rld[i].reg_rtx);
1700 chain->rld[i].regno = regno;
1701 chain->rld[i].nregs = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1704 chain->rld[i].regno = -1;
1705 reload_order[i] = i;
1708 n_reloads = chain->n_reloads;
1709 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1711 CLEAR_HARD_REG_SET (used_spill_regs_local);
1714 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1716 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1718 /* Compute the order of preference for hard registers to spill. */
1720 order_regs_for_reload (chain);
1722 for (i = 0; i < n_reloads; i++)
1724 int r = reload_order[i];
1726 /* Ignore reloads that got marked inoperative. */
1727 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1728 && ! rld[r].optional
1729 && rld[r].regno == -1)
1730 if (! find_reg (chain, i, dumpfile))
1732 spill_failure (chain->insn, rld[r].class);
1738 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1739 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1741 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1745 select_reload_regs (dumpfile)
1748 struct insn_chain *chain;
1750 /* Try to satisfy the needs for each insn. */
1751 for (chain = insns_need_reload; chain != 0;
1752 chain = chain->next_need_reload)
1753 find_reload_regs (chain, dumpfile);
1756 /* Delete all insns that were inserted by emit_caller_save_insns during
1759 delete_caller_save_insns ()
1761 struct insn_chain *c = reload_insn_chain;
1765 while (c != 0 && c->is_caller_save_insn)
1767 struct insn_chain *next = c->next;
1770 if (insn == BLOCK_HEAD (c->block))
1771 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1772 if (insn == BLOCK_END (c->block))
1773 BLOCK_END (c->block) = PREV_INSN (insn);
1774 if (c == reload_insn_chain)
1775 reload_insn_chain = next;
1777 if (NEXT_INSN (insn) != 0)
1778 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1779 if (PREV_INSN (insn) != 0)
1780 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1783 next->prev = c->prev;
1785 c->prev->next = next;
1786 c->next = unused_insn_chains;
1787 unused_insn_chains = c;
1795 /* Handle the failure to find a register to spill.
1796 INSN should be one of the insns which needed this particular spill reg. */
1799 spill_failure (insn, class)
1801 enum reg_class class;
1803 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1804 if (asm_noperands (PATTERN (insn)) >= 0)
1805 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1806 reg_class_names[class]);
1809 error ("Unable to find a register to spill in class `%s'.",
1810 reg_class_names[class]);
1811 fatal_insn ("This is the insn:", insn);
1815 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1816 data that is dead in INSN. */
1819 delete_dead_insn (insn)
1822 rtx prev = prev_real_insn (insn);
1825 /* If the previous insn sets a register that dies in our insn, delete it
1827 if (prev && GET_CODE (PATTERN (prev)) == SET
1828 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1829 && reg_mentioned_p (prev_dest, PATTERN (insn))
1830 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1831 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1832 delete_dead_insn (prev);
1834 PUT_CODE (insn, NOTE);
1835 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1836 NOTE_SOURCE_FILE (insn) = 0;
1839 /* Modify the home of pseudo-reg I.
1840 The new home is present in reg_renumber[I].
1842 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1843 or it may be -1, meaning there is none or it is not relevant.
1844 This is used so that all pseudos spilled from a given hard reg
1845 can share one stack slot. */
1848 alter_reg (i, from_reg)
1852 /* When outputting an inline function, this can happen
1853 for a reg that isn't actually used. */
1854 if (regno_reg_rtx[i] == 0)
1857 /* If the reg got changed to a MEM at rtl-generation time,
1859 if (GET_CODE (regno_reg_rtx[i]) != REG)
1862 /* Modify the reg-rtx to contain the new hard reg
1863 number or else to contain its pseudo reg number. */
1864 REGNO (regno_reg_rtx[i])
1865 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1867 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1868 allocate a stack slot for it. */
1870 if (reg_renumber[i] < 0
1871 && REG_N_REFS (i) > 0
1872 && reg_equiv_constant[i] == 0
1873 && reg_equiv_memory_loc[i] == 0)
1876 int inherent_size = PSEUDO_REGNO_BYTES (i);
1877 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1880 /* Each pseudo reg has an inherent size which comes from its own mode,
1881 and a total size which provides room for paradoxical subregs
1882 which refer to the pseudo reg in wider modes.
1884 We can use a slot already allocated if it provides both
1885 enough inherent space and enough total space.
1886 Otherwise, we allocate a new slot, making sure that it has no less
1887 inherent space, and no less total space, then the previous slot. */
1890 /* No known place to spill from => no slot to reuse. */
1891 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1892 inherent_size == total_size ? 0 : -1);
1893 if (BYTES_BIG_ENDIAN)
1894 /* Cancel the big-endian correction done in assign_stack_local.
1895 Get the address of the beginning of the slot.
1896 This is so we can do a big-endian correction unconditionally
1898 adjust = inherent_size - total_size;
1900 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1902 /* Reuse a stack slot if possible. */
1903 else if (spill_stack_slot[from_reg] != 0
1904 && spill_stack_slot_width[from_reg] >= total_size
1905 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1907 x = spill_stack_slot[from_reg];
1908 /* Allocate a bigger slot. */
1911 /* Compute maximum size needed, both for inherent size
1912 and for total size. */
1913 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1915 if (spill_stack_slot[from_reg])
1917 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1919 mode = GET_MODE (spill_stack_slot[from_reg]);
1920 if (spill_stack_slot_width[from_reg] > total_size)
1921 total_size = spill_stack_slot_width[from_reg];
1923 /* Make a slot with that size. */
1924 x = assign_stack_local (mode, total_size,
1925 inherent_size == total_size ? 0 : -1);
1927 if (BYTES_BIG_ENDIAN)
1929 /* Cancel the big-endian correction done in assign_stack_local.
1930 Get the address of the beginning of the slot.
1931 This is so we can do a big-endian correction unconditionally
1933 adjust = GET_MODE_SIZE (mode) - total_size;
1935 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1938 plus_constant (XEXP (x, 0), adjust));
1940 spill_stack_slot[from_reg] = stack_slot;
1941 spill_stack_slot_width[from_reg] = total_size;
1944 /* On a big endian machine, the "address" of the slot
1945 is the address of the low part that fits its inherent mode. */
1946 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1947 adjust += (total_size - inherent_size);
1949 /* If we have any adjustment to make, or if the stack slot is the
1950 wrong mode, make a new stack slot. */
1951 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1953 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1954 plus_constant (XEXP (x, 0), adjust));
1956 /* If this was shared among registers, must ensure we never
1957 set it readonly since that can cause scheduling
1958 problems. Note we would only have in this adjustment
1959 case in any event, since the code above doesn't set it. */
1962 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1965 /* Save the stack slot for later. */
1966 reg_equiv_memory_loc[i] = x;
1970 /* Mark the slots in regs_ever_live for the hard regs
1971 used by pseudo-reg number REGNO. */
1974 mark_home_live (regno)
1977 register int i, lim;
1978 i = reg_renumber[regno];
1981 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1983 regs_ever_live[i++] = 1;
1986 /* This function handles the tracking of elimination offsets around branches.
1988 X is a piece of RTL being scanned.
1990 INSN is the insn that it came from, if any.
1992 INITIAL_P is non-zero if we are to set the offset to be the initial
1993 offset and zero if we are setting the offset of the label to be the
1997 set_label_offsets (x, insn, initial_p)
2002 enum rtx_code code = GET_CODE (x);
2005 struct elim_table *p;
2010 if (LABEL_REF_NONLOCAL_P (x))
2015 /* ... fall through ... */
2018 /* If we know nothing about this label, set the desired offsets. Note
2019 that this sets the offset at a label to be the offset before a label
2020 if we don't know anything about the label. This is not correct for
2021 the label after a BARRIER, but is the best guess we can make. If
2022 we guessed wrong, we will suppress an elimination that might have
2023 been possible had we been able to guess correctly. */
2025 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2027 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2028 offsets_at[CODE_LABEL_NUMBER (x)][i]
2029 = (initial_p ? reg_eliminate[i].initial_offset
2030 : reg_eliminate[i].offset);
2031 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2034 /* Otherwise, if this is the definition of a label and it is
2035 preceded by a BARRIER, set our offsets to the known offset of
2039 && (tem = prev_nonnote_insn (insn)) != 0
2040 && GET_CODE (tem) == BARRIER)
2041 set_offsets_for_label (insn);
2043 /* If neither of the above cases is true, compare each offset
2044 with those previously recorded and suppress any eliminations
2045 where the offsets disagree. */
2047 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2048 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2049 != (initial_p ? reg_eliminate[i].initial_offset
2050 : reg_eliminate[i].offset))
2051 reg_eliminate[i].can_eliminate = 0;
2056 set_label_offsets (PATTERN (insn), insn, initial_p);
2058 /* ... fall through ... */
2062 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2063 and hence must have all eliminations at their initial offsets. */
2064 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2065 if (REG_NOTE_KIND (tem) == REG_LABEL)
2066 set_label_offsets (XEXP (tem, 0), insn, 1);
2071 /* Each of the labels in the address vector must be at their initial
2072 offsets. We want the first field for ADDR_VEC and the second
2073 field for ADDR_DIFF_VEC. */
2075 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2076 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2081 /* We only care about setting PC. If the source is not RETURN,
2082 IF_THEN_ELSE, or a label, disable any eliminations not at
2083 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2084 isn't one of those possibilities. For branches to a label,
2085 call ourselves recursively.
2087 Note that this can disable elimination unnecessarily when we have
2088 a non-local goto since it will look like a non-constant jump to
2089 someplace in the current function. This isn't a significant
2090 problem since such jumps will normally be when all elimination
2091 pairs are back to their initial offsets. */
2093 if (SET_DEST (x) != pc_rtx)
2096 switch (GET_CODE (SET_SRC (x)))
2103 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2107 tem = XEXP (SET_SRC (x), 1);
2108 if (GET_CODE (tem) == LABEL_REF)
2109 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2110 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2113 tem = XEXP (SET_SRC (x), 2);
2114 if (GET_CODE (tem) == LABEL_REF)
2115 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2116 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2124 /* If we reach here, all eliminations must be at their initial
2125 offset because we are doing a jump to a variable address. */
2126 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2127 if (p->offset != p->initial_offset)
2128 p->can_eliminate = 0;
2136 /* Scan X and replace any eliminable registers (such as fp) with a
2137 replacement (such as sp), plus an offset.
2139 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2140 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2141 MEM, we are allowed to replace a sum of a register and the constant zero
2142 with the register, which we cannot do outside a MEM. In addition, we need
2143 to record the fact that a register is referenced outside a MEM.
2145 If INSN is an insn, it is the insn containing X. If we replace a REG
2146 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2147 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2148 the REG is being modified.
2150 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2151 That's used when we eliminate in expressions stored in notes.
2152 This means, do not set ref_outside_mem even if the reference
2155 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2156 replacements done assuming all offsets are at their initial values. If
2157 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2158 encounter, return the actual location so that find_reloads will do
2159 the proper thing. */
2162 eliminate_regs (x, mem_mode, insn)
2164 enum machine_mode mem_mode;
2167 enum rtx_code code = GET_CODE (x);
2168 struct elim_table *ep;
2175 if (! current_function_decl)
2194 /* This is only for the benefit of the debugging backends, which call
2195 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2196 removed after CSE. */
2197 new = eliminate_regs (XEXP (x, 0), 0, insn);
2198 if (GET_CODE (new) == MEM)
2199 return XEXP (new, 0);
2205 /* First handle the case where we encounter a bare register that
2206 is eliminable. Replace it with a PLUS. */
2207 if (regno < FIRST_PSEUDO_REGISTER)
2209 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2211 if (ep->from_rtx == x && ep->can_eliminate)
2212 return plus_constant (ep->to_rtx, ep->previous_offset);
2215 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2216 && reg_equiv_constant[regno]
2217 && ! CONSTANT_P (reg_equiv_constant[regno]))
2218 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2222 /* You might think handling MINUS in a manner similar to PLUS is a
2223 good idea. It is not. It has been tried multiple times and every
2224 time the change has had to have been reverted.
2226 Other parts of reload know a PLUS is special (gen_reload for example)
2227 and require special code to handle code a reloaded PLUS operand.
2229 Also consider backends where the flags register is clobbered by a
2230 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2231 lea instruction comes to mind). If we try to reload a MINUS, we
2232 may kill the flags register that was holding a useful value.
2234 So, please before trying to handle MINUS, consider reload as a
2235 whole instead of this little section as well as the backend issues. */
2237 /* If this is the sum of an eliminable register and a constant, rework
2239 if (GET_CODE (XEXP (x, 0)) == REG
2240 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2241 && CONSTANT_P (XEXP (x, 1)))
2243 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2245 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2247 /* The only time we want to replace a PLUS with a REG (this
2248 occurs when the constant operand of the PLUS is the negative
2249 of the offset) is when we are inside a MEM. We won't want
2250 to do so at other times because that would change the
2251 structure of the insn in a way that reload can't handle.
2252 We special-case the commonest situation in
2253 eliminate_regs_in_insn, so just replace a PLUS with a
2254 PLUS here, unless inside a MEM. */
2255 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2256 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2259 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2260 plus_constant (XEXP (x, 1),
2261 ep->previous_offset));
2264 /* If the register is not eliminable, we are done since the other
2265 operand is a constant. */
2269 /* If this is part of an address, we want to bring any constant to the
2270 outermost PLUS. We will do this by doing register replacement in
2271 our operands and seeing if a constant shows up in one of them.
2273 Note that there is no risk of modifying the structure of the insn,
2274 since we only get called for its operands, thus we are either
2275 modifying the address inside a MEM, or something like an address
2276 operand of a load-address insn. */
2279 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2280 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2282 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2284 /* If one side is a PLUS and the other side is a pseudo that
2285 didn't get a hard register but has a reg_equiv_constant,
2286 we must replace the constant here since it may no longer
2287 be in the position of any operand. */
2288 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2289 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2290 && reg_renumber[REGNO (new1)] < 0
2291 && reg_equiv_constant != 0
2292 && reg_equiv_constant[REGNO (new1)] != 0)
2293 new1 = reg_equiv_constant[REGNO (new1)];
2294 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2295 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2296 && reg_renumber[REGNO (new0)] < 0
2297 && reg_equiv_constant[REGNO (new0)] != 0)
2298 new0 = reg_equiv_constant[REGNO (new0)];
2300 new = form_sum (new0, new1);
2302 /* As above, if we are not inside a MEM we do not want to
2303 turn a PLUS into something else. We might try to do so here
2304 for an addition of 0 if we aren't optimizing. */
2305 if (! mem_mode && GET_CODE (new) != PLUS)
2306 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2314 /* If this is the product of an eliminable register and a
2315 constant, apply the distribute law and move the constant out
2316 so that we have (plus (mult ..) ..). This is needed in order
2317 to keep load-address insns valid. This case is pathological.
2318 We ignore the possibility of overflow here. */
2319 if (GET_CODE (XEXP (x, 0)) == REG
2320 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2321 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2322 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2324 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2327 /* Refs inside notes don't count for this purpose. */
2328 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2329 || GET_CODE (insn) == INSN_LIST)))
2330 ep->ref_outside_mem = 1;
2333 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2334 ep->previous_offset * INTVAL (XEXP (x, 1)));
2337 /* ... fall through ... */
2341 /* See comments before PLUS about handling MINUS. */
2343 case DIV: case UDIV:
2344 case MOD: case UMOD:
2345 case AND: case IOR: case XOR:
2346 case ROTATERT: case ROTATE:
2347 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2349 case GE: case GT: case GEU: case GTU:
2350 case LE: case LT: case LEU: case LTU:
2352 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2354 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2356 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2357 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2362 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2365 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2366 if (new != XEXP (x, 0))
2368 /* If this is a REG_DEAD note, it is not valid anymore.
2369 Using the eliminated version could result in creating a
2370 REG_DEAD note for the stack or frame pointer. */
2371 if (GET_MODE (x) == REG_DEAD)
2373 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2376 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2380 /* ... fall through ... */
2383 /* Now do eliminations in the rest of the chain. If this was
2384 an EXPR_LIST, this might result in allocating more memory than is
2385 strictly needed, but it simplifies the code. */
2388 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2389 if (new != XEXP (x, 1))
2390 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2398 case STRICT_LOW_PART:
2400 case SIGN_EXTEND: case ZERO_EXTEND:
2401 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2402 case FLOAT: case FIX:
2403 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2407 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2408 if (new != XEXP (x, 0))
2409 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2413 /* Similar to above processing, but preserve SUBREG_WORD.
2414 Convert (subreg (mem)) to (mem) if not paradoxical.
2415 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2416 pseudo didn't get a hard reg, we must replace this with the
2417 eliminated version of the memory location because push_reloads
2418 may do the replacement in certain circumstances. */
2419 if (GET_CODE (SUBREG_REG (x)) == REG
2420 && (GET_MODE_SIZE (GET_MODE (x))
2421 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2422 && reg_equiv_memory_loc != 0
2423 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2425 new = SUBREG_REG (x);
2428 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2430 if (new != XEXP (x, 0))
2432 int x_size = GET_MODE_SIZE (GET_MODE (x));
2433 int new_size = GET_MODE_SIZE (GET_MODE (new));
2435 if (GET_CODE (new) == MEM
2436 && ((x_size < new_size
2437 #ifdef WORD_REGISTER_OPERATIONS
2438 /* On these machines, combine can create rtl of the form
2439 (set (subreg:m1 (reg:m2 R) 0) ...)
2440 where m1 < m2, and expects something interesting to
2441 happen to the entire word. Moreover, it will use the
2442 (reg:m2 R) later, expecting all bits to be preserved.
2443 So if the number of words is the same, preserve the
2444 subreg so that push_reloads can see it. */
2445 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2448 || (x_size == new_size))
2451 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2452 enum machine_mode mode = GET_MODE (x);
2454 if (BYTES_BIG_ENDIAN)
2455 offset += (MIN (UNITS_PER_WORD,
2456 GET_MODE_SIZE (GET_MODE (new)))
2457 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2459 PUT_MODE (new, mode);
2460 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2464 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2470 /* This is only for the benefit of the debugging backends, which call
2471 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2472 removed after CSE. */
2473 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2474 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2476 /* Our only special processing is to pass the mode of the MEM to our
2477 recursive call and copy the flags. While we are here, handle this
2478 case more efficiently. */
2479 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2480 if (new != XEXP (x, 0))
2482 new = gen_rtx_MEM (GET_MODE (x), new);
2483 new->volatil = x->volatil;
2484 new->unchanging = x->unchanging;
2485 new->in_struct = x->in_struct;
2501 /* Process each of our operands recursively. If any have changed, make a
2503 fmt = GET_RTX_FORMAT (code);
2504 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2508 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2509 if (new != XEXP (x, i) && ! copied)
2511 rtx new_x = rtx_alloc (code);
2512 bcopy ((char *) x, (char *) new_x,
2513 (sizeof (*new_x) - sizeof (new_x->fld)
2514 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2520 else if (*fmt == 'E')
2523 for (j = 0; j < XVECLEN (x, i); j++)
2525 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2526 if (new != XVECEXP (x, i, j) && ! copied_vec)
2528 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2532 rtx new_x = rtx_alloc (code);
2533 bcopy ((char *) x, (char *) new_x,
2534 (sizeof (*new_x) - sizeof (new_x->fld)
2535 + (sizeof (new_x->fld[0])
2536 * GET_RTX_LENGTH (code))));
2540 XVEC (x, i) = new_v;
2543 XVECEXP (x, i, j) = new;
2551 /* Scan rtx X for modifications of elimination target registers. Update
2552 the table of eliminables to reflect the changed state. MEM_MODE is
2553 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2556 elimination_effects (x, mem_mode)
2558 enum machine_mode mem_mode;
2561 enum rtx_code code = GET_CODE (x);
2562 struct elim_table *ep;
2588 /* First handle the case where we encounter a bare register that
2589 is eliminable. Replace it with a PLUS. */
2590 if (regno < FIRST_PSEUDO_REGISTER)
2592 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2594 if (ep->from_rtx == x && ep->can_eliminate)
2597 ep->ref_outside_mem = 1;
2602 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2603 && reg_equiv_constant[regno]
2604 && ! CONSTANT_P (reg_equiv_constant[regno]))
2605 elimination_effects (reg_equiv_constant[regno], mem_mode);
2612 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2613 if (ep->to_rtx == XEXP (x, 0))
2615 int size = GET_MODE_SIZE (mem_mode);
2617 /* If more bytes than MEM_MODE are pushed, account for them. */
2618 #ifdef PUSH_ROUNDING
2619 if (ep->to_rtx == stack_pointer_rtx)
2620 size = PUSH_ROUNDING (size);
2622 if (code == PRE_DEC || code == POST_DEC)
2628 /* Fall through to generic unary operation case. */
2629 case STRICT_LOW_PART:
2631 case SIGN_EXTEND: case ZERO_EXTEND:
2632 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2633 case FLOAT: case FIX:
2634 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2638 elimination_effects (XEXP (x, 0), mem_mode);
2642 if (GET_CODE (SUBREG_REG (x)) == REG
2643 && (GET_MODE_SIZE (GET_MODE (x))
2644 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2645 && reg_equiv_memory_loc != 0
2646 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2649 elimination_effects (SUBREG_REG (x), mem_mode);
2653 /* If using a register that is the source of an eliminate we still
2654 think can be performed, note it cannot be performed since we don't
2655 know how this register is used. */
2656 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2657 if (ep->from_rtx == XEXP (x, 0))
2658 ep->can_eliminate = 0;
2660 elimination_effects (XEXP (x, 0), mem_mode);
2664 /* If clobbering a register that is the replacement register for an
2665 elimination we still think can be performed, note that it cannot
2666 be performed. Otherwise, we need not be concerned about it. */
2667 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2668 if (ep->to_rtx == XEXP (x, 0))
2669 ep->can_eliminate = 0;
2671 elimination_effects (XEXP (x, 0), mem_mode);
2675 /* Check for setting a register that we know about. */
2676 if (GET_CODE (SET_DEST (x)) == REG)
2678 /* See if this is setting the replacement register for an
2681 If DEST is the hard frame pointer, we do nothing because we
2682 assume that all assignments to the frame pointer are for
2683 non-local gotos and are being done at a time when they are valid
2684 and do not disturb anything else. Some machines want to
2685 eliminate a fake argument pointer (or even a fake frame pointer)
2686 with either the real frame or the stack pointer. Assignments to
2687 the hard frame pointer must not prevent this elimination. */
2689 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2691 if (ep->to_rtx == SET_DEST (x)
2692 && SET_DEST (x) != hard_frame_pointer_rtx)
2694 /* If it is being incremented, adjust the offset. Otherwise,
2695 this elimination can't be done. */
2696 rtx src = SET_SRC (x);
2698 if (GET_CODE (src) == PLUS
2699 && XEXP (src, 0) == SET_DEST (x)
2700 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2701 ep->offset -= INTVAL (XEXP (src, 1));
2703 ep->can_eliminate = 0;
2707 elimination_effects (SET_DEST (x), 0);
2708 elimination_effects (SET_SRC (x), 0);
2712 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2715 /* Our only special processing is to pass the mode of the MEM to our
2717 elimination_effects (XEXP (x, 0), GET_MODE (x));
2724 fmt = GET_RTX_FORMAT (code);
2725 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2728 elimination_effects (XEXP (x, i), mem_mode);
2729 else if (*fmt == 'E')
2730 for (j = 0; j < XVECLEN (x, i); j++)
2731 elimination_effects (XVECEXP (x, i, j), mem_mode);
2735 /* Descend through rtx X and verify that no references to eliminable registers
2736 remain. If any do remain, mark the involved register as not
2739 check_eliminable_occurrences (x)
2749 code = GET_CODE (x);
2751 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2753 struct elim_table *ep;
2755 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2756 if (ep->from_rtx == x && ep->can_eliminate)
2757 ep->can_eliminate = 0;
2761 fmt = GET_RTX_FORMAT (code);
2762 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2765 check_eliminable_occurrences (XEXP (x, i));
2766 else if (*fmt == 'E')
2769 for (j = 0; j < XVECLEN (x, i); j++)
2770 check_eliminable_occurrences (XVECEXP (x, i, j));
2775 /* Scan INSN and eliminate all eliminable registers in it.
2777 If REPLACE is nonzero, do the replacement destructively. Also
2778 delete the insn as dead it if it is setting an eliminable register.
2780 If REPLACE is zero, do all our allocations in reload_obstack.
2782 If no eliminations were done and this insn doesn't require any elimination
2783 processing (these are not identical conditions: it might be updating sp,
2784 but not referencing fp; this needs to be seen during reload_as_needed so
2785 that the offset between fp and sp can be taken into consideration), zero
2786 is returned. Otherwise, 1 is returned. */
2789 eliminate_regs_in_insn (insn, replace)
2793 int icode = recog_memoized (insn);
2794 rtx old_body = PATTERN (insn);
2795 int insn_is_asm = asm_noperands (old_body) >= 0;
2796 rtx old_set = single_set (insn);
2800 rtx substed_operand[MAX_RECOG_OPERANDS];
2801 rtx orig_operand[MAX_RECOG_OPERANDS];
2802 struct elim_table *ep;
2804 if (! insn_is_asm && icode < 0)
2806 if (GET_CODE (PATTERN (insn)) == USE
2807 || GET_CODE (PATTERN (insn)) == CLOBBER
2808 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2809 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2810 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2816 push_obstacks (&reload_obstack, &reload_obstack);
2818 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2819 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2821 /* Check for setting an eliminable register. */
2822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2823 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2825 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2826 /* If this is setting the frame pointer register to the
2827 hardware frame pointer register and this is an elimination
2828 that will be done (tested above), this insn is really
2829 adjusting the frame pointer downward to compensate for
2830 the adjustment done before a nonlocal goto. */
2831 if (ep->from == FRAME_POINTER_REGNUM
2832 && ep->to == HARD_FRAME_POINTER_REGNUM)
2834 rtx src = SET_SRC (old_set);
2835 int offset = 0, ok = 0;
2836 rtx prev_insn, prev_set;
2838 if (src == ep->to_rtx)
2840 else if (GET_CODE (src) == PLUS
2841 && GET_CODE (XEXP (src, 0)) == CONST_INT
2842 && XEXP (src, 1) == ep->to_rtx)
2843 offset = INTVAL (XEXP (src, 0)), ok = 1;
2844 else if (GET_CODE (src) == PLUS
2845 && GET_CODE (XEXP (src, 1)) == CONST_INT
2846 && XEXP (src, 0) == ep->to_rtx)
2847 offset = INTVAL (XEXP (src, 1)), ok = 1;
2848 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2849 && (prev_set = single_set (prev_insn)) != 0
2850 && rtx_equal_p (SET_DEST (prev_set), src))
2852 src = SET_SRC (prev_set);
2853 if (src == ep->to_rtx)
2855 else if (GET_CODE (src) == PLUS
2856 && GET_CODE (XEXP (src, 0)) == CONST_INT
2857 && XEXP (src, 1) == ep->to_rtx)
2858 offset = INTVAL (XEXP (src, 0)), ok = 1;
2859 else if (GET_CODE (src) == PLUS
2860 && GET_CODE (XEXP (src, 1)) == CONST_INT
2861 && XEXP (src, 0) == ep->to_rtx)
2862 offset = INTVAL (XEXP (src, 1)), ok = 1;
2870 = plus_constant (ep->to_rtx, offset - ep->offset);
2872 /* First see if this insn remains valid when we
2873 make the change. If not, keep the INSN_CODE
2874 the same and let reload fit it up. */
2875 validate_change (insn, &SET_SRC (old_set), src, 1);
2876 validate_change (insn, &SET_DEST (old_set),
2878 if (! apply_change_group ())
2880 SET_SRC (old_set) = src;
2881 SET_DEST (old_set) = ep->to_rtx;
2891 /* In this case this insn isn't serving a useful purpose. We
2892 will delete it in reload_as_needed once we know that this
2893 elimination is, in fact, being done.
2895 If REPLACE isn't set, we can't delete this insn, but needn't
2896 process it since it won't be used unless something changes. */
2899 delete_dead_insn (insn);
2906 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2907 in the insn is the negative of the offset in FROM. Substitute
2908 (set (reg) (reg to)) for the insn and change its code.
2910 We have to do this here, rather than in eliminate_regs, so that we can
2911 change the insn code. */
2913 if (GET_CODE (SET_SRC (old_set)) == PLUS
2914 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2915 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
2916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2918 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
2919 && ep->can_eliminate)
2921 /* We must stop at the first elimination that will be used.
2922 If this one would replace the PLUS with a REG, do it
2923 now. Otherwise, quit the loop and let eliminate_regs
2924 do its normal replacement. */
2925 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
2927 /* We assume here that we don't need a PARALLEL of
2928 any CLOBBERs for this assignment. There's not
2929 much we can do if we do need it. */
2930 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2933 INSN_CODE (insn) = -1;
2942 /* Determine the effects of this insn on elimination offsets. */
2943 elimination_effects (old_body, 0);
2945 /* Eliminate all eliminable registers occurring in operands that
2946 can be handled by reload. */
2947 extract_insn (insn);
2949 for (i = 0; i < recog_data.n_operands; i++)
2951 orig_operand[i] = recog_data.operand[i];
2952 substed_operand[i] = recog_data.operand[i];
2954 /* For an asm statement, every operand is eliminable. */
2955 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2957 /* Check for setting a register that we know about. */
2958 if (recog_data.operand_type[i] != OP_IN
2959 && GET_CODE (orig_operand[i]) == REG)
2961 /* If we are assigning to a register that can be eliminated, it
2962 must be as part of a PARALLEL, since the code above handles
2963 single SETs. We must indicate that we can no longer
2964 eliminate this reg. */
2965 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2967 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
2968 ep->can_eliminate = 0;
2971 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
2972 replace ? insn : NULL_RTX);
2973 if (substed_operand[i] != orig_operand[i])
2974 val = any_changes = 1;
2975 /* Terminate the search in check_eliminable_occurrences at
2977 *recog_data.operand_loc[i] = 0;
2979 /* If an output operand changed from a REG to a MEM and INSN is an
2980 insn, write a CLOBBER insn. */
2981 if (recog_data.operand_type[i] != OP_IN
2982 && GET_CODE (orig_operand[i]) == REG
2983 && GET_CODE (substed_operand[i]) == MEM
2985 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
2990 for (i = 0; i < recog_data.n_dups; i++)
2991 *recog_data.dup_loc[i]
2992 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
2994 /* If any eliminable remain, they aren't eliminable anymore. */
2995 check_eliminable_occurrences (old_body);
2997 /* Substitute the operands; the new values are in the substed_operand
2999 for (i = 0; i < recog_data.n_operands; i++)
3000 *recog_data.operand_loc[i] = substed_operand[i];
3001 for (i = 0; i < recog_data.n_dups; i++)
3002 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3004 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3005 re-recognize the insn. We do this in case we had a simple addition
3006 but now can do this as a load-address. This saves an insn in this
3008 If re-recognition fails, the old insn code number will still be used,
3009 and some register operands may have changed into PLUS expressions.
3010 These will be handled by find_reloads by loading them into a register
3015 /* If we aren't replacing things permanently and we changed something,
3016 make another copy to ensure that all the RTL is new. Otherwise
3017 things can go wrong if find_reload swaps commutative operands
3018 and one is inside RTL that has been copied while the other is not. */
3019 new_body = old_body;
3022 new_body = copy_insn (old_body);
3023 if (REG_NOTES (insn))
3024 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3026 PATTERN (insn) = new_body;
3028 /* If we had a move insn but now we don't, rerecognize it. This will
3029 cause spurious re-recognition if the old move had a PARALLEL since
3030 the new one still will, but we can't call single_set without
3031 having put NEW_BODY into the insn and the re-recognition won't
3032 hurt in this rare case. */
3033 /* ??? Why this huge if statement - why don't we just rerecognize the
3037 && ((GET_CODE (SET_SRC (old_set)) == REG
3038 && (GET_CODE (new_body) != SET
3039 || GET_CODE (SET_SRC (new_body)) != REG))
3040 /* If this was a load from or store to memory, compare
3041 the MEM in recog_data.operand to the one in the insn.
3042 If they are not equal, then rerecognize the insn. */
3044 && ((GET_CODE (SET_SRC (old_set)) == MEM
3045 && SET_SRC (old_set) != recog_data.operand[1])
3046 || (GET_CODE (SET_DEST (old_set)) == MEM
3047 && SET_DEST (old_set) != recog_data.operand[0])))
3048 /* If this was an add insn before, rerecognize. */
3049 || GET_CODE (SET_SRC (old_set)) == PLUS))
3051 int new_icode = recog (PATTERN (insn), insn, 0);
3053 INSN_CODE (insn) = icode;
3057 /* Restore the old body. If there were any changes to it, we made a copy
3058 of it while the changes were still in place, so we'll correctly return
3059 a modified insn below. */
3062 /* Restore the old body. */
3063 for (i = 0; i < recog_data.n_operands; i++)
3064 *recog_data.operand_loc[i] = orig_operand[i];
3065 for (i = 0; i < recog_data.n_dups; i++)
3066 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3069 /* Update all elimination pairs to reflect the status after the current
3070 insn. The changes we make were determined by the earlier call to
3071 elimination_effects.
3073 We also detect a cases where register elimination cannot be done,
3074 namely, if a register would be both changed and referenced outside a MEM
3075 in the resulting insn since such an insn is often undefined and, even if
3076 not, we cannot know what meaning will be given to it. Note that it is
3077 valid to have a register used in an address in an insn that changes it
3078 (presumably with a pre- or post-increment or decrement).
3080 If anything changes, return nonzero. */
3082 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3084 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3085 ep->can_eliminate = 0;
3087 ep->ref_outside_mem = 0;
3089 if (ep->previous_offset != ep->offset)
3094 /* If we changed something, perform elimination in REG_NOTES. This is
3095 needed even when REPLACE is zero because a REG_DEAD note might refer
3096 to a register that we eliminate and could cause a different number
3097 of spill registers to be needed in the final reload pass than in
3099 if (val && REG_NOTES (insn) != 0)
3100 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3108 /* Loop through all elimination pairs.
3109 Recalculate the number not at initial offset.
3111 Compute the maximum offset (minimum offset if the stack does not
3112 grow downward) for each elimination pair. */
3115 update_eliminable_offsets ()
3117 struct elim_table *ep;
3119 num_not_at_initial_offset = 0;
3120 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3122 ep->previous_offset = ep->offset;
3123 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3124 num_not_at_initial_offset++;
3128 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3129 replacement we currently believe is valid, mark it as not eliminable if X
3130 modifies DEST in any way other than by adding a constant integer to it.
3132 If DEST is the frame pointer, we do nothing because we assume that
3133 all assignments to the hard frame pointer are nonlocal gotos and are being
3134 done at a time when they are valid and do not disturb anything else.
3135 Some machines want to eliminate a fake argument pointer with either the
3136 frame or stack pointer. Assignments to the hard frame pointer must not
3137 prevent this elimination.
3139 Called via note_stores from reload before starting its passes to scan
3140 the insns of the function. */
3143 mark_not_eliminable (dest, x, data)
3146 void *data ATTRIBUTE_UNUSED;
3148 register unsigned int i;
3150 /* A SUBREG of a hard register here is just changing its mode. We should
3151 not see a SUBREG of an eliminable hard register, but check just in
3153 if (GET_CODE (dest) == SUBREG)
3154 dest = SUBREG_REG (dest);
3156 if (dest == hard_frame_pointer_rtx)
3159 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3160 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3161 && (GET_CODE (x) != SET
3162 || GET_CODE (SET_SRC (x)) != PLUS
3163 || XEXP (SET_SRC (x), 0) != dest
3164 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3166 reg_eliminate[i].can_eliminate_previous
3167 = reg_eliminate[i].can_eliminate = 0;
3172 /* Verify that the initial elimination offsets did not change since the
3173 last call to set_initial_elim_offsets. This is used to catch cases
3174 where something illegal happened during reload_as_needed that could
3175 cause incorrect code to be generated if we did not check for it. */
3177 verify_initial_elim_offsets ()
3181 #ifdef ELIMINABLE_REGS
3182 struct elim_table *ep;
3184 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3186 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3187 if (t != ep->initial_offset)
3191 INITIAL_FRAME_POINTER_OFFSET (t);
3192 if (t != reg_eliminate[0].initial_offset)
3197 /* Reset all offsets on eliminable registers to their initial values. */
3199 set_initial_elim_offsets ()
3201 struct elim_table *ep = reg_eliminate;
3203 #ifdef ELIMINABLE_REGS
3204 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3206 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3207 ep->previous_offset = ep->offset = ep->initial_offset;
3210 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3211 ep->previous_offset = ep->offset = ep->initial_offset;
3214 num_not_at_initial_offset = 0;
3217 /* Initialize the known label offsets.
3218 Set a known offset for each forced label to be at the initial offset
3219 of each elimination. We do this because we assume that all
3220 computed jumps occur from a location where each elimination is
3221 at its initial offset.
3222 For all other labels, show that we don't know the offsets. */
3225 set_initial_label_offsets ()
3228 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3230 for (x = forced_labels; x; x = XEXP (x, 1))
3232 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3235 /* Set all elimination offsets to the known values for the code label given
3238 set_offsets_for_label (insn)
3242 int label_nr = CODE_LABEL_NUMBER (insn);
3243 struct elim_table *ep;
3245 num_not_at_initial_offset = 0;
3246 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3248 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3249 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3250 num_not_at_initial_offset++;
3254 /* See if anything that happened changes which eliminations are valid.
3255 For example, on the Sparc, whether or not the frame pointer can
3256 be eliminated can depend on what registers have been used. We need
3257 not check some conditions again (such as flag_omit_frame_pointer)
3258 since they can't have changed. */
3261 update_eliminables (pset)
3264 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3265 int previous_frame_pointer_needed = frame_pointer_needed;
3267 struct elim_table *ep;
3269 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3270 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3271 #ifdef ELIMINABLE_REGS
3272 || ! CAN_ELIMINATE (ep->from, ep->to)
3275 ep->can_eliminate = 0;
3277 /* Look for the case where we have discovered that we can't replace
3278 register A with register B and that means that we will now be
3279 trying to replace register A with register C. This means we can
3280 no longer replace register C with register B and we need to disable
3281 such an elimination, if it exists. This occurs often with A == ap,
3282 B == sp, and C == fp. */
3284 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3286 struct elim_table *op;
3287 register int new_to = -1;
3289 if (! ep->can_eliminate && ep->can_eliminate_previous)
3291 /* Find the current elimination for ep->from, if there is a
3293 for (op = reg_eliminate;
3294 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3295 if (op->from == ep->from && op->can_eliminate)
3301 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3303 for (op = reg_eliminate;
3304 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3305 if (op->from == new_to && op->to == ep->to)
3306 op->can_eliminate = 0;
3310 /* See if any registers that we thought we could eliminate the previous
3311 time are no longer eliminable. If so, something has changed and we
3312 must spill the register. Also, recompute the number of eliminable
3313 registers and see if the frame pointer is needed; it is if there is
3314 no elimination of the frame pointer that we can perform. */
3316 frame_pointer_needed = 1;
3317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3319 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3320 && ep->to != HARD_FRAME_POINTER_REGNUM)
3321 frame_pointer_needed = 0;
3323 if (! ep->can_eliminate && ep->can_eliminate_previous)
3325 ep->can_eliminate_previous = 0;
3326 SET_HARD_REG_BIT (*pset, ep->from);
3331 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3332 /* If we didn't need a frame pointer last time, but we do now, spill
3333 the hard frame pointer. */
3334 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3335 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3339 /* Initialize the table of registers to eliminate. */
3343 struct elim_table *ep;
3344 #ifdef ELIMINABLE_REGS
3345 struct elim_table_1 *ep1;
3349 reg_eliminate = (struct elim_table *)
3350 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3352 /* Does this function require a frame pointer? */
3354 frame_pointer_needed = (! flag_omit_frame_pointer
3355 #ifdef EXIT_IGNORE_STACK
3356 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3357 and restore sp for alloca. So we can't eliminate
3358 the frame pointer in that case. At some point,
3359 we should improve this by emitting the
3360 sp-adjusting insns for this case. */
3361 || (current_function_calls_alloca
3362 && EXIT_IGNORE_STACK)
3364 || FRAME_POINTER_REQUIRED);
3368 #ifdef ELIMINABLE_REGS
3369 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3370 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3372 ep->from = ep1->from;
3374 ep->can_eliminate = ep->can_eliminate_previous
3375 = (CAN_ELIMINATE (ep->from, ep->to)
3376 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3379 reg_eliminate[0].from = reg_eliminate_1[0].from;
3380 reg_eliminate[0].to = reg_eliminate_1[0].to;
3381 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3382 = ! frame_pointer_needed;
3385 /* Count the number of eliminable registers and build the FROM and TO
3386 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3387 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3388 We depend on this. */
3389 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3391 num_eliminable += ep->can_eliminate;
3392 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3393 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3397 /* Kick all pseudos out of hard register REGNO.
3398 If DUMPFILE is nonzero, log actions taken on that file.
3400 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3401 because we found we can't eliminate some register. In the case, no pseudos
3402 are allowed to be in the register, even if they are only in a block that
3403 doesn't require spill registers, unlike the case when we are spilling this
3404 hard reg to produce another spill register.
3406 Return nonzero if any pseudos needed to be kicked out. */
3409 spill_hard_reg (regno, dumpfile, cant_eliminate)
3411 FILE *dumpfile ATTRIBUTE_UNUSED;
3418 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3419 regs_ever_live[regno] = 1;
3422 /* Spill every pseudo reg that was allocated to this reg
3423 or to something that overlaps this reg. */
3425 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3426 if (reg_renumber[i] >= 0
3427 && reg_renumber[i] <= regno
3429 + HARD_REGNO_NREGS (reg_renumber[i],
3430 PSEUDO_REGNO_MODE (i))
3432 SET_REGNO_REG_SET (&spilled_pseudos, i);
3435 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3436 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3438 ior_hard_reg_set (set1, set2)
3439 HARD_REG_SET *set1, *set2;
3441 IOR_HARD_REG_SET (*set1, *set2);
3444 /* After find_reload_regs has been run for all insn that need reloads,
3445 and/or spill_hard_regs was called, this function is used to actually
3446 spill pseudo registers and try to reallocate them. It also sets up the
3447 spill_regs array for use by choose_reload_regs. */
3450 finish_spills (global, dumpfile)
3454 struct insn_chain *chain;
3455 int something_changed = 0;
3458 /* Build the spill_regs array for the function. */
3459 /* If there are some registers still to eliminate and one of the spill regs
3460 wasn't ever used before, additional stack space may have to be
3461 allocated to store this register. Thus, we may have changed the offset
3462 between the stack and frame pointers, so mark that something has changed.
3464 One might think that we need only set VAL to 1 if this is a call-used
3465 register. However, the set of registers that must be saved by the
3466 prologue is not identical to the call-used set. For example, the
3467 register used by the call insn for the return PC is a call-used register,
3468 but must be saved by the prologue. */
3471 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3472 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3474 spill_reg_order[i] = n_spills;
3475 spill_regs[n_spills++] = i;
3476 if (num_eliminable && ! regs_ever_live[i])
3477 something_changed = 1;
3478 regs_ever_live[i] = 1;
3481 spill_reg_order[i] = -1;
3483 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3484 if (REGNO_REG_SET_P (&spilled_pseudos, i))
3486 /* Record the current hard register the pseudo is allocated to in
3487 pseudo_previous_regs so we avoid reallocating it to the same
3488 hard reg in a later pass. */
3489 if (reg_renumber[i] < 0)
3491 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3492 /* Mark it as no longer having a hard register home. */
3493 reg_renumber[i] = -1;
3494 /* We will need to scan everything again. */
3495 something_changed = 1;
3498 /* Retry global register allocation if possible. */
3501 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3502 /* For every insn that needs reloads, set the registers used as spill
3503 regs in pseudo_forbidden_regs for every pseudo live across the
3505 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3507 EXECUTE_IF_SET_IN_REG_SET
3508 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3510 ior_hard_reg_set (pseudo_forbidden_regs + i,
3511 &chain->used_spill_regs);
3513 EXECUTE_IF_SET_IN_REG_SET
3514 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3516 ior_hard_reg_set (pseudo_forbidden_regs + i,
3517 &chain->used_spill_regs);
3521 /* Retry allocating the spilled pseudos. For each reg, merge the
3522 various reg sets that indicate which hard regs can't be used,
3523 and call retry_global_alloc.
3524 We change spill_pseudos here to only contain pseudos that did not
3525 get a new hard register. */
3526 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3527 if (reg_old_renumber[i] != reg_renumber[i])
3529 HARD_REG_SET forbidden;
3530 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3531 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3532 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3533 retry_global_alloc (i, forbidden);
3534 if (reg_renumber[i] >= 0)
3535 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3539 /* Fix up the register information in the insn chain.
3540 This involves deleting those of the spilled pseudos which did not get
3541 a new hard register home from the live_{before,after} sets. */
3542 for (chain = reload_insn_chain; chain; chain = chain->next)
3544 HARD_REG_SET used_by_pseudos;
3545 HARD_REG_SET used_by_pseudos2;
3547 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3548 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3550 /* Mark any unallocated hard regs as available for spills. That
3551 makes inheritance work somewhat better. */
3552 if (chain->need_reload)
3554 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3555 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3556 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3558 /* Save the old value for the sanity test below. */
3559 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3561 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3562 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3563 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3564 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3566 /* Make sure we only enlarge the set. */
3567 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3573 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3574 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3576 int regno = reg_renumber[i];
3577 if (reg_old_renumber[i] == regno)
3580 alter_reg (i, reg_old_renumber[i]);
3581 reg_old_renumber[i] = regno;
3585 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3587 fprintf (dumpfile, " Register %d now in %d.\n\n",
3588 i, reg_renumber[i]);
3592 return something_changed;
3595 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3596 Also mark any hard registers used to store user variables as
3597 forbidden from being used for spill registers. */
3600 scan_paradoxical_subregs (x)
3604 register const char *fmt;
3605 register enum rtx_code code = GET_CODE (x);
3611 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3612 && REG_USERVAR_P (x))
3613 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3629 if (GET_CODE (SUBREG_REG (x)) == REG
3630 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3631 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3632 = GET_MODE_SIZE (GET_MODE (x));
3639 fmt = GET_RTX_FORMAT (code);
3640 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3643 scan_paradoxical_subregs (XEXP (x, i));
3644 else if (fmt[i] == 'E')
3647 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3648 scan_paradoxical_subregs (XVECEXP (x, i, j));
3653 /* Reload pseudo-registers into hard regs around each insn as needed.
3654 Additional register load insns are output before the insn that needs it
3655 and perhaps store insns after insns that modify the reloaded pseudo reg.
3657 reg_last_reload_reg and reg_reloaded_contents keep track of
3658 which registers are already available in reload registers.
3659 We update these for the reloads that we perform,
3660 as the insns are scanned. */
3663 reload_as_needed (live_known)
3666 struct insn_chain *chain;
3667 #if defined (AUTO_INC_DEC)
3672 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3673 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3674 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3675 reg_has_output_reload = (char *) xmalloc (max_regno);
3676 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3678 set_initial_elim_offsets ();
3680 for (chain = reload_insn_chain; chain; chain = chain->next)
3683 rtx insn = chain->insn;
3684 rtx old_next = NEXT_INSN (insn);
3686 /* If we pass a label, copy the offsets from the label information
3687 into the current offsets of each elimination. */
3688 if (GET_CODE (insn) == CODE_LABEL)
3689 set_offsets_for_label (insn);
3691 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3693 rtx oldpat = PATTERN (insn);
3695 /* If this is a USE and CLOBBER of a MEM, ensure that any
3696 references to eliminable registers have been removed. */
3698 if ((GET_CODE (PATTERN (insn)) == USE
3699 || GET_CODE (PATTERN (insn)) == CLOBBER)
3700 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3701 XEXP (XEXP (PATTERN (insn), 0), 0)
3702 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3703 GET_MODE (XEXP (PATTERN (insn), 0)),
3706 /* If we need to do register elimination processing, do so.
3707 This might delete the insn, in which case we are done. */
3708 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3710 eliminate_regs_in_insn (insn, 1);
3711 if (GET_CODE (insn) == NOTE)
3713 update_eliminable_offsets ();
3718 /* If need_elim is nonzero but need_reload is zero, one might think
3719 that we could simply set n_reloads to 0. However, find_reloads
3720 could have done some manipulation of the insn (such as swapping
3721 commutative operands), and these manipulations are lost during
3722 the first pass for every insn that needs register elimination.
3723 So the actions of find_reloads must be redone here. */
3725 if (! chain->need_elim && ! chain->need_reload
3726 && ! chain->need_operand_change)
3728 /* First find the pseudo regs that must be reloaded for this insn.
3729 This info is returned in the tables reload_... (see reload.h).
3730 Also modify the body of INSN by substituting RELOAD
3731 rtx's for those pseudo regs. */
3734 bzero (reg_has_output_reload, max_regno);
3735 CLEAR_HARD_REG_SET (reg_is_output_reload);
3737 find_reloads (insn, 1, spill_indirect_levels, live_known,
3741 if (num_eliminable && chain->need_elim)
3742 update_eliminable_offsets ();
3746 rtx next = NEXT_INSN (insn);
3749 prev = PREV_INSN (insn);
3751 /* Now compute which reload regs to reload them into. Perhaps
3752 reusing reload regs from previous insns, or else output
3753 load insns to reload them. Maybe output store insns too.
3754 Record the choices of reload reg in reload_reg_rtx. */
3755 choose_reload_regs (chain);
3757 /* Merge any reloads that we didn't combine for fear of
3758 increasing the number of spill registers needed but now
3759 discover can be safely merged. */
3760 if (SMALL_REGISTER_CLASSES)
3761 merge_assigned_reloads (insn);
3763 /* Generate the insns to reload operands into or out of
3764 their reload regs. */
3765 emit_reload_insns (chain);
3767 /* Substitute the chosen reload regs from reload_reg_rtx
3768 into the insn's body (or perhaps into the bodies of other
3769 load and store insn that we just made for reloading
3770 and that we moved the structure into). */
3773 /* If this was an ASM, make sure that all the reload insns
3774 we have generated are valid. If not, give an error
3777 if (asm_noperands (PATTERN (insn)) >= 0)
3778 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3779 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3780 && (recog_memoized (p) < 0
3781 || (extract_insn (p), ! constrain_operands (1))))
3783 error_for_asm (insn,
3784 "`asm' operand requires impossible reload");
3786 NOTE_SOURCE_FILE (p) = 0;
3787 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3790 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3791 is no longer validly lying around to save a future reload.
3792 Note that this does not detect pseudos that were reloaded
3793 for this insn in order to be stored in
3794 (obeying register constraints). That is correct; such reload
3795 registers ARE still valid. */
3796 note_stores (oldpat, forget_old_reloads_1, NULL);
3798 /* There may have been CLOBBER insns placed after INSN. So scan
3799 between INSN and NEXT and use them to forget old reloads. */
3800 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3801 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3802 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3805 /* Likewise for regs altered by auto-increment in this insn.
3806 REG_INC notes have been changed by reloading:
3807 find_reloads_address_1 records substitutions for them,
3808 which have been performed by subst_reloads above. */
3809 for (i = n_reloads - 1; i >= 0; i--)
3811 rtx in_reg = rld[i].in_reg;
3814 enum rtx_code code = GET_CODE (in_reg);
3815 /* PRE_INC / PRE_DEC will have the reload register ending up
3816 with the same value as the stack slot, but that doesn't
3817 hold true for POST_INC / POST_DEC. Either we have to
3818 convert the memory access to a true POST_INC / POST_DEC,
3819 or we can't use the reload register for inheritance. */
3820 if ((code == POST_INC || code == POST_DEC)
3821 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3822 REGNO (rld[i].reg_rtx))
3823 /* Make sure it is the inc/dec pseudo, and not
3824 some other (e.g. output operand) pseudo. */
3825 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3826 == REGNO (XEXP (in_reg, 0))))
3829 rtx reload_reg = rld[i].reg_rtx;
3830 enum machine_mode mode = GET_MODE (reload_reg);
3834 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3836 /* We really want to ignore REG_INC notes here, so
3837 use PATTERN (p) as argument to reg_set_p . */
3838 if (reg_set_p (reload_reg, PATTERN (p)))
3840 n = count_occurrences (PATTERN (p), reload_reg);
3845 n = validate_replace_rtx (reload_reg,
3846 gen_rtx (code, mode,
3850 /* We must also verify that the constraints
3851 are met after the replacement. */
3854 n = constrain_operands (1);
3858 /* If the constraints were not met, then
3859 undo the replacement. */
3862 validate_replace_rtx (gen_rtx (code, mode,
3874 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3876 /* Mark this as having an output reload so that the
3877 REG_INC processing code below won't invalidate
3878 the reload for inheritance. */
3879 SET_HARD_REG_BIT (reg_is_output_reload,
3880 REGNO (reload_reg));
3881 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3884 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3887 else if ((code == PRE_INC || code == PRE_DEC)
3888 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3889 REGNO (rld[i].reg_rtx))
3890 /* Make sure it is the inc/dec pseudo, and not
3891 some other (e.g. output operand) pseudo. */
3892 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3893 == REGNO (XEXP (in_reg, 0))))
3895 SET_HARD_REG_BIT (reg_is_output_reload,
3896 REGNO (rld[i].reg_rtx));
3897 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3901 /* If a pseudo that got a hard register is auto-incremented,
3902 we must purge records of copying it into pseudos without
3904 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3905 if (REG_NOTE_KIND (x) == REG_INC)
3907 /* See if this pseudo reg was reloaded in this insn.
3908 If so, its last-reload info is still valid
3909 because it is based on this insn's reload. */
3910 for (i = 0; i < n_reloads; i++)
3911 if (rld[i].out == XEXP (x, 0))
3915 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3919 /* A reload reg's contents are unknown after a label. */
3920 if (GET_CODE (insn) == CODE_LABEL)
3921 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3923 /* Don't assume a reload reg is still good after a call insn
3924 if it is a call-used reg. */
3925 else if (GET_CODE (insn) == CALL_INSN)
3926 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3930 free (reg_last_reload_reg);
3931 free (reg_has_output_reload);
3934 /* Discard all record of any value reloaded from X,
3935 or reloaded in X from someplace else;
3936 unless X is an output reload reg of the current insn.
3938 X may be a hard reg (the reload reg)
3939 or it may be a pseudo reg that was reloaded from. */
3942 forget_old_reloads_1 (x, ignored, data)
3944 rtx ignored ATTRIBUTE_UNUSED;
3945 void *data ATTRIBUTE_UNUSED;
3951 /* note_stores does give us subregs of hard regs. */
3952 while (GET_CODE (x) == SUBREG)
3954 offset += SUBREG_WORD (x);
3958 if (GET_CODE (x) != REG)
3961 regno = REGNO (x) + offset;
3963 if (regno >= FIRST_PSEUDO_REGISTER)
3968 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3969 /* Storing into a spilled-reg invalidates its contents.
3970 This can happen if a block-local pseudo is allocated to that reg
3971 and it wasn't spilled because this block's total need is 0.
3972 Then some insn might have an optional reload and use this reg. */
3973 for (i = 0; i < nr; i++)
3974 /* But don't do this if the reg actually serves as an output
3975 reload reg in the current instruction. */
3977 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
3978 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
3981 /* Since value of X has changed,
3982 forget any value previously copied from it. */
3985 /* But don't forget a copy if this is the output reload
3986 that establishes the copy's validity. */
3987 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3988 reg_last_reload_reg[regno + nr] = 0;
3991 /* The following HARD_REG_SETs indicate when each hard register is
3992 used for a reload of various parts of the current insn. */
3994 /* If reg is unavailable for all reloads. */
3995 static HARD_REG_SET reload_reg_unavailable;
3996 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3997 static HARD_REG_SET reload_reg_used;
3998 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
3999 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4000 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4001 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4002 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4003 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4004 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4005 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4006 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4007 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4008 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4009 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4010 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4011 static HARD_REG_SET reload_reg_used_in_op_addr;
4012 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4013 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4014 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4015 static HARD_REG_SET reload_reg_used_in_insn;
4016 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4017 static HARD_REG_SET reload_reg_used_in_other_addr;
4019 /* If reg is in use as a reload reg for any sort of reload. */
4020 static HARD_REG_SET reload_reg_used_at_all;
4022 /* If reg is use as an inherited reload. We just mark the first register
4024 static HARD_REG_SET reload_reg_used_for_inherit;
4026 /* Records which hard regs are used in any way, either as explicit use or
4027 by being allocated to a pseudo during any point of the current insn. */
4028 static HARD_REG_SET reg_used_in_insn;
4030 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4031 TYPE. MODE is used to indicate how many consecutive regs are
4035 mark_reload_reg_in_use (regno, opnum, type, mode)
4038 enum reload_type type;
4039 enum machine_mode mode;
4041 int nregs = HARD_REGNO_NREGS (regno, mode);
4044 for (i = regno; i < nregs + regno; i++)
4049 SET_HARD_REG_BIT (reload_reg_used, i);
4052 case RELOAD_FOR_INPUT_ADDRESS:
4053 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4056 case RELOAD_FOR_INPADDR_ADDRESS:
4057 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4060 case RELOAD_FOR_OUTPUT_ADDRESS:
4061 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4064 case RELOAD_FOR_OUTADDR_ADDRESS:
4065 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4068 case RELOAD_FOR_OPERAND_ADDRESS:
4069 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4072 case RELOAD_FOR_OPADDR_ADDR:
4073 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4076 case RELOAD_FOR_OTHER_ADDRESS:
4077 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4080 case RELOAD_FOR_INPUT:
4081 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4084 case RELOAD_FOR_OUTPUT:
4085 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4088 case RELOAD_FOR_INSN:
4089 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4093 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4097 /* Similarly, but show REGNO is no longer in use for a reload. */
4100 clear_reload_reg_in_use (regno, opnum, type, mode)
4103 enum reload_type type;
4104 enum machine_mode mode;
4106 int nregs = HARD_REGNO_NREGS (regno, mode);
4107 int start_regno, end_regno;
4109 /* A complication is that for some reload types, inheritance might
4110 allow multiple reloads of the same types to share a reload register.
4111 We set check_opnum if we have to check only reloads with the same
4112 operand number, and check_any if we have to check all reloads. */
4113 int check_opnum = 0;
4115 HARD_REG_SET *used_in_set;
4120 used_in_set = &reload_reg_used;
4123 case RELOAD_FOR_INPUT_ADDRESS:
4124 used_in_set = &reload_reg_used_in_input_addr[opnum];
4127 case RELOAD_FOR_INPADDR_ADDRESS:
4129 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4132 case RELOAD_FOR_OUTPUT_ADDRESS:
4133 used_in_set = &reload_reg_used_in_output_addr[opnum];
4136 case RELOAD_FOR_OUTADDR_ADDRESS:
4138 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4141 case RELOAD_FOR_OPERAND_ADDRESS:
4142 used_in_set = &reload_reg_used_in_op_addr;
4145 case RELOAD_FOR_OPADDR_ADDR:
4147 used_in_set = &reload_reg_used_in_op_addr_reload;
4150 case RELOAD_FOR_OTHER_ADDRESS:
4151 used_in_set = &reload_reg_used_in_other_addr;
4155 case RELOAD_FOR_INPUT:
4156 used_in_set = &reload_reg_used_in_input[opnum];
4159 case RELOAD_FOR_OUTPUT:
4160 used_in_set = &reload_reg_used_in_output[opnum];
4163 case RELOAD_FOR_INSN:
4164 used_in_set = &reload_reg_used_in_insn;
4169 /* We resolve conflicts with remaining reloads of the same type by
4170 excluding the intervals of of reload registers by them from the
4171 interval of freed reload registers. Since we only keep track of
4172 one set of interval bounds, we might have to exclude somewhat
4173 more then what would be necessary if we used a HARD_REG_SET here.
4174 But this should only happen very infrequently, so there should
4175 be no reason to worry about it. */
4177 start_regno = regno;
4178 end_regno = regno + nregs;
4179 if (check_opnum || check_any)
4181 for (i = n_reloads - 1; i >= 0; i--)
4183 if (rld[i].when_needed == type
4184 && (check_any || rld[i].opnum == opnum)
4187 int conflict_start = true_regnum (rld[i].reg_rtx);
4190 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4192 /* If there is an overlap with the first to-be-freed register,
4193 adjust the interval start. */
4194 if (conflict_start <= start_regno && conflict_end > start_regno)
4195 start_regno = conflict_end;
4196 /* Otherwise, if there is a conflict with one of the other
4197 to-be-freed registers, adjust the interval end. */
4198 if (conflict_start > start_regno && conflict_start < end_regno)
4199 end_regno = conflict_start;
4203 for (i = start_regno; i < end_regno; i++)
4204 CLEAR_HARD_REG_BIT (*used_in_set, i);
4207 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4208 specified by OPNUM and TYPE. */
4211 reload_reg_free_p (regno, opnum, type)
4214 enum reload_type type;
4218 /* In use for a RELOAD_OTHER means it's not available for anything. */
4219 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4220 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4226 /* In use for anything means we can't use it for RELOAD_OTHER. */
4227 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4228 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4229 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4232 for (i = 0; i < reload_n_operands; i++)
4233 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4234 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4235 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4236 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4237 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4238 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4243 case RELOAD_FOR_INPUT:
4244 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4245 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4248 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4251 /* If it is used for some other input, can't use it. */
4252 for (i = 0; i < reload_n_operands; i++)
4253 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4256 /* If it is used in a later operand's address, can't use it. */
4257 for (i = opnum + 1; i < reload_n_operands; i++)
4258 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4259 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4264 case RELOAD_FOR_INPUT_ADDRESS:
4265 /* Can't use a register if it is used for an input address for this
4266 operand or used as an input in an earlier one. */
4267 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4268 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4271 for (i = 0; i < opnum; i++)
4272 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4277 case RELOAD_FOR_INPADDR_ADDRESS:
4278 /* Can't use a register if it is used for an input address
4279 for this operand or used as an input in an earlier
4281 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4284 for (i = 0; i < opnum; i++)
4285 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4290 case RELOAD_FOR_OUTPUT_ADDRESS:
4291 /* Can't use a register if it is used for an output address for this
4292 operand or used as an output in this or a later operand. */
4293 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4296 for (i = opnum; i < reload_n_operands; i++)
4297 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4302 case RELOAD_FOR_OUTADDR_ADDRESS:
4303 /* Can't use a register if it is used for an output address
4304 for this operand or used as an output in this or a
4306 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4309 for (i = opnum; i < reload_n_operands; i++)
4310 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4315 case RELOAD_FOR_OPERAND_ADDRESS:
4316 for (i = 0; i < reload_n_operands; i++)
4317 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4320 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4321 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4323 case RELOAD_FOR_OPADDR_ADDR:
4324 for (i = 0; i < reload_n_operands; i++)
4325 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4328 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4330 case RELOAD_FOR_OUTPUT:
4331 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4332 outputs, or an operand address for this or an earlier output. */
4333 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4336 for (i = 0; i < reload_n_operands; i++)
4337 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4340 for (i = 0; i <= opnum; i++)
4341 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4342 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4347 case RELOAD_FOR_INSN:
4348 for (i = 0; i < reload_n_operands; i++)
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4350 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4353 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4354 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4356 case RELOAD_FOR_OTHER_ADDRESS:
4357 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4362 /* Return 1 if the value in reload reg REGNO, as used by a reload
4363 needed for the part of the insn specified by OPNUM and TYPE,
4364 is still available in REGNO at the end of the insn.
4366 We can assume that the reload reg was already tested for availability
4367 at the time it is needed, and we should not check this again,
4368 in case the reg has already been marked in use. */
4371 reload_reg_reaches_end_p (regno, opnum, type)
4374 enum reload_type type;
4381 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4382 its value must reach the end. */
4385 /* If this use is for part of the insn,
4386 its value reaches if no subsequent part uses the same register.
4387 Just like the above function, don't try to do this with lots
4390 case RELOAD_FOR_OTHER_ADDRESS:
4391 /* Here we check for everything else, since these don't conflict
4392 with anything else and everything comes later. */
4394 for (i = 0; i < reload_n_operands; i++)
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4397 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4398 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4400 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4403 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4404 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4405 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4407 case RELOAD_FOR_INPUT_ADDRESS:
4408 case RELOAD_FOR_INPADDR_ADDRESS:
4409 /* Similar, except that we check only for this and subsequent inputs
4410 and the address of only subsequent inputs and we do not need
4411 to check for RELOAD_OTHER objects since they are known not to
4414 for (i = opnum; i < reload_n_operands; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4418 for (i = opnum + 1; i < reload_n_operands; i++)
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4420 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4423 for (i = 0; i < reload_n_operands; i++)
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4425 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4426 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4432 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4433 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4435 case RELOAD_FOR_INPUT:
4436 /* Similar to input address, except we start at the next operand for
4437 both input and input address and we do not check for
4438 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4441 for (i = opnum + 1; i < reload_n_operands; i++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4447 /* ... fall through ... */
4449 case RELOAD_FOR_OPERAND_ADDRESS:
4450 /* Check outputs and their addresses. */
4452 for (i = 0; i < reload_n_operands; i++)
4453 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4454 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4455 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4460 case RELOAD_FOR_OPADDR_ADDR:
4461 for (i = 0; i < reload_n_operands; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4464 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4467 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4468 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4470 case RELOAD_FOR_INSN:
4471 /* These conflict with other outputs with RELOAD_OTHER. So
4472 we need only check for output addresses. */
4476 /* ... fall through ... */
4478 case RELOAD_FOR_OUTPUT:
4479 case RELOAD_FOR_OUTPUT_ADDRESS:
4480 case RELOAD_FOR_OUTADDR_ADDRESS:
4481 /* We already know these can't conflict with a later output. So the
4482 only thing to check are later output addresses. */
4483 for (i = opnum + 1; i < reload_n_operands; i++)
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4485 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4494 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4497 This function uses the same algorithm as reload_reg_free_p above. */
4500 reloads_conflict (r1, r2)
4503 enum reload_type r1_type = rld[r1].when_needed;
4504 enum reload_type r2_type = rld[r2].when_needed;
4505 int r1_opnum = rld[r1].opnum;
4506 int r2_opnum = rld[r2].opnum;
4508 /* RELOAD_OTHER conflicts with everything. */
4509 if (r2_type == RELOAD_OTHER)
4512 /* Otherwise, check conflicts differently for each type. */
4516 case RELOAD_FOR_INPUT:
4517 return (r2_type == RELOAD_FOR_INSN
4518 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4519 || r2_type == RELOAD_FOR_OPADDR_ADDR
4520 || r2_type == RELOAD_FOR_INPUT
4521 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4522 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4523 && r2_opnum > r1_opnum));
4525 case RELOAD_FOR_INPUT_ADDRESS:
4526 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4527 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4529 case RELOAD_FOR_INPADDR_ADDRESS:
4530 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4531 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4533 case RELOAD_FOR_OUTPUT_ADDRESS:
4534 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4535 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4537 case RELOAD_FOR_OUTADDR_ADDRESS:
4538 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4539 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4541 case RELOAD_FOR_OPERAND_ADDRESS:
4542 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4543 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4545 case RELOAD_FOR_OPADDR_ADDR:
4546 return (r2_type == RELOAD_FOR_INPUT
4547 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4549 case RELOAD_FOR_OUTPUT:
4550 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4551 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4552 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4553 && r2_opnum <= r1_opnum));
4555 case RELOAD_FOR_INSN:
4556 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4557 || r2_type == RELOAD_FOR_INSN
4558 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4560 case RELOAD_FOR_OTHER_ADDRESS:
4561 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4571 /* Indexed by reload number, 1 if incoming value
4572 inherited from previous insns. */
4573 char reload_inherited[MAX_RELOADS];
4575 /* For an inherited reload, this is the insn the reload was inherited from,
4576 if we know it. Otherwise, this is 0. */
4577 rtx reload_inheritance_insn[MAX_RELOADS];
4579 /* If non-zero, this is a place to get the value of the reload,
4580 rather than using reload_in. */
4581 rtx reload_override_in[MAX_RELOADS];
4583 /* For each reload, the hard register number of the register used,
4584 or -1 if we did not need a register for this reload. */
4585 int reload_spill_index[MAX_RELOADS];
4587 /* Return 1 if the value in reload reg REGNO, as used by a reload
4588 needed for the part of the insn specified by OPNUM and TYPE,
4589 may be used to load VALUE into it.
4591 Other read-only reloads with the same value do not conflict
4592 unless OUT is non-zero and these other reloads have to live while
4593 output reloads live.
4594 If OUT is CONST0_RTX, this is a special case: it means that the
4595 test should not be for using register REGNO as reload register, but
4596 for copying from register REGNO into the reload register.
4598 RELOADNUM is the number of the reload we want to load this value for;
4599 a reload does not conflict with itself.
4601 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4602 reloads that load an address for the very reload we are considering.
4604 The caller has to make sure that there is no conflict with the return
4607 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4608 ignore_address_reloads)
4611 enum reload_type type;
4614 int ignore_address_reloads;
4617 /* Set if we see an input reload that must not share its reload register
4618 with any new earlyclobber, but might otherwise share the reload
4619 register with an output or input-output reload. */
4620 int check_earlyclobber = 0;
4624 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4627 if (out == const0_rtx)
4633 /* We use some pseudo 'time' value to check if the lifetimes of the
4634 new register use would overlap with the one of a previous reload
4635 that is not read-only or uses a different value.
4636 The 'time' used doesn't have to be linear in any shape or form, just
4638 Some reload types use different 'buckets' for each operand.
4639 So there are MAX_RECOG_OPERANDS different time values for each
4641 We compute TIME1 as the time when the register for the prospective
4642 new reload ceases to be live, and TIME2 for each existing
4643 reload as the time when that the reload register of that reload
4645 Where there is little to be gained by exact lifetime calculations,
4646 we just make conservative assumptions, i.e. a longer lifetime;
4647 this is done in the 'default:' cases. */
4650 case RELOAD_FOR_OTHER_ADDRESS:
4651 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4652 time1 = copy ? 0 : 1;
4655 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4657 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4658 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4659 respectively, to the time values for these, we get distinct time
4660 values. To get distinct time values for each operand, we have to
4661 multiply opnum by at least three. We round that up to four because
4662 multiply by four is often cheaper. */
4663 case RELOAD_FOR_INPADDR_ADDRESS:
4664 time1 = opnum * 4 + 2;
4666 case RELOAD_FOR_INPUT_ADDRESS:
4667 time1 = opnum * 4 + 3;
4669 case RELOAD_FOR_INPUT:
4670 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4671 executes (inclusive). */
4672 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4674 case RELOAD_FOR_OPADDR_ADDR:
4676 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4677 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4679 case RELOAD_FOR_OPERAND_ADDRESS:
4680 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4682 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4684 case RELOAD_FOR_OUTADDR_ADDRESS:
4685 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4687 case RELOAD_FOR_OUTPUT_ADDRESS:
4688 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4691 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4694 for (i = 0; i < n_reloads; i++)
4696 rtx reg = rld[i].reg_rtx;
4697 if (reg && GET_CODE (reg) == REG
4698 && ((unsigned) regno - true_regnum (reg)
4699 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4702 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4703 || rld[i].out || out)
4706 switch (rld[i].when_needed)
4708 case RELOAD_FOR_OTHER_ADDRESS:
4711 case RELOAD_FOR_INPADDR_ADDRESS:
4712 /* find_reloads makes sure that a
4713 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4714 by at most one - the first -
4715 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4716 address reload is inherited, the address address reload
4717 goes away, so we can ignore this conflict. */
4718 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4719 && ignore_address_reloads
4720 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4721 Then the address address is still needed to store
4722 back the new address. */
4723 && ! rld[reloadnum].out)
4725 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4726 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4728 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4729 && ignore_address_reloads
4730 /* Unless we are reloading an auto_inc expression. */
4731 && ! rld[reloadnum].out)
4733 time2 = rld[i].opnum * 4 + 2;
4735 case RELOAD_FOR_INPUT_ADDRESS:
4736 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4737 && ignore_address_reloads
4738 && ! rld[reloadnum].out)
4740 time2 = rld[i].opnum * 4 + 3;
4742 case RELOAD_FOR_INPUT:
4743 time2 = rld[i].opnum * 4 + 4;
4744 check_earlyclobber = 1;
4746 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4747 == MAX_RECOG_OPERAND * 4 */
4748 case RELOAD_FOR_OPADDR_ADDR:
4749 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4750 && ignore_address_reloads
4751 && ! rld[reloadnum].out)
4753 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4755 case RELOAD_FOR_OPERAND_ADDRESS:
4756 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4757 check_earlyclobber = 1;
4759 case RELOAD_FOR_INSN:
4760 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4762 case RELOAD_FOR_OUTPUT:
4763 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4764 instruction is executed. */
4765 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4767 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4768 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4770 case RELOAD_FOR_OUTADDR_ADDRESS:
4771 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4772 && ignore_address_reloads
4773 && ! rld[reloadnum].out)
4775 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4777 case RELOAD_FOR_OUTPUT_ADDRESS:
4778 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4781 /* If there is no conflict in the input part, handle this
4782 like an output reload. */
4783 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4785 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4786 /* Earlyclobbered outputs must conflict with inputs. */
4787 if (earlyclobber_operand_p (rld[i].out))
4788 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4793 /* RELOAD_OTHER might be live beyond instruction execution,
4794 but this is not obvious when we set time2 = 1. So check
4795 here if there might be a problem with the new reload
4796 clobbering the register used by the RELOAD_OTHER. */
4804 && (! rld[i].in || rld[i].out
4805 || ! rtx_equal_p (rld[i].in, value)))
4806 || (out && rld[reloadnum].out_reg
4807 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4813 /* Earlyclobbered outputs must conflict with inputs. */
4814 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4820 /* Give an error message saying we failed to find a reload for INSN,
4821 and clear out reload R. */
4823 failed_reload (insn, r)
4827 if (asm_noperands (PATTERN (insn)) < 0)
4828 /* It's the compiler's fault. */
4829 fatal_insn ("Could not find a spill register", insn);
4831 /* It's the user's fault; the operand's mode and constraint
4832 don't match. Disable this reload so we don't crash in final. */
4833 error_for_asm (insn,
4834 "`asm' operand constraint incompatible with operand size");
4838 rld[r].optional = 1;
4839 rld[r].secondary_p = 1;
4842 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4843 for reload R. If it's valid, get an rtx for it. Return nonzero if
4846 set_reload_reg (i, r)
4850 rtx reg = spill_reg_rtx[i];
4852 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4853 spill_reg_rtx[i] = reg
4854 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4856 regno = true_regnum (reg);
4858 /* Detect when the reload reg can't hold the reload mode.
4859 This used to be one `if', but Sequent compiler can't handle that. */
4860 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4862 enum machine_mode test_mode = VOIDmode;
4864 test_mode = GET_MODE (rld[r].in);
4865 /* If rld[r].in has VOIDmode, it means we will load it
4866 in whatever mode the reload reg has: to wit, rld[r].mode.
4867 We have already tested that for validity. */
4868 /* Aside from that, we need to test that the expressions
4869 to reload from or into have modes which are valid for this
4870 reload register. Otherwise the reload insns would be invalid. */
4871 if (! (rld[r].in != 0 && test_mode != VOIDmode
4872 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4873 if (! (rld[r].out != 0
4874 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4876 /* The reg is OK. */
4879 /* Mark as in use for this insn the reload regs we use
4881 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4882 rld[r].when_needed, rld[r].mode);
4884 rld[r].reg_rtx = reg;
4885 reload_spill_index[r] = spill_regs[i];
4892 /* Find a spill register to use as a reload register for reload R.
4893 LAST_RELOAD is non-zero if this is the last reload for the insn being
4896 Set rld[R].reg_rtx to the register allocated.
4898 We return 1 if successful, or 0 if we couldn't find a spill reg and
4899 we didn't change anything. */
4902 allocate_reload_reg (chain, r, last_reload)
4903 struct insn_chain *chain ATTRIBUTE_UNUSED;
4909 /* If we put this reload ahead, thinking it is a group,
4910 then insist on finding a group. Otherwise we can grab a
4911 reg that some other reload needs.
4912 (That can happen when we have a 68000 DATA_OR_FP_REG
4913 which is a group of data regs or one fp reg.)
4914 We need not be so restrictive if there are no more reloads
4917 ??? Really it would be nicer to have smarter handling
4918 for that kind of reg class, where a problem like this is normal.
4919 Perhaps those classes should be avoided for reloading
4920 by use of more alternatives. */
4922 int force_group = rld[r].nregs > 1 && ! last_reload;
4924 /* If we want a single register and haven't yet found one,
4925 take any reg in the right class and not in use.
4926 If we want a consecutive group, here is where we look for it.
4928 We use two passes so we can first look for reload regs to
4929 reuse, which are already in use for other reloads in this insn,
4930 and only then use additional registers.
4931 I think that maximizing reuse is needed to make sure we don't
4932 run out of reload regs. Suppose we have three reloads, and
4933 reloads A and B can share regs. These need two regs.
4934 Suppose A and B are given different regs.
4935 That leaves none for C. */
4936 for (pass = 0; pass < 2; pass++)
4938 /* I is the index in spill_regs.
4939 We advance it round-robin between insns to use all spill regs
4940 equally, so that inherited reloads have a chance
4941 of leapfrogging each other. */
4945 for (count = 0; count < n_spills; count++)
4947 int class = (int) rld[r].class;
4953 regnum = spill_regs[i];
4955 if ((reload_reg_free_p (regnum, rld[r].opnum,
4958 /* We check reload_reg_used to make sure we
4959 don't clobber the return register. */
4960 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
4961 && reload_reg_free_for_value_p (regnum,
4966 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
4967 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
4968 /* Look first for regs to share, then for unshared. But
4969 don't share regs used for inherited reloads; they are
4970 the ones we want to preserve. */
4972 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4974 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4977 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
4978 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4979 (on 68000) got us two FP regs. If NR is 1,
4980 we would reject both of them. */
4983 /* If we need only one reg, we have already won. */
4986 /* But reject a single reg if we demand a group. */
4991 /* Otherwise check that as many consecutive regs as we need
4992 are available here. */
4995 int regno = regnum + nr - 1;
4996 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4997 && spill_reg_order[regno] >= 0
4998 && reload_reg_free_p (regno, rld[r].opnum,
4999 rld[r].when_needed)))
5008 /* If we found something on pass 1, omit pass 2. */
5009 if (count < n_spills)
5013 /* We should have found a spill register by now. */
5014 if (count >= n_spills)
5017 /* I is the index in SPILL_REG_RTX of the reload register we are to
5018 allocate. Get an rtx for it and find its register number. */
5020 return set_reload_reg (i, r);
5023 /* Initialize all the tables needed to allocate reload registers.
5024 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5025 is the array we use to restore the reg_rtx field for every reload. */
5027 choose_reload_regs_init (chain, save_reload_reg_rtx)
5028 struct insn_chain *chain;
5029 rtx *save_reload_reg_rtx;
5033 for (i = 0; i < n_reloads; i++)
5034 rld[i].reg_rtx = save_reload_reg_rtx[i];
5036 bzero (reload_inherited, MAX_RELOADS);
5037 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5038 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5040 CLEAR_HARD_REG_SET (reload_reg_used);
5041 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5042 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5043 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5044 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5045 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5047 CLEAR_HARD_REG_SET (reg_used_in_insn);
5050 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5051 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5052 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5053 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5054 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5055 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5057 for (i = 0; i < reload_n_operands; i++)
5059 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5060 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5061 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5062 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5063 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5064 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5067 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5069 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5071 for (i = 0; i < n_reloads; i++)
5072 /* If we have already decided to use a certain register,
5073 don't use it in another way. */
5075 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5076 rld[i].when_needed, rld[i].mode);
5079 /* Assign hard reg targets for the pseudo-registers we must reload
5080 into hard regs for this insn.
5081 Also output the instructions to copy them in and out of the hard regs.
5083 For machines with register classes, we are responsible for
5084 finding a reload reg in the proper class. */
5087 choose_reload_regs (chain)
5088 struct insn_chain *chain;
5090 rtx insn = chain->insn;
5092 int max_group_size = 1;
5093 enum reg_class group_class = NO_REGS;
5094 int pass, win, inheritance;
5096 rtx save_reload_reg_rtx[MAX_RELOADS];
5098 /* In order to be certain of getting the registers we need,
5099 we must sort the reloads into order of increasing register class.
5100 Then our grabbing of reload registers will parallel the process
5101 that provided the reload registers.
5103 Also note whether any of the reloads wants a consecutive group of regs.
5104 If so, record the maximum size of the group desired and what
5105 register class contains all the groups needed by this insn. */
5107 for (j = 0; j < n_reloads; j++)
5109 reload_order[j] = j;
5110 reload_spill_index[j] = -1;
5112 if (rld[j].nregs > 1)
5114 max_group_size = MAX (rld[j].nregs, max_group_size);
5115 group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
5118 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5122 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5124 /* If -O, try first with inheritance, then turning it off.
5125 If not -O, don't do inheritance.
5126 Using inheritance when not optimizing leads to paradoxes
5127 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5128 because one side of the comparison might be inherited. */
5130 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5132 choose_reload_regs_init (chain, save_reload_reg_rtx);
5134 /* Process the reloads in order of preference just found.
5135 Beyond this point, subregs can be found in reload_reg_rtx.
5137 This used to look for an existing reloaded home for all
5138 of the reloads, and only then perform any new reloads.
5139 But that could lose if the reloads were done out of reg-class order
5140 because a later reload with a looser constraint might have an old
5141 home in a register needed by an earlier reload with a tighter constraint.
5143 To solve this, we make two passes over the reloads, in the order
5144 described above. In the first pass we try to inherit a reload
5145 from a previous insn. If there is a later reload that needs a
5146 class that is a proper subset of the class being processed, we must
5147 also allocate a spill register during the first pass.
5149 Then make a second pass over the reloads to allocate any reloads
5150 that haven't been given registers yet. */
5152 for (j = 0; j < n_reloads; j++)
5154 register int r = reload_order[j];
5155 rtx search_equiv = NULL_RTX;
5157 /* Ignore reloads that got marked inoperative. */
5158 if (rld[r].out == 0 && rld[r].in == 0
5159 && ! rld[r].secondary_p)
5162 /* If find_reloads chose to use reload_in or reload_out as a reload
5163 register, we don't need to chose one. Otherwise, try even if it
5164 found one since we might save an insn if we find the value lying
5166 Try also when reload_in is a pseudo without a hard reg. */
5167 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5168 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5169 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5170 && GET_CODE (rld[r].in) != MEM
5171 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5174 #if 0 /* No longer needed for correct operation.
5175 It might give better code, or might not; worth an experiment? */
5176 /* If this is an optional reload, we can't inherit from earlier insns
5177 until we are sure that any non-optional reloads have been allocated.
5178 The following code takes advantage of the fact that optional reloads
5179 are at the end of reload_order. */
5180 if (rld[r].optional != 0)
5181 for (i = 0; i < j; i++)
5182 if ((rld[reload_order[i]].out != 0
5183 || rld[reload_order[i]].in != 0
5184 || rld[reload_order[i]].secondary_p)
5185 && ! rld[reload_order[i]].optional
5186 && rld[reload_order[i]].reg_rtx == 0)
5187 allocate_reload_reg (chain, reload_order[i], 0);
5190 /* First see if this pseudo is already available as reloaded
5191 for a previous insn. We cannot try to inherit for reloads
5192 that are smaller than the maximum number of registers needed
5193 for groups unless the register we would allocate cannot be used
5196 We could check here to see if this is a secondary reload for
5197 an object that is already in a register of the desired class.
5198 This would avoid the need for the secondary reload register.
5199 But this is complex because we can't easily determine what
5200 objects might want to be loaded via this reload. So let a
5201 register be allocated here. In `emit_reload_insns' we suppress
5202 one of the loads in the case described above. */
5207 register int regno = -1;
5208 enum machine_mode mode = VOIDmode;
5212 else if (GET_CODE (rld[r].in) == REG)
5214 regno = REGNO (rld[r].in);
5215 mode = GET_MODE (rld[r].in);
5217 else if (GET_CODE (rld[r].in_reg) == REG)
5219 regno = REGNO (rld[r].in_reg);
5220 mode = GET_MODE (rld[r].in_reg);
5222 else if (GET_CODE (rld[r].in_reg) == SUBREG
5223 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5225 word = SUBREG_WORD (rld[r].in_reg);
5226 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5227 if (regno < FIRST_PSEUDO_REGISTER)
5229 mode = GET_MODE (rld[r].in_reg);
5232 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5233 || GET_CODE (rld[r].in_reg) == PRE_DEC
5234 || GET_CODE (rld[r].in_reg) == POST_INC
5235 || GET_CODE (rld[r].in_reg) == POST_DEC)
5236 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5238 regno = REGNO (XEXP (rld[r].in_reg, 0));
5239 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5240 rld[r].out = rld[r].in;
5244 /* This won't work, since REGNO can be a pseudo reg number.
5245 Also, it takes much more hair to keep track of all the things
5246 that can invalidate an inherited reload of part of a pseudoreg. */
5247 else if (GET_CODE (rld[r].in) == SUBREG
5248 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5249 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5252 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5254 enum reg_class class = rld[r].class, last_class;
5255 rtx last_reg = reg_last_reload_reg[regno];
5257 i = REGNO (last_reg) + word;
5258 last_class = REGNO_REG_CLASS (i);
5259 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5260 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5261 && reg_reloaded_contents[i] == regno
5262 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5263 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5264 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5265 /* Even if we can't use this register as a reload
5266 register, we might use it for reload_override_in,
5267 if copying it to the desired class is cheap
5269 || ((REGISTER_MOVE_COST (last_class, class)
5270 < MEMORY_MOVE_COST (mode, class, 1))
5271 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5272 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5276 #ifdef SECONDARY_MEMORY_NEEDED
5277 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5282 && (rld[r].nregs == max_group_size
5283 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5285 && reload_reg_free_for_value_p (i, rld[r].opnum,
5290 /* If a group is needed, verify that all the subsequent
5291 registers still have their values intact. */
5293 = HARD_REGNO_NREGS (i, rld[r].mode);
5296 for (k = 1; k < nr; k++)
5297 if (reg_reloaded_contents[i + k] != regno
5298 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5305 last_reg = (GET_MODE (last_reg) == mode
5306 ? last_reg : gen_rtx_REG (mode, i));
5308 /* We found a register that contains the
5309 value we need. If this register is the
5310 same as an `earlyclobber' operand of the
5311 current insn, just mark it as a place to
5312 reload from since we can't use it as the
5313 reload register itself. */
5315 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5316 if (reg_overlap_mentioned_for_reload_p
5317 (reg_last_reload_reg[regno],
5318 reload_earlyclobbers[i1]))
5321 if (i1 != n_earlyclobbers
5322 || ! (reload_reg_free_for_value_p
5323 (i, rld[r].opnum, rld[r].when_needed,
5324 rld[r].in, rld[r].out, r, 1))
5325 /* Don't use it if we'd clobber a pseudo reg. */
5326 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5328 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5329 /* Don't clobber the frame pointer. */
5330 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5331 /* Don't really use the inherited spill reg
5332 if we need it wider than we've got it. */
5333 || (GET_MODE_SIZE (rld[r].mode)
5334 > GET_MODE_SIZE (mode))
5335 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5338 /* If find_reloads chose reload_out as reload
5339 register, stay with it - that leaves the
5340 inherited register for subsequent reloads. */
5341 || (rld[r].out && rld[r].reg_rtx
5342 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5344 reload_override_in[r] = last_reg;
5345 reload_inheritance_insn[r]
5346 = reg_reloaded_insn[i];
5351 /* We can use this as a reload reg. */
5352 /* Mark the register as in use for this part of
5354 mark_reload_reg_in_use (i,
5358 rld[r].reg_rtx = last_reg;
5359 reload_inherited[r] = 1;
5360 reload_inheritance_insn[r]
5361 = reg_reloaded_insn[i];
5362 reload_spill_index[r] = i;
5363 for (k = 0; k < nr; k++)
5364 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5372 /* Here's another way to see if the value is already lying around. */
5375 && ! reload_inherited[r]
5377 && (CONSTANT_P (rld[r].in)
5378 || GET_CODE (rld[r].in) == PLUS
5379 || GET_CODE (rld[r].in) == REG
5380 || GET_CODE (rld[r].in) == MEM)
5381 && (rld[r].nregs == max_group_size
5382 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5383 search_equiv = rld[r].in;
5384 /* If this is an output reload from a simple move insn, look
5385 if an equivalence for the input is available. */
5386 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5388 rtx set = single_set (insn);
5391 && rtx_equal_p (rld[r].out, SET_DEST (set))
5392 && CONSTANT_P (SET_SRC (set)))
5393 search_equiv = SET_SRC (set);
5399 = find_equiv_reg (search_equiv, insn, rld[r].class,
5400 -1, NULL_PTR, 0, rld[r].mode);
5405 if (GET_CODE (equiv) == REG)
5406 regno = REGNO (equiv);
5407 else if (GET_CODE (equiv) == SUBREG)
5409 /* This must be a SUBREG of a hard register.
5410 Make a new REG since this might be used in an
5411 address and not all machines support SUBREGs
5413 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5414 equiv = gen_rtx_REG (rld[r].mode, regno);
5420 /* If we found a spill reg, reject it unless it is free
5421 and of the desired class. */
5423 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5424 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5428 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5432 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5435 /* We found a register that contains the value we need.
5436 If this register is the same as an `earlyclobber' operand
5437 of the current insn, just mark it as a place to reload from
5438 since we can't use it as the reload register itself. */
5441 for (i = 0; i < n_earlyclobbers; i++)
5442 if (reg_overlap_mentioned_for_reload_p (equiv,
5443 reload_earlyclobbers[i]))
5445 reload_override_in[r] = equiv;
5450 /* If the equiv register we have found is explicitly clobbered
5451 in the current insn, it depends on the reload type if we
5452 can use it, use it for reload_override_in, or not at all.
5453 In particular, we then can't use EQUIV for a
5454 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5456 if (equiv != 0 && regno_clobbered_p (regno, insn))
5458 switch (rld[r].when_needed)
5460 case RELOAD_FOR_OTHER_ADDRESS:
5461 case RELOAD_FOR_INPADDR_ADDRESS:
5462 case RELOAD_FOR_INPUT_ADDRESS:
5463 case RELOAD_FOR_OPADDR_ADDR:
5466 case RELOAD_FOR_INPUT:
5467 case RELOAD_FOR_OPERAND_ADDRESS:
5468 reload_override_in[r] = equiv;
5476 /* If we found an equivalent reg, say no code need be generated
5477 to load it, and use it as our reload reg. */
5478 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5480 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5482 rld[r].reg_rtx = equiv;
5483 reload_inherited[r] = 1;
5485 /* If reg_reloaded_valid is not set for this register,
5486 there might be a stale spill_reg_store lying around.
5487 We must clear it, since otherwise emit_reload_insns
5488 might delete the store. */
5489 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5490 spill_reg_store[regno] = NULL_RTX;
5491 /* If any of the hard registers in EQUIV are spill
5492 registers, mark them as in use for this insn. */
5493 for (k = 0; k < nr; k++)
5495 i = spill_reg_order[regno + k];
5498 mark_reload_reg_in_use (regno, rld[r].opnum,
5501 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5508 /* If we found a register to use already, or if this is an optional
5509 reload, we are done. */
5510 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5513 #if 0 /* No longer needed for correct operation. Might or might not
5514 give better code on the average. Want to experiment? */
5516 /* See if there is a later reload that has a class different from our
5517 class that intersects our class or that requires less register
5518 than our reload. If so, we must allocate a register to this
5519 reload now, since that reload might inherit a previous reload
5520 and take the only available register in our class. Don't do this
5521 for optional reloads since they will force all previous reloads
5522 to be allocated. Also don't do this for reloads that have been
5525 for (i = j + 1; i < n_reloads; i++)
5527 int s = reload_order[i];
5529 if ((rld[s].in == 0 && rld[s].out == 0
5530 && ! rld[s].secondary_p)
5534 if ((rld[s].class != rld[r].class
5535 && reg_classes_intersect_p (rld[r].class,
5537 || rld[s].nregs < rld[r].nregs)
5544 allocate_reload_reg (chain, r, j == n_reloads - 1);
5548 /* Now allocate reload registers for anything non-optional that
5549 didn't get one yet. */
5550 for (j = 0; j < n_reloads; j++)
5552 register int r = reload_order[j];
5554 /* Ignore reloads that got marked inoperative. */
5555 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5558 /* Skip reloads that already have a register allocated or are
5560 if (rld[r].reg_rtx != 0 || rld[r].optional)
5563 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5567 /* If that loop got all the way, we have won. */
5574 /* Loop around and try without any inheritance. */
5579 /* First undo everything done by the failed attempt
5580 to allocate with inheritance. */
5581 choose_reload_regs_init (chain, save_reload_reg_rtx);
5583 /* Some sanity tests to verify that the reloads found in the first
5584 pass are identical to the ones we have now. */
5585 if (chain->n_reloads != n_reloads)
5588 for (i = 0; i < n_reloads; i++)
5590 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5592 if (chain->rld[i].when_needed != rld[i].when_needed)
5594 for (j = 0; j < n_spills; j++)
5595 if (spill_regs[j] == chain->rld[i].regno)
5596 if (! set_reload_reg (j, i))
5597 failed_reload (chain->insn, i);
5601 /* If we thought we could inherit a reload, because it seemed that
5602 nothing else wanted the same reload register earlier in the insn,
5603 verify that assumption, now that all reloads have been assigned.
5604 Likewise for reloads where reload_override_in has been set. */
5606 /* If doing expensive optimizations, do one preliminary pass that doesn't
5607 cancel any inheritance, but removes reloads that have been needed only
5608 for reloads that we know can be inherited. */
5609 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5611 for (j = 0; j < n_reloads; j++)
5613 register int r = reload_order[j];
5615 if (reload_inherited[r] && rld[r].reg_rtx)
5616 check_reg = rld[r].reg_rtx;
5617 else if (reload_override_in[r]
5618 && (GET_CODE (reload_override_in[r]) == REG
5619 || GET_CODE (reload_override_in[r]) == SUBREG))
5620 check_reg = reload_override_in[r];
5623 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5627 (reload_inherited[r]
5628 ? rld[r].out : const0_rtx),
5633 reload_inherited[r] = 0;
5634 reload_override_in[r] = 0;
5636 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5637 reload_override_in, then we do not need its related
5638 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5639 likewise for other reload types.
5640 We handle this by removing a reload when its only replacement
5641 is mentioned in reload_in of the reload we are going to inherit.
5642 A special case are auto_inc expressions; even if the input is
5643 inherited, we still need the address for the output. We can
5644 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5645 If we suceeded removing some reload and we are doing a preliminary
5646 pass just to remove such reloads, make another pass, since the
5647 removal of one reload might allow us to inherit another one. */
5649 && rld[r].out != rld[r].in
5650 && remove_address_replacements (rld[r].in) && pass)
5655 /* Now that reload_override_in is known valid,
5656 actually override reload_in. */
5657 for (j = 0; j < n_reloads; j++)
5658 if (reload_override_in[j])
5659 rld[j].in = reload_override_in[j];
5661 /* If this reload won't be done because it has been cancelled or is
5662 optional and not inherited, clear reload_reg_rtx so other
5663 routines (such as subst_reloads) don't get confused. */
5664 for (j = 0; j < n_reloads; j++)
5665 if (rld[j].reg_rtx != 0
5666 && ((rld[j].optional && ! reload_inherited[j])
5667 || (rld[j].in == 0 && rld[j].out == 0
5668 && ! rld[j].secondary_p)))
5670 int regno = true_regnum (rld[j].reg_rtx);
5672 if (spill_reg_order[regno] >= 0)
5673 clear_reload_reg_in_use (regno, rld[j].opnum,
5674 rld[j].when_needed, rld[j].mode);
5676 reload_spill_index[j] = -1;
5679 /* Record which pseudos and which spill regs have output reloads. */
5680 for (j = 0; j < n_reloads; j++)
5682 register int r = reload_order[j];
5684 i = reload_spill_index[r];
5686 /* I is nonneg if this reload uses a register.
5687 If rld[r].reg_rtx is 0, this is an optional reload
5688 that we opted to ignore. */
5689 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5690 && rld[r].reg_rtx != 0)
5692 register int nregno = REGNO (rld[r].out_reg);
5695 if (nregno < FIRST_PSEUDO_REGISTER)
5696 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5699 reg_has_output_reload[nregno + nr] = 1;
5703 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5705 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5708 if (rld[r].when_needed != RELOAD_OTHER
5709 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5710 && rld[r].when_needed != RELOAD_FOR_INSN)
5716 /* Deallocate the reload register for reload R. This is called from
5717 remove_address_replacements. */
5719 deallocate_reload_reg (r)
5724 if (! rld[r].reg_rtx)
5726 regno = true_regnum (rld[r].reg_rtx);
5728 if (spill_reg_order[regno] >= 0)
5729 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5731 reload_spill_index[r] = -1;
5734 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5735 reloads of the same item for fear that we might not have enough reload
5736 registers. However, normally they will get the same reload register
5737 and hence actually need not be loaded twice.
5739 Here we check for the most common case of this phenomenon: when we have
5740 a number of reloads for the same object, each of which were allocated
5741 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5742 reload, and is not modified in the insn itself. If we find such,
5743 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5744 This will not increase the number of spill registers needed and will
5745 prevent redundant code. */
5748 merge_assigned_reloads (insn)
5753 /* Scan all the reloads looking for ones that only load values and
5754 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5755 assigned and not modified by INSN. */
5757 for (i = 0; i < n_reloads; i++)
5759 int conflicting_input = 0;
5760 int max_input_address_opnum = -1;
5761 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5763 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5764 || rld[i].out != 0 || rld[i].reg_rtx == 0
5765 || reg_set_p (rld[i].reg_rtx, insn))
5768 /* Look at all other reloads. Ensure that the only use of this
5769 reload_reg_rtx is in a reload that just loads the same value
5770 as we do. Note that any secondary reloads must be of the identical
5771 class since the values, modes, and result registers are the
5772 same, so we need not do anything with any secondary reloads. */
5774 for (j = 0; j < n_reloads; j++)
5776 if (i == j || rld[j].reg_rtx == 0
5777 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5781 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5782 && rld[j].opnum > max_input_address_opnum)
5783 max_input_address_opnum = rld[j].opnum;
5785 /* If the reload regs aren't exactly the same (e.g, different modes)
5786 or if the values are different, we can't merge this reload.
5787 But if it is an input reload, we might still merge
5788 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5790 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5791 || rld[j].out != 0 || rld[j].in == 0
5792 || ! rtx_equal_p (rld[i].in, rld[j].in))
5794 if (rld[j].when_needed != RELOAD_FOR_INPUT
5795 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5796 || rld[i].opnum > rld[j].opnum)
5797 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5799 conflicting_input = 1;
5800 if (min_conflicting_input_opnum > rld[j].opnum)
5801 min_conflicting_input_opnum = rld[j].opnum;
5805 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5806 we, in fact, found any matching reloads. */
5809 && max_input_address_opnum <= min_conflicting_input_opnum)
5811 for (j = 0; j < n_reloads; j++)
5812 if (i != j && rld[j].reg_rtx != 0
5813 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5814 && (! conflicting_input
5815 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5816 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5818 rld[i].when_needed = RELOAD_OTHER;
5820 reload_spill_index[j] = -1;
5821 transfer_replacements (i, j);
5824 /* If this is now RELOAD_OTHER, look for any reloads that load
5825 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5826 if they were for inputs, RELOAD_OTHER for outputs. Note that
5827 this test is equivalent to looking for reloads for this operand
5830 if (rld[i].when_needed == RELOAD_OTHER)
5831 for (j = 0; j < n_reloads; j++)
5833 && rld[i].when_needed != RELOAD_OTHER
5834 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5837 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5838 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5839 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5845 /* These arrays are filled by emit_reload_insns and its subroutines. */
5846 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5847 static rtx other_input_address_reload_insns = 0;
5848 static rtx other_input_reload_insns = 0;
5849 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5850 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5851 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5852 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5853 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5854 static rtx operand_reload_insns = 0;
5855 static rtx other_operand_reload_insns = 0;
5856 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5858 /* Values to be put in spill_reg_store are put here first. */
5859 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5860 static HARD_REG_SET reg_reloaded_died;
5862 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5863 has the number J. OLD contains the value to be used as input. */
5865 emit_input_reload_insns (chain, rl, old, j)
5866 struct insn_chain *chain;
5871 rtx insn = chain->insn;
5872 register rtx reloadreg = rl->reg_rtx;
5873 rtx oldequiv_reg = 0;
5876 enum machine_mode mode;
5879 /* Determine the mode to reload in.
5880 This is very tricky because we have three to choose from.
5881 There is the mode the insn operand wants (rl->inmode).
5882 There is the mode of the reload register RELOADREG.
5883 There is the intrinsic mode of the operand, which we could find
5884 by stripping some SUBREGs.
5885 It turns out that RELOADREG's mode is irrelevant:
5886 we can change that arbitrarily.
5888 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5889 then the reload reg may not support QImode moves, so use SImode.
5890 If foo is in memory due to spilling a pseudo reg, this is safe,
5891 because the QImode value is in the least significant part of a
5892 slot big enough for a SImode. If foo is some other sort of
5893 memory reference, then it is impossible to reload this case,
5894 so previous passes had better make sure this never happens.
5896 Then consider a one-word union which has SImode and one of its
5897 members is a float, being fetched as (SUBREG:SF union:SI).
5898 We must fetch that as SFmode because we could be loading into
5899 a float-only register. In this case OLD's mode is correct.
5901 Consider an immediate integer: it has VOIDmode. Here we need
5902 to get a mode from something else.
5904 In some cases, there is a fourth mode, the operand's
5905 containing mode. If the insn specifies a containing mode for
5906 this operand, it overrides all others.
5908 I am not sure whether the algorithm here is always right,
5909 but it does the right things in those cases. */
5911 mode = GET_MODE (old);
5912 if (mode == VOIDmode)
5915 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5916 /* If we need a secondary register for this operation, see if
5917 the value is already in a register in that class. Don't
5918 do this if the secondary register will be used as a scratch
5921 if (rl->secondary_in_reload >= 0
5922 && rl->secondary_in_icode == CODE_FOR_nothing
5925 = find_equiv_reg (old, insn,
5926 rld[rl->secondary_in_reload].class,
5927 -1, NULL_PTR, 0, mode);
5930 /* If reloading from memory, see if there is a register
5931 that already holds the same value. If so, reload from there.
5932 We can pass 0 as the reload_reg_p argument because
5933 any other reload has either already been emitted,
5934 in which case find_equiv_reg will see the reload-insn,
5935 or has yet to be emitted, in which case it doesn't matter
5936 because we will use this equiv reg right away. */
5938 if (oldequiv == 0 && optimize
5939 && (GET_CODE (old) == MEM
5940 || (GET_CODE (old) == REG
5941 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5942 && reg_renumber[REGNO (old)] < 0)))
5943 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5944 -1, NULL_PTR, 0, mode);
5948 int regno = true_regnum (oldequiv);
5950 /* Don't use OLDEQUIV if any other reload changes it at an
5951 earlier stage of this insn or at this stage. */
5952 if (! reload_reg_free_for_value_p (regno, rl->opnum,
5954 rl->in, const0_rtx, j,
5958 /* If it is no cheaper to copy from OLDEQUIV into the
5959 reload register than it would be to move from memory,
5960 don't use it. Likewise, if we need a secondary register
5964 && ((REGNO_REG_CLASS (regno) != rl->class
5965 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5967 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
5968 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5969 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
5973 #ifdef SECONDARY_MEMORY_NEEDED
5974 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
5982 /* delete_output_reload is only invoked properly if old contains
5983 the original pseudo register. Since this is replaced with a
5984 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
5985 find the pseudo in RELOAD_IN_REG. */
5987 && reload_override_in[j]
5988 && GET_CODE (rl->in_reg) == REG)
5995 else if (GET_CODE (oldequiv) == REG)
5996 oldequiv_reg = oldequiv;
5997 else if (GET_CODE (oldequiv) == SUBREG)
5998 oldequiv_reg = SUBREG_REG (oldequiv);
6000 /* If we are reloading from a register that was recently stored in
6001 with an output-reload, see if we can prove there was
6002 actually no need to store the old value in it. */
6004 if (optimize && GET_CODE (oldequiv) == REG
6005 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6006 && spill_reg_store[REGNO (oldequiv)]
6007 && GET_CODE (old) == REG
6008 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6009 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6011 delete_output_reload (insn, j, REGNO (oldequiv));
6013 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6014 then load RELOADREG from OLDEQUIV. Note that we cannot use
6015 gen_lowpart_common since it can do the wrong thing when
6016 RELOADREG has a multi-word mode. Note that RELOADREG
6017 must always be a REG here. */
6019 if (GET_MODE (reloadreg) != mode)
6020 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6021 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6022 oldequiv = SUBREG_REG (oldequiv);
6023 if (GET_MODE (oldequiv) != VOIDmode
6024 && mode != GET_MODE (oldequiv))
6025 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6027 /* Switch to the right place to emit the reload insns. */
6028 switch (rl->when_needed)
6031 where = &other_input_reload_insns;
6033 case RELOAD_FOR_INPUT:
6034 where = &input_reload_insns[rl->opnum];
6036 case RELOAD_FOR_INPUT_ADDRESS:
6037 where = &input_address_reload_insns[rl->opnum];
6039 case RELOAD_FOR_INPADDR_ADDRESS:
6040 where = &inpaddr_address_reload_insns[rl->opnum];
6042 case RELOAD_FOR_OUTPUT_ADDRESS:
6043 where = &output_address_reload_insns[rl->opnum];
6045 case RELOAD_FOR_OUTADDR_ADDRESS:
6046 where = &outaddr_address_reload_insns[rl->opnum];
6048 case RELOAD_FOR_OPERAND_ADDRESS:
6049 where = &operand_reload_insns;
6051 case RELOAD_FOR_OPADDR_ADDR:
6052 where = &other_operand_reload_insns;
6054 case RELOAD_FOR_OTHER_ADDRESS:
6055 where = &other_input_address_reload_insns;
6061 push_to_sequence (*where);
6063 /* Auto-increment addresses must be reloaded in a special way. */
6064 if (rl->out && ! rl->out_reg)
6066 /* We are not going to bother supporting the case where a
6067 incremented register can't be copied directly from
6068 OLDEQUIV since this seems highly unlikely. */
6069 if (rl->secondary_in_reload >= 0)
6072 if (reload_inherited[j])
6073 oldequiv = reloadreg;
6075 old = XEXP (rl->in_reg, 0);
6077 if (optimize && GET_CODE (oldequiv) == REG
6078 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6079 && spill_reg_store[REGNO (oldequiv)]
6080 && GET_CODE (old) == REG
6081 && (dead_or_set_p (insn,
6082 spill_reg_stored_to[REGNO (oldequiv)])
6083 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6085 delete_output_reload (insn, j, REGNO (oldequiv));
6087 /* Prevent normal processing of this reload. */
6089 /* Output a special code sequence for this case. */
6090 new_spill_reg_store[REGNO (reloadreg)]
6091 = inc_for_reload (reloadreg, oldequiv, rl->out,
6095 /* If we are reloading a pseudo-register that was set by the previous
6096 insn, see if we can get rid of that pseudo-register entirely
6097 by redirecting the previous insn into our reload register. */
6099 else if (optimize && GET_CODE (old) == REG
6100 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6101 && dead_or_set_p (insn, old)
6102 /* This is unsafe if some other reload
6103 uses the same reg first. */
6104 && reload_reg_free_for_value_p (REGNO (reloadreg),
6110 rtx temp = PREV_INSN (insn);
6111 while (temp && GET_CODE (temp) == NOTE)
6112 temp = PREV_INSN (temp);
6114 && GET_CODE (temp) == INSN
6115 && GET_CODE (PATTERN (temp)) == SET
6116 && SET_DEST (PATTERN (temp)) == old
6117 /* Make sure we can access insn_operand_constraint. */
6118 && asm_noperands (PATTERN (temp)) < 0
6119 /* This is unsafe if prev insn rejects our reload reg. */
6120 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6122 /* This is unsafe if operand occurs more than once in current
6123 insn. Perhaps some occurrences aren't reloaded. */
6124 && count_occurrences (PATTERN (insn), old) == 1
6125 /* Don't risk splitting a matching pair of operands. */
6126 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6128 /* Store into the reload register instead of the pseudo. */
6129 SET_DEST (PATTERN (temp)) = reloadreg;
6131 /* If the previous insn is an output reload, the source is
6132 a reload register, and its spill_reg_store entry will
6133 contain the previous destination. This is now
6135 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6136 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6138 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6139 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6142 /* If these are the only uses of the pseudo reg,
6143 pretend for GDB it lives in the reload reg we used. */
6144 if (REG_N_DEATHS (REGNO (old)) == 1
6145 && REG_N_SETS (REGNO (old)) == 1)
6147 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6148 alter_reg (REGNO (old), -1);
6154 /* We can't do that, so output an insn to load RELOADREG. */
6156 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6157 /* If we have a secondary reload, pick up the secondary register
6158 and icode, if any. If OLDEQUIV and OLD are different or
6159 if this is an in-out reload, recompute whether or not we
6160 still need a secondary register and what the icode should
6161 be. If we still need a secondary register and the class or
6162 icode is different, go back to reloading from OLD if using
6163 OLDEQUIV means that we got the wrong type of register. We
6164 cannot have different class or icode due to an in-out reload
6165 because we don't make such reloads when both the input and
6166 output need secondary reload registers. */
6168 if (! special && rl->secondary_in_reload >= 0)
6170 rtx second_reload_reg = 0;
6171 int secondary_reload = rl->secondary_in_reload;
6172 rtx real_oldequiv = oldequiv;
6175 enum insn_code icode;
6177 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6178 and similarly for OLD.
6179 See comments in get_secondary_reload in reload.c. */
6180 /* If it is a pseudo that cannot be replaced with its
6181 equivalent MEM, we must fall back to reload_in, which
6182 will have all the necessary substitutions registered.
6183 Likewise for a pseudo that can't be replaced with its
6184 equivalent constant.
6186 Take extra care for subregs of such pseudos. Note that
6187 we cannot use reg_equiv_mem in this case because it is
6188 not in the right mode. */
6191 if (GET_CODE (tmp) == SUBREG)
6192 tmp = SUBREG_REG (tmp);
6193 if (GET_CODE (tmp) == REG
6194 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6195 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6196 || reg_equiv_constant[REGNO (tmp)] != 0))
6198 if (! reg_equiv_mem[REGNO (tmp)]
6199 || num_not_at_initial_offset
6200 || GET_CODE (oldequiv) == SUBREG)
6201 real_oldequiv = rl->in;
6203 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6207 if (GET_CODE (tmp) == SUBREG)
6208 tmp = SUBREG_REG (tmp);
6209 if (GET_CODE (tmp) == REG
6210 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6211 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6212 || reg_equiv_constant[REGNO (tmp)] != 0))
6214 if (! reg_equiv_mem[REGNO (tmp)]
6215 || num_not_at_initial_offset
6216 || GET_CODE (old) == SUBREG)
6219 real_old = reg_equiv_mem[REGNO (tmp)];
6222 second_reload_reg = rld[secondary_reload].reg_rtx;
6223 icode = rl->secondary_in_icode;
6225 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6226 || (rl->in != 0 && rl->out != 0))
6228 enum reg_class new_class
6229 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6230 mode, real_oldequiv);
6232 if (new_class == NO_REGS)
6233 second_reload_reg = 0;
6236 enum insn_code new_icode;
6237 enum machine_mode new_mode;
6239 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6240 REGNO (second_reload_reg)))
6241 oldequiv = old, real_oldequiv = real_old;
6244 new_icode = reload_in_optab[(int) mode];
6245 if (new_icode != CODE_FOR_nothing
6246 && ((insn_data[(int) new_icode].operand[0].predicate
6247 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6249 || (insn_data[(int) new_icode].operand[1].predicate
6250 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6251 (real_oldequiv, mode)))))
6252 new_icode = CODE_FOR_nothing;
6254 if (new_icode == CODE_FOR_nothing)
6257 new_mode = insn_data[(int) new_icode].operand[2].mode;
6259 if (GET_MODE (second_reload_reg) != new_mode)
6261 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6263 oldequiv = old, real_oldequiv = real_old;
6266 = gen_rtx_REG (new_mode,
6267 REGNO (second_reload_reg));
6273 /* If we still need a secondary reload register, check
6274 to see if it is being used as a scratch or intermediate
6275 register and generate code appropriately. If we need
6276 a scratch register, use REAL_OLDEQUIV since the form of
6277 the insn may depend on the actual address if it is
6280 if (second_reload_reg)
6282 if (icode != CODE_FOR_nothing)
6284 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6285 second_reload_reg));
6290 /* See if we need a scratch register to load the
6291 intermediate register (a tertiary reload). */
6292 enum insn_code tertiary_icode
6293 = rld[secondary_reload].secondary_in_icode;
6295 if (tertiary_icode != CODE_FOR_nothing)
6297 rtx third_reload_reg
6298 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6300 emit_insn ((GEN_FCN (tertiary_icode)
6301 (second_reload_reg, real_oldequiv,
6302 third_reload_reg)));
6305 gen_reload (second_reload_reg, real_oldequiv,
6309 oldequiv = second_reload_reg;
6315 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6317 rtx real_oldequiv = oldequiv;
6319 if ((GET_CODE (oldequiv) == REG
6320 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6321 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6322 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6323 || (GET_CODE (oldequiv) == SUBREG
6324 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6325 && (REGNO (SUBREG_REG (oldequiv))
6326 >= FIRST_PSEUDO_REGISTER)
6327 && ((reg_equiv_memory_loc
6328 [REGNO (SUBREG_REG (oldequiv))] != 0)
6329 || (reg_equiv_constant
6330 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6331 real_oldequiv = rl->in;
6332 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6336 /* End this sequence. */
6337 *where = get_insns ();
6340 /* Update reload_override_in so that delete_address_reloads_1
6341 can see the actual register usage. */
6343 reload_override_in[j] = oldequiv;
6346 /* Generate insns to for the output reload RL, which is for the insn described
6347 by CHAIN and has the number J. */
6349 emit_output_reload_insns (chain, rl, j)
6350 struct insn_chain *chain;
6354 rtx reloadreg = rl->reg_rtx;
6355 rtx insn = chain->insn;
6358 enum machine_mode mode = GET_MODE (old);
6361 if (rl->when_needed == RELOAD_OTHER)
6364 push_to_sequence (output_reload_insns[rl->opnum]);
6366 /* Determine the mode to reload in.
6367 See comments above (for input reloading). */
6369 if (mode == VOIDmode)
6371 /* VOIDmode should never happen for an output. */
6372 if (asm_noperands (PATTERN (insn)) < 0)
6373 /* It's the compiler's fault. */
6374 fatal_insn ("VOIDmode on an output", insn);
6375 error_for_asm (insn, "output operand is constant in `asm'");
6376 /* Prevent crash--use something we know is valid. */
6378 old = gen_rtx_REG (mode, REGNO (reloadreg));
6381 if (GET_MODE (reloadreg) != mode)
6382 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6384 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6386 /* If we need two reload regs, set RELOADREG to the intermediate
6387 one, since it will be stored into OLD. We might need a secondary
6388 register only for an input reload, so check again here. */
6390 if (rl->secondary_out_reload >= 0)
6394 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6395 && reg_equiv_mem[REGNO (old)] != 0)
6396 real_old = reg_equiv_mem[REGNO (old)];
6398 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6402 rtx second_reloadreg = reloadreg;
6403 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6405 /* See if RELOADREG is to be used as a scratch register
6406 or as an intermediate register. */
6407 if (rl->secondary_out_icode != CODE_FOR_nothing)
6409 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6410 (real_old, second_reloadreg, reloadreg)));
6415 /* See if we need both a scratch and intermediate reload
6418 int secondary_reload = rl->secondary_out_reload;
6419 enum insn_code tertiary_icode
6420 = rld[secondary_reload].secondary_out_icode;
6422 if (GET_MODE (reloadreg) != mode)
6423 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6425 if (tertiary_icode != CODE_FOR_nothing)
6428 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6431 /* Copy primary reload reg to secondary reload reg.
6432 (Note that these have been swapped above, then
6433 secondary reload reg to OLD using our insn. */
6435 /* If REAL_OLD is a paradoxical SUBREG, remove it
6436 and try to put the opposite SUBREG on
6438 if (GET_CODE (real_old) == SUBREG
6439 && (GET_MODE_SIZE (GET_MODE (real_old))
6440 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6441 && 0 != (tem = gen_lowpart_common
6442 (GET_MODE (SUBREG_REG (real_old)),
6444 real_old = SUBREG_REG (real_old), reloadreg = tem;
6446 gen_reload (reloadreg, second_reloadreg,
6447 rl->opnum, rl->when_needed);
6448 emit_insn ((GEN_FCN (tertiary_icode)
6449 (real_old, reloadreg, third_reloadreg)));
6454 /* Copy between the reload regs here and then to
6457 gen_reload (reloadreg, second_reloadreg,
6458 rl->opnum, rl->when_needed);
6464 /* Output the last reload insn. */
6469 /* Don't output the last reload if OLD is not the dest of
6470 INSN and is in the src and is clobbered by INSN. */
6471 if (! flag_expensive_optimizations
6472 || GET_CODE (old) != REG
6473 || !(set = single_set (insn))
6474 || rtx_equal_p (old, SET_DEST (set))
6475 || !reg_mentioned_p (old, SET_SRC (set))
6476 || !regno_clobbered_p (REGNO (old), insn))
6477 gen_reload (old, reloadreg, rl->opnum,
6481 /* Look at all insns we emitted, just to be safe. */
6482 for (p = get_insns (); p; p = NEXT_INSN (p))
6483 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6485 rtx pat = PATTERN (p);
6487 /* If this output reload doesn't come from a spill reg,
6488 clear any memory of reloaded copies of the pseudo reg.
6489 If this output reload comes from a spill reg,
6490 reg_has_output_reload will make this do nothing. */
6491 note_stores (pat, forget_old_reloads_1, NULL);
6493 if (reg_mentioned_p (rl->reg_rtx, pat))
6495 rtx set = single_set (insn);
6496 if (reload_spill_index[j] < 0
6498 && SET_SRC (set) == rl->reg_rtx)
6500 int src = REGNO (SET_SRC (set));
6502 reload_spill_index[j] = src;
6503 SET_HARD_REG_BIT (reg_is_output_reload, src);
6504 if (find_regno_note (insn, REG_DEAD, src))
6505 SET_HARD_REG_BIT (reg_reloaded_died, src);
6507 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6509 int s = rl->secondary_out_reload;
6510 set = single_set (p);
6511 /* If this reload copies only to the secondary reload
6512 register, the secondary reload does the actual
6514 if (s >= 0 && set == NULL_RTX)
6515 ; /* We can't tell what function the secondary reload
6516 has and where the actual store to the pseudo is
6517 made; leave new_spill_reg_store alone. */
6519 && SET_SRC (set) == rl->reg_rtx
6520 && SET_DEST (set) == rld[s].reg_rtx)
6522 /* Usually the next instruction will be the
6523 secondary reload insn; if we can confirm
6524 that it is, setting new_spill_reg_store to
6525 that insn will allow an extra optimization. */
6526 rtx s_reg = rld[s].reg_rtx;
6527 rtx next = NEXT_INSN (p);
6528 rld[s].out = rl->out;
6529 rld[s].out_reg = rl->out_reg;
6530 set = single_set (next);
6531 if (set && SET_SRC (set) == s_reg
6532 && ! new_spill_reg_store[REGNO (s_reg)])
6534 SET_HARD_REG_BIT (reg_is_output_reload,
6536 new_spill_reg_store[REGNO (s_reg)] = next;
6540 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6545 if (rl->when_needed == RELOAD_OTHER)
6547 emit_insns (other_output_reload_insns[rl->opnum]);
6548 other_output_reload_insns[rl->opnum] = get_insns ();
6551 output_reload_insns[rl->opnum] = get_insns ();
6556 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6557 and has the number J. */
6559 do_input_reload (chain, rl, j)
6560 struct insn_chain *chain;
6564 int expect_occurrences = 1;
6565 rtx insn = chain->insn;
6566 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6567 ? rl->in_reg : rl->in);
6570 /* AUTO_INC reloads need to be handled even if inherited. We got an
6571 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6572 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6573 && ! rtx_equal_p (rl->reg_rtx, old)
6574 && rl->reg_rtx != 0)
6576 emit_input_reload_insns (chain, rld + j, old, j);
6579 /* When inheriting a wider reload, we have a MEM in rl->in,
6580 e.g. inheriting a SImode output reload for
6581 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6582 if (optimize && reload_inherited[j] && rl->in
6583 && GET_CODE (rl->in) == MEM
6584 && GET_CODE (rl->in_reg) == MEM
6585 && reload_spill_index[j] >= 0
6586 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6589 = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1;
6591 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6594 /* If we are reloading a register that was recently stored in with an
6595 output-reload, see if we can prove there was
6596 actually no need to store the old value in it. */
6599 && (reload_inherited[j] || reload_override_in[j])
6601 && GET_CODE (rl->reg_rtx) == REG
6602 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6604 /* There doesn't seem to be any reason to restrict this to pseudos
6605 and doing so loses in the case where we are copying from a
6606 register of the wrong class. */
6607 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6608 >= FIRST_PSEUDO_REGISTER)
6610 /* The insn might have already some references to stackslots
6611 replaced by MEMs, while reload_out_reg still names the
6613 && (dead_or_set_p (insn,
6614 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6615 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6617 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6620 /* Do output reloading for reload RL, which is for the insn described by
6621 CHAIN and has the number J.
6622 ??? At some point we need to support handling output reloads of
6623 JUMP_INSNs or insns that set cc0. */
6625 do_output_reload (chain, rl, j)
6626 struct insn_chain *chain;
6631 rtx insn = chain->insn;
6632 /* If this is an output reload that stores something that is
6633 not loaded in this same reload, see if we can eliminate a previous
6635 rtx pseudo = rl->out_reg;
6638 && GET_CODE (pseudo) == REG
6639 && ! rtx_equal_p (rl->in_reg, pseudo)
6640 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6641 && reg_last_reload_reg[REGNO (pseudo)])
6643 int pseudo_no = REGNO (pseudo);
6644 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6646 /* We don't need to test full validity of last_regno for
6647 inherit here; we only want to know if the store actually
6648 matches the pseudo. */
6649 if (reg_reloaded_contents[last_regno] == pseudo_no
6650 && spill_reg_store[last_regno]
6651 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6652 delete_output_reload (insn, j, last_regno);
6657 || rl->reg_rtx == old
6658 || rl->reg_rtx == 0)
6661 /* An output operand that dies right away does need a reload,
6662 but need not be copied from it. Show the new location in the
6664 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6665 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6667 XEXP (note, 0) = rl->reg_rtx;
6670 /* Likewise for a SUBREG of an operand that dies. */
6671 else if (GET_CODE (old) == SUBREG
6672 && GET_CODE (SUBREG_REG (old)) == REG
6673 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6676 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6680 else if (GET_CODE (old) == SCRATCH)
6681 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6682 but we don't want to make an output reload. */
6685 /* If is a JUMP_INSN, we can't support output reloads yet. */
6686 if (GET_CODE (insn) == JUMP_INSN)
6689 emit_output_reload_insns (chain, rld + j, j);
6692 /* Output insns to reload values in and out of the chosen reload regs. */
6695 emit_reload_insns (chain)
6696 struct insn_chain *chain;
6698 rtx insn = chain->insn;
6701 rtx following_insn = NEXT_INSN (insn);
6702 rtx before_insn = PREV_INSN (insn);
6704 CLEAR_HARD_REG_SET (reg_reloaded_died);
6706 for (j = 0; j < reload_n_operands; j++)
6707 input_reload_insns[j] = input_address_reload_insns[j]
6708 = inpaddr_address_reload_insns[j]
6709 = output_reload_insns[j] = output_address_reload_insns[j]
6710 = outaddr_address_reload_insns[j]
6711 = other_output_reload_insns[j] = 0;
6712 other_input_address_reload_insns = 0;
6713 other_input_reload_insns = 0;
6714 operand_reload_insns = 0;
6715 other_operand_reload_insns = 0;
6717 /* Now output the instructions to copy the data into and out of the
6718 reload registers. Do these in the order that the reloads were reported,
6719 since reloads of base and index registers precede reloads of operands
6720 and the operands may need the base and index registers reloaded. */
6722 for (j = 0; j < n_reloads; j++)
6725 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6726 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6728 do_input_reload (chain, rld + j, j);
6729 do_output_reload (chain, rld + j, j);
6732 /* Now write all the insns we made for reloads in the order expected by
6733 the allocation functions. Prior to the insn being reloaded, we write
6734 the following reloads:
6736 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6738 RELOAD_OTHER reloads.
6740 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6741 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6742 RELOAD_FOR_INPUT reload for the operand.
6744 RELOAD_FOR_OPADDR_ADDRS reloads.
6746 RELOAD_FOR_OPERAND_ADDRESS reloads.
6748 After the insn being reloaded, we write the following:
6750 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6751 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6752 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6753 reloads for the operand. The RELOAD_OTHER output reloads are
6754 output in descending order by reload number. */
6756 emit_insns_before (other_input_address_reload_insns, insn);
6757 emit_insns_before (other_input_reload_insns, insn);
6759 for (j = 0; j < reload_n_operands; j++)
6761 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6762 emit_insns_before (input_address_reload_insns[j], insn);
6763 emit_insns_before (input_reload_insns[j], insn);
6766 emit_insns_before (other_operand_reload_insns, insn);
6767 emit_insns_before (operand_reload_insns, insn);
6769 for (j = 0; j < reload_n_operands; j++)
6771 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6772 emit_insns_before (output_address_reload_insns[j], following_insn);
6773 emit_insns_before (output_reload_insns[j], following_insn);
6774 emit_insns_before (other_output_reload_insns[j], following_insn);
6777 /* Keep basic block info up to date. */
6780 if (BLOCK_HEAD (chain->block) == insn)
6781 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6782 if (BLOCK_END (chain->block) == insn)
6783 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6786 /* For all the spill regs newly reloaded in this instruction,
6787 record what they were reloaded from, so subsequent instructions
6788 can inherit the reloads.
6790 Update spill_reg_store for the reloads of this insn.
6791 Copy the elements that were updated in the loop above. */
6793 for (j = 0; j < n_reloads; j++)
6795 register int r = reload_order[j];
6796 register int i = reload_spill_index[r];
6798 /* If this is a non-inherited input reload from a pseudo, we must
6799 clear any memory of a previous store to the same pseudo. Only do
6800 something if there will not be an output reload for the pseudo
6802 if (rld[r].in_reg != 0
6803 && ! (reload_inherited[r] || reload_override_in[r]))
6805 rtx reg = rld[r].in_reg;
6807 if (GET_CODE (reg) == SUBREG)
6808 reg = SUBREG_REG (reg);
6810 if (GET_CODE (reg) == REG
6811 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6812 && ! reg_has_output_reload[REGNO (reg)])
6814 int nregno = REGNO (reg);
6816 if (reg_last_reload_reg[nregno])
6818 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6820 if (reg_reloaded_contents[last_regno] == nregno)
6821 spill_reg_store[last_regno] = 0;
6826 /* I is nonneg if this reload used a register.
6827 If rld[r].reg_rtx is 0, this is an optional reload
6828 that we opted to ignore. */
6830 if (i >= 0 && rld[r].reg_rtx != 0)
6833 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6835 int part_reaches_end = 0;
6836 int all_reaches_end = 1;
6838 /* For a multi register reload, we need to check if all or part
6839 of the value lives to the end. */
6840 for (k = 0; k < nr; k++)
6842 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6843 rld[r].when_needed))
6844 part_reaches_end = 1;
6846 all_reaches_end = 0;
6849 /* Ignore reloads that don't reach the end of the insn in
6851 if (all_reaches_end)
6853 /* First, clear out memory of what used to be in this spill reg.
6854 If consecutive registers are used, clear them all. */
6856 for (k = 0; k < nr; k++)
6857 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6859 /* Maybe the spill reg contains a copy of reload_out. */
6861 && (GET_CODE (rld[r].out) == REG
6865 || GET_CODE (rld[r].out_reg) == REG))
6867 rtx out = (GET_CODE (rld[r].out) == REG
6871 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6872 register int nregno = REGNO (out);
6873 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6874 : HARD_REGNO_NREGS (nregno,
6875 GET_MODE (rld[r].reg_rtx)));
6877 spill_reg_store[i] = new_spill_reg_store[i];
6878 spill_reg_stored_to[i] = out;
6879 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6881 /* If NREGNO is a hard register, it may occupy more than
6882 one register. If it does, say what is in the
6883 rest of the registers assuming that both registers
6884 agree on how many words the object takes. If not,
6885 invalidate the subsequent registers. */
6887 if (nregno < FIRST_PSEUDO_REGISTER)
6888 for (k = 1; k < nnr; k++)
6889 reg_last_reload_reg[nregno + k]
6891 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6892 REGNO (rld[r].reg_rtx) + k)
6895 /* Now do the inverse operation. */
6896 for (k = 0; k < nr; k++)
6898 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6899 reg_reloaded_contents[i + k]
6900 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6903 reg_reloaded_insn[i + k] = insn;
6904 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6908 /* Maybe the spill reg contains a copy of reload_in. Only do
6909 something if there will not be an output reload for
6910 the register being reloaded. */
6911 else if (rld[r].out_reg == 0
6913 && ((GET_CODE (rld[r].in) == REG
6914 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6915 && ! reg_has_output_reload[REGNO (rld[r].in)])
6916 || (GET_CODE (rld[r].in_reg) == REG
6917 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6918 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6920 register int nregno;
6923 if (GET_CODE (rld[r].in) == REG
6924 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6925 nregno = REGNO (rld[r].in);
6926 else if (GET_CODE (rld[r].in_reg) == REG)
6927 nregno = REGNO (rld[r].in_reg);
6929 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6931 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6932 : HARD_REGNO_NREGS (nregno,
6933 GET_MODE (rld[r].reg_rtx)));
6935 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6937 if (nregno < FIRST_PSEUDO_REGISTER)
6938 for (k = 1; k < nnr; k++)
6939 reg_last_reload_reg[nregno + k]
6941 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6942 REGNO (rld[r].reg_rtx) + k)
6945 /* Unless we inherited this reload, show we haven't
6946 recently done a store.
6947 Previous stores of inherited auto_inc expressions
6948 also have to be discarded. */
6949 if (! reload_inherited[r]
6950 || (rld[r].out && ! rld[r].out_reg))
6951 spill_reg_store[i] = 0;
6953 for (k = 0; k < nr; k++)
6955 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6956 reg_reloaded_contents[i + k]
6957 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6960 reg_reloaded_insn[i + k] = insn;
6961 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6966 /* However, if part of the reload reaches the end, then we must
6967 invalidate the old info for the part that survives to the end. */
6968 else if (part_reaches_end)
6970 for (k = 0; k < nr; k++)
6971 if (reload_reg_reaches_end_p (i + k,
6973 rld[r].when_needed))
6974 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6978 /* The following if-statement was #if 0'd in 1.34 (or before...).
6979 It's reenabled in 1.35 because supposedly nothing else
6980 deals with this problem. */
6982 /* If a register gets output-reloaded from a non-spill register,
6983 that invalidates any previous reloaded copy of it.
6984 But forget_old_reloads_1 won't get to see it, because
6985 it thinks only about the original insn. So invalidate it here. */
6986 if (i < 0 && rld[r].out != 0
6987 && (GET_CODE (rld[r].out) == REG
6988 || (GET_CODE (rld[r].out) == MEM
6989 && GET_CODE (rld[r].out_reg) == REG)))
6991 rtx out = (GET_CODE (rld[r].out) == REG
6992 ? rld[r].out : rld[r].out_reg);
6993 register int nregno = REGNO (out);
6994 if (nregno >= FIRST_PSEUDO_REGISTER)
6996 rtx src_reg, store_insn = NULL_RTX;
6998 reg_last_reload_reg[nregno] = 0;
7000 /* If we can find a hard register that is stored, record
7001 the storing insn so that we may delete this insn with
7002 delete_output_reload. */
7003 src_reg = rld[r].reg_rtx;
7005 /* If this is an optional reload, try to find the source reg
7006 from an input reload. */
7009 rtx set = single_set (insn);
7010 if (set && SET_DEST (set) == rld[r].out)
7014 src_reg = SET_SRC (set);
7016 for (k = 0; k < n_reloads; k++)
7018 if (rld[k].in == src_reg)
7020 src_reg = rld[k].reg_rtx;
7027 store_insn = new_spill_reg_store[REGNO (src_reg)];
7028 if (src_reg && GET_CODE (src_reg) == REG
7029 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7031 int src_regno = REGNO (src_reg);
7032 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7033 /* The place where to find a death note varies with
7034 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7035 necessarily checked exactly in the code that moves
7036 notes, so just check both locations. */
7037 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7039 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7042 spill_reg_store[src_regno + nr] = store_insn;
7043 spill_reg_stored_to[src_regno + nr] = out;
7044 reg_reloaded_contents[src_regno + nr] = nregno;
7045 reg_reloaded_insn[src_regno + nr] = store_insn;
7046 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7047 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7048 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7050 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7052 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7054 reg_last_reload_reg[nregno] = src_reg;
7059 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7061 while (num_regs-- > 0)
7062 reg_last_reload_reg[nregno + num_regs] = 0;
7066 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7069 /* Emit code to perform a reload from IN (which may be a reload register) to
7070 OUT (which may also be a reload register). IN or OUT is from operand
7071 OPNUM with reload type TYPE.
7073 Returns first insn emitted. */
7076 gen_reload (out, in, opnum, type)
7080 enum reload_type type;
7082 rtx last = get_last_insn ();
7085 /* If IN is a paradoxical SUBREG, remove it and try to put the
7086 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7087 if (GET_CODE (in) == SUBREG
7088 && (GET_MODE_SIZE (GET_MODE (in))
7089 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7090 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7091 in = SUBREG_REG (in), out = tem;
7092 else if (GET_CODE (out) == SUBREG
7093 && (GET_MODE_SIZE (GET_MODE (out))
7094 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7095 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7096 out = SUBREG_REG (out), in = tem;
7098 /* How to do this reload can get quite tricky. Normally, we are being
7099 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7100 register that didn't get a hard register. In that case we can just
7101 call emit_move_insn.
7103 We can also be asked to reload a PLUS that adds a register or a MEM to
7104 another register, constant or MEM. This can occur during frame pointer
7105 elimination and while reloading addresses. This case is handled by
7106 trying to emit a single insn to perform the add. If it is not valid,
7107 we use a two insn sequence.
7109 Finally, we could be called to handle an 'o' constraint by putting
7110 an address into a register. In that case, we first try to do this
7111 with a named pattern of "reload_load_address". If no such pattern
7112 exists, we just emit a SET insn and hope for the best (it will normally
7113 be valid on machines that use 'o').
7115 This entire process is made complex because reload will never
7116 process the insns we generate here and so we must ensure that
7117 they will fit their constraints and also by the fact that parts of
7118 IN might be being reloaded separately and replaced with spill registers.
7119 Because of this, we are, in some sense, just guessing the right approach
7120 here. The one listed above seems to work.
7122 ??? At some point, this whole thing needs to be rethought. */
7124 if (GET_CODE (in) == PLUS
7125 && (GET_CODE (XEXP (in, 0)) == REG
7126 || GET_CODE (XEXP (in, 0)) == SUBREG
7127 || GET_CODE (XEXP (in, 0)) == MEM)
7128 && (GET_CODE (XEXP (in, 1)) == REG
7129 || GET_CODE (XEXP (in, 1)) == SUBREG
7130 || CONSTANT_P (XEXP (in, 1))
7131 || GET_CODE (XEXP (in, 1)) == MEM))
7133 /* We need to compute the sum of a register or a MEM and another
7134 register, constant, or MEM, and put it into the reload
7135 register. The best possible way of doing this is if the machine
7136 has a three-operand ADD insn that accepts the required operands.
7138 The simplest approach is to try to generate such an insn and see if it
7139 is recognized and matches its constraints. If so, it can be used.
7141 It might be better not to actually emit the insn unless it is valid,
7142 but we need to pass the insn as an operand to `recog' and
7143 `extract_insn' and it is simpler to emit and then delete the insn if
7144 not valid than to dummy things up. */
7146 rtx op0, op1, tem, insn;
7149 op0 = find_replacement (&XEXP (in, 0));
7150 op1 = find_replacement (&XEXP (in, 1));
7152 /* Since constraint checking is strict, commutativity won't be
7153 checked, so we need to do that here to avoid spurious failure
7154 if the add instruction is two-address and the second operand
7155 of the add is the same as the reload reg, which is frequently
7156 the case. If the insn would be A = B + A, rearrange it so
7157 it will be A = A + B as constrain_operands expects. */
7159 if (GET_CODE (XEXP (in, 1)) == REG
7160 && REGNO (out) == REGNO (XEXP (in, 1)))
7161 tem = op0, op0 = op1, op1 = tem;
7163 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7164 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7166 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7167 code = recog_memoized (insn);
7171 extract_insn (insn);
7172 /* We want constrain operands to treat this insn strictly in
7173 its validity determination, i.e., the way it would after reload
7175 if (constrain_operands (1))
7179 delete_insns_since (last);
7181 /* If that failed, we must use a conservative two-insn sequence.
7183 Use a move to copy one operand into the reload register. Prefer
7184 to reload a constant, MEM or pseudo since the move patterns can
7185 handle an arbitrary operand. If OP1 is not a constant, MEM or
7186 pseudo and OP1 is not a valid operand for an add instruction, then
7189 After reloading one of the operands into the reload register, add
7190 the reload register to the output register.
7192 If there is another way to do this for a specific machine, a
7193 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7196 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7198 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7199 || (GET_CODE (op1) == REG
7200 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7201 || (code != CODE_FOR_nothing
7202 && ! ((*insn_data[code].operand[2].predicate)
7203 (op1, insn_data[code].operand[2].mode))))
7204 tem = op0, op0 = op1, op1 = tem;
7206 gen_reload (out, op0, opnum, type);
7208 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7209 This fixes a problem on the 32K where the stack pointer cannot
7210 be used as an operand of an add insn. */
7212 if (rtx_equal_p (op0, op1))
7215 insn = emit_insn (gen_add2_insn (out, op1));
7217 /* If that failed, copy the address register to the reload register.
7218 Then add the constant to the reload register. */
7220 code = recog_memoized (insn);
7224 extract_insn (insn);
7225 /* We want constrain operands to treat this insn strictly in
7226 its validity determination, i.e., the way it would after reload
7228 if (constrain_operands (1))
7230 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7232 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7237 delete_insns_since (last);
7239 gen_reload (out, op1, opnum, type);
7240 insn = emit_insn (gen_add2_insn (out, op0));
7241 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7244 #ifdef SECONDARY_MEMORY_NEEDED
7245 /* If we need a memory location to do the move, do it that way. */
7246 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7247 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7248 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7249 REGNO_REG_CLASS (REGNO (out)),
7252 /* Get the memory to use and rewrite both registers to its mode. */
7253 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7255 if (GET_MODE (loc) != GET_MODE (out))
7256 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7258 if (GET_MODE (loc) != GET_MODE (in))
7259 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7261 gen_reload (loc, in, opnum, type);
7262 gen_reload (out, loc, opnum, type);
7266 /* If IN is a simple operand, use gen_move_insn. */
7267 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7268 emit_insn (gen_move_insn (out, in));
7270 #ifdef HAVE_reload_load_address
7271 else if (HAVE_reload_load_address)
7272 emit_insn (gen_reload_load_address (out, in));
7275 /* Otherwise, just write (set OUT IN) and hope for the best. */
7277 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7279 /* Return the first insn emitted.
7280 We can not just return get_last_insn, because there may have
7281 been multiple instructions emitted. Also note that gen_move_insn may
7282 emit more than one insn itself, so we can not assume that there is one
7283 insn emitted per emit_insn_before call. */
7285 return last ? NEXT_INSN (last) : get_insns ();
7288 /* Delete a previously made output-reload
7289 whose result we now believe is not needed.
7290 First we double-check.
7292 INSN is the insn now being processed.
7293 LAST_RELOAD_REG is the hard register number for which we want to delete
7294 the last output reload.
7295 J is the reload-number that originally used REG. The caller has made
7296 certain that reload J doesn't use REG any longer for input. */
7299 delete_output_reload (insn, j, last_reload_reg)
7302 int last_reload_reg;
7304 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7305 rtx reg = spill_reg_stored_to[last_reload_reg];
7308 int n_inherited = 0;
7312 /* Get the raw pseudo-register referred to. */
7314 while (GET_CODE (reg) == SUBREG)
7315 reg = SUBREG_REG (reg);
7316 substed = reg_equiv_memory_loc[REGNO (reg)];
7318 /* This is unsafe if the operand occurs more often in the current
7319 insn than it is inherited. */
7320 for (k = n_reloads - 1; k >= 0; k--)
7322 rtx reg2 = rld[k].in;
7325 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7326 reg2 = rld[k].in_reg;
7328 if (rld[k].out && ! rld[k].out_reg)
7329 reg2 = XEXP (rld[k].in_reg, 0);
7331 while (GET_CODE (reg2) == SUBREG)
7332 reg2 = SUBREG_REG (reg2);
7333 if (rtx_equal_p (reg2, reg))
7335 if (reload_inherited[k] || reload_override_in[k] || k == j)
7338 reg2 = rld[k].out_reg;
7341 while (GET_CODE (reg2) == SUBREG)
7342 reg2 = XEXP (reg2, 0);
7343 if (rtx_equal_p (reg2, reg))
7350 n_occurrences = count_occurrences (PATTERN (insn), reg);
7352 n_occurrences += count_occurrences (PATTERN (insn), substed);
7353 if (n_occurrences > n_inherited)
7356 /* If the pseudo-reg we are reloading is no longer referenced
7357 anywhere between the store into it and here,
7358 and no jumps or labels intervene, then the value can get
7359 here through the reload reg alone.
7360 Otherwise, give up--return. */
7361 for (i1 = NEXT_INSN (output_reload_insn);
7362 i1 != insn; i1 = NEXT_INSN (i1))
7364 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7366 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7367 && reg_mentioned_p (reg, PATTERN (i1)))
7369 /* If this is USE in front of INSN, we only have to check that
7370 there are no more references than accounted for by inheritance. */
7371 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7373 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7374 i1 = NEXT_INSN (i1);
7376 if (n_occurrences <= n_inherited && i1 == insn)
7382 /* The caller has already checked that REG dies or is set in INSN.
7383 It has also checked that we are optimizing, and thus some inaccurancies
7384 in the debugging information are acceptable.
7385 So we could just delete output_reload_insn.
7386 But in some cases we can improve the debugging information without
7387 sacrificing optimization - maybe even improving the code:
7388 See if the pseudo reg has been completely replaced
7389 with reload regs. If so, delete the store insn
7390 and forget we had a stack slot for the pseudo. */
7391 if (rld[j].out != rld[j].in
7392 && REG_N_DEATHS (REGNO (reg)) == 1
7393 && REG_N_SETS (REGNO (reg)) == 1
7394 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7395 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7399 /* We know that it was used only between here
7400 and the beginning of the current basic block.
7401 (We also know that the last use before INSN was
7402 the output reload we are thinking of deleting, but never mind that.)
7403 Search that range; see if any ref remains. */
7404 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7406 rtx set = single_set (i2);
7408 /* Uses which just store in the pseudo don't count,
7409 since if they are the only uses, they are dead. */
7410 if (set != 0 && SET_DEST (set) == reg)
7412 if (GET_CODE (i2) == CODE_LABEL
7413 || GET_CODE (i2) == JUMP_INSN)
7415 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7416 && reg_mentioned_p (reg, PATTERN (i2)))
7418 /* Some other ref remains; just delete the output reload we
7420 delete_address_reloads (output_reload_insn, insn);
7421 PUT_CODE (output_reload_insn, NOTE);
7422 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7423 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7428 /* Delete the now-dead stores into this pseudo. */
7429 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7431 rtx set = single_set (i2);
7433 if (set != 0 && SET_DEST (set) == reg)
7435 delete_address_reloads (i2, insn);
7436 /* This might be a basic block head,
7437 thus don't use delete_insn. */
7438 PUT_CODE (i2, NOTE);
7439 NOTE_SOURCE_FILE (i2) = 0;
7440 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7442 if (GET_CODE (i2) == CODE_LABEL
7443 || GET_CODE (i2) == JUMP_INSN)
7447 /* For the debugging info,
7448 say the pseudo lives in this reload reg. */
7449 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7450 alter_reg (REGNO (reg), -1);
7452 delete_address_reloads (output_reload_insn, insn);
7453 PUT_CODE (output_reload_insn, NOTE);
7454 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7455 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7459 /* We are going to delete DEAD_INSN. Recursively delete loads of
7460 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7461 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7463 delete_address_reloads (dead_insn, current_insn)
7464 rtx dead_insn, current_insn;
7466 rtx set = single_set (dead_insn);
7467 rtx set2, dst, prev, next;
7470 rtx dst = SET_DEST (set);
7471 if (GET_CODE (dst) == MEM)
7472 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7474 /* If we deleted the store from a reloaded post_{in,de}c expression,
7475 we can delete the matching adds. */
7476 prev = PREV_INSN (dead_insn);
7477 next = NEXT_INSN (dead_insn);
7478 if (! prev || ! next)
7480 set = single_set (next);
7481 set2 = single_set (prev);
7483 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7484 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7485 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7487 dst = SET_DEST (set);
7488 if (! rtx_equal_p (dst, SET_DEST (set2))
7489 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7490 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7491 || (INTVAL (XEXP (SET_SRC (set), 1))
7492 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7498 /* Subfunction of delete_address_reloads: process registers found in X. */
7500 delete_address_reloads_1 (dead_insn, x, current_insn)
7501 rtx dead_insn, x, current_insn;
7503 rtx prev, set, dst, i2;
7505 enum rtx_code code = GET_CODE (x);
7509 const char *fmt= GET_RTX_FORMAT (code);
7510 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7513 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7514 else if (fmt[i] == 'E')
7516 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7517 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7524 if (spill_reg_order[REGNO (x)] < 0)
7527 /* Scan backwards for the insn that sets x. This might be a way back due
7529 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7531 code = GET_CODE (prev);
7532 if (code == CODE_LABEL || code == JUMP_INSN)
7534 if (GET_RTX_CLASS (code) != 'i')
7536 if (reg_set_p (x, PATTERN (prev)))
7538 if (reg_referenced_p (x, PATTERN (prev)))
7541 if (! prev || INSN_UID (prev) < reload_first_uid)
7543 /* Check that PREV only sets the reload register. */
7544 set = single_set (prev);
7547 dst = SET_DEST (set);
7548 if (GET_CODE (dst) != REG
7549 || ! rtx_equal_p (dst, x))
7551 if (! reg_set_p (dst, PATTERN (dead_insn)))
7553 /* Check if DST was used in a later insn -
7554 it might have been inherited. */
7555 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7557 if (GET_CODE (i2) == CODE_LABEL)
7559 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7561 if (reg_referenced_p (dst, PATTERN (i2)))
7563 /* If there is a reference to the register in the current insn,
7564 it might be loaded in a non-inherited reload. If no other
7565 reload uses it, that means the register is set before
7567 if (i2 == current_insn)
7569 for (j = n_reloads - 1; j >= 0; j--)
7570 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7571 || reload_override_in[j] == dst)
7573 for (j = n_reloads - 1; j >= 0; j--)
7574 if (rld[j].in && rld[j].reg_rtx == dst)
7581 if (GET_CODE (i2) == JUMP_INSN)
7583 /* If DST is still live at CURRENT_INSN, check if it is used for
7584 any reload. Note that even if CURRENT_INSN sets DST, we still
7585 have to check the reloads. */
7586 if (i2 == current_insn)
7588 for (j = n_reloads - 1; j >= 0; j--)
7589 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7590 || reload_override_in[j] == dst)
7592 /* ??? We can't finish the loop here, because dst might be
7593 allocated to a pseudo in this block if no reload in this
7594 block needs any of the clsses containing DST - see
7595 spill_hard_reg. There is no easy way to tell this, so we
7596 have to scan till the end of the basic block. */
7598 if (reg_set_p (dst, PATTERN (i2)))
7602 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7603 reg_reloaded_contents[REGNO (dst)] = -1;
7604 /* Can't use delete_insn here because PREV might be a basic block head. */
7605 PUT_CODE (prev, NOTE);
7606 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7607 NOTE_SOURCE_FILE (prev) = 0;
7610 /* Output reload-insns to reload VALUE into RELOADREG.
7611 VALUE is an autoincrement or autodecrement RTX whose operand
7612 is a register or memory location;
7613 so reloading involves incrementing that location.
7614 IN is either identical to VALUE, or some cheaper place to reload from.
7616 INC_AMOUNT is the number to increment or decrement by (always positive).
7617 This cannot be deduced from VALUE.
7619 Return the instruction that stores into RELOADREG. */
7622 inc_for_reload (reloadreg, in, value, inc_amount)
7627 /* REG or MEM to be copied and incremented. */
7628 rtx incloc = XEXP (value, 0);
7629 /* Nonzero if increment after copying. */
7630 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7636 rtx real_in = in == value ? XEXP (in, 0) : in;
7638 /* No hard register is equivalent to this register after
7639 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7640 we could inc/dec that register as well (maybe even using it for
7641 the source), but I'm not sure it's worth worrying about. */
7642 if (GET_CODE (incloc) == REG)
7643 reg_last_reload_reg[REGNO (incloc)] = 0;
7645 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7646 inc_amount = - inc_amount;
7648 inc = GEN_INT (inc_amount);
7650 /* If this is post-increment, first copy the location to the reload reg. */
7651 if (post && real_in != reloadreg)
7652 emit_insn (gen_move_insn (reloadreg, real_in));
7656 /* See if we can directly increment INCLOC. Use a method similar to
7657 that in gen_reload. */
7659 last = get_last_insn ();
7660 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7661 gen_rtx_PLUS (GET_MODE (incloc),
7664 code = recog_memoized (add_insn);
7667 extract_insn (add_insn);
7668 if (constrain_operands (1))
7670 /* If this is a pre-increment and we have incremented the value
7671 where it lives, copy the incremented value to RELOADREG to
7672 be used as an address. */
7675 emit_insn (gen_move_insn (reloadreg, incloc));
7680 delete_insns_since (last);
7683 /* If couldn't do the increment directly, must increment in RELOADREG.
7684 The way we do this depends on whether this is pre- or post-increment.
7685 For pre-increment, copy INCLOC to the reload register, increment it
7686 there, then save back. */
7690 if (in != reloadreg)
7691 emit_insn (gen_move_insn (reloadreg, real_in));
7692 emit_insn (gen_add2_insn (reloadreg, inc));
7693 store = emit_insn (gen_move_insn (incloc, reloadreg));
7698 Because this might be a jump insn or a compare, and because RELOADREG
7699 may not be available after the insn in an input reload, we must do
7700 the incrementation before the insn being reloaded for.
7702 We have already copied IN to RELOADREG. Increment the copy in
7703 RELOADREG, save that back, then decrement RELOADREG so it has
7704 the original value. */
7706 emit_insn (gen_add2_insn (reloadreg, inc));
7707 store = emit_insn (gen_move_insn (incloc, reloadreg));
7708 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7714 /* Return 1 if we are certain that the constraint-string STRING allows
7715 the hard register REG. Return 0 if we can't be sure of this. */
7718 constraint_accepts_reg_p (string, reg)
7723 int regno = true_regnum (reg);
7726 /* Initialize for first alternative. */
7728 /* Check that each alternative contains `g' or `r'. */
7730 switch (c = *string++)
7733 /* If an alternative lacks `g' or `r', we lose. */
7736 /* If an alternative lacks `g' or `r', we lose. */
7739 /* Initialize for next alternative. */
7744 /* Any general reg wins for this alternative. */
7745 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7749 /* Any reg in specified class wins for this alternative. */
7751 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7753 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7759 /* Return the number of places FIND appears within X, but don't count
7760 an occurrence if some SET_DEST is FIND. */
7763 count_occurrences (x, find)
7764 register rtx x, find;
7767 register enum rtx_code code;
7768 register const char *format_ptr;
7776 code = GET_CODE (x);
7791 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
7795 if (SET_DEST (x) == find)
7796 return count_occurrences (SET_SRC (x), find);
7803 format_ptr = GET_RTX_FORMAT (code);
7806 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7808 switch (*format_ptr++)
7811 count += count_occurrences (XEXP (x, i), find);
7815 if (XVEC (x, i) != NULL)
7817 for (j = 0; j < XVECLEN (x, i); j++)
7818 count += count_occurrences (XVECEXP (x, i, j), find);
7826 /* This array holds values which are equivalent to a hard register
7827 during reload_cse_regs. Each array element is an EXPR_LIST of
7828 values. Each time a hard register is set, we set the corresponding
7829 array element to the value. Each time a hard register is copied
7830 into memory, we add the memory location to the corresponding array
7831 element. We don't store values or memory addresses with side
7832 effects in this array.
7834 If the value is a CONST_INT, then the mode of the containing
7835 EXPR_LIST is the mode in which that CONST_INT was referenced.
7837 We sometimes clobber a specific entry in a list. In that case, we
7838 just set XEXP (list-entry, 0) to 0. */
7840 static rtx *reg_values;
7842 /* This is a preallocated REG rtx which we use as a temporary in
7843 reload_cse_invalidate_regno, so that we don't need to allocate a
7844 new one each time through a loop in that function. */
7846 static rtx invalidate_regno_rtx;
7848 /* Invalidate any entries in reg_values which depend on REGNO,
7849 including those for REGNO itself. This is called if REGNO is
7850 changing. If CLOBBER is true, then always forget anything we
7851 currently know about REGNO. MODE is the mode of the assignment to
7852 REGNO, which is used to determine how many hard registers are being
7853 changed. If MODE is VOIDmode, then only REGNO is being changed;
7854 this is used when invalidating call clobbered registers across a
7858 reload_cse_invalidate_regno (regno, mode, clobber)
7860 enum machine_mode mode;
7866 /* Our callers don't always go through true_regnum; we may see a
7867 pseudo-register here from a CLOBBER or the like. We probably
7868 won't ever see a pseudo-register that has a real register number,
7869 for we check anyhow for safety. */
7870 if (regno >= FIRST_PSEUDO_REGISTER)
7871 regno = reg_renumber[regno];
7875 if (mode == VOIDmode)
7876 endregno = regno + 1;
7878 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7881 for (i = regno; i < endregno; i++)
7884 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7888 for (x = reg_values[i]; x; x = XEXP (x, 1))
7890 if (XEXP (x, 0) != 0
7891 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7893 /* If this is the only entry on the list, clear
7894 reg_values[i]. Otherwise, just clear this entry on
7896 if (XEXP (x, 1) == 0 && x == reg_values[i])
7906 /* We must look at earlier registers, in case REGNO is part of a
7907 multi word value but is not the first register. If an earlier
7908 register has a value in a mode which overlaps REGNO, then we must
7909 invalidate that earlier register. Note that we do not need to
7910 check REGNO or later registers (we must not check REGNO itself,
7911 because we would incorrectly conclude that there was a conflict). */
7913 for (i = 0; i < regno; i++)
7917 for (x = reg_values[i]; x; x = XEXP (x, 1))
7919 if (XEXP (x, 0) != 0)
7921 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
7922 REGNO (invalidate_regno_rtx) = i;
7923 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7926 reload_cse_invalidate_regno (i, VOIDmode, 1);
7934 /* The memory at address MEM_BASE is being changed.
7935 Return whether this change will invalidate VAL. */
7938 reload_cse_mem_conflict_p (mem_base, val)
7946 code = GET_CODE (val);
7949 /* Get rid of a few simple cases quickly. */
7962 if (GET_MODE (mem_base) == BLKmode
7963 || GET_MODE (val) == BLKmode)
7965 if (anti_dependence (val, mem_base))
7967 /* The address may contain nested MEMs. */
7974 fmt = GET_RTX_FORMAT (code);
7976 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7980 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
7983 else if (fmt[i] == 'E')
7987 for (j = 0; j < XVECLEN (val, i); j++)
7988 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
7996 /* Invalidate any entries in reg_values which are changed because of a
7997 store to MEM_RTX. If this is called because of a non-const call
7998 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8001 reload_cse_invalidate_mem (mem_rtx)
8006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8010 for (x = reg_values[i]; x; x = XEXP (x, 1))
8012 if (XEXP (x, 0) != 0
8013 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8015 /* If this is the only entry on the list, clear
8016 reg_values[i]. Otherwise, just clear this entry on
8018 if (XEXP (x, 1) == 0 && x == reg_values[i])
8029 /* Invalidate DEST, which is being assigned to or clobbered. The
8030 second parameter exists so that this function can be passed to
8031 note_stores; it is ignored. */
8034 reload_cse_invalidate_rtx (dest, ignore, data)
8036 rtx ignore ATTRIBUTE_UNUSED;
8037 void *data ATTRIBUTE_UNUSED;
8039 while (GET_CODE (dest) == STRICT_LOW_PART
8040 || GET_CODE (dest) == SIGN_EXTRACT
8041 || GET_CODE (dest) == ZERO_EXTRACT
8042 || GET_CODE (dest) == SUBREG)
8043 dest = XEXP (dest, 0);
8045 if (GET_CODE (dest) == REG)
8046 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8047 else if (GET_CODE (dest) == MEM)
8048 reload_cse_invalidate_mem (dest);
8051 /* Do a very simple CSE pass over the hard registers.
8053 This function detects no-op moves where we happened to assign two
8054 different pseudo-registers to the same hard register, and then
8055 copied one to the other. Reload will generate a useless
8056 instruction copying a register to itself.
8058 This function also detects cases where we load a value from memory
8059 into two different registers, and (if memory is more expensive than
8060 registers) changes it to simply copy the first register into the
8063 Another optimization is performed that scans the operands of each
8064 instruction to see whether the value is already available in a
8065 hard register. It then replaces the operand with the hard register
8066 if possible, much like an optional reload would. */
8069 reload_cse_regs_1 (first)
8077 init_alias_analysis ();
8079 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8080 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8082 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8083 free them when we are done. */
8084 push_obstacks (&reload_obstack, &reload_obstack);
8085 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8087 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8088 memory for a non-const call instruction. */
8089 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8091 /* This is used in reload_cse_invalidate_regno to avoid consing a
8092 new REG in a loop in that function. */
8093 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8095 for (insn = first; insn; insn = NEXT_INSN (insn))
8099 if (GET_CODE (insn) == CODE_LABEL)
8101 /* Forget all the register values at a code label. We don't
8102 try to do anything clever around jumps. */
8103 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8109 #ifdef NON_SAVING_SETJMP
8110 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8111 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8113 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8120 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8123 /* If this is a call instruction, forget anything stored in a
8124 call clobbered register, or, if this is not a const call, in
8126 if (GET_CODE (insn) == CALL_INSN)
8128 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8129 if (call_used_regs[i])
8130 reload_cse_invalidate_regno (i, VOIDmode, 1);
8132 if (! CONST_CALL_P (insn))
8133 reload_cse_invalidate_mem (callmem);
8137 /* Forget all the register values at a volatile asm. */
8138 if (GET_CODE (insn) == INSN
8139 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8140 && MEM_VOLATILE_P (PATTERN (insn)))
8141 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8144 body = PATTERN (insn);
8145 if (GET_CODE (body) == SET)
8148 if (reload_cse_noop_set_p (body, insn))
8150 /* If this sets the return value of the function, we must keep
8151 a USE around, in case this is in a different basic block
8152 than the final USE. Otherwise, we could loose important
8153 register lifeness information on SMALL_REGISTER_CLASSES
8154 machines, where return registers might be used as spills:
8155 subsequent passes assume that spill registers are dead at
8156 the end of a basic block. */
8157 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8160 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8161 INSN_CODE (insn) = -1;
8162 REG_NOTES (insn) = NULL_RTX;
8163 push_obstacks (&reload_obstack, &reload_obstack);
8167 PUT_CODE (insn, NOTE);
8168 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8169 NOTE_SOURCE_FILE (insn) = 0;
8172 /* We're done with this insn. */
8176 /* It's not a no-op, but we can try to simplify it. */
8177 count += reload_cse_simplify_set (body, insn);
8180 apply_change_group ();
8182 reload_cse_simplify_operands (insn);
8184 reload_cse_record_set (body, body);
8186 else if (GET_CODE (body) == PARALLEL)
8189 rtx value = NULL_RTX;
8191 /* If every action in a PARALLEL is a noop, we can delete
8192 the entire PARALLEL. */
8193 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8195 rtx part = XVECEXP (body, 0, i);
8196 if (GET_CODE (part) == SET)
8198 if (! reload_cse_noop_set_p (part, insn))
8200 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8204 value = SET_DEST (part);
8207 else if (GET_CODE (part) != CLOBBER)
8215 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8216 INSN_CODE (insn) = -1;
8217 REG_NOTES (insn) = NULL_RTX;
8218 push_obstacks (&reload_obstack, &reload_obstack);
8222 PUT_CODE (insn, NOTE);
8223 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8224 NOTE_SOURCE_FILE (insn) = 0;
8227 /* We're done with this insn. */
8231 /* It's not a no-op, but we can try to simplify it. */
8232 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8233 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8234 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8237 apply_change_group ();
8239 reload_cse_simplify_operands (insn);
8241 /* Look through the PARALLEL and record the values being
8242 set, if possible. Also handle any CLOBBERs. */
8243 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8245 rtx x = XVECEXP (body, 0, i);
8247 if (GET_CODE (x) == SET)
8248 reload_cse_record_set (x, body);
8250 note_stores (x, reload_cse_invalidate_rtx, NULL);
8254 note_stores (body, reload_cse_invalidate_rtx, NULL);
8257 /* Clobber any registers which appear in REG_INC notes. We
8258 could keep track of the changes to their values, but it is
8259 unlikely to help. */
8263 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8264 if (REG_NOTE_KIND (x) == REG_INC)
8265 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL);
8269 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8270 after we have processed the insn. */
8271 if (GET_CODE (insn) == CALL_INSN)
8275 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8276 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8277 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX,
8283 end_alias_analysis ();
8285 /* Free all the temporary structures we created, and go back to the
8286 regular obstacks. */
8287 obstack_free (&reload_obstack, firstobj);
8291 /* Call cse / combine like post-reload optimization phases.
8292 FIRST is the first instruction. */
8294 reload_cse_regs (first)
8297 reload_cse_regs_1 (first);
8299 reload_cse_move2add (first);
8300 if (flag_expensive_optimizations)
8301 reload_cse_regs_1 (first);
8304 /* Return whether the values known for REGNO are equal to VAL. MODE
8305 is the mode of the object that VAL is being copied to; this matters
8306 if VAL is a CONST_INT. */
8309 reload_cse_regno_equal_p (regno, val, mode)
8312 enum machine_mode mode;
8319 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8320 if (XEXP (x, 0) != 0
8321 && rtx_equal_p (XEXP (x, 0), val)
8322 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8323 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8324 && (GET_CODE (val) != CONST_INT
8325 || mode == GET_MODE (x)
8326 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8327 /* On a big endian machine if the value spans more than
8328 one register then this register holds the high part of
8329 it and we can't use it.
8331 ??? We should also compare with the high part of the
8333 && !(WORDS_BIG_ENDIAN
8334 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8335 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8336 GET_MODE_BITSIZE (GET_MODE (x))))))
8342 /* See whether a single set is a noop. SET is the set instruction we
8343 are should check, and INSN is the instruction from which it came. */
8346 reload_cse_noop_set_p (set, insn)
8348 rtx insn ATTRIBUTE_UNUSED;
8351 enum machine_mode dest_mode;
8355 src = SET_SRC (set);
8356 dest = SET_DEST (set);
8357 dest_mode = GET_MODE (dest);
8359 if (side_effects_p (src))
8362 dreg = true_regnum (dest);
8363 sreg = true_regnum (src);
8365 /* Check for setting a register to itself. In this case, we don't
8366 have to worry about REG_DEAD notes. */
8367 if (dreg >= 0 && dreg == sreg)
8373 /* Check for setting a register to itself. */
8377 /* Check for setting a register to a value which we already know
8378 is in the register. */
8379 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8382 /* Check for setting a register DREG to another register SREG
8383 where SREG is equal to a value which is already in DREG. */
8388 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8392 if (XEXP (x, 0) == 0)
8395 if (dest_mode == GET_MODE (x))
8397 else if (GET_MODE_BITSIZE (dest_mode)
8398 < GET_MODE_BITSIZE (GET_MODE (x)))
8399 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8404 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8412 else if (GET_CODE (dest) == MEM)
8414 /* Check for storing a register to memory when we know that the
8415 register is equivalent to the memory location. */
8417 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8418 && ! side_effects_p (dest))
8425 /* Try to simplify a single SET instruction. SET is the set pattern.
8426 INSN is the instruction it came from.
8427 This function only handles one case: if we set a register to a value
8428 which is not a register, we try to find that value in some other register
8429 and change the set into a register copy. */
8432 reload_cse_simplify_set (set, insn)
8438 enum machine_mode dest_mode;
8439 enum reg_class dclass;
8442 dreg = true_regnum (SET_DEST (set));
8446 src = SET_SRC (set);
8447 if (side_effects_p (src) || true_regnum (src) >= 0)
8450 dclass = REGNO_REG_CLASS (dreg);
8452 /* If memory loads are cheaper than register copies, don't change them. */
8453 if (GET_CODE (src) == MEM
8454 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8457 /* If the constant is cheaper than a register, don't change it. */
8458 if (CONSTANT_P (src)
8459 && rtx_cost (src, SET) < 2)
8462 dest_mode = GET_MODE (SET_DEST (set));
8463 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8466 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8467 && reload_cse_regno_equal_p (i, src, dest_mode))
8471 /* Pop back to the real obstacks while changing the insn. */
8474 validated = validate_change (insn, &SET_SRC (set),
8475 gen_rtx_REG (dest_mode, i), 1);
8477 /* Go back to the obstack we are using for temporary
8479 push_obstacks (&reload_obstack, &reload_obstack);
8488 /* Try to replace operands in INSN with equivalent values that are already
8489 in registers. This can be viewed as optional reloading.
8491 For each non-register operand in the insn, see if any hard regs are
8492 known to be equivalent to that operand. Record the alternatives which
8493 can accept these hard registers. Among all alternatives, select the
8494 ones which are better or equal to the one currently matching, where
8495 "better" is in terms of '?' and '!' constraints. Among the remaining
8496 alternatives, select the one which replaces most operands with
8500 reload_cse_simplify_operands (insn)
8505 const char *constraints[MAX_RECOG_OPERANDS];
8507 /* Vector recording how bad an alternative is. */
8508 int *alternative_reject;
8509 /* Vector recording how many registers can be introduced by choosing
8510 this alternative. */
8511 int *alternative_nregs;
8512 /* Array of vectors recording, for each operand and each alternative,
8513 which hard register to substitute, or -1 if the operand should be
8515 int *op_alt_regno[MAX_RECOG_OPERANDS];
8516 /* Array of alternatives, sorted in order of decreasing desirability. */
8517 int *alternative_order;
8518 rtx reg = gen_rtx_REG (VOIDmode, -1);
8520 extract_insn (insn);
8522 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8525 /* Figure out which alternative currently matches. */
8526 if (! constrain_operands (1))
8527 fatal_insn_not_found (insn);
8529 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8530 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8531 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8532 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8533 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8535 for (i = 0; i < recog_data.n_operands; i++)
8537 enum machine_mode mode;
8541 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8542 for (j = 0; j < recog_data.n_alternatives; j++)
8543 op_alt_regno[i][j] = -1;
8545 p = constraints[i] = recog_data.constraints[i];
8546 mode = recog_data.operand_mode[i];
8548 /* Add the reject values for each alternative given by the constraints
8549 for this operand. */
8557 alternative_reject[j] += 3;
8559 alternative_reject[j] += 300;
8562 /* We won't change operands which are already registers. We
8563 also don't want to modify output operands. */
8564 regno = true_regnum (recog_data.operand[i]);
8566 || constraints[i][0] == '='
8567 || constraints[i][0] == '+')
8570 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8572 int class = (int) NO_REGS;
8574 if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
8577 REGNO (reg) = regno;
8578 PUT_MODE (reg, mode);
8580 /* We found a register equal to this operand. Now look for all
8581 alternatives that can accept this register and have not been
8582 assigned a register they can use yet. */
8591 case '=': case '+': case '?':
8592 case '#': case '&': case '!':
8594 case '0': case '1': case '2': case '3': case '4':
8595 case '5': case '6': case '7': case '8': case '9':
8596 case 'm': case '<': case '>': case 'V': case 'o':
8597 case 'E': case 'F': case 'G': case 'H':
8598 case 's': case 'i': case 'n':
8599 case 'I': case 'J': case 'K': case 'L':
8600 case 'M': case 'N': case 'O': case 'P':
8601 #ifdef EXTRA_CONSTRAINT
8602 case 'Q': case 'R': case 'S': case 'T': case 'U':
8605 /* These don't say anything we care about. */
8609 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8614 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8617 case ',': case '\0':
8618 /* See if REGNO fits this alternative, and set it up as the
8619 replacement register if we don't have one for this
8620 alternative yet and the operand being replaced is not
8621 a cheap CONST_INT. */
8622 if (op_alt_regno[i][j] == -1
8623 && reg_fits_class_p (reg, class, 0, mode)
8624 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8625 || (rtx_cost (recog_data.operand[i], SET)
8626 > rtx_cost (reg, SET))))
8628 alternative_nregs[j]++;
8629 op_alt_regno[i][j] = regno;
8641 /* Record all alternatives which are better or equal to the currently
8642 matching one in the alternative_order array. */
8643 for (i = j = 0; i < recog_data.n_alternatives; i++)
8644 if (alternative_reject[i] <= alternative_reject[which_alternative])
8645 alternative_order[j++] = i;
8646 recog_data.n_alternatives = j;
8648 /* Sort it. Given a small number of alternatives, a dumb algorithm
8649 won't hurt too much. */
8650 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8653 int best_reject = alternative_reject[alternative_order[i]];
8654 int best_nregs = alternative_nregs[alternative_order[i]];
8657 for (j = i + 1; j < recog_data.n_alternatives; j++)
8659 int this_reject = alternative_reject[alternative_order[j]];
8660 int this_nregs = alternative_nregs[alternative_order[j]];
8662 if (this_reject < best_reject
8663 || (this_reject == best_reject && this_nregs < best_nregs))
8666 best_reject = this_reject;
8667 best_nregs = this_nregs;
8671 tmp = alternative_order[best];
8672 alternative_order[best] = alternative_order[i];
8673 alternative_order[i] = tmp;
8676 /* Substitute the operands as determined by op_alt_regno for the best
8678 j = alternative_order[0];
8680 /* Pop back to the real obstacks while changing the insn. */
8683 for (i = 0; i < recog_data.n_operands; i++)
8685 enum machine_mode mode = recog_data.operand_mode[i];
8686 if (op_alt_regno[i][j] == -1)
8689 validate_change (insn, recog_data.operand_loc[i],
8690 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8693 for (i = recog_data.n_dups - 1; i >= 0; i--)
8695 int op = recog_data.dup_num[i];
8696 enum machine_mode mode = recog_data.operand_mode[op];
8698 if (op_alt_regno[op][j] == -1)
8701 validate_change (insn, recog_data.dup_loc[i],
8702 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8705 /* Go back to the obstack we are using for temporary
8707 push_obstacks (&reload_obstack, &reload_obstack);
8709 return apply_change_group ();
8712 /* These two variables are used to pass information from
8713 reload_cse_record_set to reload_cse_check_clobber. */
8715 static int reload_cse_check_clobbered;
8716 static rtx reload_cse_check_src;
8718 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8719 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8720 second argument, which is passed by note_stores, is ignored. */
8723 reload_cse_check_clobber (dest, ignore, data)
8725 rtx ignore ATTRIBUTE_UNUSED;
8726 void *data ATTRIBUTE_UNUSED;
8728 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8729 reload_cse_check_clobbered = 1;
8732 /* Record the result of a SET instruction. SET is the set pattern.
8733 BODY is the pattern of the insn that it came from. */
8736 reload_cse_record_set (set, body)
8742 enum machine_mode dest_mode;
8744 dest = SET_DEST (set);
8745 src = SET_SRC (set);
8746 dreg = true_regnum (dest);
8747 sreg = true_regnum (src);
8748 dest_mode = GET_MODE (dest);
8750 /* Some machines don't define AUTO_INC_DEC, but they still use push
8751 instructions. We need to catch that case here in order to
8752 invalidate the stack pointer correctly. Note that invalidating
8753 the stack pointer is different from invalidating DEST. */
8755 while (GET_CODE (x) == SUBREG
8756 || GET_CODE (x) == ZERO_EXTRACT
8757 || GET_CODE (x) == SIGN_EXTRACT
8758 || GET_CODE (x) == STRICT_LOW_PART)
8760 if (push_operand (x, GET_MODE (x)))
8762 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL);
8763 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8767 /* We can only handle an assignment to a register, or a store of a
8768 register to a memory location. For other cases, we just clobber
8769 the destination. We also have to just clobber if there are side
8770 effects in SRC or DEST. */
8771 if ((dreg < 0 && GET_CODE (dest) != MEM)
8772 || side_effects_p (src)
8773 || side_effects_p (dest))
8775 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8780 /* We don't try to handle values involving CC, because it's a pain
8781 to keep track of when they have to be invalidated. */
8782 if (reg_mentioned_p (cc0_rtx, src)
8783 || reg_mentioned_p (cc0_rtx, dest))
8785 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8790 /* If BODY is a PARALLEL, then we need to see whether the source of
8791 SET is clobbered by some other instruction in the PARALLEL. */
8792 if (GET_CODE (body) == PARALLEL)
8796 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8800 x = XVECEXP (body, 0, i);
8804 reload_cse_check_clobbered = 0;
8805 reload_cse_check_src = src;
8806 note_stores (x, reload_cse_check_clobber, NULL);
8807 if (reload_cse_check_clobbered)
8809 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8819 /* This is an assignment to a register. Update the value we
8820 have stored for the register. */
8825 /* This is a copy from one register to another. Any values
8826 which were valid for SREG are now valid for DREG. If the
8827 mode changes, we use gen_lowpart_common to extract only
8828 the part of the value that is copied. */
8829 reg_values[dreg] = 0;
8830 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8834 if (XEXP (x, 0) == 0)
8836 if (dest_mode == GET_MODE (XEXP (x, 0)))
8838 else if (GET_MODE_BITSIZE (dest_mode)
8839 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8842 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8844 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
8849 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
8851 /* We've changed DREG, so invalidate any values held by other
8852 registers that depend upon it. */
8853 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8855 /* If this assignment changes more than one hard register,
8856 forget anything we know about the others. */
8857 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8858 reg_values[dreg + i] = 0;
8860 else if (GET_CODE (dest) == MEM)
8862 /* Invalidate conflicting memory locations. */
8863 reload_cse_invalidate_mem (dest);
8865 /* If we're storing a register to memory, add DEST to the list
8867 if (sreg >= 0 && ! side_effects_p (dest))
8868 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
8873 /* We should have bailed out earlier. */
8878 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8880 This code might also be useful when reload gave up on reg+reg addresssing
8881 because of clashes between the return register and INDEX_REG_CLASS. */
8883 /* The maximum number of uses of a register we can keep track of to
8884 replace them with reg+reg addressing. */
8885 #define RELOAD_COMBINE_MAX_USES 6
8887 /* INSN is the insn where a register has ben used, and USEP points to the
8888 location of the register within the rtl. */
8889 struct reg_use { rtx insn, *usep; };
8891 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8892 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8893 indicates where it becomes live again.
8894 Otherwise, USE_INDEX is the index of the last encountered use of the
8895 register (which is first among these we have seen since we scan backwards),
8896 OFFSET contains the constant offset that is added to the register in
8897 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8898 last, of these uses.
8899 STORE_RUID is always meaningful if we only want to use a value in a
8900 register in a different place: it denotes the next insn in the insn
8901 stream (i.e. the last ecountered) that sets or clobbers the register. */
8904 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8909 } reg_state[FIRST_PSEUDO_REGISTER];
8911 /* Reverse linear uid. This is increased in reload_combine while scanning
8912 the instructions from last to first. It is used to set last_label_ruid
8913 and the store_ruid / use_ruid fields in reg_state. */
8914 static int reload_combine_ruid;
8916 #define LABEL_LIVE(LABEL) \
8917 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8923 int first_index_reg = 1, last_index_reg = 0;
8925 int last_label_ruid;
8926 int min_labelno, n_labels;
8927 HARD_REG_SET ever_live_at_start, *label_live;
8929 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8930 reload has already used it where appropriate, so there is no use in
8931 trying to generate it now. */
8932 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8935 /* To avoid wasting too much time later searching for an index register,
8936 determine the minimum and maximum index register numbers. */
8937 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8939 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
8941 if (! last_index_reg)
8943 first_index_reg = i;
8946 /* If no index register is available, we can quit now. */
8947 if (first_index_reg > last_index_reg)
8950 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8951 information is a bit fuzzy immediately after reload, but it's
8952 still good enough to determine which registers are live at a jump
8954 min_labelno = get_first_label_num ();
8955 n_labels = max_label_num () - min_labelno;
8956 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8957 CLEAR_HARD_REG_SET (ever_live_at_start);
8958 for (i = n_basic_blocks - 1; i >= 0; i--)
8960 insn = BLOCK_HEAD (i);
8961 if (GET_CODE (insn) == CODE_LABEL)
8965 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
8966 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
8967 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8968 IOR_HARD_REG_SET (ever_live_at_start, live);
8972 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8973 last_label_ruid = reload_combine_ruid = 0;
8974 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8976 reg_state[i].store_ruid = reload_combine_ruid;
8978 reg_state[i].use_index = -1;
8980 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8983 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8987 /* We cannot do our optimization across labels. Invalidating all the use
8988 information we have would be costly, so we just note where the label
8989 is and then later disable any optimization that would cross it. */
8990 if (GET_CODE (insn) == CODE_LABEL)
8991 last_label_ruid = reload_combine_ruid;
8992 if (GET_CODE (insn) == BARRIER)
8994 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8995 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8997 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8999 reload_combine_ruid++;
9001 /* Look for (set (REGX) (CONST_INT))
9002 (set (REGX) (PLUS (REGX) (REGY)))
9004 ... (MEM (REGX)) ...
9006 (set (REGZ) (CONST_INT))
9008 ... (MEM (PLUS (REGZ) (REGY)))... .
9010 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9011 and that we know all uses of REGX before it dies. */
9012 set = single_set (insn);
9014 && GET_CODE (SET_DEST (set)) == REG
9015 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9016 GET_MODE (SET_DEST (set)))
9018 && GET_CODE (SET_SRC (set)) == PLUS
9019 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9020 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9021 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9023 rtx reg = SET_DEST (set);
9024 rtx plus = SET_SRC (set);
9025 rtx base = XEXP (plus, 1);
9026 rtx prev = prev_nonnote_insn (insn);
9027 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9028 int regno = REGNO (reg);
9029 rtx const_reg = NULL_RTX;
9030 rtx reg_sum = NULL_RTX;
9032 /* Now, we need an index register.
9033 We'll set index_reg to this index register, const_reg to the
9034 register that is to be loaded with the constant
9035 (denoted as REGZ in the substitution illustration above),
9036 and reg_sum to the register-register that we want to use to
9037 substitute uses of REG (typically in MEMs) with.
9038 First check REG and BASE for being index registers;
9039 we can use them even if they are not dead. */
9040 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9041 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9049 /* Otherwise, look for a free index register. Since we have
9050 checked above that neiter REG nor BASE are index registers,
9051 if we find anything at all, it will be different from these
9053 for (i = first_index_reg; i <= last_index_reg; i++)
9055 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9056 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9057 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9058 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9060 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9061 const_reg = index_reg;
9062 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9067 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9068 (REGY), i.e. BASE, is not clobbered before the last use we'll
9071 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9072 && rtx_equal_p (SET_DEST (prev_set), reg)
9073 && reg_state[regno].use_index >= 0
9074 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9079 /* Change destination register and - if necessary - the
9080 constant value in PREV, the constant loading instruction. */
9081 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9082 if (reg_state[regno].offset != const0_rtx)
9083 validate_change (prev,
9084 &SET_SRC (prev_set),
9085 GEN_INT (INTVAL (SET_SRC (prev_set))
9086 + INTVAL (reg_state[regno].offset)),
9088 /* Now for every use of REG that we have recorded, replace REG
9090 for (i = reg_state[regno].use_index;
9091 i < RELOAD_COMBINE_MAX_USES; i++)
9092 validate_change (reg_state[regno].reg_use[i].insn,
9093 reg_state[regno].reg_use[i].usep,
9096 if (apply_change_group ())
9100 /* Delete the reg-reg addition. */
9101 PUT_CODE (insn, NOTE);
9102 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9103 NOTE_SOURCE_FILE (insn) = 0;
9105 if (reg_state[regno].offset != const0_rtx)
9107 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9109 for (np = ®_NOTES (prev); *np; )
9111 if (REG_NOTE_KIND (*np) == REG_EQUAL
9112 || REG_NOTE_KIND (*np) == REG_EQUIV)
9113 *np = XEXP (*np, 1);
9115 np = &XEXP (*np, 1);
9118 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9119 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9124 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
9125 if (GET_CODE (insn) == CALL_INSN)
9129 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9131 if (call_used_regs[i])
9133 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9134 reg_state[i].store_ruid = reload_combine_ruid;
9137 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9138 link = XEXP (link, 1))
9140 rtx use = XEXP (link, 0);
9141 int regno = REGNO (XEXP (use, 0));
9142 if (GET_CODE (use) == CLOBBER)
9144 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9145 reg_state[regno].store_ruid = reload_combine_ruid;
9148 reg_state[regno].use_index = -1;
9151 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9153 /* Non-spill registers might be used at the call destination in
9154 some unknown fashion, so we have to mark the unknown use. */
9156 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9157 && JUMP_LABEL (insn))
9158 live = &LABEL_LIVE (JUMP_LABEL (insn));
9160 live = &ever_live_at_start;
9161 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9163 if (TEST_HARD_REG_BIT (*live, i))
9164 reg_state[i].use_index = -1;
9167 reload_combine_note_use (&PATTERN (insn), insn);
9168 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9170 if (REG_NOTE_KIND (note) == REG_INC
9171 && GET_CODE (XEXP (note, 0)) == REG)
9173 int regno = REGNO (XEXP (note, 0));
9175 reg_state[regno].store_ruid = reload_combine_ruid;
9176 reg_state[regno].use_index = -1;
9183 /* Check if DST is a register or a subreg of a register; if it is,
9184 update reg_state[regno].store_ruid and reg_state[regno].use_index
9185 accordingly. Called via note_stores from reload_combine. */
9187 reload_combine_note_store (dst, set, data)
9189 void *data ATTRIBUTE_UNUSED;
9193 enum machine_mode mode = GET_MODE (dst);
9195 if (GET_CODE (dst) == SUBREG)
9197 regno = SUBREG_WORD (dst);
9198 dst = SUBREG_REG (dst);
9200 if (GET_CODE (dst) != REG)
9202 regno += REGNO (dst);
9204 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9205 careful with registers / register parts that are not full words.
9207 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9208 if (GET_CODE (set) != SET
9209 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9210 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9211 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9213 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
9215 reg_state[i].use_index = -1;
9216 reg_state[i].store_ruid = reload_combine_ruid;
9221 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
9223 reg_state[i].store_ruid = reload_combine_ruid;
9224 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9229 /* XP points to a piece of rtl that has to be checked for any uses of
9231 *XP is the pattern of INSN, or a part of it.
9232 Called from reload_combine, and recursively by itself. */
9234 reload_combine_note_use (xp, insn)
9238 enum rtx_code code = x->code;
9241 rtx offset = const0_rtx; /* For the REG case below. */
9246 if (GET_CODE (SET_DEST (x)) == REG)
9248 reload_combine_note_use (&SET_SRC (x), insn);
9254 if (GET_CODE (SET_DEST (x)) == REG)
9259 /* We are interested in (plus (reg) (const_int)) . */
9260 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9262 offset = XEXP (x, 1);
9267 int regno = REGNO (x);
9270 /* Some spurious USEs of pseudo registers might remain.
9271 Just ignore them. */
9272 if (regno >= FIRST_PSEUDO_REGISTER)
9275 /* If this register is already used in some unknown fashion, we
9277 If we decrement the index from zero to -1, we can't store more
9278 uses, so this register becomes used in an unknown fashion. */
9279 use_index = --reg_state[regno].use_index;
9283 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9285 /* We have found another use for a register that is already
9286 used later. Check if the offsets match; if not, mark the
9287 register as used in an unknown fashion. */
9288 if (! rtx_equal_p (offset, reg_state[regno].offset))
9290 reg_state[regno].use_index = -1;
9296 /* This is the first use of this register we have seen since we
9297 marked it as dead. */
9298 reg_state[regno].offset = offset;
9299 reg_state[regno].use_ruid = reload_combine_ruid;
9301 reg_state[regno].reg_use[use_index].insn = insn;
9302 reg_state[regno].reg_use[use_index].usep = xp;
9310 /* Recursively process the components of X. */
9311 fmt = GET_RTX_FORMAT (code);
9312 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9315 reload_combine_note_use (&XEXP (x, i), insn);
9316 else if (fmt[i] == 'E')
9318 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9319 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9324 /* See if we can reduce the cost of a constant by replacing a move with
9326 /* We cannot do our optimization across labels. Invalidating all the
9327 information about register contents we have would be costly, so we
9328 use last_label_luid (local variable of reload_cse_move2add) to note
9329 where the label is and then later disable any optimization that would
9331 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9332 reg_set_luid[n] is larger than last_label_luid[n] . */
9333 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9334 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9335 reg_mode[n] to be valid.
9336 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9337 has been set to reg_offset[n] in mode reg_mode[n] .
9338 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9339 register n has been set to the sum of reg_offset[n] and register
9340 reg_base_reg[n], calculated in mode reg_mode[n] . */
9341 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9342 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9343 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9344 /* move2add_luid is linearily increased while scanning the instructions
9345 from first to last. It is used to set reg_set_luid in
9346 reload_cse_move2add and move2add_note_store. */
9347 static int move2add_luid;
9349 /* Generate a CONST_INT and force it in the range of MODE. */
9351 gen_mode_int (mode, value)
9352 enum machine_mode mode;
9353 HOST_WIDE_INT value;
9355 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9356 int width = GET_MODE_BITSIZE (mode);
9358 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9360 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9361 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9362 cval |= (HOST_WIDE_INT) -1 << width;
9364 return GEN_INT (cval);
9368 reload_cse_move2add (first)
9373 int last_label_luid;
9375 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9376 reg_set_luid[i] = 0;
9378 last_label_luid = 0;
9380 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9384 if (GET_CODE (insn) == CODE_LABEL)
9385 last_label_luid = move2add_luid;
9386 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9388 pat = PATTERN (insn);
9389 /* For simplicity, we only perform this optimization on
9390 straightforward SETs. */
9391 if (GET_CODE (pat) == SET
9392 && GET_CODE (SET_DEST (pat)) == REG)
9394 rtx reg = SET_DEST (pat);
9395 int regno = REGNO (reg);
9396 rtx src = SET_SRC (pat);
9398 /* Check if we have valid information on the contents of this
9399 register in the mode of REG. */
9400 /* ??? We don't know how zero / sign extension is handled, hence
9401 we can't go from a narrower to a wider mode. */
9402 if (reg_set_luid[regno] > last_label_luid
9403 && (GET_MODE_SIZE (GET_MODE (reg))
9404 <= GET_MODE_SIZE (reg_mode[regno]))
9405 && GET_CODE (reg_offset[regno]) == CONST_INT)
9407 /* Try to transform (set (REGX) (CONST_INT A))
9409 (set (REGX) (CONST_INT B))
9411 (set (REGX) (CONST_INT A))
9413 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9415 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9419 = gen_mode_int (GET_MODE (reg),
9420 INTVAL (src) - INTVAL (reg_offset[regno]));
9421 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9422 use (set (reg) (reg)) instead.
9423 We don't delete this insn, nor do we convert it into a
9424 note, to avoid losing register notes or the return
9425 value flag. jump2 already knowns how to get rid of
9427 if (new_src == const0_rtx)
9428 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9429 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9430 && have_add2_insn (GET_MODE (reg)))
9431 success = validate_change (insn, &PATTERN (insn),
9432 gen_add2_insn (reg, new_src), 0);
9433 reg_set_luid[regno] = move2add_luid;
9434 reg_mode[regno] = GET_MODE (reg);
9435 reg_offset[regno] = src;
9439 /* Try to transform (set (REGX) (REGY))
9440 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9443 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9446 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9448 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9449 else if (GET_CODE (src) == REG
9450 && reg_base_reg[regno] == REGNO (src)
9451 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9453 rtx next = next_nonnote_insn (insn);
9456 set = single_set (next);
9459 && SET_DEST (set) == reg
9460 && GET_CODE (SET_SRC (set)) == PLUS
9461 && XEXP (SET_SRC (set), 0) == reg
9462 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9464 rtx src3 = XEXP (SET_SRC (set), 1);
9466 = gen_mode_int (GET_MODE (reg),
9468 - INTVAL (reg_offset[regno]));
9471 if (new_src == const0_rtx)
9472 /* See above why we create (set (reg) (reg)) here. */
9474 = validate_change (next, &SET_SRC (set), reg, 0);
9475 else if ((rtx_cost (new_src, PLUS)
9476 < 2 + rtx_cost (src3, SET))
9477 && have_add2_insn (GET_MODE (reg)))
9479 = validate_change (next, &PATTERN (next),
9480 gen_add2_insn (reg, new_src), 0);
9483 /* INSN might be the first insn in a basic block
9484 if the preceding insn is a conditional jump
9485 or a possible-throwing call. */
9486 PUT_CODE (insn, NOTE);
9487 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9488 NOTE_SOURCE_FILE (insn) = 0;
9491 reg_set_luid[regno] = move2add_luid;
9492 reg_mode[regno] = GET_MODE (reg);
9493 reg_offset[regno] = src3;
9500 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9502 if (REG_NOTE_KIND (note) == REG_INC
9503 && GET_CODE (XEXP (note, 0)) == REG)
9505 /* Indicate that this register has been recently written to,
9506 but the exact contents are not available. */
9507 int regno = REGNO (XEXP (note, 0));
9508 if (regno < FIRST_PSEUDO_REGISTER)
9510 reg_set_luid[regno] = move2add_luid;
9511 reg_offset[regno] = note;
9515 note_stores (PATTERN (insn), move2add_note_store, NULL);
9516 /* If this is a CALL_INSN, all call used registers are stored with
9518 if (GET_CODE (insn) == CALL_INSN)
9520 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9522 if (call_used_regs[i])
9524 reg_set_luid[i] = move2add_luid;
9525 reg_offset[i] = insn; /* Invalidate contents. */
9532 /* SET is a SET or CLOBBER that sets DST.
9533 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9534 Called from reload_cse_move2add via note_stores. */
9536 move2add_note_store (dst, set, data)
9538 void *data ATTRIBUTE_UNUSED;
9543 enum machine_mode mode = GET_MODE (dst);
9544 if (GET_CODE (dst) == SUBREG)
9546 regno = SUBREG_WORD (dst);
9547 dst = SUBREG_REG (dst);
9549 if (GET_CODE (dst) != REG)
9552 regno += REGNO (dst);
9554 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9555 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9556 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9557 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9559 rtx src = SET_SRC (set);
9561 reg_mode[regno] = mode;
9562 switch (GET_CODE (src))
9566 rtx src0 = XEXP (src, 0);
9567 if (GET_CODE (src0) == REG)
9569 if (REGNO (src0) != regno
9570 || reg_offset[regno] != const0_rtx)
9572 reg_base_reg[regno] = REGNO (src0);
9573 reg_set_luid[regno] = move2add_luid;
9575 reg_offset[regno] = XEXP (src, 1);
9578 reg_set_luid[regno] = move2add_luid;
9579 reg_offset[regno] = set; /* Invalidate contents. */
9584 reg_base_reg[regno] = REGNO (SET_SRC (set));
9585 reg_offset[regno] = const0_rtx;
9586 reg_set_luid[regno] = move2add_luid;
9590 reg_base_reg[regno] = -1;
9591 reg_offset[regno] = SET_SRC (set);
9592 reg_set_luid[regno] = move2add_luid;
9598 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9600 /* Indicate that this register has been recently written to,
9601 but the exact contents are not available. */
9602 reg_set_luid[i] = move2add_luid;
9603 reg_offset[i] = dst;
9610 add_auto_inc_notes (insn, x)
9614 enum rtx_code code = GET_CODE (x);
9618 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9621 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9625 /* Scan all the operand sub-expressions. */
9626 fmt = GET_RTX_FORMAT (code);
9627 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9630 add_auto_inc_notes (insn, XEXP (x, i));
9631 else if (fmt[i] == 'E')
9632 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9633 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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