1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
37 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 All the pseudos that were formerly allocated to the hard regs that
58 are now in use as reload regs must be ``spilled''. This means
59 that they go to other hard regs, or to stack slots if no other
60 available hard regs can be found. Spilling can invalidate more
61 insns, requiring additional need for reloads, so we must keep checking
62 until the process stabilizes.
64 For machines with different classes of registers, we must keep track
65 of the register class needed for each reload, and make sure that
66 we allocate enough reload registers of each class.
68 The file reload.c contains the code that checks one insn for
69 validity and reports the reloads that it needs. This file
70 is in charge of scanning the entire rtl code, accumulating the
71 reload needs, spilling, assigning reload registers to use for
72 fixing up each insn, and generating the new insns to copy values
73 into the reload registers. */
76 #ifndef REGISTER_MOVE_COST
77 #define REGISTER_MOVE_COST(x, y) 2
80 /* During reload_as_needed, element N contains a REG rtx for the hard reg
81 into which reg N has been reloaded (perhaps for a previous insn). */
82 static rtx *reg_last_reload_reg;
84 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
85 for an output reload that stores into reg N. */
86 static char *reg_has_output_reload;
88 /* Indicates which hard regs are reload-registers for an output reload
89 in the current insn. */
90 static HARD_REG_SET reg_is_output_reload;
92 /* Element N is the constant value to which pseudo reg N is equivalent,
93 or zero if pseudo reg N is not equivalent to a constant.
94 find_reloads looks at this in order to replace pseudo reg N
95 with the constant it stands for. */
96 rtx *reg_equiv_constant;
98 /* Element N is a memory location to which pseudo reg N is equivalent,
99 prior to any register elimination (such as frame pointer to stack
100 pointer). Depending on whether or not it is a valid address, this value
101 is transferred to either reg_equiv_address or reg_equiv_mem. */
102 rtx *reg_equiv_memory_loc;
104 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
105 This is used when the address is not valid as a memory address
106 (because its displacement is too big for the machine.) */
107 rtx *reg_equiv_address;
109 /* Element N is the memory slot to which pseudo reg N is equivalent,
110 or zero if pseudo reg N is not equivalent to a memory slot. */
113 /* Widest width in which each pseudo reg is referred to (via subreg). */
114 static int *reg_max_ref_width;
116 /* Element N is the insn that initialized reg N from its equivalent
117 constant or memory slot. */
118 static rtx *reg_equiv_init;
120 /* During reload_as_needed, element N contains the last pseudo regno reloaded
121 into hard register N. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 hard register N was last used. Its contents are significant only
128 when reg_reloaded_valid is set for this register. */
129 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
131 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
132 static HARD_REG_SET reg_reloaded_valid;
133 /* Indicate if the register was dead at the end of the reload.
134 This is only valid if reg_reloaded_contents is set and valid. */
135 static HARD_REG_SET reg_reloaded_dead;
137 /* Number of spill-regs so far; number of valid elements of spill_regs. */
140 /* In parallel with spill_regs, contains REG rtx's for those regs.
141 Holds the last rtx used for any given reg, or 0 if it has never
142 been used for spilling yet. This rtx is reused, provided it has
144 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
146 /* In parallel with spill_regs, contains nonzero for a spill reg
147 that was stored after the last time it was used.
148 The precise value is the insn generated to do the store. */
149 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
151 /* This table is the inverse mapping of spill_regs:
152 indexed by hard reg number,
153 it contains the position of that reg in spill_regs,
154 or -1 for something that is not in spill_regs. */
155 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
157 /* This reg set indicates registers that may not be used for retrying global
158 allocation. The registers that may not be used include all spill registers
159 and the frame pointer (if we are using one). */
160 HARD_REG_SET forbidden_regs;
162 /* This reg set indicates registers that are not good for spill registers.
163 They will not be used to complete groups of spill registers. This includes
164 all fixed registers, registers that may be eliminated, and, if
165 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl.
167 (spill_reg_order prevents these registers from being used to start a
169 static HARD_REG_SET bad_spill_regs;
171 /* Describes order of use of registers for reloading
172 of spilled pseudo-registers. `spills' is the number of
173 elements that are actually valid; new ones are added at the end. */
174 static short spill_regs[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates those registers that have been used a spill
177 registers. This information is used in reorg.c, to help figure out
178 what registers are live at any point. It is assumed that all spill_regs
179 are dead at every CODE_LABEL. */
181 HARD_REG_SET used_spill_regs;
183 /* Index of last register assigned as a spill register. We allocate in
184 a round-robin fashion. */
186 static int last_spill_reg;
188 /* Describes order of preference for putting regs into spill_regs.
189 Contains the numbers of all the hard regs, in order most preferred first.
190 This order is different for each function.
191 It is set up by order_regs_for_reload.
192 Empty elements at the end contain -1. */
193 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
195 /* 1 for a hard register that appears explicitly in the rtl
196 (for example, function value registers, special registers
197 used by insns, structure value pointer registers). */
198 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
200 /* Indicates if a register was counted against the need for
201 groups. 0 means it can count against max_nongroup instead. */
202 static HARD_REG_SET counted_for_groups;
204 /* Indicates if a register was counted against the need for
205 non-groups. 0 means it can become part of a new group.
206 During choose_reload_regs, 1 here means don't use this reg
207 as part of a group, even if it seems to be otherwise ok. */
208 static HARD_REG_SET counted_for_nongroups;
210 /* Nonzero if indirect addressing is supported on the machine; this means
211 that spilling (REG n) does not require reloading it into a register in
212 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
213 value indicates the level of indirect addressing supported, e.g., two
214 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
217 static char spill_indirect_levels;
219 /* Nonzero if indirect addressing is supported when the innermost MEM is
220 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
221 which these are valid is the same as spill_indirect_levels, above. */
223 char indirect_symref_ok;
225 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
227 char double_reg_address_ok;
229 /* Record the stack slot for each spilled hard register. */
231 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
233 /* Width allocated so far for that stack slot. */
235 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
237 /* Indexed by register class and basic block number, nonzero if there is
238 any need for a spill register of that class in that basic block.
239 The pointer is 0 if we did stupid allocation and don't know
240 the structure of basic blocks. */
242 char *basic_block_needs[N_REG_CLASSES];
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* The register class to use for a base register when reloading an
254 address. This is normally BASE_REG_CLASS, but it may be different
255 when using SMALL_REGISTER_CLASSES and passing parameters in
257 enum reg_class reload_address_base_reg_class;
259 /* The register class to use for an index register when reloading an
260 address. This is normally INDEX_REG_CLASS, but it may be different
261 when using SMALL_REGISTER_CLASSES and passing parameters in
263 enum reg_class reload_address_index_reg_class;
265 /* Set to 1 while reload_as_needed is operating.
266 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress = 0;
270 /* These arrays record the insn_code of insns that may be needed to
271 perform input and output reloads of special objects. They provide a
272 place to pass a scratch register. */
274 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
275 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
277 /* This obstack is used for allocation of rtl during register elimination.
278 The allocated storage can be freed once find_reloads has processed the
281 struct obstack reload_obstack;
282 char *reload_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of labels that must never be deleted. */
288 extern rtx forced_labels;
290 /* Allocation number table from global register allocation. */
291 extern int *reg_allocno;
293 /* This structure is used to record information about register eliminations.
294 Each array entry describes one possible way of eliminating a register
295 in favor of another. If there is more than one way of eliminating a
296 particular register, the most preferred should be specified first. */
298 static struct elim_table
300 int from; /* Register number to be eliminated. */
301 int to; /* Register number used as replacement. */
302 int initial_offset; /* Initial difference between values. */
303 int can_eliminate; /* Non-zero if this elimination can be done. */
304 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
305 insns made by reload. */
306 int offset; /* Current offset between the two regs. */
307 int max_offset; /* Maximum offset between the two regs. */
308 int previous_offset; /* Offset at end of previous insn. */
309 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
310 rtx from_rtx; /* REG rtx for the register to be eliminated.
311 We cannot simply compare the number since
312 we might then spuriously replace a hard
313 register corresponding to a pseudo
314 assigned to the reg to be eliminated. */
315 rtx to_rtx; /* REG rtx for the replacement. */
318 /* If a set of eliminable registers was specified, define the table from it.
319 Otherwise, default to the normal case of the frame pointer being
320 replaced by the stack pointer. */
322 #ifdef ELIMINABLE_REGS
325 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
328 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
330 /* Record the number of pending eliminations that have an offset not equal
331 to their initial offset. If non-zero, we use a new copy of each
332 replacement result in any insns encountered. */
333 static int num_not_at_initial_offset;
335 /* Count the number of registers that we may be able to eliminate. */
336 static int num_eliminable;
338 /* For each label, we record the offset of each elimination. If we reach
339 a label by more than one path and an offset differs, we cannot do the
340 elimination. This information is indexed by the number of the label.
341 The first table is an array of flags that records whether we have yet
342 encountered a label and the second table is an array of arrays, one
343 entry in the latter array for each elimination. */
345 static char *offsets_known_at;
346 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
348 /* Number of labels in the current function. */
350 static int num_labels;
352 struct hard_reg_n_uses { int regno; int uses; };
354 static int possible_group_p PROTO((int, int *));
355 static void count_possible_groups PROTO((int *, enum machine_mode *,
357 static int modes_equiv_for_class_p PROTO((enum machine_mode,
360 static void spill_failure PROTO((rtx));
361 static int new_spill_reg PROTO((int, int, int *, int *, int,
363 static void delete_dead_insn PROTO((rtx));
364 static void alter_reg PROTO((int, int));
365 static void mark_scratch_live PROTO((rtx));
366 static void set_label_offsets PROTO((rtx, rtx, int));
367 static int eliminate_regs_in_insn PROTO((rtx, int));
368 static void mark_not_eliminable PROTO((rtx, rtx));
369 static int spill_hard_reg PROTO((int, int, FILE *, int));
370 static void scan_paradoxical_subregs PROTO((rtx));
371 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
372 static void order_regs_for_reload PROTO((int));
373 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
374 static void reload_as_needed PROTO((rtx, int));
375 static void forget_old_reloads_1 PROTO((rtx, rtx));
376 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
377 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
379 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
381 static int reload_reg_free_p PROTO((int, int, enum reload_type));
382 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
383 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int));
384 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
385 static int allocate_reload_reg PROTO((int, rtx, int, int));
386 static void choose_reload_regs PROTO((rtx, rtx));
387 static void merge_assigned_reloads PROTO((rtx));
388 static void emit_reload_insns PROTO((rtx));
389 static void delete_output_reload PROTO((rtx, int, rtx));
390 static void inc_for_reload PROTO((rtx, rtx, int));
391 static int constraint_accepts_reg_p PROTO((char *, rtx));
392 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
393 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
394 static void reload_cse_invalidate_mem PROTO((rtx));
395 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
396 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
397 static int reload_cse_noop_set_p PROTO((rtx, rtx));
398 static int reload_cse_simplify_set PROTO((rtx, rtx));
399 static int reload_cse_simplify_operands PROTO((rtx));
400 static void reload_cse_check_clobber PROTO((rtx, rtx));
401 static void reload_cse_record_set PROTO((rtx, rtx));
402 static void reload_cse_delete_death_notes PROTO((rtx));
403 static void reload_cse_no_longer_dead PROTO((int, enum machine_mode));
405 /* Initialize the reload pass once per compilation. */
412 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
413 Set spill_indirect_levels to the number of levels such addressing is
414 permitted, zero if it is not permitted at all. */
417 = gen_rtx_MEM (Pmode,
419 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
421 spill_indirect_levels = 0;
423 while (memory_address_p (QImode, tem))
425 spill_indirect_levels++;
426 tem = gen_rtx_MEM (Pmode, tem);
429 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
431 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
432 indirect_symref_ok = memory_address_p (QImode, tem);
434 /* See if reg+reg is a valid (and offsettable) address. */
436 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
438 tem = gen_rtx_PLUS (Pmode,
439 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
440 gen_rtx_REG (Pmode, i));
441 /* This way, we make sure that reg+reg is an offsettable address. */
442 tem = plus_constant (tem, 4);
444 if (memory_address_p (QImode, tem))
446 double_reg_address_ok = 1;
451 /* Initialize obstack for our rtl allocation. */
452 gcc_obstack_init (&reload_obstack);
453 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
455 /* Decide which register class should be used when reloading
456 addresses. If we are using SMALL_REGISTER_CLASSES, and any
457 parameters are passed in registers, then we do not want to use
458 those registers when reloading an address. Otherwise, if a
459 function argument needs a reload, we may wind up clobbering
460 another argument to the function which was already computed. If
461 we find a subset class which simply avoids those registers, we
462 use it instead. ??? It would be better to only use the
463 restricted class when we actually are loading function arguments,
464 but that is hard to determine. */
465 reload_address_base_reg_class = BASE_REG_CLASS;
466 reload_address_index_reg_class = INDEX_REG_CLASS;
467 if (SMALL_REGISTER_CLASSES)
470 HARD_REG_SET base, index;
473 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
474 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
475 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
477 if (FUNCTION_ARG_REGNO_P (regno))
479 CLEAR_HARD_REG_BIT (base, regno);
480 CLEAR_HARD_REG_BIT (index, regno);
484 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
486 for (p = reg_class_subclasses[BASE_REG_CLASS];
487 *p != LIM_REG_CLASSES;
490 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
493 reload_address_base_reg_class = *p;
498 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
500 for (p = reg_class_subclasses[INDEX_REG_CLASS];
501 *p != LIM_REG_CLASSES;
504 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
507 reload_address_index_reg_class = *p;
514 /* Main entry point for the reload pass.
516 FIRST is the first insn of the function being compiled.
518 GLOBAL nonzero means we were called from global_alloc
519 and should attempt to reallocate any pseudoregs that we
520 displace from hard regs we will use for reloads.
521 If GLOBAL is zero, we do not have enough information to do that,
522 so any pseudo reg that is spilled must go to the stack.
524 DUMPFILE is the global-reg debugging dump file stream, or 0.
525 If it is nonzero, messages are written to it to describe
526 which registers are seized as reload regs, which pseudo regs
527 are spilled from them, and where the pseudo regs are reallocated to.
529 Return value is nonzero if reload failed
530 and we must not do any more for this function. */
533 reload (first, global, dumpfile)
539 register int i, j, k;
541 register struct elim_table *ep;
543 /* The two pointers used to track the true location of the memory used
544 for label offsets. */
545 char *real_known_ptr = NULL_PTR;
546 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
548 int something_changed;
549 int something_needs_reloads;
550 int something_needs_elimination;
551 int new_basic_block_needs;
552 enum reg_class caller_save_spill_class = NO_REGS;
553 int caller_save_group_size = 1;
555 /* Nonzero means we couldn't get enough spill regs. */
558 /* The basic block number currently being processed for INSN. */
561 /* Make sure even insns with volatile mem refs are recognizable. */
564 /* Enable find_equiv_reg to distinguish insns made by reload. */
565 reload_first_uid = get_max_uid ();
567 for (i = 0; i < N_REG_CLASSES; i++)
568 basic_block_needs[i] = 0;
570 #ifdef SECONDARY_MEMORY_NEEDED
571 /* Initialize the secondary memory table. */
572 clear_secondary_mem ();
575 /* Remember which hard regs appear explicitly
576 before we merge into `regs_ever_live' the ones in which
577 pseudo regs have been allocated. */
578 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
580 /* We don't have a stack slot for any spill reg yet. */
581 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
582 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
584 /* Initialize the save area information for caller-save, in case some
588 /* Compute which hard registers are now in use
589 as homes for pseudo registers.
590 This is done here rather than (eg) in global_alloc
591 because this point is reached even if not optimizing. */
592 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
595 /* A function that receives a nonlocal goto must save all call-saved
597 if (current_function_has_nonlocal_label)
598 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
600 if (! call_used_regs[i] && ! fixed_regs[i])
601 regs_ever_live[i] = 1;
604 for (i = 0; i < scratch_list_length; i++)
606 mark_scratch_live (scratch_list[i]);
608 /* Make sure that the last insn in the chain
609 is not something that needs reloading. */
610 emit_note (NULL_PTR, NOTE_INSN_DELETED);
612 /* Find all the pseudo registers that didn't get hard regs
613 but do have known equivalent constants or memory slots.
614 These include parameters (known equivalent to parameter slots)
615 and cse'd or loop-moved constant memory addresses.
617 Record constant equivalents in reg_equiv_constant
618 so they will be substituted by find_reloads.
619 Record memory equivalents in reg_mem_equiv so they can
620 be substituted eventually by altering the REG-rtx's. */
622 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
623 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
624 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
625 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
626 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
627 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
628 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
629 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
630 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
631 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
632 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
633 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
635 if (SMALL_REGISTER_CLASSES)
636 CLEAR_HARD_REG_SET (forbidden_regs);
638 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
639 Also find all paradoxical subregs and find largest such for each pseudo.
640 On machines with small register classes, record hard registers that
641 are used for user variables. These can never be used for spills.
642 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
643 caller-saved registers must be marked live. */
645 for (insn = first; insn; insn = NEXT_INSN (insn))
647 rtx set = single_set (insn);
649 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
650 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
652 if (! call_used_regs[i])
653 regs_ever_live[i] = 1;
655 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
657 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
659 #ifdef LEGITIMATE_PIC_OPERAND_P
660 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
661 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
665 rtx x = XEXP (note, 0);
666 i = REGNO (SET_DEST (set));
667 if (i > LAST_VIRTUAL_REGISTER)
669 if (GET_CODE (x) == MEM)
671 /* If the operand is a PLUS, the MEM may be shared,
672 so make sure we have an unshared copy here. */
673 if (GET_CODE (XEXP (x, 0)) == PLUS)
676 reg_equiv_memory_loc[i] = x;
678 else if (CONSTANT_P (x))
680 if (LEGITIMATE_CONSTANT_P (x))
681 reg_equiv_constant[i] = x;
683 reg_equiv_memory_loc[i]
684 = force_const_mem (GET_MODE (SET_DEST (set)), x);
689 /* If this register is being made equivalent to a MEM
690 and the MEM is not SET_SRC, the equivalencing insn
691 is one with the MEM as a SET_DEST and it occurs later.
692 So don't mark this insn now. */
693 if (GET_CODE (x) != MEM
694 || rtx_equal_p (SET_SRC (set), x))
695 reg_equiv_init[i] = insn;
700 /* If this insn is setting a MEM from a register equivalent to it,
701 this is the equivalencing insn. */
702 else if (set && GET_CODE (SET_DEST (set)) == MEM
703 && GET_CODE (SET_SRC (set)) == REG
704 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
705 && rtx_equal_p (SET_DEST (set),
706 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
707 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
709 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
710 scan_paradoxical_subregs (PATTERN (insn));
713 /* Does this function require a frame pointer? */
715 frame_pointer_needed = (! flag_omit_frame_pointer
716 #ifdef EXIT_IGNORE_STACK
717 /* ?? If EXIT_IGNORE_STACK is set, we will not save
718 and restore sp for alloca. So we can't eliminate
719 the frame pointer in that case. At some point,
720 we should improve this by emitting the
721 sp-adjusting insns for this case. */
722 || (current_function_calls_alloca
723 && EXIT_IGNORE_STACK)
725 || FRAME_POINTER_REQUIRED);
729 /* Initialize the table of registers to eliminate. The way we do this
730 depends on how the eliminable registers were defined. */
731 #ifdef ELIMINABLE_REGS
732 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
734 ep->can_eliminate = ep->can_eliminate_previous
735 = (CAN_ELIMINATE (ep->from, ep->to)
736 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
739 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
740 = ! frame_pointer_needed;
743 /* Count the number of eliminable registers and build the FROM and TO
744 REG rtx's. Note that code in gen_rtx will cause, e.g.,
745 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
746 We depend on this. */
747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
749 num_eliminable += ep->can_eliminate;
750 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
751 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
754 num_labels = max_label_num () - get_first_label_num ();
756 /* Allocate the tables used to store offset information at labels. */
757 /* We used to use alloca here, but the size of what it would try to
758 allocate would occasionally cause it to exceed the stack limit and
759 cause a core dump. */
760 real_known_ptr = xmalloc (num_labels);
762 = (int (*)[NUM_ELIMINABLE_REGS])
763 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
765 offsets_known_at = real_known_ptr - get_first_label_num ();
767 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
769 /* Alter each pseudo-reg rtx to contain its hard reg number.
770 Assign stack slots to the pseudos that lack hard regs or equivalents.
771 Do not touch virtual registers. */
773 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
776 /* If we have some registers we think can be eliminated, scan all insns to
777 see if there is an insn that sets one of these registers to something
778 other than itself plus a constant. If so, the register cannot be
779 eliminated. Doing this scan here eliminates an extra pass through the
780 main reload loop in the most common case where register elimination
782 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
783 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
784 || GET_CODE (insn) == CALL_INSN)
785 note_stores (PATTERN (insn), mark_not_eliminable);
787 #ifndef REGISTER_CONSTRAINTS
788 /* If all the pseudo regs have hard regs,
789 except for those that are never referenced,
790 we know that no reloads are needed. */
791 /* But that is not true if there are register constraints, since
792 in that case some pseudos might be in the wrong kind of hard reg. */
794 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
795 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
798 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
800 free (real_known_ptr);
806 /* Compute the order of preference for hard registers to spill.
807 Store them by decreasing preference in potential_reload_regs. */
809 order_regs_for_reload (global);
811 /* So far, no hard regs have been spilled. */
813 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
814 spill_reg_order[i] = -1;
816 /* Initialize to -1, which means take the first spill register. */
819 /* On most machines, we can't use any register explicitly used in the
820 rtl as a spill register. But on some, we have to. Those will have
821 taken care to keep the life of hard regs as short as possible. */
823 if (! SMALL_REGISTER_CLASSES)
824 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
826 /* Spill any hard regs that we know we can't eliminate. */
827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
828 if (! ep->can_eliminate)
829 spill_hard_reg (ep->from, global, dumpfile, 1);
831 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
832 if (frame_pointer_needed)
833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
837 for (i = 0; i < N_REG_CLASSES; i++)
839 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
840 bzero (basic_block_needs[i], n_basic_blocks);
843 /* From now on, we need to emit any moves without making new pseudos. */
844 reload_in_progress = 1;
846 /* This loop scans the entire function each go-round
847 and repeats until one repetition spills no additional hard regs. */
849 /* This flag is set when a pseudo reg is spilled,
850 to require another pass. Note that getting an additional reload
851 reg does not necessarily imply any pseudo reg was spilled;
852 sometimes we find a reload reg that no pseudo reg was allocated in. */
853 something_changed = 1;
854 /* This flag is set if there are any insns that require reloading. */
855 something_needs_reloads = 0;
856 /* This flag is set if there are any insns that require register
858 something_needs_elimination = 0;
859 while (something_changed)
863 /* For each class, number of reload regs needed in that class.
864 This is the maximum over all insns of the needs in that class
865 of the individual insn. */
866 int max_needs[N_REG_CLASSES];
867 /* For each class, size of group of consecutive regs
868 that is needed for the reloads of this class. */
869 int group_size[N_REG_CLASSES];
870 /* For each class, max number of consecutive groups needed.
871 (Each group contains group_size[CLASS] consecutive registers.) */
872 int max_groups[N_REG_CLASSES];
873 /* For each class, max number needed of regs that don't belong
874 to any of the groups. */
875 int max_nongroups[N_REG_CLASSES];
876 /* For each class, the machine mode which requires consecutive
877 groups of regs of that class.
878 If two different modes ever require groups of one class,
879 they must be the same size and equally restrictive for that class,
880 otherwise we can't handle the complexity. */
881 enum machine_mode group_mode[N_REG_CLASSES];
882 /* Record the insn where each maximum need is first found. */
883 rtx max_needs_insn[N_REG_CLASSES];
884 rtx max_groups_insn[N_REG_CLASSES];
885 rtx max_nongroups_insn[N_REG_CLASSES];
887 HOST_WIDE_INT starting_frame_size;
888 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
889 int previous_frame_pointer_needed = frame_pointer_needed;
891 static char *reg_class_names[] = REG_CLASS_NAMES;
893 something_changed = 0;
894 bzero ((char *) max_needs, sizeof max_needs);
895 bzero ((char *) max_groups, sizeof max_groups);
896 bzero ((char *) max_nongroups, sizeof max_nongroups);
897 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
898 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
899 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
900 bzero ((char *) group_size, sizeof group_size);
901 for (i = 0; i < N_REG_CLASSES; i++)
902 group_mode[i] = VOIDmode;
904 /* Keep track of which basic blocks are needing the reloads. */
907 /* Remember whether any element of basic_block_needs
908 changes from 0 to 1 in this pass. */
909 new_basic_block_needs = 0;
911 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
912 here because the stack size may be a part of the offset computation
913 for register elimination, and there might have been new stack slots
914 created in the last iteration of this loop. */
915 assign_stack_local (BLKmode, 0, 0);
917 starting_frame_size = get_frame_size ();
919 /* Reset all offsets on eliminable registers to their initial values. */
920 #ifdef ELIMINABLE_REGS
921 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
923 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
924 ep->previous_offset = ep->offset
925 = ep->max_offset = ep->initial_offset;
928 #ifdef INITIAL_FRAME_POINTER_OFFSET
929 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
931 if (!FRAME_POINTER_REQUIRED)
933 reg_eliminate[0].initial_offset = 0;
935 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
936 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
939 num_not_at_initial_offset = 0;
941 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
943 /* Set a known offset for each forced label to be at the initial offset
944 of each elimination. We do this because we assume that all
945 computed jumps occur from a location where each elimination is
946 at its initial offset. */
948 for (x = forced_labels; x; x = XEXP (x, 1))
950 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
952 /* For each pseudo register that has an equivalent location defined,
953 try to eliminate any eliminable registers (such as the frame pointer)
954 assuming initial offsets for the replacement register, which
957 If the resulting location is directly addressable, substitute
958 the MEM we just got directly for the old REG.
960 If it is not addressable but is a constant or the sum of a hard reg
961 and constant, it is probably not addressable because the constant is
962 out of range, in that case record the address; we will generate
963 hairy code to compute the address in a register each time it is
964 needed. Similarly if it is a hard register, but one that is not
965 valid as an address register.
967 If the location is not addressable, but does not have one of the
968 above forms, assign a stack slot. We have to do this to avoid the
969 potential of producing lots of reloads if, e.g., a location involves
970 a pseudo that didn't get a hard register and has an equivalent memory
971 location that also involves a pseudo that didn't get a hard register.
973 Perhaps at some point we will improve reload_when_needed handling
974 so this problem goes away. But that's very hairy. */
976 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
977 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
979 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
981 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
983 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
984 else if (CONSTANT_P (XEXP (x, 0))
985 || (GET_CODE (XEXP (x, 0)) == REG
986 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
987 || (GET_CODE (XEXP (x, 0)) == PLUS
988 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
989 && (REGNO (XEXP (XEXP (x, 0), 0))
990 < FIRST_PSEUDO_REGISTER)
991 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
992 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
995 /* Make a new stack slot. Then indicate that something
996 changed so we go back and recompute offsets for
997 eliminable registers because the allocation of memory
998 below might change some offset. reg_equiv_{mem,address}
999 will be set up for this pseudo on the next pass around
1001 reg_equiv_memory_loc[i] = 0;
1002 reg_equiv_init[i] = 0;
1004 something_changed = 1;
1008 /* If we allocated another pseudo to the stack, redo elimination
1010 if (something_changed)
1013 /* If caller-saves needs a group, initialize the group to include
1014 the size and mode required for caller-saves. */
1016 if (caller_save_group_size > 1)
1018 group_mode[(int) caller_save_spill_class] = Pmode;
1019 group_size[(int) caller_save_spill_class] = caller_save_group_size;
1022 /* Compute the most additional registers needed by any instruction.
1023 Collect information separately for each class of regs. */
1025 for (insn = first; insn; insn = NEXT_INSN (insn))
1027 if (global && this_block + 1 < n_basic_blocks
1028 && insn == basic_block_head[this_block+1])
1031 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1032 might include REG_LABEL), we need to see what effects this
1033 has on the known offsets at labels. */
1035 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1036 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1037 && REG_NOTES (insn) != 0))
1038 set_label_offsets (insn, insn, 0);
1040 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1042 /* Nonzero means don't use a reload reg that overlaps
1043 the place where a function value can be returned. */
1044 rtx avoid_return_reg = 0;
1046 rtx old_body = PATTERN (insn);
1047 int old_code = INSN_CODE (insn);
1048 rtx old_notes = REG_NOTES (insn);
1049 int did_elimination = 0;
1051 /* To compute the number of reload registers of each class
1052 needed for an insn, we must simulate what choose_reload_regs
1053 can do. We do this by splitting an insn into an "input" and
1054 an "output" part. RELOAD_OTHER reloads are used in both.
1055 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1056 which must be live over the entire input section of reloads,
1057 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1058 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1061 The registers needed for output are RELOAD_OTHER and
1062 RELOAD_FOR_OUTPUT, which are live for the entire output
1063 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1064 reloads for each operand.
1066 The total number of registers needed is the maximum of the
1067 inputs and outputs. */
1071 /* [0] is normal, [1] is nongroup. */
1072 int regs[2][N_REG_CLASSES];
1073 int groups[N_REG_CLASSES];
1076 /* Each `struct needs' corresponds to one RELOAD_... type. */
1080 struct needs output;
1082 struct needs other_addr;
1083 struct needs op_addr;
1084 struct needs op_addr_reload;
1085 struct needs in_addr[MAX_RECOG_OPERANDS];
1086 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1087 struct needs out_addr[MAX_RECOG_OPERANDS];
1088 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1091 /* If needed, eliminate any eliminable registers. */
1093 did_elimination = eliminate_regs_in_insn (insn, 0);
1095 /* Set avoid_return_reg if this is an insn
1096 that might use the value of a function call. */
1097 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1099 if (GET_CODE (PATTERN (insn)) == SET)
1100 after_call = SET_DEST (PATTERN (insn));
1101 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1102 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1103 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1107 else if (SMALL_REGISTER_CLASSES && after_call != 0
1108 && !(GET_CODE (PATTERN (insn)) == SET
1109 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
1110 && GET_CODE (PATTERN (insn)) != USE)
1112 if (reg_referenced_p (after_call, PATTERN (insn)))
1113 avoid_return_reg = after_call;
1117 /* Analyze the instruction. */
1118 find_reloads (insn, 0, spill_indirect_levels, global,
1121 /* Remember for later shortcuts which insns had any reloads or
1122 register eliminations.
1124 One might think that it would be worthwhile to mark insns
1125 that need register replacements but not reloads, but this is
1126 not safe because find_reloads may do some manipulation of
1127 the insn (such as swapping commutative operands), which would
1128 be lost when we restore the old pattern after register
1129 replacement. So the actions of find_reloads must be redone in
1130 subsequent passes or in reload_as_needed.
1132 However, it is safe to mark insns that need reloads
1133 but not register replacement. */
1135 PUT_MODE (insn, (did_elimination ? QImode
1136 : n_reloads ? HImode
1137 : GET_MODE (insn) == DImode ? DImode
1140 /* Discard any register replacements done. */
1141 if (did_elimination)
1143 obstack_free (&reload_obstack, reload_firstobj);
1144 PATTERN (insn) = old_body;
1145 INSN_CODE (insn) = old_code;
1146 REG_NOTES (insn) = old_notes;
1147 something_needs_elimination = 1;
1150 /* If this insn has no reloads, we need not do anything except
1151 in the case of a CALL_INSN when we have caller-saves and
1152 caller-save needs reloads. */
1155 && ! (GET_CODE (insn) == CALL_INSN
1156 && caller_save_spill_class != NO_REGS))
1159 something_needs_reloads = 1;
1160 bzero ((char *) &insn_needs, sizeof insn_needs);
1162 /* Count each reload once in every class
1163 containing the reload's own class. */
1165 for (i = 0; i < n_reloads; i++)
1167 register enum reg_class *p;
1168 enum reg_class class = reload_reg_class[i];
1170 enum machine_mode mode;
1171 struct needs *this_needs;
1173 /* Don't count the dummy reloads, for which one of the
1174 regs mentioned in the insn can be used for reloading.
1175 Don't count optional reloads.
1176 Don't count reloads that got combined with others. */
1177 if (reload_reg_rtx[i] != 0
1178 || reload_optional[i] != 0
1179 || (reload_out[i] == 0 && reload_in[i] == 0
1180 && ! reload_secondary_p[i]))
1183 /* Show that a reload register of this class is needed
1184 in this basic block. We do not use insn_needs and
1185 insn_groups because they are overly conservative for
1187 if (global && ! basic_block_needs[(int) class][this_block])
1189 basic_block_needs[(int) class][this_block] = 1;
1190 new_basic_block_needs = 1;
1193 mode = reload_inmode[i];
1194 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1195 mode = reload_outmode[i];
1196 size = CLASS_MAX_NREGS (class, mode);
1198 /* Decide which time-of-use to count this reload for. */
1199 switch (reload_when_needed[i])
1202 this_needs = &insn_needs.other;
1204 case RELOAD_FOR_INPUT:
1205 this_needs = &insn_needs.input;
1207 case RELOAD_FOR_OUTPUT:
1208 this_needs = &insn_needs.output;
1210 case RELOAD_FOR_INSN:
1211 this_needs = &insn_needs.insn;
1213 case RELOAD_FOR_OTHER_ADDRESS:
1214 this_needs = &insn_needs.other_addr;
1216 case RELOAD_FOR_INPUT_ADDRESS:
1217 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1219 case RELOAD_FOR_INPADDR_ADDRESS:
1220 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1222 case RELOAD_FOR_OUTPUT_ADDRESS:
1223 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1225 case RELOAD_FOR_OUTADDR_ADDRESS:
1226 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1228 case RELOAD_FOR_OPERAND_ADDRESS:
1229 this_needs = &insn_needs.op_addr;
1231 case RELOAD_FOR_OPADDR_ADDR:
1232 this_needs = &insn_needs.op_addr_reload;
1238 enum machine_mode other_mode, allocate_mode;
1240 /* Count number of groups needed separately from
1241 number of individual regs needed. */
1242 this_needs->groups[(int) class]++;
1243 p = reg_class_superclasses[(int) class];
1244 while (*p != LIM_REG_CLASSES)
1245 this_needs->groups[(int) *p++]++;
1247 /* Record size and mode of a group of this class. */
1248 /* If more than one size group is needed,
1249 make all groups the largest needed size. */
1250 if (group_size[(int) class] < size)
1252 other_mode = group_mode[(int) class];
1253 allocate_mode = mode;
1255 group_size[(int) class] = size;
1256 group_mode[(int) class] = mode;
1261 allocate_mode = group_mode[(int) class];
1264 /* Crash if two dissimilar machine modes both need
1265 groups of consecutive regs of the same class. */
1267 if (other_mode != VOIDmode && other_mode != allocate_mode
1268 && ! modes_equiv_for_class_p (allocate_mode,
1270 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1275 this_needs->regs[reload_nongroup[i]][(int) class] += 1;
1276 p = reg_class_superclasses[(int) class];
1277 while (*p != LIM_REG_CLASSES)
1278 this_needs->regs[reload_nongroup[i]][(int) *p++] += 1;
1284 /* All reloads have been counted for this insn;
1285 now merge the various times of use.
1286 This sets insn_needs, etc., to the maximum total number
1287 of registers needed at any point in this insn. */
1289 for (i = 0; i < N_REG_CLASSES; i++)
1291 int in_max, out_max;
1293 /* Compute normal and nongroup needs. */
1294 for (j = 0; j <= 1; j++)
1296 for (in_max = 0, out_max = 0, k = 0;
1297 k < reload_n_operands; k++)
1301 (insn_needs.in_addr[k].regs[j][i]
1302 + insn_needs.in_addr_addr[k].regs[j][i]));
1304 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1307 insn_needs.out_addr_addr[k].regs[j][i]);
1310 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1311 and operand addresses but not things used to reload
1312 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1313 don't conflict with things needed to reload inputs or
1316 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1317 insn_needs.op_addr_reload.regs[j][i]),
1320 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1322 insn_needs.input.regs[j][i]
1323 = MAX (insn_needs.input.regs[j][i]
1324 + insn_needs.op_addr.regs[j][i]
1325 + insn_needs.insn.regs[j][i],
1326 in_max + insn_needs.input.regs[j][i]);
1328 insn_needs.output.regs[j][i] += out_max;
1329 insn_needs.other.regs[j][i]
1330 += MAX (MAX (insn_needs.input.regs[j][i],
1331 insn_needs.output.regs[j][i]),
1332 insn_needs.other_addr.regs[j][i]);
1336 /* Now compute group needs. */
1337 for (in_max = 0, out_max = 0, j = 0;
1338 j < reload_n_operands; j++)
1340 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1341 in_max = MAX (in_max,
1342 insn_needs.in_addr_addr[j].groups[i]);
1344 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1346 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1349 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1350 insn_needs.op_addr_reload.groups[i]),
1352 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1354 insn_needs.input.groups[i]
1355 = MAX (insn_needs.input.groups[i]
1356 + insn_needs.op_addr.groups[i]
1357 + insn_needs.insn.groups[i],
1358 in_max + insn_needs.input.groups[i]);
1360 insn_needs.output.groups[i] += out_max;
1361 insn_needs.other.groups[i]
1362 += MAX (MAX (insn_needs.input.groups[i],
1363 insn_needs.output.groups[i]),
1364 insn_needs.other_addr.groups[i]);
1367 /* If this is a CALL_INSN and caller-saves will need
1368 a spill register, act as if the spill register is
1369 needed for this insn. However, the spill register
1370 can be used by any reload of this insn, so we only
1371 need do something if no need for that class has
1374 The assumption that every CALL_INSN will trigger a
1375 caller-save is highly conservative, however, the number
1376 of cases where caller-saves will need a spill register but
1377 a block containing a CALL_INSN won't need a spill register
1378 of that class should be quite rare.
1380 If a group is needed, the size and mode of the group will
1381 have been set up at the beginning of this loop. */
1383 if (GET_CODE (insn) == CALL_INSN
1384 && caller_save_spill_class != NO_REGS)
1386 /* See if this register would conflict with any reload that
1387 needs a group or any reload that needs a nongroup. */
1388 int nongroup_need = 0;
1389 int *caller_save_needs;
1391 for (j = 0; j < n_reloads; j++)
1392 if (reg_classes_intersect_p (caller_save_spill_class,
1393 reload_reg_class[j])
1394 && ((CLASS_MAX_NREGS
1395 (reload_reg_class[j],
1396 (GET_MODE_SIZE (reload_outmode[j])
1397 > GET_MODE_SIZE (reload_inmode[j]))
1398 ? reload_outmode[j] : reload_inmode[j])
1400 || reload_nongroup[j]))
1407 = (caller_save_group_size > 1
1408 ? insn_needs.other.groups
1409 : insn_needs.other.regs[nongroup_need]);
1411 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1413 register enum reg_class *p
1414 = reg_class_superclasses[(int) caller_save_spill_class];
1416 caller_save_needs[(int) caller_save_spill_class]++;
1418 while (*p != LIM_REG_CLASSES)
1419 caller_save_needs[(int) *p++] += 1;
1422 /* Show that this basic block will need a register of
1426 && ! (basic_block_needs[(int) caller_save_spill_class]
1429 basic_block_needs[(int) caller_save_spill_class]
1431 new_basic_block_needs = 1;
1435 /* If this insn stores the value of a function call,
1436 and that value is in a register that has been spilled,
1437 and if the insn needs a reload in a class
1438 that might use that register as the reload register,
1439 then add an extra need in that class.
1440 This makes sure we have a register available that does
1441 not overlap the return value. */
1443 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1445 int regno = REGNO (avoid_return_reg);
1447 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1449 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1451 /* First compute the "basic needs", which counts a
1452 need only in the smallest class in which it
1455 bcopy ((char *) insn_needs.other.regs[0],
1456 (char *) basic_needs, sizeof basic_needs);
1457 bcopy ((char *) insn_needs.other.groups,
1458 (char *) basic_groups, sizeof basic_groups);
1460 for (i = 0; i < N_REG_CLASSES; i++)
1464 if (basic_needs[i] >= 0)
1465 for (p = reg_class_superclasses[i];
1466 *p != LIM_REG_CLASSES; p++)
1467 basic_needs[(int) *p] -= basic_needs[i];
1469 if (basic_groups[i] >= 0)
1470 for (p = reg_class_superclasses[i];
1471 *p != LIM_REG_CLASSES; p++)
1472 basic_groups[(int) *p] -= basic_groups[i];
1475 /* Now count extra regs if there might be a conflict with
1476 the return value register. */
1478 for (r = regno; r < regno + nregs; r++)
1479 if (spill_reg_order[r] >= 0)
1480 for (i = 0; i < N_REG_CLASSES; i++)
1481 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1483 if (basic_needs[i] > 0)
1487 insn_needs.other.regs[0][i]++;
1488 p = reg_class_superclasses[i];
1489 while (*p != LIM_REG_CLASSES)
1490 insn_needs.other.regs[0][(int) *p++]++;
1492 if (basic_groups[i] > 0)
1496 insn_needs.other.groups[i]++;
1497 p = reg_class_superclasses[i];
1498 while (*p != LIM_REG_CLASSES)
1499 insn_needs.other.groups[(int) *p++]++;
1504 /* For each class, collect maximum need of any insn. */
1506 for (i = 0; i < N_REG_CLASSES; i++)
1508 if (max_needs[i] < insn_needs.other.regs[0][i])
1510 max_needs[i] = insn_needs.other.regs[0][i];
1511 max_needs_insn[i] = insn;
1513 if (max_groups[i] < insn_needs.other.groups[i])
1515 max_groups[i] = insn_needs.other.groups[i];
1516 max_groups_insn[i] = insn;
1518 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1520 max_nongroups[i] = insn_needs.other.regs[1][i];
1521 max_nongroups_insn[i] = insn;
1525 /* Note that there is a continue statement above. */
1528 /* If we allocated any new memory locations, make another pass
1529 since it might have changed elimination offsets. */
1530 if (starting_frame_size != get_frame_size ())
1531 something_changed = 1;
1534 for (i = 0; i < N_REG_CLASSES; i++)
1536 if (max_needs[i] > 0)
1538 ";; Need %d reg%s of class %s (for insn %d).\n",
1539 max_needs[i], max_needs[i] == 1 ? "" : "s",
1540 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1541 if (max_nongroups[i] > 0)
1543 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1544 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1545 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1546 if (max_groups[i] > 0)
1548 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1549 max_groups[i], max_groups[i] == 1 ? "" : "s",
1550 mode_name[(int) group_mode[i]],
1551 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1554 /* If we have caller-saves, set up the save areas and see if caller-save
1555 will need a spill register. */
1557 if (caller_save_needed)
1559 /* Set the offsets for setup_save_areas. */
1560 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1562 ep->previous_offset = ep->max_offset;
1564 if ( ! setup_save_areas (&something_changed)
1565 && caller_save_spill_class == NO_REGS)
1567 /* The class we will need depends on whether the machine
1568 supports the sum of two registers for an address; see
1569 find_address_reloads for details. */
1571 caller_save_spill_class
1572 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1573 caller_save_group_size
1574 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1575 something_changed = 1;
1579 /* See if anything that happened changes which eliminations are valid.
1580 For example, on the Sparc, whether or not the frame pointer can
1581 be eliminated can depend on what registers have been used. We need
1582 not check some conditions again (such as flag_omit_frame_pointer)
1583 since they can't have changed. */
1585 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1586 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1587 #ifdef ELIMINABLE_REGS
1588 || ! CAN_ELIMINATE (ep->from, ep->to)
1591 ep->can_eliminate = 0;
1593 /* Look for the case where we have discovered that we can't replace
1594 register A with register B and that means that we will now be
1595 trying to replace register A with register C. This means we can
1596 no longer replace register C with register B and we need to disable
1597 such an elimination, if it exists. This occurs often with A == ap,
1598 B == sp, and C == fp. */
1600 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1602 struct elim_table *op;
1603 register int new_to = -1;
1605 if (! ep->can_eliminate && ep->can_eliminate_previous)
1607 /* Find the current elimination for ep->from, if there is a
1609 for (op = reg_eliminate;
1610 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1611 if (op->from == ep->from && op->can_eliminate)
1617 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1619 for (op = reg_eliminate;
1620 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1621 if (op->from == new_to && op->to == ep->to)
1622 op->can_eliminate = 0;
1626 /* See if any registers that we thought we could eliminate the previous
1627 time are no longer eliminable. If so, something has changed and we
1628 must spill the register. Also, recompute the number of eliminable
1629 registers and see if the frame pointer is needed; it is if there is
1630 no elimination of the frame pointer that we can perform. */
1632 frame_pointer_needed = 1;
1633 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1635 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1636 && ep->to != HARD_FRAME_POINTER_REGNUM)
1637 frame_pointer_needed = 0;
1639 if (! ep->can_eliminate && ep->can_eliminate_previous)
1641 ep->can_eliminate_previous = 0;
1642 spill_hard_reg (ep->from, global, dumpfile, 1);
1643 something_changed = 1;
1648 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1649 /* If we didn't need a frame pointer last time, but we do now, spill
1650 the hard frame pointer. */
1651 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1653 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1654 something_changed = 1;
1658 /* If all needs are met, we win. */
1660 for (i = 0; i < N_REG_CLASSES; i++)
1661 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1663 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1666 /* Not all needs are met; must spill some hard regs. */
1668 /* Put all registers spilled so far back in potential_reload_regs, but
1669 put them at the front, since we've already spilled most of the
1670 pseudos in them (we might have left some pseudos unspilled if they
1671 were in a block that didn't need any spill registers of a conflicting
1672 class. We used to try to mark off the need for those registers,
1673 but doing so properly is very complex and reallocating them is the
1674 simpler approach. First, "pack" potential_reload_regs by pushing
1675 any nonnegative entries towards the end. That will leave room
1676 for the registers we already spilled.
1678 Also, undo the marking of the spill registers from the last time
1679 around in FORBIDDEN_REGS since we will be probably be allocating
1682 ??? It is theoretically possible that we might end up not using one
1683 of our previously-spilled registers in this allocation, even though
1684 they are at the head of the list. It's not clear what to do about
1685 this, but it was no better before, when we marked off the needs met
1686 by the previously-spilled registers. With the current code, globals
1687 can be allocated into these registers, but locals cannot. */
1691 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1692 if (potential_reload_regs[i] != -1)
1693 potential_reload_regs[j--] = potential_reload_regs[i];
1695 for (i = 0; i < n_spills; i++)
1697 potential_reload_regs[i] = spill_regs[i];
1698 spill_reg_order[spill_regs[i]] = -1;
1699 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1705 /* Now find more reload regs to satisfy the remaining need
1706 Do it by ascending class number, since otherwise a reg
1707 might be spilled for a big class and might fail to count
1708 for a smaller class even though it belongs to that class.
1710 Count spilled regs in `spills', and add entries to
1711 `spill_regs' and `spill_reg_order'.
1713 ??? Note there is a problem here.
1714 When there is a need for a group in a high-numbered class,
1715 and also need for non-group regs that come from a lower class,
1716 the non-group regs are chosen first. If there aren't many regs,
1717 they might leave no room for a group.
1719 This was happening on the 386. To fix it, we added the code
1720 that calls possible_group_p, so that the lower class won't
1721 break up the last possible group.
1723 Really fixing the problem would require changes above
1724 in counting the regs already spilled, and in choose_reload_regs.
1725 It might be hard to avoid introducing bugs there. */
1727 CLEAR_HARD_REG_SET (counted_for_groups);
1728 CLEAR_HARD_REG_SET (counted_for_nongroups);
1730 for (class = 0; class < N_REG_CLASSES; class++)
1732 /* First get the groups of registers.
1733 If we got single registers first, we might fragment
1735 while (max_groups[class] > 0)
1737 /* If any single spilled regs happen to form groups,
1738 count them now. Maybe we don't really need
1739 to spill another group. */
1740 count_possible_groups (group_size, group_mode, max_groups,
1743 if (max_groups[class] <= 0)
1746 /* Groups of size 2 (the only groups used on most machines)
1747 are treated specially. */
1748 if (group_size[class] == 2)
1750 /* First, look for a register that will complete a group. */
1751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1755 j = potential_reload_regs[i];
1756 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1758 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1759 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1760 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1761 && HARD_REGNO_MODE_OK (other, group_mode[class])
1762 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1764 /* We don't want one part of another group.
1765 We could get "two groups" that overlap! */
1766 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1768 (j < FIRST_PSEUDO_REGISTER - 1
1769 && (other = j + 1, spill_reg_order[other] >= 0)
1770 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1771 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1772 && HARD_REGNO_MODE_OK (j, group_mode[class])
1773 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1775 && ! TEST_HARD_REG_BIT (counted_for_groups,
1778 register enum reg_class *p;
1780 /* We have found one that will complete a group,
1781 so count off one group as provided. */
1782 max_groups[class]--;
1783 p = reg_class_superclasses[class];
1784 while (*p != LIM_REG_CLASSES)
1786 if (group_size [(int) *p] <= group_size [class])
1787 max_groups[(int) *p]--;
1791 /* Indicate both these regs are part of a group. */
1792 SET_HARD_REG_BIT (counted_for_groups, j);
1793 SET_HARD_REG_BIT (counted_for_groups, other);
1797 /* We can't complete a group, so start one. */
1798 /* Look for a pair neither of which is explicitly used. */
1799 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1800 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1803 j = potential_reload_regs[i];
1804 /* Verify that J+1 is a potential reload reg. */
1805 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1806 if (potential_reload_regs[k] == j + 1)
1808 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1809 && k < FIRST_PSEUDO_REGISTER
1810 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1811 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1812 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1813 && HARD_REGNO_MODE_OK (j, group_mode[class])
1814 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1816 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1817 /* Reject J at this stage
1818 if J+1 was explicitly used. */
1819 && ! regs_explicitly_used[j + 1])
1822 /* Now try any group at all
1823 whose registers are not in bad_spill_regs. */
1824 if (i == FIRST_PSEUDO_REGISTER)
1825 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1828 j = potential_reload_regs[i];
1829 /* Verify that J+1 is a potential reload reg. */
1830 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1831 if (potential_reload_regs[k] == j + 1)
1833 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1834 && k < FIRST_PSEUDO_REGISTER
1835 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1836 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1837 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1838 && HARD_REGNO_MODE_OK (j, group_mode[class])
1839 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1841 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1845 /* I should be the index in potential_reload_regs
1846 of the new reload reg we have found. */
1848 if (i >= FIRST_PSEUDO_REGISTER)
1850 /* There are no groups left to spill. */
1851 spill_failure (max_groups_insn[class]);
1857 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1862 /* For groups of more than 2 registers,
1863 look for a sufficient sequence of unspilled registers,
1864 and spill them all at once. */
1865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1869 j = potential_reload_regs[i];
1871 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1872 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1874 /* Check each reg in the sequence. */
1875 for (k = 0; k < group_size[class]; k++)
1876 if (! (spill_reg_order[j + k] < 0
1877 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1878 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1880 /* We got a full sequence, so spill them all. */
1881 if (k == group_size[class])
1883 register enum reg_class *p;
1884 for (k = 0; k < group_size[class]; k++)
1887 SET_HARD_REG_BIT (counted_for_groups, j + k);
1888 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1889 if (potential_reload_regs[idx] == j + k)
1892 |= new_spill_reg (idx, class,
1893 max_needs, NULL_PTR,
1897 /* We have found one that will complete a group,
1898 so count off one group as provided. */
1899 max_groups[class]--;
1900 p = reg_class_superclasses[class];
1901 while (*p != LIM_REG_CLASSES)
1903 if (group_size [(int) *p]
1904 <= group_size [class])
1905 max_groups[(int) *p]--;
1912 /* We couldn't find any registers for this reload.
1913 Avoid going into an infinite loop. */
1914 if (i >= FIRST_PSEUDO_REGISTER)
1916 /* There are no groups left. */
1917 spill_failure (max_groups_insn[class]);
1924 /* Now similarly satisfy all need for single registers. */
1926 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1928 /* If we spilled enough regs, but they weren't counted
1929 against the non-group need, see if we can count them now.
1930 If so, we can avoid some actual spilling. */
1931 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1932 for (i = 0; i < n_spills; i++)
1933 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1935 && !TEST_HARD_REG_BIT (counted_for_groups,
1937 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1939 && max_nongroups[class] > 0)
1941 register enum reg_class *p;
1943 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1944 max_nongroups[class]--;
1945 p = reg_class_superclasses[class];
1946 while (*p != LIM_REG_CLASSES)
1947 max_nongroups[(int) *p++]--;
1949 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1952 /* Consider the potential reload regs that aren't
1953 yet in use as reload regs, in order of preference.
1954 Find the most preferred one that's in this class. */
1956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1957 if (potential_reload_regs[i] >= 0
1958 && TEST_HARD_REG_BIT (reg_class_contents[class],
1959 potential_reload_regs[i])
1960 /* If this reg will not be available for groups,
1961 pick one that does not foreclose possible groups.
1962 This is a kludge, and not very general,
1963 but it should be sufficient to make the 386 work,
1964 and the problem should not occur on machines with
1966 && (max_nongroups[class] == 0
1967 || possible_group_p (potential_reload_regs[i], max_groups)))
1970 /* If we couldn't get a register, try to get one even if we
1971 might foreclose possible groups. This may cause problems
1972 later, but that's better than aborting now, since it is
1973 possible that we will, in fact, be able to form the needed
1974 group even with this allocation. */
1976 if (i >= FIRST_PSEUDO_REGISTER
1977 && (asm_noperands (max_needs[class] > 0
1978 ? max_needs_insn[class]
1979 : max_nongroups_insn[class])
1981 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1982 if (potential_reload_regs[i] >= 0
1983 && TEST_HARD_REG_BIT (reg_class_contents[class],
1984 potential_reload_regs[i]))
1987 /* I should be the index in potential_reload_regs
1988 of the new reload reg we have found. */
1990 if (i >= FIRST_PSEUDO_REGISTER)
1992 /* There are no possible registers left to spill. */
1993 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1994 : max_nongroups_insn[class]);
2000 |= new_spill_reg (i, class, max_needs, max_nongroups,
2006 /* If global-alloc was run, notify it of any register eliminations we have
2009 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2010 if (ep->can_eliminate)
2011 mark_elimination (ep->from, ep->to);
2013 /* Insert code to save and restore call-clobbered hard regs
2014 around calls. Tell if what mode to use so that we will process
2015 those insns in reload_as_needed if we have to. */
2017 if (caller_save_needed)
2018 save_call_clobbered_regs (num_eliminable ? QImode
2019 : caller_save_spill_class != NO_REGS ? HImode
2022 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2023 If that insn didn't set the register (i.e., it copied the register to
2024 memory), just delete that insn instead of the equivalencing insn plus
2025 anything now dead. If we call delete_dead_insn on that insn, we may
2026 delete the insn that actually sets the register if the register die
2027 there and that is incorrect. */
2029 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2031 && GET_CODE (reg_equiv_init[i]) != NOTE)
2033 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2034 delete_dead_insn (reg_equiv_init[i]);
2037 PUT_CODE (reg_equiv_init[i], NOTE);
2038 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2039 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2043 /* Use the reload registers where necessary
2044 by generating move instructions to move the must-be-register
2045 values into or out of the reload registers. */
2047 if (something_needs_reloads || something_needs_elimination
2048 || (caller_save_needed && num_eliminable)
2049 || caller_save_spill_class != NO_REGS)
2050 reload_as_needed (first, global);
2052 /* If we were able to eliminate the frame pointer, show that it is no
2053 longer live at the start of any basic block. If it ls live by
2054 virtue of being in a pseudo, that pseudo will be marked live
2055 and hence the frame pointer will be known to be live via that
2058 if (! frame_pointer_needed)
2059 for (i = 0; i < n_basic_blocks; i++)
2060 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
2061 HARD_FRAME_POINTER_REGNUM);
2063 /* Come here (with failure set nonzero) if we can't get enough spill regs
2064 and we decide not to abort about it. */
2067 reload_in_progress = 0;
2069 /* Now eliminate all pseudo regs by modifying them into
2070 their equivalent memory references.
2071 The REG-rtx's for the pseudos are modified in place,
2072 so all insns that used to refer to them now refer to memory.
2074 For a reg that has a reg_equiv_address, all those insns
2075 were changed by reloading so that no insns refer to it any longer;
2076 but the DECL_RTL of a variable decl may refer to it,
2077 and if so this causes the debugging info to mention the variable. */
2079 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2083 int is_readonly = 0;
2085 if (reg_equiv_memory_loc[i])
2087 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
2088 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
2091 if (reg_equiv_mem[i])
2092 addr = XEXP (reg_equiv_mem[i], 0);
2094 if (reg_equiv_address[i])
2095 addr = reg_equiv_address[i];
2099 if (reg_renumber[i] < 0)
2101 rtx reg = regno_reg_rtx[i];
2102 XEXP (reg, 0) = addr;
2103 REG_USERVAR_P (reg) = 0;
2104 RTX_UNCHANGING_P (reg) = is_readonly;
2105 MEM_IN_STRUCT_P (reg) = in_struct;
2106 /* We have no alias information about this newly created
2108 MEM_ALIAS_SET (reg) = 0;
2109 PUT_CODE (reg, MEM);
2111 else if (reg_equiv_mem[i])
2112 XEXP (reg_equiv_mem[i], 0) = addr;
2116 /* Make a pass over all the insns and delete all USEs which we inserted
2117 only to tag a REG_EQUAL note on them; if PRESERVE_DEATH_INFO_REGNO_P
2118 is defined, also remove death notes for things that are no longer
2119 registers or no longer die in the insn (e.g., an input and output
2120 pseudo being tied). */
2122 for (insn = first; insn; insn = NEXT_INSN (insn))
2123 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2125 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2129 if (GET_CODE (PATTERN (insn)) == USE
2130 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
2132 PUT_CODE (insn, NOTE);
2133 NOTE_SOURCE_FILE (insn) = 0;
2134 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2137 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2138 for (note = REG_NOTES (insn); note; note = next)
2140 next = XEXP (note, 1);
2141 if (REG_NOTE_KIND (note) == REG_DEAD
2142 && (GET_CODE (XEXP (note, 0)) != REG
2143 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2144 remove_note (insn, note);
2149 /* If we are doing stack checking, give a warning if this function's
2150 frame size is larger than we expect. */
2151 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
2153 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
2155 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2156 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
2157 size += UNITS_PER_WORD;
2159 if (size > STACK_CHECK_MAX_FRAME_SIZE)
2160 warning ("frame size too large for reliable stack checking");
2163 /* Indicate that we no longer have known memory locations or constants. */
2164 reg_equiv_constant = 0;
2165 reg_equiv_memory_loc = 0;
2168 free (real_known_ptr);
2173 free (scratch_list);
2176 free (scratch_block);
2179 CLEAR_HARD_REG_SET (used_spill_regs);
2180 for (i = 0; i < n_spills; i++)
2181 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2186 /* Nonzero if, after spilling reg REGNO for non-groups,
2187 it will still be possible to find a group if we still need one. */
2190 possible_group_p (regno, max_groups)
2195 int class = (int) NO_REGS;
2197 for (i = 0; i < (int) N_REG_CLASSES; i++)
2198 if (max_groups[i] > 0)
2204 if (class == (int) NO_REGS)
2207 /* Consider each pair of consecutive registers. */
2208 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2210 /* Ignore pairs that include reg REGNO. */
2211 if (i == regno || i + 1 == regno)
2214 /* Ignore pairs that are outside the class that needs the group.
2215 ??? Here we fail to handle the case where two different classes
2216 independently need groups. But this never happens with our
2217 current machine descriptions. */
2218 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2219 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2222 /* A pair of consecutive regs we can still spill does the trick. */
2223 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2224 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2225 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2228 /* A pair of one already spilled and one we can spill does it
2229 provided the one already spilled is not otherwise reserved. */
2230 if (spill_reg_order[i] < 0
2231 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2232 && spill_reg_order[i + 1] >= 0
2233 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2234 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2236 if (spill_reg_order[i + 1] < 0
2237 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2238 && spill_reg_order[i] >= 0
2239 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2240 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2247 /* Count any groups of CLASS that can be formed from the registers recently
2251 count_possible_groups (group_size, group_mode, max_groups, class)
2253 enum machine_mode *group_mode;
2260 /* Now find all consecutive groups of spilled registers
2261 and mark each group off against the need for such groups.
2262 But don't count them against ordinary need, yet. */
2264 if (group_size[class] == 0)
2267 CLEAR_HARD_REG_SET (new);
2269 /* Make a mask of all the regs that are spill regs in class I. */
2270 for (i = 0; i < n_spills; i++)
2271 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2272 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2273 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2274 SET_HARD_REG_BIT (new, spill_regs[i]);
2276 /* Find each consecutive group of them. */
2277 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2278 if (TEST_HARD_REG_BIT (new, i)
2279 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2280 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2282 for (j = 1; j < group_size[class]; j++)
2283 if (! TEST_HARD_REG_BIT (new, i + j))
2286 if (j == group_size[class])
2288 /* We found a group. Mark it off against this class's need for
2289 groups, and against each superclass too. */
2290 register enum reg_class *p;
2292 max_groups[class]--;
2293 p = reg_class_superclasses[class];
2294 while (*p != LIM_REG_CLASSES)
2296 if (group_size [(int) *p] <= group_size [class])
2297 max_groups[(int) *p]--;
2301 /* Don't count these registers again. */
2302 for (j = 0; j < group_size[class]; j++)
2303 SET_HARD_REG_BIT (counted_for_groups, i + j);
2306 /* Skip to the last reg in this group. When i is incremented above,
2307 it will then point to the first reg of the next possible group. */
2312 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2313 another mode that needs to be reloaded for the same register class CLASS.
2314 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2315 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2317 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2318 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2319 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2320 causes unnecessary failures on machines requiring alignment of register
2321 groups when the two modes are different sizes, because the larger mode has
2322 more strict alignment rules than the smaller mode. */
2325 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2326 enum machine_mode allocate_mode, other_mode;
2327 enum reg_class class;
2330 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2332 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2333 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2334 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2340 /* Handle the failure to find a register to spill.
2341 INSN should be one of the insns which needed this particular spill reg. */
2344 spill_failure (insn)
2347 if (asm_noperands (PATTERN (insn)) >= 0)
2348 error_for_asm (insn, "`asm' needs too many reloads");
2350 fatal_insn ("Unable to find a register to spill.", insn);
2353 /* Add a new register to the tables of available spill-registers
2354 (as well as spilling all pseudos allocated to the register).
2355 I is the index of this register in potential_reload_regs.
2356 CLASS is the regclass whose need is being satisfied.
2357 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2358 so that this register can count off against them.
2359 MAX_NONGROUPS is 0 if this register is part of a group.
2360 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2363 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2371 register enum reg_class *p;
2373 int regno = potential_reload_regs[i];
2375 if (i >= FIRST_PSEUDO_REGISTER)
2376 abort (); /* Caller failed to find any register. */
2378 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2380 static char *reg_class_names[] = REG_CLASS_NAMES;
2381 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\
2382 This may be due to a compiler bug or to impossible asm\n\
2383 statements or clauses.", regno, reg_names[regno], reg_class_names[class]);
2386 /* Make reg REGNO an additional reload reg. */
2388 potential_reload_regs[i] = -1;
2389 spill_regs[n_spills] = regno;
2390 spill_reg_order[regno] = n_spills;
2392 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2394 /* Clear off the needs we just satisfied. */
2397 p = reg_class_superclasses[class];
2398 while (*p != LIM_REG_CLASSES)
2399 max_needs[(int) *p++]--;
2401 if (max_nongroups && max_nongroups[class] > 0)
2403 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2404 max_nongroups[class]--;
2405 p = reg_class_superclasses[class];
2406 while (*p != LIM_REG_CLASSES)
2407 max_nongroups[(int) *p++]--;
2410 /* Spill every pseudo reg that was allocated to this reg
2411 or to something that overlaps this reg. */
2413 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2415 /* If there are some registers still to eliminate and this register
2416 wasn't ever used before, additional stack space may have to be
2417 allocated to store this register. Thus, we may have changed the offset
2418 between the stack and frame pointers, so mark that something has changed.
2419 (If new pseudos were spilled, thus requiring more space, VAL would have
2420 been set non-zero by the call to spill_hard_reg above since additional
2421 reloads may be needed in that case.
2423 One might think that we need only set VAL to 1 if this is a call-used
2424 register. However, the set of registers that must be saved by the
2425 prologue is not identical to the call-used set. For example, the
2426 register used by the call insn for the return PC is a call-used register,
2427 but must be saved by the prologue. */
2428 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2431 regs_ever_live[spill_regs[n_spills]] = 1;
2437 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2438 data that is dead in INSN. */
2441 delete_dead_insn (insn)
2444 rtx prev = prev_real_insn (insn);
2447 /* If the previous insn sets a register that dies in our insn, delete it
2449 if (prev && GET_CODE (PATTERN (prev)) == SET
2450 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2451 && reg_mentioned_p (prev_dest, PATTERN (insn))
2452 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2453 delete_dead_insn (prev);
2455 PUT_CODE (insn, NOTE);
2456 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2457 NOTE_SOURCE_FILE (insn) = 0;
2460 /* Modify the home of pseudo-reg I.
2461 The new home is present in reg_renumber[I].
2463 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2464 or it may be -1, meaning there is none or it is not relevant.
2465 This is used so that all pseudos spilled from a given hard reg
2466 can share one stack slot. */
2469 alter_reg (i, from_reg)
2473 /* When outputting an inline function, this can happen
2474 for a reg that isn't actually used. */
2475 if (regno_reg_rtx[i] == 0)
2478 /* If the reg got changed to a MEM at rtl-generation time,
2480 if (GET_CODE (regno_reg_rtx[i]) != REG)
2483 /* Modify the reg-rtx to contain the new hard reg
2484 number or else to contain its pseudo reg number. */
2485 REGNO (regno_reg_rtx[i])
2486 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2488 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2489 allocate a stack slot for it. */
2491 if (reg_renumber[i] < 0
2492 && REG_N_REFS (i) > 0
2493 && reg_equiv_constant[i] == 0
2494 && reg_equiv_memory_loc[i] == 0)
2497 int inherent_size = PSEUDO_REGNO_BYTES (i);
2498 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2501 /* Each pseudo reg has an inherent size which comes from its own mode,
2502 and a total size which provides room for paradoxical subregs
2503 which refer to the pseudo reg in wider modes.
2505 We can use a slot already allocated if it provides both
2506 enough inherent space and enough total space.
2507 Otherwise, we allocate a new slot, making sure that it has no less
2508 inherent space, and no less total space, then the previous slot. */
2511 /* No known place to spill from => no slot to reuse. */
2512 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2513 inherent_size == total_size ? 0 : -1);
2514 if (BYTES_BIG_ENDIAN)
2515 /* Cancel the big-endian correction done in assign_stack_local.
2516 Get the address of the beginning of the slot.
2517 This is so we can do a big-endian correction unconditionally
2519 adjust = inherent_size - total_size;
2521 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2523 /* Reuse a stack slot if possible. */
2524 else if (spill_stack_slot[from_reg] != 0
2525 && spill_stack_slot_width[from_reg] >= total_size
2526 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2528 x = spill_stack_slot[from_reg];
2529 /* Allocate a bigger slot. */
2532 /* Compute maximum size needed, both for inherent size
2533 and for total size. */
2534 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2536 if (spill_stack_slot[from_reg])
2538 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2540 mode = GET_MODE (spill_stack_slot[from_reg]);
2541 if (spill_stack_slot_width[from_reg] > total_size)
2542 total_size = spill_stack_slot_width[from_reg];
2544 /* Make a slot with that size. */
2545 x = assign_stack_local (mode, total_size,
2546 inherent_size == total_size ? 0 : -1);
2548 if (BYTES_BIG_ENDIAN)
2550 /* Cancel the big-endian correction done in assign_stack_local.
2551 Get the address of the beginning of the slot.
2552 This is so we can do a big-endian correction unconditionally
2554 adjust = GET_MODE_SIZE (mode) - total_size;
2556 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2559 plus_constant (XEXP (x, 0), adjust));
2561 spill_stack_slot[from_reg] = stack_slot;
2562 spill_stack_slot_width[from_reg] = total_size;
2565 /* On a big endian machine, the "address" of the slot
2566 is the address of the low part that fits its inherent mode. */
2567 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2568 adjust += (total_size - inherent_size);
2570 /* If we have any adjustment to make, or if the stack slot is the
2571 wrong mode, make a new stack slot. */
2572 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2574 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2575 plus_constant (XEXP (x, 0), adjust));
2577 /* If this was shared among registers, must ensure we never
2578 set it readonly since that can cause scheduling
2579 problems. Note we would only have in this adjustment
2580 case in any event, since the code above doesn't set it. */
2583 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2586 /* Save the stack slot for later. */
2587 reg_equiv_memory_loc[i] = x;
2591 /* Mark the slots in regs_ever_live for the hard regs
2592 used by pseudo-reg number REGNO. */
2595 mark_home_live (regno)
2598 register int i, lim;
2599 i = reg_renumber[regno];
2602 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2604 regs_ever_live[i++] = 1;
2607 /* Mark the registers used in SCRATCH as being live. */
2610 mark_scratch_live (scratch)
2614 int regno = REGNO (scratch);
2615 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2617 for (i = regno; i < lim; i++)
2618 regs_ever_live[i] = 1;
2621 /* This function handles the tracking of elimination offsets around branches.
2623 X is a piece of RTL being scanned.
2625 INSN is the insn that it came from, if any.
2627 INITIAL_P is non-zero if we are to set the offset to be the initial
2628 offset and zero if we are setting the offset of the label to be the
2632 set_label_offsets (x, insn, initial_p)
2637 enum rtx_code code = GET_CODE (x);
2640 struct elim_table *p;
2645 if (LABEL_REF_NONLOCAL_P (x))
2650 /* ... fall through ... */
2653 /* If we know nothing about this label, set the desired offsets. Note
2654 that this sets the offset at a label to be the offset before a label
2655 if we don't know anything about the label. This is not correct for
2656 the label after a BARRIER, but is the best guess we can make. If
2657 we guessed wrong, we will suppress an elimination that might have
2658 been possible had we been able to guess correctly. */
2660 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2662 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2663 offsets_at[CODE_LABEL_NUMBER (x)][i]
2664 = (initial_p ? reg_eliminate[i].initial_offset
2665 : reg_eliminate[i].offset);
2666 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2669 /* Otherwise, if this is the definition of a label and it is
2670 preceded by a BARRIER, set our offsets to the known offset of
2674 && (tem = prev_nonnote_insn (insn)) != 0
2675 && GET_CODE (tem) == BARRIER)
2677 num_not_at_initial_offset = 0;
2678 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2680 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2681 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2682 if (reg_eliminate[i].can_eliminate
2683 && (reg_eliminate[i].offset
2684 != reg_eliminate[i].initial_offset))
2685 num_not_at_initial_offset++;
2690 /* If neither of the above cases is true, compare each offset
2691 with those previously recorded and suppress any eliminations
2692 where the offsets disagree. */
2694 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2695 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2696 != (initial_p ? reg_eliminate[i].initial_offset
2697 : reg_eliminate[i].offset))
2698 reg_eliminate[i].can_eliminate = 0;
2703 set_label_offsets (PATTERN (insn), insn, initial_p);
2705 /* ... fall through ... */
2709 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2710 and hence must have all eliminations at their initial offsets. */
2711 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2712 if (REG_NOTE_KIND (tem) == REG_LABEL)
2713 set_label_offsets (XEXP (tem, 0), insn, 1);
2718 /* Each of the labels in the address vector must be at their initial
2719 offsets. We want the first field for ADDR_VEC and the second
2720 field for ADDR_DIFF_VEC. */
2722 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2723 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2728 /* We only care about setting PC. If the source is not RETURN,
2729 IF_THEN_ELSE, or a label, disable any eliminations not at
2730 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2731 isn't one of those possibilities. For branches to a label,
2732 call ourselves recursively.
2734 Note that this can disable elimination unnecessarily when we have
2735 a non-local goto since it will look like a non-constant jump to
2736 someplace in the current function. This isn't a significant
2737 problem since such jumps will normally be when all elimination
2738 pairs are back to their initial offsets. */
2740 if (SET_DEST (x) != pc_rtx)
2743 switch (GET_CODE (SET_SRC (x)))
2750 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2754 tem = XEXP (SET_SRC (x), 1);
2755 if (GET_CODE (tem) == LABEL_REF)
2756 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2757 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2760 tem = XEXP (SET_SRC (x), 2);
2761 if (GET_CODE (tem) == LABEL_REF)
2762 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2763 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2771 /* If we reach here, all eliminations must be at their initial
2772 offset because we are doing a jump to a variable address. */
2773 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2774 if (p->offset != p->initial_offset)
2775 p->can_eliminate = 0;
2783 /* Used for communication between the next two function to properly share
2784 the vector for an ASM_OPERANDS. */
2786 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2788 /* Scan X and replace any eliminable registers (such as fp) with a
2789 replacement (such as sp), plus an offset.
2791 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2792 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2793 MEM, we are allowed to replace a sum of a register and the constant zero
2794 with the register, which we cannot do outside a MEM. In addition, we need
2795 to record the fact that a register is referenced outside a MEM.
2797 If INSN is an insn, it is the insn containing X. If we replace a REG
2798 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2799 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2800 the REG is being modified.
2802 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2803 That's used when we eliminate in expressions stored in notes.
2804 This means, do not set ref_outside_mem even if the reference
2807 If we see a modification to a register we know about, take the
2808 appropriate action (see case SET, below).
2810 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2811 replacements done assuming all offsets are at their initial values. If
2812 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2813 encounter, return the actual location so that find_reloads will do
2814 the proper thing. */
2817 eliminate_regs (x, mem_mode, insn)
2819 enum machine_mode mem_mode;
2822 enum rtx_code code = GET_CODE (x);
2823 struct elim_table *ep;
2846 /* This is only for the benefit of the debugging backends, which call
2847 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2848 removed after CSE. */
2849 new = eliminate_regs (XEXP (x, 0), 0, insn);
2850 if (GET_CODE (new) == MEM)
2851 return XEXP (new, 0);
2857 /* First handle the case where we encounter a bare register that
2858 is eliminable. Replace it with a PLUS. */
2859 if (regno < FIRST_PSEUDO_REGISTER)
2861 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2863 if (ep->from_rtx == x && ep->can_eliminate)
2866 /* Refs inside notes don't count for this purpose. */
2867 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2868 || GET_CODE (insn) == INSN_LIST)))
2869 ep->ref_outside_mem = 1;
2870 return plus_constant (ep->to_rtx, ep->previous_offset);
2874 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2875 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2877 /* In this case, find_reloads would attempt to either use an
2878 incorrect address (if something is not at its initial offset)
2879 or substitute an replaced address into an insn (which loses
2880 if the offset is changed by some later action). So we simply
2881 return the replaced stack slot (assuming it is changed by
2882 elimination) and ignore the fact that this is actually a
2883 reference to the pseudo. Ensure we make a copy of the
2884 address in case it is shared. */
2885 new = eliminate_regs (reg_equiv_memory_loc[regno], mem_mode, insn);
2886 if (new != reg_equiv_memory_loc[regno])
2888 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2889 && GET_CODE (insn) != INSN_LIST)
2890 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn))
2891 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2892 return copy_rtx (new);
2898 /* If this is the sum of an eliminable register and a constant, rework
2900 if (GET_CODE (XEXP (x, 0)) == REG
2901 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2902 && CONSTANT_P (XEXP (x, 1)))
2904 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2906 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2909 /* Refs inside notes don't count for this purpose. */
2910 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2911 || GET_CODE (insn) == INSN_LIST)))
2912 ep->ref_outside_mem = 1;
2914 /* The only time we want to replace a PLUS with a REG (this
2915 occurs when the constant operand of the PLUS is the negative
2916 of the offset) is when we are inside a MEM. We won't want
2917 to do so at other times because that would change the
2918 structure of the insn in a way that reload can't handle.
2919 We special-case the commonest situation in
2920 eliminate_regs_in_insn, so just replace a PLUS with a
2921 PLUS here, unless inside a MEM. */
2922 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2923 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2926 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2927 plus_constant (XEXP (x, 1),
2928 ep->previous_offset));
2931 /* If the register is not eliminable, we are done since the other
2932 operand is a constant. */
2936 /* If this is part of an address, we want to bring any constant to the
2937 outermost PLUS. We will do this by doing register replacement in
2938 our operands and seeing if a constant shows up in one of them.
2940 We assume here this is part of an address (or a "load address" insn)
2941 since an eliminable register is not likely to appear in any other
2944 If we have (plus (eliminable) (reg)), we want to produce
2945 (plus (plus (replacement) (reg) (const))). If this was part of a
2946 normal add insn, (plus (replacement) (reg)) will be pushed as a
2947 reload. This is the desired action. */
2950 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2951 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2953 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2955 /* If one side is a PLUS and the other side is a pseudo that
2956 didn't get a hard register but has a reg_equiv_constant,
2957 we must replace the constant here since it may no longer
2958 be in the position of any operand. */
2959 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2960 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2961 && reg_renumber[REGNO (new1)] < 0
2962 && reg_equiv_constant != 0
2963 && reg_equiv_constant[REGNO (new1)] != 0)
2964 new1 = reg_equiv_constant[REGNO (new1)];
2965 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2966 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2967 && reg_renumber[REGNO (new0)] < 0
2968 && reg_equiv_constant[REGNO (new0)] != 0)
2969 new0 = reg_equiv_constant[REGNO (new0)];
2971 new = form_sum (new0, new1);
2973 /* As above, if we are not inside a MEM we do not want to
2974 turn a PLUS into something else. We might try to do so here
2975 for an addition of 0 if we aren't optimizing. */
2976 if (! mem_mode && GET_CODE (new) != PLUS)
2977 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2985 /* If this is the product of an eliminable register and a
2986 constant, apply the distribute law and move the constant out
2987 so that we have (plus (mult ..) ..). This is needed in order
2988 to keep load-address insns valid. This case is pathological.
2989 We ignore the possibility of overflow here. */
2990 if (GET_CODE (XEXP (x, 0)) == REG
2991 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2992 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2993 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2995 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2998 /* Refs inside notes don't count for this purpose. */
2999 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
3000 || GET_CODE (insn) == INSN_LIST)))
3001 ep->ref_outside_mem = 1;
3004 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
3005 ep->previous_offset * INTVAL (XEXP (x, 1)));
3008 /* ... fall through ... */
3013 case DIV: case UDIV:
3014 case MOD: case UMOD:
3015 case AND: case IOR: case XOR:
3016 case ROTATERT: case ROTATE:
3017 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3019 case GE: case GT: case GEU: case GTU:
3020 case LE: case LT: case LEU: case LTU:
3022 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3024 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
3026 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
3027 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
3032 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
3035 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3036 if (new != XEXP (x, 0))
3037 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
3040 /* ... fall through ... */
3043 /* Now do eliminations in the rest of the chain. If this was
3044 an EXPR_LIST, this might result in allocating more memory than is
3045 strictly needed, but it simplifies the code. */
3048 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
3049 if (new != XEXP (x, 1))
3050 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
3058 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3059 if (ep->to_rtx == XEXP (x, 0))
3061 int size = GET_MODE_SIZE (mem_mode);
3063 /* If more bytes than MEM_MODE are pushed, account for them. */
3064 #ifdef PUSH_ROUNDING
3065 if (ep->to_rtx == stack_pointer_rtx)
3066 size = PUSH_ROUNDING (size);
3068 if (code == PRE_DEC || code == POST_DEC)
3074 /* Fall through to generic unary operation case. */
3075 case STRICT_LOW_PART:
3077 case SIGN_EXTEND: case ZERO_EXTEND:
3078 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3079 case FLOAT: case FIX:
3080 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3084 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3085 if (new != XEXP (x, 0))
3086 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3090 /* Similar to above processing, but preserve SUBREG_WORD.
3091 Convert (subreg (mem)) to (mem) if not paradoxical.
3092 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3093 pseudo didn't get a hard reg, we must replace this with the
3094 eliminated version of the memory location because push_reloads
3095 may do the replacement in certain circumstances. */
3096 if (GET_CODE (SUBREG_REG (x)) == REG
3097 && (GET_MODE_SIZE (GET_MODE (x))
3098 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3099 && reg_equiv_memory_loc != 0
3100 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3102 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3105 /* If we didn't change anything, we must retain the pseudo. */
3106 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3107 new = SUBREG_REG (x);
3110 /* In this case, we must show that the pseudo is used in this
3111 insn so that delete_output_reload will do the right thing. */
3112 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3113 && GET_CODE (insn) != INSN_LIST)
3114 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
3117 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3119 /* Ensure NEW isn't shared in case we have to reload it. */
3120 new = copy_rtx (new);
3124 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3126 if (new != XEXP (x, 0))
3128 int x_size = GET_MODE_SIZE (GET_MODE (x));
3129 int new_size = GET_MODE_SIZE (GET_MODE (new));
3131 if (GET_CODE (new) == MEM
3132 && ((x_size < new_size
3133 #ifdef WORD_REGISTER_OPERATIONS
3134 /* On these machines, combine can create rtl of the form
3135 (set (subreg:m1 (reg:m2 R) 0) ...)
3136 where m1 < m2, and expects something interesting to
3137 happen to the entire word. Moreover, it will use the
3138 (reg:m2 R) later, expecting all bits to be preserved.
3139 So if the number of words is the same, preserve the
3140 subreg so that push_reloads can see it. */
3141 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3144 || (x_size == new_size))
3147 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3148 enum machine_mode mode = GET_MODE (x);
3150 if (BYTES_BIG_ENDIAN)
3151 offset += (MIN (UNITS_PER_WORD,
3152 GET_MODE_SIZE (GET_MODE (new)))
3153 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3155 PUT_MODE (new, mode);
3156 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3160 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3166 /* If using a register that is the source of an eliminate we still
3167 think can be performed, note it cannot be performed since we don't
3168 know how this register is used. */
3169 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3170 if (ep->from_rtx == XEXP (x, 0))
3171 ep->can_eliminate = 0;
3173 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3174 if (new != XEXP (x, 0))
3175 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3179 /* If clobbering a register that is the replacement register for an
3180 elimination we still think can be performed, note that it cannot
3181 be performed. Otherwise, we need not be concerned about it. */
3182 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3183 if (ep->to_rtx == XEXP (x, 0))
3184 ep->can_eliminate = 0;
3186 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3187 if (new != XEXP (x, 0))
3188 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3194 /* Properly handle sharing input and constraint vectors. */
3195 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3197 /* When we come to a new vector not seen before,
3198 scan all its elements; keep the old vector if none
3199 of them changes; otherwise, make a copy. */
3200 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3201 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3202 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3203 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3206 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3207 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3210 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3211 new_asm_operands_vec = old_asm_operands_vec;
3213 new_asm_operands_vec
3214 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3217 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3218 if (new_asm_operands_vec == old_asm_operands_vec)
3221 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3222 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3223 ASM_OPERANDS_OUTPUT_IDX (x),
3224 new_asm_operands_vec,
3225 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3226 ASM_OPERANDS_SOURCE_FILE (x),
3227 ASM_OPERANDS_SOURCE_LINE (x));
3228 new->volatil = x->volatil;
3233 /* Check for setting a register that we know about. */
3234 if (GET_CODE (SET_DEST (x)) == REG)
3236 /* See if this is setting the replacement register for an
3239 If DEST is the hard frame pointer, we do nothing because we
3240 assume that all assignments to the frame pointer are for
3241 non-local gotos and are being done at a time when they are valid
3242 and do not disturb anything else. Some machines want to
3243 eliminate a fake argument pointer (or even a fake frame pointer)
3244 with either the real frame or the stack pointer. Assignments to
3245 the hard frame pointer must not prevent this elimination. */
3247 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3249 if (ep->to_rtx == SET_DEST (x)
3250 && SET_DEST (x) != hard_frame_pointer_rtx)
3252 /* If it is being incremented, adjust the offset. Otherwise,
3253 this elimination can't be done. */
3254 rtx src = SET_SRC (x);
3256 if (GET_CODE (src) == PLUS
3257 && XEXP (src, 0) == SET_DEST (x)
3258 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3259 ep->offset -= INTVAL (XEXP (src, 1));
3261 ep->can_eliminate = 0;
3264 /* Now check to see we are assigning to a register that can be
3265 eliminated. If so, it must be as part of a PARALLEL, since we
3266 will not have been called if this is a single SET. So indicate
3267 that we can no longer eliminate this reg. */
3268 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3270 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3271 ep->can_eliminate = 0;
3274 /* Now avoid the loop below in this common case. */
3276 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3277 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3279 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3280 write a CLOBBER insn. */
3281 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3282 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3283 && GET_CODE (insn) != INSN_LIST)
3284 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3286 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3287 return gen_rtx_SET (VOIDmode, new0, new1);
3293 /* This is only for the benefit of the debugging backends, which call
3294 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3295 removed after CSE. */
3296 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3297 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3299 /* Our only special processing is to pass the mode of the MEM to our
3300 recursive call and copy the flags. While we are here, handle this
3301 case more efficiently. */
3302 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3303 if (new != XEXP (x, 0))
3305 new = gen_rtx_MEM (GET_MODE (x), new);
3306 new->volatil = x->volatil;
3307 new->unchanging = x->unchanging;
3308 new->in_struct = x->in_struct;
3318 /* Process each of our operands recursively. If any have changed, make a
3320 fmt = GET_RTX_FORMAT (code);
3321 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3325 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3326 if (new != XEXP (x, i) && ! copied)
3328 rtx new_x = rtx_alloc (code);
3329 bcopy ((char *) x, (char *) new_x,
3330 (sizeof (*new_x) - sizeof (new_x->fld)
3331 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3337 else if (*fmt == 'E')
3340 for (j = 0; j < XVECLEN (x, i); j++)
3342 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3343 if (new != XVECEXP (x, i, j) && ! copied_vec)
3345 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3349 rtx new_x = rtx_alloc (code);
3350 bcopy ((char *) x, (char *) new_x,
3351 (sizeof (*new_x) - sizeof (new_x->fld)
3352 + (sizeof (new_x->fld[0])
3353 * GET_RTX_LENGTH (code))));
3357 XVEC (x, i) = new_v;
3360 XVECEXP (x, i, j) = new;
3368 /* Scan INSN and eliminate all eliminable registers in it.
3370 If REPLACE is nonzero, do the replacement destructively. Also
3371 delete the insn as dead it if it is setting an eliminable register.
3373 If REPLACE is zero, do all our allocations in reload_obstack.
3375 If no eliminations were done and this insn doesn't require any elimination
3376 processing (these are not identical conditions: it might be updating sp,
3377 but not referencing fp; this needs to be seen during reload_as_needed so
3378 that the offset between fp and sp can be taken into consideration), zero
3379 is returned. Otherwise, 1 is returned. */
3382 eliminate_regs_in_insn (insn, replace)
3386 rtx old_body = PATTERN (insn);
3387 rtx old_set = single_set (insn);
3390 struct elim_table *ep;
3393 push_obstacks (&reload_obstack, &reload_obstack);
3395 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3396 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3398 /* Check for setting an eliminable register. */
3399 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3400 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3402 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3403 /* If this is setting the frame pointer register to the
3404 hardware frame pointer register and this is an elimination
3405 that will be done (tested above), this insn is really
3406 adjusting the frame pointer downward to compensate for
3407 the adjustment done before a nonlocal goto. */
3408 if (ep->from == FRAME_POINTER_REGNUM
3409 && ep->to == HARD_FRAME_POINTER_REGNUM)
3411 rtx src = SET_SRC (old_set);
3413 rtx prev_insn, prev_set;
3415 if (src == ep->to_rtx)
3417 else if (GET_CODE (src) == PLUS
3418 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3419 offset = INTVAL (XEXP (src, 0)), ok = 1;
3420 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3421 && (prev_set = single_set (prev_insn)) != 0
3422 && rtx_equal_p (SET_DEST (prev_set), src))
3424 src = SET_SRC (prev_set);
3425 if (src == ep->to_rtx)
3427 else if (GET_CODE (src) == PLUS
3428 && GET_CODE (XEXP (src, 0)) == CONST_INT
3429 && XEXP (src, 1) == ep->to_rtx)
3430 offset = INTVAL (XEXP (src, 0)), ok = 1;
3431 else if (GET_CODE (src) == PLUS
3432 && GET_CODE (XEXP (src, 1)) == CONST_INT
3433 && XEXP (src, 0) == ep->to_rtx)
3434 offset = INTVAL (XEXP (src, 1)), ok = 1;
3442 = plus_constant (ep->to_rtx, offset - ep->offset);
3444 /* First see if this insn remains valid when we
3445 make the change. If not, keep the INSN_CODE
3446 the same and let reload fit it up. */
3447 validate_change (insn, &SET_SRC (old_set), src, 1);
3448 validate_change (insn, &SET_DEST (old_set),
3450 if (! apply_change_group ())
3452 SET_SRC (old_set) = src;
3453 SET_DEST (old_set) = ep->to_rtx;
3463 /* In this case this insn isn't serving a useful purpose. We
3464 will delete it in reload_as_needed once we know that this
3465 elimination is, in fact, being done.
3467 If REPLACE isn't set, we can't delete this insn, but needn't
3468 process it since it won't be used unless something changes. */
3470 delete_dead_insn (insn);
3475 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3476 in the insn is the negative of the offset in FROM. Substitute
3477 (set (reg) (reg to)) for the insn and change its code.
3479 We have to do this here, rather than in eliminate_regs, do that we can
3480 change the insn code. */
3482 if (GET_CODE (SET_SRC (old_set)) == PLUS
3483 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3484 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3485 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3487 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3488 && ep->can_eliminate)
3490 /* We must stop at the first elimination that will be used.
3491 If this one would replace the PLUS with a REG, do it
3492 now. Otherwise, quit the loop and let eliminate_regs
3493 do its normal replacement. */
3494 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3496 /* We assume here that we don't need a PARALLEL of
3497 any CLOBBERs for this assignment. There's not
3498 much we can do if we do need it. */
3499 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3502 INSN_CODE (insn) = -1;
3511 old_asm_operands_vec = 0;
3513 /* Replace the body of this insn with a substituted form. If we changed
3514 something, return non-zero.
3516 If we are replacing a body that was a (set X (plus Y Z)), try to
3517 re-recognize the insn. We do this in case we had a simple addition
3518 but now can do this as a load-address. This saves an insn in this
3521 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3522 if (new_body != old_body)
3524 /* If we aren't replacing things permanently and we changed something,
3525 make another copy to ensure that all the RTL is new. Otherwise
3526 things can go wrong if find_reload swaps commutative operands
3527 and one is inside RTL that has been copied while the other is not. */
3529 /* Don't copy an asm_operands because (1) there's no need and (2)
3530 copy_rtx can't do it properly when there are multiple outputs. */
3531 if (! replace && asm_noperands (old_body) < 0)
3532 new_body = copy_rtx (new_body);
3534 /* If we had a move insn but now we don't, rerecognize it. This will
3535 cause spurious re-recognition if the old move had a PARALLEL since
3536 the new one still will, but we can't call single_set without
3537 having put NEW_BODY into the insn and the re-recognition won't
3538 hurt in this rare case. */
3540 && ((GET_CODE (SET_SRC (old_set)) == REG
3541 && (GET_CODE (new_body) != SET
3542 || GET_CODE (SET_SRC (new_body)) != REG))
3543 /* If this was a load from or store to memory, compare
3544 the MEM in recog_operand to the one in the insn. If they
3545 are not equal, then rerecognize the insn. */
3547 && ((GET_CODE (SET_SRC (old_set)) == MEM
3548 && SET_SRC (old_set) != recog_operand[1])
3549 || (GET_CODE (SET_DEST (old_set)) == MEM
3550 && SET_DEST (old_set) != recog_operand[0])))
3551 /* If this was an add insn before, rerecognize. */
3552 || GET_CODE (SET_SRC (old_set)) == PLUS))
3554 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3555 /* If recognition fails, store the new body anyway.
3556 It's normal to have recognition failures here
3557 due to bizarre memory addresses; reloading will fix them. */
3558 PATTERN (insn) = new_body;
3561 PATTERN (insn) = new_body;
3566 /* Loop through all elimination pairs. See if any have changed and
3567 recalculate the number not at initial offset.
3569 Compute the maximum offset (minimum offset if the stack does not
3570 grow downward) for each elimination pair.
3572 We also detect a cases where register elimination cannot be done,
3573 namely, if a register would be both changed and referenced outside a MEM
3574 in the resulting insn since such an insn is often undefined and, even if
3575 not, we cannot know what meaning will be given to it. Note that it is
3576 valid to have a register used in an address in an insn that changes it
3577 (presumably with a pre- or post-increment or decrement).
3579 If anything changes, return nonzero. */
3581 num_not_at_initial_offset = 0;
3582 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3584 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3585 ep->can_eliminate = 0;
3587 ep->ref_outside_mem = 0;
3589 if (ep->previous_offset != ep->offset)
3592 ep->previous_offset = ep->offset;
3593 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3594 num_not_at_initial_offset++;
3596 #ifdef STACK_GROWS_DOWNWARD
3597 ep->max_offset = MAX (ep->max_offset, ep->offset);
3599 ep->max_offset = MIN (ep->max_offset, ep->offset);
3604 /* If we changed something, perform elimination in REG_NOTES. This is
3605 needed even when REPLACE is zero because a REG_DEAD note might refer
3606 to a register that we eliminate and could cause a different number
3607 of spill registers to be needed in the final reload pass than in
3609 if (val && REG_NOTES (insn) != 0)
3610 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3618 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3619 replacement we currently believe is valid, mark it as not eliminable if X
3620 modifies DEST in any way other than by adding a constant integer to it.
3622 If DEST is the frame pointer, we do nothing because we assume that
3623 all assignments to the hard frame pointer are nonlocal gotos and are being
3624 done at a time when they are valid and do not disturb anything else.
3625 Some machines want to eliminate a fake argument pointer with either the
3626 frame or stack pointer. Assignments to the hard frame pointer must not
3627 prevent this elimination.
3629 Called via note_stores from reload before starting its passes to scan
3630 the insns of the function. */
3633 mark_not_eliminable (dest, x)
3639 /* A SUBREG of a hard register here is just changing its mode. We should
3640 not see a SUBREG of an eliminable hard register, but check just in
3642 if (GET_CODE (dest) == SUBREG)
3643 dest = SUBREG_REG (dest);
3645 if (dest == hard_frame_pointer_rtx)
3648 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3649 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3650 && (GET_CODE (x) != SET
3651 || GET_CODE (SET_SRC (x)) != PLUS
3652 || XEXP (SET_SRC (x), 0) != dest
3653 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3655 reg_eliminate[i].can_eliminate_previous
3656 = reg_eliminate[i].can_eliminate = 0;
3661 /* Kick all pseudos out of hard register REGNO.
3662 If GLOBAL is nonzero, try to find someplace else to put them.
3663 If DUMPFILE is nonzero, log actions taken on that file.
3665 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3666 because we found we can't eliminate some register. In the case, no pseudos
3667 are allowed to be in the register, even if they are only in a block that
3668 doesn't require spill registers, unlike the case when we are spilling this
3669 hard reg to produce another spill register.
3671 Return nonzero if any pseudos needed to be kicked out. */
3674 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3680 enum reg_class class = REGNO_REG_CLASS (regno);
3681 int something_changed = 0;
3684 SET_HARD_REG_BIT (forbidden_regs, regno);
3687 regs_ever_live[regno] = 1;
3689 /* Spill every pseudo reg that was allocated to this reg
3690 or to something that overlaps this reg. */
3692 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3693 if (reg_renumber[i] >= 0
3694 && reg_renumber[i] <= regno
3696 + HARD_REGNO_NREGS (reg_renumber[i],
3697 PSEUDO_REGNO_MODE (i))
3700 /* If this register belongs solely to a basic block which needed no
3701 spilling of any class that this register is contained in,
3702 leave it be, unless we are spilling this register because
3703 it was a hard register that can't be eliminated. */
3705 if (! cant_eliminate
3706 && basic_block_needs[0]
3707 && REG_BASIC_BLOCK (i) >= 0
3708 && basic_block_needs[(int) class][REG_BASIC_BLOCK (i)] == 0)
3712 for (p = reg_class_superclasses[(int) class];
3713 *p != LIM_REG_CLASSES; p++)
3714 if (basic_block_needs[(int) *p][REG_BASIC_BLOCK (i)] > 0)
3717 if (*p == LIM_REG_CLASSES)
3721 /* Mark it as no longer having a hard register home. */
3722 reg_renumber[i] = -1;
3723 /* We will need to scan everything again. */
3724 something_changed = 1;
3726 retry_global_alloc (i, forbidden_regs);
3728 alter_reg (i, regno);
3731 if (reg_renumber[i] == -1)
3732 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3734 fprintf (dumpfile, " Register %d now in %d.\n\n",
3735 i, reg_renumber[i]);
3738 for (i = 0; i < scratch_list_length; i++)
3741 && regno >= REGNO (scratch_list[i])
3742 && regno < REGNO (scratch_list[i])
3743 + HARD_REGNO_NREGS (REGNO (scratch_list[i]),
3744 GET_MODE (scratch_list[i])))
3746 if (! cant_eliminate && basic_block_needs[0]
3747 && ! basic_block_needs[(int) class][scratch_block[i]])
3751 for (p = reg_class_superclasses[(int) class];
3752 *p != LIM_REG_CLASSES; p++)
3753 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3756 if (*p == LIM_REG_CLASSES)
3759 PUT_CODE (scratch_list[i], SCRATCH);
3760 scratch_list[i] = 0;
3761 something_changed = 1;
3766 return something_changed;
3769 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3770 Also mark any hard registers used to store user variables as
3771 forbidden from being used for spill registers. */
3774 scan_paradoxical_subregs (x)
3779 register enum rtx_code code = GET_CODE (x);
3784 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3785 && REG_USERVAR_P (x))
3786 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3801 if (GET_CODE (SUBREG_REG (x)) == REG
3802 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3803 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3804 = GET_MODE_SIZE (GET_MODE (x));
3811 fmt = GET_RTX_FORMAT (code);
3812 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3815 scan_paradoxical_subregs (XEXP (x, i));
3816 else if (fmt[i] == 'E')
3819 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3820 scan_paradoxical_subregs (XVECEXP (x, i, j));
3826 hard_reg_use_compare (p1p, p2p)
3827 const GENERIC_PTR p1p;
3828 const GENERIC_PTR p2p;
3830 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3831 *p2 = (struct hard_reg_n_uses *)p2p;
3832 int tem = p1->uses - p2->uses;
3833 if (tem != 0) return tem;
3834 /* If regs are equally good, sort by regno,
3835 so that the results of qsort leave nothing to chance. */
3836 return p1->regno - p2->regno;
3839 /* Choose the order to consider regs for use as reload registers
3840 based on how much trouble would be caused by spilling one.
3841 Store them in order of decreasing preference in potential_reload_regs. */
3844 order_regs_for_reload (global)
3851 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3853 CLEAR_HARD_REG_SET (bad_spill_regs);
3855 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3856 potential_reload_regs[i] = -1;
3858 /* Count number of uses of each hard reg by pseudo regs allocated to it
3859 and then order them by decreasing use. */
3861 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3863 hard_reg_n_uses[i].uses = 0;
3864 hard_reg_n_uses[i].regno = i;
3867 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3869 int regno = reg_renumber[i];
3872 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3875 /* If allocated by local-alloc, show more uses since
3876 we're not going to be able to reallocate it, but
3877 we might if allocated by global alloc. */
3878 if (global && reg_allocno[i] < 0)
3879 hard_reg_n_uses[regno].uses += (REG_N_REFS (i) + 1) / 2;
3881 hard_reg_n_uses[regno++].uses += REG_N_REFS (i);
3884 large += REG_N_REFS (i);
3887 /* Now fixed registers (which cannot safely be used for reloading)
3888 get a very high use count so they will be considered least desirable.
3889 Registers used explicitly in the rtl code are almost as bad. */
3891 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3895 hard_reg_n_uses[i].uses += 2 * large + 2;
3896 SET_HARD_REG_BIT (bad_spill_regs, i);
3898 else if (regs_explicitly_used[i])
3900 hard_reg_n_uses[i].uses += large + 1;
3901 if (! SMALL_REGISTER_CLASSES)
3902 /* ??? We are doing this here because of the potential
3903 that bad code may be generated if a register explicitly
3904 used in an insn was used as a spill register for that
3905 insn. But not using these are spill registers may lose
3906 on some machine. We'll have to see how this works out. */
3907 SET_HARD_REG_BIT (bad_spill_regs, i);
3910 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3911 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3913 #ifdef ELIMINABLE_REGS
3914 /* If registers other than the frame pointer are eliminable, mark them as
3916 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3918 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3919 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3923 /* Prefer registers not so far used, for use in temporary loading.
3924 Among them, if REG_ALLOC_ORDER is defined, use that order.
3925 Otherwise, prefer registers not preserved by calls. */
3927 #ifdef REG_ALLOC_ORDER
3928 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3930 int regno = reg_alloc_order[i];
3932 if (hard_reg_n_uses[regno].uses == 0)
3933 potential_reload_regs[o++] = regno;
3936 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3938 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3939 potential_reload_regs[o++] = i;
3941 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3943 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3944 potential_reload_regs[o++] = i;
3948 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3949 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3951 /* Now add the regs that are already used,
3952 preferring those used less often. The fixed and otherwise forbidden
3953 registers will be at the end of this list. */
3955 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3956 if (hard_reg_n_uses[i].uses != 0)
3957 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3960 /* Used in reload_as_needed to sort the spilled regs. */
3963 compare_spill_regs (r1p, r2p)
3964 const GENERIC_PTR r1p;
3965 const GENERIC_PTR r2p;
3967 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3971 /* Reload pseudo-registers into hard regs around each insn as needed.
3972 Additional register load insns are output before the insn that needs it
3973 and perhaps store insns after insns that modify the reloaded pseudo reg.
3975 reg_last_reload_reg and reg_reloaded_contents keep track of
3976 which registers are already available in reload registers.
3977 We update these for the reloads that we perform,
3978 as the insns are scanned. */
3981 reload_as_needed (first, live_known)
3991 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3992 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3993 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3994 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3995 reg_has_output_reload = (char *) alloca (max_regno);
3996 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3998 /* Reset all offsets on eliminable registers to their initial values. */
3999 #ifdef ELIMINABLE_REGS
4000 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4002 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
4003 reg_eliminate[i].initial_offset);
4004 reg_eliminate[i].previous_offset
4005 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
4008 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
4009 reg_eliminate[0].previous_offset
4010 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
4013 num_not_at_initial_offset = 0;
4015 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
4016 pack registers with group needs. */
4019 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
4020 for (i = 0; i < n_spills; i++)
4021 spill_reg_order[spill_regs[i]] = i;
4024 for (insn = first; insn;)
4026 register rtx next = NEXT_INSN (insn);
4028 /* Notice when we move to a new basic block. */
4029 if (live_known && this_block + 1 < n_basic_blocks
4030 && insn == basic_block_head[this_block+1])
4033 /* If we pass a label, copy the offsets from the label information
4034 into the current offsets of each elimination. */
4035 if (GET_CODE (insn) == CODE_LABEL)
4037 num_not_at_initial_offset = 0;
4038 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4040 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
4041 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
4042 if (reg_eliminate[i].can_eliminate
4043 && (reg_eliminate[i].offset
4044 != reg_eliminate[i].initial_offset))
4045 num_not_at_initial_offset++;
4049 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4051 rtx avoid_return_reg = 0;
4052 rtx oldpat = PATTERN (insn);
4054 /* Set avoid_return_reg if this is an insn
4055 that might use the value of a function call. */
4056 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
4058 if (GET_CODE (PATTERN (insn)) == SET)
4059 after_call = SET_DEST (PATTERN (insn));
4060 else if (GET_CODE (PATTERN (insn)) == PARALLEL
4061 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4062 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
4066 else if (SMALL_REGISTER_CLASSES && after_call != 0
4067 && !(GET_CODE (PATTERN (insn)) == SET
4068 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
4069 && GET_CODE (PATTERN (insn)) != USE)
4071 if (reg_referenced_p (after_call, PATTERN (insn)))
4072 avoid_return_reg = after_call;
4076 /* If this is a USE and CLOBBER of a MEM, ensure that any
4077 references to eliminable registers have been removed. */
4079 if ((GET_CODE (PATTERN (insn)) == USE
4080 || GET_CODE (PATTERN (insn)) == CLOBBER)
4081 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4082 XEXP (XEXP (PATTERN (insn), 0), 0)
4083 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4084 GET_MODE (XEXP (PATTERN (insn), 0)),
4087 /* If we need to do register elimination processing, do so.
4088 This might delete the insn, in which case we are done. */
4089 if (num_eliminable && GET_MODE (insn) == QImode)
4091 eliminate_regs_in_insn (insn, 1);
4092 if (GET_CODE (insn) == NOTE)
4099 if (GET_MODE (insn) == VOIDmode)
4101 /* First find the pseudo regs that must be reloaded for this insn.
4102 This info is returned in the tables reload_... (see reload.h).
4103 Also modify the body of INSN by substituting RELOAD
4104 rtx's for those pseudo regs. */
4107 bzero (reg_has_output_reload, max_regno);
4108 CLEAR_HARD_REG_SET (reg_is_output_reload);
4110 find_reloads (insn, 1, spill_indirect_levels, live_known,
4116 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4120 /* If this block has not had spilling done for a
4121 particular clas and we have any non-optionals that need a
4122 spill reg in that class, abort. */
4124 for (class = 0; class < N_REG_CLASSES; class++)
4125 if (basic_block_needs[class] != 0
4126 && basic_block_needs[class][this_block] == 0)
4127 for (i = 0; i < n_reloads; i++)
4128 if (class == (int) reload_reg_class[i]
4129 && reload_reg_rtx[i] == 0
4130 && ! reload_optional[i]
4131 && (reload_in[i] != 0 || reload_out[i] != 0
4132 || reload_secondary_p[i] != 0))
4133 fatal_insn ("Non-optional registers need a spill register", insn);
4135 /* Now compute which reload regs to reload them into. Perhaps
4136 reusing reload regs from previous insns, or else output
4137 load insns to reload them. Maybe output store insns too.
4138 Record the choices of reload reg in reload_reg_rtx. */
4139 choose_reload_regs (insn, avoid_return_reg);
4141 /* Merge any reloads that we didn't combine for fear of
4142 increasing the number of spill registers needed but now
4143 discover can be safely merged. */
4144 if (SMALL_REGISTER_CLASSES)
4145 merge_assigned_reloads (insn);
4147 /* Generate the insns to reload operands into or out of
4148 their reload regs. */
4149 emit_reload_insns (insn);
4151 /* Substitute the chosen reload regs from reload_reg_rtx
4152 into the insn's body (or perhaps into the bodies of other
4153 load and store insn that we just made for reloading
4154 and that we moved the structure into). */
4157 /* If this was an ASM, make sure that all the reload insns
4158 we have generated are valid. If not, give an error
4161 if (asm_noperands (PATTERN (insn)) >= 0)
4162 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4163 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4164 && (recog_memoized (p) < 0
4165 || (insn_extract (p),
4166 ! constrain_operands (INSN_CODE (p), 1))))
4168 error_for_asm (insn,
4169 "`asm' operand requires impossible reload");
4171 NOTE_SOURCE_FILE (p) = 0;
4172 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4175 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4176 is no longer validly lying around to save a future reload.
4177 Note that this does not detect pseudos that were reloaded
4178 for this insn in order to be stored in
4179 (obeying register constraints). That is correct; such reload
4180 registers ARE still valid. */
4181 note_stores (oldpat, forget_old_reloads_1);
4183 /* There may have been CLOBBER insns placed after INSN. So scan
4184 between INSN and NEXT and use them to forget old reloads. */
4185 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4186 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4187 note_stores (PATTERN (x), forget_old_reloads_1);
4190 /* Likewise for regs altered by auto-increment in this insn.
4191 But note that the reg-notes are not changed by reloading:
4192 they still contain the pseudo-regs, not the spill regs. */
4193 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4194 if (REG_NOTE_KIND (x) == REG_INC)
4196 /* See if this pseudo reg was reloaded in this insn.
4197 If so, its last-reload info is still valid
4198 because it is based on this insn's reload. */
4199 for (i = 0; i < n_reloads; i++)
4200 if (reload_out[i] == XEXP (x, 0))
4204 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4208 /* A reload reg's contents are unknown after a label. */
4209 if (GET_CODE (insn) == CODE_LABEL)
4210 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4212 /* Don't assume a reload reg is still good after a call insn
4213 if it is a call-used reg. */
4214 else if (GET_CODE (insn) == CALL_INSN)
4215 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4217 /* In case registers overlap, allow certain insns to invalidate
4218 particular hard registers. */
4220 #ifdef INSN_CLOBBERS_REGNO_P
4221 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4222 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4223 && INSN_CLOBBERS_REGNO_P (insn, i))
4224 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4235 /* Discard all record of any value reloaded from X,
4236 or reloaded in X from someplace else;
4237 unless X is an output reload reg of the current insn.
4239 X may be a hard reg (the reload reg)
4240 or it may be a pseudo reg that was reloaded from. */
4243 forget_old_reloads_1 (x, ignored)
4245 rtx ignored ATTRIBUTE_UNUSED;
4251 /* note_stores does give us subregs of hard regs. */
4252 while (GET_CODE (x) == SUBREG)
4254 offset += SUBREG_WORD (x);
4258 if (GET_CODE (x) != REG)
4261 regno = REGNO (x) + offset;
4263 if (regno >= FIRST_PSEUDO_REGISTER)
4268 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4269 /* Storing into a spilled-reg invalidates its contents.
4270 This can happen if a block-local pseudo is allocated to that reg
4271 and it wasn't spilled because this block's total need is 0.
4272 Then some insn might have an optional reload and use this reg. */
4273 for (i = 0; i < nr; i++)
4274 /* But don't do this if the reg actually serves as an output
4275 reload reg in the current instruction. */
4277 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4278 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4281 /* Since value of X has changed,
4282 forget any value previously copied from it. */
4285 /* But don't forget a copy if this is the output reload
4286 that establishes the copy's validity. */
4287 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4288 reg_last_reload_reg[regno + nr] = 0;
4291 /* For each reload, the mode of the reload register. */
4292 static enum machine_mode reload_mode[MAX_RELOADS];
4294 /* For each reload, the largest number of registers it will require. */
4295 static int reload_nregs[MAX_RELOADS];
4297 /* Comparison function for qsort to decide which of two reloads
4298 should be handled first. *P1 and *P2 are the reload numbers. */
4301 reload_reg_class_lower (r1p, r2p)
4302 const GENERIC_PTR r1p;
4303 const GENERIC_PTR r2p;
4305 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4308 /* Consider required reloads before optional ones. */
4309 t = reload_optional[r1] - reload_optional[r2];
4313 /* Count all solitary classes before non-solitary ones. */
4314 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4315 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4319 /* Aside from solitaires, consider all multi-reg groups first. */
4320 t = reload_nregs[r2] - reload_nregs[r1];
4324 /* Consider reloads in order of increasing reg-class number. */
4325 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4329 /* If reloads are equally urgent, sort by reload number,
4330 so that the results of qsort leave nothing to chance. */
4334 /* The following HARD_REG_SETs indicate when each hard register is
4335 used for a reload of various parts of the current insn. */
4337 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4338 static HARD_REG_SET reload_reg_used;
4339 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4340 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4341 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4342 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4343 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4344 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4345 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4346 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4347 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4348 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4349 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4350 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4351 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4352 static HARD_REG_SET reload_reg_used_in_op_addr;
4353 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4354 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4355 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4356 static HARD_REG_SET reload_reg_used_in_insn;
4357 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4358 static HARD_REG_SET reload_reg_used_in_other_addr;
4360 /* If reg is in use as a reload reg for any sort of reload. */
4361 static HARD_REG_SET reload_reg_used_at_all;
4363 /* If reg is use as an inherited reload. We just mark the first register
4365 static HARD_REG_SET reload_reg_used_for_inherit;
4367 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4368 TYPE. MODE is used to indicate how many consecutive regs are
4372 mark_reload_reg_in_use (regno, opnum, type, mode)
4375 enum reload_type type;
4376 enum machine_mode mode;
4378 int nregs = HARD_REGNO_NREGS (regno, mode);
4381 for (i = regno; i < nregs + regno; i++)
4386 SET_HARD_REG_BIT (reload_reg_used, i);
4389 case RELOAD_FOR_INPUT_ADDRESS:
4390 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4393 case RELOAD_FOR_INPADDR_ADDRESS:
4394 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4397 case RELOAD_FOR_OUTPUT_ADDRESS:
4398 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4401 case RELOAD_FOR_OUTADDR_ADDRESS:
4402 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4405 case RELOAD_FOR_OPERAND_ADDRESS:
4406 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4409 case RELOAD_FOR_OPADDR_ADDR:
4410 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4413 case RELOAD_FOR_OTHER_ADDRESS:
4414 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4417 case RELOAD_FOR_INPUT:
4418 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4421 case RELOAD_FOR_OUTPUT:
4422 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4425 case RELOAD_FOR_INSN:
4426 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4430 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4434 /* Similarly, but show REGNO is no longer in use for a reload. */
4437 clear_reload_reg_in_use (regno, opnum, type, mode)
4440 enum reload_type type;
4441 enum machine_mode mode;
4443 int nregs = HARD_REGNO_NREGS (regno, mode);
4446 for (i = regno; i < nregs + regno; i++)
4451 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4454 case RELOAD_FOR_INPUT_ADDRESS:
4455 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4458 case RELOAD_FOR_INPADDR_ADDRESS:
4459 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4462 case RELOAD_FOR_OUTPUT_ADDRESS:
4463 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4466 case RELOAD_FOR_OUTADDR_ADDRESS:
4467 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4470 case RELOAD_FOR_OPERAND_ADDRESS:
4471 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4474 case RELOAD_FOR_OPADDR_ADDR:
4475 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4478 case RELOAD_FOR_OTHER_ADDRESS:
4479 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4482 case RELOAD_FOR_INPUT:
4483 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4486 case RELOAD_FOR_OUTPUT:
4487 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4490 case RELOAD_FOR_INSN:
4491 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4497 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4498 specified by OPNUM and TYPE. */
4501 reload_reg_free_p (regno, opnum, type)
4504 enum reload_type type;
4508 /* In use for a RELOAD_OTHER means it's not available for anything. */
4509 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4515 /* In use for anything means we can't use it for RELOAD_OTHER. */
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4521 for (i = 0; i < reload_n_operands; i++)
4522 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4532 case RELOAD_FOR_INPUT:
4533 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4540 /* If it is used for some other input, can't use it. */
4541 for (i = 0; i < reload_n_operands; i++)
4542 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4545 /* If it is used in a later operand's address, can't use it. */
4546 for (i = opnum + 1; i < reload_n_operands; i++)
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4553 case RELOAD_FOR_INPUT_ADDRESS:
4554 /* Can't use a register if it is used for an input address for this
4555 operand or used as an input in an earlier one. */
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4560 for (i = 0; i < opnum; i++)
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4566 case RELOAD_FOR_INPADDR_ADDRESS:
4567 /* Can't use a register if it is used for an input address
4568 for this operand or used as an input in an earlier
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4573 for (i = 0; i < opnum; i++)
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4579 case RELOAD_FOR_OUTPUT_ADDRESS:
4580 /* Can't use a register if it is used for an output address for this
4581 operand or used as an output in this or a later operand. */
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4585 for (i = opnum; i < reload_n_operands; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4591 case RELOAD_FOR_OUTADDR_ADDRESS:
4592 /* Can't use a register if it is used for an output address
4593 for this operand or used as an output in this or a
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4598 for (i = opnum; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4604 case RELOAD_FOR_OPERAND_ADDRESS:
4605 for (i = 0; i < reload_n_operands; i++)
4606 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4609 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4610 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4612 case RELOAD_FOR_OPADDR_ADDR:
4613 for (i = 0; i < reload_n_operands; i++)
4614 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4617 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4619 case RELOAD_FOR_OUTPUT:
4620 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4621 outputs, or an operand address for this or an earlier output. */
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4625 for (i = 0; i < reload_n_operands; i++)
4626 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4629 for (i = 0; i <= opnum; i++)
4630 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4631 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4636 case RELOAD_FOR_INSN:
4637 for (i = 0; i < reload_n_operands; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4642 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4643 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4645 case RELOAD_FOR_OTHER_ADDRESS:
4646 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4651 /* Return 1 if the value in reload reg REGNO, as used by a reload
4652 needed for the part of the insn specified by OPNUM and TYPE,
4653 is not in use for a reload in any prior part of the insn.
4655 We can assume that the reload reg was already tested for availability
4656 at the time it is needed, and we should not check this again,
4657 in case the reg has already been marked in use. */
4660 reload_reg_free_before_p (regno, opnum, type)
4663 enum reload_type type;
4669 case RELOAD_FOR_OTHER_ADDRESS:
4670 /* These always come first. */
4674 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4676 /* If this use is for part of the insn,
4677 check the reg is not in use for any prior part. It is tempting
4678 to try to do this by falling through from objecs that occur
4679 later in the insn to ones that occur earlier, but that will not
4680 correctly take into account the fact that here we MUST ignore
4681 things that would prevent the register from being allocated in
4682 the first place, since we know that it was allocated. */
4684 case RELOAD_FOR_OUTPUT_ADDRESS:
4685 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4686 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4688 /* ... fall through ... */
4689 case RELOAD_FOR_OUTADDR_ADDRESS:
4690 /* Earlier reloads are for earlier outputs or their addresses,
4691 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4692 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4694 for (i = 0; i < opnum; i++)
4695 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4696 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4697 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4703 for (i = 0; i < reload_n_operands; i++)
4704 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4705 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4706 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4709 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4710 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4711 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4712 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4714 case RELOAD_FOR_OUTPUT:
4715 /* This can't be used in the output address for this operand and
4716 anything that can't be used for it, except that we've already
4717 tested for RELOAD_FOR_INSN objects. */
4719 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)
4720 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4723 for (i = 0; i < opnum; i++)
4724 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4725 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4726 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4729 for (i = 0; i < reload_n_operands; i++)
4730 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4731 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4732 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4733 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4736 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4738 case RELOAD_FOR_OPERAND_ADDRESS:
4739 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4740 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4743 /* ... fall through ... */
4745 case RELOAD_FOR_OPADDR_ADDR:
4746 case RELOAD_FOR_INSN:
4747 /* These can't conflict with inputs, or each other, so all we have to
4748 test is input addresses and the addresses of OTHER items. */
4750 for (i = 0; i < reload_n_operands; i++)
4751 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4752 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4755 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4757 case RELOAD_FOR_INPUT:
4758 /* The only things earlier are the address for this and
4759 earlier inputs, other inputs (which we know we don't conflict
4760 with), and addresses of RELOAD_OTHER objects. */
4762 for (i = 0; i <= opnum; i++)
4763 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4764 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4767 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4769 case RELOAD_FOR_INPUT_ADDRESS:
4770 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4771 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4773 /* ... fall through ... */
4774 case RELOAD_FOR_INPADDR_ADDRESS:
4775 /* Similarly, all we have to check is for use in earlier inputs'
4777 for (i = 0; i < opnum; i++)
4778 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4779 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4782 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4787 /* Return 1 if the value in reload reg REGNO, as used by a reload
4788 needed for the part of the insn specified by OPNUM and TYPE,
4789 is still available in REGNO at the end of the insn.
4791 We can assume that the reload reg was already tested for availability
4792 at the time it is needed, and we should not check this again,
4793 in case the reg has already been marked in use. */
4796 reload_reg_reaches_end_p (regno, opnum, type)
4799 enum reload_type type;
4806 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4807 its value must reach the end. */
4810 /* If this use is for part of the insn,
4811 its value reaches if no subsequent part uses the same register.
4812 Just like the above function, don't try to do this with lots
4815 case RELOAD_FOR_OTHER_ADDRESS:
4816 /* Here we check for everything else, since these don't conflict
4817 with anything else and everything comes later. */
4819 for (i = 0; i < reload_n_operands; i++)
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4824 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4825 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4828 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4829 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4830 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4832 case RELOAD_FOR_INPUT_ADDRESS:
4833 case RELOAD_FOR_INPADDR_ADDRESS:
4834 /* Similar, except that we check only for this and subsequent inputs
4835 and the address of only subsequent inputs and we do not need
4836 to check for RELOAD_OTHER objects since they are known not to
4839 for (i = opnum; i < reload_n_operands; i++)
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4843 for (i = opnum + 1; i < reload_n_operands; i++)
4844 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4845 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4848 for (i = 0; i < reload_n_operands; i++)
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4850 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4851 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4857 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4858 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4860 case RELOAD_FOR_INPUT:
4861 /* Similar to input address, except we start at the next operand for
4862 both input and input address and we do not check for
4863 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4866 for (i = opnum + 1; i < reload_n_operands; i++)
4867 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4868 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4869 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4872 /* ... fall through ... */
4874 case RELOAD_FOR_OPERAND_ADDRESS:
4875 /* Check outputs and their addresses. */
4877 for (i = 0; i < reload_n_operands; i++)
4878 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4879 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4880 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4885 case RELOAD_FOR_OPADDR_ADDR:
4886 for (i = 0; i < reload_n_operands; i++)
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4888 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4892 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4893 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4895 case RELOAD_FOR_INSN:
4896 /* These conflict with other outputs with RELOAD_OTHER. So
4897 we need only check for output addresses. */
4901 /* ... fall through ... */
4903 case RELOAD_FOR_OUTPUT:
4904 case RELOAD_FOR_OUTPUT_ADDRESS:
4905 case RELOAD_FOR_OUTADDR_ADDRESS:
4906 /* We already know these can't conflict with a later output. So the
4907 only thing to check are later output addresses. */
4908 for (i = opnum + 1; i < reload_n_operands; i++)
4909 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4910 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4919 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4922 This function uses the same algorithm as reload_reg_free_p above. */
4925 reloads_conflict (r1, r2)
4928 enum reload_type r1_type = reload_when_needed[r1];
4929 enum reload_type r2_type = reload_when_needed[r2];
4930 int r1_opnum = reload_opnum[r1];
4931 int r2_opnum = reload_opnum[r2];
4933 /* RELOAD_OTHER conflicts with everything. */
4934 if (r2_type == RELOAD_OTHER)
4937 /* Otherwise, check conflicts differently for each type. */
4941 case RELOAD_FOR_INPUT:
4942 return (r2_type == RELOAD_FOR_INSN
4943 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4944 || r2_type == RELOAD_FOR_OPADDR_ADDR
4945 || r2_type == RELOAD_FOR_INPUT
4946 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4947 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4948 && r2_opnum > r1_opnum));
4950 case RELOAD_FOR_INPUT_ADDRESS:
4951 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4952 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4954 case RELOAD_FOR_INPADDR_ADDRESS:
4955 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4956 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4958 case RELOAD_FOR_OUTPUT_ADDRESS:
4959 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4960 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4962 case RELOAD_FOR_OUTADDR_ADDRESS:
4963 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4964 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4966 case RELOAD_FOR_OPERAND_ADDRESS:
4967 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4968 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4970 case RELOAD_FOR_OPADDR_ADDR:
4971 return (r2_type == RELOAD_FOR_INPUT
4972 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4974 case RELOAD_FOR_OUTPUT:
4975 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4976 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4977 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4978 && r2_opnum >= r1_opnum));
4980 case RELOAD_FOR_INSN:
4981 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4982 || r2_type == RELOAD_FOR_INSN
4983 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4985 case RELOAD_FOR_OTHER_ADDRESS:
4986 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4996 /* Vector of reload-numbers showing the order in which the reloads should
4998 short reload_order[MAX_RELOADS];
5000 /* Indexed by reload number, 1 if incoming value
5001 inherited from previous insns. */
5002 char reload_inherited[MAX_RELOADS];
5004 /* For an inherited reload, this is the insn the reload was inherited from,
5005 if we know it. Otherwise, this is 0. */
5006 rtx reload_inheritance_insn[MAX_RELOADS];
5008 /* If non-zero, this is a place to get the value of the reload,
5009 rather than using reload_in. */
5010 rtx reload_override_in[MAX_RELOADS];
5012 /* For each reload, the hard register number of the register used,
5013 or -1 if we did not need a register for this reload. */
5014 int reload_spill_index[MAX_RELOADS];
5016 /* Return 1 if the value in reload reg REGNO, as used by a reload
5017 needed for the part of the insn specified by OPNUM and TYPE,
5018 may be used to load VALUE into it.
5020 Other read-only reloads with the same value do not conflict
5021 unless OUT is non-zero and these other reloads have to live while
5022 output reloads live.
5024 RELOADNUM is the number of the reload we want to load this value for;
5025 a reload does not conflict with itself.
5027 The caller has to make sure that there is no conflict with the return
5030 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum)
5033 enum reload_type type;
5040 /* We use some pseudo 'time' value to check if the lifetimes of the
5041 new register use would overlap with the one of a previous reload
5042 that is not read-only or uses a different value.
5043 The 'time' used doesn't have to be linear in any shape or form, just
5045 Some reload types use different 'buckets' for each operand.
5046 So there are MAX_RECOG_OPERANDS different time values for each
5048 We compute TIME1 as the time when the register for the prospective
5049 new reload ceases to be live, and TIME2 for each existing
5050 reload as the time when that the reload register of that reload
5052 Where there is little to be gained by exact lifetime calculations,
5053 we just make conservative assumptions, i.e. a longer lifetime;
5054 this is done in the 'default:' cases. */
5057 case RELOAD_FOR_OTHER_ADDRESS:
5060 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5061 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5062 respectively, to the time values for these, we get distinct time
5063 values. To get distinct time values for each operand, we have to
5064 multiply opnum by at least three. We round that up to four because
5065 multiply by four is often cheaper. */
5066 case RELOAD_FOR_INPADDR_ADDRESS:
5067 time1 = opnum * 4 + 1;
5069 case RELOAD_FOR_INPUT_ADDRESS:
5070 time1 = opnum * 4 + 2;
5072 case RELOAD_FOR_INPUT:
5073 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5074 instruction is executed. */
5075 time1 = (MAX_RECOG_OPERANDS - 1) * 4 + 3;
5077 /* opnum * 4 + 3 < opnum * 4 + 4
5078 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5079 case RELOAD_FOR_OUTPUT_ADDRESS:
5080 time1 = MAX_RECOG_OPERANDS * 4 + opnum;
5083 time1 = MAX_RECOG_OPERANDS * 5;
5086 for (i = 0; i < n_reloads; i++)
5088 rtx reg = reload_reg_rtx[i];
5089 if (reg && GET_CODE (reg) == REG
5090 && ((unsigned) regno - true_regnum (reg)
5091 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5095 && reload_when_needed[i] != RELOAD_FOR_INPUT
5096 && reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
5097 && reload_when_needed[i] != RELOAD_FOR_INPADDR_ADDRESS)
5099 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5103 switch (reload_when_needed[i])
5105 case RELOAD_FOR_OTHER_ADDRESS:
5108 case RELOAD_FOR_INPADDR_ADDRESS:
5109 time2 = reload_opnum[i] * 4 + 1;
5111 case RELOAD_FOR_INPUT_ADDRESS:
5112 time2 = reload_opnum[i] * 4 + 2;
5114 case RELOAD_FOR_INPUT:
5115 time2 = reload_opnum[i] * 4 + 3;
5117 case RELOAD_FOR_OUTPUT:
5118 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5119 instruction is executed. */
5120 time2 = MAX_RECOG_OPERANDS * 4;
5122 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5123 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5124 case RELOAD_FOR_OUTPUT_ADDRESS:
5125 time2 = MAX_RECOG_OPERANDS * 4 + reload_opnum[i];
5128 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5130 time2 = MAX_RECOG_OPERANDS * 4;
5144 /* Find a spill register to use as a reload register for reload R.
5145 LAST_RELOAD is non-zero if this is the last reload for the insn being
5148 Set reload_reg_rtx[R] to the register allocated.
5150 If NOERROR is nonzero, we return 1 if successful,
5151 or 0 if we couldn't find a spill reg and we didn't change anything. */
5154 allocate_reload_reg (r, insn, last_reload, noerror)
5166 /* If we put this reload ahead, thinking it is a group,
5167 then insist on finding a group. Otherwise we can grab a
5168 reg that some other reload needs.
5169 (That can happen when we have a 68000 DATA_OR_FP_REG
5170 which is a group of data regs or one fp reg.)
5171 We need not be so restrictive if there are no more reloads
5174 ??? Really it would be nicer to have smarter handling
5175 for that kind of reg class, where a problem like this is normal.
5176 Perhaps those classes should be avoided for reloading
5177 by use of more alternatives. */
5179 int force_group = reload_nregs[r] > 1 && ! last_reload;
5181 /* If we want a single register and haven't yet found one,
5182 take any reg in the right class and not in use.
5183 If we want a consecutive group, here is where we look for it.
5185 We use two passes so we can first look for reload regs to
5186 reuse, which are already in use for other reloads in this insn,
5187 and only then use additional registers.
5188 I think that maximizing reuse is needed to make sure we don't
5189 run out of reload regs. Suppose we have three reloads, and
5190 reloads A and B can share regs. These need two regs.
5191 Suppose A and B are given different regs.
5192 That leaves none for C. */
5193 for (pass = 0; pass < 2; pass++)
5195 /* I is the index in spill_regs.
5196 We advance it round-robin between insns to use all spill regs
5197 equally, so that inherited reloads have a chance
5198 of leapfrogging each other. Don't do this, however, when we have
5199 group needs and failure would be fatal; if we only have a relatively
5200 small number of spill registers, and more than one of them has
5201 group needs, then by starting in the middle, we may end up
5202 allocating the first one in such a way that we are not left with
5203 sufficient groups to handle the rest. */
5205 if (noerror || ! force_group)
5210 for (count = 0; count < n_spills; count++)
5212 int class = (int) reload_reg_class[r];
5214 i = (i + 1) % n_spills;
5216 if ((reload_reg_free_p (spill_regs[i], reload_opnum[r],
5217 reload_when_needed[r])
5219 /* We check reload_reg_used to make sure we
5220 don't clobber the return register. */
5221 && ! TEST_HARD_REG_BIT (reload_reg_used, spill_regs[i])
5222 && reload_reg_free_for_value_p (spill_regs[i],
5224 reload_when_needed[r],
5227 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5228 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5229 /* Look first for regs to share, then for unshared. But
5230 don't share regs used for inherited reloads; they are
5231 the ones we want to preserve. */
5233 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5235 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5238 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5239 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5240 (on 68000) got us two FP regs. If NR is 1,
5241 we would reject both of them. */
5243 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5244 /* If we need only one reg, we have already won. */
5247 /* But reject a single reg if we demand a group. */
5252 /* Otherwise check that as many consecutive regs as we need
5254 Also, don't use for a group registers that are
5255 needed for nongroups. */
5256 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5259 regno = spill_regs[i] + nr - 1;
5260 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5261 && spill_reg_order[regno] >= 0
5262 && reload_reg_free_p (regno, reload_opnum[r],
5263 reload_when_needed[r])
5264 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5274 /* If we found something on pass 1, omit pass 2. */
5275 if (count < n_spills)
5279 /* We should have found a spill register by now. */
5280 if (count == n_spills)
5287 /* I is the index in SPILL_REG_RTX of the reload register we are to
5288 allocate. Get an rtx for it and find its register number. */
5290 new = spill_reg_rtx[i];
5292 if (new == 0 || GET_MODE (new) != reload_mode[r])
5293 spill_reg_rtx[i] = new
5294 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5296 regno = true_regnum (new);
5298 /* Detect when the reload reg can't hold the reload mode.
5299 This used to be one `if', but Sequent compiler can't handle that. */
5300 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5302 enum machine_mode test_mode = VOIDmode;
5304 test_mode = GET_MODE (reload_in[r]);
5305 /* If reload_in[r] has VOIDmode, it means we will load it
5306 in whatever mode the reload reg has: to wit, reload_mode[r].
5307 We have already tested that for validity. */
5308 /* Aside from that, we need to test that the expressions
5309 to reload from or into have modes which are valid for this
5310 reload register. Otherwise the reload insns would be invalid. */
5311 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5312 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5313 if (! (reload_out[r] != 0
5314 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5316 /* The reg is OK. */
5319 /* Mark as in use for this insn the reload regs we use
5321 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5322 reload_when_needed[r], reload_mode[r]);
5324 reload_reg_rtx[r] = new;
5325 reload_spill_index[r] = spill_regs[i];
5330 /* The reg is not OK. */
5335 if (asm_noperands (PATTERN (insn)) < 0)
5336 /* It's the compiler's fault. */
5337 fatal_insn ("Could not find a spill register", insn);
5339 /* It's the user's fault; the operand's mode and constraint
5340 don't match. Disable this reload so we don't crash in final. */
5341 error_for_asm (insn,
5342 "`asm' operand constraint incompatible with operand size");
5345 reload_reg_rtx[r] = 0;
5346 reload_optional[r] = 1;
5347 reload_secondary_p[r] = 1;
5352 /* Assign hard reg targets for the pseudo-registers we must reload
5353 into hard regs for this insn.
5354 Also output the instructions to copy them in and out of the hard regs.
5356 For machines with register classes, we are responsible for
5357 finding a reload reg in the proper class. */
5360 choose_reload_regs (insn, avoid_return_reg)
5362 rtx avoid_return_reg;
5365 int max_group_size = 1;
5366 enum reg_class group_class = NO_REGS;
5369 rtx save_reload_reg_rtx[MAX_RELOADS];
5370 char save_reload_inherited[MAX_RELOADS];
5371 rtx save_reload_inheritance_insn[MAX_RELOADS];
5372 rtx save_reload_override_in[MAX_RELOADS];
5373 int save_reload_spill_index[MAX_RELOADS];
5374 HARD_REG_SET save_reload_reg_used;
5375 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5376 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5377 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5378 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5379 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5380 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5381 HARD_REG_SET save_reload_reg_used_in_op_addr;
5382 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5383 HARD_REG_SET save_reload_reg_used_in_insn;
5384 HARD_REG_SET save_reload_reg_used_in_other_addr;
5385 HARD_REG_SET save_reload_reg_used_at_all;
5387 bzero (reload_inherited, MAX_RELOADS);
5388 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5389 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5391 CLEAR_HARD_REG_SET (reload_reg_used);
5392 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5393 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5394 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5395 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5396 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5398 for (i = 0; i < reload_n_operands; i++)
5400 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5401 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5402 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5403 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5404 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5405 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5408 /* Don't bother with avoiding the return reg
5409 if we have no mandatory reload that could use it. */
5410 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5413 int regno = REGNO (avoid_return_reg);
5415 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5418 for (r = regno; r < regno + nregs; r++)
5419 if (spill_reg_order[r] >= 0)
5420 for (j = 0; j < n_reloads; j++)
5421 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5422 && (reload_in[j] != 0 || reload_out[j] != 0
5423 || reload_secondary_p[j])
5425 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5428 avoid_return_reg = 0;
5431 #if 0 /* Not needed, now that we can always retry without inheritance. */
5432 /* See if we have more mandatory reloads than spill regs.
5433 If so, then we cannot risk optimizations that could prevent
5434 reloads from sharing one spill register.
5436 Since we will try finding a better register than reload_reg_rtx
5437 unless it is equal to reload_in or reload_out, count such reloads. */
5440 int tem = SMALL_REGISTER_CLASSES? (avoid_return_reg != 0): 0;
5441 for (j = 0; j < n_reloads; j++)
5442 if (! reload_optional[j]
5443 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5444 && (reload_reg_rtx[j] == 0
5445 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5446 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5453 /* Don't use the subroutine call return reg for a reload
5454 if we are supposed to avoid it. */
5455 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5457 int regno = REGNO (avoid_return_reg);
5459 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5462 for (r = regno; r < regno + nregs; r++)
5463 if (spill_reg_order[r] >= 0)
5464 SET_HARD_REG_BIT (reload_reg_used, r);
5467 /* In order to be certain of getting the registers we need,
5468 we must sort the reloads into order of increasing register class.
5469 Then our grabbing of reload registers will parallel the process
5470 that provided the reload registers.
5472 Also note whether any of the reloads wants a consecutive group of regs.
5473 If so, record the maximum size of the group desired and what
5474 register class contains all the groups needed by this insn. */
5476 for (j = 0; j < n_reloads; j++)
5478 reload_order[j] = j;
5479 reload_spill_index[j] = -1;
5482 = (reload_inmode[j] == VOIDmode
5483 || (GET_MODE_SIZE (reload_outmode[j])
5484 > GET_MODE_SIZE (reload_inmode[j])))
5485 ? reload_outmode[j] : reload_inmode[j];
5487 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5489 if (reload_nregs[j] > 1)
5491 max_group_size = MAX (reload_nregs[j], max_group_size);
5492 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5495 /* If we have already decided to use a certain register,
5496 don't use it in another way. */
5497 if (reload_reg_rtx[j])
5498 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5499 reload_when_needed[j], reload_mode[j]);
5503 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5505 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5506 sizeof reload_reg_rtx);
5507 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5508 bcopy ((char *) reload_inheritance_insn,
5509 (char *) save_reload_inheritance_insn,
5510 sizeof reload_inheritance_insn);
5511 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5512 sizeof reload_override_in);
5513 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5514 sizeof reload_spill_index);
5515 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5516 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5517 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5518 reload_reg_used_in_op_addr);
5520 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5521 reload_reg_used_in_op_addr_reload);
5523 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5524 reload_reg_used_in_insn);
5525 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5526 reload_reg_used_in_other_addr);
5528 for (i = 0; i < reload_n_operands; i++)
5530 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5531 reload_reg_used_in_output[i]);
5532 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5533 reload_reg_used_in_input[i]);
5534 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5535 reload_reg_used_in_input_addr[i]);
5536 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5537 reload_reg_used_in_inpaddr_addr[i]);
5538 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5539 reload_reg_used_in_output_addr[i]);
5540 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5541 reload_reg_used_in_outaddr_addr[i]);
5544 /* If -O, try first with inheritance, then turning it off.
5545 If not -O, don't do inheritance.
5546 Using inheritance when not optimizing leads to paradoxes
5547 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5548 because one side of the comparison might be inherited. */
5550 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5552 /* Process the reloads in order of preference just found.
5553 Beyond this point, subregs can be found in reload_reg_rtx.
5555 This used to look for an existing reloaded home for all
5556 of the reloads, and only then perform any new reloads.
5557 But that could lose if the reloads were done out of reg-class order
5558 because a later reload with a looser constraint might have an old
5559 home in a register needed by an earlier reload with a tighter constraint.
5561 To solve this, we make two passes over the reloads, in the order
5562 described above. In the first pass we try to inherit a reload
5563 from a previous insn. If there is a later reload that needs a
5564 class that is a proper subset of the class being processed, we must
5565 also allocate a spill register during the first pass.
5567 Then make a second pass over the reloads to allocate any reloads
5568 that haven't been given registers yet. */
5570 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5572 for (j = 0; j < n_reloads; j++)
5574 register int r = reload_order[j];
5576 /* Ignore reloads that got marked inoperative. */
5577 if (reload_out[r] == 0 && reload_in[r] == 0
5578 && ! reload_secondary_p[r])
5581 /* If find_reloads chose a to use reload_in or reload_out as a reload
5582 register, we don't need to chose one. Otherwise, try even if it
5583 found one since we might save an insn if we find the value lying
5585 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5586 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5587 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5590 #if 0 /* No longer needed for correct operation.
5591 It might give better code, or might not; worth an experiment? */
5592 /* If this is an optional reload, we can't inherit from earlier insns
5593 until we are sure that any non-optional reloads have been allocated.
5594 The following code takes advantage of the fact that optional reloads
5595 are at the end of reload_order. */
5596 if (reload_optional[r] != 0)
5597 for (i = 0; i < j; i++)
5598 if ((reload_out[reload_order[i]] != 0
5599 || reload_in[reload_order[i]] != 0
5600 || reload_secondary_p[reload_order[i]])
5601 && ! reload_optional[reload_order[i]]
5602 && reload_reg_rtx[reload_order[i]] == 0)
5603 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5606 /* First see if this pseudo is already available as reloaded
5607 for a previous insn. We cannot try to inherit for reloads
5608 that are smaller than the maximum number of registers needed
5609 for groups unless the register we would allocate cannot be used
5612 We could check here to see if this is a secondary reload for
5613 an object that is already in a register of the desired class.
5614 This would avoid the need for the secondary reload register.
5615 But this is complex because we can't easily determine what
5616 objects might want to be loaded via this reload. So let a
5617 register be allocated here. In `emit_reload_insns' we suppress
5618 one of the loads in the case described above. */
5622 register int regno = -1;
5623 enum machine_mode mode;
5625 if (reload_in[r] == 0)
5627 else if (GET_CODE (reload_in[r]) == REG)
5629 regno = REGNO (reload_in[r]);
5630 mode = GET_MODE (reload_in[r]);
5632 else if (GET_CODE (reload_in_reg[r]) == REG)
5634 regno = REGNO (reload_in_reg[r]);
5635 mode = GET_MODE (reload_in_reg[r]);
5637 else if (GET_CODE (reload_in[r]) == MEM)
5639 rtx prev = prev_nonnote_insn (insn), note;
5641 if (prev && GET_CODE (prev) == INSN
5642 && GET_CODE (PATTERN (prev)) == USE
5643 && GET_CODE (XEXP (PATTERN (prev), 0)) == REG
5644 && (REGNO (XEXP (PATTERN (prev), 0))
5645 >= FIRST_PSEUDO_REGISTER)
5646 && (note = find_reg_note (prev, REG_EQUAL, NULL_RTX))
5647 && GET_CODE (XEXP (note, 0)) == MEM)
5649 rtx addr = XEXP (XEXP (note, 0), 0);
5651 = (GET_MODE_SIZE (GET_MODE (addr))
5652 - GET_MODE_SIZE (GET_MODE (reload_in[r])));
5654 && rtx_equal_p ((BYTES_BIG_ENDIAN
5655 ? plus_constant (addr, size_diff)
5657 XEXP (reload_in[r], 0)))
5659 regno = REGNO (XEXP (PATTERN (prev), 0));
5660 mode = GET_MODE (reload_in[r]);
5665 /* This won't work, since REGNO can be a pseudo reg number.
5666 Also, it takes much more hair to keep track of all the things
5667 that can invalidate an inherited reload of part of a pseudoreg. */
5668 else if (GET_CODE (reload_in[r]) == SUBREG
5669 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5670 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5673 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5675 i = REGNO (reg_last_reload_reg[regno]);
5677 if (reg_reloaded_contents[i] == regno
5678 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5679 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5680 >= GET_MODE_SIZE (mode))
5681 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5682 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5684 && (reload_nregs[r] == max_group_size
5685 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5687 && ((reload_reg_free_p (i, reload_opnum[r],
5688 reload_when_needed[r])
5689 && reload_reg_free_before_p (i, reload_opnum[r],
5690 reload_when_needed[r]))
5691 || reload_reg_free_for_value_p (i, reload_opnum[r],
5692 reload_when_needed[r],
5696 /* If a group is needed, verify that all the subsequent
5697 registers still have their values intact. */
5699 = HARD_REGNO_NREGS (i, reload_mode[r]);
5702 for (k = 1; k < nr; k++)
5703 if (reg_reloaded_contents[i + k] != regno
5704 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5711 /* We found a register that contains the
5712 value we need. If this register is the
5713 same as an `earlyclobber' operand of the
5714 current insn, just mark it as a place to
5715 reload from since we can't use it as the
5716 reload register itself. */
5718 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5719 if (reg_overlap_mentioned_for_reload_p
5720 (reg_last_reload_reg[regno],
5721 reload_earlyclobbers[i1]))
5724 if (i1 != n_earlyclobbers
5725 /* Don't use it if we'd clobber a pseudo reg. */
5726 || (spill_reg_order[i] < 0
5728 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5729 /* Don't really use the inherited spill reg
5730 if we need it wider than we've got it. */
5731 || (GET_MODE_SIZE (reload_mode[r])
5732 > GET_MODE_SIZE (mode)))
5733 reload_override_in[r] = reg_last_reload_reg[regno];
5737 /* We can use this as a reload reg. */
5738 /* Mark the register as in use for this part of
5740 mark_reload_reg_in_use (i,
5742 reload_when_needed[r],
5744 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5745 reload_inherited[r] = 1;
5746 reload_inheritance_insn[r]
5747 = reg_reloaded_insn[i];
5748 reload_spill_index[r] = i;
5749 for (k = 0; k < nr; k++)
5750 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5758 /* Here's another way to see if the value is already lying around. */
5760 && reload_in[r] != 0
5761 && ! reload_inherited[r]
5762 && reload_out[r] == 0
5763 && (CONSTANT_P (reload_in[r])
5764 || GET_CODE (reload_in[r]) == PLUS
5765 || GET_CODE (reload_in[r]) == REG
5766 || GET_CODE (reload_in[r]) == MEM)
5767 && (reload_nregs[r] == max_group_size
5768 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5771 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5772 -1, NULL_PTR, 0, reload_mode[r]);
5777 if (GET_CODE (equiv) == REG)
5778 regno = REGNO (equiv);
5779 else if (GET_CODE (equiv) == SUBREG)
5781 /* This must be a SUBREG of a hard register.
5782 Make a new REG since this might be used in an
5783 address and not all machines support SUBREGs
5785 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5786 equiv = gen_rtx_REG (reload_mode[r], regno);
5792 /* If we found a spill reg, reject it unless it is free
5793 and of the desired class. */
5795 && ((spill_reg_order[regno] >= 0
5796 && ! (reload_reg_free_before_p (regno, reload_opnum[r],
5797 reload_when_needed[r])
5798 || reload_reg_free_for_value_p (regno,
5800 reload_when_needed[r],
5803 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5807 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5810 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5813 /* We found a register that contains the value we need.
5814 If this register is the same as an `earlyclobber' operand
5815 of the current insn, just mark it as a place to reload from
5816 since we can't use it as the reload register itself. */
5819 for (i = 0; i < n_earlyclobbers; i++)
5820 if (reg_overlap_mentioned_for_reload_p (equiv,
5821 reload_earlyclobbers[i]))
5823 reload_override_in[r] = equiv;
5828 /* JRV: If the equiv register we have found is
5829 explicitly clobbered in the current insn, mark but
5830 don't use, as above. */
5832 if (equiv != 0 && regno_clobbered_p (regno, insn))
5834 reload_override_in[r] = equiv;
5838 /* If we found an equivalent reg, say no code need be generated
5839 to load it, and use it as our reload reg. */
5840 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5842 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5844 reload_reg_rtx[r] = equiv;
5845 reload_inherited[r] = 1;
5847 /* If any of the hard registers in EQUIV are spill
5848 registers, mark them as in use for this insn. */
5849 for (k = 0; k < nr; k++)
5851 i = spill_reg_order[regno + k];
5854 mark_reload_reg_in_use (regno, reload_opnum[r],
5855 reload_when_needed[r],
5857 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5864 /* If we found a register to use already, or if this is an optional
5865 reload, we are done. */
5866 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5869 #if 0 /* No longer needed for correct operation. Might or might not
5870 give better code on the average. Want to experiment? */
5872 /* See if there is a later reload that has a class different from our
5873 class that intersects our class or that requires less register
5874 than our reload. If so, we must allocate a register to this
5875 reload now, since that reload might inherit a previous reload
5876 and take the only available register in our class. Don't do this
5877 for optional reloads since they will force all previous reloads
5878 to be allocated. Also don't do this for reloads that have been
5881 for (i = j + 1; i < n_reloads; i++)
5883 int s = reload_order[i];
5885 if ((reload_in[s] == 0 && reload_out[s] == 0
5886 && ! reload_secondary_p[s])
5887 || reload_optional[s])
5890 if ((reload_reg_class[s] != reload_reg_class[r]
5891 && reg_classes_intersect_p (reload_reg_class[r],
5892 reload_reg_class[s]))
5893 || reload_nregs[s] < reload_nregs[r])
5900 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5904 /* Now allocate reload registers for anything non-optional that
5905 didn't get one yet. */
5906 for (j = 0; j < n_reloads; j++)
5908 register int r = reload_order[j];
5910 /* Ignore reloads that got marked inoperative. */
5911 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5914 /* Skip reloads that already have a register allocated or are
5916 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5919 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5923 /* If that loop got all the way, we have won. */
5928 /* Loop around and try without any inheritance. */
5929 /* First undo everything done by the failed attempt
5930 to allocate with inheritance. */
5931 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5932 sizeof reload_reg_rtx);
5933 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5934 sizeof reload_inherited);
5935 bcopy ((char *) save_reload_inheritance_insn,
5936 (char *) reload_inheritance_insn,
5937 sizeof reload_inheritance_insn);
5938 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5939 sizeof reload_override_in);
5940 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5941 sizeof reload_spill_index);
5942 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5943 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5944 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5945 save_reload_reg_used_in_op_addr);
5946 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5947 save_reload_reg_used_in_op_addr_reload);
5948 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5949 save_reload_reg_used_in_insn);
5950 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5951 save_reload_reg_used_in_other_addr);
5953 for (i = 0; i < reload_n_operands; i++)
5955 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5956 save_reload_reg_used_in_input[i]);
5957 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5958 save_reload_reg_used_in_output[i]);
5959 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5960 save_reload_reg_used_in_input_addr[i]);
5961 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
5962 save_reload_reg_used_in_inpaddr_addr[i]);
5963 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5964 save_reload_reg_used_in_output_addr[i]);
5965 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
5966 save_reload_reg_used_in_outaddr_addr[i]);
5970 /* If we thought we could inherit a reload, because it seemed that
5971 nothing else wanted the same reload register earlier in the insn,
5972 verify that assumption, now that all reloads have been assigned. */
5974 for (j = 0; j < n_reloads; j++)
5976 register int r = reload_order[j];
5978 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5979 && ! (reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5981 reload_when_needed[r])
5982 || reload_reg_free_for_value_p (true_regnum (reload_reg_rtx[r]),
5984 reload_when_needed[r],
5987 reload_inherited[r] = 0;
5988 /* If we can inherit a RELOAD_FOR_INPUT, then we do not need its related
5989 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads.
5990 ??? This could be extended to other reload types, but these are
5991 more tricky to handle:
5992 RELOAD_FOR_OTHER_ADDRESS reloads might have been merged, so we
5993 can't eliminate them without a check that *all* references are
5994 now unused due to inheritance.
5995 While RELOAD_FOR_INPADDR_ADDRESS and RELOAD_FOR_OUTADDR_ADDRESS are
5996 not merged, we can't be sure that we have eliminated the use of
5997 that particular reload if we have seen just one
5998 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_OUTPUT_ADDRESS being inherited,
5999 since there might be multiple of the latter two reloads for a single
6001 RELOAD_FOR_OPADDR_ADDR reloads for different operands are not
6002 merged, but might share the same register by courtesy of
6003 reload_reg_free_for_value_p. reload_reg_used_in_op_addr_reload
6004 does not differentiate by opnum, thus calling clear_reload_reg_in_use
6005 for one of these reloads would mark the register as free even though
6006 another RELOAD_FOR_OPADDR_ADDR reload might still use it. */
6007 else if (reload_inherited[r] && reload_when_needed[r] == RELOAD_FOR_INPUT)
6009 for (i = 0; i < n_reloads; i++)
6011 if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6012 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6013 && reload_opnum[i] == reload_opnum[r]
6014 && reload_in[i] && reload_reg_rtx[i])
6016 int regno = true_regnum (reload_reg_rtx[i]);
6019 if (spill_reg_order[regno] >= 0)
6020 clear_reload_reg_in_use (regno, reload_opnum[i],
6021 reload_when_needed[i],
6023 reload_reg_rtx[i] = 0;
6024 reload_spill_index[i] = -1;
6025 remove_replacements (i);
6030 /* If we found a better place to reload from,
6031 validate it in the same fashion, if it is a reload reg. */
6032 if (reload_override_in[r]
6033 && (GET_CODE (reload_override_in[r]) == REG
6034 || GET_CODE (reload_override_in[r]) == SUBREG))
6036 int regno = true_regnum (reload_override_in[r]);
6037 if (spill_reg_order[regno] >= 0
6038 && ! reload_reg_free_before_p (regno, reload_opnum[r],
6039 reload_when_needed[r]))
6040 reload_override_in[r] = 0;
6044 /* Now that reload_override_in is known valid,
6045 actually override reload_in. */
6046 for (j = 0; j < n_reloads; j++)
6047 if (reload_override_in[j])
6048 reload_in[j] = reload_override_in[j];
6050 /* If this reload won't be done because it has been cancelled or is
6051 optional and not inherited, clear reload_reg_rtx so other
6052 routines (such as subst_reloads) don't get confused. */
6053 for (j = 0; j < n_reloads; j++)
6054 if (reload_reg_rtx[j] != 0
6055 && ((reload_optional[j] && ! reload_inherited[j])
6056 || (reload_in[j] == 0 && reload_out[j] == 0
6057 && ! reload_secondary_p[j])))
6059 int regno = true_regnum (reload_reg_rtx[j]);
6061 if (spill_reg_order[regno] >= 0)
6062 clear_reload_reg_in_use (regno, reload_opnum[j],
6063 reload_when_needed[j], reload_mode[j]);
6064 reload_reg_rtx[j] = 0;
6067 /* Record which pseudos and which spill regs have output reloads. */
6068 for (j = 0; j < n_reloads; j++)
6070 register int r = reload_order[j];
6072 i = reload_spill_index[r];
6074 /* I is nonneg if this reload uses a register.
6075 If reload_reg_rtx[r] is 0, this is an optional reload
6076 that we opted to ignore. */
6077 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
6078 && reload_reg_rtx[r] != 0)
6080 register int nregno = REGNO (reload_out[r]);
6083 if (nregno < FIRST_PSEUDO_REGISTER)
6084 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6087 reg_has_output_reload[nregno + nr] = 1;
6091 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6093 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6096 if (reload_when_needed[r] != RELOAD_OTHER
6097 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6098 && reload_when_needed[r] != RELOAD_FOR_INSN)
6104 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6105 reloads of the same item for fear that we might not have enough reload
6106 registers. However, normally they will get the same reload register
6107 and hence actually need not be loaded twice.
6109 Here we check for the most common case of this phenomenon: when we have
6110 a number of reloads for the same object, each of which were allocated
6111 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6112 reload, and is not modified in the insn itself. If we find such,
6113 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6114 This will not increase the number of spill registers needed and will
6115 prevent redundant code. */
6118 merge_assigned_reloads (insn)
6123 /* Scan all the reloads looking for ones that only load values and
6124 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6125 assigned and not modified by INSN. */
6127 for (i = 0; i < n_reloads; i++)
6129 int conflicting_input = 0;
6130 int max_input_address_opnum = -1;
6131 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6133 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6134 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6135 || reg_set_p (reload_reg_rtx[i], insn))
6138 /* Look at all other reloads. Ensure that the only use of this
6139 reload_reg_rtx is in a reload that just loads the same value
6140 as we do. Note that any secondary reloads must be of the identical
6141 class since the values, modes, and result registers are the
6142 same, so we need not do anything with any secondary reloads. */
6144 for (j = 0; j < n_reloads; j++)
6146 if (i == j || reload_reg_rtx[j] == 0
6147 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6151 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6152 && reload_opnum[j] > max_input_address_opnum)
6153 max_input_address_opnum = reload_opnum[j];
6155 /* If the reload regs aren't exactly the same (e.g, different modes)
6156 or if the values are different, we can't merge this reload.
6157 But if it is an input reload, we might still merge
6158 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6160 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6161 || reload_out[j] != 0 || reload_in[j] == 0
6162 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6164 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6165 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6166 || reload_opnum[i] > reload_opnum[j])
6167 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6169 conflicting_input = 1;
6170 if (min_conflicting_input_opnum > reload_opnum[j])
6171 min_conflicting_input_opnum = reload_opnum[j];
6175 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6176 we, in fact, found any matching reloads. */
6179 && max_input_address_opnum <= min_conflicting_input_opnum)
6181 for (j = 0; j < n_reloads; j++)
6182 if (i != j && reload_reg_rtx[j] != 0
6183 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6184 && (! conflicting_input
6185 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6186 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6188 reload_when_needed[i] = RELOAD_OTHER;
6190 reload_spill_index[j] = -1;
6191 transfer_replacements (i, j);
6194 /* If this is now RELOAD_OTHER, look for any reloads that load
6195 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6196 if they were for inputs, RELOAD_OTHER for outputs. Note that
6197 this test is equivalent to looking for reloads for this operand
6200 if (reload_when_needed[i] == RELOAD_OTHER)
6201 for (j = 0; j < n_reloads; j++)
6202 if (reload_in[j] != 0
6203 && reload_when_needed[i] != RELOAD_OTHER
6204 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6206 reload_when_needed[j]
6207 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6208 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6209 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6215 /* Output insns to reload values in and out of the chosen reload regs. */
6218 emit_reload_insns (insn)
6222 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6223 rtx other_input_address_reload_insns = 0;
6224 rtx other_input_reload_insns = 0;
6225 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6226 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6227 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6228 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6229 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6230 rtx operand_reload_insns = 0;
6231 rtx other_operand_reload_insns = 0;
6232 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6233 rtx following_insn = NEXT_INSN (insn);
6234 rtx before_insn = insn;
6236 /* Values to be put in spill_reg_store are put here first. */
6237 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6238 HARD_REG_SET reg_reloaded_died;
6240 CLEAR_HARD_REG_SET (reg_reloaded_died);
6242 for (j = 0; j < reload_n_operands; j++)
6243 input_reload_insns[j] = input_address_reload_insns[j]
6244 = inpaddr_address_reload_insns[j]
6245 = output_reload_insns[j] = output_address_reload_insns[j]
6246 = outaddr_address_reload_insns[j]
6247 = other_output_reload_insns[j] = 0;
6249 /* Now output the instructions to copy the data into and out of the
6250 reload registers. Do these in the order that the reloads were reported,
6251 since reloads of base and index registers precede reloads of operands
6252 and the operands may need the base and index registers reloaded. */
6254 for (j = 0; j < n_reloads; j++)
6257 rtx oldequiv_reg = 0;
6258 rtx this_reload_insn = 0;
6259 int expect_occurrences = 1;
6261 if (reload_spill_index[j] >= 0)
6262 new_spill_reg_store[reload_spill_index[j]] = 0;
6265 if (old != 0 && ! reload_inherited[j]
6266 && ! rtx_equal_p (reload_reg_rtx[j], old)
6267 && reload_reg_rtx[j] != 0)
6269 register rtx reloadreg = reload_reg_rtx[j];
6271 enum machine_mode mode;
6274 /* Determine the mode to reload in.
6275 This is very tricky because we have three to choose from.
6276 There is the mode the insn operand wants (reload_inmode[J]).
6277 There is the mode of the reload register RELOADREG.
6278 There is the intrinsic mode of the operand, which we could find
6279 by stripping some SUBREGs.
6280 It turns out that RELOADREG's mode is irrelevant:
6281 we can change that arbitrarily.
6283 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6284 then the reload reg may not support QImode moves, so use SImode.
6285 If foo is in memory due to spilling a pseudo reg, this is safe,
6286 because the QImode value is in the least significant part of a
6287 slot big enough for a SImode. If foo is some other sort of
6288 memory reference, then it is impossible to reload this case,
6289 so previous passes had better make sure this never happens.
6291 Then consider a one-word union which has SImode and one of its
6292 members is a float, being fetched as (SUBREG:SF union:SI).
6293 We must fetch that as SFmode because we could be loading into
6294 a float-only register. In this case OLD's mode is correct.
6296 Consider an immediate integer: it has VOIDmode. Here we need
6297 to get a mode from something else.
6299 In some cases, there is a fourth mode, the operand's
6300 containing mode. If the insn specifies a containing mode for
6301 this operand, it overrides all others.
6303 I am not sure whether the algorithm here is always right,
6304 but it does the right things in those cases. */
6306 mode = GET_MODE (old);
6307 if (mode == VOIDmode)
6308 mode = reload_inmode[j];
6310 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6311 /* If we need a secondary register for this operation, see if
6312 the value is already in a register in that class. Don't
6313 do this if the secondary register will be used as a scratch
6316 if (reload_secondary_in_reload[j] >= 0
6317 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6320 = find_equiv_reg (old, insn,
6321 reload_reg_class[reload_secondary_in_reload[j]],
6322 -1, NULL_PTR, 0, mode);
6325 /* If reloading from memory, see if there is a register
6326 that already holds the same value. If so, reload from there.
6327 We can pass 0 as the reload_reg_p argument because
6328 any other reload has either already been emitted,
6329 in which case find_equiv_reg will see the reload-insn,
6330 or has yet to be emitted, in which case it doesn't matter
6331 because we will use this equiv reg right away. */
6333 if (oldequiv == 0 && optimize
6334 && (GET_CODE (old) == MEM
6335 || (GET_CODE (old) == REG
6336 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6337 && reg_renumber[REGNO (old)] < 0)))
6338 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6339 -1, NULL_PTR, 0, mode);
6343 int regno = true_regnum (oldequiv);
6345 /* If OLDEQUIV is a spill register, don't use it for this
6346 if any other reload needs it at an earlier stage of this insn
6347 or at this stage. */
6348 if (spill_reg_order[regno] >= 0
6349 && (! reload_reg_free_p (regno, reload_opnum[j],
6350 reload_when_needed[j])
6351 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6352 reload_when_needed[j])))
6355 /* If OLDEQUIV is not a spill register,
6356 don't use it if any other reload wants it. */
6357 if (spill_reg_order[regno] < 0)
6360 for (k = 0; k < n_reloads; k++)
6361 if (reload_reg_rtx[k] != 0 && k != j
6362 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6370 /* If it is no cheaper to copy from OLDEQUIV into the
6371 reload register than it would be to move from memory,
6372 don't use it. Likewise, if we need a secondary register
6376 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6377 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6378 reload_reg_class[j])
6379 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6380 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6381 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6385 #ifdef SECONDARY_MEMORY_NEEDED
6386 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6387 reload_reg_class[j],
6396 else if (GET_CODE (oldequiv) == REG)
6397 oldequiv_reg = oldequiv;
6398 else if (GET_CODE (oldequiv) == SUBREG)
6399 oldequiv_reg = SUBREG_REG (oldequiv);
6401 /* If we are reloading from a register that was recently stored in
6402 with an output-reload, see if we can prove there was
6403 actually no need to store the old value in it. */
6405 if (optimize && GET_CODE (oldequiv) == REG
6406 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6407 && spill_reg_store[REGNO (oldequiv)]
6408 && GET_CODE (old) == REG && dead_or_set_p (insn, old)
6409 /* This is unsafe if operand occurs more than once in current
6410 insn. Perhaps some occurrences weren't reloaded. */
6411 && count_occurrences (PATTERN (insn), old) == 1)
6412 delete_output_reload (insn, j, spill_reg_store[REGNO (oldequiv)]);
6414 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6415 then load RELOADREG from OLDEQUIV. Note that we cannot use
6416 gen_lowpart_common since it can do the wrong thing when
6417 RELOADREG has a multi-word mode. Note that RELOADREG
6418 must always be a REG here. */
6420 if (GET_MODE (reloadreg) != mode)
6421 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6422 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6423 oldequiv = SUBREG_REG (oldequiv);
6424 if (GET_MODE (oldequiv) != VOIDmode
6425 && mode != GET_MODE (oldequiv))
6426 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6428 /* Switch to the right place to emit the reload insns. */
6429 switch (reload_when_needed[j])
6432 where = &other_input_reload_insns;
6434 case RELOAD_FOR_INPUT:
6435 where = &input_reload_insns[reload_opnum[j]];
6437 case RELOAD_FOR_INPUT_ADDRESS:
6438 where = &input_address_reload_insns[reload_opnum[j]];
6440 case RELOAD_FOR_INPADDR_ADDRESS:
6441 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6443 case RELOAD_FOR_OUTPUT_ADDRESS:
6444 where = &output_address_reload_insns[reload_opnum[j]];
6446 case RELOAD_FOR_OUTADDR_ADDRESS:
6447 where = &outaddr_address_reload_insns[reload_opnum[j]];
6449 case RELOAD_FOR_OPERAND_ADDRESS:
6450 where = &operand_reload_insns;
6452 case RELOAD_FOR_OPADDR_ADDR:
6453 where = &other_operand_reload_insns;
6455 case RELOAD_FOR_OTHER_ADDRESS:
6456 where = &other_input_address_reload_insns;
6462 push_to_sequence (*where);
6465 /* Auto-increment addresses must be reloaded in a special way. */
6466 if (GET_CODE (oldequiv) == POST_INC
6467 || GET_CODE (oldequiv) == POST_DEC
6468 || GET_CODE (oldequiv) == PRE_INC
6469 || GET_CODE (oldequiv) == PRE_DEC)
6471 /* We are not going to bother supporting the case where a
6472 incremented register can't be copied directly from
6473 OLDEQUIV since this seems highly unlikely. */
6474 if (reload_secondary_in_reload[j] >= 0)
6476 /* Prevent normal processing of this reload. */
6478 /* Output a special code sequence for this case. */
6479 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6482 /* If we are reloading a pseudo-register that was set by the previous
6483 insn, see if we can get rid of that pseudo-register entirely
6484 by redirecting the previous insn into our reload register. */
6486 else if (optimize && GET_CODE (old) == REG
6487 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6488 && dead_or_set_p (insn, old)
6489 /* This is unsafe if some other reload
6490 uses the same reg first. */
6491 && reload_reg_free_before_p (REGNO (reloadreg),
6493 reload_when_needed[j]))
6495 rtx temp = PREV_INSN (insn);
6496 while (temp && GET_CODE (temp) == NOTE)
6497 temp = PREV_INSN (temp);
6499 && GET_CODE (temp) == INSN
6500 && GET_CODE (PATTERN (temp)) == SET
6501 && SET_DEST (PATTERN (temp)) == old
6502 /* Make sure we can access insn_operand_constraint. */
6503 && asm_noperands (PATTERN (temp)) < 0
6504 /* This is unsafe if prev insn rejects our reload reg. */
6505 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6507 /* This is unsafe if operand occurs more than once in current
6508 insn. Perhaps some occurrences aren't reloaded. */
6509 && count_occurrences (PATTERN (insn), old) == 1
6510 /* Don't risk splitting a matching pair of operands. */
6511 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6513 /* Store into the reload register instead of the pseudo. */
6514 SET_DEST (PATTERN (temp)) = reloadreg;
6515 /* If these are the only uses of the pseudo reg,
6516 pretend for GDB it lives in the reload reg we used. */
6517 if (REG_N_DEATHS (REGNO (old)) == 1
6518 && REG_N_SETS (REGNO (old)) == 1)
6520 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6521 alter_reg (REGNO (old), -1);
6527 /* We can't do that, so output an insn to load RELOADREG. */
6531 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6532 rtx second_reload_reg = 0;
6533 enum insn_code icode;
6535 /* If we have a secondary reload, pick up the secondary register
6536 and icode, if any. If OLDEQUIV and OLD are different or
6537 if this is an in-out reload, recompute whether or not we
6538 still need a secondary register and what the icode should
6539 be. If we still need a secondary register and the class or
6540 icode is different, go back to reloading from OLD if using
6541 OLDEQUIV means that we got the wrong type of register. We
6542 cannot have different class or icode due to an in-out reload
6543 because we don't make such reloads when both the input and
6544 output need secondary reload registers. */
6546 if (reload_secondary_in_reload[j] >= 0)
6548 int secondary_reload = reload_secondary_in_reload[j];
6549 rtx real_oldequiv = oldequiv;
6552 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6553 and similarly for OLD.
6554 See comments in get_secondary_reload in reload.c. */
6555 if (GET_CODE (oldequiv) == REG
6556 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6557 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6558 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6560 if (GET_CODE (old) == REG
6561 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6562 && reg_equiv_mem[REGNO (old)] != 0)
6563 real_old = reg_equiv_mem[REGNO (old)];
6565 second_reload_reg = reload_reg_rtx[secondary_reload];
6566 icode = reload_secondary_in_icode[j];
6568 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6569 || (reload_in[j] != 0 && reload_out[j] != 0))
6571 enum reg_class new_class
6572 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6573 mode, real_oldequiv);
6575 if (new_class == NO_REGS)
6576 second_reload_reg = 0;
6579 enum insn_code new_icode;
6580 enum machine_mode new_mode;
6582 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6583 REGNO (second_reload_reg)))
6584 oldequiv = old, real_oldequiv = real_old;
6587 new_icode = reload_in_optab[(int) mode];
6588 if (new_icode != CODE_FOR_nothing
6589 && ((insn_operand_predicate[(int) new_icode][0]
6590 && ! ((*insn_operand_predicate[(int) new_icode][0])
6592 || (insn_operand_predicate[(int) new_icode][1]
6593 && ! ((*insn_operand_predicate[(int) new_icode][1])
6594 (real_oldequiv, mode)))))
6595 new_icode = CODE_FOR_nothing;
6597 if (new_icode == CODE_FOR_nothing)
6600 new_mode = insn_operand_mode[(int) new_icode][2];
6602 if (GET_MODE (second_reload_reg) != new_mode)
6604 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6606 oldequiv = old, real_oldequiv = real_old;
6609 = gen_rtx_REG (new_mode,
6610 REGNO (second_reload_reg));
6616 /* If we still need a secondary reload register, check
6617 to see if it is being used as a scratch or intermediate
6618 register and generate code appropriately. If we need
6619 a scratch register, use REAL_OLDEQUIV since the form of
6620 the insn may depend on the actual address if it is
6623 if (second_reload_reg)
6625 if (icode != CODE_FOR_nothing)
6627 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6628 second_reload_reg));
6633 /* See if we need a scratch register to load the
6634 intermediate register (a tertiary reload). */
6635 enum insn_code tertiary_icode
6636 = reload_secondary_in_icode[secondary_reload];
6638 if (tertiary_icode != CODE_FOR_nothing)
6640 rtx third_reload_reg
6641 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6643 emit_insn ((GEN_FCN (tertiary_icode)
6644 (second_reload_reg, real_oldequiv,
6645 third_reload_reg)));
6648 gen_reload (second_reload_reg, oldequiv,
6650 reload_when_needed[j]);
6652 oldequiv = second_reload_reg;
6658 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6659 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6660 reload_when_needed[j]);
6662 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6663 /* We may have to make a REG_DEAD note for the secondary reload
6664 register in the insns we just made. Find the last insn that
6665 mentioned the register. */
6666 if (! special && second_reload_reg
6667 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6671 for (prev = get_last_insn (); prev;
6672 prev = PREV_INSN (prev))
6673 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6674 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6677 REG_NOTES (prev) = gen_rtx_EXPR_LIST (REG_DEAD,
6686 this_reload_insn = get_last_insn ();
6687 /* End this sequence. */
6688 *where = get_insns ();
6692 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6693 e.g. inheriting a SImode output reload for
6694 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6695 if (optimize && reload_inherited[j] && reload_in[j]
6696 && GET_CODE (reload_in[j]) == MEM
6697 && reload_spill_index[j] >= 0
6698 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6701 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6703 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6705 /* Add a note saying the input reload reg
6706 dies in this insn, if anyone cares. */
6707 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6709 && reload_reg_rtx[j] != old
6710 && reload_reg_rtx[j] != 0
6711 && reload_out[j] == 0
6712 && ! reload_inherited[j]
6713 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6715 register rtx reloadreg = reload_reg_rtx[j];
6718 /* We can't abort here because we need to support this for sched.c.
6719 It's not terrible to miss a REG_DEAD note, but we should try
6720 to figure out how to do this correctly. */
6721 /* The code below is incorrect for address-only reloads. */
6722 if (reload_when_needed[j] != RELOAD_OTHER
6723 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6727 /* Add a death note to this insn, for an input reload. */
6729 if ((reload_when_needed[j] == RELOAD_OTHER
6730 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6731 && ! dead_or_set_p (insn, reloadreg))
6733 = gen_rtx_EXPR_LIST (REG_DEAD,
6734 reloadreg, REG_NOTES (insn));
6737 /* When we inherit a reload, the last marked death of the reload reg
6738 may no longer really be a death. */
6739 if (reload_reg_rtx[j] != 0
6740 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6741 && reload_inherited[j])
6743 /* Handle inheriting an output reload.
6744 Remove the death note from the output reload insn. */
6745 if (reload_spill_index[j] >= 0
6746 && GET_CODE (reload_in[j]) == REG
6747 && spill_reg_store[reload_spill_index[j]] != 0
6748 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6749 REG_DEAD, REGNO (reload_reg_rtx[j])))
6750 remove_death (REGNO (reload_reg_rtx[j]),
6751 spill_reg_store[reload_spill_index[j]]);
6752 /* Likewise for input reloads that were inherited. */
6753 else if (reload_spill_index[j] >= 0
6754 && GET_CODE (reload_in[j]) == REG
6755 && spill_reg_store[reload_spill_index[j]] == 0
6756 && reload_inheritance_insn[j] != 0
6757 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6758 REGNO (reload_reg_rtx[j])))
6759 remove_death (REGNO (reload_reg_rtx[j]),
6760 reload_inheritance_insn[j]);
6765 /* We got this register from find_equiv_reg.
6766 Search back for its last death note and get rid of it.
6767 But don't search back too far.
6768 Don't go past a place where this reg is set,
6769 since a death note before that remains valid. */
6770 for (prev = PREV_INSN (insn);
6771 prev && GET_CODE (prev) != CODE_LABEL;
6772 prev = PREV_INSN (prev))
6773 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6774 && dead_or_set_p (prev, reload_reg_rtx[j]))
6776 if (find_regno_note (prev, REG_DEAD,
6777 REGNO (reload_reg_rtx[j])))
6778 remove_death (REGNO (reload_reg_rtx[j]), prev);
6784 /* We might have used find_equiv_reg above to choose an alternate
6785 place from which to reload. If so, and it died, we need to remove
6786 that death and move it to one of the insns we just made. */
6788 if (oldequiv_reg != 0
6789 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6793 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6794 prev = PREV_INSN (prev))
6795 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6796 && dead_or_set_p (prev, oldequiv_reg))
6798 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6800 for (prev1 = this_reload_insn;
6801 prev1; prev1 = PREV_INSN (prev1))
6802 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6803 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6806 REG_NOTES (prev1) = gen_rtx_EXPR_LIST (REG_DEAD,
6811 remove_death (REGNO (oldequiv_reg), prev);
6818 /* If we are reloading a register that was recently stored in with an
6819 output-reload, see if we can prove there was
6820 actually no need to store the old value in it. */
6822 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6823 && reload_in[j] != 0
6824 && GET_CODE (reload_in[j]) == REG
6826 /* There doesn't seem to be any reason to restrict this to pseudos
6827 and doing so loses in the case where we are copying from a
6828 register of the wrong class. */
6829 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6831 && spill_reg_store[reload_spill_index[j]] != 0
6832 /* This is unsafe if some other reload uses the same reg first. */
6833 && reload_reg_free_before_p (reload_spill_index[j],
6834 reload_opnum[j], reload_when_needed[j])
6835 && dead_or_set_p (insn, reload_in[j])
6836 /* This is unsafe if operand occurs more than once in current
6837 insn. Perhaps some occurrences weren't reloaded. */
6838 && (count_occurrences (PATTERN (insn), reload_in[j])
6839 == expect_occurrences))
6840 delete_output_reload (insn, j,
6841 spill_reg_store[reload_spill_index[j]]);
6843 /* Input-reloading is done. Now do output-reloading,
6844 storing the value from the reload-register after the main insn
6845 if reload_out[j] is nonzero.
6847 ??? At some point we need to support handling output reloads of
6848 JUMP_INSNs or insns that set cc0. */
6849 old = reload_out[j];
6851 && reload_reg_rtx[j] != old
6852 && reload_reg_rtx[j] != 0)
6854 register rtx reloadreg = reload_reg_rtx[j];
6855 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6856 register rtx second_reloadreg = 0;
6859 enum machine_mode mode;
6862 /* An output operand that dies right away does need a reload,
6863 but need not be copied from it. Show the new location in the
6865 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6866 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6868 XEXP (note, 0) = reload_reg_rtx[j];
6871 /* Likewise for a SUBREG of an operand that dies. */
6872 else if (GET_CODE (old) == SUBREG
6873 && GET_CODE (SUBREG_REG (old)) == REG
6874 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6877 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6881 else if (GET_CODE (old) == SCRATCH)
6882 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6883 but we don't want to make an output reload. */
6887 /* Strip off of OLD any size-increasing SUBREGs such as
6888 (SUBREG:SI foo:QI 0). */
6890 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6891 && (GET_MODE_SIZE (GET_MODE (old))
6892 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6893 old = SUBREG_REG (old);
6896 /* If is a JUMP_INSN, we can't support output reloads yet. */
6897 if (GET_CODE (insn) == JUMP_INSN)
6900 if (reload_when_needed[j] == RELOAD_OTHER)
6903 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6905 /* Determine the mode to reload in.
6906 See comments above (for input reloading). */
6908 mode = GET_MODE (old);
6909 if (mode == VOIDmode)
6911 /* VOIDmode should never happen for an output. */
6912 if (asm_noperands (PATTERN (insn)) < 0)
6913 /* It's the compiler's fault. */
6914 fatal_insn ("VOIDmode on an output", insn);
6915 error_for_asm (insn, "output operand is constant in `asm'");
6916 /* Prevent crash--use something we know is valid. */
6918 old = gen_rtx_REG (mode, REGNO (reloadreg));
6921 if (GET_MODE (reloadreg) != mode)
6922 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6924 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6926 /* If we need two reload regs, set RELOADREG to the intermediate
6927 one, since it will be stored into OLD. We might need a secondary
6928 register only for an input reload, so check again here. */
6930 if (reload_secondary_out_reload[j] >= 0)
6934 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6935 && reg_equiv_mem[REGNO (old)] != 0)
6936 real_old = reg_equiv_mem[REGNO (old)];
6938 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6942 second_reloadreg = reloadreg;
6943 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6945 /* See if RELOADREG is to be used as a scratch register
6946 or as an intermediate register. */
6947 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6949 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6950 (real_old, second_reloadreg, reloadreg)));
6955 /* See if we need both a scratch and intermediate reload
6958 int secondary_reload = reload_secondary_out_reload[j];
6959 enum insn_code tertiary_icode
6960 = reload_secondary_out_icode[secondary_reload];
6962 if (GET_MODE (reloadreg) != mode)
6963 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6965 if (tertiary_icode != CODE_FOR_nothing)
6968 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6971 /* Copy primary reload reg to secondary reload reg.
6972 (Note that these have been swapped above, then
6973 secondary reload reg to OLD using our insn. */
6975 /* If REAL_OLD is a paradoxical SUBREG, remove it
6976 and try to put the opposite SUBREG on
6978 if (GET_CODE (real_old) == SUBREG
6979 && (GET_MODE_SIZE (GET_MODE (real_old))
6980 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6981 && 0 != (tem = gen_lowpart_common
6982 (GET_MODE (SUBREG_REG (real_old)),
6984 real_old = SUBREG_REG (real_old), reloadreg = tem;
6986 gen_reload (reloadreg, second_reloadreg,
6987 reload_opnum[j], reload_when_needed[j]);
6988 emit_insn ((GEN_FCN (tertiary_icode)
6989 (real_old, reloadreg, third_reloadreg)));
6994 /* Copy between the reload regs here and then to
6997 gen_reload (reloadreg, second_reloadreg,
6998 reload_opnum[j], reload_when_needed[j]);
7004 /* Output the last reload insn. */
7009 /* Don't output the last reload if OLD is not the dest of
7010 INSN and is in the src and is clobbered by INSN. */
7011 if (! flag_expensive_optimizations
7012 || GET_CODE (old) != REG
7013 || !(set = single_set (insn))
7014 || rtx_equal_p (old, SET_DEST (set))
7015 || !reg_mentioned_p (old, SET_SRC (set))
7016 || !regno_clobbered_p (REGNO (old), insn))
7017 gen_reload (old, reloadreg, reload_opnum[j],
7018 reload_when_needed[j]);
7021 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7022 /* If final will look at death notes for this reg,
7023 put one on the last output-reload insn to use it. Similarly
7024 for any secondary register. */
7025 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
7026 for (p = get_last_insn (); p; p = PREV_INSN (p))
7027 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
7028 && reg_overlap_mentioned_for_reload_p (reloadreg,
7030 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
7031 reloadreg, REG_NOTES (p));
7033 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7034 if (! special && second_reloadreg
7035 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
7036 for (p = get_last_insn (); p; p = PREV_INSN (p))
7037 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
7038 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
7040 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
7045 /* Look at all insns we emitted, just to be safe. */
7046 for (p = get_insns (); p; p = NEXT_INSN (p))
7047 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7049 rtx pat = PATTERN (p);
7051 /* If this output reload doesn't come from a spill reg,
7052 clear any memory of reloaded copies of the pseudo reg.
7053 If this output reload comes from a spill reg,
7054 reg_has_output_reload will make this do nothing. */
7055 note_stores (pat, forget_old_reloads_1);
7057 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7059 if (reload_spill_index[j] < 0
7060 && GET_CODE (pat) == SET
7061 && SET_SRC (pat) == reload_reg_rtx[j])
7063 int src = REGNO (SET_SRC (pat));
7065 reload_spill_index[j] = src;
7066 SET_HARD_REG_BIT (reg_is_output_reload, src);
7067 if (find_regno_note (insn, REG_DEAD, src))
7068 SET_HARD_REG_BIT (reg_reloaded_died, src);
7070 if (reload_spill_index[j] >= 0)
7071 new_spill_reg_store[reload_spill_index[j]] = p;
7075 if (reload_when_needed[j] == RELOAD_OTHER)
7077 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7078 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7081 output_reload_insns[reload_opnum[j]] = get_insns ();
7087 /* Now write all the insns we made for reloads in the order expected by
7088 the allocation functions. Prior to the insn being reloaded, we write
7089 the following reloads:
7091 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7093 RELOAD_OTHER reloads.
7095 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7096 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7097 RELOAD_FOR_INPUT reload for the operand.
7099 RELOAD_FOR_OPADDR_ADDRS reloads.
7101 RELOAD_FOR_OPERAND_ADDRESS reloads.
7103 After the insn being reloaded, we write the following:
7105 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7106 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7107 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7108 reloads for the operand. The RELOAD_OTHER output reloads are
7109 output in descending order by reload number. */
7111 emit_insns_before (other_input_address_reload_insns, before_insn);
7112 emit_insns_before (other_input_reload_insns, before_insn);
7114 for (j = 0; j < reload_n_operands; j++)
7116 emit_insns_before (inpaddr_address_reload_insns[j], before_insn);
7117 emit_insns_before (input_address_reload_insns[j], before_insn);
7118 emit_insns_before (input_reload_insns[j], before_insn);
7121 emit_insns_before (other_operand_reload_insns, before_insn);
7122 emit_insns_before (operand_reload_insns, before_insn);
7124 for (j = 0; j < reload_n_operands; j++)
7126 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7127 emit_insns_before (output_address_reload_insns[j], following_insn);
7128 emit_insns_before (output_reload_insns[j], following_insn);
7129 emit_insns_before (other_output_reload_insns[j], following_insn);
7132 /* Move death notes from INSN
7133 to output-operand-address and output reload insns. */
7134 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7137 /* Loop over those insns, last ones first. */
7138 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
7139 insn1 = PREV_INSN (insn1))
7140 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
7142 rtx source = SET_SRC (PATTERN (insn1));
7143 rtx dest = SET_DEST (PATTERN (insn1));
7145 /* The note we will examine next. */
7146 rtx reg_notes = REG_NOTES (insn);
7147 /* The place that pointed to this note. */
7148 rtx *prev_reg_note = ®_NOTES (insn);
7150 /* If the note is for something used in the source of this
7151 reload insn, or in the output address, move the note. */
7154 rtx next_reg_notes = XEXP (reg_notes, 1);
7155 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
7156 && GET_CODE (XEXP (reg_notes, 0)) == REG
7157 && ((GET_CODE (dest) != REG
7158 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
7160 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
7163 *prev_reg_note = next_reg_notes;
7164 XEXP (reg_notes, 1) = REG_NOTES (insn1);
7165 REG_NOTES (insn1) = reg_notes;
7168 prev_reg_note = &XEXP (reg_notes, 1);
7170 reg_notes = next_reg_notes;
7176 /* For all the spill regs newly reloaded in this instruction,
7177 record what they were reloaded from, so subsequent instructions
7178 can inherit the reloads.
7180 Update spill_reg_store for the reloads of this insn.
7181 Copy the elements that were updated in the loop above. */
7183 for (j = 0; j < n_reloads; j++)
7185 register int r = reload_order[j];
7186 register int i = reload_spill_index[r];
7188 /* I is nonneg if this reload used a register.
7189 If reload_reg_rtx[r] is 0, this is an optional reload
7190 that we opted to ignore. */
7192 if (i >= 0 && reload_reg_rtx[r] != 0)
7195 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7197 int part_reaches_end = 0;
7198 int all_reaches_end = 1;
7200 /* For a multi register reload, we need to check if all or part
7201 of the value lives to the end. */
7202 for (k = 0; k < nr; k++)
7204 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7205 reload_when_needed[r]))
7206 part_reaches_end = 1;
7208 all_reaches_end = 0;
7211 /* Ignore reloads that don't reach the end of the insn in
7213 if (all_reaches_end)
7215 /* First, clear out memory of what used to be in this spill reg.
7216 If consecutive registers are used, clear them all. */
7218 for (k = 0; k < nr; k++)
7219 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7221 /* Maybe the spill reg contains a copy of reload_out. */
7222 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7224 register int nregno = REGNO (reload_out[r]);
7225 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7226 : HARD_REGNO_NREGS (nregno,
7227 GET_MODE (reload_reg_rtx[r])));
7229 spill_reg_store[i] = new_spill_reg_store[i];
7230 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7232 /* If NREGNO is a hard register, it may occupy more than
7233 one register. If it does, say what is in the
7234 rest of the registers assuming that both registers
7235 agree on how many words the object takes. If not,
7236 invalidate the subsequent registers. */
7238 if (nregno < FIRST_PSEUDO_REGISTER)
7239 for (k = 1; k < nnr; k++)
7240 reg_last_reload_reg[nregno + k]
7242 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7243 REGNO (reload_reg_rtx[r]) + k)
7246 /* Now do the inverse operation. */
7247 for (k = 0; k < nr; k++)
7249 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7250 reg_reloaded_contents[i + k]
7251 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7254 reg_reloaded_insn[i + k] = insn;
7255 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7259 /* Maybe the spill reg contains a copy of reload_in. Only do
7260 something if there will not be an output reload for
7261 the register being reloaded. */
7262 else if (reload_out[r] == 0
7263 && reload_in[r] != 0
7264 && spill_reg_order[i] >= 0
7265 && ((GET_CODE (reload_in[r]) == REG
7266 && ! reg_has_output_reload[REGNO (reload_in[r])])
7267 || (GET_CODE (reload_in_reg[r]) == REG
7268 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
7270 register int nregno;
7273 if (GET_CODE (reload_in[r]) == REG)
7274 nregno = REGNO (reload_in[r]);
7276 nregno = REGNO (reload_in_reg[r]);
7278 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7279 : HARD_REGNO_NREGS (nregno,
7280 GET_MODE (reload_reg_rtx[r])));
7282 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7284 if (nregno < FIRST_PSEUDO_REGISTER)
7285 for (k = 1; k < nnr; k++)
7286 reg_last_reload_reg[nregno + k]
7288 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7289 REGNO (reload_reg_rtx[r]) + k)
7292 /* Unless we inherited this reload, show we haven't
7293 recently done a store. */
7294 if (! reload_inherited[r])
7295 spill_reg_store[i] = 0;
7297 for (k = 0; k < nr; k++)
7299 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7300 reg_reloaded_contents[i + k]
7301 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7304 reg_reloaded_insn[i + k] = insn;
7305 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7310 /* However, if part of the reload reaches the end, then we must
7311 invalidate the old info for the part that survives to the end. */
7312 else if (part_reaches_end)
7314 for (k = 0; k < nr; k++)
7315 if (reload_reg_reaches_end_p (i + k,
7317 reload_when_needed[r]))
7318 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7322 /* The following if-statement was #if 0'd in 1.34 (or before...).
7323 It's reenabled in 1.35 because supposedly nothing else
7324 deals with this problem. */
7326 /* If a register gets output-reloaded from a non-spill register,
7327 that invalidates any previous reloaded copy of it.
7328 But forget_old_reloads_1 won't get to see it, because
7329 it thinks only about the original insn. So invalidate it here. */
7330 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7332 register int nregno = REGNO (reload_out[r]);
7333 if (nregno >= FIRST_PSEUDO_REGISTER)
7334 reg_last_reload_reg[nregno] = 0;
7337 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7339 while (num_regs-- > 0)
7340 reg_last_reload_reg[nregno + num_regs] = 0;
7344 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7347 /* Emit code to perform a reload from IN (which may be a reload register) to
7348 OUT (which may also be a reload register). IN or OUT is from operand
7349 OPNUM with reload type TYPE.
7351 Returns first insn emitted. */
7354 gen_reload (out, in, opnum, type)
7358 enum reload_type type;
7360 rtx last = get_last_insn ();
7363 /* If IN is a paradoxical SUBREG, remove it and try to put the
7364 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7365 if (GET_CODE (in) == SUBREG
7366 && (GET_MODE_SIZE (GET_MODE (in))
7367 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7368 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7369 in = SUBREG_REG (in), out = tem;
7370 else if (GET_CODE (out) == SUBREG
7371 && (GET_MODE_SIZE (GET_MODE (out))
7372 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7373 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7374 out = SUBREG_REG (out), in = tem;
7376 /* How to do this reload can get quite tricky. Normally, we are being
7377 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7378 register that didn't get a hard register. In that case we can just
7379 call emit_move_insn.
7381 We can also be asked to reload a PLUS that adds a register or a MEM to
7382 another register, constant or MEM. This can occur during frame pointer
7383 elimination and while reloading addresses. This case is handled by
7384 trying to emit a single insn to perform the add. If it is not valid,
7385 we use a two insn sequence.
7387 Finally, we could be called to handle an 'o' constraint by putting
7388 an address into a register. In that case, we first try to do this
7389 with a named pattern of "reload_load_address". If no such pattern
7390 exists, we just emit a SET insn and hope for the best (it will normally
7391 be valid on machines that use 'o').
7393 This entire process is made complex because reload will never
7394 process the insns we generate here and so we must ensure that
7395 they will fit their constraints and also by the fact that parts of
7396 IN might be being reloaded separately and replaced with spill registers.
7397 Because of this, we are, in some sense, just guessing the right approach
7398 here. The one listed above seems to work.
7400 ??? At some point, this whole thing needs to be rethought. */
7402 if (GET_CODE (in) == PLUS
7403 && (GET_CODE (XEXP (in, 0)) == REG
7404 || GET_CODE (XEXP (in, 0)) == SUBREG
7405 || GET_CODE (XEXP (in, 0)) == MEM)
7406 && (GET_CODE (XEXP (in, 1)) == REG
7407 || GET_CODE (XEXP (in, 1)) == SUBREG
7408 || CONSTANT_P (XEXP (in, 1))
7409 || GET_CODE (XEXP (in, 1)) == MEM))
7411 /* We need to compute the sum of a register or a MEM and another
7412 register, constant, or MEM, and put it into the reload
7413 register. The best possible way of doing this is if the machine
7414 has a three-operand ADD insn that accepts the required operands.
7416 The simplest approach is to try to generate such an insn and see if it
7417 is recognized and matches its constraints. If so, it can be used.
7419 It might be better not to actually emit the insn unless it is valid,
7420 but we need to pass the insn as an operand to `recog' and
7421 `insn_extract' and it is simpler to emit and then delete the insn if
7422 not valid than to dummy things up. */
7424 rtx op0, op1, tem, insn;
7427 op0 = find_replacement (&XEXP (in, 0));
7428 op1 = find_replacement (&XEXP (in, 1));
7430 /* Since constraint checking is strict, commutativity won't be
7431 checked, so we need to do that here to avoid spurious failure
7432 if the add instruction is two-address and the second operand
7433 of the add is the same as the reload reg, which is frequently
7434 the case. If the insn would be A = B + A, rearrange it so
7435 it will be A = A + B as constrain_operands expects. */
7437 if (GET_CODE (XEXP (in, 1)) == REG
7438 && REGNO (out) == REGNO (XEXP (in, 1)))
7439 tem = op0, op0 = op1, op1 = tem;
7441 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7442 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7444 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7445 code = recog_memoized (insn);
7449 insn_extract (insn);
7450 /* We want constrain operands to treat this insn strictly in
7451 its validity determination, i.e., the way it would after reload
7453 if (constrain_operands (code, 1))
7457 delete_insns_since (last);
7459 /* If that failed, we must use a conservative two-insn sequence.
7460 use move to copy constant, MEM, or pseudo register to the reload
7461 register since "move" will be able to handle an arbitrary operand,
7462 unlike add which can't, in general. Then add the registers.
7464 If there is another way to do this for a specific machine, a
7465 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7468 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7469 || (GET_CODE (op1) == REG
7470 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7471 tem = op0, op0 = op1, op1 = tem;
7473 gen_reload (out, op0, opnum, type);
7475 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7476 This fixes a problem on the 32K where the stack pointer cannot
7477 be used as an operand of an add insn. */
7479 if (rtx_equal_p (op0, op1))
7482 insn = emit_insn (gen_add2_insn (out, op1));
7484 /* If that failed, copy the address register to the reload register.
7485 Then add the constant to the reload register. */
7487 code = recog_memoized (insn);
7491 insn_extract (insn);
7492 /* We want constrain operands to treat this insn strictly in
7493 its validity determination, i.e., the way it would after reload
7495 if (constrain_operands (code, 1))
7497 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7499 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7504 delete_insns_since (last);
7506 gen_reload (out, op1, opnum, type);
7507 insn = emit_insn (gen_add2_insn (out, op0));
7508 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7511 #ifdef SECONDARY_MEMORY_NEEDED
7512 /* If we need a memory location to do the move, do it that way. */
7513 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7514 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7515 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7516 REGNO_REG_CLASS (REGNO (out)),
7519 /* Get the memory to use and rewrite both registers to its mode. */
7520 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7522 if (GET_MODE (loc) != GET_MODE (out))
7523 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7525 if (GET_MODE (loc) != GET_MODE (in))
7526 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7528 gen_reload (loc, in, opnum, type);
7529 gen_reload (out, loc, opnum, type);
7533 /* If IN is a simple operand, use gen_move_insn. */
7534 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7535 emit_insn (gen_move_insn (out, in));
7537 #ifdef HAVE_reload_load_address
7538 else if (HAVE_reload_load_address)
7539 emit_insn (gen_reload_load_address (out, in));
7542 /* Otherwise, just write (set OUT IN) and hope for the best. */
7544 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7546 /* Return the first insn emitted.
7547 We can not just return get_last_insn, because there may have
7548 been multiple instructions emitted. Also note that gen_move_insn may
7549 emit more than one insn itself, so we can not assume that there is one
7550 insn emitted per emit_insn_before call. */
7552 return last ? NEXT_INSN (last) : get_insns ();
7555 /* Delete a previously made output-reload
7556 whose result we now believe is not needed.
7557 First we double-check.
7559 INSN is the insn now being processed.
7560 OUTPUT_RELOAD_INSN is the insn of the output reload.
7561 J is the reload-number for this insn. */
7564 delete_output_reload (insn, j, output_reload_insn)
7567 rtx output_reload_insn;
7571 /* Get the raw pseudo-register referred to. */
7573 rtx reg = reload_in[j];
7574 while (GET_CODE (reg) == SUBREG)
7575 reg = SUBREG_REG (reg);
7577 /* If the pseudo-reg we are reloading is no longer referenced
7578 anywhere between the store into it and here,
7579 and no jumps or labels intervene, then the value can get
7580 here through the reload reg alone.
7581 Otherwise, give up--return. */
7582 for (i1 = NEXT_INSN (output_reload_insn);
7583 i1 != insn; i1 = NEXT_INSN (i1))
7585 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7587 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7588 && reg_mentioned_p (reg, PATTERN (i1)))
7590 /* If this is just a single USE with an REG_EQUAL note in front
7591 of INSN, this is no problem, because this mentions just the
7592 address that we are using here.
7593 But if there is more than one such USE, the insn might use
7594 the operand directly, or another reload might do that.
7595 This is analogous to the count_occurences check in the callers. */
7596 int num_occurences = 0;
7598 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE
7599 && find_reg_note (i1, REG_EQUAL, NULL_RTX))
7601 num_occurences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7602 i1 = NEXT_INSN (i1);
7604 if (num_occurences == 1 && i1 == insn)
7610 /* The caller has already checked that REG dies or is set in INSN.
7611 It has also checked that we are optimizing, and thus some inaccurancies
7612 in the debugging information are acceptable.
7613 So we could just delete output_reload_insn.
7614 But in some cases we can improve the debugging information without
7615 sacrificing optimization - maybe even improving the code:
7616 See if the pseudo reg has been completely replaced
7617 with reload regs. If so, delete the store insn
7618 and forget we had a stack slot for the pseudo. */
7619 if (reload_out[j] != reload_in[j]
7620 && REG_N_DEATHS (REGNO (reg)) == 1
7621 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7622 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7626 /* We know that it was used only between here
7627 and the beginning of the current basic block.
7628 (We also know that the last use before INSN was
7629 the output reload we are thinking of deleting, but never mind that.)
7630 Search that range; see if any ref remains. */
7631 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7633 rtx set = single_set (i2);
7635 /* Uses which just store in the pseudo don't count,
7636 since if they are the only uses, they are dead. */
7637 if (set != 0 && SET_DEST (set) == reg)
7639 if (GET_CODE (i2) == CODE_LABEL
7640 || GET_CODE (i2) == JUMP_INSN)
7642 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7643 && reg_mentioned_p (reg, PATTERN (i2)))
7645 /* Some other ref remains; just delete the output reload we
7647 delete_insn (output_reload_insn);
7652 /* Delete the now-dead stores into this pseudo. */
7653 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7655 rtx set = single_set (i2);
7657 if (set != 0 && SET_DEST (set) == reg)
7659 /* This might be a basic block head,
7660 thus don't use delete_insn. */
7661 PUT_CODE (i2, NOTE);
7662 NOTE_SOURCE_FILE (i2) = 0;
7663 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7665 if (GET_CODE (i2) == CODE_LABEL
7666 || GET_CODE (i2) == JUMP_INSN)
7670 /* For the debugging info,
7671 say the pseudo lives in this reload reg. */
7672 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7673 alter_reg (REGNO (reg), -1);
7675 delete_insn (output_reload_insn);
7679 /* Output reload-insns to reload VALUE into RELOADREG.
7680 VALUE is an autoincrement or autodecrement RTX whose operand
7681 is a register or memory location;
7682 so reloading involves incrementing that location.
7684 INC_AMOUNT is the number to increment or decrement by (always positive).
7685 This cannot be deduced from VALUE. */
7688 inc_for_reload (reloadreg, value, inc_amount)
7693 /* REG or MEM to be copied and incremented. */
7694 rtx incloc = XEXP (value, 0);
7695 /* Nonzero if increment after copying. */
7696 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7702 /* No hard register is equivalent to this register after
7703 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7704 we could inc/dec that register as well (maybe even using it for
7705 the source), but I'm not sure it's worth worrying about. */
7706 if (GET_CODE (incloc) == REG)
7707 reg_last_reload_reg[REGNO (incloc)] = 0;
7709 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7710 inc_amount = - inc_amount;
7712 inc = GEN_INT (inc_amount);
7714 /* If this is post-increment, first copy the location to the reload reg. */
7716 emit_insn (gen_move_insn (reloadreg, incloc));
7718 /* See if we can directly increment INCLOC. Use a method similar to that
7721 last = get_last_insn ();
7722 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7723 gen_rtx_PLUS (GET_MODE (incloc),
7726 code = recog_memoized (add_insn);
7729 insn_extract (add_insn);
7730 if (constrain_operands (code, 1))
7732 /* If this is a pre-increment and we have incremented the value
7733 where it lives, copy the incremented value to RELOADREG to
7734 be used as an address. */
7737 emit_insn (gen_move_insn (reloadreg, incloc));
7743 delete_insns_since (last);
7745 /* If couldn't do the increment directly, must increment in RELOADREG.
7746 The way we do this depends on whether this is pre- or post-increment.
7747 For pre-increment, copy INCLOC to the reload register, increment it
7748 there, then save back. */
7752 emit_insn (gen_move_insn (reloadreg, incloc));
7753 emit_insn (gen_add2_insn (reloadreg, inc));
7754 emit_insn (gen_move_insn (incloc, reloadreg));
7759 Because this might be a jump insn or a compare, and because RELOADREG
7760 may not be available after the insn in an input reload, we must do
7761 the incrementation before the insn being reloaded for.
7763 We have already copied INCLOC to RELOADREG. Increment the copy in
7764 RELOADREG, save that back, then decrement RELOADREG so it has
7765 the original value. */
7767 emit_insn (gen_add2_insn (reloadreg, inc));
7768 emit_insn (gen_move_insn (incloc, reloadreg));
7769 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7775 /* Return 1 if we are certain that the constraint-string STRING allows
7776 the hard register REG. Return 0 if we can't be sure of this. */
7779 constraint_accepts_reg_p (string, reg)
7784 int regno = true_regnum (reg);
7787 /* Initialize for first alternative. */
7789 /* Check that each alternative contains `g' or `r'. */
7791 switch (c = *string++)
7794 /* If an alternative lacks `g' or `r', we lose. */
7797 /* If an alternative lacks `g' or `r', we lose. */
7800 /* Initialize for next alternative. */
7805 /* Any general reg wins for this alternative. */
7806 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7810 /* Any reg in specified class wins for this alternative. */
7812 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7814 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7820 /* Return the number of places FIND appears within X, but don't count
7821 an occurrence if some SET_DEST is FIND. */
7824 count_occurrences (x, find)
7825 register rtx x, find;
7828 register enum rtx_code code;
7829 register char *format_ptr;
7837 code = GET_CODE (x);
7852 if (SET_DEST (x) == find)
7853 return count_occurrences (SET_SRC (x), find);
7860 format_ptr = GET_RTX_FORMAT (code);
7863 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7865 switch (*format_ptr++)
7868 count += count_occurrences (XEXP (x, i), find);
7872 if (XVEC (x, i) != NULL)
7874 for (j = 0; j < XVECLEN (x, i); j++)
7875 count += count_occurrences (XVECEXP (x, i, j), find);
7883 /* This array holds values which are equivalent to a hard register
7884 during reload_cse_regs. Each array element is an EXPR_LIST of
7885 values. Each time a hard register is set, we set the corresponding
7886 array element to the value. Each time a hard register is copied
7887 into memory, we add the memory location to the corresponding array
7888 element. We don't store values or memory addresses with side
7889 effects in this array.
7891 If the value is a CONST_INT, then the mode of the containing
7892 EXPR_LIST is the mode in which that CONST_INT was referenced.
7894 We sometimes clobber a specific entry in a list. In that case, we
7895 just set XEXP (list-entry, 0) to 0. */
7897 static rtx *reg_values;
7899 /* This is a preallocated REG rtx which we use as a temporary in
7900 reload_cse_invalidate_regno, so that we don't need to allocate a
7901 new one each time through a loop in that function. */
7903 static rtx invalidate_regno_rtx;
7905 /* This is a set of registers for which we must remove REG_DEAD notes in
7906 previous insns, because our modifications made them invalid. That can
7907 happen if we introduced the register into the current insn, or we deleted
7908 the current insn which used to set the register. */
7910 static HARD_REG_SET no_longer_dead_regs;
7912 /* Invalidate any entries in reg_values which depend on REGNO,
7913 including those for REGNO itself. This is called if REGNO is
7914 changing. If CLOBBER is true, then always forget anything we
7915 currently know about REGNO. MODE is the mode of the assignment to
7916 REGNO, which is used to determine how many hard registers are being
7917 changed. If MODE is VOIDmode, then only REGNO is being changed;
7918 this is used when invalidating call clobbered registers across a
7922 reload_cse_invalidate_regno (regno, mode, clobber)
7924 enum machine_mode mode;
7930 /* Our callers don't always go through true_regnum; we may see a
7931 pseudo-register here from a CLOBBER or the like. We probably
7932 won't ever see a pseudo-register that has a real register number,
7933 for we check anyhow for safety. */
7934 if (regno >= FIRST_PSEUDO_REGISTER)
7935 regno = reg_renumber[regno];
7939 if (mode == VOIDmode)
7940 endregno = regno + 1;
7942 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7945 for (i = regno; i < endregno; i++)
7948 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7952 for (x = reg_values[i]; x; x = XEXP (x, 1))
7954 if (XEXP (x, 0) != 0
7955 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7957 /* If this is the only entry on the list, clear
7958 reg_values[i]. Otherwise, just clear this entry on
7960 if (XEXP (x, 1) == 0 && x == reg_values[i])
7970 /* We must look at earlier registers, in case REGNO is part of a
7971 multi word value but is not the first register. If an earlier
7972 register has a value in a mode which overlaps REGNO, then we must
7973 invalidate that earlier register. Note that we do not need to
7974 check REGNO or later registers (we must not check REGNO itself,
7975 because we would incorrectly conclude that there was a conflict). */
7977 for (i = 0; i < regno; i++)
7981 for (x = reg_values[i]; x; x = XEXP (x, 1))
7983 if (XEXP (x, 0) != 0)
7985 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
7986 REGNO (invalidate_regno_rtx) = i;
7987 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7990 reload_cse_invalidate_regno (i, VOIDmode, 1);
7998 /* The memory at address MEM_BASE is being changed.
7999 Return whether this change will invalidate VAL. */
8002 reload_cse_mem_conflict_p (mem_base, val)
8010 code = GET_CODE (val);
8013 /* Get rid of a few simple cases quickly. */
8026 if (GET_MODE (mem_base) == BLKmode
8027 || GET_MODE (val) == BLKmode)
8029 if (anti_dependence (val, mem_base))
8031 /* The address may contain nested MEMs. */
8038 fmt = GET_RTX_FORMAT (code);
8040 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8044 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8047 else if (fmt[i] == 'E')
8051 for (j = 0; j < XVECLEN (val, i); j++)
8052 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8060 /* Invalidate any entries in reg_values which are changed because of a
8061 store to MEM_RTX. If this is called because of a non-const call
8062 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8065 reload_cse_invalidate_mem (mem_rtx)
8070 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8074 for (x = reg_values[i]; x; x = XEXP (x, 1))
8076 if (XEXP (x, 0) != 0
8077 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8079 /* If this is the only entry on the list, clear
8080 reg_values[i]. Otherwise, just clear this entry on
8082 if (XEXP (x, 1) == 0 && x == reg_values[i])
8093 /* Invalidate DEST, which is being assigned to or clobbered. The
8094 second parameter exists so that this function can be passed to
8095 note_stores; it is ignored. */
8098 reload_cse_invalidate_rtx (dest, ignore)
8100 rtx ignore ATTRIBUTE_UNUSED;
8102 while (GET_CODE (dest) == STRICT_LOW_PART
8103 || GET_CODE (dest) == SIGN_EXTRACT
8104 || GET_CODE (dest) == ZERO_EXTRACT
8105 || GET_CODE (dest) == SUBREG)
8106 dest = XEXP (dest, 0);
8108 if (GET_CODE (dest) == REG)
8109 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8110 else if (GET_CODE (dest) == MEM)
8111 reload_cse_invalidate_mem (dest);
8114 /* Possibly delete death notes on the insns before INSN if modifying INSN
8115 extended the lifespan of the registers. */
8118 reload_cse_delete_death_notes (insn)
8123 for (dreg = 0; dreg < FIRST_PSEUDO_REGISTER; dreg++)
8127 if (! TEST_HARD_REG_BIT (no_longer_dead_regs, dreg))
8130 for (trial = prev_nonnote_insn (insn);
8132 && GET_CODE (trial) != CODE_LABEL
8133 && GET_CODE (trial) != BARRIER);
8134 trial = prev_nonnote_insn (trial))
8136 if (find_regno_note (trial, REG_DEAD, dreg))
8138 remove_death (dreg, trial);
8145 /* Record that the current insn uses hard reg REGNO in mode MODE. This
8146 will be used in reload_cse_delete_death_notes to delete prior REG_DEAD
8147 notes for this register. */
8150 reload_cse_no_longer_dead (regno, mode)
8152 enum machine_mode mode;
8154 int nregs = HARD_REGNO_NREGS (regno, mode);
8157 SET_HARD_REG_BIT (no_longer_dead_regs, regno);
8163 /* Do a very simple CSE pass over the hard registers.
8165 This function detects no-op moves where we happened to assign two
8166 different pseudo-registers to the same hard register, and then
8167 copied one to the other. Reload will generate a useless
8168 instruction copying a register to itself.
8170 This function also detects cases where we load a value from memory
8171 into two different registers, and (if memory is more expensive than
8172 registers) changes it to simply copy the first register into the
8175 Another optimization is performed that scans the operands of each
8176 instruction to see whether the value is already available in a
8177 hard register. It then replaces the operand with the hard register
8178 if possible, much like an optional reload would. */
8181 reload_cse_regs (first)
8189 init_alias_analysis ();
8191 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8192 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8194 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8195 free them when we are done. */
8196 push_obstacks (&reload_obstack, &reload_obstack);
8197 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8199 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8200 memory for a non-const call instruction. */
8201 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8203 /* This is used in reload_cse_invalidate_regno to avoid consing a
8204 new REG in a loop in that function. */
8205 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8207 for (insn = first; insn; insn = NEXT_INSN (insn))
8211 if (GET_CODE (insn) == CODE_LABEL)
8213 /* Forget all the register values at a code label. We don't
8214 try to do anything clever around jumps. */
8215 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8221 #ifdef NON_SAVING_SETJMP
8222 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8223 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8225 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8232 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8235 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8237 /* If this is a call instruction, forget anything stored in a
8238 call clobbered register, or, if this is not a const call, in
8240 if (GET_CODE (insn) == CALL_INSN)
8242 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8243 if (call_used_regs[i])
8244 reload_cse_invalidate_regno (i, VOIDmode, 1);
8246 if (! CONST_CALL_P (insn))
8247 reload_cse_invalidate_mem (callmem);
8250 body = PATTERN (insn);
8251 if (GET_CODE (body) == SET)
8254 if (reload_cse_noop_set_p (body, insn))
8256 PUT_CODE (insn, NOTE);
8257 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8258 NOTE_SOURCE_FILE (insn) = 0;
8259 reload_cse_delete_death_notes (insn);
8261 /* We're done with this insn. */
8265 /* It's not a no-op, but we can try to simplify it. */
8266 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8267 count += reload_cse_simplify_set (body, insn);
8269 if (count > 0 && apply_change_group ())
8270 reload_cse_delete_death_notes (insn);
8271 else if (reload_cse_simplify_operands (insn))
8272 reload_cse_delete_death_notes (insn);
8274 reload_cse_record_set (body, body);
8276 else if (GET_CODE (body) == PARALLEL)
8280 /* If every action in a PARALLEL is a noop, we can delete
8281 the entire PARALLEL. */
8282 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8283 if ((GET_CODE (XVECEXP (body, 0, i)) != SET
8284 || ! reload_cse_noop_set_p (XVECEXP (body, 0, i), insn))
8285 && GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
8289 PUT_CODE (insn, NOTE);
8290 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8291 NOTE_SOURCE_FILE (insn) = 0;
8292 reload_cse_delete_death_notes (insn);
8294 /* We're done with this insn. */
8298 /* It's not a no-op, but we can try to simplify it. */
8299 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8300 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8301 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8302 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8304 if (count > 0 && apply_change_group ())
8305 reload_cse_delete_death_notes (insn);
8306 else if (reload_cse_simplify_operands (insn))
8307 reload_cse_delete_death_notes (insn);
8309 /* Look through the PARALLEL and record the values being
8310 set, if possible. Also handle any CLOBBERs. */
8311 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8313 rtx x = XVECEXP (body, 0, i);
8315 if (GET_CODE (x) == SET)
8316 reload_cse_record_set (x, body);
8318 note_stores (x, reload_cse_invalidate_rtx);
8322 note_stores (body, reload_cse_invalidate_rtx);
8325 /* Clobber any registers which appear in REG_INC notes. We
8326 could keep track of the changes to their values, but it is
8327 unlikely to help. */
8331 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8332 if (REG_NOTE_KIND (x) == REG_INC)
8333 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8337 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8338 after we have processed the insn. */
8339 if (GET_CODE (insn) == CALL_INSN)
8343 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8344 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8345 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8349 /* Free all the temporary structures we created, and go back to the
8350 regular obstacks. */
8351 obstack_free (&reload_obstack, firstobj);
8355 /* Return whether the values known for REGNO are equal to VAL. MODE
8356 is the mode of the object that VAL is being copied to; this matters
8357 if VAL is a CONST_INT. */
8360 reload_cse_regno_equal_p (regno, val, mode)
8363 enum machine_mode mode;
8370 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8371 if (XEXP (x, 0) != 0
8372 && rtx_equal_p (XEXP (x, 0), val)
8373 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8374 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8375 && (GET_CODE (val) != CONST_INT
8376 || mode == GET_MODE (x)
8377 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8378 /* On a big endian machine if the value spans more than
8379 one register then this register holds the high part of
8380 it and we can't use it.
8382 ??? We should also compare with the high part of the
8384 && !(WORDS_BIG_ENDIAN
8385 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8386 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8387 GET_MODE_BITSIZE (GET_MODE (x))))))
8393 /* See whether a single set is a noop. SET is the set instruction we
8394 are should check, and INSN is the instruction from which it came. */
8397 reload_cse_noop_set_p (set, insn)
8402 enum machine_mode dest_mode;
8406 src = SET_SRC (set);
8407 dest = SET_DEST (set);
8408 dest_mode = GET_MODE (dest);
8410 if (side_effects_p (src))
8413 dreg = true_regnum (dest);
8414 sreg = true_regnum (src);
8416 /* Check for setting a register to itself. In this case, we don't
8417 have to worry about REG_DEAD notes. */
8418 if (dreg >= 0 && dreg == sreg)
8424 /* Check for setting a register to itself. */
8428 /* Check for setting a register to a value which we already know
8429 is in the register. */
8430 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8433 /* Check for setting a register DREG to another register SREG
8434 where SREG is equal to a value which is already in DREG. */
8439 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8443 if (XEXP (x, 0) == 0)
8446 if (dest_mode == GET_MODE (x))
8448 else if (GET_MODE_BITSIZE (dest_mode)
8449 < GET_MODE_BITSIZE (GET_MODE (x)))
8450 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8455 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8463 else if (GET_CODE (dest) == MEM)
8465 /* Check for storing a register to memory when we know that the
8466 register is equivalent to the memory location. */
8468 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8469 && ! side_effects_p (dest))
8473 /* If we can delete this SET, then we need to look for an earlier
8474 REG_DEAD note on DREG, and remove it if it exists. */
8475 if (ret && dreg >= 0)
8477 if (! find_regno_note (insn, REG_UNUSED, dreg))
8478 reload_cse_no_longer_dead (dreg, dest_mode);
8484 /* Try to simplify a single SET instruction. SET is the set pattern.
8485 INSN is the instruction it came from.
8486 This function only handles one case: if we set a register to a value
8487 which is not a register, we try to find that value in some other register
8488 and change the set into a register copy. */
8491 reload_cse_simplify_set (set, insn)
8497 enum machine_mode dest_mode;
8498 enum reg_class dclass;
8501 dreg = true_regnum (SET_DEST (set));
8505 src = SET_SRC (set);
8506 if (side_effects_p (src) || true_regnum (src) >= 0)
8509 dclass = REGNO_REG_CLASS (dreg);
8511 /* If memory loads are cheaper than register copies, don't change them. */
8512 if (GET_CODE (src) == MEM
8513 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8516 /* If the constant is cheaper than a register, don't change it. */
8517 if (CONSTANT_P (src)
8518 && rtx_cost (src, SET) < 2)
8521 dest_mode = GET_MODE (SET_DEST (set));
8522 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8525 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8526 && reload_cse_regno_equal_p (i, src, dest_mode))
8530 /* Pop back to the real obstacks while changing the insn. */
8533 validated = validate_change (insn, &SET_SRC (set),
8534 gen_rtx_REG (dest_mode, i), 1);
8536 /* Go back to the obstack we are using for temporary
8538 push_obstacks (&reload_obstack, &reload_obstack);
8540 if (validated && ! find_regno_note (insn, REG_UNUSED, i))
8542 reload_cse_no_longer_dead (i, dest_mode);
8550 /* Try to replace operands in INSN with equivalent values that are already
8551 in registers. This can be viewed as optional reloading.
8553 For each non-register operand in the insn, see if any hard regs are
8554 known to be equivalent to that operand. Record the alternatives which
8555 can accept these hard registers. Among all alternatives, select the
8556 ones which are better or equal to the one currently matching, where
8557 "better" is in terms of '?' and '!' constraints. Among the remaining
8558 alternatives, select the one which replaces most operands with
8562 reload_cse_simplify_operands (insn)
8565 #ifdef REGISTER_CONSTRAINTS
8566 int insn_code_number, n_operands, n_alternatives;
8569 char *constraints[MAX_RECOG_OPERANDS];
8571 /* Vector recording how bad an alternative is. */
8572 int *alternative_reject;
8573 /* Vector recording how many registers can be introduced by choosing
8574 this alternative. */
8575 int *alternative_nregs;
8576 /* Array of vectors recording, for each operand and each alternative,
8577 which hard register to substitute, or -1 if the operand should be
8579 int *op_alt_regno[MAX_RECOG_OPERANDS];
8580 /* Array of alternatives, sorted in order of decreasing desirability. */
8581 int *alternative_order;
8582 rtx reg = gen_rtx_REG (VOIDmode, -1);
8584 /* Find out some information about this insn. */
8585 insn_code_number = recog_memoized (insn);
8586 /* We don't modify asm instructions. */
8587 if (insn_code_number < 0)
8590 n_operands = insn_n_operands[insn_code_number];
8591 n_alternatives = insn_n_alternatives[insn_code_number];
8593 if (n_alternatives == 0 || n_operands == 0)
8595 insn_extract (insn);
8597 /* Figure out which alternative currently matches. */
8598 if (! constrain_operands (insn_code_number, 1))
8599 fatal_insn_not_found (insn);
8601 alternative_reject = (int *) alloca (n_alternatives * sizeof (int));
8602 alternative_nregs = (int *) alloca (n_alternatives * sizeof (int));
8603 alternative_order = (int *) alloca (n_alternatives * sizeof (int));
8604 bzero ((char *)alternative_reject, n_alternatives * sizeof (int));
8605 bzero ((char *)alternative_nregs, n_alternatives * sizeof (int));
8607 for (i = 0; i < n_operands; i++)
8609 enum machine_mode mode;
8613 op_alt_regno[i] = (int *) alloca (n_alternatives * sizeof (int));
8614 for (j = 0; j < n_alternatives; j++)
8615 op_alt_regno[i][j] = -1;
8617 p = constraints[i] = insn_operand_constraint[insn_code_number][i];
8618 mode = insn_operand_mode[insn_code_number][i];
8620 /* Add the reject values for each alternative given by the constraints
8621 for this operand. */
8629 alternative_reject[j] += 3;
8631 alternative_reject[j] += 300;
8634 /* We won't change operands which are already registers. We
8635 also don't want to modify output operands. */
8636 regno = true_regnum (recog_operand[i]);
8638 || constraints[i][0] == '='
8639 || constraints[i][0] == '+')
8642 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8644 int class = (int) NO_REGS;
8646 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
8649 REGNO (reg) = regno;
8650 PUT_MODE (reg, mode);
8652 /* We found a register equal to this operand. Now look for all
8653 alternatives that can accept this register and have not been
8654 assigned a register they can use yet. */
8663 case '=': case '+': case '?':
8664 case '#': case '&': case '!':
8666 case '0': case '1': case '2': case '3': case '4':
8667 case 'm': case '<': case '>': case 'V': case 'o':
8668 case 'E': case 'F': case 'G': case 'H':
8669 case 's': case 'i': case 'n':
8670 case 'I': case 'J': case 'K': case 'L':
8671 case 'M': case 'N': case 'O': case 'P':
8672 #ifdef EXTRA_CONSTRAINT
8673 case 'Q': case 'R': case 'S': case 'T': case 'U':
8676 /* These don't say anything we care about. */
8680 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8685 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
8688 case ',': case '\0':
8689 /* See if REGNO fits this alternative, and set it up as the
8690 replacement register if we don't have one for this
8691 alternative yet and the operand being replaced is not
8692 a cheap CONST_INT. */
8693 if (op_alt_regno[i][j] == -1
8694 && reg_fits_class_p (reg, class, 0, mode)
8695 && (GET_CODE (recog_operand[i]) != CONST_INT
8696 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
8698 alternative_nregs[j]++;
8699 op_alt_regno[i][j] = regno;
8711 /* Record all alternatives which are better or equal to the currently
8712 matching one in the alternative_order array. */
8713 for (i = j = 0; i < n_alternatives; i++)
8714 if (alternative_reject[i] <= alternative_reject[which_alternative])
8715 alternative_order[j++] = i;
8718 /* Sort it. Given a small number of alternatives, a dumb algorithm
8719 won't hurt too much. */
8720 for (i = 0; i < n_alternatives - 1; i++)
8723 int best_reject = alternative_reject[alternative_order[i]];
8724 int best_nregs = alternative_nregs[alternative_order[i]];
8727 for (j = i + 1; j < n_alternatives; j++)
8729 int this_reject = alternative_reject[alternative_order[j]];
8730 int this_nregs = alternative_nregs[alternative_order[j]];
8732 if (this_reject < best_reject
8733 || (this_reject == best_reject && this_nregs < best_nregs))
8736 best_reject = this_reject;
8737 best_nregs = this_nregs;
8741 tmp = alternative_order[best];
8742 alternative_order[best] = alternative_order[i];
8743 alternative_order[i] = tmp;
8746 /* Substitute the operands as determined by op_alt_regno for the best
8748 j = alternative_order[0];
8749 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8751 /* Pop back to the real obstacks while changing the insn. */
8754 for (i = 0; i < n_operands; i++)
8756 enum machine_mode mode = insn_operand_mode[insn_code_number][i];
8757 if (op_alt_regno[i][j] == -1)
8760 reload_cse_no_longer_dead (op_alt_regno[i][j], mode);
8761 validate_change (insn, recog_operand_loc[i],
8762 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8765 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
8767 int op = recog_dup_num[i];
8768 enum machine_mode mode = insn_operand_mode[insn_code_number][op];
8770 if (op_alt_regno[op][j] == -1)
8773 reload_cse_no_longer_dead (op_alt_regno[op][j], mode);
8774 validate_change (insn, recog_dup_loc[i],
8775 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8778 /* Go back to the obstack we are using for temporary
8780 push_obstacks (&reload_obstack, &reload_obstack);
8782 return apply_change_group ();
8788 /* These two variables are used to pass information from
8789 reload_cse_record_set to reload_cse_check_clobber. */
8791 static int reload_cse_check_clobbered;
8792 static rtx reload_cse_check_src;
8794 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8795 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8796 second argument, which is passed by note_stores, is ignored. */
8799 reload_cse_check_clobber (dest, ignore)
8801 rtx ignore ATTRIBUTE_UNUSED;
8803 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8804 reload_cse_check_clobbered = 1;
8807 /* Record the result of a SET instruction. SET is the set pattern.
8808 BODY is the pattern of the insn that it came from. */
8811 reload_cse_record_set (set, body)
8817 enum machine_mode dest_mode;
8819 dest = SET_DEST (set);
8820 src = SET_SRC (set);
8821 dreg = true_regnum (dest);
8822 sreg = true_regnum (src);
8823 dest_mode = GET_MODE (dest);
8825 /* Some machines don't define AUTO_INC_DEC, but they still use push
8826 instructions. We need to catch that case here in order to
8827 invalidate the stack pointer correctly. Note that invalidating
8828 the stack pointer is different from invalidating DEST. */
8830 while (GET_CODE (x) == SUBREG
8831 || GET_CODE (x) == ZERO_EXTRACT
8832 || GET_CODE (x) == SIGN_EXTRACT
8833 || GET_CODE (x) == STRICT_LOW_PART)
8835 if (push_operand (x, GET_MODE (x)))
8837 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
8838 reload_cse_invalidate_rtx (dest, NULL_RTX);
8842 /* We can only handle an assignment to a register, or a store of a
8843 register to a memory location. For other cases, we just clobber
8844 the destination. We also have to just clobber if there are side
8845 effects in SRC or DEST. */
8846 if ((dreg < 0 && GET_CODE (dest) != MEM)
8847 || side_effects_p (src)
8848 || side_effects_p (dest))
8850 reload_cse_invalidate_rtx (dest, NULL_RTX);
8855 /* We don't try to handle values involving CC, because it's a pain
8856 to keep track of when they have to be invalidated. */
8857 if (reg_mentioned_p (cc0_rtx, src)
8858 || reg_mentioned_p (cc0_rtx, dest))
8860 reload_cse_invalidate_rtx (dest, NULL_RTX);
8865 /* If BODY is a PARALLEL, then we need to see whether the source of
8866 SET is clobbered by some other instruction in the PARALLEL. */
8867 if (GET_CODE (body) == PARALLEL)
8871 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8875 x = XVECEXP (body, 0, i);
8879 reload_cse_check_clobbered = 0;
8880 reload_cse_check_src = src;
8881 note_stores (x, reload_cse_check_clobber);
8882 if (reload_cse_check_clobbered)
8884 reload_cse_invalidate_rtx (dest, NULL_RTX);
8894 /* This is an assignment to a register. Update the value we
8895 have stored for the register. */
8900 /* This is a copy from one register to another. Any values
8901 which were valid for SREG are now valid for DREG. If the
8902 mode changes, we use gen_lowpart_common to extract only
8903 the part of the value that is copied. */
8904 reg_values[dreg] = 0;
8905 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8909 if (XEXP (x, 0) == 0)
8911 if (dest_mode == GET_MODE (XEXP (x, 0)))
8913 else if (GET_MODE_BITSIZE (dest_mode)
8914 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8917 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8919 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
8924 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
8926 /* We've changed DREG, so invalidate any values held by other
8927 registers that depend upon it. */
8928 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8930 /* If this assignment changes more than one hard register,
8931 forget anything we know about the others. */
8932 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8933 reg_values[dreg + i] = 0;
8935 else if (GET_CODE (dest) == MEM)
8937 /* Invalidate conflicting memory locations. */
8938 reload_cse_invalidate_mem (dest);
8940 /* If we're storing a register to memory, add DEST to the list
8942 if (sreg >= 0 && ! side_effects_p (dest))
8943 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
8948 /* We should have bailed out earlier. */
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