1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Replace all pseudos found in LOC with their corresponding
568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
581 unsigned int regno = REGNO (x);
583 if (regno < FIRST_PSEUDO_REGISTER)
586 x = eliminate_regs (x, mem_mode, usage);
590 replace_pseudos_in (loc, mem_mode, usage);
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (rtx first, int global)
654 struct elim_table *ep;
657 /* Make sure even insns with volatile mem refs are recognizable. */
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
680 /* Initialize the save area information for caller-save, in case some
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
691 /* A function that receives a nonlocal goto must save all call-saved
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
728 rtx set = single_set (insn);
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
738 scan_paradoxical_subregs (PATTERN (insn));
740 if (set != 0 && REG_P (SET_DEST (set)))
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
748 i = REGNO (SET_DEST (set));
751 if (i <= LAST_VIRTUAL_REGISTER)
754 if (! function_invariant_p (x)
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
760 && LEGITIMATE_PIC_OPERAND_P (x)))
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
772 reg_equiv_memory_loc[i] = copy_rtx (x);
774 else if (function_invariant_p (x))
776 if (GET_CODE (x) == PLUS)
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
800 reg_equiv_init[i] = NULL_RTX;
805 reg_equiv_init[i] = NULL_RTX;
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
891 HOST_WIDE_INT starting_frame_size;
893 starting_frame_size = get_frame_size ();
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
925 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
927 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
929 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
930 else if (CONSTANT_P (XEXP (x, 0))
931 || (REG_P (XEXP (x, 0))
932 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
933 || (GET_CODE (XEXP (x, 0)) == PLUS
934 && REG_P (XEXP (XEXP (x, 0), 0))
935 && (REGNO (XEXP (XEXP (x, 0), 0))
936 < FIRST_PSEUDO_REGISTER)
937 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
938 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
941 /* Make a new stack slot. Then indicate that something
942 changed so we go back and recompute offsets for
943 eliminable registers because the allocation of memory
944 below might change some offset. reg_equiv_{mem,address}
945 will be set up for this pseudo on the next pass around
947 reg_equiv_memory_loc[i] = 0;
948 reg_equiv_init[i] = 0;
953 if (caller_save_needed)
956 /* If we allocated another stack slot, redo elimination bookkeeping. */
957 if (starting_frame_size != get_frame_size ())
959 if (starting_frame_size && cfun->stack_alignment_needed)
961 /* If we have a stack frame, we must align it now. The
962 stack size may be a part of the offset computation for
963 register elimination. So if this changes the stack size,
964 then repeat the elimination bookkeeping. We don't
965 realign when there is no stack, as that will cause a
966 stack frame when none is needed should
967 STARTING_FRAME_OFFSET not be already aligned to
969 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
970 if (starting_frame_size != get_frame_size ())
974 if (caller_save_needed)
976 save_call_clobbered_regs ();
977 /* That might have allocated new insn_chain structures. */
978 reload_firstobj = obstack_alloc (&reload_obstack, 0);
981 calculate_needs_all_insns (global);
983 CLEAR_REG_SET (&spilled_pseudos);
986 something_changed = 0;
988 /* If we allocated any new memory locations, make another pass
989 since it might have changed elimination offsets. */
990 if (starting_frame_size != get_frame_size ())
991 something_changed = 1;
993 /* Even if the frame size remained the same, we might still have
994 changed elimination offsets, e.g. if find_reloads called
995 force_const_mem requiring the back end to allocate a constant
996 pool base register that needs to be saved on the stack. */
997 else if (!verify_initial_elim_offsets ())
998 something_changed = 1;
1001 HARD_REG_SET to_spill;
1002 CLEAR_HARD_REG_SET (to_spill);
1003 update_eliminables (&to_spill);
1004 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1007 if (TEST_HARD_REG_BIT (to_spill, i))
1009 spill_hard_reg (i, 1);
1012 /* Regardless of the state of spills, if we previously had
1013 a register that we thought we could eliminate, but now can
1014 not eliminate, we must run another pass.
1016 Consider pseudos which have an entry in reg_equiv_* which
1017 reference an eliminable register. We must make another pass
1018 to update reg_equiv_* so that we do not substitute in the
1019 old value from when we thought the elimination could be
1021 something_changed = 1;
1025 select_reload_regs ();
1029 if (insns_need_reload != 0 || did_spill)
1030 something_changed |= finish_spills (global);
1032 if (! something_changed)
1035 if (caller_save_needed)
1036 delete_caller_save_insns ();
1038 obstack_free (&reload_obstack, reload_firstobj);
1041 /* If global-alloc was run, notify it of any register eliminations we have
1044 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1045 if (ep->can_eliminate)
1046 mark_elimination (ep->from, ep->to);
1048 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1049 If that insn didn't set the register (i.e., it copied the register to
1050 memory), just delete that insn instead of the equivalencing insn plus
1051 anything now dead. If we call delete_dead_insn on that insn, we may
1052 delete the insn that actually sets the register if the register dies
1053 there and that is incorrect. */
1055 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1057 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1060 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1062 rtx equiv_insn = XEXP (list, 0);
1064 /* If we already deleted the insn or if it may trap, we can't
1065 delete it. The latter case shouldn't happen, but can
1066 if an insn has a variable address, gets a REG_EH_REGION
1067 note added to it, and then gets converted into a load
1068 from a constant address. */
1069 if (NOTE_P (equiv_insn)
1070 || can_throw_internal (equiv_insn))
1072 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1073 delete_dead_insn (equiv_insn);
1075 SET_INSN_DELETED (equiv_insn);
1080 /* Use the reload registers where necessary
1081 by generating move instructions to move the must-be-register
1082 values into or out of the reload registers. */
1084 if (insns_need_reload != 0 || something_needs_elimination
1085 || something_needs_operands_changed)
1087 HOST_WIDE_INT old_frame_size = get_frame_size ();
1089 reload_as_needed (global);
1091 gcc_assert (old_frame_size == get_frame_size ());
1093 gcc_assert (verify_initial_elim_offsets ());
1096 /* If we were able to eliminate the frame pointer, show that it is no
1097 longer live at the start of any basic block. If it ls live by
1098 virtue of being in a pseudo, that pseudo will be marked live
1099 and hence the frame pointer will be known to be live via that
1102 if (! frame_pointer_needed)
1104 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1105 HARD_FRAME_POINTER_REGNUM);
1107 /* Come here (with failure set nonzero) if we can't get enough spill
1111 CLEAR_REG_SET (&spilled_pseudos);
1112 reload_in_progress = 0;
1114 /* Now eliminate all pseudo regs by modifying them into
1115 their equivalent memory references.
1116 The REG-rtx's for the pseudos are modified in place,
1117 so all insns that used to refer to them now refer to memory.
1119 For a reg that has a reg_equiv_address, all those insns
1120 were changed by reloading so that no insns refer to it any longer;
1121 but the DECL_RTL of a variable decl may refer to it,
1122 and if so this causes the debugging info to mention the variable. */
1124 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1128 if (reg_equiv_mem[i])
1129 addr = XEXP (reg_equiv_mem[i], 0);
1131 if (reg_equiv_address[i])
1132 addr = reg_equiv_address[i];
1136 if (reg_renumber[i] < 0)
1138 rtx reg = regno_reg_rtx[i];
1140 REG_USERVAR_P (reg) = 0;
1141 PUT_CODE (reg, MEM);
1142 XEXP (reg, 0) = addr;
1143 if (reg_equiv_memory_loc[i])
1144 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1147 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1148 MEM_ATTRS (reg) = 0;
1150 MEM_NOTRAP_P (reg) = 1;
1152 else if (reg_equiv_mem[i])
1153 XEXP (reg_equiv_mem[i], 0) = addr;
1157 /* We must set reload_completed now since the cleanup_subreg_operands call
1158 below will re-recognize each insn and reload may have generated insns
1159 which are only valid during and after reload. */
1160 reload_completed = 1;
1162 /* Make a pass over all the insns and delete all USEs which we inserted
1163 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1164 notes. Delete all CLOBBER insns, except those that refer to the return
1165 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1166 from misarranging variable-array code, and simplify (subreg (reg))
1167 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1168 are no longer useful or accurate. Strip and regenerate REG_INC notes
1169 that may have been moved around. */
1171 for (insn = first; insn; insn = NEXT_INSN (insn))
1177 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1178 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1180 if ((GET_CODE (PATTERN (insn)) == USE
1181 /* We mark with QImode USEs introduced by reload itself. */
1182 && (GET_MODE (insn) == QImode
1183 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1184 || (GET_CODE (PATTERN (insn)) == CLOBBER
1185 && (!MEM_P (XEXP (PATTERN (insn), 0))
1186 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1187 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1188 && XEXP (XEXP (PATTERN (insn), 0), 0)
1189 != stack_pointer_rtx))
1190 && (!REG_P (XEXP (PATTERN (insn), 0))
1191 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1197 /* Some CLOBBERs may survive until here and still reference unassigned
1198 pseudos with const equivalent, which may in turn cause ICE in later
1199 passes if the reference remains in place. */
1200 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1201 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1202 VOIDmode, PATTERN (insn));
1204 /* Discard obvious no-ops, even without -O. This optimization
1205 is fast and doesn't interfere with debugging. */
1206 if (NONJUMP_INSN_P (insn)
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && REG_P (SET_SRC (PATTERN (insn)))
1209 && REG_P (SET_DEST (PATTERN (insn)))
1210 && (REGNO (SET_SRC (PATTERN (insn)))
1211 == REGNO (SET_DEST (PATTERN (insn)))))
1217 pnote = ®_NOTES (insn);
1220 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1221 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1222 || REG_NOTE_KIND (*pnote) == REG_INC
1223 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1224 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1225 *pnote = XEXP (*pnote, 1);
1227 pnote = &XEXP (*pnote, 1);
1231 add_auto_inc_notes (insn, PATTERN (insn));
1234 /* Simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn);
1237 /* Clean up invalid ASMs so that they don't confuse later passes.
1239 if (asm_noperands (PATTERN (insn)) >= 0)
1241 extract_insn (insn);
1242 if (!constrain_operands (1))
1244 error_for_asm (insn,
1245 "%<asm%> operand has impossible constraints");
1252 /* If we are doing stack checking, give a warning if this function's
1253 frame size is larger than we expect. */
1254 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1256 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1257 static int verbose_warned = 0;
1259 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1260 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1261 size += UNITS_PER_WORD;
1263 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1265 warning (0, "frame size too large for reliable stack checking");
1266 if (! verbose_warned)
1268 warning (0, "try reducing the number of local variables");
1274 /* Indicate that we no longer have known memory locations or constants. */
1275 if (reg_equiv_constant)
1276 free (reg_equiv_constant);
1277 if (reg_equiv_invariant)
1278 free (reg_equiv_invariant);
1279 reg_equiv_constant = 0;
1280 reg_equiv_invariant = 0;
1281 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1282 reg_equiv_memory_loc = 0;
1284 if (offsets_known_at)
1285 free (offsets_known_at);
1289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1290 if (reg_equiv_alt_mem_list[i])
1291 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1292 free (reg_equiv_alt_mem_list);
1294 free (reg_equiv_mem);
1296 free (reg_equiv_address);
1297 free (reg_max_ref_width);
1298 free (reg_old_renumber);
1299 free (pseudo_previous_regs);
1300 free (pseudo_forbidden_regs);
1302 CLEAR_HARD_REG_SET (used_spill_regs);
1303 for (i = 0; i < n_spills; i++)
1304 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1306 /* Free all the insn_chain structures at once. */
1307 obstack_free (&reload_obstack, reload_startobj);
1308 unused_insn_chains = 0;
1309 fixup_abnormal_edges ();
1311 /* Replacing pseudos with their memory equivalents might have
1312 created shared rtx. Subsequent passes would get confused
1313 by this, so unshare everything here. */
1314 unshare_all_rtl_again (first);
1316 #ifdef STACK_BOUNDARY
1317 /* init_emit has set the alignment of the hard frame pointer
1318 to STACK_BOUNDARY. It is very likely no longer valid if
1319 the hard frame pointer was used for register allocation. */
1320 if (!frame_pointer_needed)
1321 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1327 /* Yet another special case. Unfortunately, reg-stack forces people to
1328 write incorrect clobbers in asm statements. These clobbers must not
1329 cause the register to appear in bad_spill_regs, otherwise we'll call
1330 fatal_insn later. We clear the corresponding regnos in the live
1331 register sets to avoid this.
1332 The whole thing is rather sick, I'm afraid. */
1335 maybe_fix_stack_asms (void)
1338 const char *constraints[MAX_RECOG_OPERANDS];
1339 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1340 struct insn_chain *chain;
1342 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1345 HARD_REG_SET clobbered, allowed;
1348 if (! INSN_P (chain->insn)
1349 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1351 pat = PATTERN (chain->insn);
1352 if (GET_CODE (pat) != PARALLEL)
1355 CLEAR_HARD_REG_SET (clobbered);
1356 CLEAR_HARD_REG_SET (allowed);
1358 /* First, make a mask of all stack regs that are clobbered. */
1359 for (i = 0; i < XVECLEN (pat, 0); i++)
1361 rtx t = XVECEXP (pat, 0, i);
1362 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1363 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1366 /* Get the operand values and constraints out of the insn. */
1367 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1368 constraints, operand_mode, NULL);
1370 /* For every operand, see what registers are allowed. */
1371 for (i = 0; i < noperands; i++)
1373 const char *p = constraints[i];
1374 /* For every alternative, we compute the class of registers allowed
1375 for reloading in CLS, and merge its contents into the reg set
1377 int cls = (int) NO_REGS;
1383 if (c == '\0' || c == ',' || c == '#')
1385 /* End of one alternative - mark the regs in the current
1386 class, and reset the class. */
1387 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1393 } while (c != '\0' && c != ',');
1401 case '=': case '+': case '*': case '%': case '?': case '!':
1402 case '0': case '1': case '2': case '3': case '4': case 'm':
1403 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1404 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1405 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1410 cls = (int) reg_class_subunion[cls]
1411 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1416 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1420 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1421 cls = (int) reg_class_subunion[cls]
1422 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1424 cls = (int) reg_class_subunion[cls]
1425 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1427 p += CONSTRAINT_LEN (c, p);
1430 /* Those of the registers which are clobbered, but allowed by the
1431 constraints, must be usable as reload registers. So clear them
1432 out of the life information. */
1433 AND_HARD_REG_SET (allowed, clobbered);
1434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1435 if (TEST_HARD_REG_BIT (allowed, i))
1437 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1438 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1445 /* Copy the global variables n_reloads and rld into the corresponding elts
1448 copy_reloads (struct insn_chain *chain)
1450 chain->n_reloads = n_reloads;
1451 chain->rld = obstack_alloc (&reload_obstack,
1452 n_reloads * sizeof (struct reload));
1453 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1454 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1457 /* Walk the chain of insns, and determine for each whether it needs reloads
1458 and/or eliminations. Build the corresponding insns_need_reload list, and
1459 set something_needs_elimination as appropriate. */
1461 calculate_needs_all_insns (int global)
1463 struct insn_chain **pprev_reload = &insns_need_reload;
1464 struct insn_chain *chain, *next = 0;
1466 something_needs_elimination = 0;
1468 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1469 for (chain = reload_insn_chain; chain != 0; chain = next)
1471 rtx insn = chain->insn;
1475 /* Clear out the shortcuts. */
1476 chain->n_reloads = 0;
1477 chain->need_elim = 0;
1478 chain->need_reload = 0;
1479 chain->need_operand_change = 0;
1481 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1482 include REG_LABEL), we need to see what effects this has on the
1483 known offsets at labels. */
1485 if (LABEL_P (insn) || JUMP_P (insn)
1486 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1487 set_label_offsets (insn, insn, 0);
1491 rtx old_body = PATTERN (insn);
1492 int old_code = INSN_CODE (insn);
1493 rtx old_notes = REG_NOTES (insn);
1494 int did_elimination = 0;
1495 int operands_changed = 0;
1496 rtx set = single_set (insn);
1498 /* Skip insns that only set an equivalence. */
1499 if (set && REG_P (SET_DEST (set))
1500 && reg_renumber[REGNO (SET_DEST (set))] < 0
1501 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1502 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1503 && reg_equiv_init[REGNO (SET_DEST (set))])
1506 /* If needed, eliminate any eliminable registers. */
1507 if (num_eliminable || num_eliminable_invariants)
1508 did_elimination = eliminate_regs_in_insn (insn, 0);
1510 /* Analyze the instruction. */
1511 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1512 global, spill_reg_order);
1514 /* If a no-op set needs more than one reload, this is likely
1515 to be something that needs input address reloads. We
1516 can't get rid of this cleanly later, and it is of no use
1517 anyway, so discard it now.
1518 We only do this when expensive_optimizations is enabled,
1519 since this complements reload inheritance / output
1520 reload deletion, and it can make debugging harder. */
1521 if (flag_expensive_optimizations && n_reloads > 1)
1523 rtx set = single_set (insn);
1525 && SET_SRC (set) == SET_DEST (set)
1526 && REG_P (SET_SRC (set))
1527 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1530 /* Delete it from the reload chain. */
1532 chain->prev->next = next;
1534 reload_insn_chain = next;
1536 next->prev = chain->prev;
1537 chain->next = unused_insn_chains;
1538 unused_insn_chains = chain;
1543 update_eliminable_offsets ();
1545 /* Remember for later shortcuts which insns had any reloads or
1546 register eliminations. */
1547 chain->need_elim = did_elimination;
1548 chain->need_reload = n_reloads > 0;
1549 chain->need_operand_change = operands_changed;
1551 /* Discard any register replacements done. */
1552 if (did_elimination)
1554 obstack_free (&reload_obstack, reload_insn_firstobj);
1555 PATTERN (insn) = old_body;
1556 INSN_CODE (insn) = old_code;
1557 REG_NOTES (insn) = old_notes;
1558 something_needs_elimination = 1;
1561 something_needs_operands_changed |= operands_changed;
1565 copy_reloads (chain);
1566 *pprev_reload = chain;
1567 pprev_reload = &chain->next_need_reload;
1574 /* Comparison function for qsort to decide which of two reloads
1575 should be handled first. *P1 and *P2 are the reload numbers. */
1578 reload_reg_class_lower (const void *r1p, const void *r2p)
1580 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1583 /* Consider required reloads before optional ones. */
1584 t = rld[r1].optional - rld[r2].optional;
1588 /* Count all solitary classes before non-solitary ones. */
1589 t = ((reg_class_size[(int) rld[r2].class] == 1)
1590 - (reg_class_size[(int) rld[r1].class] == 1));
1594 /* Aside from solitaires, consider all multi-reg groups first. */
1595 t = rld[r2].nregs - rld[r1].nregs;
1599 /* Consider reloads in order of increasing reg-class number. */
1600 t = (int) rld[r1].class - (int) rld[r2].class;
1604 /* If reloads are equally urgent, sort by reload number,
1605 so that the results of qsort leave nothing to chance. */
1609 /* The cost of spilling each hard reg. */
1610 static int spill_cost[FIRST_PSEUDO_REGISTER];
1612 /* When spilling multiple hard registers, we use SPILL_COST for the first
1613 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1614 only the first hard reg for a multi-reg pseudo. */
1615 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1617 /* Update the spill cost arrays, considering that pseudo REG is live. */
1620 count_pseudo (int reg)
1622 int freq = REG_FREQ (reg);
1623 int r = reg_renumber[reg];
1626 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1627 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1630 SET_REGNO_REG_SET (&pseudos_counted, reg);
1632 gcc_assert (r >= 0);
1634 spill_add_cost[r] += freq;
1636 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1638 spill_cost[r + nregs] += freq;
1641 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1642 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1645 order_regs_for_reload (struct insn_chain *chain)
1648 HARD_REG_SET used_by_pseudos;
1649 HARD_REG_SET used_by_pseudos2;
1650 reg_set_iterator rsi;
1652 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1654 memset (spill_cost, 0, sizeof spill_cost);
1655 memset (spill_add_cost, 0, sizeof spill_add_cost);
1657 /* Count number of uses of each hard reg by pseudo regs allocated to it
1658 and then order them by decreasing use. First exclude hard registers
1659 that are live in or across this insn. */
1661 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1662 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1663 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1664 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1666 /* Now find out which pseudos are allocated to it, and update
1668 CLEAR_REG_SET (&pseudos_counted);
1670 EXECUTE_IF_SET_IN_REG_SET
1671 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1675 EXECUTE_IF_SET_IN_REG_SET
1676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1680 CLEAR_REG_SET (&pseudos_counted);
1683 /* Vector of reload-numbers showing the order in which the reloads should
1685 static short reload_order[MAX_RELOADS];
1687 /* This is used to keep track of the spill regs used in one insn. */
1688 static HARD_REG_SET used_spill_regs_local;
1690 /* We decided to spill hard register SPILLED, which has a size of
1691 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1692 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1693 update SPILL_COST/SPILL_ADD_COST. */
1696 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1698 int r = reg_renumber[reg];
1699 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1701 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1702 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1705 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1707 spill_add_cost[r] -= REG_FREQ (reg);
1709 spill_cost[r + nregs] -= REG_FREQ (reg);
1712 /* Find reload register to use for reload number ORDER. */
1715 find_reg (struct insn_chain *chain, int order)
1717 int rnum = reload_order[order];
1718 struct reload *rl = rld + rnum;
1719 int best_cost = INT_MAX;
1723 HARD_REG_SET not_usable;
1724 HARD_REG_SET used_by_other_reload;
1725 reg_set_iterator rsi;
1727 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1728 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1729 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1731 CLEAR_HARD_REG_SET (used_by_other_reload);
1732 for (k = 0; k < order; k++)
1734 int other = reload_order[k];
1736 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1737 for (j = 0; j < rld[other].nregs; j++)
1738 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1741 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1743 unsigned int regno = i;
1745 if (! TEST_HARD_REG_BIT (not_usable, regno)
1746 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1747 && HARD_REGNO_MODE_OK (regno, rl->mode))
1749 int this_cost = spill_cost[regno];
1751 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1753 for (j = 1; j < this_nregs; j++)
1755 this_cost += spill_add_cost[regno + j];
1756 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1757 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1762 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1764 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1766 if (this_cost < best_cost
1767 /* Among registers with equal cost, prefer caller-saved ones, or
1768 use REG_ALLOC_ORDER if it is defined. */
1769 || (this_cost == best_cost
1770 #ifdef REG_ALLOC_ORDER
1771 && (inv_reg_alloc_order[regno]
1772 < inv_reg_alloc_order[best_reg])
1774 && call_used_regs[regno]
1775 && ! call_used_regs[best_reg]
1780 best_cost = this_cost;
1788 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1790 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1791 rl->regno = best_reg;
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1796 count_spilled_pseudo (best_reg, rl->nregs, j);
1799 EXECUTE_IF_SET_IN_REG_SET
1800 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1802 count_spilled_pseudo (best_reg, rl->nregs, j);
1805 for (i = 0; i < rl->nregs; i++)
1807 gcc_assert (spill_cost[best_reg + i] == 0);
1808 gcc_assert (spill_add_cost[best_reg + i] == 0);
1809 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1814 /* Find more reload regs to satisfy the remaining need of an insn, which
1816 Do it by ascending class number, since otherwise a reg
1817 might be spilled for a big class and might fail to count
1818 for a smaller class even though it belongs to that class. */
1821 find_reload_regs (struct insn_chain *chain)
1825 /* In order to be certain of getting the registers we need,
1826 we must sort the reloads into order of increasing register class.
1827 Then our grabbing of reload registers will parallel the process
1828 that provided the reload registers. */
1829 for (i = 0; i < chain->n_reloads; i++)
1831 /* Show whether this reload already has a hard reg. */
1832 if (chain->rld[i].reg_rtx)
1834 int regno = REGNO (chain->rld[i].reg_rtx);
1835 chain->rld[i].regno = regno;
1837 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1840 chain->rld[i].regno = -1;
1841 reload_order[i] = i;
1844 n_reloads = chain->n_reloads;
1845 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1847 CLEAR_HARD_REG_SET (used_spill_regs_local);
1850 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1852 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1854 /* Compute the order of preference for hard registers to spill. */
1856 order_regs_for_reload (chain);
1858 for (i = 0; i < n_reloads; i++)
1860 int r = reload_order[i];
1862 /* Ignore reloads that got marked inoperative. */
1863 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1864 && ! rld[r].optional
1865 && rld[r].regno == -1)
1866 if (! find_reg (chain, i))
1869 fprintf (dump_file, "reload failure for reload %d\n", r);
1870 spill_failure (chain->insn, rld[r].class);
1876 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1877 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1879 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1883 select_reload_regs (void)
1885 struct insn_chain *chain;
1887 /* Try to satisfy the needs for each insn. */
1888 for (chain = insns_need_reload; chain != 0;
1889 chain = chain->next_need_reload)
1890 find_reload_regs (chain);
1893 /* Delete all insns that were inserted by emit_caller_save_insns during
1896 delete_caller_save_insns (void)
1898 struct insn_chain *c = reload_insn_chain;
1902 while (c != 0 && c->is_caller_save_insn)
1904 struct insn_chain *next = c->next;
1907 if (c == reload_insn_chain)
1908 reload_insn_chain = next;
1912 next->prev = c->prev;
1914 c->prev->next = next;
1915 c->next = unused_insn_chains;
1916 unused_insn_chains = c;
1924 /* Handle the failure to find a register to spill.
1925 INSN should be one of the insns which needed this particular spill reg. */
1928 spill_failure (rtx insn, enum reg_class class)
1930 if (asm_noperands (PATTERN (insn)) >= 0)
1931 error_for_asm (insn, "can't find a register in class %qs while "
1932 "reloading %<asm%>",
1933 reg_class_names[class]);
1936 error ("unable to find a register to spill in class %qs",
1937 reg_class_names[class]);
1941 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1942 debug_reload_to_stream (dump_file);
1944 fatal_insn ("this is the insn:", insn);
1948 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1949 data that is dead in INSN. */
1952 delete_dead_insn (rtx insn)
1954 rtx prev = prev_real_insn (insn);
1957 /* If the previous insn sets a register that dies in our insn, delete it
1959 if (prev && GET_CODE (PATTERN (prev)) == SET
1960 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1961 && reg_mentioned_p (prev_dest, PATTERN (insn))
1962 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1963 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1964 delete_dead_insn (prev);
1966 SET_INSN_DELETED (insn);
1969 /* Modify the home of pseudo-reg I.
1970 The new home is present in reg_renumber[I].
1972 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1973 or it may be -1, meaning there is none or it is not relevant.
1974 This is used so that all pseudos spilled from a given hard reg
1975 can share one stack slot. */
1978 alter_reg (int i, int from_reg)
1980 /* When outputting an inline function, this can happen
1981 for a reg that isn't actually used. */
1982 if (regno_reg_rtx[i] == 0)
1985 /* If the reg got changed to a MEM at rtl-generation time,
1987 if (!REG_P (regno_reg_rtx[i]))
1990 /* Modify the reg-rtx to contain the new hard reg
1991 number or else to contain its pseudo reg number. */
1992 REGNO (regno_reg_rtx[i])
1993 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1995 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1996 allocate a stack slot for it. */
1998 if (reg_renumber[i] < 0
1999 && REG_N_REFS (i) > 0
2000 && reg_equiv_constant[i] == 0
2001 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2002 && reg_equiv_memory_loc[i] == 0)
2005 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2006 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2007 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2008 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2009 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2012 /* Each pseudo reg has an inherent size which comes from its own mode,
2013 and a total size which provides room for paradoxical subregs
2014 which refer to the pseudo reg in wider modes.
2016 We can use a slot already allocated if it provides both
2017 enough inherent space and enough total space.
2018 Otherwise, we allocate a new slot, making sure that it has no less
2019 inherent space, and no less total space, then the previous slot. */
2022 /* No known place to spill from => no slot to reuse. */
2023 x = assign_stack_local (mode, total_size,
2024 min_align > inherent_align
2025 || total_size > inherent_size ? -1 : 0);
2026 if (BYTES_BIG_ENDIAN)
2027 /* Cancel the big-endian correction done in assign_stack_local.
2028 Get the address of the beginning of the slot.
2029 This is so we can do a big-endian correction unconditionally
2031 adjust = inherent_size - total_size;
2033 /* Nothing can alias this slot except this pseudo. */
2034 set_mem_alias_set (x, new_alias_set ());
2037 /* Reuse a stack slot if possible. */
2038 else if (spill_stack_slot[from_reg] != 0
2039 && spill_stack_slot_width[from_reg] >= total_size
2040 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2042 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2043 x = spill_stack_slot[from_reg];
2045 /* Allocate a bigger slot. */
2048 /* Compute maximum size needed, both for inherent size
2049 and for total size. */
2052 if (spill_stack_slot[from_reg])
2054 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2056 mode = GET_MODE (spill_stack_slot[from_reg]);
2057 if (spill_stack_slot_width[from_reg] > total_size)
2058 total_size = spill_stack_slot_width[from_reg];
2059 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2060 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2063 /* Make a slot with that size. */
2064 x = assign_stack_local (mode, total_size,
2065 min_align > inherent_align
2066 || total_size > inherent_size ? -1 : 0);
2069 /* All pseudos mapped to this slot can alias each other. */
2070 if (spill_stack_slot[from_reg])
2071 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2073 set_mem_alias_set (x, new_alias_set ());
2075 if (BYTES_BIG_ENDIAN)
2077 /* Cancel the big-endian correction done in assign_stack_local.
2078 Get the address of the beginning of the slot.
2079 This is so we can do a big-endian correction unconditionally
2081 adjust = GET_MODE_SIZE (mode) - total_size;
2084 = adjust_address_nv (x, mode_for_size (total_size
2090 spill_stack_slot[from_reg] = stack_slot;
2091 spill_stack_slot_width[from_reg] = total_size;
2094 /* On a big endian machine, the "address" of the slot
2095 is the address of the low part that fits its inherent mode. */
2096 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2097 adjust += (total_size - inherent_size);
2099 /* If we have any adjustment to make, or if the stack slot is the
2100 wrong mode, make a new stack slot. */
2101 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2103 /* If we have a decl for the original register, set it for the
2104 memory. If this is a shared MEM, make a copy. */
2105 if (REG_EXPR (regno_reg_rtx[i])
2106 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2108 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2110 /* We can do this only for the DECLs home pseudo, not for
2111 any copies of it, since otherwise when the stack slot
2112 is reused, nonoverlapping_memrefs_p might think they
2114 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2116 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2119 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2123 /* Save the stack slot for later. */
2124 reg_equiv_memory_loc[i] = x;
2128 /* Mark the slots in regs_ever_live for the hard regs
2129 used by pseudo-reg number REGNO. */
2132 mark_home_live (int regno)
2136 i = reg_renumber[regno];
2139 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2141 regs_ever_live[i++] = 1;
2144 /* This function handles the tracking of elimination offsets around branches.
2146 X is a piece of RTL being scanned.
2148 INSN is the insn that it came from, if any.
2150 INITIAL_P is nonzero if we are to set the offset to be the initial
2151 offset and zero if we are setting the offset of the label to be the
2155 set_label_offsets (rtx x, rtx insn, int initial_p)
2157 enum rtx_code code = GET_CODE (x);
2160 struct elim_table *p;
2165 if (LABEL_REF_NONLOCAL_P (x))
2170 /* ... fall through ... */
2173 /* If we know nothing about this label, set the desired offsets. Note
2174 that this sets the offset at a label to be the offset before a label
2175 if we don't know anything about the label. This is not correct for
2176 the label after a BARRIER, but is the best guess we can make. If
2177 we guessed wrong, we will suppress an elimination that might have
2178 been possible had we been able to guess correctly. */
2180 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2182 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2183 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2184 = (initial_p ? reg_eliminate[i].initial_offset
2185 : reg_eliminate[i].offset);
2186 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2189 /* Otherwise, if this is the definition of a label and it is
2190 preceded by a BARRIER, set our offsets to the known offset of
2194 && (tem = prev_nonnote_insn (insn)) != 0
2196 set_offsets_for_label (insn);
2198 /* If neither of the above cases is true, compare each offset
2199 with those previously recorded and suppress any eliminations
2200 where the offsets disagree. */
2202 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2203 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2204 != (initial_p ? reg_eliminate[i].initial_offset
2205 : reg_eliminate[i].offset))
2206 reg_eliminate[i].can_eliminate = 0;
2211 set_label_offsets (PATTERN (insn), insn, initial_p);
2213 /* ... fall through ... */
2217 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2218 and hence must have all eliminations at their initial offsets. */
2219 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2220 if (REG_NOTE_KIND (tem) == REG_LABEL)
2221 set_label_offsets (XEXP (tem, 0), insn, 1);
2227 /* Each of the labels in the parallel or address vector must be
2228 at their initial offsets. We want the first field for PARALLEL
2229 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2231 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2232 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2237 /* We only care about setting PC. If the source is not RETURN,
2238 IF_THEN_ELSE, or a label, disable any eliminations not at
2239 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2240 isn't one of those possibilities. For branches to a label,
2241 call ourselves recursively.
2243 Note that this can disable elimination unnecessarily when we have
2244 a non-local goto since it will look like a non-constant jump to
2245 someplace in the current function. This isn't a significant
2246 problem since such jumps will normally be when all elimination
2247 pairs are back to their initial offsets. */
2249 if (SET_DEST (x) != pc_rtx)
2252 switch (GET_CODE (SET_SRC (x)))
2259 set_label_offsets (SET_SRC (x), insn, initial_p);
2263 tem = XEXP (SET_SRC (x), 1);
2264 if (GET_CODE (tem) == LABEL_REF)
2265 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2266 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2269 tem = XEXP (SET_SRC (x), 2);
2270 if (GET_CODE (tem) == LABEL_REF)
2271 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2272 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2280 /* If we reach here, all eliminations must be at their initial
2281 offset because we are doing a jump to a variable address. */
2282 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2283 if (p->offset != p->initial_offset)
2284 p->can_eliminate = 0;
2292 /* Scan X and replace any eliminable registers (such as fp) with a
2293 replacement (such as sp), plus an offset.
2295 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2296 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2297 MEM, we are allowed to replace a sum of a register and the constant zero
2298 with the register, which we cannot do outside a MEM. In addition, we need
2299 to record the fact that a register is referenced outside a MEM.
2301 If INSN is an insn, it is the insn containing X. If we replace a REG
2302 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2303 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2304 the REG is being modified.
2306 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2307 That's used when we eliminate in expressions stored in notes.
2308 This means, do not set ref_outside_mem even if the reference
2311 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2312 replacements done assuming all offsets are at their initial values. If
2313 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2314 encounter, return the actual location so that find_reloads will do
2315 the proper thing. */
2318 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2319 bool may_use_invariant)
2321 enum rtx_code code = GET_CODE (x);
2322 struct elim_table *ep;
2329 if (! current_function_decl)
2351 /* First handle the case where we encounter a bare register that
2352 is eliminable. Replace it with a PLUS. */
2353 if (regno < FIRST_PSEUDO_REGISTER)
2355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2357 if (ep->from_rtx == x && ep->can_eliminate)
2358 return plus_constant (ep->to_rtx, ep->previous_offset);
2361 else if (reg_renumber && reg_renumber[regno] < 0
2362 && reg_equiv_invariant && reg_equiv_invariant[regno])
2364 if (may_use_invariant)
2365 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2366 mem_mode, insn, true);
2367 /* There exists at least one use of REGNO that cannot be
2368 eliminated. Prevent the defining insn from being deleted. */
2369 reg_equiv_init[regno] = NULL_RTX;
2370 alter_reg (regno, -1);
2374 /* You might think handling MINUS in a manner similar to PLUS is a
2375 good idea. It is not. It has been tried multiple times and every
2376 time the change has had to have been reverted.
2378 Other parts of reload know a PLUS is special (gen_reload for example)
2379 and require special code to handle code a reloaded PLUS operand.
2381 Also consider backends where the flags register is clobbered by a
2382 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2383 lea instruction comes to mind). If we try to reload a MINUS, we
2384 may kill the flags register that was holding a useful value.
2386 So, please before trying to handle MINUS, consider reload as a
2387 whole instead of this little section as well as the backend issues. */
2389 /* If this is the sum of an eliminable register and a constant, rework
2391 if (REG_P (XEXP (x, 0))
2392 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2393 && CONSTANT_P (XEXP (x, 1)))
2395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2397 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2399 /* The only time we want to replace a PLUS with a REG (this
2400 occurs when the constant operand of the PLUS is the negative
2401 of the offset) is when we are inside a MEM. We won't want
2402 to do so at other times because that would change the
2403 structure of the insn in a way that reload can't handle.
2404 We special-case the commonest situation in
2405 eliminate_regs_in_insn, so just replace a PLUS with a
2406 PLUS here, unless inside a MEM. */
2407 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2408 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2411 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2412 plus_constant (XEXP (x, 1),
2413 ep->previous_offset));
2416 /* If the register is not eliminable, we are done since the other
2417 operand is a constant. */
2421 /* If this is part of an address, we want to bring any constant to the
2422 outermost PLUS. We will do this by doing register replacement in
2423 our operands and seeing if a constant shows up in one of them.
2425 Note that there is no risk of modifying the structure of the insn,
2426 since we only get called for its operands, thus we are either
2427 modifying the address inside a MEM, or something like an address
2428 operand of a load-address insn. */
2431 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2432 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2434 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2436 /* If one side is a PLUS and the other side is a pseudo that
2437 didn't get a hard register but has a reg_equiv_constant,
2438 we must replace the constant here since it may no longer
2439 be in the position of any operand. */
2440 if (GET_CODE (new0) == PLUS && REG_P (new1)
2441 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2442 && reg_renumber[REGNO (new1)] < 0
2443 && reg_equiv_constant != 0
2444 && reg_equiv_constant[REGNO (new1)] != 0)
2445 new1 = reg_equiv_constant[REGNO (new1)];
2446 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2447 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2448 && reg_renumber[REGNO (new0)] < 0
2449 && reg_equiv_constant[REGNO (new0)] != 0)
2450 new0 = reg_equiv_constant[REGNO (new0)];
2452 new = form_sum (new0, new1);
2454 /* As above, if we are not inside a MEM we do not want to
2455 turn a PLUS into something else. We might try to do so here
2456 for an addition of 0 if we aren't optimizing. */
2457 if (! mem_mode && GET_CODE (new) != PLUS)
2458 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2466 /* If this is the product of an eliminable register and a
2467 constant, apply the distribute law and move the constant out
2468 so that we have (plus (mult ..) ..). This is needed in order
2469 to keep load-address insns valid. This case is pathological.
2470 We ignore the possibility of overflow here. */
2471 if (REG_P (XEXP (x, 0))
2472 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2473 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2476 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2479 /* Refs inside notes don't count for this purpose. */
2480 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2481 || GET_CODE (insn) == INSN_LIST)))
2482 ep->ref_outside_mem = 1;
2485 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2486 ep->previous_offset * INTVAL (XEXP (x, 1)));
2489 /* ... fall through ... */
2493 /* See comments before PLUS about handling MINUS. */
2495 case DIV: case UDIV:
2496 case MOD: case UMOD:
2497 case AND: case IOR: case XOR:
2498 case ROTATERT: case ROTATE:
2499 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2501 case GE: case GT: case GEU: case GTU:
2502 case LE: case LT: case LEU: case LTU:
2504 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2505 rtx new1 = XEXP (x, 1)
2506 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2508 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2509 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2514 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2517 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2518 if (new != XEXP (x, 0))
2520 /* If this is a REG_DEAD note, it is not valid anymore.
2521 Using the eliminated version could result in creating a
2522 REG_DEAD note for the stack or frame pointer. */
2523 if (GET_MODE (x) == REG_DEAD)
2525 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2528 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2532 /* ... fall through ... */
2535 /* Now do eliminations in the rest of the chain. If this was
2536 an EXPR_LIST, this might result in allocating more memory than is
2537 strictly needed, but it simplifies the code. */
2540 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2541 if (new != XEXP (x, 1))
2543 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2551 /* We do not support elimination of a register that is modified.
2552 elimination_effects has already make sure that this does not
2558 /* We do not support elimination of a register that is modified.
2559 elimination_effects has already make sure that this does not
2560 happen. The only remaining case we need to consider here is
2561 that the increment value may be an eliminable register. */
2562 if (GET_CODE (XEXP (x, 1)) == PLUS
2563 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2565 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2568 if (new != XEXP (XEXP (x, 1), 1))
2569 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2570 gen_rtx_PLUS (GET_MODE (x),
2575 case STRICT_LOW_PART:
2577 case SIGN_EXTEND: case ZERO_EXTEND:
2578 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2579 case FLOAT: case FIX:
2580 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2589 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2590 if (new != XEXP (x, 0))
2591 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2595 /* Similar to above processing, but preserve SUBREG_BYTE.
2596 Convert (subreg (mem)) to (mem) if not paradoxical.
2597 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2598 pseudo didn't get a hard reg, we must replace this with the
2599 eliminated version of the memory location because push_reload
2600 may do the replacement in certain circumstances. */
2601 if (REG_P (SUBREG_REG (x))
2602 && (GET_MODE_SIZE (GET_MODE (x))
2603 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2604 && reg_equiv_memory_loc != 0
2605 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2607 new = SUBREG_REG (x);
2610 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2612 if (new != SUBREG_REG (x))
2614 int x_size = GET_MODE_SIZE (GET_MODE (x));
2615 int new_size = GET_MODE_SIZE (GET_MODE (new));
2618 && ((x_size < new_size
2619 #ifdef WORD_REGISTER_OPERATIONS
2620 /* On these machines, combine can create rtl of the form
2621 (set (subreg:m1 (reg:m2 R) 0) ...)
2622 where m1 < m2, and expects something interesting to
2623 happen to the entire word. Moreover, it will use the
2624 (reg:m2 R) later, expecting all bits to be preserved.
2625 So if the number of words is the same, preserve the
2626 subreg so that push_reload can see it. */
2627 && ! ((x_size - 1) / UNITS_PER_WORD
2628 == (new_size -1 ) / UNITS_PER_WORD)
2631 || x_size == new_size)
2633 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2635 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2641 /* Our only special processing is to pass the mode of the MEM to our
2642 recursive call and copy the flags. While we are here, handle this
2643 case more efficiently. */
2645 replace_equiv_address_nv (x,
2646 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2650 /* Handle insn_list USE that a call to a pure function may generate. */
2651 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2652 if (new != XEXP (x, 0))
2653 return gen_rtx_USE (GET_MODE (x), new);
2665 /* Process each of our operands recursively. If any have changed, make a
2667 fmt = GET_RTX_FORMAT (code);
2668 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2672 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2673 if (new != XEXP (x, i) && ! copied)
2675 x = shallow_copy_rtx (x);
2680 else if (*fmt == 'E')
2683 for (j = 0; j < XVECLEN (x, i); j++)
2685 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2686 if (new != XVECEXP (x, i, j) && ! copied_vec)
2688 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2692 x = shallow_copy_rtx (x);
2695 XVEC (x, i) = new_v;
2698 XVECEXP (x, i, j) = new;
2707 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2709 return eliminate_regs_1 (x, mem_mode, insn, false);
2712 /* Scan rtx X for modifications of elimination target registers. Update
2713 the table of eliminables to reflect the changed state. MEM_MODE is
2714 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2717 elimination_effects (rtx x, enum machine_mode mem_mode)
2719 enum rtx_code code = GET_CODE (x);
2720 struct elim_table *ep;
2744 /* First handle the case where we encounter a bare register that
2745 is eliminable. Replace it with a PLUS. */
2746 if (regno < FIRST_PSEUDO_REGISTER)
2748 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2750 if (ep->from_rtx == x && ep->can_eliminate)
2753 ep->ref_outside_mem = 1;
2758 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2759 && reg_equiv_constant[regno]
2760 && ! function_invariant_p (reg_equiv_constant[regno]))
2761 elimination_effects (reg_equiv_constant[regno], mem_mode);
2770 /* If we modify the source of an elimination rule, disable it. */
2771 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2772 if (ep->from_rtx == XEXP (x, 0))
2773 ep->can_eliminate = 0;
2775 /* If we modify the target of an elimination rule by adding a constant,
2776 update its offset. If we modify the target in any other way, we'll
2777 have to disable the rule as well. */
2778 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2779 if (ep->to_rtx == XEXP (x, 0))
2781 int size = GET_MODE_SIZE (mem_mode);
2783 /* If more bytes than MEM_MODE are pushed, account for them. */
2784 #ifdef PUSH_ROUNDING
2785 if (ep->to_rtx == stack_pointer_rtx)
2786 size = PUSH_ROUNDING (size);
2788 if (code == PRE_DEC || code == POST_DEC)
2790 else if (code == PRE_INC || code == POST_INC)
2792 else if (code == PRE_MODIFY || code == POST_MODIFY)
2794 if (GET_CODE (XEXP (x, 1)) == PLUS
2795 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2796 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2797 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2799 ep->can_eliminate = 0;
2803 /* These two aren't unary operators. */
2804 if (code == POST_MODIFY || code == PRE_MODIFY)
2807 /* Fall through to generic unary operation case. */
2808 case STRICT_LOW_PART:
2810 case SIGN_EXTEND: case ZERO_EXTEND:
2811 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2812 case FLOAT: case FIX:
2813 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2822 elimination_effects (XEXP (x, 0), mem_mode);
2826 if (REG_P (SUBREG_REG (x))
2827 && (GET_MODE_SIZE (GET_MODE (x))
2828 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2829 && reg_equiv_memory_loc != 0
2830 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2833 elimination_effects (SUBREG_REG (x), mem_mode);
2837 /* If using a register that is the source of an eliminate we still
2838 think can be performed, note it cannot be performed since we don't
2839 know how this register is used. */
2840 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2841 if (ep->from_rtx == XEXP (x, 0))
2842 ep->can_eliminate = 0;
2844 elimination_effects (XEXP (x, 0), mem_mode);
2848 /* If clobbering a register that is the replacement register for an
2849 elimination we still think can be performed, note that it cannot
2850 be performed. Otherwise, we need not be concerned about it. */
2851 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2852 if (ep->to_rtx == XEXP (x, 0))
2853 ep->can_eliminate = 0;
2855 elimination_effects (XEXP (x, 0), mem_mode);
2859 /* Check for setting a register that we know about. */
2860 if (REG_P (SET_DEST (x)))
2862 /* See if this is setting the replacement register for an
2865 If DEST is the hard frame pointer, we do nothing because we
2866 assume that all assignments to the frame pointer are for
2867 non-local gotos and are being done at a time when they are valid
2868 and do not disturb anything else. Some machines want to
2869 eliminate a fake argument pointer (or even a fake frame pointer)
2870 with either the real frame or the stack pointer. Assignments to
2871 the hard frame pointer must not prevent this elimination. */
2873 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2875 if (ep->to_rtx == SET_DEST (x)
2876 && SET_DEST (x) != hard_frame_pointer_rtx)
2878 /* If it is being incremented, adjust the offset. Otherwise,
2879 this elimination can't be done. */
2880 rtx src = SET_SRC (x);
2882 if (GET_CODE (src) == PLUS
2883 && XEXP (src, 0) == SET_DEST (x)
2884 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2885 ep->offset -= INTVAL (XEXP (src, 1));
2887 ep->can_eliminate = 0;
2891 elimination_effects (SET_DEST (x), 0);
2892 elimination_effects (SET_SRC (x), 0);
2896 /* Our only special processing is to pass the mode of the MEM to our
2898 elimination_effects (XEXP (x, 0), GET_MODE (x));
2905 fmt = GET_RTX_FORMAT (code);
2906 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2909 elimination_effects (XEXP (x, i), mem_mode);
2910 else if (*fmt == 'E')
2911 for (j = 0; j < XVECLEN (x, i); j++)
2912 elimination_effects (XVECEXP (x, i, j), mem_mode);
2916 /* Descend through rtx X and verify that no references to eliminable registers
2917 remain. If any do remain, mark the involved register as not
2921 check_eliminable_occurrences (rtx x)
2930 code = GET_CODE (x);
2932 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2934 struct elim_table *ep;
2936 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2937 if (ep->from_rtx == x)
2938 ep->can_eliminate = 0;
2942 fmt = GET_RTX_FORMAT (code);
2943 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2946 check_eliminable_occurrences (XEXP (x, i));
2947 else if (*fmt == 'E')
2950 for (j = 0; j < XVECLEN (x, i); j++)
2951 check_eliminable_occurrences (XVECEXP (x, i, j));
2956 /* Scan INSN and eliminate all eliminable registers in it.
2958 If REPLACE is nonzero, do the replacement destructively. Also
2959 delete the insn as dead it if it is setting an eliminable register.
2961 If REPLACE is zero, do all our allocations in reload_obstack.
2963 If no eliminations were done and this insn doesn't require any elimination
2964 processing (these are not identical conditions: it might be updating sp,
2965 but not referencing fp; this needs to be seen during reload_as_needed so
2966 that the offset between fp and sp can be taken into consideration), zero
2967 is returned. Otherwise, 1 is returned. */
2970 eliminate_regs_in_insn (rtx insn, int replace)
2972 int icode = recog_memoized (insn);
2973 rtx old_body = PATTERN (insn);
2974 int insn_is_asm = asm_noperands (old_body) >= 0;
2975 rtx old_set = single_set (insn);
2979 rtx substed_operand[MAX_RECOG_OPERANDS];
2980 rtx orig_operand[MAX_RECOG_OPERANDS];
2981 struct elim_table *ep;
2982 rtx plus_src, plus_cst_src;
2984 if (! insn_is_asm && icode < 0)
2986 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2987 || GET_CODE (PATTERN (insn)) == CLOBBER
2988 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2989 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2990 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2994 if (old_set != 0 && REG_P (SET_DEST (old_set))
2995 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2997 /* Check for setting an eliminable register. */
2998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2999 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3001 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3002 /* If this is setting the frame pointer register to the
3003 hardware frame pointer register and this is an elimination
3004 that will be done (tested above), this insn is really
3005 adjusting the frame pointer downward to compensate for
3006 the adjustment done before a nonlocal goto. */
3007 if (ep->from == FRAME_POINTER_REGNUM
3008 && ep->to == HARD_FRAME_POINTER_REGNUM)
3010 rtx base = SET_SRC (old_set);
3011 rtx base_insn = insn;
3012 HOST_WIDE_INT offset = 0;
3014 while (base != ep->to_rtx)
3016 rtx prev_insn, prev_set;
3018 if (GET_CODE (base) == PLUS
3019 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3021 offset += INTVAL (XEXP (base, 1));
3022 base = XEXP (base, 0);
3024 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3025 && (prev_set = single_set (prev_insn)) != 0
3026 && rtx_equal_p (SET_DEST (prev_set), base))
3028 base = SET_SRC (prev_set);
3029 base_insn = prev_insn;
3035 if (base == ep->to_rtx)
3038 = plus_constant (ep->to_rtx, offset - ep->offset);
3040 new_body = old_body;
3043 new_body = copy_insn (old_body);
3044 if (REG_NOTES (insn))
3045 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3047 PATTERN (insn) = new_body;
3048 old_set = single_set (insn);
3050 /* First see if this insn remains valid when we
3051 make the change. If not, keep the INSN_CODE
3052 the same and let reload fit it up. */
3053 validate_change (insn, &SET_SRC (old_set), src, 1);
3054 validate_change (insn, &SET_DEST (old_set),
3056 if (! apply_change_group ())
3058 SET_SRC (old_set) = src;
3059 SET_DEST (old_set) = ep->to_rtx;
3068 /* In this case this insn isn't serving a useful purpose. We
3069 will delete it in reload_as_needed once we know that this
3070 elimination is, in fact, being done.
3072 If REPLACE isn't set, we can't delete this insn, but needn't
3073 process it since it won't be used unless something changes. */
3076 delete_dead_insn (insn);
3084 /* We allow one special case which happens to work on all machines we
3085 currently support: a single set with the source or a REG_EQUAL
3086 note being a PLUS of an eliminable register and a constant. */
3087 plus_src = plus_cst_src = 0;
3088 if (old_set && REG_P (SET_DEST (old_set)))
3090 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3091 plus_src = SET_SRC (old_set);
3092 /* First see if the source is of the form (plus (...) CST). */
3094 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3095 plus_cst_src = plus_src;
3096 else if (REG_P (SET_SRC (old_set))
3099 /* Otherwise, see if we have a REG_EQUAL note of the form
3100 (plus (...) CST). */
3102 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3104 if ((REG_NOTE_KIND (links) == REG_EQUAL
3105 || REG_NOTE_KIND (links) == REG_EQUIV)
3106 && GET_CODE (XEXP (links, 0)) == PLUS
3107 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3109 plus_cst_src = XEXP (links, 0);
3115 /* Check that the first operand of the PLUS is a hard reg or
3116 the lowpart subreg of one. */
3119 rtx reg = XEXP (plus_cst_src, 0);
3120 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3121 reg = SUBREG_REG (reg);
3123 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3129 rtx reg = XEXP (plus_cst_src, 0);
3130 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3132 if (GET_CODE (reg) == SUBREG)
3133 reg = SUBREG_REG (reg);
3135 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3136 if (ep->from_rtx == reg && ep->can_eliminate)
3138 rtx to_rtx = ep->to_rtx;
3139 offset += ep->offset;
3140 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3142 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3143 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3145 /* If we have a nonzero offset, and the source is already
3146 a simple REG, the following transformation would
3147 increase the cost of the insn by replacing a simple REG
3148 with (plus (reg sp) CST). So try only when we already
3149 had a PLUS before. */
3150 if (offset == 0 || plus_src)
3152 rtx new_src = plus_constant (to_rtx, offset);
3154 new_body = old_body;
3157 new_body = copy_insn (old_body);
3158 if (REG_NOTES (insn))
3159 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3161 PATTERN (insn) = new_body;
3162 old_set = single_set (insn);
3164 /* First see if this insn remains valid when we make the
3165 change. If not, try to replace the whole pattern with
3166 a simple set (this may help if the original insn was a
3167 PARALLEL that was only recognized as single_set due to
3168 REG_UNUSED notes). If this isn't valid either, keep
3169 the INSN_CODE the same and let reload fix it up. */
3170 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3172 rtx new_pat = gen_rtx_SET (VOIDmode,
3173 SET_DEST (old_set), new_src);
3175 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3176 SET_SRC (old_set) = new_src;
3183 /* This can't have an effect on elimination offsets, so skip right
3189 /* Determine the effects of this insn on elimination offsets. */
3190 elimination_effects (old_body, 0);
3192 /* Eliminate all eliminable registers occurring in operands that
3193 can be handled by reload. */
3194 extract_insn (insn);
3195 for (i = 0; i < recog_data.n_operands; i++)
3197 orig_operand[i] = recog_data.operand[i];
3198 substed_operand[i] = recog_data.operand[i];
3200 /* For an asm statement, every operand is eliminable. */
3201 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3203 bool is_set_src, in_plus;
3205 /* Check for setting a register that we know about. */
3206 if (recog_data.operand_type[i] != OP_IN
3207 && REG_P (orig_operand[i]))
3209 /* If we are assigning to a register that can be eliminated, it
3210 must be as part of a PARALLEL, since the code above handles
3211 single SETs. We must indicate that we can no longer
3212 eliminate this reg. */
3213 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3215 if (ep->from_rtx == orig_operand[i])
3216 ep->can_eliminate = 0;
3219 /* Companion to the above plus substitution, we can allow
3220 invariants as the source of a plain move. */
3222 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3226 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3227 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3231 = eliminate_regs_1 (recog_data.operand[i], 0,
3232 replace ? insn : NULL_RTX,
3233 is_set_src || in_plus);
3234 if (substed_operand[i] != orig_operand[i])
3236 /* Terminate the search in check_eliminable_occurrences at
3238 *recog_data.operand_loc[i] = 0;
3240 /* If an output operand changed from a REG to a MEM and INSN is an
3241 insn, write a CLOBBER insn. */
3242 if (recog_data.operand_type[i] != OP_IN
3243 && REG_P (orig_operand[i])
3244 && MEM_P (substed_operand[i])
3246 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3251 for (i = 0; i < recog_data.n_dups; i++)
3252 *recog_data.dup_loc[i]
3253 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3255 /* If any eliminable remain, they aren't eliminable anymore. */
3256 check_eliminable_occurrences (old_body);
3258 /* Substitute the operands; the new values are in the substed_operand
3260 for (i = 0; i < recog_data.n_operands; i++)
3261 *recog_data.operand_loc[i] = substed_operand[i];
3262 for (i = 0; i < recog_data.n_dups; i++)
3263 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3265 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3266 re-recognize the insn. We do this in case we had a simple addition
3267 but now can do this as a load-address. This saves an insn in this
3269 If re-recognition fails, the old insn code number will still be used,
3270 and some register operands may have changed into PLUS expressions.
3271 These will be handled by find_reloads by loading them into a register
3276 /* If we aren't replacing things permanently and we changed something,
3277 make another copy to ensure that all the RTL is new. Otherwise
3278 things can go wrong if find_reload swaps commutative operands
3279 and one is inside RTL that has been copied while the other is not. */
3280 new_body = old_body;
3283 new_body = copy_insn (old_body);
3284 if (REG_NOTES (insn))
3285 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3287 PATTERN (insn) = new_body;
3289 /* If we had a move insn but now we don't, rerecognize it. This will
3290 cause spurious re-recognition if the old move had a PARALLEL since
3291 the new one still will, but we can't call single_set without
3292 having put NEW_BODY into the insn and the re-recognition won't
3293 hurt in this rare case. */
3294 /* ??? Why this huge if statement - why don't we just rerecognize the
3298 && ((REG_P (SET_SRC (old_set))
3299 && (GET_CODE (new_body) != SET
3300 || !REG_P (SET_SRC (new_body))))
3301 /* If this was a load from or store to memory, compare
3302 the MEM in recog_data.operand to the one in the insn.
3303 If they are not equal, then rerecognize the insn. */
3305 && ((MEM_P (SET_SRC (old_set))
3306 && SET_SRC (old_set) != recog_data.operand[1])
3307 || (MEM_P (SET_DEST (old_set))
3308 && SET_DEST (old_set) != recog_data.operand[0])))
3309 /* If this was an add insn before, rerecognize. */
3310 || GET_CODE (SET_SRC (old_set)) == PLUS))
3312 int new_icode = recog (PATTERN (insn), insn, 0);
3314 INSN_CODE (insn) = new_icode;
3318 /* Restore the old body. If there were any changes to it, we made a copy
3319 of it while the changes were still in place, so we'll correctly return
3320 a modified insn below. */
3323 /* Restore the old body. */
3324 for (i = 0; i < recog_data.n_operands; i++)
3325 *recog_data.operand_loc[i] = orig_operand[i];
3326 for (i = 0; i < recog_data.n_dups; i++)
3327 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3330 /* Update all elimination pairs to reflect the status after the current
3331 insn. The changes we make were determined by the earlier call to
3332 elimination_effects.
3334 We also detect cases where register elimination cannot be done,
3335 namely, if a register would be both changed and referenced outside a MEM
3336 in the resulting insn since such an insn is often undefined and, even if
3337 not, we cannot know what meaning will be given to it. Note that it is
3338 valid to have a register used in an address in an insn that changes it
3339 (presumably with a pre- or post-increment or decrement).
3341 If anything changes, return nonzero. */
3343 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3345 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3346 ep->can_eliminate = 0;
3348 ep->ref_outside_mem = 0;
3350 if (ep->previous_offset != ep->offset)
3355 /* If we changed something, perform elimination in REG_NOTES. This is
3356 needed even when REPLACE is zero because a REG_DEAD note might refer
3357 to a register that we eliminate and could cause a different number
3358 of spill registers to be needed in the final reload pass than in
3360 if (val && REG_NOTES (insn) != 0)
3362 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3367 /* Loop through all elimination pairs.
3368 Recalculate the number not at initial offset.
3370 Compute the maximum offset (minimum offset if the stack does not
3371 grow downward) for each elimination pair. */
3374 update_eliminable_offsets (void)
3376 struct elim_table *ep;
3378 num_not_at_initial_offset = 0;
3379 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3381 ep->previous_offset = ep->offset;
3382 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3383 num_not_at_initial_offset++;
3387 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3388 replacement we currently believe is valid, mark it as not eliminable if X
3389 modifies DEST in any way other than by adding a constant integer to it.
3391 If DEST is the frame pointer, we do nothing because we assume that
3392 all assignments to the hard frame pointer are nonlocal gotos and are being
3393 done at a time when they are valid and do not disturb anything else.
3394 Some machines want to eliminate a fake argument pointer with either the
3395 frame or stack pointer. Assignments to the hard frame pointer must not
3396 prevent this elimination.
3398 Called via note_stores from reload before starting its passes to scan
3399 the insns of the function. */
3402 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3406 /* A SUBREG of a hard register here is just changing its mode. We should
3407 not see a SUBREG of an eliminable hard register, but check just in
3409 if (GET_CODE (dest) == SUBREG)
3410 dest = SUBREG_REG (dest);
3412 if (dest == hard_frame_pointer_rtx)
3415 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3416 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3417 && (GET_CODE (x) != SET
3418 || GET_CODE (SET_SRC (x)) != PLUS
3419 || XEXP (SET_SRC (x), 0) != dest
3420 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3422 reg_eliminate[i].can_eliminate_previous
3423 = reg_eliminate[i].can_eliminate = 0;
3428 /* Verify that the initial elimination offsets did not change since the
3429 last call to set_initial_elim_offsets. This is used to catch cases
3430 where something illegal happened during reload_as_needed that could
3431 cause incorrect code to be generated if we did not check for it. */
3434 verify_initial_elim_offsets (void)
3438 if (!num_eliminable)
3441 #ifdef ELIMINABLE_REGS
3443 struct elim_table *ep;
3445 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3447 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3448 if (t != ep->initial_offset)
3453 INITIAL_FRAME_POINTER_OFFSET (t);
3454 if (t != reg_eliminate[0].initial_offset)
3461 /* Reset all offsets on eliminable registers to their initial values. */
3464 set_initial_elim_offsets (void)
3466 struct elim_table *ep = reg_eliminate;
3468 #ifdef ELIMINABLE_REGS
3469 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3471 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3472 ep->previous_offset = ep->offset = ep->initial_offset;
3475 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3476 ep->previous_offset = ep->offset = ep->initial_offset;
3479 num_not_at_initial_offset = 0;
3482 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3485 set_initial_eh_label_offset (rtx label)
3487 set_label_offsets (label, NULL_RTX, 1);
3490 /* Initialize the known label offsets.
3491 Set a known offset for each forced label to be at the initial offset
3492 of each elimination. We do this because we assume that all
3493 computed jumps occur from a location where each elimination is
3494 at its initial offset.
3495 For all other labels, show that we don't know the offsets. */
3498 set_initial_label_offsets (void)
3501 memset (offsets_known_at, 0, num_labels);
3503 for (x = forced_labels; x; x = XEXP (x, 1))
3505 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3507 for_each_eh_label (set_initial_eh_label_offset);
3510 /* Set all elimination offsets to the known values for the code label given
3514 set_offsets_for_label (rtx insn)
3517 int label_nr = CODE_LABEL_NUMBER (insn);
3518 struct elim_table *ep;
3520 num_not_at_initial_offset = 0;
3521 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3523 ep->offset = ep->previous_offset
3524 = offsets_at[label_nr - first_label_num][i];
3525 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3526 num_not_at_initial_offset++;
3530 /* See if anything that happened changes which eliminations are valid.
3531 For example, on the SPARC, whether or not the frame pointer can
3532 be eliminated can depend on what registers have been used. We need
3533 not check some conditions again (such as flag_omit_frame_pointer)
3534 since they can't have changed. */
3537 update_eliminables (HARD_REG_SET *pset)
3539 int previous_frame_pointer_needed = frame_pointer_needed;
3540 struct elim_table *ep;
3542 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3543 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3544 #ifdef ELIMINABLE_REGS
3545 || ! CAN_ELIMINATE (ep->from, ep->to)
3548 ep->can_eliminate = 0;
3550 /* Look for the case where we have discovered that we can't replace
3551 register A with register B and that means that we will now be
3552 trying to replace register A with register C. This means we can
3553 no longer replace register C with register B and we need to disable
3554 such an elimination, if it exists. This occurs often with A == ap,
3555 B == sp, and C == fp. */
3557 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3559 struct elim_table *op;
3562 if (! ep->can_eliminate && ep->can_eliminate_previous)
3564 /* Find the current elimination for ep->from, if there is a
3566 for (op = reg_eliminate;
3567 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3568 if (op->from == ep->from && op->can_eliminate)
3574 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3576 for (op = reg_eliminate;
3577 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3578 if (op->from == new_to && op->to == ep->to)
3579 op->can_eliminate = 0;
3583 /* See if any registers that we thought we could eliminate the previous
3584 time are no longer eliminable. If so, something has changed and we
3585 must spill the register. Also, recompute the number of eliminable
3586 registers and see if the frame pointer is needed; it is if there is
3587 no elimination of the frame pointer that we can perform. */
3589 frame_pointer_needed = 1;
3590 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3592 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3593 && ep->to != HARD_FRAME_POINTER_REGNUM)
3594 frame_pointer_needed = 0;
3596 if (! ep->can_eliminate && ep->can_eliminate_previous)
3598 ep->can_eliminate_previous = 0;
3599 SET_HARD_REG_BIT (*pset, ep->from);
3604 /* If we didn't need a frame pointer last time, but we do now, spill
3605 the hard frame pointer. */
3606 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3607 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3610 /* Return true if X is used as the target register of an elimination. */
3613 elimination_target_reg_p (rtx x)
3615 struct elim_table *ep;
3617 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3618 if (ep->to_rtx == x && ep->can_eliminate)
3624 /* Initialize the table of registers to eliminate. */
3627 init_elim_table (void)
3629 struct elim_table *ep;
3630 #ifdef ELIMINABLE_REGS
3631 const struct elim_table_1 *ep1;
3635 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3637 /* Does this function require a frame pointer? */
3639 frame_pointer_needed = (! flag_omit_frame_pointer
3640 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3641 and restore sp for alloca. So we can't eliminate
3642 the frame pointer in that case. At some point,
3643 we should improve this by emitting the
3644 sp-adjusting insns for this case. */
3645 || (current_function_calls_alloca
3646 && EXIT_IGNORE_STACK)
3647 || current_function_accesses_prior_frames
3648 || FRAME_POINTER_REQUIRED);
3652 #ifdef ELIMINABLE_REGS
3653 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3654 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3656 ep->from = ep1->from;
3658 ep->can_eliminate = ep->can_eliminate_previous
3659 = (CAN_ELIMINATE (ep->from, ep->to)
3660 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3663 reg_eliminate[0].from = reg_eliminate_1[0].from;
3664 reg_eliminate[0].to = reg_eliminate_1[0].to;
3665 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3666 = ! frame_pointer_needed;
3669 /* Count the number of eliminable registers and build the FROM and TO
3670 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3671 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3672 We depend on this. */
3673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3675 num_eliminable += ep->can_eliminate;
3676 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3677 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3681 /* Kick all pseudos out of hard register REGNO.
3683 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3684 because we found we can't eliminate some register. In the case, no pseudos
3685 are allowed to be in the register, even if they are only in a block that
3686 doesn't require spill registers, unlike the case when we are spilling this
3687 hard reg to produce another spill register.
3689 Return nonzero if any pseudos needed to be kicked out. */
3692 spill_hard_reg (unsigned int regno, int cant_eliminate)
3698 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3699 regs_ever_live[regno] = 1;
3702 /* Spill every pseudo reg that was allocated to this reg
3703 or to something that overlaps this reg. */
3705 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3706 if (reg_renumber[i] >= 0
3707 && (unsigned int) reg_renumber[i] <= regno
3708 && ((unsigned int) reg_renumber[i]
3709 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3710 [PSEUDO_REGNO_MODE (i)]
3712 SET_REGNO_REG_SET (&spilled_pseudos, i);
3715 /* After find_reload_regs has been run for all insn that need reloads,
3716 and/or spill_hard_regs was called, this function is used to actually
3717 spill pseudo registers and try to reallocate them. It also sets up the
3718 spill_regs array for use by choose_reload_regs. */
3721 finish_spills (int global)
3723 struct insn_chain *chain;
3724 int something_changed = 0;
3726 reg_set_iterator rsi;
3728 /* Build the spill_regs array for the function. */
3729 /* If there are some registers still to eliminate and one of the spill regs
3730 wasn't ever used before, additional stack space may have to be
3731 allocated to store this register. Thus, we may have changed the offset
3732 between the stack and frame pointers, so mark that something has changed.
3734 One might think that we need only set VAL to 1 if this is a call-used
3735 register. However, the set of registers that must be saved by the
3736 prologue is not identical to the call-used set. For example, the
3737 register used by the call insn for the return PC is a call-used register,
3738 but must be saved by the prologue. */
3741 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3742 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3744 spill_reg_order[i] = n_spills;
3745 spill_regs[n_spills++] = i;
3746 if (num_eliminable && ! regs_ever_live[i])
3747 something_changed = 1;
3748 regs_ever_live[i] = 1;
3751 spill_reg_order[i] = -1;
3753 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3755 /* Record the current hard register the pseudo is allocated to in
3756 pseudo_previous_regs so we avoid reallocating it to the same
3757 hard reg in a later pass. */
3758 gcc_assert (reg_renumber[i] >= 0);
3760 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3761 /* Mark it as no longer having a hard register home. */
3762 reg_renumber[i] = -1;
3763 /* We will need to scan everything again. */
3764 something_changed = 1;
3767 /* Retry global register allocation if possible. */
3770 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3771 /* For every insn that needs reloads, set the registers used as spill
3772 regs in pseudo_forbidden_regs for every pseudo live across the
3774 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3776 EXECUTE_IF_SET_IN_REG_SET
3777 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3779 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3780 chain->used_spill_regs);
3782 EXECUTE_IF_SET_IN_REG_SET
3783 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3785 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3786 chain->used_spill_regs);
3790 /* Retry allocating the spilled pseudos. For each reg, merge the
3791 various reg sets that indicate which hard regs can't be used,
3792 and call retry_global_alloc.
3793 We change spill_pseudos here to only contain pseudos that did not
3794 get a new hard register. */
3795 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3796 if (reg_old_renumber[i] != reg_renumber[i])
3798 HARD_REG_SET forbidden;
3799 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3800 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3801 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3802 retry_global_alloc (i, forbidden);
3803 if (reg_renumber[i] >= 0)
3804 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3808 /* Fix up the register information in the insn chain.
3809 This involves deleting those of the spilled pseudos which did not get
3810 a new hard register home from the live_{before,after} sets. */
3811 for (chain = reload_insn_chain; chain; chain = chain->next)
3813 HARD_REG_SET used_by_pseudos;
3814 HARD_REG_SET used_by_pseudos2;
3816 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3817 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3819 /* Mark any unallocated hard regs as available for spills. That
3820 makes inheritance work somewhat better. */
3821 if (chain->need_reload)
3823 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3824 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3825 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3827 /* Save the old value for the sanity test below. */
3828 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3830 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3831 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3832 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3833 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3835 /* Make sure we only enlarge the set. */
3836 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3842 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3843 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3845 int regno = reg_renumber[i];
3846 if (reg_old_renumber[i] == regno)
3849 alter_reg (i, reg_old_renumber[i]);
3850 reg_old_renumber[i] = regno;
3854 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3856 fprintf (dump_file, " Register %d now in %d.\n\n",
3857 i, reg_renumber[i]);
3861 return something_changed;
3864 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3867 scan_paradoxical_subregs (rtx x)
3871 enum rtx_code code = GET_CODE (x);
3881 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3889 if (REG_P (SUBREG_REG (x))
3890 && (GET_MODE_SIZE (GET_MODE (x))
3891 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3892 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3893 = GET_MODE_SIZE (GET_MODE (x));
3900 fmt = GET_RTX_FORMAT (code);
3901 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3904 scan_paradoxical_subregs (XEXP (x, i));
3905 else if (fmt[i] == 'E')
3908 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3909 scan_paradoxical_subregs (XVECEXP (x, i, j));
3914 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3915 examine all of the reload insns between PREV and NEXT exclusive, and
3916 annotate all that may trap. */
3919 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3921 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3922 unsigned int trap_count;
3928 if (may_trap_p (PATTERN (insn)))
3932 remove_note (insn, note);
3936 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3937 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3941 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3945 /* Reload pseudo-registers into hard regs around each insn as needed.
3946 Additional register load insns are output before the insn that needs it
3947 and perhaps store insns after insns that modify the reloaded pseudo reg.
3949 reg_last_reload_reg and reg_reloaded_contents keep track of
3950 which registers are already available in reload registers.
3951 We update these for the reloads that we perform,
3952 as the insns are scanned. */
3955 reload_as_needed (int live_known)
3957 struct insn_chain *chain;
3958 #if defined (AUTO_INC_DEC)
3963 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3964 memset (spill_reg_store, 0, sizeof spill_reg_store);
3965 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3966 INIT_REG_SET (®_has_output_reload);
3967 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3968 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3970 set_initial_elim_offsets ();
3972 for (chain = reload_insn_chain; chain; chain = chain->next)
3975 rtx insn = chain->insn;
3976 rtx old_next = NEXT_INSN (insn);
3978 /* If we pass a label, copy the offsets from the label information
3979 into the current offsets of each elimination. */
3981 set_offsets_for_label (insn);
3983 else if (INSN_P (insn))
3985 regset_head regs_to_forget;
3986 INIT_REG_SET (®s_to_forget);
3987 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3989 /* If this is a USE and CLOBBER of a MEM, ensure that any
3990 references to eliminable registers have been removed. */
3992 if ((GET_CODE (PATTERN (insn)) == USE
3993 || GET_CODE (PATTERN (insn)) == CLOBBER)
3994 && MEM_P (XEXP (PATTERN (insn), 0)))
3995 XEXP (XEXP (PATTERN (insn), 0), 0)
3996 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3997 GET_MODE (XEXP (PATTERN (insn), 0)),
4000 /* If we need to do register elimination processing, do so.
4001 This might delete the insn, in which case we are done. */
4002 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4004 eliminate_regs_in_insn (insn, 1);
4007 update_eliminable_offsets ();
4008 CLEAR_REG_SET (®s_to_forget);
4013 /* If need_elim is nonzero but need_reload is zero, one might think
4014 that we could simply set n_reloads to 0. However, find_reloads
4015 could have done some manipulation of the insn (such as swapping
4016 commutative operands), and these manipulations are lost during
4017 the first pass for every insn that needs register elimination.
4018 So the actions of find_reloads must be redone here. */
4020 if (! chain->need_elim && ! chain->need_reload
4021 && ! chain->need_operand_change)
4023 /* First find the pseudo regs that must be reloaded for this insn.
4024 This info is returned in the tables reload_... (see reload.h).
4025 Also modify the body of INSN by substituting RELOAD
4026 rtx's for those pseudo regs. */
4029 CLEAR_REG_SET (®_has_output_reload);
4030 CLEAR_HARD_REG_SET (reg_is_output_reload);
4032 find_reloads (insn, 1, spill_indirect_levels, live_known,
4038 rtx next = NEXT_INSN (insn);
4041 prev = PREV_INSN (insn);
4043 /* Now compute which reload regs to reload them into. Perhaps
4044 reusing reload regs from previous insns, or else output
4045 load insns to reload them. Maybe output store insns too.
4046 Record the choices of reload reg in reload_reg_rtx. */
4047 choose_reload_regs (chain);
4049 /* Merge any reloads that we didn't combine for fear of
4050 increasing the number of spill registers needed but now
4051 discover can be safely merged. */
4052 if (SMALL_REGISTER_CLASSES)
4053 merge_assigned_reloads (insn);
4055 /* Generate the insns to reload operands into or out of
4056 their reload regs. */
4057 emit_reload_insns (chain);
4059 /* Substitute the chosen reload regs from reload_reg_rtx
4060 into the insn's body (or perhaps into the bodies of other
4061 load and store insn that we just made for reloading
4062 and that we moved the structure into). */
4063 subst_reloads (insn);
4065 /* Adjust the exception region notes for loads and stores. */
4066 if (flag_non_call_exceptions && !CALL_P (insn))
4067 fixup_eh_region_note (insn, prev, next);
4069 /* If this was an ASM, make sure that all the reload insns
4070 we have generated are valid. If not, give an error
4072 if (asm_noperands (PATTERN (insn)) >= 0)
4073 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4074 if (p != insn && INSN_P (p)
4075 && GET_CODE (PATTERN (p)) != USE
4076 && (recog_memoized (p) < 0
4077 || (extract_insn (p), ! constrain_operands (1))))
4079 error_for_asm (insn,
4080 "%<asm%> operand requires "
4081 "impossible reload");
4086 if (num_eliminable && chain->need_elim)
4087 update_eliminable_offsets ();
4089 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4090 is no longer validly lying around to save a future reload.
4091 Note that this does not detect pseudos that were reloaded
4092 for this insn in order to be stored in
4093 (obeying register constraints). That is correct; such reload
4094 registers ARE still valid. */
4095 forget_marked_reloads (®s_to_forget);
4096 CLEAR_REG_SET (®s_to_forget);
4098 /* There may have been CLOBBER insns placed after INSN. So scan
4099 between INSN and NEXT and use them to forget old reloads. */
4100 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4101 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4102 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4105 /* Likewise for regs altered by auto-increment in this insn.
4106 REG_INC notes have been changed by reloading:
4107 find_reloads_address_1 records substitutions for them,
4108 which have been performed by subst_reloads above. */
4109 for (i = n_reloads - 1; i >= 0; i--)
4111 rtx in_reg = rld[i].in_reg;
4114 enum rtx_code code = GET_CODE (in_reg);
4115 /* PRE_INC / PRE_DEC will have the reload register ending up
4116 with the same value as the stack slot, but that doesn't
4117 hold true for POST_INC / POST_DEC. Either we have to
4118 convert the memory access to a true POST_INC / POST_DEC,
4119 or we can't use the reload register for inheritance. */
4120 if ((code == POST_INC || code == POST_DEC)
4121 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4122 REGNO (rld[i].reg_rtx))
4123 /* Make sure it is the inc/dec pseudo, and not
4124 some other (e.g. output operand) pseudo. */
4125 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4126 == REGNO (XEXP (in_reg, 0))))
4129 rtx reload_reg = rld[i].reg_rtx;
4130 enum machine_mode mode = GET_MODE (reload_reg);
4134 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4136 /* We really want to ignore REG_INC notes here, so
4137 use PATTERN (p) as argument to reg_set_p . */
4138 if (reg_set_p (reload_reg, PATTERN (p)))
4140 n = count_occurrences (PATTERN (p), reload_reg, 0);
4145 n = validate_replace_rtx (reload_reg,
4146 gen_rtx_fmt_e (code,
4151 /* We must also verify that the constraints
4152 are met after the replacement. */
4155 n = constrain_operands (1);
4159 /* If the constraints were not met, then
4160 undo the replacement. */
4163 validate_replace_rtx (gen_rtx_fmt_e (code,
4176 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4178 /* Mark this as having an output reload so that the
4179 REG_INC processing code below won't invalidate
4180 the reload for inheritance. */
4181 SET_HARD_REG_BIT (reg_is_output_reload,
4182 REGNO (reload_reg));
4183 SET_REGNO_REG_SET (®_has_output_reload,
4184 REGNO (XEXP (in_reg, 0)));
4187 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4190 else if ((code == PRE_INC || code == PRE_DEC)
4191 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4192 REGNO (rld[i].reg_rtx))
4193 /* Make sure it is the inc/dec pseudo, and not
4194 some other (e.g. output operand) pseudo. */
4195 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4196 == REGNO (XEXP (in_reg, 0))))
4198 SET_HARD_REG_BIT (reg_is_output_reload,
4199 REGNO (rld[i].reg_rtx));
4200 SET_REGNO_REG_SET (®_has_output_reload,
4201 REGNO (XEXP (in_reg, 0)));
4205 /* If a pseudo that got a hard register is auto-incremented,
4206 we must purge records of copying it into pseudos without
4208 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4209 if (REG_NOTE_KIND (x) == REG_INC)
4211 /* See if this pseudo reg was reloaded in this insn.
4212 If so, its last-reload info is still valid
4213 because it is based on this insn's reload. */
4214 for (i = 0; i < n_reloads; i++)
4215 if (rld[i].out == XEXP (x, 0))
4219 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4223 /* A reload reg's contents are unknown after a label. */
4225 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4227 /* Don't assume a reload reg is still good after a call insn
4228 if it is a call-used reg, or if it contains a value that will
4229 be partially clobbered by the call. */
4230 else if (CALL_P (insn))
4232 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4233 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4238 free (reg_last_reload_reg);
4239 CLEAR_REG_SET (®_has_output_reload);
4242 /* Discard all record of any value reloaded from X,
4243 or reloaded in X from someplace else;
4244 unless X is an output reload reg of the current insn.
4246 X may be a hard reg (the reload reg)
4247 or it may be a pseudo reg that was reloaded from.
4249 When DATA is non-NULL just mark the registers in regset
4250 to be forgotten later. */
4253 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4258 regset regs = (regset) data;
4260 /* note_stores does give us subregs of hard regs,
4261 subreg_regno_offset requires a hard reg. */
4262 while (GET_CODE (x) == SUBREG)
4264 /* We ignore the subreg offset when calculating the regno,
4265 because we are using the entire underlying hard register
4275 if (regno >= FIRST_PSEUDO_REGISTER)
4281 nr = hard_regno_nregs[regno][GET_MODE (x)];
4282 /* Storing into a spilled-reg invalidates its contents.
4283 This can happen if a block-local pseudo is allocated to that reg
4284 and it wasn't spilled because this block's total need is 0.
4285 Then some insn might have an optional reload and use this reg. */
4287 for (i = 0; i < nr; i++)
4288 /* But don't do this if the reg actually serves as an output
4289 reload reg in the current instruction. */
4291 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4293 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4294 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4295 spill_reg_store[regno + i] = 0;
4301 SET_REGNO_REG_SET (regs, regno + nr);
4304 /* Since value of X has changed,
4305 forget any value previously copied from it. */
4308 /* But don't forget a copy if this is the output reload
4309 that establishes the copy's validity. */
4311 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4312 reg_last_reload_reg[regno + nr] = 0;
4316 /* Forget the reloads marked in regset by previous function. */
4318 forget_marked_reloads (regset regs)
4321 reg_set_iterator rsi;
4322 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4324 if (reg < FIRST_PSEUDO_REGISTER
4325 /* But don't do this if the reg actually serves as an output
4326 reload reg in the current instruction. */
4328 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4330 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4331 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4332 spill_reg_store[reg] = 0;
4335 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4336 reg_last_reload_reg[reg] = 0;
4340 /* The following HARD_REG_SETs indicate when each hard register is
4341 used for a reload of various parts of the current insn. */
4343 /* If reg is unavailable for all reloads. */
4344 static HARD_REG_SET reload_reg_unavailable;
4345 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4346 static HARD_REG_SET reload_reg_used;
4347 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4348 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4349 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4350 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4351 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4352 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4353 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4354 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4355 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4356 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4357 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4358 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4359 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4360 static HARD_REG_SET reload_reg_used_in_op_addr;
4361 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4362 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4363 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4364 static HARD_REG_SET reload_reg_used_in_insn;
4365 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4366 static HARD_REG_SET reload_reg_used_in_other_addr;
4368 /* If reg is in use as a reload reg for any sort of reload. */
4369 static HARD_REG_SET reload_reg_used_at_all;
4371 /* If reg is use as an inherited reload. We just mark the first register
4373 static HARD_REG_SET reload_reg_used_for_inherit;
4375 /* Records which hard regs are used in any way, either as explicit use or
4376 by being allocated to a pseudo during any point of the current insn. */
4377 static HARD_REG_SET reg_used_in_insn;
4379 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4380 TYPE. MODE is used to indicate how many consecutive regs are
4384 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4385 enum machine_mode mode)
4387 unsigned int nregs = hard_regno_nregs[regno][mode];
4390 for (i = regno; i < nregs + regno; i++)
4395 SET_HARD_REG_BIT (reload_reg_used, i);
4398 case RELOAD_FOR_INPUT_ADDRESS:
4399 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4402 case RELOAD_FOR_INPADDR_ADDRESS:
4403 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4406 case RELOAD_FOR_OUTPUT_ADDRESS:
4407 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4410 case RELOAD_FOR_OUTADDR_ADDRESS:
4411 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4414 case RELOAD_FOR_OPERAND_ADDRESS:
4415 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4418 case RELOAD_FOR_OPADDR_ADDR:
4419 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4422 case RELOAD_FOR_OTHER_ADDRESS:
4423 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4426 case RELOAD_FOR_INPUT:
4427 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4430 case RELOAD_FOR_OUTPUT:
4431 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4434 case RELOAD_FOR_INSN:
4435 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4439 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4443 /* Similarly, but show REGNO is no longer in use for a reload. */
4446 clear_reload_reg_in_use (unsigned int regno, int opnum,
4447 enum reload_type type, enum machine_mode mode)
4449 unsigned int nregs = hard_regno_nregs[regno][mode];
4450 unsigned int start_regno, end_regno, r;
4452 /* A complication is that for some reload types, inheritance might
4453 allow multiple reloads of the same types to share a reload register.
4454 We set check_opnum if we have to check only reloads with the same
4455 operand number, and check_any if we have to check all reloads. */
4456 int check_opnum = 0;
4458 HARD_REG_SET *used_in_set;
4463 used_in_set = &reload_reg_used;
4466 case RELOAD_FOR_INPUT_ADDRESS:
4467 used_in_set = &reload_reg_used_in_input_addr[opnum];
4470 case RELOAD_FOR_INPADDR_ADDRESS:
4472 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4475 case RELOAD_FOR_OUTPUT_ADDRESS:
4476 used_in_set = &reload_reg_used_in_output_addr[opnum];
4479 case RELOAD_FOR_OUTADDR_ADDRESS:
4481 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4484 case RELOAD_FOR_OPERAND_ADDRESS:
4485 used_in_set = &reload_reg_used_in_op_addr;
4488 case RELOAD_FOR_OPADDR_ADDR:
4490 used_in_set = &reload_reg_used_in_op_addr_reload;
4493 case RELOAD_FOR_OTHER_ADDRESS:
4494 used_in_set = &reload_reg_used_in_other_addr;
4498 case RELOAD_FOR_INPUT:
4499 used_in_set = &reload_reg_used_in_input[opnum];
4502 case RELOAD_FOR_OUTPUT:
4503 used_in_set = &reload_reg_used_in_output[opnum];
4506 case RELOAD_FOR_INSN:
4507 used_in_set = &reload_reg_used_in_insn;
4512 /* We resolve conflicts with remaining reloads of the same type by
4513 excluding the intervals of reload registers by them from the
4514 interval of freed reload registers. Since we only keep track of
4515 one set of interval bounds, we might have to exclude somewhat
4516 more than what would be necessary if we used a HARD_REG_SET here.
4517 But this should only happen very infrequently, so there should
4518 be no reason to worry about it. */
4520 start_regno = regno;
4521 end_regno = regno + nregs;
4522 if (check_opnum || check_any)
4524 for (i = n_reloads - 1; i >= 0; i--)
4526 if (rld[i].when_needed == type
4527 && (check_any || rld[i].opnum == opnum)
4530 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4531 unsigned int conflict_end
4533 + hard_regno_nregs[conflict_start][rld[i].mode]);
4535 /* If there is an overlap with the first to-be-freed register,
4536 adjust the interval start. */
4537 if (conflict_start <= start_regno && conflict_end > start_regno)
4538 start_regno = conflict_end;
4539 /* Otherwise, if there is a conflict with one of the other
4540 to-be-freed registers, adjust the interval end. */
4541 if (conflict_start > start_regno && conflict_start < end_regno)
4542 end_regno = conflict_start;
4547 for (r = start_regno; r < end_regno; r++)
4548 CLEAR_HARD_REG_BIT (*used_in_set, r);
4551 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4552 specified by OPNUM and TYPE. */
4555 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4559 /* In use for a RELOAD_OTHER means it's not available for anything. */
4560 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4561 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4567 /* In use for anything means we can't use it for RELOAD_OTHER. */
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4574 for (i = 0; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4578 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4585 case RELOAD_FOR_INPUT:
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4590 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4593 /* If it is used for some other input, can't use it. */
4594 for (i = 0; i < reload_n_operands; i++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4598 /* If it is used in a later operand's address, can't use it. */
4599 for (i = opnum + 1; i < reload_n_operands; i++)
4600 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4606 case RELOAD_FOR_INPUT_ADDRESS:
4607 /* Can't use a register if it is used for an input address for this
4608 operand or used as an input in an earlier one. */
4609 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4613 for (i = 0; i < opnum; i++)
4614 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4619 case RELOAD_FOR_INPADDR_ADDRESS:
4620 /* Can't use a register if it is used for an input address
4621 for this operand or used as an input in an earlier
4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4626 for (i = 0; i < opnum; i++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4632 case RELOAD_FOR_OUTPUT_ADDRESS:
4633 /* Can't use a register if it is used for an output address for this
4634 operand or used as an output in this or a later operand. Note
4635 that multiple output operands are emitted in reverse order, so
4636 the conflicting ones are those with lower indices. */
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4640 for (i = 0; i <= opnum; i++)
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4646 case RELOAD_FOR_OUTADDR_ADDRESS:
4647 /* Can't use a register if it is used for an output address
4648 for this operand or used as an output in this or a
4649 later operand. Note that multiple output operands are
4650 emitted in reverse order, so the conflicting ones are
4651 those with lower indices. */
4652 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4655 for (i = 0; i <= opnum; i++)
4656 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4661 case RELOAD_FOR_OPERAND_ADDRESS:
4662 for (i = 0; i < reload_n_operands; i++)
4663 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4666 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4667 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4669 case RELOAD_FOR_OPADDR_ADDR:
4670 for (i = 0; i < reload_n_operands; i++)
4671 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4674 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4676 case RELOAD_FOR_OUTPUT:
4677 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4678 outputs, or an operand address for this or an earlier output.
4679 Note that multiple output operands are emitted in reverse order,
4680 so the conflicting ones are those with higher indices. */
4681 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4684 for (i = 0; i < reload_n_operands; i++)
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4688 for (i = opnum; i < reload_n_operands; i++)
4689 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4690 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4695 case RELOAD_FOR_INSN:
4696 for (i = 0; i < reload_n_operands; i++)
4697 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4698 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4701 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4702 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4704 case RELOAD_FOR_OTHER_ADDRESS:
4705 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4712 /* Return 1 if the value in reload reg REGNO, as used by a reload
4713 needed for the part of the insn specified by OPNUM and TYPE,
4714 is still available in REGNO at the end of the insn.
4716 We can assume that the reload reg was already tested for availability
4717 at the time it is needed, and we should not check this again,
4718 in case the reg has already been marked in use. */
4721 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4728 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4729 its value must reach the end. */
4732 /* If this use is for part of the insn,
4733 its value reaches if no subsequent part uses the same register.
4734 Just like the above function, don't try to do this with lots
4737 case RELOAD_FOR_OTHER_ADDRESS:
4738 /* Here we check for everything else, since these don't conflict
4739 with anything else and everything comes later. */
4741 for (i = 0; i < reload_n_operands; i++)
4742 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4743 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4744 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4745 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4746 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4747 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4750 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4751 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4752 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4753 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4755 case RELOAD_FOR_INPUT_ADDRESS:
4756 case RELOAD_FOR_INPADDR_ADDRESS:
4757 /* Similar, except that we check only for this and subsequent inputs
4758 and the address of only subsequent inputs and we do not need
4759 to check for RELOAD_OTHER objects since they are known not to
4762 for (i = opnum; i < reload_n_operands; i++)
4763 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4766 for (i = opnum + 1; i < reload_n_operands; i++)
4767 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4768 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4771 for (i = 0; i < reload_n_operands; i++)
4772 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4773 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4774 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4777 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4780 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4781 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4782 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4784 case RELOAD_FOR_INPUT:
4785 /* Similar to input address, except we start at the next operand for
4786 both input and input address and we do not check for
4787 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4790 for (i = opnum + 1; i < reload_n_operands; i++)
4791 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4792 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4793 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4796 /* ... fall through ... */
4798 case RELOAD_FOR_OPERAND_ADDRESS:
4799 /* Check outputs and their addresses. */
4801 for (i = 0; i < reload_n_operands; i++)
4802 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4803 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4804 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4807 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4809 case RELOAD_FOR_OPADDR_ADDR:
4810 for (i = 0; i < reload_n_operands; i++)
4811 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4813 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4816 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4817 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4818 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4820 case RELOAD_FOR_INSN:
4821 /* These conflict with other outputs with RELOAD_OTHER. So
4822 we need only check for output addresses. */
4824 opnum = reload_n_operands;
4826 /* ... fall through ... */
4828 case RELOAD_FOR_OUTPUT:
4829 case RELOAD_FOR_OUTPUT_ADDRESS:
4830 case RELOAD_FOR_OUTADDR_ADDRESS:
4831 /* We already know these can't conflict with a later output. So the
4832 only thing to check are later output addresses.
4833 Note that multiple output operands are emitted in reverse order,
4834 so the conflicting ones are those with lower indices. */
4835 for (i = 0; i < opnum; i++)
4836 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4837 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4848 /* Returns whether R1 and R2 are uniquely chained: the value of one
4849 is used by the other, and that value is not used by any other
4850 reload for this insn. This is used to partially undo the decision
4851 made in find_reloads when in the case of multiple
4852 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4853 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4854 reloads. This code tries to avoid the conflict created by that
4855 change. It might be cleaner to explicitly keep track of which
4856 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4857 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4858 this after the fact. */
4860 reloads_unique_chain_p (int r1, int r2)
4864 /* We only check input reloads. */
4865 if (! rld[r1].in || ! rld[r2].in)
4868 /* Avoid anything with output reloads. */
4869 if (rld[r1].out || rld[r2].out)
4872 /* "chained" means one reload is a component of the other reload,
4873 not the same as the other reload. */
4874 if (rld[r1].opnum != rld[r2].opnum
4875 || rtx_equal_p (rld[r1].in, rld[r2].in)
4876 || rld[r1].optional || rld[r2].optional
4877 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4878 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4881 for (i = 0; i < n_reloads; i ++)
4882 /* Look for input reloads that aren't our two */
4883 if (i != r1 && i != r2 && rld[i].in)
4885 /* If our reload is mentioned at all, it isn't a simple chain. */
4886 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4892 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4895 This function uses the same algorithm as reload_reg_free_p above. */
4898 reloads_conflict (int r1, int r2)
4900 enum reload_type r1_type = rld[r1].when_needed;
4901 enum reload_type r2_type = rld[r2].when_needed;
4902 int r1_opnum = rld[r1].opnum;
4903 int r2_opnum = rld[r2].opnum;
4905 /* RELOAD_OTHER conflicts with everything. */
4906 if (r2_type == RELOAD_OTHER)
4909 /* Otherwise, check conflicts differently for each type. */
4913 case RELOAD_FOR_INPUT:
4914 return (r2_type == RELOAD_FOR_INSN
4915 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4916 || r2_type == RELOAD_FOR_OPADDR_ADDR
4917 || r2_type == RELOAD_FOR_INPUT
4918 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4919 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4920 && r2_opnum > r1_opnum));
4922 case RELOAD_FOR_INPUT_ADDRESS:
4923 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4924 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4926 case RELOAD_FOR_INPADDR_ADDRESS:
4927 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4928 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4930 case RELOAD_FOR_OUTPUT_ADDRESS:
4931 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4932 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4934 case RELOAD_FOR_OUTADDR_ADDRESS:
4935 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4936 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4938 case RELOAD_FOR_OPERAND_ADDRESS:
4939 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4940 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
4941 && !reloads_unique_chain_p (r1, r2)));
4943 case RELOAD_FOR_OPADDR_ADDR:
4944 return (r2_type == RELOAD_FOR_INPUT
4945 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4947 case RELOAD_FOR_OUTPUT:
4948 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4949 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4950 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4951 && r2_opnum >= r1_opnum));
4953 case RELOAD_FOR_INSN:
4954 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4955 || r2_type == RELOAD_FOR_INSN
4956 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4958 case RELOAD_FOR_OTHER_ADDRESS:
4959 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4969 /* Indexed by reload number, 1 if incoming value
4970 inherited from previous insns. */
4971 static char reload_inherited[MAX_RELOADS];
4973 /* For an inherited reload, this is the insn the reload was inherited from,
4974 if we know it. Otherwise, this is 0. */
4975 static rtx reload_inheritance_insn[MAX_RELOADS];
4977 /* If nonzero, this is a place to get the value of the reload,
4978 rather than using reload_in. */
4979 static rtx reload_override_in[MAX_RELOADS];
4981 /* For each reload, the hard register number of the register used,
4982 or -1 if we did not need a register for this reload. */
4983 static int reload_spill_index[MAX_RELOADS];
4985 /* Subroutine of free_for_value_p, used to check a single register.
4986 START_REGNO is the starting regno of the full reload register
4987 (possibly comprising multiple hard registers) that we are considering. */
4990 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4991 enum reload_type type, rtx value, rtx out,
4992 int reloadnum, int ignore_address_reloads)
4995 /* Set if we see an input reload that must not share its reload register
4996 with any new earlyclobber, but might otherwise share the reload
4997 register with an output or input-output reload. */
4998 int check_earlyclobber = 0;
5002 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5005 if (out == const0_rtx)
5011 /* We use some pseudo 'time' value to check if the lifetimes of the
5012 new register use would overlap with the one of a previous reload
5013 that is not read-only or uses a different value.
5014 The 'time' used doesn't have to be linear in any shape or form, just
5016 Some reload types use different 'buckets' for each operand.
5017 So there are MAX_RECOG_OPERANDS different time values for each
5019 We compute TIME1 as the time when the register for the prospective
5020 new reload ceases to be live, and TIME2 for each existing
5021 reload as the time when that the reload register of that reload
5023 Where there is little to be gained by exact lifetime calculations,
5024 we just make conservative assumptions, i.e. a longer lifetime;
5025 this is done in the 'default:' cases. */
5028 case RELOAD_FOR_OTHER_ADDRESS:
5029 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5030 time1 = copy ? 0 : 1;
5033 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5035 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5036 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5037 respectively, to the time values for these, we get distinct time
5038 values. To get distinct time values for each operand, we have to
5039 multiply opnum by at least three. We round that up to four because
5040 multiply by four is often cheaper. */
5041 case RELOAD_FOR_INPADDR_ADDRESS:
5042 time1 = opnum * 4 + 2;
5044 case RELOAD_FOR_INPUT_ADDRESS:
5045 time1 = opnum * 4 + 3;
5047 case RELOAD_FOR_INPUT:
5048 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5049 executes (inclusive). */
5050 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5052 case RELOAD_FOR_OPADDR_ADDR:
5054 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5055 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5057 case RELOAD_FOR_OPERAND_ADDRESS:
5058 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5060 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5062 case RELOAD_FOR_OUTADDR_ADDRESS:
5063 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5065 case RELOAD_FOR_OUTPUT_ADDRESS:
5066 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5069 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5072 for (i = 0; i < n_reloads; i++)
5074 rtx reg = rld[i].reg_rtx;
5075 if (reg && REG_P (reg)
5076 && ((unsigned) regno - true_regnum (reg)
5077 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5080 rtx other_input = rld[i].in;
5082 /* If the other reload loads the same input value, that
5083 will not cause a conflict only if it's loading it into
5084 the same register. */
5085 if (true_regnum (reg) != start_regno)
5086 other_input = NULL_RTX;
5087 if (! other_input || ! rtx_equal_p (other_input, value)
5088 || rld[i].out || out)
5091 switch (rld[i].when_needed)
5093 case RELOAD_FOR_OTHER_ADDRESS:
5096 case RELOAD_FOR_INPADDR_ADDRESS:
5097 /* find_reloads makes sure that a
5098 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5099 by at most one - the first -
5100 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5101 address reload is inherited, the address address reload
5102 goes away, so we can ignore this conflict. */
5103 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5104 && ignore_address_reloads
5105 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5106 Then the address address is still needed to store
5107 back the new address. */
5108 && ! rld[reloadnum].out)
5110 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5111 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5113 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5114 && ignore_address_reloads
5115 /* Unless we are reloading an auto_inc expression. */
5116 && ! rld[reloadnum].out)
5118 time2 = rld[i].opnum * 4 + 2;
5120 case RELOAD_FOR_INPUT_ADDRESS:
5121 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5122 && ignore_address_reloads
5123 && ! rld[reloadnum].out)
5125 time2 = rld[i].opnum * 4 + 3;
5127 case RELOAD_FOR_INPUT:
5128 time2 = rld[i].opnum * 4 + 4;
5129 check_earlyclobber = 1;
5131 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5132 == MAX_RECOG_OPERAND * 4 */
5133 case RELOAD_FOR_OPADDR_ADDR:
5134 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5135 && ignore_address_reloads
5136 && ! rld[reloadnum].out)
5138 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5140 case RELOAD_FOR_OPERAND_ADDRESS:
5141 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5142 check_earlyclobber = 1;
5144 case RELOAD_FOR_INSN:
5145 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5147 case RELOAD_FOR_OUTPUT:
5148 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5149 instruction is executed. */
5150 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5152 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5153 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5155 case RELOAD_FOR_OUTADDR_ADDRESS:
5156 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5157 && ignore_address_reloads
5158 && ! rld[reloadnum].out)
5160 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5162 case RELOAD_FOR_OUTPUT_ADDRESS:
5163 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5166 /* If there is no conflict in the input part, handle this
5167 like an output reload. */
5168 if (! rld[i].in || rtx_equal_p (other_input, value))
5170 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5171 /* Earlyclobbered outputs must conflict with inputs. */
5172 if (earlyclobber_operand_p (rld[i].out))
5173 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5178 /* RELOAD_OTHER might be live beyond instruction execution,
5179 but this is not obvious when we set time2 = 1. So check
5180 here if there might be a problem with the new reload
5181 clobbering the register used by the RELOAD_OTHER. */
5189 && (! rld[i].in || rld[i].out
5190 || ! rtx_equal_p (other_input, value)))
5191 || (out && rld[reloadnum].out_reg
5192 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5198 /* Earlyclobbered outputs must conflict with inputs. */
5199 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5205 /* Return 1 if the value in reload reg REGNO, as used by a reload
5206 needed for the part of the insn specified by OPNUM and TYPE,
5207 may be used to load VALUE into it.
5209 MODE is the mode in which the register is used, this is needed to
5210 determine how many hard regs to test.
5212 Other read-only reloads with the same value do not conflict
5213 unless OUT is nonzero and these other reloads have to live while
5214 output reloads live.
5215 If OUT is CONST0_RTX, this is a special case: it means that the
5216 test should not be for using register REGNO as reload register, but
5217 for copying from register REGNO into the reload register.
5219 RELOADNUM is the number of the reload we want to load this value for;
5220 a reload does not conflict with itself.
5222 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5223 reloads that load an address for the very reload we are considering.
5225 The caller has to make sure that there is no conflict with the return
5229 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5230 enum reload_type type, rtx value, rtx out, int reloadnum,
5231 int ignore_address_reloads)
5233 int nregs = hard_regno_nregs[regno][mode];
5235 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5236 value, out, reloadnum,
5237 ignore_address_reloads))
5242 /* Return nonzero if the rtx X is invariant over the current function. */
5243 /* ??? Actually, the places where we use this expect exactly what is
5244 tested here, and not everything that is function invariant. In
5245 particular, the frame pointer and arg pointer are special cased;
5246 pic_offset_table_rtx is not, and we must not spill these things to
5250 function_invariant_p (rtx x)
5254 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5256 if (GET_CODE (x) == PLUS
5257 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5258 && CONSTANT_P (XEXP (x, 1)))
5263 /* Determine whether the reload reg X overlaps any rtx'es used for
5264 overriding inheritance. Return nonzero if so. */
5267 conflicts_with_override (rtx x)
5270 for (i = 0; i < n_reloads; i++)
5271 if (reload_override_in[i]
5272 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5277 /* Give an error message saying we failed to find a reload for INSN,
5278 and clear out reload R. */
5280 failed_reload (rtx insn, int r)
5282 if (asm_noperands (PATTERN (insn)) < 0)
5283 /* It's the compiler's fault. */
5284 fatal_insn ("could not find a spill register", insn);
5286 /* It's the user's fault; the operand's mode and constraint
5287 don't match. Disable this reload so we don't crash in final. */
5288 error_for_asm (insn,
5289 "%<asm%> operand constraint incompatible with operand size");
5293 rld[r].optional = 1;
5294 rld[r].secondary_p = 1;
5297 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5298 for reload R. If it's valid, get an rtx for it. Return nonzero if
5301 set_reload_reg (int i, int r)
5304 rtx reg = spill_reg_rtx[i];
5306 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5307 spill_reg_rtx[i] = reg
5308 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5310 regno = true_regnum (reg);
5312 /* Detect when the reload reg can't hold the reload mode.
5313 This used to be one `if', but Sequent compiler can't handle that. */
5314 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5316 enum machine_mode test_mode = VOIDmode;
5318 test_mode = GET_MODE (rld[r].in);
5319 /* If rld[r].in has VOIDmode, it means we will load it
5320 in whatever mode the reload reg has: to wit, rld[r].mode.
5321 We have already tested that for validity. */
5322 /* Aside from that, we need to test that the expressions
5323 to reload from or into have modes which are valid for this
5324 reload register. Otherwise the reload insns would be invalid. */
5325 if (! (rld[r].in != 0 && test_mode != VOIDmode
5326 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5327 if (! (rld[r].out != 0
5328 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5330 /* The reg is OK. */
5333 /* Mark as in use for this insn the reload regs we use
5335 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5336 rld[r].when_needed, rld[r].mode);
5338 rld[r].reg_rtx = reg;
5339 reload_spill_index[r] = spill_regs[i];
5346 /* Find a spill register to use as a reload register for reload R.
5347 LAST_RELOAD is nonzero if this is the last reload for the insn being
5350 Set rld[R].reg_rtx to the register allocated.
5352 We return 1 if successful, or 0 if we couldn't find a spill reg and
5353 we didn't change anything. */
5356 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5361 /* If we put this reload ahead, thinking it is a group,
5362 then insist on finding a group. Otherwise we can grab a
5363 reg that some other reload needs.
5364 (That can happen when we have a 68000 DATA_OR_FP_REG
5365 which is a group of data regs or one fp reg.)
5366 We need not be so restrictive if there are no more reloads
5369 ??? Really it would be nicer to have smarter handling
5370 for that kind of reg class, where a problem like this is normal.
5371 Perhaps those classes should be avoided for reloading
5372 by use of more alternatives. */
5374 int force_group = rld[r].nregs > 1 && ! last_reload;
5376 /* If we want a single register and haven't yet found one,
5377 take any reg in the right class and not in use.
5378 If we want a consecutive group, here is where we look for it.
5380 We use two passes so we can first look for reload regs to
5381 reuse, which are already in use for other reloads in this insn,
5382 and only then use additional registers.
5383 I think that maximizing reuse is needed to make sure we don't
5384 run out of reload regs. Suppose we have three reloads, and
5385 reloads A and B can share regs. These need two regs.
5386 Suppose A and B are given different regs.
5387 That leaves none for C. */
5388 for (pass = 0; pass < 2; pass++)
5390 /* I is the index in spill_regs.
5391 We advance it round-robin between insns to use all spill regs
5392 equally, so that inherited reloads have a chance
5393 of leapfrogging each other. */
5397 for (count = 0; count < n_spills; count++)
5399 int class = (int) rld[r].class;
5405 regnum = spill_regs[i];
5407 if ((reload_reg_free_p (regnum, rld[r].opnum,
5410 /* We check reload_reg_used to make sure we
5411 don't clobber the return register. */
5412 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5413 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5414 rld[r].when_needed, rld[r].in,
5416 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5417 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5418 /* Look first for regs to share, then for unshared. But
5419 don't share regs used for inherited reloads; they are
5420 the ones we want to preserve. */
5422 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5424 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5427 int nr = hard_regno_nregs[regnum][rld[r].mode];
5428 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5429 (on 68000) got us two FP regs. If NR is 1,
5430 we would reject both of them. */
5433 /* If we need only one reg, we have already won. */
5436 /* But reject a single reg if we demand a group. */
5441 /* Otherwise check that as many consecutive regs as we need
5442 are available here. */
5445 int regno = regnum + nr - 1;
5446 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5447 && spill_reg_order[regno] >= 0
5448 && reload_reg_free_p (regno, rld[r].opnum,
5449 rld[r].when_needed)))
5458 /* If we found something on pass 1, omit pass 2. */
5459 if (count < n_spills)
5463 /* We should have found a spill register by now. */
5464 if (count >= n_spills)
5467 /* I is the index in SPILL_REG_RTX of the reload register we are to
5468 allocate. Get an rtx for it and find its register number. */
5470 return set_reload_reg (i, r);
5473 /* Initialize all the tables needed to allocate reload registers.
5474 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5475 is the array we use to restore the reg_rtx field for every reload. */
5478 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5482 for (i = 0; i < n_reloads; i++)
5483 rld[i].reg_rtx = save_reload_reg_rtx[i];
5485 memset (reload_inherited, 0, MAX_RELOADS);
5486 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5487 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5489 CLEAR_HARD_REG_SET (reload_reg_used);
5490 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5491 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5492 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5493 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5494 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5496 CLEAR_HARD_REG_SET (reg_used_in_insn);
5499 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5500 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5501 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5502 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5503 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5504 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5507 for (i = 0; i < reload_n_operands; i++)
5509 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5510 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5511 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5512 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5513 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5514 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5517 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5519 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5521 for (i = 0; i < n_reloads; i++)
5522 /* If we have already decided to use a certain register,
5523 don't use it in another way. */
5525 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5526 rld[i].when_needed, rld[i].mode);
5529 /* Assign hard reg targets for the pseudo-registers we must reload
5530 into hard regs for this insn.
5531 Also output the instructions to copy them in and out of the hard regs.
5533 For machines with register classes, we are responsible for
5534 finding a reload reg in the proper class. */
5537 choose_reload_regs (struct insn_chain *chain)
5539 rtx insn = chain->insn;
5541 unsigned int max_group_size = 1;
5542 enum reg_class group_class = NO_REGS;
5543 int pass, win, inheritance;
5545 rtx save_reload_reg_rtx[MAX_RELOADS];
5547 /* In order to be certain of getting the registers we need,
5548 we must sort the reloads into order of increasing register class.
5549 Then our grabbing of reload registers will parallel the process
5550 that provided the reload registers.
5552 Also note whether any of the reloads wants a consecutive group of regs.
5553 If so, record the maximum size of the group desired and what
5554 register class contains all the groups needed by this insn. */
5556 for (j = 0; j < n_reloads; j++)
5558 reload_order[j] = j;
5559 reload_spill_index[j] = -1;
5561 if (rld[j].nregs > 1)
5563 max_group_size = MAX (rld[j].nregs, max_group_size);
5565 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5568 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5572 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5574 /* If -O, try first with inheritance, then turning it off.
5575 If not -O, don't do inheritance.
5576 Using inheritance when not optimizing leads to paradoxes
5577 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5578 because one side of the comparison might be inherited. */
5580 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5582 choose_reload_regs_init (chain, save_reload_reg_rtx);
5584 /* Process the reloads in order of preference just found.
5585 Beyond this point, subregs can be found in reload_reg_rtx.
5587 This used to look for an existing reloaded home for all of the
5588 reloads, and only then perform any new reloads. But that could lose
5589 if the reloads were done out of reg-class order because a later
5590 reload with a looser constraint might have an old home in a register
5591 needed by an earlier reload with a tighter constraint.
5593 To solve this, we make two passes over the reloads, in the order
5594 described above. In the first pass we try to inherit a reload
5595 from a previous insn. If there is a later reload that needs a
5596 class that is a proper subset of the class being processed, we must
5597 also allocate a spill register during the first pass.
5599 Then make a second pass over the reloads to allocate any reloads
5600 that haven't been given registers yet. */
5602 for (j = 0; j < n_reloads; j++)
5604 int r = reload_order[j];
5605 rtx search_equiv = NULL_RTX;
5607 /* Ignore reloads that got marked inoperative. */
5608 if (rld[r].out == 0 && rld[r].in == 0
5609 && ! rld[r].secondary_p)
5612 /* If find_reloads chose to use reload_in or reload_out as a reload
5613 register, we don't need to chose one. Otherwise, try even if it
5614 found one since we might save an insn if we find the value lying
5616 Try also when reload_in is a pseudo without a hard reg. */
5617 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5618 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5619 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5620 && !MEM_P (rld[r].in)
5621 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5624 #if 0 /* No longer needed for correct operation.
5625 It might give better code, or might not; worth an experiment? */
5626 /* If this is an optional reload, we can't inherit from earlier insns
5627 until we are sure that any non-optional reloads have been allocated.
5628 The following code takes advantage of the fact that optional reloads
5629 are at the end of reload_order. */
5630 if (rld[r].optional != 0)
5631 for (i = 0; i < j; i++)
5632 if ((rld[reload_order[i]].out != 0
5633 || rld[reload_order[i]].in != 0
5634 || rld[reload_order[i]].secondary_p)
5635 && ! rld[reload_order[i]].optional
5636 && rld[reload_order[i]].reg_rtx == 0)
5637 allocate_reload_reg (chain, reload_order[i], 0);
5640 /* First see if this pseudo is already available as reloaded
5641 for a previous insn. We cannot try to inherit for reloads
5642 that are smaller than the maximum number of registers needed
5643 for groups unless the register we would allocate cannot be used
5646 We could check here to see if this is a secondary reload for
5647 an object that is already in a register of the desired class.
5648 This would avoid the need for the secondary reload register.
5649 But this is complex because we can't easily determine what
5650 objects might want to be loaded via this reload. So let a
5651 register be allocated here. In `emit_reload_insns' we suppress
5652 one of the loads in the case described above. */
5658 enum machine_mode mode = VOIDmode;
5662 else if (REG_P (rld[r].in))
5664 regno = REGNO (rld[r].in);
5665 mode = GET_MODE (rld[r].in);
5667 else if (REG_P (rld[r].in_reg))
5669 regno = REGNO (rld[r].in_reg);
5670 mode = GET_MODE (rld[r].in_reg);
5672 else if (GET_CODE (rld[r].in_reg) == SUBREG
5673 && REG_P (SUBREG_REG (rld[r].in_reg)))
5675 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5676 if (regno < FIRST_PSEUDO_REGISTER)
5677 regno = subreg_regno (rld[r].in_reg);
5679 byte = SUBREG_BYTE (rld[r].in_reg);
5680 mode = GET_MODE (rld[r].in_reg);
5683 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5684 && REG_P (XEXP (rld[r].in_reg, 0)))
5686 regno = REGNO (XEXP (rld[r].in_reg, 0));
5687 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5688 rld[r].out = rld[r].in;
5692 /* This won't work, since REGNO can be a pseudo reg number.
5693 Also, it takes much more hair to keep track of all the things
5694 that can invalidate an inherited reload of part of a pseudoreg. */
5695 else if (GET_CODE (rld[r].in) == SUBREG
5696 && REG_P (SUBREG_REG (rld[r].in)))
5697 regno = subreg_regno (rld[r].in);
5701 && reg_last_reload_reg[regno] != 0
5702 #ifdef CANNOT_CHANGE_MODE_CLASS
5703 /* Verify that the register it's in can be used in
5705 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5706 GET_MODE (reg_last_reload_reg[regno]),
5711 enum reg_class class = rld[r].class, last_class;
5712 rtx last_reg = reg_last_reload_reg[regno];
5713 enum machine_mode need_mode;
5715 i = REGNO (last_reg);
5716 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5717 last_class = REGNO_REG_CLASS (i);
5723 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5724 + byte * BITS_PER_UNIT,
5725 GET_MODE_CLASS (mode));
5727 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5728 >= GET_MODE_SIZE (need_mode))
5729 && reg_reloaded_contents[i] == regno
5730 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5731 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5732 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5733 /* Even if we can't use this register as a reload
5734 register, we might use it for reload_override_in,
5735 if copying it to the desired class is cheap
5737 || ((REGISTER_MOVE_COST (mode, last_class, class)
5738 < MEMORY_MOVE_COST (mode, class, 1))
5739 && (secondary_reload_class (1, class, mode,
5742 #ifdef SECONDARY_MEMORY_NEEDED
5743 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5748 && (rld[r].nregs == max_group_size
5749 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5751 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5752 rld[r].when_needed, rld[r].in,
5755 /* If a group is needed, verify that all the subsequent
5756 registers still have their values intact. */
5757 int nr = hard_regno_nregs[i][rld[r].mode];
5760 for (k = 1; k < nr; k++)
5761 if (reg_reloaded_contents[i + k] != regno
5762 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5770 last_reg = (GET_MODE (last_reg) == mode
5771 ? last_reg : gen_rtx_REG (mode, i));
5774 for (k = 0; k < nr; k++)
5775 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5778 /* We found a register that contains the
5779 value we need. If this register is the
5780 same as an `earlyclobber' operand of the
5781 current insn, just mark it as a place to
5782 reload from since we can't use it as the
5783 reload register itself. */
5785 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5786 if (reg_overlap_mentioned_for_reload_p
5787 (reg_last_reload_reg[regno],
5788 reload_earlyclobbers[i1]))
5791 if (i1 != n_earlyclobbers
5792 || ! (free_for_value_p (i, rld[r].mode,
5794 rld[r].when_needed, rld[r].in,
5796 /* Don't use it if we'd clobber a pseudo reg. */
5797 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5799 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5800 /* Don't clobber the frame pointer. */
5801 || (i == HARD_FRAME_POINTER_REGNUM
5802 && frame_pointer_needed
5804 /* Don't really use the inherited spill reg
5805 if we need it wider than we've got it. */
5806 || (GET_MODE_SIZE (rld[r].mode)
5807 > GET_MODE_SIZE (mode))
5810 /* If find_reloads chose reload_out as reload
5811 register, stay with it - that leaves the
5812 inherited register for subsequent reloads. */
5813 || (rld[r].out && rld[r].reg_rtx
5814 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5816 if (! rld[r].optional)
5818 reload_override_in[r] = last_reg;
5819 reload_inheritance_insn[r]
5820 = reg_reloaded_insn[i];
5826 /* We can use this as a reload reg. */
5827 /* Mark the register as in use for this part of
5829 mark_reload_reg_in_use (i,
5833 rld[r].reg_rtx = last_reg;
5834 reload_inherited[r] = 1;
5835 reload_inheritance_insn[r]
5836 = reg_reloaded_insn[i];
5837 reload_spill_index[r] = i;
5838 for (k = 0; k < nr; k++)
5839 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5847 /* Here's another way to see if the value is already lying around. */
5850 && ! reload_inherited[r]
5852 && (CONSTANT_P (rld[r].in)
5853 || GET_CODE (rld[r].in) == PLUS
5854 || REG_P (rld[r].in)
5855 || MEM_P (rld[r].in))
5856 && (rld[r].nregs == max_group_size
5857 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5858 search_equiv = rld[r].in;
5859 /* If this is an output reload from a simple move insn, look
5860 if an equivalence for the input is available. */
5861 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5863 rtx set = single_set (insn);
5866 && rtx_equal_p (rld[r].out, SET_DEST (set))
5867 && CONSTANT_P (SET_SRC (set)))
5868 search_equiv = SET_SRC (set);
5874 = find_equiv_reg (search_equiv, insn, rld[r].class,
5875 -1, NULL, 0, rld[r].mode);
5881 regno = REGNO (equiv);
5884 /* This must be a SUBREG of a hard register.
5885 Make a new REG since this might be used in an
5886 address and not all machines support SUBREGs
5888 gcc_assert (GET_CODE (equiv) == SUBREG);
5889 regno = subreg_regno (equiv);
5890 equiv = gen_rtx_REG (rld[r].mode, regno);
5891 /* If we choose EQUIV as the reload register, but the
5892 loop below decides to cancel the inheritance, we'll
5893 end up reloading EQUIV in rld[r].mode, not the mode
5894 it had originally. That isn't safe when EQUIV isn't
5895 available as a spill register since its value might
5896 still be live at this point. */
5897 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5898 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5903 /* If we found a spill reg, reject it unless it is free
5904 and of the desired class. */
5908 int bad_for_class = 0;
5909 int max_regno = regno + rld[r].nregs;
5911 for (i = regno; i < max_regno; i++)
5913 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5915 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5920 && ! free_for_value_p (regno, rld[r].mode,
5921 rld[r].opnum, rld[r].when_needed,
5922 rld[r].in, rld[r].out, r, 1))
5927 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5930 /* We found a register that contains the value we need.
5931 If this register is the same as an `earlyclobber' operand
5932 of the current insn, just mark it as a place to reload from
5933 since we can't use it as the reload register itself. */
5936 for (i = 0; i < n_earlyclobbers; i++)
5937 if (reg_overlap_mentioned_for_reload_p (equiv,
5938 reload_earlyclobbers[i]))
5940 if (! rld[r].optional)
5941 reload_override_in[r] = equiv;
5946 /* If the equiv register we have found is explicitly clobbered
5947 in the current insn, it depends on the reload type if we
5948 can use it, use it for reload_override_in, or not at all.
5949 In particular, we then can't use EQUIV for a
5950 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5954 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5955 switch (rld[r].when_needed)
5957 case RELOAD_FOR_OTHER_ADDRESS:
5958 case RELOAD_FOR_INPADDR_ADDRESS:
5959 case RELOAD_FOR_INPUT_ADDRESS:
5960 case RELOAD_FOR_OPADDR_ADDR:
5963 case RELOAD_FOR_INPUT:
5964 case RELOAD_FOR_OPERAND_ADDRESS:
5965 if (! rld[r].optional)
5966 reload_override_in[r] = equiv;
5972 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5973 switch (rld[r].when_needed)
5975 case RELOAD_FOR_OTHER_ADDRESS:
5976 case RELOAD_FOR_INPADDR_ADDRESS:
5977 case RELOAD_FOR_INPUT_ADDRESS:
5978 case RELOAD_FOR_OPADDR_ADDR:
5979 case RELOAD_FOR_OPERAND_ADDRESS:
5980 case RELOAD_FOR_INPUT:
5983 if (! rld[r].optional)
5984 reload_override_in[r] = equiv;
5992 /* If we found an equivalent reg, say no code need be generated
5993 to load it, and use it as our reload reg. */
5995 && (regno != HARD_FRAME_POINTER_REGNUM
5996 || !frame_pointer_needed))
5998 int nr = hard_regno_nregs[regno][rld[r].mode];
6000 rld[r].reg_rtx = equiv;
6001 reload_inherited[r] = 1;
6003 /* If reg_reloaded_valid is not set for this register,
6004 there might be a stale spill_reg_store lying around.
6005 We must clear it, since otherwise emit_reload_insns
6006 might delete the store. */
6007 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6008 spill_reg_store[regno] = NULL_RTX;
6009 /* If any of the hard registers in EQUIV are spill
6010 registers, mark them as in use for this insn. */
6011 for (k = 0; k < nr; k++)
6013 i = spill_reg_order[regno + k];
6016 mark_reload_reg_in_use (regno, rld[r].opnum,
6019 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6026 /* If we found a register to use already, or if this is an optional
6027 reload, we are done. */
6028 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6032 /* No longer needed for correct operation. Might or might
6033 not give better code on the average. Want to experiment? */
6035 /* See if there is a later reload that has a class different from our
6036 class that intersects our class or that requires less register
6037 than our reload. If so, we must allocate a register to this
6038 reload now, since that reload might inherit a previous reload
6039 and take the only available register in our class. Don't do this
6040 for optional reloads since they will force all previous reloads
6041 to be allocated. Also don't do this for reloads that have been
6044 for (i = j + 1; i < n_reloads; i++)
6046 int s = reload_order[i];
6048 if ((rld[s].in == 0 && rld[s].out == 0
6049 && ! rld[s].secondary_p)
6053 if ((rld[s].class != rld[r].class
6054 && reg_classes_intersect_p (rld[r].class,
6056 || rld[s].nregs < rld[r].nregs)
6063 allocate_reload_reg (chain, r, j == n_reloads - 1);
6067 /* Now allocate reload registers for anything non-optional that
6068 didn't get one yet. */
6069 for (j = 0; j < n_reloads; j++)
6071 int r = reload_order[j];
6073 /* Ignore reloads that got marked inoperative. */
6074 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6077 /* Skip reloads that already have a register allocated or are
6079 if (rld[r].reg_rtx != 0 || rld[r].optional)
6082 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6086 /* If that loop got all the way, we have won. */
6093 /* Loop around and try without any inheritance. */
6098 /* First undo everything done by the failed attempt
6099 to allocate with inheritance. */
6100 choose_reload_regs_init (chain, save_reload_reg_rtx);
6102 /* Some sanity tests to verify that the reloads found in the first
6103 pass are identical to the ones we have now. */
6104 gcc_assert (chain->n_reloads == n_reloads);
6106 for (i = 0; i < n_reloads; i++)
6108 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6110 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6111 for (j = 0; j < n_spills; j++)
6112 if (spill_regs[j] == chain->rld[i].regno)
6113 if (! set_reload_reg (j, i))
6114 failed_reload (chain->insn, i);
6118 /* If we thought we could inherit a reload, because it seemed that
6119 nothing else wanted the same reload register earlier in the insn,
6120 verify that assumption, now that all reloads have been assigned.
6121 Likewise for reloads where reload_override_in has been set. */
6123 /* If doing expensive optimizations, do one preliminary pass that doesn't
6124 cancel any inheritance, but removes reloads that have been needed only
6125 for reloads that we know can be inherited. */
6126 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6128 for (j = 0; j < n_reloads; j++)
6130 int r = reload_order[j];
6132 if (reload_inherited[r] && rld[r].reg_rtx)
6133 check_reg = rld[r].reg_rtx;
6134 else if (reload_override_in[r]
6135 && (REG_P (reload_override_in[r])
6136 || GET_CODE (reload_override_in[r]) == SUBREG))
6137 check_reg = reload_override_in[r];
6140 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6141 rld[r].opnum, rld[r].when_needed, rld[r].in,
6142 (reload_inherited[r]
6143 ? rld[r].out : const0_rtx),
6148 reload_inherited[r] = 0;
6149 reload_override_in[r] = 0;
6151 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6152 reload_override_in, then we do not need its related
6153 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6154 likewise for other reload types.
6155 We handle this by removing a reload when its only replacement
6156 is mentioned in reload_in of the reload we are going to inherit.
6157 A special case are auto_inc expressions; even if the input is
6158 inherited, we still need the address for the output. We can
6159 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6160 If we succeeded removing some reload and we are doing a preliminary
6161 pass just to remove such reloads, make another pass, since the
6162 removal of one reload might allow us to inherit another one. */
6164 && rld[r].out != rld[r].in
6165 && remove_address_replacements (rld[r].in) && pass)
6170 /* Now that reload_override_in is known valid,
6171 actually override reload_in. */
6172 for (j = 0; j < n_reloads; j++)
6173 if (reload_override_in[j])
6174 rld[j].in = reload_override_in[j];
6176 /* If this reload won't be done because it has been canceled or is
6177 optional and not inherited, clear reload_reg_rtx so other
6178 routines (such as subst_reloads) don't get confused. */
6179 for (j = 0; j < n_reloads; j++)
6180 if (rld[j].reg_rtx != 0
6181 && ((rld[j].optional && ! reload_inherited[j])
6182 || (rld[j].in == 0 && rld[j].out == 0
6183 && ! rld[j].secondary_p)))
6185 int regno = true_regnum (rld[j].reg_rtx);
6187 if (spill_reg_order[regno] >= 0)
6188 clear_reload_reg_in_use (regno, rld[j].opnum,
6189 rld[j].when_needed, rld[j].mode);
6191 reload_spill_index[j] = -1;
6194 /* Record which pseudos and which spill regs have output reloads. */
6195 for (j = 0; j < n_reloads; j++)
6197 int r = reload_order[j];
6199 i = reload_spill_index[r];
6201 /* I is nonneg if this reload uses a register.
6202 If rld[r].reg_rtx is 0, this is an optional reload
6203 that we opted to ignore. */
6204 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6205 && rld[r].reg_rtx != 0)
6207 int nregno = REGNO (rld[r].out_reg);
6210 if (nregno < FIRST_PSEUDO_REGISTER)
6211 nr = hard_regno_nregs[nregno][rld[r].mode];
6214 SET_REGNO_REG_SET (®_has_output_reload,
6219 nr = hard_regno_nregs[i][rld[r].mode];
6221 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6224 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6225 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6226 || rld[r].when_needed == RELOAD_FOR_INSN);
6231 /* Deallocate the reload register for reload R. This is called from
6232 remove_address_replacements. */
6235 deallocate_reload_reg (int r)
6239 if (! rld[r].reg_rtx)
6241 regno = true_regnum (rld[r].reg_rtx);
6243 if (spill_reg_order[regno] >= 0)
6244 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6246 reload_spill_index[r] = -1;
6249 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6250 reloads of the same item for fear that we might not have enough reload
6251 registers. However, normally they will get the same reload register
6252 and hence actually need not be loaded twice.
6254 Here we check for the most common case of this phenomenon: when we have
6255 a number of reloads for the same object, each of which were allocated
6256 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6257 reload, and is not modified in the insn itself. If we find such,
6258 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6259 This will not increase the number of spill registers needed and will
6260 prevent redundant code. */
6263 merge_assigned_reloads (rtx insn)
6267 /* Scan all the reloads looking for ones that only load values and
6268 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6269 assigned and not modified by INSN. */
6271 for (i = 0; i < n_reloads; i++)
6273 int conflicting_input = 0;
6274 int max_input_address_opnum = -1;
6275 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6277 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6278 || rld[i].out != 0 || rld[i].reg_rtx == 0
6279 || reg_set_p (rld[i].reg_rtx, insn))
6282 /* Look at all other reloads. Ensure that the only use of this
6283 reload_reg_rtx is in a reload that just loads the same value
6284 as we do. Note that any secondary reloads must be of the identical
6285 class since the values, modes, and result registers are the
6286 same, so we need not do anything with any secondary reloads. */
6288 for (j = 0; j < n_reloads; j++)
6290 if (i == j || rld[j].reg_rtx == 0
6291 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6295 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6296 && rld[j].opnum > max_input_address_opnum)
6297 max_input_address_opnum = rld[j].opnum;
6299 /* If the reload regs aren't exactly the same (e.g, different modes)
6300 or if the values are different, we can't merge this reload.
6301 But if it is an input reload, we might still merge
6302 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6304 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6305 || rld[j].out != 0 || rld[j].in == 0
6306 || ! rtx_equal_p (rld[i].in, rld[j].in))
6308 if (rld[j].when_needed != RELOAD_FOR_INPUT
6309 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6310 || rld[i].opnum > rld[j].opnum)
6311 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6313 conflicting_input = 1;
6314 if (min_conflicting_input_opnum > rld[j].opnum)
6315 min_conflicting_input_opnum = rld[j].opnum;
6319 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6320 we, in fact, found any matching reloads. */
6323 && max_input_address_opnum <= min_conflicting_input_opnum)
6325 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6327 for (j = 0; j < n_reloads; j++)
6328 if (i != j && rld[j].reg_rtx != 0
6329 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6330 && (! conflicting_input
6331 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6332 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6334 rld[i].when_needed = RELOAD_OTHER;
6336 reload_spill_index[j] = -1;
6337 transfer_replacements (i, j);
6340 /* If this is now RELOAD_OTHER, look for any reloads that
6341 load parts of this operand and set them to
6342 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6343 RELOAD_OTHER for outputs. Note that this test is
6344 equivalent to looking for reloads for this operand
6347 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6348 it may share registers with a RELOAD_FOR_INPUT, so we can
6349 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6350 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6352 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6353 instruction is assigned the same register as the earlier
6354 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6355 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6356 instruction to be deleted later on. */
6358 if (rld[i].when_needed == RELOAD_OTHER)
6359 for (j = 0; j < n_reloads; j++)
6361 && rld[j].when_needed != RELOAD_OTHER
6362 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6363 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6364 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6365 && (! conflicting_input
6366 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6367 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6368 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6374 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6375 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6376 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6378 /* Check to see if we accidentally converted two
6379 reloads that use the same reload register with
6380 different inputs to the same type. If so, the
6381 resulting code won't work. */
6383 for (k = 0; k < j; k++)
6384 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6385 || rld[k].when_needed != rld[j].when_needed
6386 || !rtx_equal_p (rld[k].reg_rtx,
6388 || rtx_equal_p (rld[k].in,
6395 /* These arrays are filled by emit_reload_insns and its subroutines. */
6396 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6397 static rtx other_input_address_reload_insns = 0;
6398 static rtx other_input_reload_insns = 0;
6399 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6400 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6401 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6402 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6403 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6404 static rtx operand_reload_insns = 0;
6405 static rtx other_operand_reload_insns = 0;
6406 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6408 /* Values to be put in spill_reg_store are put here first. */
6409 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6410 static HARD_REG_SET reg_reloaded_died;
6412 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6413 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6414 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6415 adjusted register, and return true. Otherwise, return false. */
6417 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6418 enum reg_class new_class,
6419 enum machine_mode new_mode)
6424 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6426 unsigned regno = REGNO (reg);
6428 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6430 if (GET_MODE (reg) != new_mode)
6432 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6434 if (hard_regno_nregs[regno][new_mode]
6435 > hard_regno_nregs[regno][GET_MODE (reg)])
6437 reg = reload_adjust_reg_for_mode (reg, new_mode);
6445 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6446 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6447 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6448 adjusted register, and return true. Otherwise, return false. */
6450 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6451 enum insn_code icode)
6454 enum reg_class new_class = scratch_reload_class (icode);
6455 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6457 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6458 new_class, new_mode);
6461 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6462 has the number J. OLD contains the value to be used as input. */
6465 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6468 rtx insn = chain->insn;
6469 rtx reloadreg = rl->reg_rtx;
6470 rtx oldequiv_reg = 0;
6473 enum machine_mode mode;
6476 /* Determine the mode to reload in.
6477 This is very tricky because we have three to choose from.
6478 There is the mode the insn operand wants (rl->inmode).
6479 There is the mode of the reload register RELOADREG.
6480 There is the intrinsic mode of the operand, which we could find
6481 by stripping some SUBREGs.
6482 It turns out that RELOADREG's mode is irrelevant:
6483 we can change that arbitrarily.
6485 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6486 then the reload reg may not support QImode moves, so use SImode.
6487 If foo is in memory due to spilling a pseudo reg, this is safe,
6488 because the QImode value is in the least significant part of a
6489 slot big enough for a SImode. If foo is some other sort of
6490 memory reference, then it is impossible to reload this case,
6491 so previous passes had better make sure this never happens.
6493 Then consider a one-word union which has SImode and one of its
6494 members is a float, being fetched as (SUBREG:SF union:SI).
6495 We must fetch that as SFmode because we could be loading into
6496 a float-only register. In this case OLD's mode is correct.
6498 Consider an immediate integer: it has VOIDmode. Here we need
6499 to get a mode from something else.
6501 In some cases, there is a fourth mode, the operand's
6502 containing mode. If the insn specifies a containing mode for
6503 this operand, it overrides all others.
6505 I am not sure whether the algorithm here is always right,
6506 but it does the right things in those cases. */
6508 mode = GET_MODE (old);
6509 if (mode == VOIDmode)
6512 /* delete_output_reload is only invoked properly if old contains
6513 the original pseudo register. Since this is replaced with a
6514 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6515 find the pseudo in RELOAD_IN_REG. */
6516 if (reload_override_in[j]
6517 && REG_P (rl->in_reg))
6524 else if (REG_P (oldequiv))
6525 oldequiv_reg = oldequiv;
6526 else if (GET_CODE (oldequiv) == SUBREG)
6527 oldequiv_reg = SUBREG_REG (oldequiv);
6529 /* If we are reloading from a register that was recently stored in
6530 with an output-reload, see if we can prove there was
6531 actually no need to store the old value in it. */
6533 if (optimize && REG_P (oldequiv)
6534 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6535 && spill_reg_store[REGNO (oldequiv)]
6537 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6538 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6540 delete_output_reload (insn, j, REGNO (oldequiv));
6542 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6543 then load RELOADREG from OLDEQUIV. Note that we cannot use
6544 gen_lowpart_common since it can do the wrong thing when
6545 RELOADREG has a multi-word mode. Note that RELOADREG
6546 must always be a REG here. */
6548 if (GET_MODE (reloadreg) != mode)
6549 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6550 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6551 oldequiv = SUBREG_REG (oldequiv);
6552 if (GET_MODE (oldequiv) != VOIDmode
6553 && mode != GET_MODE (oldequiv))
6554 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6556 /* Switch to the right place to emit the reload insns. */
6557 switch (rl->when_needed)
6560 where = &other_input_reload_insns;
6562 case RELOAD_FOR_INPUT:
6563 where = &input_reload_insns[rl->opnum];
6565 case RELOAD_FOR_INPUT_ADDRESS:
6566 where = &input_address_reload_insns[rl->opnum];
6568 case RELOAD_FOR_INPADDR_ADDRESS:
6569 where = &inpaddr_address_reload_insns[rl->opnum];
6571 case RELOAD_FOR_OUTPUT_ADDRESS:
6572 where = &output_address_reload_insns[rl->opnum];
6574 case RELOAD_FOR_OUTADDR_ADDRESS:
6575 where = &outaddr_address_reload_insns[rl->opnum];
6577 case RELOAD_FOR_OPERAND_ADDRESS:
6578 where = &operand_reload_insns;
6580 case RELOAD_FOR_OPADDR_ADDR:
6581 where = &other_operand_reload_insns;
6583 case RELOAD_FOR_OTHER_ADDRESS:
6584 where = &other_input_address_reload_insns;
6590 push_to_sequence (*where);
6592 /* Auto-increment addresses must be reloaded in a special way. */
6593 if (rl->out && ! rl->out_reg)
6595 /* We are not going to bother supporting the case where a
6596 incremented register can't be copied directly from
6597 OLDEQUIV since this seems highly unlikely. */
6598 gcc_assert (rl->secondary_in_reload < 0);
6600 if (reload_inherited[j])
6601 oldequiv = reloadreg;
6603 old = XEXP (rl->in_reg, 0);
6605 if (optimize && REG_P (oldequiv)
6606 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6607 && spill_reg_store[REGNO (oldequiv)]
6609 && (dead_or_set_p (insn,
6610 spill_reg_stored_to[REGNO (oldequiv)])
6611 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6613 delete_output_reload (insn, j, REGNO (oldequiv));
6615 /* Prevent normal processing of this reload. */
6617 /* Output a special code sequence for this case. */
6618 new_spill_reg_store[REGNO (reloadreg)]
6619 = inc_for_reload (reloadreg, oldequiv, rl->out,
6623 /* If we are reloading a pseudo-register that was set by the previous
6624 insn, see if we can get rid of that pseudo-register entirely
6625 by redirecting the previous insn into our reload register. */
6627 else if (optimize && REG_P (old)
6628 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6629 && dead_or_set_p (insn, old)
6630 /* This is unsafe if some other reload
6631 uses the same reg first. */
6632 && ! conflicts_with_override (reloadreg)
6633 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6634 rl->when_needed, old, rl->out, j, 0))
6636 rtx temp = PREV_INSN (insn);
6637 while (temp && NOTE_P (temp))
6638 temp = PREV_INSN (temp);
6640 && NONJUMP_INSN_P (temp)
6641 && GET_CODE (PATTERN (temp)) == SET
6642 && SET_DEST (PATTERN (temp)) == old
6643 /* Make sure we can access insn_operand_constraint. */
6644 && asm_noperands (PATTERN (temp)) < 0
6645 /* This is unsafe if operand occurs more than once in current
6646 insn. Perhaps some occurrences aren't reloaded. */
6647 && count_occurrences (PATTERN (insn), old, 0) == 1)
6649 rtx old = SET_DEST (PATTERN (temp));
6650 /* Store into the reload register instead of the pseudo. */
6651 SET_DEST (PATTERN (temp)) = reloadreg;
6653 /* Verify that resulting insn is valid. */
6654 extract_insn (temp);
6655 if (constrain_operands (1))
6657 /* If the previous insn is an output reload, the source is
6658 a reload register, and its spill_reg_store entry will
6659 contain the previous destination. This is now
6661 if (REG_P (SET_SRC (PATTERN (temp)))
6662 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6664 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6665 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6668 /* If these are the only uses of the pseudo reg,
6669 pretend for GDB it lives in the reload reg we used. */
6670 if (REG_N_DEATHS (REGNO (old)) == 1
6671 && REG_N_SETS (REGNO (old)) == 1)
6673 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6674 alter_reg (REGNO (old), -1);
6680 SET_DEST (PATTERN (temp)) = old;
6685 /* We can't do that, so output an insn to load RELOADREG. */
6687 /* If we have a secondary reload, pick up the secondary register
6688 and icode, if any. If OLDEQUIV and OLD are different or
6689 if this is an in-out reload, recompute whether or not we
6690 still need a secondary register and what the icode should
6691 be. If we still need a secondary register and the class or
6692 icode is different, go back to reloading from OLD if using
6693 OLDEQUIV means that we got the wrong type of register. We
6694 cannot have different class or icode due to an in-out reload
6695 because we don't make such reloads when both the input and
6696 output need secondary reload registers. */
6698 if (! special && rl->secondary_in_reload >= 0)
6700 rtx second_reload_reg = 0;
6701 rtx third_reload_reg = 0;
6702 int secondary_reload = rl->secondary_in_reload;
6703 rtx real_oldequiv = oldequiv;
6706 enum insn_code icode;
6707 enum insn_code tertiary_icode = CODE_FOR_nothing;
6709 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6710 and similarly for OLD.
6711 See comments in get_secondary_reload in reload.c. */
6712 /* If it is a pseudo that cannot be replaced with its
6713 equivalent MEM, we must fall back to reload_in, which
6714 will have all the necessary substitutions registered.
6715 Likewise for a pseudo that can't be replaced with its
6716 equivalent constant.
6718 Take extra care for subregs of such pseudos. Note that
6719 we cannot use reg_equiv_mem in this case because it is
6720 not in the right mode. */
6723 if (GET_CODE (tmp) == SUBREG)
6724 tmp = SUBREG_REG (tmp);
6726 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6727 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6728 || reg_equiv_constant[REGNO (tmp)] != 0))
6730 if (! reg_equiv_mem[REGNO (tmp)]
6731 || num_not_at_initial_offset
6732 || GET_CODE (oldequiv) == SUBREG)
6733 real_oldequiv = rl->in;
6735 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6739 if (GET_CODE (tmp) == SUBREG)
6740 tmp = SUBREG_REG (tmp);
6742 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6743 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6744 || reg_equiv_constant[REGNO (tmp)] != 0))
6746 if (! reg_equiv_mem[REGNO (tmp)]
6747 || num_not_at_initial_offset
6748 || GET_CODE (old) == SUBREG)
6751 real_old = reg_equiv_mem[REGNO (tmp)];
6754 second_reload_reg = rld[secondary_reload].reg_rtx;
6755 if (rld[secondary_reload].secondary_in_reload >= 0)
6757 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6759 third_reload_reg = rld[tertiary_reload].reg_rtx;
6760 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6761 /* We'd have to add more code for quartary reloads. */
6762 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6764 icode = rl->secondary_in_icode;
6766 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6767 || (rl->in != 0 && rl->out != 0))
6769 secondary_reload_info sri, sri2;
6770 enum reg_class new_class, new_t_class;
6772 sri.icode = CODE_FOR_nothing;
6773 sri.prev_sri = NULL;
6774 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6777 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6778 second_reload_reg = 0;
6779 else if (new_class == NO_REGS)
6781 if (reload_adjust_reg_for_icode (&second_reload_reg,
6782 third_reload_reg, sri.icode))
6783 icode = sri.icode, third_reload_reg = 0;
6785 oldequiv = old, real_oldequiv = real_old;
6787 else if (sri.icode != CODE_FOR_nothing)
6788 /* We currently lack a way to express this in reloads. */
6792 sri2.icode = CODE_FOR_nothing;
6793 sri2.prev_sri = &sri;
6794 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6795 new_class, mode, &sri);
6796 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6798 if (reload_adjust_reg_for_temp (&second_reload_reg,
6801 third_reload_reg = 0, tertiary_icode = sri2.icode;
6803 oldequiv = old, real_oldequiv = real_old;
6805 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6807 rtx intermediate = second_reload_reg;
6809 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6811 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6814 second_reload_reg = intermediate;
6815 tertiary_icode = sri2.icode;
6818 oldequiv = old, real_oldequiv = real_old;
6820 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6822 rtx intermediate = second_reload_reg;
6824 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6826 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6829 second_reload_reg = intermediate;
6830 tertiary_icode = sri2.icode;
6833 oldequiv = old, real_oldequiv = real_old;
6836 /* This could be handled more intelligently too. */
6837 oldequiv = old, real_oldequiv = real_old;
6841 /* If we still need a secondary reload register, check
6842 to see if it is being used as a scratch or intermediate
6843 register and generate code appropriately. If we need
6844 a scratch register, use REAL_OLDEQUIV since the form of
6845 the insn may depend on the actual address if it is
6848 if (second_reload_reg)
6850 if (icode != CODE_FOR_nothing)
6852 /* We'd have to add extra code to handle this case. */
6853 gcc_assert (!third_reload_reg);
6855 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6856 second_reload_reg));
6861 /* See if we need a scratch register to load the
6862 intermediate register (a tertiary reload). */
6863 if (tertiary_icode != CODE_FOR_nothing)
6865 emit_insn ((GEN_FCN (tertiary_icode)
6866 (second_reload_reg, real_oldequiv,
6867 third_reload_reg)));
6869 else if (third_reload_reg)
6871 gen_reload (third_reload_reg, real_oldequiv,
6874 gen_reload (second_reload_reg, third_reload_reg,
6879 gen_reload (second_reload_reg, real_oldequiv,
6883 oldequiv = second_reload_reg;
6888 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6890 rtx real_oldequiv = oldequiv;
6892 if ((REG_P (oldequiv)
6893 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6894 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6895 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6896 || (GET_CODE (oldequiv) == SUBREG
6897 && REG_P (SUBREG_REG (oldequiv))
6898 && (REGNO (SUBREG_REG (oldequiv))
6899 >= FIRST_PSEUDO_REGISTER)
6900 && ((reg_equiv_memory_loc
6901 [REGNO (SUBREG_REG (oldequiv))] != 0)
6902 || (reg_equiv_constant
6903 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6904 || (CONSTANT_P (oldequiv)
6905 && (PREFERRED_RELOAD_CLASS (oldequiv,
6906 REGNO_REG_CLASS (REGNO (reloadreg)))
6908 real_oldequiv = rl->in;
6909 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6913 if (flag_non_call_exceptions)
6914 copy_eh_notes (insn, get_insns ());
6916 /* End this sequence. */
6917 *where = get_insns ();
6920 /* Update reload_override_in so that delete_address_reloads_1
6921 can see the actual register usage. */
6923 reload_override_in[j] = oldequiv;
6926 /* Generate insns to for the output reload RL, which is for the insn described
6927 by CHAIN and has the number J. */
6929 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6932 rtx reloadreg = rl->reg_rtx;
6933 rtx insn = chain->insn;
6936 enum machine_mode mode = GET_MODE (old);
6939 if (rl->when_needed == RELOAD_OTHER)
6942 push_to_sequence (output_reload_insns[rl->opnum]);
6944 /* Determine the mode to reload in.
6945 See comments above (for input reloading). */
6947 if (mode == VOIDmode)
6949 /* VOIDmode should never happen for an output. */
6950 if (asm_noperands (PATTERN (insn)) < 0)
6951 /* It's the compiler's fault. */
6952 fatal_insn ("VOIDmode on an output", insn);
6953 error_for_asm (insn, "output operand is constant in %<asm%>");
6954 /* Prevent crash--use something we know is valid. */
6956 old = gen_rtx_REG (mode, REGNO (reloadreg));
6959 if (GET_MODE (reloadreg) != mode)
6960 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6962 /* If we need two reload regs, set RELOADREG to the intermediate
6963 one, since it will be stored into OLD. We might need a secondary
6964 register only for an input reload, so check again here. */
6966 if (rl->secondary_out_reload >= 0)
6969 int secondary_reload = rl->secondary_out_reload;
6970 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6972 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6973 && reg_equiv_mem[REGNO (old)] != 0)
6974 real_old = reg_equiv_mem[REGNO (old)];
6976 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6978 rtx second_reloadreg = reloadreg;
6979 reloadreg = rld[secondary_reload].reg_rtx;
6981 /* See if RELOADREG is to be used as a scratch register
6982 or as an intermediate register. */
6983 if (rl->secondary_out_icode != CODE_FOR_nothing)
6985 /* We'd have to add extra code to handle this case. */
6986 gcc_assert (tertiary_reload < 0);
6988 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6989 (real_old, second_reloadreg, reloadreg)));
6994 /* See if we need both a scratch and intermediate reload
6997 enum insn_code tertiary_icode
6998 = rld[secondary_reload].secondary_out_icode;
7000 /* We'd have to add more code for quartary reloads. */
7001 gcc_assert (tertiary_reload < 0
7002 || rld[tertiary_reload].secondary_out_reload < 0);
7004 if (GET_MODE (reloadreg) != mode)
7005 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7007 if (tertiary_icode != CODE_FOR_nothing)
7009 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7012 /* Copy primary reload reg to secondary reload reg.
7013 (Note that these have been swapped above, then
7014 secondary reload reg to OLD using our insn.) */
7016 /* If REAL_OLD is a paradoxical SUBREG, remove it
7017 and try to put the opposite SUBREG on
7019 if (GET_CODE (real_old) == SUBREG
7020 && (GET_MODE_SIZE (GET_MODE (real_old))
7021 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7022 && 0 != (tem = gen_lowpart_common
7023 (GET_MODE (SUBREG_REG (real_old)),
7025 real_old = SUBREG_REG (real_old), reloadreg = tem;
7027 gen_reload (reloadreg, second_reloadreg,
7028 rl->opnum, rl->when_needed);
7029 emit_insn ((GEN_FCN (tertiary_icode)
7030 (real_old, reloadreg, third_reloadreg)));
7036 /* Copy between the reload regs here and then to
7039 gen_reload (reloadreg, second_reloadreg,
7040 rl->opnum, rl->when_needed);
7041 if (tertiary_reload >= 0)
7043 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7045 gen_reload (third_reloadreg, reloadreg,
7046 rl->opnum, rl->when_needed);
7047 reloadreg = third_reloadreg;
7054 /* Output the last reload insn. */
7059 /* Don't output the last reload if OLD is not the dest of
7060 INSN and is in the src and is clobbered by INSN. */
7061 if (! flag_expensive_optimizations
7063 || !(set = single_set (insn))
7064 || rtx_equal_p (old, SET_DEST (set))
7065 || !reg_mentioned_p (old, SET_SRC (set))
7066 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7067 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7068 gen_reload (old, reloadreg, rl->opnum,
7072 /* Look at all insns we emitted, just to be safe. */
7073 for (p = get_insns (); p; p = NEXT_INSN (p))
7076 rtx pat = PATTERN (p);
7078 /* If this output reload doesn't come from a spill reg,
7079 clear any memory of reloaded copies of the pseudo reg.
7080 If this output reload comes from a spill reg,
7081 reg_has_output_reload will make this do nothing. */
7082 note_stores (pat, forget_old_reloads_1, NULL);
7084 if (reg_mentioned_p (rl->reg_rtx, pat))
7086 rtx set = single_set (insn);
7087 if (reload_spill_index[j] < 0
7089 && SET_SRC (set) == rl->reg_rtx)
7091 int src = REGNO (SET_SRC (set));
7093 reload_spill_index[j] = src;
7094 SET_HARD_REG_BIT (reg_is_output_reload, src);
7095 if (find_regno_note (insn, REG_DEAD, src))
7096 SET_HARD_REG_BIT (reg_reloaded_died, src);
7098 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7100 int s = rl->secondary_out_reload;
7101 set = single_set (p);
7102 /* If this reload copies only to the secondary reload
7103 register, the secondary reload does the actual
7105 if (s >= 0 && set == NULL_RTX)
7106 /* We can't tell what function the secondary reload
7107 has and where the actual store to the pseudo is
7108 made; leave new_spill_reg_store alone. */
7111 && SET_SRC (set) == rl->reg_rtx
7112 && SET_DEST (set) == rld[s].reg_rtx)
7114 /* Usually the next instruction will be the
7115 secondary reload insn; if we can confirm
7116 that it is, setting new_spill_reg_store to
7117 that insn will allow an extra optimization. */
7118 rtx s_reg = rld[s].reg_rtx;
7119 rtx next = NEXT_INSN (p);
7120 rld[s].out = rl->out;
7121 rld[s].out_reg = rl->out_reg;
7122 set = single_set (next);
7123 if (set && SET_SRC (set) == s_reg
7124 && ! new_spill_reg_store[REGNO (s_reg)])
7126 SET_HARD_REG_BIT (reg_is_output_reload,
7128 new_spill_reg_store[REGNO (s_reg)] = next;
7132 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7137 if (rl->when_needed == RELOAD_OTHER)
7139 emit_insn (other_output_reload_insns[rl->opnum]);
7140 other_output_reload_insns[rl->opnum] = get_insns ();
7143 output_reload_insns[rl->opnum] = get_insns ();
7145 if (flag_non_call_exceptions)
7146 copy_eh_notes (insn, get_insns ());
7151 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7152 and has the number J. */
7154 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7156 rtx insn = chain->insn;
7157 rtx old = (rl->in && MEM_P (rl->in)
7158 ? rl->in_reg : rl->in);
7161 /* AUTO_INC reloads need to be handled even if inherited. We got an
7162 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7163 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7164 && ! rtx_equal_p (rl->reg_rtx, old)
7165 && rl->reg_rtx != 0)
7166 emit_input_reload_insns (chain, rld + j, old, j);
7168 /* When inheriting a wider reload, we have a MEM in rl->in,
7169 e.g. inheriting a SImode output reload for
7170 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7171 if (optimize && reload_inherited[j] && rl->in
7173 && MEM_P (rl->in_reg)
7174 && reload_spill_index[j] >= 0
7175 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7176 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7178 /* If we are reloading a register that was recently stored in with an
7179 output-reload, see if we can prove there was
7180 actually no need to store the old value in it. */
7183 && (reload_inherited[j] || reload_override_in[j])
7185 && REG_P (rl->reg_rtx)
7186 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7188 /* There doesn't seem to be any reason to restrict this to pseudos
7189 and doing so loses in the case where we are copying from a
7190 register of the wrong class. */
7191 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7192 >= FIRST_PSEUDO_REGISTER)
7194 /* The insn might have already some references to stackslots
7195 replaced by MEMs, while reload_out_reg still names the
7197 && (dead_or_set_p (insn,
7198 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7199 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7201 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7204 /* Do output reloading for reload RL, which is for the insn described by
7205 CHAIN and has the number J.
7206 ??? At some point we need to support handling output reloads of
7207 JUMP_INSNs or insns that set cc0. */
7209 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7212 rtx insn = chain->insn;
7213 /* If this is an output reload that stores something that is
7214 not loaded in this same reload, see if we can eliminate a previous
7216 rtx pseudo = rl->out_reg;
7221 && ! rtx_equal_p (rl->in_reg, pseudo)
7222 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7223 && reg_last_reload_reg[REGNO (pseudo)])
7225 int pseudo_no = REGNO (pseudo);
7226 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7228 /* We don't need to test full validity of last_regno for
7229 inherit here; we only want to know if the store actually
7230 matches the pseudo. */
7231 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7232 && reg_reloaded_contents[last_regno] == pseudo_no
7233 && spill_reg_store[last_regno]
7234 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7235 delete_output_reload (insn, j, last_regno);
7240 || rl->reg_rtx == old
7241 || rl->reg_rtx == 0)
7244 /* An output operand that dies right away does need a reload,
7245 but need not be copied from it. Show the new location in the
7247 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7248 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7250 XEXP (note, 0) = rl->reg_rtx;
7253 /* Likewise for a SUBREG of an operand that dies. */
7254 else if (GET_CODE (old) == SUBREG
7255 && REG_P (SUBREG_REG (old))
7256 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7259 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7263 else if (GET_CODE (old) == SCRATCH)
7264 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7265 but we don't want to make an output reload. */
7268 /* If is a JUMP_INSN, we can't support output reloads yet. */
7269 gcc_assert (NONJUMP_INSN_P (insn));
7271 emit_output_reload_insns (chain, rld + j, j);
7274 /* Reload number R reloads from or to a group of hard registers starting at
7275 register REGNO. Return true if it can be treated for inheritance purposes
7276 like a group of reloads, each one reloading a single hard register.
7277 The caller has already checked that the spill register and REGNO use
7278 the same number of registers to store the reload value. */
7281 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7283 #ifdef CANNOT_CHANGE_MODE_CLASS
7284 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7285 GET_MODE (rld[r].reg_rtx),
7286 reg_raw_mode[reload_spill_index[r]])
7287 && !REG_CANNOT_CHANGE_MODE_P (regno,
7288 GET_MODE (rld[r].reg_rtx),
7289 reg_raw_mode[regno]));
7295 /* Output insns to reload values in and out of the chosen reload regs. */
7298 emit_reload_insns (struct insn_chain *chain)
7300 rtx insn = chain->insn;
7304 CLEAR_HARD_REG_SET (reg_reloaded_died);
7306 for (j = 0; j < reload_n_operands; j++)
7307 input_reload_insns[j] = input_address_reload_insns[j]
7308 = inpaddr_address_reload_insns[j]
7309 = output_reload_insns[j] = output_address_reload_insns[j]
7310 = outaddr_address_reload_insns[j]
7311 = other_output_reload_insns[j] = 0;
7312 other_input_address_reload_insns = 0;
7313 other_input_reload_insns = 0;
7314 operand_reload_insns = 0;
7315 other_operand_reload_insns = 0;
7317 /* Dump reloads into the dump file. */
7320 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7321 debug_reload_to_stream (dump_file);
7324 /* Now output the instructions to copy the data into and out of the
7325 reload registers. Do these in the order that the reloads were reported,
7326 since reloads of base and index registers precede reloads of operands
7327 and the operands may need the base and index registers reloaded. */
7329 for (j = 0; j < n_reloads; j++)
7332 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7333 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7335 do_input_reload (chain, rld + j, j);
7336 do_output_reload (chain, rld + j, j);
7339 /* Now write all the insns we made for reloads in the order expected by
7340 the allocation functions. Prior to the insn being reloaded, we write
7341 the following reloads:
7343 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7345 RELOAD_OTHER reloads.
7347 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7348 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7349 RELOAD_FOR_INPUT reload for the operand.
7351 RELOAD_FOR_OPADDR_ADDRS reloads.
7353 RELOAD_FOR_OPERAND_ADDRESS reloads.
7355 After the insn being reloaded, we write the following:
7357 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7358 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7359 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7360 reloads for the operand. The RELOAD_OTHER output reloads are
7361 output in descending order by reload number. */
7363 emit_insn_before (other_input_address_reload_insns, insn);
7364 emit_insn_before (other_input_reload_insns, insn);
7366 for (j = 0; j < reload_n_operands; j++)
7368 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7369 emit_insn_before (input_address_reload_insns[j], insn);
7370 emit_insn_before (input_reload_insns[j], insn);
7373 emit_insn_before (other_operand_reload_insns, insn);
7374 emit_insn_before (operand_reload_insns, insn);
7376 for (j = 0; j < reload_n_operands; j++)
7378 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7379 x = emit_insn_after (output_address_reload_insns[j], x);
7380 x = emit_insn_after (output_reload_insns[j], x);
7381 emit_insn_after (other_output_reload_insns[j], x);
7384 /* For all the spill regs newly reloaded in this instruction,
7385 record what they were reloaded from, so subsequent instructions
7386 can inherit the reloads.
7388 Update spill_reg_store for the reloads of this insn.
7389 Copy the elements that were updated in the loop above. */
7391 for (j = 0; j < n_reloads; j++)
7393 int r = reload_order[j];
7394 int i = reload_spill_index[r];
7396 /* If this is a non-inherited input reload from a pseudo, we must
7397 clear any memory of a previous store to the same pseudo. Only do
7398 something if there will not be an output reload for the pseudo
7400 if (rld[r].in_reg != 0
7401 && ! (reload_inherited[r] || reload_override_in[r]))
7403 rtx reg = rld[r].in_reg;
7405 if (GET_CODE (reg) == SUBREG)
7406 reg = SUBREG_REG (reg);
7409 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7410 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7412 int nregno = REGNO (reg);
7414 if (reg_last_reload_reg[nregno])
7416 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7418 if (reg_reloaded_contents[last_regno] == nregno)
7419 spill_reg_store[last_regno] = 0;
7424 /* I is nonneg if this reload used a register.
7425 If rld[r].reg_rtx is 0, this is an optional reload
7426 that we opted to ignore. */
7428 if (i >= 0 && rld[r].reg_rtx != 0)
7430 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7432 int part_reaches_end = 0;
7433 int all_reaches_end = 1;
7435 /* For a multi register reload, we need to check if all or part
7436 of the value lives to the end. */
7437 for (k = 0; k < nr; k++)
7439 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7440 rld[r].when_needed))
7441 part_reaches_end = 1;
7443 all_reaches_end = 0;
7446 /* Ignore reloads that don't reach the end of the insn in
7448 if (all_reaches_end)
7450 /* First, clear out memory of what used to be in this spill reg.
7451 If consecutive registers are used, clear them all. */
7453 for (k = 0; k < nr; k++)
7455 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7456 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7459 /* Maybe the spill reg contains a copy of reload_out. */
7461 && (REG_P (rld[r].out)
7465 || REG_P (rld[r].out_reg)))
7467 rtx out = (REG_P (rld[r].out)
7471 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7472 int nregno = REGNO (out);
7473 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7474 : hard_regno_nregs[nregno]
7475 [GET_MODE (rld[r].reg_rtx)]);
7478 spill_reg_store[i] = new_spill_reg_store[i];
7479 spill_reg_stored_to[i] = out;
7480 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7482 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7484 && inherit_piecemeal_p (r, nregno));
7486 /* If NREGNO is a hard register, it may occupy more than
7487 one register. If it does, say what is in the
7488 rest of the registers assuming that both registers
7489 agree on how many words the object takes. If not,
7490 invalidate the subsequent registers. */
7492 if (nregno < FIRST_PSEUDO_REGISTER)
7493 for (k = 1; k < nnr; k++)
7494 reg_last_reload_reg[nregno + k]
7496 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7499 /* Now do the inverse operation. */
7500 for (k = 0; k < nr; k++)
7502 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7503 reg_reloaded_contents[i + k]
7504 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7507 reg_reloaded_insn[i + k] = insn;
7508 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7509 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7510 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7514 /* Maybe the spill reg contains a copy of reload_in. Only do
7515 something if there will not be an output reload for
7516 the register being reloaded. */
7517 else if (rld[r].out_reg == 0
7519 && ((REG_P (rld[r].in)
7520 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7521 && !REGNO_REG_SET_P (®_has_output_reload,
7523 || (REG_P (rld[r].in_reg)
7524 && !REGNO_REG_SET_P (®_has_output_reload,
7525 REGNO (rld[r].in_reg))))
7526 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7533 if (REG_P (rld[r].in)
7534 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7536 else if (REG_P (rld[r].in_reg))
7539 in = XEXP (rld[r].in_reg, 0);
7540 nregno = REGNO (in);
7542 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7543 : hard_regno_nregs[nregno]
7544 [GET_MODE (rld[r].reg_rtx)]);
7546 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7548 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7550 && inherit_piecemeal_p (r, nregno));
7552 if (nregno < FIRST_PSEUDO_REGISTER)
7553 for (k = 1; k < nnr; k++)
7554 reg_last_reload_reg[nregno + k]
7556 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7559 /* Unless we inherited this reload, show we haven't
7560 recently done a store.
7561 Previous stores of inherited auto_inc expressions
7562 also have to be discarded. */
7563 if (! reload_inherited[r]
7564 || (rld[r].out && ! rld[r].out_reg))
7565 spill_reg_store[i] = 0;
7567 for (k = 0; k < nr; k++)
7569 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7570 reg_reloaded_contents[i + k]
7571 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7574 reg_reloaded_insn[i + k] = insn;
7575 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7576 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7577 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7582 /* However, if part of the reload reaches the end, then we must
7583 invalidate the old info for the part that survives to the end. */
7584 else if (part_reaches_end)
7586 for (k = 0; k < nr; k++)
7587 if (reload_reg_reaches_end_p (i + k,
7589 rld[r].when_needed))
7590 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7594 /* The following if-statement was #if 0'd in 1.34 (or before...).
7595 It's reenabled in 1.35 because supposedly nothing else
7596 deals with this problem. */
7598 /* If a register gets output-reloaded from a non-spill register,
7599 that invalidates any previous reloaded copy of it.
7600 But forget_old_reloads_1 won't get to see it, because
7601 it thinks only about the original insn. So invalidate it here.
7602 Also do the same thing for RELOAD_OTHER constraints where the
7603 output is discarded. */
7605 && ((rld[r].out != 0
7606 && (REG_P (rld[r].out)
7607 || (MEM_P (rld[r].out)
7608 && REG_P (rld[r].out_reg))))
7609 || (rld[r].out == 0 && rld[r].out_reg
7610 && REG_P (rld[r].out_reg))))
7612 rtx out = ((rld[r].out && REG_P (rld[r].out))
7613 ? rld[r].out : rld[r].out_reg);
7614 int nregno = REGNO (out);
7616 /* REG_RTX is now set or clobbered by the main instruction.
7617 As the comment above explains, forget_old_reloads_1 only
7618 sees the original instruction, and there is no guarantee
7619 that the original instruction also clobbered REG_RTX.
7620 For example, if find_reloads sees that the input side of
7621 a matched operand pair dies in this instruction, it may
7622 use the input register as the reload register.
7624 Calling forget_old_reloads_1 is a waste of effort if
7625 REG_RTX is also the output register.
7627 If we know that REG_RTX holds the value of a pseudo
7628 register, the code after the call will record that fact. */
7629 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7630 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7632 if (nregno >= FIRST_PSEUDO_REGISTER)
7634 rtx src_reg, store_insn = NULL_RTX;
7636 reg_last_reload_reg[nregno] = 0;
7638 /* If we can find a hard register that is stored, record
7639 the storing insn so that we may delete this insn with
7640 delete_output_reload. */
7641 src_reg = rld[r].reg_rtx;
7643 /* If this is an optional reload, try to find the source reg
7644 from an input reload. */
7647 rtx set = single_set (insn);
7648 if (set && SET_DEST (set) == rld[r].out)
7652 src_reg = SET_SRC (set);
7654 for (k = 0; k < n_reloads; k++)
7656 if (rld[k].in == src_reg)
7658 src_reg = rld[k].reg_rtx;
7665 store_insn = new_spill_reg_store[REGNO (src_reg)];
7666 if (src_reg && REG_P (src_reg)
7667 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7669 int src_regno = REGNO (src_reg);
7670 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7671 /* The place where to find a death note varies with
7672 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7673 necessarily checked exactly in the code that moves
7674 notes, so just check both locations. */
7675 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7676 if (! note && store_insn)
7677 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7680 spill_reg_store[src_regno + nr] = store_insn;
7681 spill_reg_stored_to[src_regno + nr] = out;
7682 reg_reloaded_contents[src_regno + nr] = nregno;
7683 reg_reloaded_insn[src_regno + nr] = store_insn;
7684 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7685 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7686 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7687 GET_MODE (src_reg)))
7688 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7690 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7692 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7694 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7696 reg_last_reload_reg[nregno] = src_reg;
7697 /* We have to set reg_has_output_reload here, or else
7698 forget_old_reloads_1 will clear reg_last_reload_reg
7700 SET_REGNO_REG_SET (®_has_output_reload,
7706 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7708 while (num_regs-- > 0)
7709 reg_last_reload_reg[nregno + num_regs] = 0;
7713 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7716 /* Go through the motions to emit INSN and test if it is strictly valid.
7717 Return the emitted insn if valid, else return NULL. */
7720 emit_insn_if_valid_for_reload (rtx insn)
7722 rtx last = get_last_insn ();
7725 insn = emit_insn (insn);
7726 code = recog_memoized (insn);
7730 extract_insn (insn);
7731 /* We want constrain operands to treat this insn strictly in its
7732 validity determination, i.e., the way it would after reload has
7734 if (constrain_operands (1))
7738 delete_insns_since (last);
7742 /* Emit code to perform a reload from IN (which may be a reload register) to
7743 OUT (which may also be a reload register). IN or OUT is from operand
7744 OPNUM with reload type TYPE.
7746 Returns first insn emitted. */
7749 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7751 rtx last = get_last_insn ();
7754 /* If IN is a paradoxical SUBREG, remove it and try to put the
7755 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7756 if (GET_CODE (in) == SUBREG
7757 && (GET_MODE_SIZE (GET_MODE (in))
7758 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7759 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7760 in = SUBREG_REG (in), out = tem;
7761 else if (GET_CODE (out) == SUBREG
7762 && (GET_MODE_SIZE (GET_MODE (out))
7763 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7764 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7765 out = SUBREG_REG (out), in = tem;
7767 /* How to do this reload can get quite tricky. Normally, we are being
7768 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7769 register that didn't get a hard register. In that case we can just
7770 call emit_move_insn.
7772 We can also be asked to reload a PLUS that adds a register or a MEM to
7773 another register, constant or MEM. This can occur during frame pointer
7774 elimination and while reloading addresses. This case is handled by
7775 trying to emit a single insn to perform the add. If it is not valid,
7776 we use a two insn sequence.
7778 Or we can be asked to reload an unary operand that was a fragment of
7779 an addressing mode, into a register. If it isn't recognized as-is,
7780 we try making the unop operand and the reload-register the same:
7781 (set reg:X (unop:X expr:Y))
7782 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7784 Finally, we could be called to handle an 'o' constraint by putting
7785 an address into a register. In that case, we first try to do this
7786 with a named pattern of "reload_load_address". If no such pattern
7787 exists, we just emit a SET insn and hope for the best (it will normally
7788 be valid on machines that use 'o').
7790 This entire process is made complex because reload will never
7791 process the insns we generate here and so we must ensure that
7792 they will fit their constraints and also by the fact that parts of
7793 IN might be being reloaded separately and replaced with spill registers.
7794 Because of this, we are, in some sense, just guessing the right approach
7795 here. The one listed above seems to work.
7797 ??? At some point, this whole thing needs to be rethought. */
7799 if (GET_CODE (in) == PLUS
7800 && (REG_P (XEXP (in, 0))
7801 || GET_CODE (XEXP (in, 0)) == SUBREG
7802 || MEM_P (XEXP (in, 0)))
7803 && (REG_P (XEXP (in, 1))
7804 || GET_CODE (XEXP (in, 1)) == SUBREG
7805 || CONSTANT_P (XEXP (in, 1))
7806 || MEM_P (XEXP (in, 1))))
7808 /* We need to compute the sum of a register or a MEM and another
7809 register, constant, or MEM, and put it into the reload
7810 register. The best possible way of doing this is if the machine
7811 has a three-operand ADD insn that accepts the required operands.
7813 The simplest approach is to try to generate such an insn and see if it
7814 is recognized and matches its constraints. If so, it can be used.
7816 It might be better not to actually emit the insn unless it is valid,
7817 but we need to pass the insn as an operand to `recog' and
7818 `extract_insn' and it is simpler to emit and then delete the insn if
7819 not valid than to dummy things up. */
7821 rtx op0, op1, tem, insn;
7824 op0 = find_replacement (&XEXP (in, 0));
7825 op1 = find_replacement (&XEXP (in, 1));
7827 /* Since constraint checking is strict, commutativity won't be
7828 checked, so we need to do that here to avoid spurious failure
7829 if the add instruction is two-address and the second operand
7830 of the add is the same as the reload reg, which is frequently
7831 the case. If the insn would be A = B + A, rearrange it so
7832 it will be A = A + B as constrain_operands expects. */
7834 if (REG_P (XEXP (in, 1))
7835 && REGNO (out) == REGNO (XEXP (in, 1)))
7836 tem = op0, op0 = op1, op1 = tem;
7838 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7839 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7841 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7845 /* If that failed, we must use a conservative two-insn sequence.
7847 Use a move to copy one operand into the reload register. Prefer
7848 to reload a constant, MEM or pseudo since the move patterns can
7849 handle an arbitrary operand. If OP1 is not a constant, MEM or
7850 pseudo and OP1 is not a valid operand for an add instruction, then
7853 After reloading one of the operands into the reload register, add
7854 the reload register to the output register.
7856 If there is another way to do this for a specific machine, a
7857 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7860 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7862 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7864 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7865 || (code != CODE_FOR_nothing
7866 && ! ((*insn_data[code].operand[2].predicate)
7867 (op1, insn_data[code].operand[2].mode))))
7868 tem = op0, op0 = op1, op1 = tem;
7870 gen_reload (out, op0, opnum, type);
7872 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7873 This fixes a problem on the 32K where the stack pointer cannot
7874 be used as an operand of an add insn. */
7876 if (rtx_equal_p (op0, op1))
7879 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7882 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7883 set_unique_reg_note (insn, REG_EQUIV, in);
7887 /* If that failed, copy the address register to the reload register.
7888 Then add the constant to the reload register. */
7890 gcc_assert (!reg_overlap_mentioned_p (out, op0));
7891 gen_reload (out, op1, opnum, type);
7892 insn = emit_insn (gen_add2_insn (out, op0));
7893 set_unique_reg_note (insn, REG_EQUIV, in);
7896 #ifdef SECONDARY_MEMORY_NEEDED
7897 /* If we need a memory location to do the move, do it that way. */
7898 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7899 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7900 && (REG_P (out) || GET_CODE (out) == SUBREG)
7901 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7902 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7903 REGNO_REG_CLASS (reg_or_subregno (out)),
7906 /* Get the memory to use and rewrite both registers to its mode. */
7907 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7909 if (GET_MODE (loc) != GET_MODE (out))
7910 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7912 if (GET_MODE (loc) != GET_MODE (in))
7913 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7915 gen_reload (loc, in, opnum, type);
7916 gen_reload (out, loc, opnum, type);
7919 else if (REG_P (out) && UNARY_P (in))
7926 op1 = find_replacement (&XEXP (in, 0));
7927 if (op1 != XEXP (in, 0))
7928 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7930 /* First, try a plain SET. */
7931 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7935 /* If that failed, move the inner operand to the reload
7936 register, and try the same unop with the inner expression
7937 replaced with the reload register. */
7939 if (GET_MODE (op1) != GET_MODE (out))
7940 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7944 gen_reload (out_moded, op1, opnum, type);
7947 = gen_rtx_SET (VOIDmode, out,
7948 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7950 insn = emit_insn_if_valid_for_reload (insn);
7953 set_unique_reg_note (insn, REG_EQUIV, in);
7957 fatal_insn ("Failure trying to reload:", set);
7959 /* If IN is a simple operand, use gen_move_insn. */
7960 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7962 tem = emit_insn (gen_move_insn (out, in));
7963 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7964 mark_jump_label (in, tem, 0);
7967 #ifdef HAVE_reload_load_address
7968 else if (HAVE_reload_load_address)
7969 emit_insn (gen_reload_load_address (out, in));
7972 /* Otherwise, just write (set OUT IN) and hope for the best. */
7974 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7976 /* Return the first insn emitted.
7977 We can not just return get_last_insn, because there may have
7978 been multiple instructions emitted. Also note that gen_move_insn may
7979 emit more than one insn itself, so we can not assume that there is one
7980 insn emitted per emit_insn_before call. */
7982 return last ? NEXT_INSN (last) : get_insns ();
7985 /* Delete a previously made output-reload whose result we now believe
7986 is not needed. First we double-check.
7988 INSN is the insn now being processed.
7989 LAST_RELOAD_REG is the hard register number for which we want to delete
7990 the last output reload.
7991 J is the reload-number that originally used REG. The caller has made
7992 certain that reload J doesn't use REG any longer for input. */
7995 delete_output_reload (rtx insn, int j, int last_reload_reg)
7997 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7998 rtx reg = spill_reg_stored_to[last_reload_reg];
8001 int n_inherited = 0;
8005 /* It is possible that this reload has been only used to set another reload
8006 we eliminated earlier and thus deleted this instruction too. */
8007 if (INSN_DELETED_P (output_reload_insn))
8010 /* Get the raw pseudo-register referred to. */
8012 while (GET_CODE (reg) == SUBREG)
8013 reg = SUBREG_REG (reg);
8014 substed = reg_equiv_memory_loc[REGNO (reg)];
8016 /* This is unsafe if the operand occurs more often in the current
8017 insn than it is inherited. */
8018 for (k = n_reloads - 1; k >= 0; k--)
8020 rtx reg2 = rld[k].in;
8023 if (MEM_P (reg2) || reload_override_in[k])
8024 reg2 = rld[k].in_reg;
8026 if (rld[k].out && ! rld[k].out_reg)
8027 reg2 = XEXP (rld[k].in_reg, 0);
8029 while (GET_CODE (reg2) == SUBREG)
8030 reg2 = SUBREG_REG (reg2);
8031 if (rtx_equal_p (reg2, reg))
8033 if (reload_inherited[k] || reload_override_in[k] || k == j)
8039 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8040 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8041 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8044 n_occurrences += count_occurrences (PATTERN (insn),
8045 eliminate_regs (substed, 0,
8047 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8049 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8050 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8052 if (n_occurrences > n_inherited)
8055 /* If the pseudo-reg we are reloading is no longer referenced
8056 anywhere between the store into it and here,
8057 and we're within the same basic block, then the value can only
8058 pass through the reload reg and end up here.
8059 Otherwise, give up--return. */
8060 for (i1 = NEXT_INSN (output_reload_insn);
8061 i1 != insn; i1 = NEXT_INSN (i1))
8063 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8065 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8066 && reg_mentioned_p (reg, PATTERN (i1)))
8068 /* If this is USE in front of INSN, we only have to check that
8069 there are no more references than accounted for by inheritance. */
8070 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8072 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8073 i1 = NEXT_INSN (i1);
8075 if (n_occurrences <= n_inherited && i1 == insn)
8081 /* We will be deleting the insn. Remove the spill reg information. */
8082 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8084 spill_reg_store[last_reload_reg + k] = 0;
8085 spill_reg_stored_to[last_reload_reg + k] = 0;
8088 /* The caller has already checked that REG dies or is set in INSN.
8089 It has also checked that we are optimizing, and thus some
8090 inaccuracies in the debugging information are acceptable.
8091 So we could just delete output_reload_insn. But in some cases
8092 we can improve the debugging information without sacrificing
8093 optimization - maybe even improving the code: See if the pseudo
8094 reg has been completely replaced with reload regs. If so, delete
8095 the store insn and forget we had a stack slot for the pseudo. */
8096 if (rld[j].out != rld[j].in
8097 && REG_N_DEATHS (REGNO (reg)) == 1
8098 && REG_N_SETS (REGNO (reg)) == 1
8099 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8100 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8104 /* We know that it was used only between here and the beginning of
8105 the current basic block. (We also know that the last use before
8106 INSN was the output reload we are thinking of deleting, but never
8107 mind that.) Search that range; see if any ref remains. */
8108 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8110 rtx set = single_set (i2);
8112 /* Uses which just store in the pseudo don't count,
8113 since if they are the only uses, they are dead. */
8114 if (set != 0 && SET_DEST (set) == reg)
8119 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8120 && reg_mentioned_p (reg, PATTERN (i2)))
8122 /* Some other ref remains; just delete the output reload we
8124 delete_address_reloads (output_reload_insn, insn);
8125 delete_insn (output_reload_insn);
8130 /* Delete the now-dead stores into this pseudo. Note that this
8131 loop also takes care of deleting output_reload_insn. */
8132 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8134 rtx set = single_set (i2);
8136 if (set != 0 && SET_DEST (set) == reg)
8138 delete_address_reloads (i2, insn);
8146 /* For the debugging info, say the pseudo lives in this reload reg. */
8147 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8148 alter_reg (REGNO (reg), -1);
8152 delete_address_reloads (output_reload_insn, insn);
8153 delete_insn (output_reload_insn);
8157 /* We are going to delete DEAD_INSN. Recursively delete loads of
8158 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8159 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8161 delete_address_reloads (rtx dead_insn, rtx current_insn)
8163 rtx set = single_set (dead_insn);
8164 rtx set2, dst, prev, next;
8167 rtx dst = SET_DEST (set);
8169 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8171 /* If we deleted the store from a reloaded post_{in,de}c expression,
8172 we can delete the matching adds. */
8173 prev = PREV_INSN (dead_insn);
8174 next = NEXT_INSN (dead_insn);
8175 if (! prev || ! next)
8177 set = single_set (next);
8178 set2 = single_set (prev);
8180 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8181 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8182 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8184 dst = SET_DEST (set);
8185 if (! rtx_equal_p (dst, SET_DEST (set2))
8186 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8187 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8188 || (INTVAL (XEXP (SET_SRC (set), 1))
8189 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8191 delete_related_insns (prev);
8192 delete_related_insns (next);
8195 /* Subfunction of delete_address_reloads: process registers found in X. */
8197 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8199 rtx prev, set, dst, i2;
8201 enum rtx_code code = GET_CODE (x);
8205 const char *fmt = GET_RTX_FORMAT (code);
8206 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8209 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8210 else if (fmt[i] == 'E')
8212 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8213 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8220 if (spill_reg_order[REGNO (x)] < 0)
8223 /* Scan backwards for the insn that sets x. This might be a way back due
8225 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8227 code = GET_CODE (prev);
8228 if (code == CODE_LABEL || code == JUMP_INSN)
8232 if (reg_set_p (x, PATTERN (prev)))
8234 if (reg_referenced_p (x, PATTERN (prev)))
8237 if (! prev || INSN_UID (prev) < reload_first_uid)
8239 /* Check that PREV only sets the reload register. */
8240 set = single_set (prev);
8243 dst = SET_DEST (set);
8245 || ! rtx_equal_p (dst, x))
8247 if (! reg_set_p (dst, PATTERN (dead_insn)))
8249 /* Check if DST was used in a later insn -
8250 it might have been inherited. */
8251 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8257 if (reg_referenced_p (dst, PATTERN (i2)))
8259 /* If there is a reference to the register in the current insn,
8260 it might be loaded in a non-inherited reload. If no other
8261 reload uses it, that means the register is set before
8263 if (i2 == current_insn)
8265 for (j = n_reloads - 1; j >= 0; j--)
8266 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8267 || reload_override_in[j] == dst)
8269 for (j = n_reloads - 1; j >= 0; j--)
8270 if (rld[j].in && rld[j].reg_rtx == dst)
8279 /* If DST is still live at CURRENT_INSN, check if it is used for
8280 any reload. Note that even if CURRENT_INSN sets DST, we still
8281 have to check the reloads. */
8282 if (i2 == current_insn)
8284 for (j = n_reloads - 1; j >= 0; j--)
8285 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8286 || reload_override_in[j] == dst)
8288 /* ??? We can't finish the loop here, because dst might be
8289 allocated to a pseudo in this block if no reload in this
8290 block needs any of the classes containing DST - see
8291 spill_hard_reg. There is no easy way to tell this, so we
8292 have to scan till the end of the basic block. */
8294 if (reg_set_p (dst, PATTERN (i2)))
8298 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8299 reg_reloaded_contents[REGNO (dst)] = -1;
8303 /* Output reload-insns to reload VALUE into RELOADREG.
8304 VALUE is an autoincrement or autodecrement RTX whose operand
8305 is a register or memory location;
8306 so reloading involves incrementing that location.
8307 IN is either identical to VALUE, or some cheaper place to reload from.
8309 INC_AMOUNT is the number to increment or decrement by (always positive).
8310 This cannot be deduced from VALUE.
8312 Return the instruction that stores into RELOADREG. */
8315 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8317 /* REG or MEM to be copied and incremented. */
8318 rtx incloc = find_replacement (&XEXP (value, 0));
8319 /* Nonzero if increment after copying. */
8320 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8321 || GET_CODE (value) == POST_MODIFY);
8327 rtx real_in = in == value ? incloc : in;
8329 /* No hard register is equivalent to this register after
8330 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8331 we could inc/dec that register as well (maybe even using it for
8332 the source), but I'm not sure it's worth worrying about. */
8334 reg_last_reload_reg[REGNO (incloc)] = 0;
8336 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8338 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8339 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8343 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8344 inc_amount = -inc_amount;
8346 inc = GEN_INT (inc_amount);
8349 /* If this is post-increment, first copy the location to the reload reg. */
8350 if (post && real_in != reloadreg)
8351 emit_insn (gen_move_insn (reloadreg, real_in));
8355 /* See if we can directly increment INCLOC. Use a method similar to
8356 that in gen_reload. */
8358 last = get_last_insn ();
8359 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8360 gen_rtx_PLUS (GET_MODE (incloc),
8363 code = recog_memoized (add_insn);
8366 extract_insn (add_insn);
8367 if (constrain_operands (1))
8369 /* If this is a pre-increment and we have incremented the value
8370 where it lives, copy the incremented value to RELOADREG to
8371 be used as an address. */
8374 emit_insn (gen_move_insn (reloadreg, incloc));
8379 delete_insns_since (last);
8382 /* If couldn't do the increment directly, must increment in RELOADREG.
8383 The way we do this depends on whether this is pre- or post-increment.
8384 For pre-increment, copy INCLOC to the reload register, increment it
8385 there, then save back. */
8389 if (in != reloadreg)
8390 emit_insn (gen_move_insn (reloadreg, real_in));
8391 emit_insn (gen_add2_insn (reloadreg, inc));
8392 store = emit_insn (gen_move_insn (incloc, reloadreg));
8397 Because this might be a jump insn or a compare, and because RELOADREG
8398 may not be available after the insn in an input reload, we must do
8399 the incrementation before the insn being reloaded for.
8401 We have already copied IN to RELOADREG. Increment the copy in
8402 RELOADREG, save that back, then decrement RELOADREG so it has
8403 the original value. */
8405 emit_insn (gen_add2_insn (reloadreg, inc));
8406 store = emit_insn (gen_move_insn (incloc, reloadreg));
8407 if (GET_CODE (inc) == CONST_INT)
8408 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8410 emit_insn (gen_sub2_insn (reloadreg, inc));
8418 add_auto_inc_notes (rtx insn, rtx x)
8420 enum rtx_code code = GET_CODE (x);
8424 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8427 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8431 /* Scan all the operand sub-expressions. */
8432 fmt = GET_RTX_FORMAT (code);
8433 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8436 add_auto_inc_notes (insn, XEXP (x, i));
8437 else if (fmt[i] == 'E')
8438 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8439 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8444 /* Copy EH notes from an insn to its reloads. */
8446 copy_eh_notes (rtx insn, rtx x)
8448 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8451 for (; x != 0; x = NEXT_INSN (x))
8453 if (may_trap_p (PATTERN (x)))
8455 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8461 /* This is used by reload pass, that does emit some instructions after
8462 abnormal calls moving basic block end, but in fact it wants to emit
8463 them on the edge. Looks for abnormal call edges, find backward the
8464 proper call and fix the damage.
8466 Similar handle instructions throwing exceptions internally. */
8468 fixup_abnormal_edges (void)
8470 bool inserted = false;
8478 /* Look for cases we are interested in - calls or instructions causing
8480 FOR_EACH_EDGE (e, ei, bb->succs)
8482 if (e->flags & EDGE_ABNORMAL_CALL)
8484 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8485 == (EDGE_ABNORMAL | EDGE_EH))
8488 if (e && !CALL_P (BB_END (bb))
8489 && !can_throw_internal (BB_END (bb)))
8493 /* Get past the new insns generated. Allow notes, as the insns
8494 may be already deleted. */
8496 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8497 && !can_throw_internal (insn)
8498 && insn != BB_HEAD (bb))
8499 insn = PREV_INSN (insn);
8501 if (CALL_P (insn) || can_throw_internal (insn))
8505 stop = NEXT_INSN (BB_END (bb));
8507 insn = NEXT_INSN (insn);
8509 FOR_EACH_EDGE (e, ei, bb->succs)
8510 if (e->flags & EDGE_FALLTHRU)
8513 while (insn && insn != stop)
8515 next = NEXT_INSN (insn);
8520 /* Sometimes there's still the return value USE.
8521 If it's placed after a trapping call (i.e. that
8522 call is the last insn anyway), we have no fallthru
8523 edge. Simply delete this use and don't try to insert
8524 on the non-existent edge. */
8525 if (GET_CODE (PATTERN (insn)) != USE)
8527 /* We're not deleting it, we're moving it. */
8528 INSN_DELETED_P (insn) = 0;
8529 PREV_INSN (insn) = NULL_RTX;
8530 NEXT_INSN (insn) = NULL_RTX;
8532 insert_insn_on_edge (insn, e);
8540 /* It may be that we don't find any such trapping insn. In this
8541 case we discovered quite late that the insn that had been
8542 marked as can_throw_internal in fact couldn't trap at all.
8543 So we should in fact delete the EH edges out of the block. */
8545 purge_dead_edges (bb);
8549 /* We've possibly turned single trapping insn into multiple ones. */
8550 if (flag_non_call_exceptions)
8553 blocks = sbitmap_alloc (last_basic_block);
8554 sbitmap_ones (blocks);
8555 find_many_sub_basic_blocks (blocks);
8559 commit_edge_insertions ();
8561 #ifdef ENABLE_CHECKING
8562 /* Verify that we didn't turn one trapping insn into many, and that
8563 we found and corrected all of the problems wrt fixups on the
8565 verify_flow_info ();
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