1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 #include "insn-config.h"
25 #include "insn-flags.h"
26 #include "insn-codes.h"
30 #include "hard-reg-set.h"
33 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
70 /* During reload_as_needed, element N contains a REG rtx for the hard reg
71 into which pseudo reg N has been reloaded (perhaps for a previous insn). */
72 static rtx *reg_last_reload_reg;
74 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
75 for an output reload that stores into reg N. */
76 static char *reg_has_output_reload;
78 /* Indicates which hard regs are reload-registers for an output reload
79 in the current insn. */
80 static HARD_REG_SET reg_is_output_reload;
82 /* Element N is the constant value to which pseudo reg N is equivalent,
83 or zero if pseudo reg N is not equivalent to a constant.
84 find_reloads looks at this in order to replace pseudo reg N
85 with the constant it stands for. */
86 rtx *reg_equiv_constant;
88 /* Element N is a memory location to which pseudo reg N is equivalent,
89 prior to any register elimination (such as frame pointer to stack
90 pointer). Depending on whether or not it is a valid address, this value
91 is transferred to either reg_equiv_address or reg_equiv_mem. */
92 rtx *reg_equiv_memory_loc;
94 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
95 This is used when the address is not valid as a memory address
96 (because its displacement is too big for the machine.) */
97 rtx *reg_equiv_address;
99 /* Element N is the memory slot to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a memory slot. */
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static int *reg_max_ref_width;
106 /* Element N is the insn that initialized reg N from its equivalent
107 constant or memory slot. */
108 static rtx *reg_equiv_init;
110 /* During reload_as_needed, element N contains the last pseudo regno
111 reloaded into the Nth reload register. This vector is in parallel
112 with spill_regs. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 the Nth reload register was last used. This vector is in parallel
119 with spill_regs, and its contents are significant only when
120 reg_reloaded_contents is significant. */
121 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
123 /* Number of spill-regs so far; number of valid elements of spill_regs. */
126 /* In parallel with spill_regs, contains REG rtx's for those regs.
127 Holds the last rtx used for any given reg, or 0 if it has never
128 been used for spilling yet. This rtx is reused, provided it has
130 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
132 /* In parallel with spill_regs, contains nonzero for a spill reg
133 that was stored after the last time it was used.
134 The precise value is the insn generated to do the store. */
135 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
137 /* This table is the inverse mapping of spill_regs:
138 indexed by hard reg number,
139 it contains the position of that reg in spill_regs,
140 or -1 for something that is not in spill_regs. */
141 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
143 /* This reg set indicates registers that may not be used for retrying global
144 allocation. The registers that may not be used include all spill registers
145 and the frame pointer (if we are using one). */
146 HARD_REG_SET forbidden_regs;
148 /* This reg set indicates registers that are not good for spill registers.
149 They will not be used to complete groups of spill registers. This includes
150 all fixed registers, registers that may be eliminated, and registers
151 explicitly used in the rtl.
153 (spill_reg_order prevents these registers from being used to start a
155 static HARD_REG_SET bad_spill_regs;
157 /* Describes order of use of registers for reloading
158 of spilled pseudo-registers. `spills' is the number of
159 elements that are actually valid; new ones are added at the end. */
160 static short spill_regs[FIRST_PSEUDO_REGISTER];
162 /* Describes order of preference for putting regs into spill_regs.
163 Contains the numbers of all the hard regs, in order most preferred first.
164 This order is different for each function.
165 It is set up by order_regs_for_reload.
166 Empty elements at the end contain -1. */
167 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
169 /* 1 for a hard register that appears explicitly in the rtl
170 (for example, function value registers, special registers
171 used by insns, structure value pointer registers). */
172 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
174 /* Indicates if a register was counted against the need for
175 groups. 0 means it can count against max_nongroup instead. */
176 static HARD_REG_SET counted_for_groups;
178 /* Indicates if a register was counted against the need for
179 non-groups. 0 means it can become part of a new group.
180 During choose_reload_regs, 1 here means don't use this reg
181 as part of a group, even if it seems to be otherwise ok. */
182 static HARD_REG_SET counted_for_nongroups;
184 /* Nonzero if indirect addressing is supported on the machine; this means
185 that spilling (REG n) does not require reloading it into a register in
186 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
187 value indicates the level of indirect addressing supported, e.g., two
188 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
191 static char spill_indirect_levels;
193 /* Nonzero if indirect addressing is supported when the innermost MEM is
194 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
195 which these are valid is the same as spill_indirect_levels, above. */
197 char indirect_symref_ok;
199 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
201 char double_reg_address_ok;
203 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
209 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
211 /* Indexed by register class and basic block number, nonzero if there is
212 any need for a spill register of that class in that basic block.
213 The pointer is 0 if we did stupid allocation and don't know
214 the structure of basic blocks. */
216 char *basic_block_needs[N_REG_CLASSES];
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
225 int caller_save_needed;
227 /* Set to 1 while reload_as_needed is operating.
228 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* These arrays record the insn_code of insns that may be needed to
233 perform input and output reloads of special objects. They provide a
234 place to pass a scratch register. */
236 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
237 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
239 /* This obstack is used for allocation of rtl during register elimination.
240 The allocated storage can be freed once find_reloads has processed the
243 struct obstack reload_obstack;
244 char *reload_firstobj;
246 #define obstack_chunk_alloc xmalloc
247 #define obstack_chunk_free free
249 /* List of labels that must never be deleted. */
250 extern rtx forced_labels;
252 /* This structure is used to record information about register eliminations.
253 Each array entry describes one possible way of eliminating a register
254 in favor of another. If there is more than one way of eliminating a
255 particular register, the most preferred should be specified first. */
257 static struct elim_table
259 int from; /* Register number to be eliminated. */
260 int to; /* Register number used as replacement. */
261 int initial_offset; /* Initial difference between values. */
262 int can_eliminate; /* Non-zero if this elimination can be done. */
263 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
264 insns made by reload. */
265 int offset; /* Current offset between the two regs. */
266 int max_offset; /* Maximum offset between the two regs. */
267 int previous_offset; /* Offset at end of previous insn. */
268 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
269 rtx from_rtx; /* REG rtx for the register to be eliminated.
270 We cannot simply compare the number since
271 we might then spuriously replace a hard
272 register corresponding to a pseudo
273 assigned to the reg to be eliminated. */
274 rtx to_rtx; /* REG rtx for the replacement. */
277 /* If a set of eliminable registers was specified, define the table from it.
278 Otherwise, default to the normal case of the frame pointer being
279 replaced by the stack pointer. */
281 #ifdef ELIMINABLE_REGS
284 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
287 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
289 /* Record the number of pending eliminations that have an offset not equal
290 to their initial offset. If non-zero, we use a new copy of each
291 replacement result in any insns encountered. */
292 static int num_not_at_initial_offset;
294 /* Count the number of registers that we may be able to eliminate. */
295 static int num_eliminable;
297 /* For each label, we record the offset of each elimination. If we reach
298 a label by more than one path and an offset differs, we cannot do the
299 elimination. This information is indexed by the number of the label.
300 The first table is an array of flags that records whether we have yet
301 encountered a label and the second table is an array of arrays, one
302 entry in the latter array for each elimination. */
304 static char *offsets_known_at;
305 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
307 /* Number of labels in the current function. */
309 static int num_labels;
311 void mark_home_live ();
312 static void count_possible_groups ();
313 static int possible_group_p ();
314 static void scan_paradoxical_subregs ();
315 static void reload_as_needed ();
316 static int modes_equiv_for_class_p ();
317 static void alter_reg ();
318 static void delete_dead_insn ();
319 static void spill_failure ();
320 static int new_spill_reg();
321 static void set_label_offsets ();
322 static int eliminate_regs_in_insn ();
323 static void mark_not_eliminable ();
324 static int spill_hard_reg ();
325 static void choose_reload_regs ();
326 static void emit_reload_insns ();
327 static void delete_output_reload ();
328 static void forget_old_reloads_1 ();
329 static void order_regs_for_reload ();
330 static rtx inc_for_reload ();
331 static int constraint_accepts_reg_p ();
332 static int count_occurrences ();
334 extern void remove_death ();
335 extern rtx adj_offsettable_operand ();
336 extern rtx form_sum ();
343 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
344 Set spill_indirect_levels to the number of levels such addressing is
345 permitted, zero if it is not permitted at all. */
348 = gen_rtx (MEM, Pmode,
349 gen_rtx (PLUS, Pmode,
350 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
352 spill_indirect_levels = 0;
354 while (memory_address_p (QImode, tem))
356 spill_indirect_levels++;
357 tem = gen_rtx (MEM, Pmode, tem);
360 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
362 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
363 indirect_symref_ok = memory_address_p (QImode, tem);
365 /* See if reg+reg is a valid (and offsettable) address. */
367 tem = gen_rtx (PLUS, Pmode,
368 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
369 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM));
370 /* This way, we make sure that reg+reg is an offsettable address. */
371 tem = plus_constant (tem, 4);
373 double_reg_address_ok = memory_address_p (QImode, tem);
375 /* Initialize obstack for our rtl allocation. */
376 gcc_obstack_init (&reload_obstack);
377 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
379 #ifdef HAVE_SECONDARY_RELOADS
381 /* Initialize the optabs for doing special input and output reloads. */
383 for (i = 0; i < NUM_MACHINE_MODES; i++)
384 reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing;
386 #ifdef HAVE_reload_inqi
387 if (HAVE_reload_inqi)
388 reload_in_optab[(int) QImode] = CODE_FOR_reload_inqi;
390 #ifdef HAVE_reload_inhi
391 if (HAVE_reload_inhi)
392 reload_in_optab[(int) HImode] = CODE_FOR_reload_inhi;
394 #ifdef HAVE_reload_insi
395 if (HAVE_reload_insi)
396 reload_in_optab[(int) SImode] = CODE_FOR_reload_insi;
398 #ifdef HAVE_reload_indi
399 if (HAVE_reload_indi)
400 reload_in_optab[(int) DImode] = CODE_FOR_reload_indi;
402 #ifdef HAVE_reload_inti
403 if (HAVE_reload_inti)
404 reload_in_optab[(int) TImode] = CODE_FOR_reload_inti;
406 #ifdef HAVE_reload_insf
407 if (HAVE_reload_insf)
408 reload_in_optab[(int) SFmode] = CODE_FOR_reload_insf;
410 #ifdef HAVE_reload_indf
411 if (HAVE_reload_indf)
412 reload_in_optab[(int) DFmode] = CODE_FOR_reload_indf;
414 #ifdef HAVE_reload_inxf
415 if (HAVE_reload_inxf)
416 reload_in_optab[(int) XFmode] = CODE_FOR_reload_inxf;
418 #ifdef HAVE_reload_intf
419 if (HAVE_reload_intf)
420 reload_in_optab[(int) TFmode] = CODE_FOR_reload_intf;
423 #ifdef HAVE_reload_outqi
424 if (HAVE_reload_outqi)
425 reload_out_optab[(int) QImode] = CODE_FOR_reload_outqi;
427 #ifdef HAVE_reload_outhi
428 if (HAVE_reload_outhi)
429 reload_out_optab[(int) HImode] = CODE_FOR_reload_outhi;
431 #ifdef HAVE_reload_outsi
432 if (HAVE_reload_outsi)
433 reload_out_optab[(int) SImode] = CODE_FOR_reload_outsi;
435 #ifdef HAVE_reload_outdi
436 if (HAVE_reload_outdi)
437 reload_out_optab[(int) DImode] = CODE_FOR_reload_outdi;
439 #ifdef HAVE_reload_outti
440 if (HAVE_reload_outti)
441 reload_out_optab[(int) TImode] = CODE_FOR_reload_outti;
443 #ifdef HAVE_reload_outsf
444 if (HAVE_reload_outsf)
445 reload_out_optab[(int) SFmode] = CODE_FOR_reload_outsf;
447 #ifdef HAVE_reload_outdf
448 if (HAVE_reload_outdf)
449 reload_out_optab[(int) DFmode] = CODE_FOR_reload_outdf;
451 #ifdef HAVE_reload_outxf
452 if (HAVE_reload_outxf)
453 reload_out_optab[(int) XFmode] = CODE_FOR_reload_outxf;
455 #ifdef HAVE_reload_outtf
456 if (HAVE_reload_outtf)
457 reload_out_optab[(int) TFmode] = CODE_FOR_reload_outtf;
460 #endif /* HAVE_SECONDARY_RELOADS */
464 /* Main entry point for the reload pass, and only entry point
467 FIRST is the first insn of the function being compiled.
469 GLOBAL nonzero means we were called from global_alloc
470 and should attempt to reallocate any pseudoregs that we
471 displace from hard regs we will use for reloads.
472 If GLOBAL is zero, we do not have enough information to do that,
473 so any pseudo reg that is spilled must go to the stack.
475 DUMPFILE is the global-reg debugging dump file stream, or 0.
476 If it is nonzero, messages are written to it to describe
477 which registers are seized as reload regs, which pseudo regs
478 are spilled from them, and where the pseudo regs are reallocated to.
480 Return value is nonzero if reload failed
481 and we must not do any more for this function. */
484 reload (first, global, dumpfile)
492 register struct elim_table *ep;
494 int something_changed;
495 int something_needs_reloads;
496 int something_needs_elimination;
497 int new_basic_block_needs;
498 enum reg_class caller_save_spill_class = NO_REGS;
499 int caller_save_group_size = 1;
501 /* Nonzero means we couldn't get enough spill regs. */
504 /* The basic block number currently being processed for INSN. */
507 /* Make sure even insns with volatile mem refs are recognizable. */
510 /* Enable find_equiv_reg to distinguish insns made by reload. */
511 reload_first_uid = get_max_uid ();
513 for (i = 0; i < N_REG_CLASSES; i++)
514 basic_block_needs[i] = 0;
516 /* Remember which hard regs appear explicitly
517 before we merge into `regs_ever_live' the ones in which
518 pseudo regs have been allocated. */
519 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
521 /* We don't have a stack slot for any spill reg yet. */
522 bzero (spill_stack_slot, sizeof spill_stack_slot);
523 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
525 /* Initialize the save area information for caller-save, in case some
529 /* Compute which hard registers are now in use
530 as homes for pseudo registers.
531 This is done here rather than (eg) in global_alloc
532 because this point is reached even if not optimizing. */
534 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
537 /* Make sure that the last insn in the chain
538 is not something that needs reloading. */
539 emit_note (NULL_PTR, NOTE_INSN_DELETED);
541 /* Find all the pseudo registers that didn't get hard regs
542 but do have known equivalent constants or memory slots.
543 These include parameters (known equivalent to parameter slots)
544 and cse'd or loop-moved constant memory addresses.
546 Record constant equivalents in reg_equiv_constant
547 so they will be substituted by find_reloads.
548 Record memory equivalents in reg_mem_equiv so they can
549 be substituted eventually by altering the REG-rtx's. */
551 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
552 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
553 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
554 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
555 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
556 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
557 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
558 bzero (reg_equiv_init, max_regno * sizeof (rtx));
559 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
560 bzero (reg_equiv_address, max_regno * sizeof (rtx));
561 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
562 bzero (reg_max_ref_width, max_regno * sizeof (int));
564 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
565 Also find all paradoxical subregs
566 and find largest such for each pseudo. */
568 for (insn = first; insn; insn = NEXT_INSN (insn))
570 rtx set = single_set (insn);
572 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
574 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
576 #ifdef LEGITIMATE_PIC_OPERAND_P
577 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
578 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
582 rtx x = XEXP (note, 0);
583 i = REGNO (SET_DEST (set));
584 if (i > LAST_VIRTUAL_REGISTER)
586 if (GET_CODE (x) == MEM)
587 reg_equiv_memory_loc[i] = x;
588 else if (CONSTANT_P (x))
590 if (LEGITIMATE_CONSTANT_P (x))
591 reg_equiv_constant[i] = x;
593 reg_equiv_memory_loc[i]
594 = force_const_mem (GET_MODE (SET_DEST (set)), x);
599 /* If this register is being made equivalent to a MEM
600 and the MEM is not SET_SRC, the equivalencing insn
601 is one with the MEM as a SET_DEST and it occurs later.
602 So don't mark this insn now. */
603 if (GET_CODE (x) != MEM
604 || rtx_equal_p (SET_SRC (set), x))
605 reg_equiv_init[i] = insn;
610 /* If this insn is setting a MEM from a register equivalent to it,
611 this is the equivalencing insn. */
612 else if (set && GET_CODE (SET_DEST (set)) == MEM
613 && GET_CODE (SET_SRC (set)) == REG
614 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
615 && rtx_equal_p (SET_DEST (set),
616 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
617 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
619 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
620 scan_paradoxical_subregs (PATTERN (insn));
623 /* Does this function require a frame pointer? */
625 frame_pointer_needed = (! flag_omit_frame_pointer
626 #ifdef EXIT_IGNORE_STACK
627 /* ?? If EXIT_IGNORE_STACK is set, we will not save
628 and restore sp for alloca. So we can't eliminate
629 the frame pointer in that case. At some point,
630 we should improve this by emitting the
631 sp-adjusting insns for this case. */
632 || (current_function_calls_alloca
633 && EXIT_IGNORE_STACK)
635 || FRAME_POINTER_REQUIRED);
639 /* Initialize the table of registers to eliminate. The way we do this
640 depends on how the eliminable registers were defined. */
641 #ifdef ELIMINABLE_REGS
642 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
644 ep->can_eliminate = ep->can_eliminate_previous
645 = (CAN_ELIMINATE (ep->from, ep->to)
646 && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
649 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
650 = ! frame_pointer_needed;
653 /* Count the number of eliminable registers and build the FROM and TO
654 REG rtx's. Note that code in gen_rtx will cause, e.g.,
655 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
656 We depend on this. */
657 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
659 num_eliminable += ep->can_eliminate;
660 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
661 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
664 num_labels = max_label_num () - get_first_label_num ();
666 /* Allocate the tables used to store offset information at labels. */
667 offsets_known_at = (char *) alloca (num_labels);
669 = (int (*)[NUM_ELIMINABLE_REGS])
670 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
672 offsets_known_at -= get_first_label_num ();
673 offsets_at -= get_first_label_num ();
675 /* Alter each pseudo-reg rtx to contain its hard reg number.
676 Assign stack slots to the pseudos that lack hard regs or equivalents.
677 Do not touch virtual registers. */
679 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
682 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
683 because the stack size may be a part of the offset computation for
684 register elimination. */
685 assign_stack_local (BLKmode, 0, 0);
687 /* If we have some registers we think can be eliminated, scan all insns to
688 see if there is an insn that sets one of these registers to something
689 other than itself plus a constant. If so, the register cannot be
690 eliminated. Doing this scan here eliminates an extra pass through the
691 main reload loop in the most common case where register elimination
693 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
694 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
695 || GET_CODE (insn) == CALL_INSN)
696 note_stores (PATTERN (insn), mark_not_eliminable);
698 #ifndef REGISTER_CONSTRAINTS
699 /* If all the pseudo regs have hard regs,
700 except for those that are never referenced,
701 we know that no reloads are needed. */
702 /* But that is not true if there are register constraints, since
703 in that case some pseudos might be in the wrong kind of hard reg. */
705 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
706 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
709 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
713 /* Compute the order of preference for hard registers to spill.
714 Store them by decreasing preference in potential_reload_regs. */
716 order_regs_for_reload ();
718 /* So far, no hard regs have been spilled. */
720 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
721 spill_reg_order[i] = -1;
723 /* On most machines, we can't use any register explicitly used in the
724 rtl as a spill register. But on some, we have to. Those will have
725 taken care to keep the life of hard regs as short as possible. */
727 #ifdef SMALL_REGISTER_CLASSES
728 CLEAR_HARD_REG_SET (forbidden_regs);
730 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
733 /* Spill any hard regs that we know we can't eliminate. */
734 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
735 if (! ep->can_eliminate)
737 spill_hard_reg (ep->from, global, dumpfile, 1);
738 regs_ever_live[ep->from] = 1;
742 for (i = 0; i < N_REG_CLASSES; i++)
744 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
745 bzero (basic_block_needs[i], n_basic_blocks);
748 /* This loop scans the entire function each go-round
749 and repeats until one repetition spills no additional hard regs. */
751 /* This flag is set when a pseudo reg is spilled,
752 to require another pass. Note that getting an additional reload
753 reg does not necessarily imply any pseudo reg was spilled;
754 sometimes we find a reload reg that no pseudo reg was allocated in. */
755 something_changed = 1;
756 /* This flag is set if there are any insns that require reloading. */
757 something_needs_reloads = 0;
758 /* This flag is set if there are any insns that require register
760 something_needs_elimination = 0;
761 while (something_changed)
765 /* For each class, number of reload regs needed in that class.
766 This is the maximum over all insns of the needs in that class
767 of the individual insn. */
768 int max_needs[N_REG_CLASSES];
769 /* For each class, size of group of consecutive regs
770 that is needed for the reloads of this class. */
771 int group_size[N_REG_CLASSES];
772 /* For each class, max number of consecutive groups needed.
773 (Each group contains group_size[CLASS] consecutive registers.) */
774 int max_groups[N_REG_CLASSES];
775 /* For each class, max number needed of regs that don't belong
776 to any of the groups. */
777 int max_nongroups[N_REG_CLASSES];
778 /* For each class, the machine mode which requires consecutive
779 groups of regs of that class.
780 If two different modes ever require groups of one class,
781 they must be the same size and equally restrictive for that class,
782 otherwise we can't handle the complexity. */
783 enum machine_mode group_mode[N_REG_CLASSES];
784 /* Record the insn where each maximum need is first found. */
785 rtx max_needs_insn[N_REG_CLASSES];
786 rtx max_groups_insn[N_REG_CLASSES];
787 rtx max_nongroups_insn[N_REG_CLASSES];
790 something_changed = 0;
791 bzero (max_needs, sizeof max_needs);
792 bzero (max_groups, sizeof max_groups);
793 bzero (max_nongroups, sizeof max_nongroups);
794 bzero (max_needs_insn, sizeof max_needs_insn);
795 bzero (max_groups_insn, sizeof max_groups_insn);
796 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
797 bzero (group_size, sizeof group_size);
798 for (i = 0; i < N_REG_CLASSES; i++)
799 group_mode[i] = VOIDmode;
801 /* Keep track of which basic blocks are needing the reloads. */
804 /* Remember whether any element of basic_block_needs
805 changes from 0 to 1 in this pass. */
806 new_basic_block_needs = 0;
808 /* Reset all offsets on eliminable registers to their initial values. */
809 #ifdef ELIMINABLE_REGS
810 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
812 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
813 ep->previous_offset = ep->offset
814 = ep->max_offset = ep->initial_offset;
817 #ifdef INITIAL_FRAME_POINTER_OFFSET
818 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
820 if (!FRAME_POINTER_REQUIRED)
822 reg_eliminate[0].initial_offset = 0;
824 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
825 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
828 num_not_at_initial_offset = 0;
830 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
832 /* Set a known offset for each forced label to be at the initial offset
833 of each elimination. We do this because we assume that all
834 computed jumps occur from a location where each elimination is
835 at its initial offset. */
837 for (x = forced_labels; x; x = XEXP (x, 1))
839 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
841 /* For each pseudo register that has an equivalent location defined,
842 try to eliminate any eliminable registers (such as the frame pointer)
843 assuming initial offsets for the replacement register, which
846 If the resulting location is directly addressable, substitute
847 the MEM we just got directly for the old REG.
849 If it is not addressable but is a constant or the sum of a hard reg
850 and constant, it is probably not addressable because the constant is
851 out of range, in that case record the address; we will generate
852 hairy code to compute the address in a register each time it is
855 If the location is not addressable, but does not have one of the
856 above forms, assign a stack slot. We have to do this to avoid the
857 potential of producing lots of reloads if, e.g., a location involves
858 a pseudo that didn't get a hard register and has an equivalent memory
859 location that also involves a pseudo that didn't get a hard register.
861 Perhaps at some point we will improve reload_when_needed handling
862 so this problem goes away. But that's very hairy. */
864 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
865 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
867 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
869 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
871 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
872 else if (CONSTANT_P (XEXP (x, 0))
873 || (GET_CODE (XEXP (x, 0)) == PLUS
874 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
875 && (REGNO (XEXP (XEXP (x, 0), 0))
876 < FIRST_PSEUDO_REGISTER)
877 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
878 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
881 /* Make a new stack slot. Then indicate that something
882 changed so we go back and recompute offsets for
883 eliminable registers because the allocation of memory
884 below might change some offset. reg_equiv_{mem,address}
885 will be set up for this pseudo on the next pass around
887 reg_equiv_memory_loc[i] = 0;
888 reg_equiv_init[i] = 0;
890 something_changed = 1;
894 /* If we allocated another pseudo to the stack, redo elimination
896 if (something_changed)
899 /* If caller-saves needs a group, initialize the group to include
900 the size and mode required for caller-saves. */
902 if (caller_save_group_size > 1)
904 group_mode[(int) caller_save_spill_class] = Pmode;
905 group_size[(int) caller_save_spill_class] = caller_save_group_size;
908 /* Compute the most additional registers needed by any instruction.
909 Collect information separately for each class of regs. */
911 for (insn = first; insn; insn = NEXT_INSN (insn))
913 if (global && this_block + 1 < n_basic_blocks
914 && insn == basic_block_head[this_block+1])
917 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
918 might include REG_LABEL), we need to see what effects this
919 has on the known offsets at labels. */
921 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
922 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
923 && REG_NOTES (insn) != 0))
924 set_label_offsets (insn, insn, 0);
926 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
928 /* Nonzero means don't use a reload reg that overlaps
929 the place where a function value can be returned. */
930 rtx avoid_return_reg = 0;
932 rtx old_body = PATTERN (insn);
933 int old_code = INSN_CODE (insn);
934 rtx old_notes = REG_NOTES (insn);
935 int did_elimination = 0;
937 /* Initially, count RELOAD_OTHER reloads.
938 Later, merge in the other kinds. */
939 int insn_needs[N_REG_CLASSES];
940 int insn_groups[N_REG_CLASSES];
941 int insn_total_groups = 0;
943 /* Count RELOAD_FOR_INPUT_RELOAD_ADDRESS reloads. */
944 int insn_needs_for_inputs[N_REG_CLASSES];
945 int insn_groups_for_inputs[N_REG_CLASSES];
946 int insn_total_groups_for_inputs = 0;
948 /* Count RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reloads. */
949 int insn_needs_for_outputs[N_REG_CLASSES];
950 int insn_groups_for_outputs[N_REG_CLASSES];
951 int insn_total_groups_for_outputs = 0;
953 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
954 int insn_needs_for_operands[N_REG_CLASSES];
955 int insn_groups_for_operands[N_REG_CLASSES];
956 int insn_total_groups_for_operands = 0;
958 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
959 looks for non-strict memory addresses. */
960 /* Optimization: a bit-field instruction whose field
961 happens to be a byte or halfword in memory
962 can be changed to a move instruction. */
964 if (GET_CODE (PATTERN (insn)) == SET)
966 rtx dest = SET_DEST (PATTERN (insn));
967 rtx src = SET_SRC (PATTERN (insn));
969 if (GET_CODE (dest) == ZERO_EXTRACT
970 || GET_CODE (dest) == SIGN_EXTRACT)
971 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
972 if (GET_CODE (src) == ZERO_EXTRACT
973 || GET_CODE (src) == SIGN_EXTRACT)
974 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
978 /* If needed, eliminate any eliminable registers. */
980 did_elimination = eliminate_regs_in_insn (insn, 0);
982 #ifdef SMALL_REGISTER_CLASSES
983 /* Set avoid_return_reg if this is an insn
984 that might use the value of a function call. */
985 if (GET_CODE (insn) == CALL_INSN)
987 if (GET_CODE (PATTERN (insn)) == SET)
988 after_call = SET_DEST (PATTERN (insn));
989 else if (GET_CODE (PATTERN (insn)) == PARALLEL
990 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
991 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
995 else if (after_call != 0
996 && !(GET_CODE (PATTERN (insn)) == SET
997 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
999 if (reg_mentioned_p (after_call, PATTERN (insn)))
1000 avoid_return_reg = after_call;
1003 #endif /* SMALL_REGISTER_CLASSES */
1005 /* Analyze the instruction. */
1006 find_reloads (insn, 0, spill_indirect_levels, global,
1009 /* Remember for later shortcuts which insns had any reloads or
1010 register eliminations.
1012 One might think that it would be worthwhile to mark insns
1013 that need register replacements but not reloads, but this is
1014 not safe because find_reloads may do some manipulation of
1015 the insn (such as swapping commutative operands), which would
1016 be lost when we restore the old pattern after register
1017 replacement. So the actions of find_reloads must be redone in
1018 subsequent passes or in reload_as_needed.
1020 However, it is safe to mark insns that need reloads
1021 but not register replacement. */
1023 PUT_MODE (insn, (did_elimination ? QImode
1024 : n_reloads ? HImode
1027 /* Discard any register replacements done. */
1028 if (did_elimination)
1030 obstack_free (&reload_obstack, reload_firstobj);
1031 PATTERN (insn) = old_body;
1032 INSN_CODE (insn) = old_code;
1033 REG_NOTES (insn) = old_notes;
1034 something_needs_elimination = 1;
1037 /* If this insn has no reloads, we need not do anything except
1038 in the case of a CALL_INSN when we have caller-saves and
1039 caller-save needs reloads. */
1042 && ! (GET_CODE (insn) == CALL_INSN
1043 && caller_save_spill_class != NO_REGS))
1046 something_needs_reloads = 1;
1048 for (i = 0; i < N_REG_CLASSES; i++)
1050 insn_needs[i] = 0, insn_groups[i] = 0;
1051 insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1052 insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1053 insn_needs_for_operands[i] = 0, insn_groups_for_operands[i] = 0;
1056 /* Count each reload once in every class
1057 containing the reload's own class. */
1059 for (i = 0; i < n_reloads; i++)
1061 register enum reg_class *p;
1062 enum reg_class class = reload_reg_class[i];
1064 enum machine_mode mode;
1067 int *this_total_groups;
1069 /* Don't count the dummy reloads, for which one of the
1070 regs mentioned in the insn can be used for reloading.
1071 Don't count optional reloads.
1072 Don't count reloads that got combined with others. */
1073 if (reload_reg_rtx[i] != 0
1074 || reload_optional[i] != 0
1075 || (reload_out[i] == 0 && reload_in[i] == 0
1076 && ! reload_secondary_p[i]))
1079 /* Show that a reload register of this class is needed
1080 in this basic block. We do not use insn_needs and
1081 insn_groups because they are overly conservative for
1083 if (global && ! basic_block_needs[(int) class][this_block])
1085 basic_block_needs[(int) class][this_block] = 1;
1086 new_basic_block_needs = 1;
1089 /* Decide which time-of-use to count this reload for. */
1090 switch (reload_when_needed[i])
1093 case RELOAD_FOR_OUTPUT:
1094 case RELOAD_FOR_INPUT:
1095 this_needs = insn_needs;
1096 this_groups = insn_groups;
1097 this_total_groups = &insn_total_groups;
1100 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
1101 this_needs = insn_needs_for_inputs;
1102 this_groups = insn_groups_for_inputs;
1103 this_total_groups = &insn_total_groups_for_inputs;
1106 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
1107 this_needs = insn_needs_for_outputs;
1108 this_groups = insn_groups_for_outputs;
1109 this_total_groups = &insn_total_groups_for_outputs;
1112 case RELOAD_FOR_OPERAND_ADDRESS:
1113 this_needs = insn_needs_for_operands;
1114 this_groups = insn_groups_for_operands;
1115 this_total_groups = &insn_total_groups_for_operands;
1119 mode = reload_inmode[i];
1120 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1121 mode = reload_outmode[i];
1122 size = CLASS_MAX_NREGS (class, mode);
1125 enum machine_mode other_mode, allocate_mode;
1127 /* Count number of groups needed separately from
1128 number of individual regs needed. */
1129 this_groups[(int) class]++;
1130 p = reg_class_superclasses[(int) class];
1131 while (*p != LIM_REG_CLASSES)
1132 this_groups[(int) *p++]++;
1133 (*this_total_groups)++;
1135 /* Record size and mode of a group of this class. */
1136 /* If more than one size group is needed,
1137 make all groups the largest needed size. */
1138 if (group_size[(int) class] < size)
1140 other_mode = group_mode[(int) class];
1141 allocate_mode = mode;
1143 group_size[(int) class] = size;
1144 group_mode[(int) class] = mode;
1149 allocate_mode = group_mode[(int) class];
1152 /* Crash if two dissimilar machine modes both need
1153 groups of consecutive regs of the same class. */
1155 if (other_mode != VOIDmode
1156 && other_mode != allocate_mode
1157 && ! modes_equiv_for_class_p (allocate_mode,
1164 this_needs[(int) class] += 1;
1165 p = reg_class_superclasses[(int) class];
1166 while (*p != LIM_REG_CLASSES)
1167 this_needs[(int) *p++] += 1;
1173 /* All reloads have been counted for this insn;
1174 now merge the various times of use.
1175 This sets insn_needs, etc., to the maximum total number
1176 of registers needed at any point in this insn. */
1178 for (i = 0; i < N_REG_CLASSES; i++)
1181 this_max = insn_needs_for_inputs[i];
1182 if (insn_needs_for_outputs[i] > this_max)
1183 this_max = insn_needs_for_outputs[i];
1184 if (insn_needs_for_operands[i] > this_max)
1185 this_max = insn_needs_for_operands[i];
1186 insn_needs[i] += this_max;
1187 this_max = insn_groups_for_inputs[i];
1188 if (insn_groups_for_outputs[i] > this_max)
1189 this_max = insn_groups_for_outputs[i];
1190 if (insn_groups_for_operands[i] > this_max)
1191 this_max = insn_groups_for_operands[i];
1192 insn_groups[i] += this_max;
1195 insn_total_groups += MAX (insn_total_groups_for_inputs,
1196 MAX (insn_total_groups_for_outputs,
1197 insn_total_groups_for_operands));
1199 /* If this is a CALL_INSN and caller-saves will need
1200 a spill register, act as if the spill register is
1201 needed for this insn. However, the spill register
1202 can be used by any reload of this insn, so we only
1203 need do something if no need for that class has
1206 The assumption that every CALL_INSN will trigger a
1207 caller-save is highly conservative, however, the number
1208 of cases where caller-saves will need a spill register but
1209 a block containing a CALL_INSN won't need a spill register
1210 of that class should be quite rare.
1212 If a group is needed, the size and mode of the group will
1213 have been set up at the beginning of this loop. */
1215 if (GET_CODE (insn) == CALL_INSN
1216 && caller_save_spill_class != NO_REGS)
1218 int *caller_save_needs
1219 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1221 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1223 register enum reg_class *p
1224 = reg_class_superclasses[(int) caller_save_spill_class];
1226 caller_save_needs[(int) caller_save_spill_class]++;
1228 while (*p != LIM_REG_CLASSES)
1229 caller_save_needs[(int) *p++] += 1;
1232 if (caller_save_group_size > 1)
1233 insn_total_groups = MAX (insn_total_groups, 1);
1236 /* Show that this basic block will need a register of
1240 && ! (basic_block_needs[(int) caller_save_spill_class]
1243 basic_block_needs[(int) caller_save_spill_class]
1245 new_basic_block_needs = 1;
1249 #ifdef SMALL_REGISTER_CLASSES
1250 /* If this insn stores the value of a function call,
1251 and that value is in a register that has been spilled,
1252 and if the insn needs a reload in a class
1253 that might use that register as the reload register,
1254 then add add an extra need in that class.
1255 This makes sure we have a register available that does
1256 not overlap the return value. */
1257 if (avoid_return_reg)
1259 int regno = REGNO (avoid_return_reg);
1261 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1264 for (r = regno; r < regno + nregs; r++)
1265 if (spill_reg_order[r] >= 0)
1266 for (i = 0; i < N_REG_CLASSES; i++)
1267 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1269 if (insn_needs[i] > 0)
1271 if (insn_groups[i] > 0
1278 #endif /* SMALL_REGISTER_CLASSES */
1280 /* For each class, collect maximum need of any insn. */
1282 for (i = 0; i < N_REG_CLASSES; i++)
1284 if (max_needs[i] < insn_needs[i])
1286 max_needs[i] = insn_needs[i];
1287 max_needs_insn[i] = insn;
1289 if (max_groups[i] < insn_groups[i])
1291 max_groups[i] = insn_groups[i];
1292 max_groups_insn[i] = insn;
1294 if (insn_total_groups > 0)
1295 if (max_nongroups[i] < insn_needs[i])
1297 max_nongroups[i] = insn_needs[i];
1298 max_nongroups_insn[i] = insn;
1302 /* Note that there is a continue statement above. */
1305 /* If we have caller-saves, set up the save areas and see if caller-save
1306 will need a spill register. */
1308 if (caller_save_needed
1309 && ! setup_save_areas (&something_changed)
1310 && caller_save_spill_class == NO_REGS)
1312 /* The class we will need depends on whether the machine
1313 supports the sum of two registers for an address; see
1314 find_address_reloads for details. */
1316 caller_save_spill_class
1317 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1318 caller_save_group_size
1319 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1320 something_changed = 1;
1323 /* Now deduct from the needs for the registers already
1324 available (already spilled). */
1326 CLEAR_HARD_REG_SET (counted_for_groups);
1327 CLEAR_HARD_REG_SET (counted_for_nongroups);
1329 /* First find all regs alone in their class
1330 and count them (if desired) for non-groups.
1331 We would be screwed if a group took the only reg in a class
1332 for which a non-group reload is needed.
1333 (Note there is still a bug; if a class has 2 regs,
1334 both could be stolen by groups and we would lose the same way.
1335 With luck, no machine will need a nongroup in a 2-reg class.) */
1337 for (i = 0; i < n_spills; i++)
1339 register enum reg_class *p;
1340 class = (int) REGNO_REG_CLASS (spill_regs[i]);
1342 if (reg_class_size[class] == 1 && max_nongroups[class] > 0)
1345 p = reg_class_superclasses[class];
1346 while (*p != LIM_REG_CLASSES)
1347 max_needs[(int) *p++]--;
1349 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1350 max_nongroups[class]--;
1351 p = reg_class_superclasses[class];
1352 while (*p != LIM_REG_CLASSES)
1354 if (max_nongroups[(int) *p] > 0)
1355 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1356 max_nongroups[(int) *p++]--;
1361 /* Now find all consecutive groups of spilled registers
1362 and mark each group off against the need for such groups.
1363 But don't count them against ordinary need, yet. */
1365 count_possible_groups (group_size, group_mode, max_groups);
1367 /* Now count all spill regs against the individual need,
1368 This includes those counted above for groups,
1369 but not those previously counted for nongroups.
1371 Those that weren't counted_for_groups can also count against
1372 the not-in-group need. */
1374 for (i = 0; i < n_spills; i++)
1376 register enum reg_class *p;
1377 class = (int) REGNO_REG_CLASS (spill_regs[i]);
1379 /* Those counted at the beginning shouldn't be counted twice. */
1380 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
1383 p = reg_class_superclasses[class];
1384 while (*p != LIM_REG_CLASSES)
1385 max_needs[(int) *p++]--;
1387 if (! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i]))
1389 if (max_nongroups[class] > 0)
1390 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1391 max_nongroups[class]--;
1392 p = reg_class_superclasses[class];
1393 while (*p != LIM_REG_CLASSES)
1395 if (max_nongroups[(int) *p] > 0)
1396 SET_HARD_REG_BIT (counted_for_nongroups,
1398 max_nongroups[(int) *p++]--;
1404 /* See if anything that happened changes which eliminations are valid.
1405 For example, on the Sparc, whether or not the frame pointer can
1406 be eliminated can depend on what registers have been used. We need
1407 not check some conditions again (such as flag_omit_frame_pointer)
1408 since they can't have changed. */
1410 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1411 if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1412 #ifdef ELIMINABLE_REGS
1413 || ! CAN_ELIMINATE (ep->from, ep->to)
1416 ep->can_eliminate = 0;
1418 /* Look for the case where we have discovered that we can't replace
1419 register A with register B and that means that we will now be
1420 trying to replace register A with register C. This means we can
1421 no longer replace register C with register B and we need to disable
1422 such an elimination, if it exists. This occurs often with A == ap,
1423 B == sp, and C == fp. */
1425 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1427 struct elim_table *op;
1428 register int new_to = -1;
1430 if (! ep->can_eliminate && ep->can_eliminate_previous)
1432 /* Find the current elimination for ep->from, if there is a
1434 for (op = reg_eliminate;
1435 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1436 if (op->from == ep->from && op->can_eliminate)
1442 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1444 for (op = reg_eliminate;
1445 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1446 if (op->from == new_to && op->to == ep->to)
1447 op->can_eliminate = 0;
1451 /* See if any registers that we thought we could eliminate the previous
1452 time are no longer eliminable. If so, something has changed and we
1453 must spill the register. Also, recompute the number of eliminable
1454 registers and see if the frame pointer is needed; it is if there is
1455 no elimination of the frame pointer that we can perform. */
1457 frame_pointer_needed = 1;
1458 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1460 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1461 frame_pointer_needed = 0;
1463 if (! ep->can_eliminate && ep->can_eliminate_previous)
1465 ep->can_eliminate_previous = 0;
1466 spill_hard_reg (ep->from, global, dumpfile, 1);
1467 regs_ever_live[ep->from] = 1;
1468 something_changed = 1;
1473 /* If all needs are met, we win. */
1475 for (i = 0; i < N_REG_CLASSES; i++)
1476 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1478 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1481 /* Not all needs are met; must spill more hard regs. */
1483 /* If any element of basic_block_needs changed from 0 to 1,
1484 re-spill all the regs already spilled. This may spill
1485 additional pseudos that didn't spill before. */
1487 if (new_basic_block_needs)
1488 for (i = 0; i < n_spills; i++)
1490 |= spill_hard_reg (spill_regs[i], global, dumpfile, 0);
1492 /* Now find more reload regs to satisfy the remaining need
1493 Do it by ascending class number, since otherwise a reg
1494 might be spilled for a big class and might fail to count
1495 for a smaller class even though it belongs to that class.
1497 Count spilled regs in `spills', and add entries to
1498 `spill_regs' and `spill_reg_order'.
1500 ??? Note there is a problem here.
1501 When there is a need for a group in a high-numbered class,
1502 and also need for non-group regs that come from a lower class,
1503 the non-group regs are chosen first. If there aren't many regs,
1504 they might leave no room for a group.
1506 This was happening on the 386. To fix it, we added the code
1507 that calls possible_group_p, so that the lower class won't
1508 break up the last possible group.
1510 Really fixing the problem would require changes above
1511 in counting the regs already spilled, and in choose_reload_regs.
1512 It might be hard to avoid introducing bugs there. */
1514 for (class = 0; class < N_REG_CLASSES; class++)
1516 /* First get the groups of registers.
1517 If we got single registers first, we might fragment
1519 while (max_groups[class] > 0)
1521 /* If any single spilled regs happen to form groups,
1522 count them now. Maybe we don't really need
1523 to spill another group. */
1524 count_possible_groups (group_size, group_mode, max_groups);
1526 /* Groups of size 2 (the only groups used on most machines)
1527 are treated specially. */
1528 if (group_size[class] == 2)
1530 /* First, look for a register that will complete a group. */
1531 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1533 int j = potential_reload_regs[i];
1535 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1537 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1538 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1539 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1540 && HARD_REGNO_MODE_OK (other, group_mode[class])
1541 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1543 /* We don't want one part of another group.
1544 We could get "two groups" that overlap! */
1545 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1547 (j < FIRST_PSEUDO_REGISTER - 1
1548 && (other = j + 1, spill_reg_order[other] >= 0)
1549 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1550 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1551 && HARD_REGNO_MODE_OK (j, group_mode[class])
1552 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1554 && ! TEST_HARD_REG_BIT (counted_for_groups,
1557 register enum reg_class *p;
1559 /* We have found one that will complete a group,
1560 so count off one group as provided. */
1561 max_groups[class]--;
1562 p = reg_class_superclasses[class];
1563 while (*p != LIM_REG_CLASSES)
1564 max_groups[(int) *p++]--;
1566 /* Indicate both these regs are part of a group. */
1567 SET_HARD_REG_BIT (counted_for_groups, j);
1568 SET_HARD_REG_BIT (counted_for_groups, other);
1572 /* We can't complete a group, so start one. */
1573 if (i == FIRST_PSEUDO_REGISTER)
1574 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1576 int j = potential_reload_regs[i];
1577 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1578 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1579 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1580 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1581 && HARD_REGNO_MODE_OK (j, group_mode[class])
1582 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1587 /* I should be the index in potential_reload_regs
1588 of the new reload reg we have found. */
1590 if (i >= FIRST_PSEUDO_REGISTER)
1592 /* There are no groups left to spill. */
1593 spill_failure (max_groups_insn[class]);
1599 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1604 /* For groups of more than 2 registers,
1605 look for a sufficient sequence of unspilled registers,
1606 and spill them all at once. */
1607 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1609 int j = potential_reload_regs[i];
1611 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1612 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1614 /* Check each reg in the sequence. */
1615 for (k = 0; k < group_size[class]; k++)
1616 if (! (spill_reg_order[j + k] < 0
1617 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1618 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1620 /* We got a full sequence, so spill them all. */
1621 if (k == group_size[class])
1623 register enum reg_class *p;
1624 for (k = 0; k < group_size[class]; k++)
1627 SET_HARD_REG_BIT (counted_for_groups, j + k);
1628 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1629 if (potential_reload_regs[idx] == j + k)
1631 if (i >= FIRST_PSEUDO_REGISTER)
1633 /* There are no groups left. */
1634 spill_failure (max_groups_insn[class]);
1640 |= new_spill_reg (idx, class,
1641 max_needs, NULL_PTR,
1645 /* We have found one that will complete a group,
1646 so count off one group as provided. */
1647 max_groups[class]--;
1648 p = reg_class_superclasses[class];
1649 while (*p != LIM_REG_CLASSES)
1650 max_groups[(int) *p++]--;
1656 /* We couldn't find any registers for this reload.
1657 Abort to avoid going into an infinite loop. */
1658 if (i == FIRST_PSEUDO_REGISTER)
1663 /* Now similarly satisfy all need for single registers. */
1665 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1667 /* Consider the potential reload regs that aren't
1668 yet in use as reload regs, in order of preference.
1669 Find the most preferred one that's in this class. */
1671 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1672 if (potential_reload_regs[i] >= 0
1673 && TEST_HARD_REG_BIT (reg_class_contents[class],
1674 potential_reload_regs[i])
1675 /* If this reg will not be available for groups,
1676 pick one that does not foreclose possible groups.
1677 This is a kludge, and not very general,
1678 but it should be sufficient to make the 386 work,
1679 and the problem should not occur on machines with
1681 && (max_nongroups[class] == 0
1682 || possible_group_p (potential_reload_regs[i], max_groups)))
1685 /* I should be the index in potential_reload_regs
1686 of the new reload reg we have found. */
1688 if (i >= FIRST_PSEUDO_REGISTER)
1690 /* There are no possible registers left to spill. */
1691 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1692 : max_nongroups_insn[class]);
1698 |= new_spill_reg (i, class, max_needs, max_nongroups,
1704 /* If global-alloc was run, notify it of any register eliminations we have
1707 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1708 if (ep->can_eliminate)
1709 mark_elimination (ep->from, ep->to);
1711 /* From now on, we need to emit any moves without making new pseudos. */
1712 reload_in_progress = 1;
1714 /* Insert code to save and restore call-clobbered hard regs
1715 around calls. Tell if what mode to use so that we will process
1716 those insns in reload_as_needed if we have to. */
1718 if (caller_save_needed)
1719 save_call_clobbered_regs (num_eliminable ? QImode
1720 : caller_save_spill_class != NO_REGS ? HImode
1723 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1724 If that insn didn't set the register (i.e., it copied the register to
1725 memory), just delete that insn instead of the equivalencing insn plus
1726 anything now dead. If we call delete_dead_insn on that insn, we may
1727 delete the insn that actually sets the register if the register die
1728 there and that is incorrect. */
1730 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1731 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1732 && GET_CODE (reg_equiv_init[i]) != NOTE)
1734 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1735 delete_dead_insn (reg_equiv_init[i]);
1738 PUT_CODE (reg_equiv_init[i], NOTE);
1739 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1740 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1744 /* Use the reload registers where necessary
1745 by generating move instructions to move the must-be-register
1746 values into or out of the reload registers. */
1748 if (something_needs_reloads || something_needs_elimination
1749 || (caller_save_needed && num_eliminable)
1750 || caller_save_spill_class != NO_REGS)
1751 reload_as_needed (first, global);
1753 reload_in_progress = 0;
1755 /* Come here (with failure set nonzero) if we can't get enough spill regs
1756 and we decide not to abort about it. */
1759 /* Now eliminate all pseudo regs by modifying them into
1760 their equivalent memory references.
1761 The REG-rtx's for the pseudos are modified in place,
1762 so all insns that used to refer to them now refer to memory.
1764 For a reg that has a reg_equiv_address, all those insns
1765 were changed by reloading so that no insns refer to it any longer;
1766 but the DECL_RTL of a variable decl may refer to it,
1767 and if so this causes the debugging info to mention the variable. */
1769 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1773 if (reg_equiv_mem[i])
1775 addr = XEXP (reg_equiv_mem[i], 0);
1776 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1778 if (reg_equiv_address[i])
1779 addr = reg_equiv_address[i];
1782 if (reg_renumber[i] < 0)
1784 rtx reg = regno_reg_rtx[i];
1785 XEXP (reg, 0) = addr;
1786 REG_USERVAR_P (reg) = 0;
1787 MEM_IN_STRUCT_P (reg) = in_struct;
1788 PUT_CODE (reg, MEM);
1790 else if (reg_equiv_mem[i])
1791 XEXP (reg_equiv_mem[i], 0) = addr;
1795 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1796 /* Make a pass over all the insns and remove death notes for things that
1797 are no longer registers or no longer die in the insn (e.g., an input
1798 and output pseudo being tied). */
1800 for (insn = first; insn; insn = NEXT_INSN (insn))
1801 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1805 for (note = REG_NOTES (insn); note; note = next)
1807 next = XEXP (note, 1);
1808 if (REG_NOTE_KIND (note) == REG_DEAD
1809 && (GET_CODE (XEXP (note, 0)) != REG
1810 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1811 remove_note (insn, note);
1816 /* Indicate that we no longer have known memory locations or constants. */
1817 reg_equiv_constant = 0;
1818 reg_equiv_memory_loc = 0;
1823 /* Nonzero if, after spilling reg REGNO for non-groups,
1824 it will still be possible to find a group if we still need one. */
1827 possible_group_p (regno, max_groups)
1832 int class = (int) NO_REGS;
1834 for (i = 0; i < (int) N_REG_CLASSES; i++)
1835 if (max_groups[i] > 0)
1841 if (class == (int) NO_REGS)
1844 /* Consider each pair of consecutive registers. */
1845 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1847 /* Ignore pairs that include reg REGNO. */
1848 if (i == regno || i + 1 == regno)
1851 /* Ignore pairs that are outside the class that needs the group.
1852 ??? Here we fail to handle the case where two different classes
1853 independently need groups. But this never happens with our
1854 current machine descriptions. */
1855 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1856 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
1859 /* A pair of consecutive regs we can still spill does the trick. */
1860 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
1861 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1862 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
1865 /* A pair of one already spilled and one we can spill does it
1866 provided the one already spilled is not otherwise reserved. */
1867 if (spill_reg_order[i] < 0
1868 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1869 && spill_reg_order[i + 1] >= 0
1870 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
1871 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
1873 if (spill_reg_order[i + 1] < 0
1874 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
1875 && spill_reg_order[i] >= 0
1876 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
1877 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
1884 /* Count any groups that can be formed from the registers recently spilled.
1885 This is done class by class, in order of ascending class number. */
1888 count_possible_groups (group_size, group_mode, max_groups)
1889 int *group_size, *max_groups;
1890 enum machine_mode *group_mode;
1893 /* Now find all consecutive groups of spilled registers
1894 and mark each group off against the need for such groups.
1895 But don't count them against ordinary need, yet. */
1897 for (i = 0; i < N_REG_CLASSES; i++)
1898 if (group_size[i] > 1)
1900 char regmask[FIRST_PSEUDO_REGISTER];
1903 bzero (regmask, sizeof regmask);
1904 /* Make a mask of all the regs that are spill regs in class I. */
1905 for (j = 0; j < n_spills; j++)
1906 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
1907 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
1908 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1910 regmask[spill_regs[j]] = 1;
1911 /* Find each consecutive group of them. */
1912 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
1913 if (regmask[j] && j + group_size[i] <= FIRST_PSEUDO_REGISTER
1914 /* Next line in case group-mode for this class
1915 demands an even-odd pair. */
1916 && HARD_REGNO_MODE_OK (j, group_mode[i]))
1919 for (k = 1; k < group_size[i]; k++)
1920 if (! regmask[j + k])
1922 if (k == group_size[i])
1924 /* We found a group. Mark it off against this class's
1925 need for groups, and against each superclass too. */
1926 register enum reg_class *p;
1928 p = reg_class_superclasses[i];
1929 while (*p != LIM_REG_CLASSES)
1930 max_groups[(int) *p++]--;
1931 /* Don't count these registers again. */
1932 for (k = 0; k < group_size[i]; k++)
1933 SET_HARD_REG_BIT (counted_for_groups, j + k);
1935 /* Skip to the last reg in this group. When j is incremented
1936 above, it will then point to the first reg of the next
1944 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
1945 another mode that needs to be reloaded for the same register class CLASS.
1946 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
1947 ALLOCATE_MODE will never be smaller than OTHER_MODE.
1949 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
1950 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
1951 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
1952 causes unnecessary failures on machines requiring alignment of register
1953 groups when the two modes are different sizes, because the larger mode has
1954 more strict alignment rules than the smaller mode. */
1957 modes_equiv_for_class_p (allocate_mode, other_mode, class)
1958 enum machine_mode allocate_mode, other_mode;
1959 enum reg_class class;
1962 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1964 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
1965 && HARD_REGNO_MODE_OK (regno, allocate_mode)
1966 && ! HARD_REGNO_MODE_OK (regno, other_mode))
1972 /* Handle the failure to find a register to spill.
1973 INSN should be one of the insns which needed this particular spill reg. */
1976 spill_failure (insn)
1979 if (asm_noperands (PATTERN (insn)) >= 0)
1980 error_for_asm (insn, "`asm' needs too many reloads");
1985 /* Add a new register to the tables of available spill-registers
1986 (as well as spilling all pseudos allocated to the register).
1987 I is the index of this register in potential_reload_regs.
1988 CLASS is the regclass whose need is being satisfied.
1989 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
1990 so that this register can count off against them.
1991 MAX_NONGROUPS is 0 if this register is part of a group.
1992 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
1995 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2003 register enum reg_class *p;
2005 int regno = potential_reload_regs[i];
2007 if (i >= FIRST_PSEUDO_REGISTER)
2008 abort (); /* Caller failed to find any register. */
2010 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2011 fatal ("fixed or forbidden register was spilled.\n\
2012 This may be due to a compiler bug or to impossible asm statements.");
2014 /* Make reg REGNO an additional reload reg. */
2016 potential_reload_regs[i] = -1;
2017 spill_regs[n_spills] = regno;
2018 spill_reg_order[regno] = n_spills;
2020 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2022 /* Clear off the needs we just satisfied. */
2025 p = reg_class_superclasses[class];
2026 while (*p != LIM_REG_CLASSES)
2027 max_needs[(int) *p++]--;
2029 if (max_nongroups && max_nongroups[class] > 0)
2031 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2032 max_nongroups[class]--;
2033 p = reg_class_superclasses[class];
2034 while (*p != LIM_REG_CLASSES)
2035 max_nongroups[(int) *p++]--;
2038 /* Spill every pseudo reg that was allocated to this reg
2039 or to something that overlaps this reg. */
2041 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2043 /* If there are some registers still to eliminate and this register
2044 wasn't ever used before, additional stack space may have to be
2045 allocated to store this register. Thus, we may have changed the offset
2046 between the stack and frame pointers, so mark that something has changed.
2047 (If new pseudos were spilled, thus requiring more space, VAL would have
2048 been set non-zero by the call to spill_hard_reg above since additional
2049 reloads may be needed in that case.
2051 One might think that we need only set VAL to 1 if this is a call-used
2052 register. However, the set of registers that must be saved by the
2053 prologue is not identical to the call-used set. For example, the
2054 register used by the call insn for the return PC is a call-used register,
2055 but must be saved by the prologue. */
2056 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2059 regs_ever_live[spill_regs[n_spills]] = 1;
2065 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2066 data that is dead in INSN. */
2069 delete_dead_insn (insn)
2072 rtx prev = prev_real_insn (insn);
2075 /* If the previous insn sets a register that dies in our insn, delete it
2077 if (prev && GET_CODE (PATTERN (prev)) == SET
2078 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2079 && reg_mentioned_p (prev_dest, PATTERN (insn))
2080 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2081 delete_dead_insn (prev);
2083 PUT_CODE (insn, NOTE);
2084 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2085 NOTE_SOURCE_FILE (insn) = 0;
2088 /* Modify the home of pseudo-reg I.
2089 The new home is present in reg_renumber[I].
2091 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2092 or it may be -1, meaning there is none or it is not relevant.
2093 This is used so that all pseudos spilled from a given hard reg
2094 can share one stack slot. */
2097 alter_reg (i, from_reg)
2101 /* When outputting an inline function, this can happen
2102 for a reg that isn't actually used. */
2103 if (regno_reg_rtx[i] == 0)
2106 /* If the reg got changed to a MEM at rtl-generation time,
2108 if (GET_CODE (regno_reg_rtx[i]) != REG)
2111 /* Modify the reg-rtx to contain the new hard reg
2112 number or else to contain its pseudo reg number. */
2113 REGNO (regno_reg_rtx[i])
2114 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2116 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2117 allocate a stack slot for it. */
2119 if (reg_renumber[i] < 0
2120 && reg_n_refs[i] > 0
2121 && reg_equiv_constant[i] == 0
2122 && reg_equiv_memory_loc[i] == 0)
2125 int inherent_size = PSEUDO_REGNO_BYTES (i);
2126 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2129 /* Each pseudo reg has an inherent size which comes from its own mode,
2130 and a total size which provides room for paradoxical subregs
2131 which refer to the pseudo reg in wider modes.
2133 We can use a slot already allocated if it provides both
2134 enough inherent space and enough total space.
2135 Otherwise, we allocate a new slot, making sure that it has no less
2136 inherent space, and no less total space, then the previous slot. */
2139 /* No known place to spill from => no slot to reuse. */
2140 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2141 #if BYTES_BIG_ENDIAN
2142 /* Cancel the big-endian correction done in assign_stack_local.
2143 Get the address of the beginning of the slot.
2144 This is so we can do a big-endian correction unconditionally
2146 adjust = inherent_size - total_size;
2149 /* Reuse a stack slot if possible. */
2150 else if (spill_stack_slot[from_reg] != 0
2151 && spill_stack_slot_width[from_reg] >= total_size
2152 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2154 x = spill_stack_slot[from_reg];
2155 /* Allocate a bigger slot. */
2158 /* Compute maximum size needed, both for inherent size
2159 and for total size. */
2160 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2161 if (spill_stack_slot[from_reg])
2163 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2165 mode = GET_MODE (spill_stack_slot[from_reg]);
2166 if (spill_stack_slot_width[from_reg] > total_size)
2167 total_size = spill_stack_slot_width[from_reg];
2169 /* Make a slot with that size. */
2170 x = assign_stack_local (mode, total_size, -1);
2171 #if BYTES_BIG_ENDIAN
2172 /* Cancel the big-endian correction done in assign_stack_local.
2173 Get the address of the beginning of the slot.
2174 This is so we can do a big-endian correction unconditionally
2176 adjust = GET_MODE_SIZE (mode) - total_size;
2178 spill_stack_slot[from_reg] = x;
2179 spill_stack_slot_width[from_reg] = total_size;
2182 #if BYTES_BIG_ENDIAN
2183 /* On a big endian machine, the "address" of the slot
2184 is the address of the low part that fits its inherent mode. */
2185 if (inherent_size < total_size)
2186 adjust += (total_size - inherent_size);
2187 #endif /* BYTES_BIG_ENDIAN */
2189 /* If we have any adjustment to make, or if the stack slot is the
2190 wrong mode, make a new stack slot. */
2191 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2193 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2194 plus_constant (XEXP (x, 0), adjust));
2195 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2198 /* Save the stack slot for later. */
2199 reg_equiv_memory_loc[i] = x;
2203 /* Mark the slots in regs_ever_live for the hard regs
2204 used by pseudo-reg number REGNO. */
2207 mark_home_live (regno)
2210 register int i, lim;
2211 i = reg_renumber[regno];
2214 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2216 regs_ever_live[i++] = 1;
2219 /* This function handles the tracking of elimination offsets around branches.
2221 X is a piece of RTL being scanned.
2223 INSN is the insn that it came from, if any.
2225 INITIAL_P is non-zero if we are to set the offset to be the initial
2226 offset and zero if we are setting the offset of the label to be the
2230 set_label_offsets (x, insn, initial_p)
2235 enum rtx_code code = GET_CODE (x);
2238 struct elim_table *p;
2245 /* ... fall through ... */
2248 /* If we know nothing about this label, set the desired offsets. Note
2249 that this sets the offset at a label to be the offset before a label
2250 if we don't know anything about the label. This is not correct for
2251 the label after a BARRIER, but is the best guess we can make. If
2252 we guessed wrong, we will suppress an elimination that might have
2253 been possible had we been able to guess correctly. */
2255 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2257 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2258 offsets_at[CODE_LABEL_NUMBER (x)][i]
2259 = (initial_p ? reg_eliminate[i].initial_offset
2260 : reg_eliminate[i].offset);
2261 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2264 /* Otherwise, if this is the definition of a label and it is
2265 preceded by a BARRIER, set our offsets to the known offset of
2269 && (tem = prev_nonnote_insn (insn)) != 0
2270 && GET_CODE (tem) == BARRIER)
2272 num_not_at_initial_offset = 0;
2273 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2275 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2276 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2277 if (reg_eliminate[i].can_eliminate
2278 && (reg_eliminate[i].offset
2279 != reg_eliminate[i].initial_offset))
2280 num_not_at_initial_offset++;
2285 /* If neither of the above cases is true, compare each offset
2286 with those previously recorded and suppress any eliminations
2287 where the offsets disagree. */
2289 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2290 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2291 != (initial_p ? reg_eliminate[i].initial_offset
2292 : reg_eliminate[i].offset))
2293 reg_eliminate[i].can_eliminate = 0;
2298 set_label_offsets (PATTERN (insn), insn, initial_p);
2300 /* ... fall through ... */
2304 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2305 and hence must have all eliminations at their initial offsets. */
2306 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2307 if (REG_NOTE_KIND (tem) == REG_LABEL)
2308 set_label_offsets (XEXP (tem, 0), insn, 1);
2313 /* Each of the labels in the address vector must be at their initial
2314 offsets. We want the first first for ADDR_VEC and the second
2315 field for ADDR_DIFF_VEC. */
2317 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2318 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2323 /* We only care about setting PC. If the source is not RETURN,
2324 IF_THEN_ELSE, or a label, disable any eliminations not at
2325 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2326 isn't one of those possibilities. For branches to a label,
2327 call ourselves recursively.
2329 Note that this can disable elimination unnecessarily when we have
2330 a non-local goto since it will look like a non-constant jump to
2331 someplace in the current function. This isn't a significant
2332 problem since such jumps will normally be when all elimination
2333 pairs are back to their initial offsets. */
2335 if (SET_DEST (x) != pc_rtx)
2338 switch (GET_CODE (SET_SRC (x)))
2345 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2349 tem = XEXP (SET_SRC (x), 1);
2350 if (GET_CODE (tem) == LABEL_REF)
2351 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2352 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2355 tem = XEXP (SET_SRC (x), 2);
2356 if (GET_CODE (tem) == LABEL_REF)
2357 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2358 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2363 /* If we reach here, all eliminations must be at their initial
2364 offset because we are doing a jump to a variable address. */
2365 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2366 if (p->offset != p->initial_offset)
2367 p->can_eliminate = 0;
2371 /* Used for communication between the next two function to properly share
2372 the vector for an ASM_OPERANDS. */
2374 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2376 /* Scan X and replace any eliminable registers (such as fp) with a
2377 replacement (such as sp), plus an offset.
2379 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2380 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2381 MEM, we are allowed to replace a sum of a register and the constant zero
2382 with the register, which we cannot do outside a MEM. In addition, we need
2383 to record the fact that a register is referenced outside a MEM.
2385 If INSN is nonzero, it is the insn containing X. If we replace a REG
2386 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2387 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2388 that the REG is being modified.
2390 If we see a modification to a register we know about, take the
2391 appropriate action (see case SET, below).
2393 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2394 replacements done assuming all offsets are at their initial values. If
2395 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2396 encounter, return the actual location so that find_reloads will do
2397 the proper thing. */
2400 eliminate_regs (x, mem_mode, insn)
2402 enum machine_mode mem_mode;
2405 enum rtx_code code = GET_CODE (x);
2406 struct elim_table *ep;
2431 /* First handle the case where we encounter a bare register that
2432 is eliminable. Replace it with a PLUS. */
2433 if (regno < FIRST_PSEUDO_REGISTER)
2435 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2437 if (ep->from_rtx == x && ep->can_eliminate)
2440 ep->ref_outside_mem = 1;
2441 return plus_constant (ep->to_rtx, ep->previous_offset);
2445 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2446 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2448 /* In this case, find_reloads would attempt to either use an
2449 incorrect address (if something is not at its initial offset)
2450 or substitute an replaced address into an insn (which loses
2451 if the offset is changed by some later action). So we simply
2452 return the replaced stack slot (assuming it is changed by
2453 elimination) and ignore the fact that this is actually a
2454 reference to the pseudo. Ensure we make a copy of the
2455 address in case it is shared. */
2456 new = eliminate_regs (reg_equiv_memory_loc[regno],
2457 mem_mode, NULL_RTX);
2458 if (new != reg_equiv_memory_loc[regno])
2459 return copy_rtx (new);
2464 /* If this is the sum of an eliminable register and a constant, rework
2466 if (GET_CODE (XEXP (x, 0)) == REG
2467 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2468 && CONSTANT_P (XEXP (x, 1)))
2470 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2472 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2475 ep->ref_outside_mem = 1;
2477 /* The only time we want to replace a PLUS with a REG (this
2478 occurs when the constant operand of the PLUS is the negative
2479 of the offset) is when we are inside a MEM. We won't want
2480 to do so at other times because that would change the
2481 structure of the insn in a way that reload can't handle.
2482 We special-case the commonest situation in
2483 eliminate_regs_in_insn, so just replace a PLUS with a
2484 PLUS here, unless inside a MEM. */
2485 if (mem_mode && GET_CODE (XEXP (x, 1)) == CONST_INT
2486 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2489 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2490 plus_constant (XEXP (x, 1),
2491 ep->previous_offset));
2494 /* If the register is not eliminable, we are done since the other
2495 operand is a constant. */
2499 /* If this is part of an address, we want to bring any constant to the
2500 outermost PLUS. We will do this by doing register replacement in
2501 our operands and seeing if a constant shows up in one of them.
2503 We assume here this is part of an address (or a "load address" insn)
2504 since an eliminable register is not likely to appear in any other
2507 If we have (plus (eliminable) (reg)), we want to produce
2508 (plus (plus (replacement) (reg) (const))). If this was part of a
2509 normal add insn, (plus (replacement) (reg)) will be pushed as a
2510 reload. This is the desired action. */
2513 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2514 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2516 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2518 /* If one side is a PLUS and the other side is a pseudo that
2519 didn't get a hard register but has a reg_equiv_constant,
2520 we must replace the constant here since it may no longer
2521 be in the position of any operand. */
2522 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2523 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2524 && reg_renumber[REGNO (new1)] < 0
2525 && reg_equiv_constant != 0
2526 && reg_equiv_constant[REGNO (new1)] != 0)
2527 new1 = reg_equiv_constant[REGNO (new1)];
2528 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2529 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2530 && reg_renumber[REGNO (new0)] < 0
2531 && reg_equiv_constant[REGNO (new0)] != 0)
2532 new0 = reg_equiv_constant[REGNO (new0)];
2534 new = form_sum (new0, new1);
2536 /* As above, if we are not inside a MEM we do not want to
2537 turn a PLUS into something else. We might try to do so here
2538 for an addition of 0 if we aren't optimizing. */
2539 if (! mem_mode && GET_CODE (new) != PLUS)
2540 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2548 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2551 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2552 if (new != XEXP (x, 0))
2553 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2556 /* ... fall through ... */
2559 /* Now do eliminations in the rest of the chain. If this was
2560 an EXPR_LIST, this might result in allocating more memory than is
2561 strictly needed, but it simplifies the code. */
2564 new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2565 if (new != XEXP (x, 1))
2566 return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2574 case DIV: case UDIV:
2575 case MOD: case UMOD:
2576 case AND: case IOR: case XOR:
2577 case LSHIFT: case ASHIFT: case ROTATE:
2578 case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2580 case GE: case GT: case GEU: case GTU:
2581 case LE: case LT: case LEU: case LTU:
2583 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2585 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0;
2587 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2588 return gen_rtx (code, GET_MODE (x), new0, new1);
2596 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2597 if (ep->to_rtx == XEXP (x, 0))
2599 if (code == PRE_DEC || code == POST_DEC)
2600 ep->offset += GET_MODE_SIZE (mem_mode);
2602 ep->offset -= GET_MODE_SIZE (mem_mode);
2605 /* Fall through to generic unary operation case. */
2607 case STRICT_LOW_PART:
2609 case SIGN_EXTEND: case ZERO_EXTEND:
2610 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2611 case FLOAT: case FIX:
2612 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2616 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2617 if (new != XEXP (x, 0))
2618 return gen_rtx (code, GET_MODE (x), new);
2622 /* Similar to above processing, but preserve SUBREG_WORD.
2623 Convert (subreg (mem)) to (mem) if not paradoxical.
2624 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2625 pseudo didn't get a hard reg, we must replace this with the
2626 eliminated version of the memory location because push_reloads
2627 may do the replacement in certain circumstances. */
2628 if (GET_CODE (SUBREG_REG (x)) == REG
2629 && (GET_MODE_SIZE (GET_MODE (x))
2630 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2631 && reg_equiv_memory_loc != 0
2632 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2634 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2635 mem_mode, NULL_RTX);
2637 /* If we didn't change anything, we must retain the pseudo. */
2638 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2641 /* Otherwise, ensure NEW isn't shared in case we have to reload
2643 new = copy_rtx (new);
2646 new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX);
2648 if (new != XEXP (x, 0))
2650 if (GET_CODE (new) == MEM
2651 && (GET_MODE_SIZE (GET_MODE (x))
2652 <= GET_MODE_SIZE (GET_MODE (new))))
2654 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2655 enum machine_mode mode = GET_MODE (x);
2657 #if BYTES_BIG_ENDIAN
2658 offset += (MIN (UNITS_PER_WORD,
2659 GET_MODE_SIZE (GET_MODE (new)))
2660 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2663 PUT_MODE (new, mode);
2664 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2668 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2674 /* If clobbering a register that is the replacement register for an
2675 elimination we still think can be performed, note that it cannot
2676 be performed. Otherwise, we need not be concerned about it. */
2677 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2678 if (ep->to_rtx == XEXP (x, 0))
2679 ep->can_eliminate = 0;
2686 /* Properly handle sharing input and constraint vectors. */
2687 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2689 /* When we come to a new vector not seen before,
2690 scan all its elements; keep the old vector if none
2691 of them changes; otherwise, make a copy. */
2692 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2693 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2694 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2695 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2696 mem_mode, NULL_RTX);
2698 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2699 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2702 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2703 new_asm_operands_vec = old_asm_operands_vec;
2705 new_asm_operands_vec
2706 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2709 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2710 if (new_asm_operands_vec == old_asm_operands_vec)
2713 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2714 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2715 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2716 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2717 ASM_OPERANDS_SOURCE_FILE (x),
2718 ASM_OPERANDS_SOURCE_LINE (x));
2719 new->volatil = x->volatil;
2724 /* Check for setting a register that we know about. */
2725 if (GET_CODE (SET_DEST (x)) == REG)
2727 /* See if this is setting the replacement register for an
2730 If DEST is the frame pointer, we do nothing because we assume that
2731 all assignments to the frame pointer are for non-local gotos and
2732 are being done at a time when they are valid and do not disturb
2733 anything else. Some machines want to eliminate a fake argument
2734 pointer with either the frame or stack pointer. Assignments to
2735 the frame pointer must not prevent this elimination. */
2737 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2739 if (ep->to_rtx == SET_DEST (x)
2740 && SET_DEST (x) != frame_pointer_rtx)
2742 /* If it is being incremented, adjust the offset. Otherwise,
2743 this elimination can't be done. */
2744 rtx src = SET_SRC (x);
2746 if (GET_CODE (src) == PLUS
2747 && XEXP (src, 0) == SET_DEST (x)
2748 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2749 ep->offset -= INTVAL (XEXP (src, 1));
2751 ep->can_eliminate = 0;
2754 /* Now check to see we are assigning to a register that can be
2755 eliminated. If so, it must be as part of a PARALLEL, since we
2756 will not have been called if this is a single SET. So indicate
2757 that we can no longer eliminate this reg. */
2758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2760 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2761 ep->can_eliminate = 0;
2764 /* Now avoid the loop below in this common case. */
2766 rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX);
2767 rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX);
2769 /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2770 write a CLOBBER insn. */
2771 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2773 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2775 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2776 return gen_rtx (SET, VOIDmode, new0, new1);
2782 /* Our only special processing is to pass the mode of the MEM to our
2783 recursive call and copy the flags. While we are here, handle this
2784 case more efficiently. */
2785 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX);
2786 if (new != XEXP (x, 0))
2788 new = gen_rtx (MEM, GET_MODE (x), new);
2789 new->volatil = x->volatil;
2790 new->unchanging = x->unchanging;
2791 new->in_struct = x->in_struct;
2798 /* Process each of our operands recursively. If any have changed, make a
2800 fmt = GET_RTX_FORMAT (code);
2801 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2805 new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX);
2806 if (new != XEXP (x, i) && ! copied)
2808 rtx new_x = rtx_alloc (code);
2809 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2810 + (sizeof (new_x->fld[0])
2811 * GET_RTX_LENGTH (code))));
2817 else if (*fmt == 'E')
2820 for (j = 0; j < XVECLEN (x, i); j++)
2822 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2823 if (new != XVECEXP (x, i, j) && ! copied_vec)
2825 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2826 &XVECEXP (x, i, 0));
2829 rtx new_x = rtx_alloc (code);
2830 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2831 + (sizeof (new_x->fld[0])
2832 * GET_RTX_LENGTH (code))));
2836 XVEC (x, i) = new_v;
2839 XVECEXP (x, i, j) = new;
2847 /* Scan INSN and eliminate all eliminable registers in it.
2849 If REPLACE is nonzero, do the replacement destructively. Also
2850 delete the insn as dead it if it is setting an eliminable register.
2852 If REPLACE is zero, do all our allocations in reload_obstack.
2854 If no eliminations were done and this insn doesn't require any elimination
2855 processing (these are not identical conditions: it might be updating sp,
2856 but not referencing fp; this needs to be seen during reload_as_needed so
2857 that the offset between fp and sp can be taken into consideration), zero
2858 is returned. Otherwise, 1 is returned. */
2861 eliminate_regs_in_insn (insn, replace)
2865 rtx old_body = PATTERN (insn);
2868 struct elim_table *ep;
2871 push_obstacks (&reload_obstack, &reload_obstack);
2873 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
2874 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
2876 /* Check for setting an eliminable register. */
2877 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2878 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
2880 /* In this case this insn isn't serving a useful purpose. We
2881 will delete it in reload_as_needed once we know that this
2882 elimination is, in fact, being done.
2884 If REPLACE isn't set, we can't delete this insn, but neededn't
2885 process it since it won't be used unless something changes. */
2887 delete_dead_insn (insn);
2892 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2893 in the insn is the negative of the offset in FROM. Substitute
2894 (set (reg) (reg to)) for the insn and change its code.
2896 We have to do this here, rather than in eliminate_regs, do that we can
2897 change the insn code. */
2899 if (GET_CODE (SET_SRC (old_body)) == PLUS
2900 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
2901 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
2902 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2904 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
2905 && ep->can_eliminate
2906 && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
2908 PATTERN (insn) = gen_rtx (SET, VOIDmode,
2909 SET_DEST (old_body), ep->to_rtx);
2910 INSN_CODE (insn) = -1;
2916 old_asm_operands_vec = 0;
2918 /* Replace the body of this insn with a substituted form. If we changed
2919 something, return non-zero. If this is the final call for this
2920 insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
2922 If we are replacing a body that was a (set X (plus Y Z)), try to
2923 re-recognize the insn. We do this in case we had a simple addition
2924 but now can do this as a load-address. This saves an insn in this
2927 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
2928 if (new_body != old_body)
2930 if (GET_CODE (old_body) != SET || GET_CODE (SET_SRC (old_body)) != PLUS
2931 || ! validate_change (insn, &PATTERN (insn), new_body, 0))
2932 PATTERN (insn) = new_body;
2934 if (replace && REG_NOTES (insn))
2935 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX);
2939 /* Loop through all elimination pairs. See if any have changed and
2940 recalculate the number not at initial offset.
2942 Compute the maximum offset (minimum offset if the stack does not
2943 grow downward) for each elimination pair.
2945 We also detect a cases where register elimination cannot be done,
2946 namely, if a register would be both changed and referenced outside a MEM
2947 in the resulting insn since such an insn is often undefined and, even if
2948 not, we cannot know what meaning will be given to it. Note that it is
2949 valid to have a register used in an address in an insn that changes it
2950 (presumably with a pre- or post-increment or decrement).
2952 If anything changes, return nonzero. */
2954 num_not_at_initial_offset = 0;
2955 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2957 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
2958 ep->can_eliminate = 0;
2960 ep->ref_outside_mem = 0;
2962 if (ep->previous_offset != ep->offset)
2965 ep->previous_offset = ep->offset;
2966 if (ep->can_eliminate && ep->offset != ep->initial_offset)
2967 num_not_at_initial_offset++;
2969 #ifdef STACK_GROWS_DOWNWARD
2970 ep->max_offset = MAX (ep->max_offset, ep->offset);
2972 ep->max_offset = MIN (ep->max_offset, ep->offset);
2983 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
2984 replacement we currently believe is valid, mark it as not eliminable if X
2985 modifies DEST in any way other than by adding a constant integer to it.
2987 If DEST is the frame pointer, we do nothing because we assume that
2988 all assignments to the frame pointer are nonlocal gotos and are being done
2989 at a time when they are valid and do not disturb anything else.
2990 Some machines want to eliminate a fake argument pointer with either the
2991 frame or stack pointer. Assignments to the frame pointer must not prevent
2994 Called via note_stores from reload before starting its passes to scan
2995 the insns of the function. */
2998 mark_not_eliminable (dest, x)
3004 /* A SUBREG of a hard register here is just changing its mode. We should
3005 not see a SUBREG of an eliminable hard register, but check just in
3007 if (GET_CODE (dest) == SUBREG)
3008 dest = SUBREG_REG (dest);
3010 if (dest == frame_pointer_rtx)
3013 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3014 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3015 && (GET_CODE (x) != SET
3016 || GET_CODE (SET_SRC (x)) != PLUS
3017 || XEXP (SET_SRC (x), 0) != dest
3018 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3020 reg_eliminate[i].can_eliminate_previous
3021 = reg_eliminate[i].can_eliminate = 0;
3026 /* Kick all pseudos out of hard register REGNO.
3027 If GLOBAL is nonzero, try to find someplace else to put them.
3028 If DUMPFILE is nonzero, log actions taken on that file.
3030 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3031 because we found we can't eliminate some register. In the case, no pseudos
3032 are allowed to be in the register, even if they are only in a block that
3033 doesn't require spill registers, unlike the case when we are spilling this
3034 hard reg to produce another spill register.
3036 Return nonzero if any pseudos needed to be kicked out. */
3039 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3045 int something_changed = 0;
3048 SET_HARD_REG_BIT (forbidden_regs, regno);
3050 /* Spill every pseudo reg that was allocated to this reg
3051 or to something that overlaps this reg. */
3053 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3054 if (reg_renumber[i] >= 0
3055 && reg_renumber[i] <= regno
3057 + HARD_REGNO_NREGS (reg_renumber[i],
3058 PSEUDO_REGNO_MODE (i))
3061 enum reg_class class = REGNO_REG_CLASS (regno);
3063 /* If this register belongs solely to a basic block which needed no
3064 spilling of any class that this register is contained in,
3065 leave it be, unless we are spilling this register because
3066 it was a hard register that can't be eliminated. */
3068 if (! cant_eliminate
3069 && basic_block_needs[0]
3070 && reg_basic_block[i] >= 0
3071 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3075 for (p = reg_class_superclasses[(int) class];
3076 *p != LIM_REG_CLASSES; p++)
3077 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3080 if (*p == LIM_REG_CLASSES)
3084 /* Mark it as no longer having a hard register home. */
3085 reg_renumber[i] = -1;
3086 /* We will need to scan everything again. */
3087 something_changed = 1;
3089 retry_global_alloc (i, forbidden_regs);
3091 alter_reg (i, regno);
3094 if (reg_renumber[i] == -1)
3095 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3097 fprintf (dumpfile, " Register %d now in %d.\n\n",
3098 i, reg_renumber[i]);
3102 return something_changed;
3105 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3108 scan_paradoxical_subregs (x)
3113 register enum rtx_code code = GET_CODE (x);
3130 if (GET_CODE (SUBREG_REG (x)) == REG
3131 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3132 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3133 = GET_MODE_SIZE (GET_MODE (x));
3137 fmt = GET_RTX_FORMAT (code);
3138 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3141 scan_paradoxical_subregs (XEXP (x, i));
3142 else if (fmt[i] == 'E')
3145 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3146 scan_paradoxical_subregs (XVECEXP (x, i, j));
3151 struct hard_reg_n_uses { int regno; int uses; };
3154 hard_reg_use_compare (p1, p2)
3155 struct hard_reg_n_uses *p1, *p2;
3157 int tem = p1->uses - p2->uses;
3158 if (tem != 0) return tem;
3159 /* If regs are equally good, sort by regno,
3160 so that the results of qsort leave nothing to chance. */
3161 return p1->regno - p2->regno;
3164 /* Choose the order to consider regs for use as reload registers
3165 based on how much trouble would be caused by spilling one.
3166 Store them in order of decreasing preference in potential_reload_regs. */
3169 order_regs_for_reload ()
3175 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3177 CLEAR_HARD_REG_SET (bad_spill_regs);
3179 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3180 potential_reload_regs[i] = -1;
3182 /* Count number of uses of each hard reg by pseudo regs allocated to it
3183 and then order them by decreasing use. */
3185 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3187 hard_reg_n_uses[i].uses = 0;
3188 hard_reg_n_uses[i].regno = i;
3191 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3193 int regno = reg_renumber[i];
3196 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3198 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3200 large += reg_n_refs[i];
3203 /* Now fixed registers (which cannot safely be used for reloading)
3204 get a very high use count so they will be considered least desirable.
3205 Registers used explicitly in the rtl code are almost as bad. */
3207 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3211 hard_reg_n_uses[i].uses += 2 * large + 2;
3212 SET_HARD_REG_BIT (bad_spill_regs, i);
3214 else if (regs_explicitly_used[i])
3216 hard_reg_n_uses[i].uses += large + 1;
3217 /* ??? We are doing this here because of the potential that
3218 bad code may be generated if a register explicitly used in
3219 an insn was used as a spill register for that insn. But
3220 not using these are spill registers may lose on some machine.
3221 We'll have to see how this works out. */
3222 SET_HARD_REG_BIT (bad_spill_regs, i);
3225 hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3226 SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3228 #ifdef ELIMINABLE_REGS
3229 /* If registers other than the frame pointer are eliminable, mark them as
3231 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3233 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3234 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3238 /* Prefer registers not so far used, for use in temporary loading.
3239 Among them, if REG_ALLOC_ORDER is defined, use that order.
3240 Otherwise, prefer registers not preserved by calls. */
3242 #ifdef REG_ALLOC_ORDER
3243 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3245 int regno = reg_alloc_order[i];
3247 if (hard_reg_n_uses[regno].uses == 0)
3248 potential_reload_regs[o++] = regno;
3251 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3253 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3254 potential_reload_regs[o++] = i;
3256 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3258 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3259 potential_reload_regs[o++] = i;
3263 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3264 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3266 /* Now add the regs that are already used,
3267 preferring those used less often. The fixed and otherwise forbidden
3268 registers will be at the end of this list. */
3270 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3271 if (hard_reg_n_uses[i].uses != 0)
3272 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3275 /* Reload pseudo-registers into hard regs around each insn as needed.
3276 Additional register load insns are output before the insn that needs it
3277 and perhaps store insns after insns that modify the reloaded pseudo reg.
3279 reg_last_reload_reg and reg_reloaded_contents keep track of
3280 which pseudo-registers are already available in reload registers.
3281 We update these for the reloads that we perform,
3282 as the insns are scanned. */
3285 reload_as_needed (first, live_known)
3295 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3296 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3297 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3298 reg_has_output_reload = (char *) alloca (max_regno);
3299 for (i = 0; i < n_spills; i++)
3301 reg_reloaded_contents[i] = -1;
3302 reg_reloaded_insn[i] = 0;
3305 /* Reset all offsets on eliminable registers to their initial values. */
3306 #ifdef ELIMINABLE_REGS
3307 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3309 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3310 reg_eliminate[i].initial_offset)
3311 reg_eliminate[i].previous_offset
3312 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3315 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3316 reg_eliminate[0].previous_offset
3317 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3320 num_not_at_initial_offset = 0;
3322 for (insn = first; insn;)
3324 register rtx next = NEXT_INSN (insn);
3326 /* Notice when we move to a new basic block. */
3327 if (live_known && this_block + 1 < n_basic_blocks
3328 && insn == basic_block_head[this_block+1])
3331 /* If we pass a label, copy the offsets from the label information
3332 into the current offsets of each elimination. */
3333 if (GET_CODE (insn) == CODE_LABEL)
3335 num_not_at_initial_offset = 0;
3336 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3338 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3339 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3340 if (reg_eliminate[i].can_eliminate
3341 && (reg_eliminate[i].offset
3342 != reg_eliminate[i].initial_offset))
3343 num_not_at_initial_offset++;
3347 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3349 rtx avoid_return_reg = 0;
3351 #ifdef SMALL_REGISTER_CLASSES
3352 /* Set avoid_return_reg if this is an insn
3353 that might use the value of a function call. */
3354 if (GET_CODE (insn) == CALL_INSN)
3356 if (GET_CODE (PATTERN (insn)) == SET)
3357 after_call = SET_DEST (PATTERN (insn));
3358 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3359 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3360 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3364 else if (after_call != 0
3365 && !(GET_CODE (PATTERN (insn)) == SET
3366 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3368 if (reg_mentioned_p (after_call, PATTERN (insn)))
3369 avoid_return_reg = after_call;
3372 #endif /* SMALL_REGISTER_CLASSES */
3374 /* If this is a USE and CLOBBER of a MEM, ensure that any
3375 references to eliminable registers have been removed. */
3377 if ((GET_CODE (PATTERN (insn)) == USE
3378 || GET_CODE (PATTERN (insn)) == CLOBBER)
3379 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3380 XEXP (XEXP (PATTERN (insn), 0), 0)
3381 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3382 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3384 /* If we need to do register elimination processing, do so.
3385 This might delete the insn, in which case we are done. */
3386 if (num_eliminable && GET_MODE (insn) == QImode)
3388 eliminate_regs_in_insn (insn, 1);
3389 if (GET_CODE (insn) == NOTE)
3396 if (GET_MODE (insn) == VOIDmode)
3398 /* First find the pseudo regs that must be reloaded for this insn.
3399 This info is returned in the tables reload_... (see reload.h).
3400 Also modify the body of INSN by substituting RELOAD
3401 rtx's for those pseudo regs. */
3404 bzero (reg_has_output_reload, max_regno);
3405 CLEAR_HARD_REG_SET (reg_is_output_reload);
3407 find_reloads (insn, 1, spill_indirect_levels, live_known,
3413 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3417 /* If this block has not had spilling done for a
3418 particular class, deactivate any optional reloads
3419 of that class lest they try to use a spill-reg which isn't
3420 available here. If we have any non-optionals that need a
3421 spill reg, abort. */
3423 for (class = 0; class < N_REG_CLASSES; class++)
3424 if (basic_block_needs[class] != 0
3425 && basic_block_needs[class][this_block] == 0)
3426 for (i = 0; i < n_reloads; i++)
3427 if (class == (int) reload_reg_class[i])
3429 if (reload_optional[i])
3431 reload_in[i] = reload_out[i] = 0;
3432 reload_secondary_p[i] = 0;
3434 else if (reload_reg_rtx[i] == 0
3435 && (reload_in[i] != 0 || reload_out[i] != 0
3436 || reload_secondary_p[i] != 0))
3440 /* Now compute which reload regs to reload them into. Perhaps
3441 reusing reload regs from previous insns, or else output
3442 load insns to reload them. Maybe output store insns too.
3443 Record the choices of reload reg in reload_reg_rtx. */
3444 choose_reload_regs (insn, avoid_return_reg);
3446 /* Generate the insns to reload operands into or out of
3447 their reload regs. */
3448 emit_reload_insns (insn);
3450 /* Substitute the chosen reload regs from reload_reg_rtx
3451 into the insn's body (or perhaps into the bodies of other
3452 load and store insn that we just made for reloading
3453 and that we moved the structure into). */
3456 /* If this was an ASM, make sure that all the reload insns
3457 we have generated are valid. If not, give an error
3460 if (asm_noperands (PATTERN (insn)) >= 0)
3461 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3462 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3463 && (recog_memoized (p) < 0
3464 || (insn_extract (p),
3465 ! constrain_operands (INSN_CODE (p), 1))))
3467 error_for_asm (insn,
3468 "`asm' operand requires impossible reload");
3470 NOTE_SOURCE_FILE (p) = 0;
3471 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3474 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3475 is no longer validly lying around to save a future reload.
3476 Note that this does not detect pseudos that were reloaded
3477 for this insn in order to be stored in
3478 (obeying register constraints). That is correct; such reload
3479 registers ARE still valid. */
3480 note_stores (PATTERN (insn), forget_old_reloads_1);
3482 /* There may have been CLOBBER insns placed after INSN. So scan
3483 between INSN and NEXT and use them to forget old reloads. */
3484 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3485 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3486 note_stores (PATTERN (x), forget_old_reloads_1);
3489 /* Likewise for regs altered by auto-increment in this insn.
3490 But note that the reg-notes are not changed by reloading:
3491 they still contain the pseudo-regs, not the spill regs. */
3492 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3493 if (REG_NOTE_KIND (x) == REG_INC)
3495 /* See if this pseudo reg was reloaded in this insn.
3496 If so, its last-reload info is still valid
3497 because it is based on this insn's reload. */
3498 for (i = 0; i < n_reloads; i++)
3499 if (reload_out[i] == XEXP (x, 0))
3503 forget_old_reloads_1 (XEXP (x, 0));
3507 /* A reload reg's contents are unknown after a label. */
3508 if (GET_CODE (insn) == CODE_LABEL)
3509 for (i = 0; i < n_spills; i++)
3511 reg_reloaded_contents[i] = -1;
3512 reg_reloaded_insn[i] = 0;
3515 /* Don't assume a reload reg is still good after a call insn
3516 if it is a call-used reg. */
3517 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == CALL_INSN)
3518 for (i = 0; i < n_spills; i++)
3519 if (call_used_regs[spill_regs[i]])
3521 reg_reloaded_contents[i] = -1;
3522 reg_reloaded_insn[i] = 0;
3525 /* In case registers overlap, allow certain insns to invalidate
3526 particular hard registers. */
3528 #ifdef INSN_CLOBBERS_REGNO_P
3529 for (i = 0 ; i < n_spills ; i++)
3530 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3532 reg_reloaded_contents[i] = -1;
3533 reg_reloaded_insn[i] = 0;
3545 /* Discard all record of any value reloaded from X,
3546 or reloaded in X from someplace else;
3547 unless X is an output reload reg of the current insn.
3549 X may be a hard reg (the reload reg)
3550 or it may be a pseudo reg that was reloaded from. */
3553 forget_old_reloads_1 (x)
3559 if (GET_CODE (x) != REG)
3564 if (regno >= FIRST_PSEUDO_REGISTER)
3569 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3570 /* Storing into a spilled-reg invalidates its contents.
3571 This can happen if a block-local pseudo is allocated to that reg
3572 and it wasn't spilled because this block's total need is 0.
3573 Then some insn might have an optional reload and use this reg. */
3574 for (i = 0; i < nr; i++)
3575 if (spill_reg_order[regno + i] >= 0
3576 /* But don't do this if the reg actually serves as an output
3577 reload reg in the current instruction. */
3579 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3581 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3582 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3586 /* Since value of X has changed,
3587 forget any value previously copied from it. */
3590 /* But don't forget a copy if this is the output reload
3591 that establishes the copy's validity. */
3592 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3593 reg_last_reload_reg[regno + nr] = 0;
3596 /* For each reload, the mode of the reload register. */
3597 static enum machine_mode reload_mode[MAX_RELOADS];
3599 /* For each reload, the largest number of registers it will require. */
3600 static int reload_nregs[MAX_RELOADS];
3602 /* Comparison function for qsort to decide which of two reloads
3603 should be handled first. *P1 and *P2 are the reload numbers. */
3606 reload_reg_class_lower (p1, p2)
3609 register int r1 = *p1, r2 = *p2;
3612 /* Consider required reloads before optional ones. */
3613 t = reload_optional[r1] - reload_optional[r2];
3617 /* Count all solitary classes before non-solitary ones. */
3618 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3619 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3623 /* Aside from solitaires, consider all multi-reg groups first. */
3624 t = reload_nregs[r2] - reload_nregs[r1];
3628 /* Consider reloads in order of increasing reg-class number. */
3629 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3633 /* If reloads are equally urgent, sort by reload number,
3634 so that the results of qsort leave nothing to chance. */
3638 /* The following HARD_REG_SETs indicate when each hard register is
3639 used for a reload of various parts of the current insn. */
3641 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3642 static HARD_REG_SET reload_reg_used;
3643 /* If reg is in use for a RELOAD_FOR_INPUT_RELOAD_ADDRESS reload. */
3644 static HARD_REG_SET reload_reg_used_in_input_addr;
3645 /* If reg is in use for a RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reload. */
3646 static HARD_REG_SET reload_reg_used_in_output_addr;
3647 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3648 static HARD_REG_SET reload_reg_used_in_op_addr;
3649 /* If reg is in use for a RELOAD_FOR_INPUT reload. */
3650 static HARD_REG_SET reload_reg_used_in_input;
3651 /* If reg is in use for a RELOAD_FOR_OUTPUT reload. */
3652 static HARD_REG_SET reload_reg_used_in_output;
3654 /* If reg is in use as a reload reg for any sort of reload. */
3655 static HARD_REG_SET reload_reg_used_at_all;
3657 /* Mark reg REGNO as in use for a reload of the sort spec'd by WHEN_NEEDED.
3658 MODE is used to indicate how many consecutive regs are actually used. */
3661 mark_reload_reg_in_use (regno, when_needed, mode)
3663 enum reload_when_needed when_needed;
3664 enum machine_mode mode;
3666 int nregs = HARD_REGNO_NREGS (regno, mode);
3669 for (i = regno; i < nregs + regno; i++)
3671 switch (when_needed)
3674 SET_HARD_REG_BIT (reload_reg_used, i);
3677 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3678 SET_HARD_REG_BIT (reload_reg_used_in_input_addr, i);
3681 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3682 SET_HARD_REG_BIT (reload_reg_used_in_output_addr, i);
3685 case RELOAD_FOR_OPERAND_ADDRESS:
3686 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3689 case RELOAD_FOR_INPUT:
3690 SET_HARD_REG_BIT (reload_reg_used_in_input, i);
3693 case RELOAD_FOR_OUTPUT:
3694 SET_HARD_REG_BIT (reload_reg_used_in_output, i);
3698 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3702 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3703 specified by WHEN_NEEDED. */
3706 reload_reg_free_p (regno, when_needed)
3708 enum reload_when_needed when_needed;
3710 /* In use for a RELOAD_OTHER means it's not available for anything. */
3711 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
3713 switch (when_needed)
3716 /* In use for anything means not available for a RELOAD_OTHER. */
3717 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
3719 /* The other kinds of use can sometimes share a register. */
3720 case RELOAD_FOR_INPUT:
3721 return (! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3722 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3723 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno));
3724 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3725 return (! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno)
3726 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno));
3727 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3728 return (! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3729 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3730 case RELOAD_FOR_OPERAND_ADDRESS:
3731 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3732 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3733 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3734 case RELOAD_FOR_OUTPUT:
3735 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3736 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3737 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3742 /* Return 1 if the value in reload reg REGNO, as used by a reload
3743 needed for the part of the insn specified by WHEN_NEEDED,
3744 is not in use for a reload in any prior part of the insn.
3746 We can assume that the reload reg was already tested for availability
3747 at the time it is needed, and we should not check this again,
3748 in case the reg has already been marked in use. */
3751 reload_reg_free_before_p (regno, when_needed)
3753 enum reload_when_needed when_needed;
3755 switch (when_needed)
3758 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3759 its use starts from the beginning, so nothing can use it earlier. */
3762 /* If this use is for part of the insn,
3763 check the reg is not in use for any prior part. */
3764 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3765 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
3767 case RELOAD_FOR_OUTPUT:
3768 if (TEST_HARD_REG_BIT (reload_reg_used_in_input, regno))
3770 case RELOAD_FOR_OPERAND_ADDRESS:
3771 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno))
3773 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3774 case RELOAD_FOR_INPUT:
3780 /* Return 1 if the value in reload reg REGNO, as used by a reload
3781 needed for the part of the insn specified by WHEN_NEEDED,
3782 is still available in REGNO at the end of the insn.
3784 We can assume that the reload reg was already tested for availability
3785 at the time it is needed, and we should not check this again,
3786 in case the reg has already been marked in use. */
3789 reload_reg_reaches_end_p (regno, when_needed)
3791 enum reload_when_needed when_needed;
3793 switch (when_needed)
3796 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3797 its value must reach the end. */
3800 /* If this use is for part of the insn,
3801 its value reaches if no subsequent part uses the same register. */
3802 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3803 case RELOAD_FOR_INPUT:
3804 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3805 || TEST_HARD_REG_BIT (reload_reg_used_in_output, regno))
3807 case RELOAD_FOR_OPERAND_ADDRESS:
3808 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno))
3810 case RELOAD_FOR_OUTPUT:
3811 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3817 /* Vector of reload-numbers showing the order in which the reloads should
3819 short reload_order[MAX_RELOADS];
3821 /* Indexed by reload number, 1 if incoming value
3822 inherited from previous insns. */
3823 char reload_inherited[MAX_RELOADS];
3825 /* For an inherited reload, this is the insn the reload was inherited from,
3826 if we know it. Otherwise, this is 0. */
3827 rtx reload_inheritance_insn[MAX_RELOADS];
3829 /* If non-zero, this is a place to get the value of the reload,
3830 rather than using reload_in. */
3831 rtx reload_override_in[MAX_RELOADS];
3833 /* For each reload, the index in spill_regs of the spill register used,
3834 or -1 if we did not need one of the spill registers for this reload. */
3835 int reload_spill_index[MAX_RELOADS];
3837 /* Index of last register assigned as a spill register. We allocate in
3838 a round-robin fashio. */
3840 static last_spill_reg = 0;
3842 /* Find a spill register to use as a reload register for reload R.
3843 LAST_RELOAD is non-zero if this is the last reload for the insn being
3846 Set reload_reg_rtx[R] to the register allocated.
3848 If NOERROR is nonzero, we return 1 if successful,
3849 or 0 if we couldn't find a spill reg and we didn't change anything. */
3852 allocate_reload_reg (r, insn, last_reload, noerror)
3864 /* If we put this reload ahead, thinking it is a group,
3865 then insist on finding a group. Otherwise we can grab a
3866 reg that some other reload needs.
3867 (That can happen when we have a 68000 DATA_OR_FP_REG
3868 which is a group of data regs or one fp reg.)
3869 We need not be so restrictive if there are no more reloads
3872 ??? Really it would be nicer to have smarter handling
3873 for that kind of reg class, where a problem like this is normal.
3874 Perhaps those classes should be avoided for reloading
3875 by use of more alternatives. */
3877 int force_group = reload_nregs[r] > 1 && ! last_reload;
3879 /* If we want a single register and haven't yet found one,
3880 take any reg in the right class and not in use.
3881 If we want a consecutive group, here is where we look for it.
3883 We use two passes so we can first look for reload regs to
3884 reuse, which are already in use for other reloads in this insn,
3885 and only then use additional registers.
3886 I think that maximizing reuse is needed to make sure we don't
3887 run out of reload regs. Suppose we have three reloads, and
3888 reloads A and B can share regs. These need two regs.
3889 Suppose A and B are given different regs.
3890 That leaves none for C. */
3891 for (pass = 0; pass < 2; pass++)
3893 /* I is the index in spill_regs.
3894 We advance it round-robin between insns to use all spill regs
3895 equally, so that inherited reloads have a chance
3896 of leapfrogging each other. */
3898 for (count = 0, i = last_spill_reg; count < n_spills; count++)
3900 int class = (int) reload_reg_class[r];
3902 i = (i + 1) % n_spills;
3904 if (reload_reg_free_p (spill_regs[i], reload_when_needed[r])
3905 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
3906 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
3907 /* Look first for regs to share, then for unshared. */
3908 && (pass || TEST_HARD_REG_BIT (reload_reg_used_at_all,
3911 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
3912 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
3913 (on 68000) got us two FP regs. If NR is 1,
3914 we would reject both of them. */
3916 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
3917 /* If we need only one reg, we have already won. */
3920 /* But reject a single reg if we demand a group. */
3925 /* Otherwise check that as many consecutive regs as we need
3927 Also, don't use for a group registers that are
3928 needed for nongroups. */
3929 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
3932 regno = spill_regs[i] + nr - 1;
3933 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
3934 && spill_reg_order[regno] >= 0
3935 && reload_reg_free_p (regno, reload_when_needed[r])
3936 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
3946 /* If we found something on pass 1, omit pass 2. */
3947 if (count < n_spills)
3951 /* We should have found a spill register by now. */
3952 if (count == n_spills)
3961 /* Mark as in use for this insn the reload regs we use for this. */
3962 mark_reload_reg_in_use (spill_regs[i], reload_when_needed[r],
3965 new = spill_reg_rtx[i];
3967 if (new == 0 || GET_MODE (new) != reload_mode[r])
3968 spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode[r], spill_regs[i]);
3970 reload_reg_rtx[r] = new;
3971 reload_spill_index[r] = i;
3972 regno = true_regnum (new);
3974 /* Detect when the reload reg can't hold the reload mode.
3975 This used to be one `if', but Sequent compiler can't handle that. */
3976 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
3978 enum machine_mode test_mode = VOIDmode;
3980 test_mode = GET_MODE (reload_in[r]);
3981 /* If reload_in[r] has VOIDmode, it means we will load it
3982 in whatever mode the reload reg has: to wit, reload_mode[r].
3983 We have already tested that for validity. */
3984 /* Aside from that, we need to test that the expressions
3985 to reload from or into have modes which are valid for this
3986 reload register. Otherwise the reload insns would be invalid. */
3987 if (! (reload_in[r] != 0 && test_mode != VOIDmode
3988 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
3989 if (! (reload_out[r] != 0
3990 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
3991 /* The reg is OK. */
3995 /* The reg is not OK. */
3999 if (asm_noperands (PATTERN (insn)) < 0)
4000 /* It's the compiler's fault. */
4003 /* It's the user's fault; the operand's mode and constraint
4004 don't match. Disable this reload so we don't crash in final. */
4005 error_for_asm (insn,
4006 "`asm' operand constraint incompatible with operand size");
4009 reload_reg_rtx[r] = 0;
4010 reload_optional[r] = 1;
4011 reload_secondary_p[r] = 1;
4016 /* Assign hard reg targets for the pseudo-registers we must reload
4017 into hard regs for this insn.
4018 Also output the instructions to copy them in and out of the hard regs.
4020 For machines with register classes, we are responsible for
4021 finding a reload reg in the proper class. */
4024 choose_reload_regs (insn, avoid_return_reg)
4026 /* This argument is currently ignored. */
4027 rtx avoid_return_reg;
4030 int max_group_size = 1;
4031 enum reg_class group_class = NO_REGS;
4034 rtx save_reload_reg_rtx[MAX_RELOADS];
4035 char save_reload_inherited[MAX_RELOADS];
4036 rtx save_reload_inheritance_insn[MAX_RELOADS];
4037 rtx save_reload_override_in[MAX_RELOADS];
4038 int save_reload_spill_index[MAX_RELOADS];
4039 HARD_REG_SET save_reload_reg_used;
4040 HARD_REG_SET save_reload_reg_used_in_input_addr;
4041 HARD_REG_SET save_reload_reg_used_in_output_addr;
4042 HARD_REG_SET save_reload_reg_used_in_op_addr;
4043 HARD_REG_SET save_reload_reg_used_in_input;
4044 HARD_REG_SET save_reload_reg_used_in_output;
4045 HARD_REG_SET save_reload_reg_used_at_all;
4047 bzero (reload_inherited, MAX_RELOADS);
4048 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4049 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4051 CLEAR_HARD_REG_SET (reload_reg_used);
4052 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4053 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr);
4054 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr);
4055 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4056 CLEAR_HARD_REG_SET (reload_reg_used_in_output);
4057 CLEAR_HARD_REG_SET (reload_reg_used_in_input);
4059 /* Distinguish output-only and input-only reloads
4060 because they can overlap with other things. */
4061 for (j = 0; j < n_reloads; j++)
4062 if (reload_when_needed[j] == RELOAD_OTHER
4063 && ! reload_needed_for_multiple[j])
4065 if (reload_in[j] == 0)
4067 /* But earlyclobber operands must stay as RELOAD_OTHER. */
4068 for (i = 0; i < n_earlyclobbers; i++)
4069 if (rtx_equal_p (reload_out[j], reload_earlyclobbers[i]))
4071 if (i == n_earlyclobbers)
4072 reload_when_needed[j] = RELOAD_FOR_OUTPUT;
4074 if (reload_out[j] == 0)
4075 reload_when_needed[j] = RELOAD_FOR_INPUT;
4077 if (reload_secondary_reload[j] >= 0
4078 && ! reload_needed_for_multiple[reload_secondary_reload[j]])
4079 reload_when_needed[reload_secondary_reload[j]]
4080 = reload_when_needed[j];
4083 #ifdef SMALL_REGISTER_CLASSES
4084 /* Don't bother with avoiding the return reg
4085 if we have no mandatory reload that could use it. */
4086 if (avoid_return_reg)
4089 int regno = REGNO (avoid_return_reg);
4091 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4094 for (r = regno; r < regno + nregs; r++)
4095 if (spill_reg_order[r] >= 0)
4096 for (j = 0; j < n_reloads; j++)
4097 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4098 && (reload_in[j] != 0 || reload_out[j] != 0
4099 || reload_secondary_p[j])
4101 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4104 avoid_return_reg = 0;
4106 #endif /* SMALL_REGISTER_CLASSES */
4108 #if 0 /* Not needed, now that we can always retry without inheritance. */
4109 /* See if we have more mandatory reloads than spill regs.
4110 If so, then we cannot risk optimizations that could prevent
4111 reloads from sharing one spill register.
4113 Since we will try finding a better register than reload_reg_rtx
4114 unless it is equal to reload_in or reload_out, count such reloads. */
4118 #ifdef SMALL_REGISTER_CLASSES
4119 int tem = (avoid_return_reg != 0);
4121 for (j = 0; j < n_reloads; j++)
4122 if (! reload_optional[j]
4123 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4124 && (reload_reg_rtx[j] == 0
4125 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4126 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4133 #ifdef SMALL_REGISTER_CLASSES
4134 /* Don't use the subroutine call return reg for a reload
4135 if we are supposed to avoid it. */
4136 if (avoid_return_reg)
4138 int regno = REGNO (avoid_return_reg);
4140 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4143 for (r = regno; r < regno + nregs; r++)
4144 if (spill_reg_order[r] >= 0)
4145 SET_HARD_REG_BIT (reload_reg_used, r);
4147 #endif /* SMALL_REGISTER_CLASSES */
4149 /* In order to be certain of getting the registers we need,
4150 we must sort the reloads into order of increasing register class.
4151 Then our grabbing of reload registers will parallel the process
4152 that provided the reload registers.
4154 Also note whether any of the reloads wants a consecutive group of regs.
4155 If so, record the maximum size of the group desired and what
4156 register class contains all the groups needed by this insn. */
4158 for (j = 0; j < n_reloads; j++)
4160 reload_order[j] = j;
4161 reload_spill_index[j] = -1;
4164 = (reload_strict_low[j] && reload_out[j]
4165 ? GET_MODE (SUBREG_REG (reload_out[j]))
4166 : (reload_inmode[j] == VOIDmode
4167 || (GET_MODE_SIZE (reload_outmode[j])
4168 > GET_MODE_SIZE (reload_inmode[j])))
4169 ? reload_outmode[j] : reload_inmode[j]);
4171 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4173 if (reload_nregs[j] > 1)
4175 max_group_size = MAX (reload_nregs[j], max_group_size);
4176 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4179 /* If we have already decided to use a certain register,
4180 don't use it in another way. */
4181 if (reload_reg_rtx[j])
4182 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]),
4183 reload_when_needed[j], reload_mode[j]);
4187 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4189 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4190 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4191 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4192 sizeof reload_inheritance_insn);
4193 bcopy (reload_override_in, save_reload_override_in,
4194 sizeof reload_override_in);
4195 bcopy (reload_spill_index, save_reload_spill_index,
4196 sizeof reload_spill_index);
4197 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4198 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4199 COPY_HARD_REG_SET (save_reload_reg_used_in_output,
4200 reload_reg_used_in_output);
4201 COPY_HARD_REG_SET (save_reload_reg_used_in_input,
4202 reload_reg_used_in_input);
4203 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr,
4204 reload_reg_used_in_input_addr);
4205 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr,
4206 reload_reg_used_in_output_addr);
4207 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4208 reload_reg_used_in_op_addr);
4210 /* Try first with inheritance, then turning it off. */
4212 for (inheritance = 1; inheritance >= 0; inheritance--)
4214 /* Process the reloads in order of preference just found.
4215 Beyond this point, subregs can be found in reload_reg_rtx.
4217 This used to look for an existing reloaded home for all
4218 of the reloads, and only then perform any new reloads.
4219 But that could lose if the reloads were done out of reg-class order
4220 because a later reload with a looser constraint might have an old
4221 home in a register needed by an earlier reload with a tighter constraint.
4223 To solve this, we make two passes over the reloads, in the order
4224 described above. In the first pass we try to inherit a reload
4225 from a previous insn. If there is a later reload that needs a
4226 class that is a proper subset of the class being processed, we must
4227 also allocate a spill register during the first pass.
4229 Then make a second pass over the reloads to allocate any reloads
4230 that haven't been given registers yet. */
4232 for (j = 0; j < n_reloads; j++)
4234 register int r = reload_order[j];
4236 /* Ignore reloads that got marked inoperative. */
4237 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4240 /* If find_reloads chose a to use reload_in or reload_out as a reload
4241 register, we don't need to chose one. Otherwise, try even if it found
4242 one since we might save an insn if we find the value lying around. */
4243 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4244 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4245 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4248 #if 0 /* No longer needed for correct operation.
4249 It might give better code, or might not; worth an experiment? */
4250 /* If this is an optional reload, we can't inherit from earlier insns
4251 until we are sure that any non-optional reloads have been allocated.
4252 The following code takes advantage of the fact that optional reloads
4253 are at the end of reload_order. */
4254 if (reload_optional[r] != 0)
4255 for (i = 0; i < j; i++)
4256 if ((reload_out[reload_order[i]] != 0
4257 || reload_in[reload_order[i]] != 0
4258 || reload_secondary_p[reload_order[i]])
4259 && ! reload_optional[reload_order[i]]
4260 && reload_reg_rtx[reload_order[i]] == 0)
4261 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4264 /* First see if this pseudo is already available as reloaded
4265 for a previous insn. We cannot try to inherit for reloads
4266 that are smaller than the maximum number of registers needed
4267 for groups unless the register we would allocate cannot be used
4270 We could check here to see if this is a secondary reload for
4271 an object that is already in a register of the desired class.
4272 This would avoid the need for the secondary reload register.
4273 But this is complex because we can't easily determine what
4274 objects might want to be loaded via this reload. So let a register
4275 be allocated here. In `emit_reload_insns' we suppress one of the
4276 loads in the case described above. */
4280 register int regno = -1;
4282 if (reload_in[r] == 0)
4284 else if (GET_CODE (reload_in[r]) == REG)
4285 regno = REGNO (reload_in[r]);
4286 else if (GET_CODE (reload_in_reg[r]) == REG)
4287 regno = REGNO (reload_in_reg[r]);
4289 /* This won't work, since REGNO can be a pseudo reg number.
4290 Also, it takes much more hair to keep track of all the things
4291 that can invalidate an inherited reload of part of a pseudoreg. */
4292 else if (GET_CODE (reload_in[r]) == SUBREG
4293 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4294 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4297 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4299 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4301 if (reg_reloaded_contents[i] == regno
4302 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4303 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4305 && (reload_nregs[r] == max_group_size
4306 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4308 && reload_reg_free_p (spill_regs[i], reload_when_needed[r])
4309 && reload_reg_free_before_p (spill_regs[i],
4310 reload_when_needed[r]))
4312 /* If a group is needed, verify that all the subsequent
4313 registers still have their values intact. */
4315 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4318 for (k = 1; k < nr; k++)
4319 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4325 /* Mark the register as in use for this part of
4327 mark_reload_reg_in_use (spill_regs[i],
4328 reload_when_needed[r],
4330 reload_reg_rtx[r] = reg_last_reload_reg[regno];
4331 reload_inherited[r] = 1;
4332 reload_inheritance_insn[r] = reg_reloaded_insn[i];
4333 reload_spill_index[r] = i;
4339 /* Here's another way to see if the value is already lying around. */
4341 && reload_in[r] != 0
4342 && ! reload_inherited[r]
4343 && reload_out[r] == 0
4344 && (CONSTANT_P (reload_in[r])
4345 || GET_CODE (reload_in[r]) == PLUS
4346 || GET_CODE (reload_in[r]) == REG
4347 || GET_CODE (reload_in[r]) == MEM)
4348 && (reload_nregs[r] == max_group_size
4349 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4352 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4353 -1, NULL_PTR, 0, reload_mode[r]);
4358 if (GET_CODE (equiv) == REG)
4359 regno = REGNO (equiv);
4360 else if (GET_CODE (equiv) == SUBREG)
4362 regno = REGNO (SUBREG_REG (equiv));
4363 if (regno < FIRST_PSEUDO_REGISTER)
4364 regno += SUBREG_WORD (equiv);
4370 /* If we found a spill reg, reject it unless it is free
4371 and of the desired class. */
4373 && ((spill_reg_order[regno] >= 0
4374 && ! reload_reg_free_before_p (regno,
4375 reload_when_needed[r]))
4376 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4380 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4383 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4386 /* We found a register that contains the value we need.
4387 If this register is the same as an `earlyclobber' operand
4388 of the current insn, just mark it as a place to reload from
4389 since we can't use it as the reload register itself. */
4392 for (i = 0; i < n_earlyclobbers; i++)
4393 if (reg_overlap_mentioned_for_reload_p (equiv,
4394 reload_earlyclobbers[i]))
4396 reload_override_in[r] = equiv;
4401 /* JRV: If the equiv register we have found is explicitly
4402 clobbered in the current insn, mark but don't use, as above. */
4404 if (equiv != 0 && regno_clobbered_p (regno, insn))
4406 reload_override_in[r] = equiv;
4410 /* If we found an equivalent reg, say no code need be generated
4411 to load it, and use it as our reload reg. */
4412 if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4414 reload_reg_rtx[r] = equiv;
4415 reload_inherited[r] = 1;
4416 /* If it is a spill reg,
4417 mark the spill reg as in use for this insn. */
4418 i = spill_reg_order[regno];
4420 mark_reload_reg_in_use (regno, reload_when_needed[r],
4425 /* If we found a register to use already, or if this is an optional
4426 reload, we are done. */
4427 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4430 #if 0 /* No longer needed for correct operation. Might or might not
4431 give better code on the average. Want to experiment? */
4433 /* See if there is a later reload that has a class different from our
4434 class that intersects our class or that requires less register
4435 than our reload. If so, we must allocate a register to this
4436 reload now, since that reload might inherit a previous reload
4437 and take the only available register in our class. Don't do this
4438 for optional reloads since they will force all previous reloads
4439 to be allocated. Also don't do this for reloads that have been
4442 for (i = j + 1; i < n_reloads; i++)
4444 int s = reload_order[i];
4446 if ((reload_in[s] == 0 && reload_out[s] == 0
4447 && ! reload_secondary_p[s])
4448 || reload_optional[s])
4451 if ((reload_reg_class[s] != reload_reg_class[r]
4452 && reg_classes_intersect_p (reload_reg_class[r],
4453 reload_reg_class[s]))
4454 || reload_nregs[s] < reload_nregs[r])
4461 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
4465 /* Now allocate reload registers for anything non-optional that
4466 didn't get one yet. */
4467 for (j = 0; j < n_reloads; j++)
4469 register int r = reload_order[j];
4471 /* Ignore reloads that got marked inoperative. */
4472 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4475 /* Skip reloads that already have a register allocated or are
4477 if (reload_reg_rtx[r] != 0 || reload_optional[r])
4480 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
4484 /* If that loop got all the way, we have won. */
4489 /* Loop around and try without any inheritance. */
4490 /* First undo everything done by the failed attempt
4491 to allocate with inheritance. */
4492 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
4493 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
4494 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
4495 sizeof reload_inheritance_insn);
4496 bcopy (save_reload_override_in, reload_override_in,
4497 sizeof reload_override_in);
4498 bcopy (save_reload_spill_index, reload_spill_index,
4499 sizeof reload_spill_index);
4500 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
4501 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
4502 COPY_HARD_REG_SET (reload_reg_used_in_input,
4503 save_reload_reg_used_in_input);
4504 COPY_HARD_REG_SET (reload_reg_used_in_output,
4505 save_reload_reg_used_in_output);
4506 COPY_HARD_REG_SET (reload_reg_used_in_input_addr,
4507 save_reload_reg_used_in_input_addr);
4508 COPY_HARD_REG_SET (reload_reg_used_in_output_addr,
4509 save_reload_reg_used_in_output_addr);
4510 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
4511 save_reload_reg_used_in_op_addr);
4514 /* If we thought we could inherit a reload, because it seemed that
4515 nothing else wanted the same reload register earlier in the insn,
4516 verify that assumption, now that all reloads have been assigned. */
4518 for (j = 0; j < n_reloads; j++)
4520 register int r = reload_order[j];
4522 if (reload_inherited[r] && reload_reg_rtx[r] != 0
4523 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
4524 reload_when_needed[r]))
4525 reload_inherited[r] = 0;
4527 /* If we found a better place to reload from,
4528 validate it in the same fashion, if it is a reload reg. */
4529 if (reload_override_in[r]
4530 && (GET_CODE (reload_override_in[r]) == REG
4531 || GET_CODE (reload_override_in[r]) == SUBREG))
4533 int regno = true_regnum (reload_override_in[r]);
4534 if (spill_reg_order[regno] >= 0
4535 && ! reload_reg_free_before_p (regno, reload_when_needed[r]))
4536 reload_override_in[r] = 0;
4540 /* Now that reload_override_in is known valid,
4541 actually override reload_in. */
4542 for (j = 0; j < n_reloads; j++)
4543 if (reload_override_in[j])
4544 reload_in[j] = reload_override_in[j];
4546 /* If this reload won't be done because it has been cancelled or is
4547 optional and not inherited, clear reload_reg_rtx so other
4548 routines (such as subst_reloads) don't get confused. */
4549 for (j = 0; j < n_reloads; j++)
4550 if ((reload_optional[j] && ! reload_inherited[j])
4551 || (reload_in[j] == 0 && reload_out[j] == 0
4552 && ! reload_secondary_p[j]))
4553 reload_reg_rtx[j] = 0;
4555 /* Record which pseudos and which spill regs have output reloads. */
4556 for (j = 0; j < n_reloads; j++)
4558 register int r = reload_order[j];
4560 i = reload_spill_index[r];
4562 /* I is nonneg if this reload used one of the spill regs.
4563 If reload_reg_rtx[r] is 0, this is an optional reload
4564 that we opted to ignore. */
4565 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
4566 && reload_reg_rtx[r] != 0)
4568 register int nregno = REGNO (reload_out[r]);
4569 int nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
4573 reg_has_output_reload[nregno + nr] = 1;
4575 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
4578 if (reload_when_needed[r] != RELOAD_OTHER
4579 && reload_when_needed[r] != RELOAD_FOR_OUTPUT)
4585 /* Output insns to reload values in and out of the chosen reload regs. */
4588 emit_reload_insns (insn)
4592 rtx following_insn = NEXT_INSN (insn);
4593 rtx before_insn = insn;
4594 rtx first_output_reload_insn = NEXT_INSN (insn);
4595 rtx first_other_reload_insn = insn;
4596 rtx first_operand_address_reload_insn = insn;
4598 /* Values to be put in spill_reg_store are put here first. */
4599 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
4601 /* If this is a CALL_INSN preceded by USE insns, any reload insns
4602 must go in front of the first USE insn, not in front of INSN. */
4604 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
4605 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
4606 while (GET_CODE (PREV_INSN (before_insn)) == INSN
4607 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
4608 first_other_reload_insn = first_operand_address_reload_insn
4609 = before_insn = PREV_INSN (before_insn);
4611 /* Now output the instructions to copy the data into and out of the
4612 reload registers. Do these in the order that the reloads were reported,
4613 since reloads of base and index registers precede reloads of operands
4614 and the operands may need the base and index registers reloaded. */
4616 for (j = 0; j < n_reloads; j++)
4619 rtx oldequiv_reg = 0;
4620 rtx this_reload_insn = 0;
4624 if (old != 0 && ! reload_inherited[j]
4625 && ! rtx_equal_p (reload_reg_rtx[j], old)
4626 && reload_reg_rtx[j] != 0)
4628 register rtx reloadreg = reload_reg_rtx[j];
4630 enum machine_mode mode;
4634 /* Determine the mode to reload in.
4635 This is very tricky because we have three to choose from.
4636 There is the mode the insn operand wants (reload_inmode[J]).
4637 There is the mode of the reload register RELOADREG.
4638 There is the intrinsic mode of the operand, which we could find
4639 by stripping some SUBREGs.
4640 It turns out that RELOADREG's mode is irrelevant:
4641 we can change that arbitrarily.
4643 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
4644 then the reload reg may not support QImode moves, so use SImode.
4645 If foo is in memory due to spilling a pseudo reg, this is safe,
4646 because the QImode value is in the least significant part of a
4647 slot big enough for a SImode. If foo is some other sort of
4648 memory reference, then it is impossible to reload this case,
4649 so previous passes had better make sure this never happens.
4651 Then consider a one-word union which has SImode and one of its
4652 members is a float, being fetched as (SUBREG:SF union:SI).
4653 We must fetch that as SFmode because we could be loading into
4654 a float-only register. In this case OLD's mode is correct.
4656 Consider an immediate integer: it has VOIDmode. Here we need
4657 to get a mode from something else.
4659 In some cases, there is a fourth mode, the operand's
4660 containing mode. If the insn specifies a containing mode for
4661 this operand, it overrides all others.
4663 I am not sure whether the algorithm here is always right,
4664 but it does the right things in those cases. */
4666 mode = GET_MODE (old);
4667 if (mode == VOIDmode)
4668 mode = reload_inmode[j];
4669 if (reload_strict_low[j])
4670 mode = GET_MODE (SUBREG_REG (reload_in[j]));
4672 #ifdef SECONDARY_INPUT_RELOAD_CLASS
4673 /* If we need a secondary register for this operation, see if
4674 the value is already in a register in that class. Don't
4675 do this if the secondary register will be used as a scratch
4678 if (reload_secondary_reload[j] >= 0
4679 && reload_secondary_icode[j] == CODE_FOR_nothing)
4681 = find_equiv_reg (old, insn,
4682 reload_reg_class[reload_secondary_reload[j]],
4683 -1, NULL_PTR, 0, mode);
4686 /* If reloading from memory, see if there is a register
4687 that already holds the same value. If so, reload from there.
4688 We can pass 0 as the reload_reg_p argument because
4689 any other reload has either already been emitted,
4690 in which case find_equiv_reg will see the reload-insn,
4691 or has yet to be emitted, in which case it doesn't matter
4692 because we will use this equiv reg right away. */
4695 && (GET_CODE (old) == MEM
4696 || (GET_CODE (old) == REG
4697 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4698 && reg_renumber[REGNO (old)] < 0)))
4699 oldequiv = find_equiv_reg (old, insn, GENERAL_REGS,
4700 -1, NULL_PTR, 0, mode);
4704 int regno = true_regnum (oldequiv);
4706 /* If OLDEQUIV is a spill register, don't use it for this
4707 if any other reload needs it at an earlier stage of this insn
4708 or at this stage. */
4709 if (spill_reg_order[regno] >= 0
4710 && (! reload_reg_free_p (regno, reload_when_needed[j])
4711 || ! reload_reg_free_before_p (regno,
4712 reload_when_needed[j])))
4715 /* If OLDEQUIV is not a spill register,
4716 don't use it if any other reload wants it. */
4717 if (spill_reg_order[regno] < 0)
4720 for (k = 0; k < n_reloads; k++)
4721 if (reload_reg_rtx[k] != 0 && k != j
4722 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
4733 else if (GET_CODE (oldequiv) == REG)
4734 oldequiv_reg = oldequiv;
4735 else if (GET_CODE (oldequiv) == SUBREG)
4736 oldequiv_reg = SUBREG_REG (oldequiv);
4738 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
4739 then load RELOADREG from OLDEQUIV. */
4741 if (GET_MODE (reloadreg) != mode)
4742 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
4743 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
4744 oldequiv = SUBREG_REG (oldequiv);
4745 if (GET_MODE (oldequiv) != VOIDmode
4746 && mode != GET_MODE (oldequiv))
4747 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
4749 /* Decide where to put reload insn for this reload. */
4750 switch (reload_when_needed[j])
4752 case RELOAD_FOR_INPUT:
4754 where = first_operand_address_reload_insn;
4756 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
4757 where = first_other_reload_insn;
4759 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
4760 where = first_output_reload_insn;
4762 case RELOAD_FOR_OPERAND_ADDRESS:
4763 where = before_insn;
4768 /* Auto-increment addresses must be reloaded in a special way. */
4769 if (GET_CODE (oldequiv) == POST_INC
4770 || GET_CODE (oldequiv) == POST_DEC
4771 || GET_CODE (oldequiv) == PRE_INC
4772 || GET_CODE (oldequiv) == PRE_DEC)
4774 /* We are not going to bother supporting the case where a
4775 incremented register can't be copied directly from
4776 OLDEQUIV since this seems highly unlikely. */
4777 if (reload_secondary_reload[j] >= 0)
4779 /* Prevent normal processing of this reload. */
4781 /* Output a special code sequence for this case. */
4783 = inc_for_reload (reloadreg, oldequiv, reload_inc[j], where);
4786 /* If we are reloading a pseudo-register that was set by the previous
4787 insn, see if we can get rid of that pseudo-register entirely
4788 by redirecting the previous insn into our reload register. */
4790 else if (optimize && GET_CODE (old) == REG
4791 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4792 && dead_or_set_p (insn, old)
4793 /* This is unsafe if some other reload
4794 uses the same reg first. */
4795 && (reload_when_needed[j] == RELOAD_OTHER
4796 || reload_when_needed[j] == RELOAD_FOR_INPUT
4797 || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS))
4799 rtx temp = PREV_INSN (insn);
4800 while (temp && GET_CODE (temp) == NOTE)
4801 temp = PREV_INSN (temp);
4803 && GET_CODE (temp) == INSN
4804 && GET_CODE (PATTERN (temp)) == SET
4805 && SET_DEST (PATTERN (temp)) == old
4806 /* Make sure we can access insn_operand_constraint. */
4807 && asm_noperands (PATTERN (temp)) < 0
4808 /* This is unsafe if prev insn rejects our reload reg. */
4809 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
4811 /* This is unsafe if operand occurs more than once in current
4812 insn. Perhaps some occurrences aren't reloaded. */
4813 && count_occurrences (PATTERN (insn), old) == 1
4814 /* Don't risk splitting a matching pair of operands. */
4815 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
4817 /* Store into the reload register instead of the pseudo. */
4818 SET_DEST (PATTERN (temp)) = reloadreg;
4819 /* If these are the only uses of the pseudo reg,
4820 pretend for GDB it lives in the reload reg we used. */
4821 if (reg_n_deaths[REGNO (old)] == 1
4822 && reg_n_sets[REGNO (old)] == 1)
4824 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
4825 alter_reg (REGNO (old), -1);
4831 /* We can't do that, so output an insn to load RELOADREG.
4832 Keep them in the following order:
4833 all reloads for input reload addresses,
4834 all reloads for ordinary input operands,
4835 all reloads for addresses of non-reloaded operands,
4836 the insn being reloaded,
4837 all reloads for addresses of output reloads,
4838 the output reloads. */
4841 #ifdef SECONDARY_INPUT_RELOAD_CLASS
4842 rtx second_reload_reg = 0;
4843 enum insn_code icode;
4845 /* If we have a secondary reload, pick up the secondary register
4846 and icode, if any. If OLDEQUIV and OLD are different or
4847 if this is an in-out reload, recompute whether or not we
4848 still need a secondary register and what the icode should
4849 be. If we still need a secondary register and the class or
4850 icode is different, go back to reloading from OLD if using
4851 OLDEQUIV means that we got the wrong type of register. We
4852 cannot have different class or icode due to an in-out reload
4853 because we don't make such reloads when both the input and
4854 output need secondary reload registers. */
4856 if (reload_secondary_reload[j] >= 0)
4858 int secondary_reload = reload_secondary_reload[j];
4859 rtx real_oldequiv = oldequiv;
4862 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
4863 and similarly for OLD.
4864 See comments in find_secondary_reload in reload.c. */
4865 if (GET_CODE (oldequiv) == REG
4866 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
4867 && reg_equiv_mem[REGNO (oldequiv)] != 0)
4868 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
4870 if (GET_CODE (old) == REG
4871 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4872 && reg_equiv_mem[REGNO (old)] != 0)
4873 real_old = reg_equiv_mem[REGNO (old)];
4875 second_reload_reg = reload_reg_rtx[secondary_reload];
4876 icode = reload_secondary_icode[j];
4878 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
4879 || (reload_in[j] != 0 && reload_out[j] != 0))
4881 enum reg_class new_class
4882 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
4883 mode, real_oldequiv);
4885 if (new_class == NO_REGS)
4886 second_reload_reg = 0;
4889 enum insn_code new_icode;
4890 enum machine_mode new_mode;
4892 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
4893 REGNO (second_reload_reg)))
4894 oldequiv = old, real_oldequiv = real_old;
4897 new_icode = reload_in_optab[(int) mode];
4898 if (new_icode != CODE_FOR_nothing
4899 && ((insn_operand_predicate[(int) new_icode][0]
4900 && ! ((*insn_operand_predicate[(int) new_icode][0])
4902 || (insn_operand_predicate[(int) new_icode][1]
4903 && ! ((*insn_operand_predicate[(int) new_icode][1])
4904 (real_oldequiv, mode)))))
4905 new_icode = CODE_FOR_nothing;
4907 if (new_icode == CODE_FOR_nothing)
4910 new_mode = insn_operand_mode[new_icode][2];
4912 if (GET_MODE (second_reload_reg) != new_mode)
4914 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
4916 oldequiv = old, real_oldequiv = real_old;
4919 = gen_reg_rtx (REG, new_mode,
4920 REGNO (second_reload_reg));
4926 /* If we still need a secondary reload register, check
4927 to see if it is being used as a scratch or intermediate
4928 register and generate code appropriately. If we need
4929 a scratch register, use REAL_OLDEQUIV since the form of
4930 the insn may depend on the actual address if it is
4933 if (second_reload_reg)
4935 if (icode != CODE_FOR_nothing)
4937 reload_insn = emit_insn_before (GEN_FCN (icode)
4942 if (this_reload_insn == 0)
4943 this_reload_insn = reload_insn;
4948 /* See if we need a scratch register to load the
4949 intermediate register (a tertiary reload). */
4950 enum insn_code tertiary_icode
4951 = reload_secondary_icode[secondary_reload];
4953 if (tertiary_icode != CODE_FOR_nothing)
4955 rtx third_reload_reg
4956 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
4959 = emit_insn_before ((GEN_FCN (tertiary_icode)
4964 if (this_reload_insn == 0)
4965 this_reload_insn = reload_insn;
4970 = gen_input_reload (second_reload_reg,
4972 if (this_reload_insn == 0)
4973 this_reload_insn = reload_insn;
4974 oldequiv = second_reload_reg;
4983 reload_insn = gen_input_reload (reloadreg, oldequiv, where);
4984 if (this_reload_insn == 0)
4985 this_reload_insn = reload_insn;
4988 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
4989 /* We may have to make a REG_DEAD note for the secondary reload
4990 register in the insns we just made. Find the last insn that
4991 mentioned the register. */
4992 if (! special && second_reload_reg
4993 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
4998 prev != PREV_INSN (this_reload_insn);
4999 prev = PREV_INSN (prev))
5000 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5001 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5004 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5013 /* Update where to put other reload insns. */
5014 if (this_reload_insn)
5015 switch (reload_when_needed[j])
5017 case RELOAD_FOR_INPUT:
5019 if (first_other_reload_insn == first_operand_address_reload_insn)
5020 first_other_reload_insn = this_reload_insn;
5022 case RELOAD_FOR_OPERAND_ADDRESS:
5023 if (first_operand_address_reload_insn == before_insn)
5024 first_operand_address_reload_insn = this_reload_insn;
5025 if (first_other_reload_insn == before_insn)
5026 first_other_reload_insn = this_reload_insn;
5029 /* reload_inc[j] was formerly processed here. */
5032 /* Add a note saying the input reload reg
5033 dies in this insn, if anyone cares. */
5034 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5036 && reload_reg_rtx[j] != old
5037 && reload_reg_rtx[j] != 0
5038 && reload_out[j] == 0
5039 && ! reload_inherited[j]
5040 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5042 register rtx reloadreg = reload_reg_rtx[j];
5045 /* We can't abort here because we need to support this for sched.c.
5046 It's not terrible to miss a REG_DEAD note, but we should try
5047 to figure out how to do this correctly. */
5048 /* The code below is incorrect for address-only reloads. */
5049 if (reload_when_needed[j] != RELOAD_OTHER
5050 && reload_when_needed[j] != RELOAD_FOR_INPUT)
5054 /* Add a death note to this insn, for an input reload. */
5056 if ((reload_when_needed[j] == RELOAD_OTHER
5057 || reload_when_needed[j] == RELOAD_FOR_INPUT)
5058 && ! dead_or_set_p (insn, reloadreg))
5060 = gen_rtx (EXPR_LIST, REG_DEAD,
5061 reloadreg, REG_NOTES (insn));
5064 /* When we inherit a reload, the last marked death of the reload reg
5065 may no longer really be a death. */
5066 if (reload_reg_rtx[j] != 0
5067 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5068 && reload_inherited[j])
5070 /* Handle inheriting an output reload.
5071 Remove the death note from the output reload insn. */
5072 if (reload_spill_index[j] >= 0
5073 && GET_CODE (reload_in[j]) == REG
5074 && spill_reg_store[reload_spill_index[j]] != 0
5075 && find_regno_note (spill_reg_store[reload_spill_index[j]],
5076 REG_DEAD, REGNO (reload_reg_rtx[j])))
5077 remove_death (REGNO (reload_reg_rtx[j]),
5078 spill_reg_store[reload_spill_index[j]]);
5079 /* Likewise for input reloads that were inherited. */
5080 else if (reload_spill_index[j] >= 0
5081 && GET_CODE (reload_in[j]) == REG
5082 && spill_reg_store[reload_spill_index[j]] == 0
5083 && reload_inheritance_insn[j] != 0
5084 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5085 REGNO (reload_reg_rtx[j])))
5086 remove_death (REGNO (reload_reg_rtx[j]),
5087 reload_inheritance_insn[j]);
5092 /* We got this register from find_equiv_reg.
5093 Search back for its last death note and get rid of it.
5094 But don't search back too far.
5095 Don't go past a place where this reg is set,
5096 since a death note before that remains valid. */
5097 for (prev = PREV_INSN (insn);
5098 prev && GET_CODE (prev) != CODE_LABEL;
5099 prev = PREV_INSN (prev))
5100 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5101 && dead_or_set_p (prev, reload_reg_rtx[j]))
5103 if (find_regno_note (prev, REG_DEAD,
5104 REGNO (reload_reg_rtx[j])))
5105 remove_death (REGNO (reload_reg_rtx[j]), prev);
5111 /* We might have used find_equiv_reg above to choose an alternate
5112 place from which to reload. If so, and it died, we need to remove
5113 that death and move it to one of the insns we just made. */
5115 if (oldequiv_reg != 0
5116 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5120 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5121 prev = PREV_INSN (prev))
5122 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5123 && dead_or_set_p (prev, oldequiv_reg))
5125 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5127 for (prev1 = this_reload_insn;
5128 prev1; prev1 = PREV_INSN (prev1))
5129 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5130 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5133 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5138 remove_death (REGNO (oldequiv_reg), prev);
5145 /* If we are reloading a register that was recently stored in with an
5146 output-reload, see if we can prove there was
5147 actually no need to store the old value in it. */
5149 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5150 /* This is unsafe if some other reload uses the same reg first. */
5151 && (reload_when_needed[j] == RELOAD_OTHER
5152 || reload_when_needed[j] == RELOAD_FOR_INPUT
5153 || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS)
5154 && GET_CODE (reload_in[j]) == REG
5156 /* There doesn't seem to be any reason to restrict this to pseudos
5157 and doing so loses in the case where we are copying from a
5158 register of the wrong class. */
5159 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5161 && spill_reg_store[reload_spill_index[j]] != 0
5162 && dead_or_set_p (insn, reload_in[j])
5163 /* This is unsafe if operand occurs more than once in current
5164 insn. Perhaps some occurrences weren't reloaded. */
5165 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5166 delete_output_reload (insn, j,
5167 spill_reg_store[reload_spill_index[j]]);
5169 /* Input-reloading is done. Now do output-reloading,
5170 storing the value from the reload-register after the main insn
5171 if reload_out[j] is nonzero.
5173 ??? At some point we need to support handling output reloads of
5174 JUMP_INSNs or insns that set cc0. */
5175 old = reload_out[j];
5177 && reload_reg_rtx[j] != old
5178 && reload_reg_rtx[j] != 0)
5180 register rtx reloadreg = reload_reg_rtx[j];
5181 register rtx second_reloadreg = 0;
5182 rtx prev_insn = PREV_INSN (first_output_reload_insn);
5184 enum machine_mode mode;
5187 /* An output operand that dies right away does need a reload,
5188 but need not be copied from it. Show the new location in the
5190 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5191 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5193 XEXP (note, 0) = reload_reg_rtx[j];
5196 else if (GET_CODE (old) == SCRATCH)
5197 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5198 but we don't want to make an output reload. */
5202 /* Strip off of OLD any size-increasing SUBREGs such as
5203 (SUBREG:SI foo:QI 0). */
5205 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5206 && (GET_MODE_SIZE (GET_MODE (old))
5207 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5208 old = SUBREG_REG (old);
5211 /* If is a JUMP_INSN, we can't support output reloads yet. */
5212 if (GET_CODE (insn) == JUMP_INSN)
5215 /* Determine the mode to reload in.
5216 See comments above (for input reloading). */
5218 mode = GET_MODE (old);
5219 if (mode == VOIDmode)
5220 abort (); /* Should never happen for an output. */
5222 /* A strict-low-part output operand needs to be reloaded
5223 in the mode of the entire value. */
5224 if (reload_strict_low[j])
5226 mode = GET_MODE (SUBREG_REG (reload_out[j]));
5227 /* Encapsulate OLD into that mode. */
5228 /* If OLD is a subreg, then strip it, since the subreg will
5229 be altered by this very reload. */
5230 while (GET_CODE (old) == SUBREG && GET_MODE (old) != mode)
5231 old = SUBREG_REG (old);
5232 if (GET_MODE (old) != VOIDmode
5233 && mode != GET_MODE (old))
5234 old = gen_rtx (SUBREG, mode, old, 0);
5237 if (GET_MODE (reloadreg) != mode)
5238 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5240 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5242 /* If we need two reload regs, set RELOADREG to the intermediate
5243 one, since it will be stored into OUT. We might need a secondary
5244 register only for an input reload, so check again here. */
5246 if (reload_secondary_reload[j] >= 0)
5250 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5251 && reg_equiv_mem[REGNO (old)] != 0)
5252 real_old = reg_equiv_mem[REGNO (old)];
5254 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
5258 second_reloadreg = reloadreg;
5259 reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
5261 /* See if RELOADREG is to be used as a scratch register
5262 or as an intermediate register. */
5263 if (reload_secondary_icode[j] != CODE_FOR_nothing)
5265 emit_insn_before ((GEN_FCN (reload_secondary_icode[j])
5266 (real_old, second_reloadreg,
5268 first_output_reload_insn);
5273 /* See if we need both a scratch and intermediate reload
5275 int secondary_reload = reload_secondary_reload[j];
5276 enum insn_code tertiary_icode
5277 = reload_secondary_icode[secondary_reload];
5280 if (GET_MODE (reloadreg) != mode)
5281 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5283 if (tertiary_icode != CODE_FOR_nothing)
5286 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5287 pat = (GEN_FCN (tertiary_icode)
5288 (reloadreg, second_reloadreg, third_reloadreg));
5291 pat = gen_move_insn (reloadreg, second_reloadreg);
5293 emit_insn_before (pat, first_output_reload_insn);
5299 /* Output the last reload insn. */
5301 emit_insn_before (gen_move_insn (old, reloadreg),
5302 first_output_reload_insn);
5304 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5305 /* If final will look at death notes for this reg,
5306 put one on the last output-reload insn to use it. Similarly
5307 for any secondary register. */
5308 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
5309 for (p = PREV_INSN (first_output_reload_insn);
5310 p != prev_insn; p = PREV_INSN (p))
5311 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5312 && reg_overlap_mentioned_for_reload_p (reloadreg,
5314 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5315 reloadreg, REG_NOTES (p));
5317 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5319 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
5320 for (p = PREV_INSN (first_output_reload_insn);
5321 p != prev_insn; p = PREV_INSN (p))
5322 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5323 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
5325 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5326 second_reloadreg, REG_NOTES (p));
5329 /* Look at all insns we emitted, just to be safe. */
5330 for (p = NEXT_INSN (prev_insn); p != first_output_reload_insn;
5332 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5334 /* If this output reload doesn't come from a spill reg,
5335 clear any memory of reloaded copies of the pseudo reg.
5336 If this output reload comes from a spill reg,
5337 reg_has_output_reload will make this do nothing. */
5338 note_stores (PATTERN (p), forget_old_reloads_1);
5340 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
5344 first_output_reload_insn = NEXT_INSN (prev_insn);
5347 if (reload_spill_index[j] >= 0)
5348 new_spill_reg_store[reload_spill_index[j]] = store_insn;
5351 /* Move death notes from INSN
5352 to output-operand-address and output reload insns. */
5353 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5356 /* Loop over those insns, last ones first. */
5357 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
5358 insn1 = PREV_INSN (insn1))
5359 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
5361 rtx source = SET_SRC (PATTERN (insn1));
5362 rtx dest = SET_DEST (PATTERN (insn1));
5364 /* The note we will examine next. */
5365 rtx reg_notes = REG_NOTES (insn);
5366 /* The place that pointed to this note. */
5367 rtx *prev_reg_note = ®_NOTES (insn);
5369 /* If the note is for something used in the source of this
5370 reload insn, or in the output address, move the note. */
5373 rtx next_reg_notes = XEXP (reg_notes, 1);
5374 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
5375 && GET_CODE (XEXP (reg_notes, 0)) == REG
5376 && ((GET_CODE (dest) != REG
5377 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5379 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5382 *prev_reg_note = next_reg_notes;
5383 XEXP (reg_notes, 1) = REG_NOTES (insn1);
5384 REG_NOTES (insn1) = reg_notes;
5387 prev_reg_note = &XEXP (reg_notes, 1);
5389 reg_notes = next_reg_notes;
5395 /* For all the spill regs newly reloaded in this instruction,
5396 record what they were reloaded from, so subsequent instructions
5397 can inherit the reloads.
5399 Update spill_reg_store for the reloads of this insn.
5400 Copy the elements that were updated in the loop above. */
5402 for (j = 0; j < n_reloads; j++)
5404 register int r = reload_order[j];
5405 register int i = reload_spill_index[r];
5407 /* I is nonneg if this reload used one of the spill regs.
5408 If reload_reg_rtx[r] is 0, this is an optional reload
5409 that we opted to ignore. */
5411 if (i >= 0 && reload_reg_rtx[r] != 0)
5413 /* First, clear out memory of what used to be in this spill reg.
5414 If consecutive registers are used, clear them all. */
5416 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
5419 for (k = 0; k < nr; k++)
5421 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
5422 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
5425 /* Maybe the spill reg contains a copy of reload_out. */
5426 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5428 register int nregno = REGNO (reload_out[r]);
5430 spill_reg_store[i] = new_spill_reg_store[i];
5431 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5433 for (k = 0; k < nr; k++)
5435 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5437 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
5441 /* Maybe the spill reg contains a copy of reload_in. */
5442 else if (reload_out[r] == 0
5443 && reload_in[r] != 0
5444 && (GET_CODE (reload_in[r]) == REG
5445 || GET_CODE (reload_in_reg[r]) == REG))
5447 register int nregno;
5448 if (GET_CODE (reload_in[r]) == REG)
5449 nregno = REGNO (reload_in[r]);
5451 nregno = REGNO (reload_in_reg[r]);
5453 /* If there are two separate reloads (one in and one out)
5454 for the same (hard or pseudo) reg,
5455 leave reg_last_reload_reg set
5456 based on the output reload.
5457 Otherwise, set it from this input reload. */
5458 if (!reg_has_output_reload[nregno]
5459 /* But don't do so if another input reload
5460 will clobber this one's value. */
5461 && reload_reg_reaches_end_p (spill_regs[i],
5462 reload_when_needed[r]))
5464 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5466 /* Unless we inherited this reload, show we haven't
5467 recently done a store. */
5468 if (! reload_inherited[r])
5469 spill_reg_store[i] = 0;
5471 for (k = 0; k < nr; k++)
5473 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5475 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
5482 /* The following if-statement was #if 0'd in 1.34 (or before...).
5483 It's reenabled in 1.35 because supposedly nothing else
5484 deals with this problem. */
5486 /* If a register gets output-reloaded from a non-spill register,
5487 that invalidates any previous reloaded copy of it.
5488 But forget_old_reloads_1 won't get to see it, because
5489 it thinks only about the original insn. So invalidate it here. */
5490 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5492 register int nregno = REGNO (reload_out[r]);
5493 reg_last_reload_reg[nregno] = 0;
5498 /* Emit code before BEFORE_INSN to perform an input reload of IN to RELOADREG.
5499 Returns first insn emitted. */
5502 gen_input_reload (reloadreg, in, before_insn)
5507 register rtx prev_insn = PREV_INSN (before_insn);
5509 /* How to do this reload can get quite tricky. Normally, we are being
5510 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
5511 register that didn't get a hard register. In that case we can just
5512 call emit_move_insn.
5514 We can also be asked to reload a PLUS that adds either two registers or
5515 a register and a constant or MEM. This can occur during frame pointer
5516 elimination. That case if handled by trying to emit a single insn
5517 to perform the add. If it is not valid, we use a two insn sequence.
5519 Finally, we could be called to handle an 'o' constraint by putting
5520 an address into a register. In that case, we first try to do this
5521 with a named pattern of "reload_load_address". If no such pattern
5522 exists, we just emit a SET insn and hope for the best (it will normally
5523 be valid on machines that use 'o').
5525 This entire process is made complex because reload will never
5526 process the insns we generate here and so we must ensure that
5527 they will fit their constraints and also by the fact that parts of
5528 IN might be being reloaded separately and replaced with spill registers.
5529 Because of this, we are, in some sense, just guessing the right approach
5530 here. The one listed above seems to work.
5532 ??? At some point, this whole thing needs to be rethought. */
5534 if (GET_CODE (in) == PLUS
5535 && GET_CODE (XEXP (in, 0)) == REG
5536 && (GET_CODE (XEXP (in, 1)) == REG
5537 || CONSTANT_P (XEXP (in, 1))
5538 || GET_CODE (XEXP (in, 1)) == MEM))
5540 /* We need to compute the sum of what is either a register and a
5541 constant, a register and memory, or a hard register and a pseudo
5542 register and put it into the reload register. The best possible way
5543 of doing this is if the machine has a three-operand ADD insn that
5544 accepts the required operands.
5546 The simplest approach is to try to generate such an insn and see if it
5547 is recognized and matches its constraints. If so, it can be used.
5549 It might be better not to actually emit the insn unless it is valid,
5550 but we need to pass the insn as an operand to `recog' and
5551 `insn_extract' and it is simpler to emit and then delete the insn if
5552 not valid than to dummy things up. */
5554 rtx op0, op1, tem, insn;
5557 op0 = find_replacement (&XEXP (in, 0));
5558 op1 = find_replacement (&XEXP (in, 1));
5560 /* Since constraint checking is strict, commutativity won't be
5561 checked, so we need to do that here to avoid spurious failure
5562 if the add instruction is two-address and the second operand
5563 of the add is the same as the reload reg, which is frequently
5564 the case. If the insn would be A = B + A, rearrange it so
5565 it will be A = A + B as constrain_operands expects. */
5567 if (GET_CODE (XEXP (in, 1)) == REG
5568 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
5569 tem = op0, op0 = op1, op1 = tem;
5571 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
5572 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
5574 insn = emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in),
5576 code = recog_memoized (insn);
5580 insn_extract (insn);
5581 /* We want constrain operands to treat this insn strictly in
5582 its validity determination, i.e., the way it would after reload
5584 if (constrain_operands (code, 1))
5588 if (PREV_INSN (insn))
5589 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
5590 if (NEXT_INSN (insn))
5591 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
5593 /* If that failed, we must use a conservative two-insn sequence.
5594 use move to copy constant, MEM, or pseudo register to the reload
5595 register since "move" will be able to handle an arbitrary operand,
5596 unlike add which can't, in general. Then add the registers.
5598 If there is another way to do this for a specific machine, a
5599 DEFINE_PEEPHOLE should be specified that recognizes the sequence
5602 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
5603 || (GET_CODE (op1) == REG
5604 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
5605 tem = op0, op0 = op1, op1 = tem;
5607 emit_insn_before (gen_move_insn (reloadreg, op0), before_insn);
5608 emit_insn_before (gen_add2_insn (reloadreg, op1), before_insn);
5611 /* If IN is a simple operand, use gen_move_insn. */
5612 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
5613 emit_insn_before (gen_move_insn (reloadreg, in), before_insn);
5615 #ifdef HAVE_reload_load_address
5616 else if (HAVE_reload_load_address)
5617 emit_insn_before (gen_reload_load_address (reloadreg, in), before_insn);
5620 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
5622 emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in), before_insn);
5624 /* Return the first insn emitted.
5625 We can not just return PREV_INSN (before_insn), because there may have
5626 been multiple instructions emitted. Also note that gen_move_insn may
5627 emit more than one insn itself, so we can not assume that there is one
5628 insn emitted per emit_insn_before call. */
5630 return NEXT_INSN (prev_insn);
5633 /* Delete a previously made output-reload
5634 whose result we now believe is not needed.
5635 First we double-check.
5637 INSN is the insn now being processed.
5638 OUTPUT_RELOAD_INSN is the insn of the output reload.
5639 J is the reload-number for this insn. */
5642 delete_output_reload (insn, j, output_reload_insn)
5645 rtx output_reload_insn;
5649 /* Get the raw pseudo-register referred to. */
5651 rtx reg = reload_in[j];
5652 while (GET_CODE (reg) == SUBREG)
5653 reg = SUBREG_REG (reg);
5655 /* If the pseudo-reg we are reloading is no longer referenced
5656 anywhere between the store into it and here,
5657 and no jumps or labels intervene, then the value can get
5658 here through the reload reg alone.
5659 Otherwise, give up--return. */
5660 for (i1 = NEXT_INSN (output_reload_insn);
5661 i1 != insn; i1 = NEXT_INSN (i1))
5663 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
5665 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
5666 && reg_mentioned_p (reg, PATTERN (i1)))
5670 /* If this insn will store in the pseudo again,
5671 the previous store can be removed. */
5672 if (reload_out[j] == reload_in[j])
5673 delete_insn (output_reload_insn);
5675 /* See if the pseudo reg has been completely replaced
5676 with reload regs. If so, delete the store insn
5677 and forget we had a stack slot for the pseudo. */
5678 else if (reg_n_deaths[REGNO (reg)] == 1
5679 && reg_basic_block[REGNO (reg)] >= 0
5680 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
5684 /* We know that it was used only between here
5685 and the beginning of the current basic block.
5686 (We also know that the last use before INSN was
5687 the output reload we are thinking of deleting, but never mind that.)
5688 Search that range; see if any ref remains. */
5689 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5691 rtx set = single_set (i2);
5693 /* Uses which just store in the pseudo don't count,
5694 since if they are the only uses, they are dead. */
5695 if (set != 0 && SET_DEST (set) == reg)
5697 if (GET_CODE (i2) == CODE_LABEL
5698 || GET_CODE (i2) == JUMP_INSN)
5700 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
5701 && reg_mentioned_p (reg, PATTERN (i2)))
5702 /* Some other ref remains;
5703 we can't do anything. */
5707 /* Delete the now-dead stores into this pseudo. */
5708 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5710 rtx set = single_set (i2);
5712 if (set != 0 && SET_DEST (set) == reg)
5714 if (GET_CODE (i2) == CODE_LABEL
5715 || GET_CODE (i2) == JUMP_INSN)
5719 /* For the debugging info,
5720 say the pseudo lives in this reload reg. */
5721 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
5722 alter_reg (REGNO (reg), -1);
5727 /* Output reload-insns to reload VALUE into RELOADREG.
5728 VALUE is a autoincrement or autodecrement RTX whose operand
5729 is a register or memory location;
5730 so reloading involves incrementing that location.
5732 INC_AMOUNT is the number to increment or decrement by (always positive).
5733 This cannot be deduced from VALUE.
5735 INSN is the insn before which the new insns should be emitted.
5737 The return value is the first of the insns emitted. */
5740 inc_for_reload (reloadreg, value, inc_amount, insn)
5746 /* REG or MEM to be copied and incremented. */
5747 rtx incloc = XEXP (value, 0);
5748 /* Nonzero if increment after copying. */
5749 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
5750 rtx prev = PREV_INSN (insn);
5755 /* No hard register is equivalent to this register after
5756 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
5757 we could inc/dec that register as well (maybe even using it for
5758 the source), but I'm not sure it's worth worrying about. */
5759 if (GET_CODE (incloc) == REG)
5760 reg_last_reload_reg[REGNO (incloc)] = 0;
5762 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
5763 inc_amount = - inc_amount;
5765 inc = GEN_INT (inc_amount);
5767 /* If this is post-increment, first copy the location to the reload reg. */
5769 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5771 /* See if we can directly increment INCLOC. Use a method similar to that
5772 in gen_input_reload. */
5774 add_insn = emit_insn_before (gen_rtx (SET, VOIDmode, incloc,
5775 gen_rtx (PLUS, GET_MODE (incloc),
5776 incloc, inc)), insn);
5778 code = recog_memoized (add_insn);
5781 insn_extract (add_insn);
5782 if (constrain_operands (code, 1))
5784 /* If this is a pre-increment and we have incremented the value
5785 where it lives, copy the incremented value to RELOADREG to
5786 be used as an address. */
5789 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5790 return NEXT_INSN (prev);
5794 if (PREV_INSN (add_insn))
5795 NEXT_INSN (PREV_INSN (add_insn)) = NEXT_INSN (add_insn);
5796 if (NEXT_INSN (add_insn))
5797 PREV_INSN (NEXT_INSN (add_insn)) = PREV_INSN (add_insn);
5799 /* If couldn't do the increment directly, must increment in RELOADREG.
5800 The way we do this depends on whether this is pre- or post-increment.
5801 For pre-increment, copy INCLOC to the reload register, increment it
5802 there, then save back. */
5806 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5807 emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
5808 emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
5813 Because this might be a jump insn or a compare, and because RELOADREG
5814 may not be available after the insn in an input reload, we must do
5815 the incrementation before the insn being reloaded for.
5817 We have already copied INCLOC to RELOADREG. Increment the copy in
5818 RELOADREG, save that back, then decrement RELOADREG so it has
5819 the original value. */
5821 emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
5822 emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
5823 emit_insn_before (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)),
5827 return NEXT_INSN (prev);
5830 /* Return 1 if we are certain that the constraint-string STRING allows
5831 the hard register REG. Return 0 if we can't be sure of this. */
5834 constraint_accepts_reg_p (string, reg)
5839 int regno = true_regnum (reg);
5842 /* Initialize for first alternative. */
5844 /* Check that each alternative contains `g' or `r'. */
5846 switch (c = *string++)
5849 /* If an alternative lacks `g' or `r', we lose. */
5852 /* If an alternative lacks `g' or `r', we lose. */
5855 /* Initialize for next alternative. */
5860 /* Any general reg wins for this alternative. */
5861 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
5865 /* Any reg in specified class wins for this alternative. */
5867 enum reg_class class = REG_CLASS_FROM_LETTER (c);
5869 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
5875 /* Return the number of places FIND appears within X, but don't count
5876 an occurrence if some SET_DEST is FIND. */
5879 count_occurrences (x, find)
5880 register rtx x, find;
5883 register enum rtx_code code;
5884 register char *format_ptr;
5892 code = GET_CODE (x);
5907 if (SET_DEST (x) == find)
5908 return count_occurrences (SET_SRC (x), find);
5912 format_ptr = GET_RTX_FORMAT (code);
5915 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5917 switch (*format_ptr++)
5920 count += count_occurrences (XEXP (x, i), find);
5924 if (XVEC (x, i) != NULL)
5926 for (j = 0; j < XVECLEN (x, i); j++)
5927 count += count_occurrences (XVECEXP (x, i, j), find);
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