1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-flags.h"
33 #include "insn-codes.h"
38 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
84 #ifndef REGISTER_MOVE_COST
85 #define REGISTER_MOVE_COST(x, y) 2
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx *reg_last_reload_reg;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static char *reg_has_output_reload;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload;
100 /* Element N is the constant value to which pseudo reg N is equivalent,
101 or zero if pseudo reg N is not equivalent to a constant.
102 find_reloads looks at this in order to replace pseudo reg N
103 with the constant it stands for. */
104 rtx *reg_equiv_constant;
106 /* Element N is a memory location to which pseudo reg N is equivalent,
107 prior to any register elimination (such as frame pointer to stack
108 pointer). Depending on whether or not it is a valid address, this value
109 is transferred to either reg_equiv_address or reg_equiv_mem. */
110 rtx *reg_equiv_memory_loc;
112 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
113 This is used when the address is not valid as a memory address
114 (because its displacement is too big for the machine.) */
115 rtx *reg_equiv_address;
117 /* Element N is the memory slot to which pseudo reg N is equivalent,
118 or zero if pseudo reg N is not equivalent to a memory slot. */
121 /* Widest width in which each pseudo reg is referred to (via subreg). */
122 static int *reg_max_ref_width;
124 /* Element N is the list of insns that initialized reg N from its equivalent
125 constant or memory slot. */
126 static rtx *reg_equiv_init;
128 /* Vector to remember old contents of reg_renumber before spilling. */
129 static short *reg_old_renumber;
131 /* During reload_as_needed, element N contains the last pseudo regno reloaded
132 into hard register N. If that pseudo reg occupied more than one register,
133 reg_reloaded_contents points to that pseudo for each spill register in
134 use; all of these must remain set for an inheritance to occur. */
135 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
137 /* During reload_as_needed, element N contains the insn for which
138 hard register N was last used. Its contents are significant only
139 when reg_reloaded_valid is set for this register. */
140 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
142 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
143 static HARD_REG_SET reg_reloaded_valid;
144 /* Indicate if the register was dead at the end of the reload.
145 This is only valid if reg_reloaded_contents is set and valid. */
146 static HARD_REG_SET reg_reloaded_dead;
148 /* Number of spill-regs so far; number of valid elements of spill_regs. */
151 /* In parallel with spill_regs, contains REG rtx's for those regs.
152 Holds the last rtx used for any given reg, or 0 if it has never
153 been used for spilling yet. This rtx is reused, provided it has
155 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
157 /* In parallel with spill_regs, contains nonzero for a spill reg
158 that was stored after the last time it was used.
159 The precise value is the insn generated to do the store. */
160 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
162 /* This is the register that was stored with spill_reg_store. This is a
163 copy of reload_out / reload_out_reg when the value was stored; if
164 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
165 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
167 /* This table is the inverse mapping of spill_regs:
168 indexed by hard reg number,
169 it contains the position of that reg in spill_regs,
170 or -1 for something that is not in spill_regs.
172 ?!? This is no longer accurate. */
173 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
175 /* This reg set indicates registers that can't be used as spill registers for
176 the currently processed insn. These are the hard registers which are live
177 during the insn, but not allocated to pseudos, as well as fixed
179 static HARD_REG_SET bad_spill_regs;
181 /* These are the hard registers that can't be used as spill register for any
182 insn. This includes registers used for user variables and registers that
183 we can't eliminate. A register that appears in this set also can't be used
184 to retry register allocation. */
185 static HARD_REG_SET bad_spill_regs_global;
187 /* Describes order of use of registers for reloading
188 of spilled pseudo-registers. `n_spills' is the number of
189 elements that are actually valid; new ones are added at the end.
191 Both spill_regs and spill_reg_order are used on two occasions:
192 once during find_reload_regs, where they keep track of the spill registers
193 for a single insn, but also during reload_as_needed where they show all
194 the registers ever used by reload. For the latter case, the information
195 is calculated during finish_spills. */
196 static short spill_regs[FIRST_PSEUDO_REGISTER];
198 /* This vector of reg sets indicates, for each pseudo, which hard registers
199 may not be used for retrying global allocation because the register was
200 formerly spilled from one of them. If we allowed reallocating a pseudo to
201 a register that it was already allocated to, reload might not
203 static HARD_REG_SET *pseudo_previous_regs;
205 /* This vector of reg sets indicates, for each pseudo, which hard
206 registers may not be used for retrying global allocation because they
207 are used as spill registers during one of the insns in which the
209 static HARD_REG_SET *pseudo_forbidden_regs;
211 /* All hard regs that have been used as spill registers for any insn are
212 marked in this set. */
213 static HARD_REG_SET used_spill_regs;
215 /* Index of last register assigned as a spill register. We allocate in
216 a round-robin fashion. */
217 static int last_spill_reg;
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset_head spilled_pseudos;
244 /* Used for communication between order_regs_for_reload and count_pseudo.
245 Used to avoid counting one pseudo twice. */
246 static regset_head pseudos_counted;
248 /* First uid used by insns created by reload in this function.
249 Used in find_equiv_reg. */
250 int reload_first_uid;
252 /* Flag set by local-alloc or global-alloc if anything is live in
253 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* Set to 1 while reload_as_needed is operating.
257 Required by some machines to handle any generated moves differently. */
258 int reload_in_progress = 0;
260 /* These arrays record the insn_code of insns that may be needed to
261 perform input and output reloads of special objects. They provide a
262 place to pass a scratch register. */
263 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
264 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
266 /* This obstack is used for allocation of rtl during register elimination.
267 The allocated storage can be freed once find_reloads has processed the
269 struct obstack reload_obstack;
271 /* Points to the beginning of the reload_obstack. All insn_chain structures
272 are allocated first. */
273 char *reload_startobj;
275 /* The point after all insn_chain structures. Used to quickly deallocate
276 memory allocated in copy_reloads during calculate_needs_all_insns. */
277 char *reload_firstobj;
279 /* This points before all local rtl generated by register elimination.
280 Used to quickly free all memory after processing one insn. */
281 static char *reload_insn_firstobj;
283 #define obstack_chunk_alloc xmalloc
284 #define obstack_chunk_free free
286 /* List of insn_chain instructions, one for every insn that reload needs to
288 struct insn_chain *reload_insn_chain;
291 extern tree current_function_decl;
293 extern union tree_node *current_function_decl;
296 /* List of all insns needing reloads. */
297 static struct insn_chain *insns_need_reload;
299 /* This structure is used to record information about register eliminations.
300 Each array entry describes one possible way of eliminating a register
301 in favor of another. If there is more than one way of eliminating a
302 particular register, the most preferred should be specified first. */
306 int from; /* Register number to be eliminated. */
307 int to; /* Register number used as replacement. */
308 int initial_offset; /* Initial difference between values. */
309 int can_eliminate; /* Non-zero if this elimination can be done. */
310 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
311 insns made by reload. */
312 int offset; /* Current offset between the two regs. */
313 int previous_offset; /* Offset at end of previous insn. */
314 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
315 rtx from_rtx; /* REG rtx for the register to be eliminated.
316 We cannot simply compare the number since
317 we might then spuriously replace a hard
318 register corresponding to a pseudo
319 assigned to the reg to be eliminated. */
320 rtx to_rtx; /* REG rtx for the replacement. */
323 static struct elim_table * reg_eliminate = 0;
325 /* This is an intermediate structure to initialize the table. It has
326 exactly the members provided by ELIMINABLE_REGS. */
327 static struct elim_table_1
331 } reg_eliminate_1[] =
333 /* If a set of eliminable registers was specified, define the table from it.
334 Otherwise, default to the normal case of the frame pointer being
335 replaced by the stack pointer. */
337 #ifdef ELIMINABLE_REGS
340 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
343 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
345 /* Record the number of pending eliminations that have an offset not equal
346 to their initial offset. If non-zero, we use a new copy of each
347 replacement result in any insns encountered. */
348 int num_not_at_initial_offset;
350 /* Count the number of registers that we may be able to eliminate. */
351 static int num_eliminable;
352 /* And the number of registers that are equivalent to a constant that
353 can be eliminated to frame_pointer / arg_pointer + constant. */
354 static int num_eliminable_invariants;
356 /* For each label, we record the offset of each elimination. If we reach
357 a label by more than one path and an offset differs, we cannot do the
358 elimination. This information is indexed by the number of the label.
359 The first table is an array of flags that records whether we have yet
360 encountered a label and the second table is an array of arrays, one
361 entry in the latter array for each elimination. */
363 static char *offsets_known_at;
364 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
366 /* Number of labels in the current function. */
368 static int num_labels;
370 static void maybe_fix_stack_asms PARAMS ((void));
371 static void copy_reloads PARAMS ((struct insn_chain *));
372 static void calculate_needs_all_insns PARAMS ((int));
373 static int find_reg PARAMS ((struct insn_chain *, int,
375 static void find_reload_regs PARAMS ((struct insn_chain *, FILE *));
376 static void select_reload_regs PARAMS ((FILE *));
377 static void delete_caller_save_insns PARAMS ((void));
379 static void spill_failure PARAMS ((rtx, enum reg_class));
380 static void count_spilled_pseudo PARAMS ((int, int, int));
381 static void delete_dead_insn PARAMS ((rtx));
382 static void alter_reg PARAMS ((int, int));
383 static void set_label_offsets PARAMS ((rtx, rtx, int));
384 static void check_eliminable_occurrences PARAMS ((rtx));
385 static void elimination_effects PARAMS ((rtx, enum machine_mode));
386 static int eliminate_regs_in_insn PARAMS ((rtx, int));
387 static void update_eliminable_offsets PARAMS ((void));
388 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
389 static void set_initial_elim_offsets PARAMS ((void));
390 static void verify_initial_elim_offsets PARAMS ((void));
391 static void set_initial_label_offsets PARAMS ((void));
392 static void set_offsets_for_label PARAMS ((rtx));
393 static void init_elim_table PARAMS ((void));
394 static void update_eliminables PARAMS ((HARD_REG_SET *));
395 static void spill_hard_reg PARAMS ((int, FILE *, int));
396 static int finish_spills PARAMS ((int, FILE *));
397 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
398 static void scan_paradoxical_subregs PARAMS ((rtx));
399 static void count_pseudo PARAMS ((int));
400 static void order_regs_for_reload PARAMS ((struct insn_chain *));
401 static void reload_as_needed PARAMS ((int));
402 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
403 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
404 static void mark_reload_reg_in_use PARAMS ((int, int, enum reload_type,
406 static void clear_reload_reg_in_use PARAMS ((int, int, enum reload_type,
408 static int reload_reg_free_p PARAMS ((int, int, enum reload_type));
409 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
410 rtx, rtx, int, int));
411 static int reload_reg_reaches_end_p PARAMS ((int, int, enum reload_type));
412 static int allocate_reload_reg PARAMS ((struct insn_chain *, int, int));
413 static void failed_reload PARAMS ((rtx, int));
414 static int set_reload_reg PARAMS ((int, int));
415 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
416 static void choose_reload_regs PARAMS ((struct insn_chain *));
417 static void merge_assigned_reloads PARAMS ((rtx));
418 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
419 struct reload *, rtx, int));
420 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
421 struct reload *, int));
422 static void do_input_reload PARAMS ((struct insn_chain *,
423 struct reload *, int));
424 static void do_output_reload PARAMS ((struct insn_chain *,
425 struct reload *, int));
426 static void emit_reload_insns PARAMS ((struct insn_chain *));
427 static void delete_output_reload PARAMS ((rtx, int, int));
428 static void delete_address_reloads PARAMS ((rtx, rtx));
429 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
430 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
431 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
432 static void reload_cse_regs_1 PARAMS ((rtx));
433 static void reload_cse_invalidate_regno PARAMS ((int, enum machine_mode, int));
434 static int reload_cse_mem_conflict_p PARAMS ((rtx, rtx));
435 static void reload_cse_invalidate_mem PARAMS ((rtx));
436 static void reload_cse_invalidate_rtx PARAMS ((rtx, rtx, void *));
437 static int reload_cse_regno_equal_p PARAMS ((int, rtx, enum machine_mode));
438 static int reload_cse_noop_set_p PARAMS ((rtx, rtx));
439 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
440 static int reload_cse_simplify_operands PARAMS ((rtx));
441 static void reload_cse_check_clobber PARAMS ((rtx, rtx, void *));
442 static void reload_cse_record_set PARAMS ((rtx, rtx));
443 static void reload_combine PARAMS ((void));
444 static void reload_combine_note_use PARAMS ((rtx *, rtx));
445 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
446 static void reload_cse_move2add PARAMS ((rtx));
447 static void move2add_note_store PARAMS ((rtx, rtx, void *));
449 static void add_auto_inc_notes PARAMS ((rtx, rtx));
451 static rtx gen_mode_int PARAMS ((enum machine_mode,
453 static void failed_reload PARAMS ((rtx, int));
454 static int set_reload_reg PARAMS ((int, int));
455 extern void dump_needs PARAMS ((struct insn_chain *, FILE *));
457 /* Initialize the reload pass once per compilation. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&pseudos_counted);
513 /* List of insn chains that are currently unused. */
514 static struct insn_chain *unused_insn_chains = 0;
516 /* Allocate an empty insn_chain structure. */
520 struct insn_chain *c;
522 if (unused_insn_chains == 0)
524 c = (struct insn_chain *)
525 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
544 compute_use_by_pseudos (to, from)
549 EXECUTE_IF_SET_IN_REG_SET
550 (from, FIRST_PSEUDO_REGISTER, regno,
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from
557 BASIC_BLOCK->global_live_at_start, which might still
558 contain registers that have not actually been allocated
559 since they have an equivalence. */
560 if (! reload_completed)
565 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
567 SET_HARD_REG_BIT (*to, r + nregs);
572 /* Global variables used by reload and its subroutines. */
574 /* Set during calculate_needs if an insn needs register elimination. */
575 static int something_needs_elimination;
576 /* Set during calculate_needs if an insn needs an operand changed. */
577 int something_needs_operands_changed;
579 /* Nonzero means we couldn't get enough spill regs. */
582 /* Main entry point for the reload pass.
584 FIRST is the first insn of the function being compiled.
586 GLOBAL nonzero means we were called from global_alloc
587 and should attempt to reallocate any pseudoregs that we
588 displace from hard regs we will use for reloads.
589 If GLOBAL is zero, we do not have enough information to do that,
590 so any pseudo reg that is spilled must go to the stack.
592 DUMPFILE is the global-reg debugging dump file stream, or 0.
593 If it is nonzero, messages are written to it to describe
594 which registers are seized as reload regs, which pseudo regs
595 are spilled from them, and where the pseudo regs are reallocated to.
597 Return value is nonzero if reload failed
598 and we must not do any more for this function. */
601 reload (first, global, dumpfile)
608 register struct elim_table *ep;
610 /* The two pointers used to track the true location of the memory used
611 for label offsets. */
612 char *real_known_ptr = NULL_PTR;
613 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
615 /* Make sure even insns with volatile mem refs are recognizable. */
620 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
622 /* Make sure that the last insn in the chain
623 is not something that needs reloading. */
624 emit_note (NULL_PTR, NOTE_INSN_DELETED);
626 /* Enable find_equiv_reg to distinguish insns made by reload. */
627 reload_first_uid = get_max_uid ();
629 #ifdef SECONDARY_MEMORY_NEEDED
630 /* Initialize the secondary memory table. */
631 clear_secondary_mem ();
634 /* We don't have a stack slot for any spill reg yet. */
635 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
636 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
638 /* Initialize the save area information for caller-save, in case some
642 /* Compute which hard registers are now in use
643 as homes for pseudo registers.
644 This is done here rather than (eg) in global_alloc
645 because this point is reached even if not optimizing. */
646 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
649 /* A function that receives a nonlocal goto must save all call-saved
651 if (current_function_has_nonlocal_label)
652 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
654 if (! call_used_regs[i] && ! fixed_regs[i])
655 regs_ever_live[i] = 1;
658 /* Find all the pseudo registers that didn't get hard regs
659 but do have known equivalent constants or memory slots.
660 These include parameters (known equivalent to parameter slots)
661 and cse'd or loop-moved constant memory addresses.
663 Record constant equivalents in reg_equiv_constant
664 so they will be substituted by find_reloads.
665 Record memory equivalents in reg_mem_equiv so they can
666 be substituted eventually by altering the REG-rtx's. */
668 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
672 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
673 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
674 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
675 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
676 pseudo_forbidden_regs
677 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
679 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
681 CLEAR_HARD_REG_SET (bad_spill_regs_global);
683 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
684 Also find all paradoxical subregs and find largest such for each pseudo.
685 On machines with small register classes, record hard registers that
686 are used for user variables. These can never be used for spills.
687 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
688 caller-saved registers must be marked live. */
690 num_eliminable_invariants = 0;
691 for (insn = first; insn; insn = NEXT_INSN (insn))
693 rtx set = single_set (insn);
695 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
696 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
697 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
698 if (! call_used_regs[i])
699 regs_ever_live[i] = 1;
701 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
703 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
705 #ifdef LEGITIMATE_PIC_OPERAND_P
706 && (! function_invariant_p (XEXP (note, 0))
708 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
712 rtx x = XEXP (note, 0);
713 i = REGNO (SET_DEST (set));
714 if (i > LAST_VIRTUAL_REGISTER)
716 if (GET_CODE (x) == MEM)
718 /* If the operand is a PLUS, the MEM may be shared,
719 so make sure we have an unshared copy here. */
720 if (GET_CODE (XEXP (x, 0)) == PLUS)
723 reg_equiv_memory_loc[i] = x;
725 else if (function_invariant_p (x))
727 if (GET_CODE (x) == PLUS)
729 /* This is PLUS of frame pointer and a constant,
730 and might be shared. Unshare it. */
731 reg_equiv_constant[i] = copy_rtx (x);
732 num_eliminable_invariants++;
734 else if (x == frame_pointer_rtx
735 || x == arg_pointer_rtx)
737 reg_equiv_constant[i] = x;
738 num_eliminable_invariants++;
740 else if (LEGITIMATE_CONSTANT_P (x))
741 reg_equiv_constant[i] = x;
743 reg_equiv_memory_loc[i]
744 = force_const_mem (GET_MODE (SET_DEST (set)), x);
749 /* If this register is being made equivalent to a MEM
750 and the MEM is not SET_SRC, the equivalencing insn
751 is one with the MEM as a SET_DEST and it occurs later.
752 So don't mark this insn now. */
753 if (GET_CODE (x) != MEM
754 || rtx_equal_p (SET_SRC (set), x))
756 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
761 /* If this insn is setting a MEM from a register equivalent to it,
762 this is the equivalencing insn. */
763 else if (set && GET_CODE (SET_DEST (set)) == MEM
764 && GET_CODE (SET_SRC (set)) == REG
765 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
766 && rtx_equal_p (SET_DEST (set),
767 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
768 reg_equiv_init[REGNO (SET_SRC (set))]
769 = gen_rtx_INSN_LIST (VOIDmode, insn,
770 reg_equiv_init[REGNO (SET_SRC (set))]);
772 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
773 scan_paradoxical_subregs (PATTERN (insn));
778 num_labels = max_label_num () - get_first_label_num ();
780 /* Allocate the tables used to store offset information at labels. */
781 /* We used to use alloca here, but the size of what it would try to
782 allocate would occasionally cause it to exceed the stack limit and
783 cause a core dump. */
784 real_known_ptr = xmalloc (num_labels);
786 = (int (*)[NUM_ELIMINABLE_REGS])
787 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
789 offsets_known_at = real_known_ptr - get_first_label_num ();
791 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
793 /* Alter each pseudo-reg rtx to contain its hard reg number.
794 Assign stack slots to the pseudos that lack hard regs or equivalents.
795 Do not touch virtual registers. */
797 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
800 /* If we have some registers we think can be eliminated, scan all insns to
801 see if there is an insn that sets one of these registers to something
802 other than itself plus a constant. If so, the register cannot be
803 eliminated. Doing this scan here eliminates an extra pass through the
804 main reload loop in the most common case where register elimination
806 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
807 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
808 || GET_CODE (insn) == CALL_INSN)
809 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
811 maybe_fix_stack_asms ();
813 insns_need_reload = 0;
814 something_needs_elimination = 0;
816 /* Initialize to -1, which means take the first spill register. */
819 /* Spill any hard regs that we know we can't eliminate. */
820 CLEAR_HARD_REG_SET (used_spill_regs);
821 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
822 if (! ep->can_eliminate)
823 spill_hard_reg (ep->from, dumpfile, 1);
825 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
826 if (frame_pointer_needed)
827 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
829 finish_spills (global, dumpfile);
831 /* From now on, we may need to generate moves differently. We may also
832 allow modifications of insns which cause them to not be recognized.
833 Any such modifications will be cleaned up during reload itself. */
834 reload_in_progress = 1;
836 /* This loop scans the entire function each go-round
837 and repeats until one repetition spills no additional hard regs. */
840 int something_changed;
843 HOST_WIDE_INT starting_frame_size;
845 /* Round size of stack frame to stack_alignment_needed. This must be done
846 here because the stack size may be a part of the offset computation
847 for register elimination, and there might have been new stack slots
848 created in the last iteration of this loop. */
849 if (cfun->stack_alignment_needed)
850 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
852 starting_frame_size = get_frame_size ();
854 set_initial_elim_offsets ();
855 set_initial_label_offsets ();
857 /* For each pseudo register that has an equivalent location defined,
858 try to eliminate any eliminable registers (such as the frame pointer)
859 assuming initial offsets for the replacement register, which
862 If the resulting location is directly addressable, substitute
863 the MEM we just got directly for the old REG.
865 If it is not addressable but is a constant or the sum of a hard reg
866 and constant, it is probably not addressable because the constant is
867 out of range, in that case record the address; we will generate
868 hairy code to compute the address in a register each time it is
869 needed. Similarly if it is a hard register, but one that is not
870 valid as an address register.
872 If the location is not addressable, but does not have one of the
873 above forms, assign a stack slot. We have to do this to avoid the
874 potential of producing lots of reloads if, e.g., a location involves
875 a pseudo that didn't get a hard register and has an equivalent memory
876 location that also involves a pseudo that didn't get a hard register.
878 Perhaps at some point we will improve reload_when_needed handling
879 so this problem goes away. But that's very hairy. */
881 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
882 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
884 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
886 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
888 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
889 else if (CONSTANT_P (XEXP (x, 0))
890 || (GET_CODE (XEXP (x, 0)) == REG
891 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
892 || (GET_CODE (XEXP (x, 0)) == PLUS
893 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
894 && (REGNO (XEXP (XEXP (x, 0), 0))
895 < FIRST_PSEUDO_REGISTER)
896 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
897 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
900 /* Make a new stack slot. Then indicate that something
901 changed so we go back and recompute offsets for
902 eliminable registers because the allocation of memory
903 below might change some offset. reg_equiv_{mem,address}
904 will be set up for this pseudo on the next pass around
906 reg_equiv_memory_loc[i] = 0;
907 reg_equiv_init[i] = 0;
912 if (caller_save_needed)
915 /* If we allocated another stack slot, redo elimination bookkeeping. */
916 if (starting_frame_size != get_frame_size ())
919 if (caller_save_needed)
921 save_call_clobbered_regs ();
922 /* That might have allocated new insn_chain structures. */
923 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
926 calculate_needs_all_insns (global);
928 CLEAR_REG_SET (&spilled_pseudos);
931 something_changed = 0;
933 /* If we allocated any new memory locations, make another pass
934 since it might have changed elimination offsets. */
935 if (starting_frame_size != get_frame_size ())
936 something_changed = 1;
939 HARD_REG_SET to_spill;
940 CLEAR_HARD_REG_SET (to_spill);
941 update_eliminables (&to_spill);
942 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
943 if (TEST_HARD_REG_BIT (to_spill, i))
945 spill_hard_reg (i, dumpfile, 1);
948 /* Regardless of the state of spills, if we previously had
949 a register that we thought we could eliminate, but no can
950 not eliminate, we must run another pass.
952 Consider pseudos which have an entry in reg_equiv_* which
953 reference an eliminable register. We must make another pass
954 to update reg_equiv_* so that we do not substitute in the
955 old value from when we thought the elimination could be
957 something_changed = 1;
961 select_reload_regs (dumpfile);
965 if (insns_need_reload != 0 || did_spill)
966 something_changed |= finish_spills (global, dumpfile);
968 if (! something_changed)
971 if (caller_save_needed)
972 delete_caller_save_insns ();
974 obstack_free (&reload_obstack, reload_firstobj);
977 /* If global-alloc was run, notify it of any register eliminations we have
980 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
981 if (ep->can_eliminate)
982 mark_elimination (ep->from, ep->to);
984 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
985 If that insn didn't set the register (i.e., it copied the register to
986 memory), just delete that insn instead of the equivalencing insn plus
987 anything now dead. If we call delete_dead_insn on that insn, we may
988 delete the insn that actually sets the register if the register dies
989 there and that is incorrect. */
991 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
993 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
996 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
998 rtx equiv_insn = XEXP (list, 0);
999 if (GET_CODE (equiv_insn) == NOTE)
1001 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1002 delete_dead_insn (equiv_insn);
1005 PUT_CODE (equiv_insn, NOTE);
1006 NOTE_SOURCE_FILE (equiv_insn) = 0;
1007 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1013 /* Use the reload registers where necessary
1014 by generating move instructions to move the must-be-register
1015 values into or out of the reload registers. */
1017 if (insns_need_reload != 0 || something_needs_elimination
1018 || something_needs_operands_changed)
1020 int old_frame_size = get_frame_size ();
1022 reload_as_needed (global);
1024 if (old_frame_size != get_frame_size ())
1028 verify_initial_elim_offsets ();
1031 /* If we were able to eliminate the frame pointer, show that it is no
1032 longer live at the start of any basic block. If it ls live by
1033 virtue of being in a pseudo, that pseudo will be marked live
1034 and hence the frame pointer will be known to be live via that
1037 if (! frame_pointer_needed)
1038 for (i = 0; i < n_basic_blocks; i++)
1039 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1040 HARD_FRAME_POINTER_REGNUM);
1042 /* Come here (with failure set nonzero) if we can't get enough spill regs
1043 and we decide not to abort about it. */
1046 CLEAR_REG_SET (&spilled_pseudos);
1047 reload_in_progress = 0;
1049 /* Now eliminate all pseudo regs by modifying them into
1050 their equivalent memory references.
1051 The REG-rtx's for the pseudos are modified in place,
1052 so all insns that used to refer to them now refer to memory.
1054 For a reg that has a reg_equiv_address, all those insns
1055 were changed by reloading so that no insns refer to it any longer;
1056 but the DECL_RTL of a variable decl may refer to it,
1057 and if so this causes the debugging info to mention the variable. */
1059 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1064 int is_readonly = 0;
1066 if (reg_equiv_memory_loc[i])
1068 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1069 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1070 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1073 if (reg_equiv_mem[i])
1074 addr = XEXP (reg_equiv_mem[i], 0);
1076 if (reg_equiv_address[i])
1077 addr = reg_equiv_address[i];
1081 if (reg_renumber[i] < 0)
1083 rtx reg = regno_reg_rtx[i];
1084 PUT_CODE (reg, MEM);
1085 XEXP (reg, 0) = addr;
1086 REG_USERVAR_P (reg) = 0;
1087 RTX_UNCHANGING_P (reg) = is_readonly;
1088 MEM_IN_STRUCT_P (reg) = in_struct;
1089 MEM_SCALAR_P (reg) = is_scalar;
1090 /* We have no alias information about this newly created
1092 MEM_ALIAS_SET (reg) = 0;
1094 else if (reg_equiv_mem[i])
1095 XEXP (reg_equiv_mem[i], 0) = addr;
1099 /* We must set reload_completed now since the cleanup_subreg_operands call
1100 below will re-recognize each insn and reload may have generated insns
1101 which are only valid during and after reload. */
1102 reload_completed = 1;
1104 /* Make a pass over all the insns and delete all USEs which we inserted
1105 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1106 notes. Delete all CLOBBER insns that don't refer to the return value
1107 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1108 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1109 and regenerate REG_INC notes that may have been moved around. */
1111 for (insn = first; insn; insn = NEXT_INSN (insn))
1112 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1116 if ((GET_CODE (PATTERN (insn)) == USE
1117 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1118 || (GET_CODE (PATTERN (insn)) == CLOBBER
1119 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1120 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1122 PUT_CODE (insn, NOTE);
1123 NOTE_SOURCE_FILE (insn) = 0;
1124 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1128 pnote = ®_NOTES (insn);
1131 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1132 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1133 || REG_NOTE_KIND (*pnote) == REG_INC
1134 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1135 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1136 *pnote = XEXP (*pnote, 1);
1138 pnote = &XEXP (*pnote, 1);
1142 add_auto_inc_notes (insn, PATTERN (insn));
1145 /* And simplify (subreg (reg)) if it appears as an operand. */
1146 cleanup_subreg_operands (insn);
1149 /* If we are doing stack checking, give a warning if this function's
1150 frame size is larger than we expect. */
1151 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1153 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1154 static int verbose_warned = 0;
1156 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1157 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1158 size += UNITS_PER_WORD;
1160 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1162 warning ("frame size too large for reliable stack checking");
1163 if (! verbose_warned)
1165 warning ("try reducing the number of local variables");
1171 /* Indicate that we no longer have known memory locations or constants. */
1172 if (reg_equiv_constant)
1173 free (reg_equiv_constant);
1174 reg_equiv_constant = 0;
1175 if (reg_equiv_memory_loc)
1176 free (reg_equiv_memory_loc);
1177 reg_equiv_memory_loc = 0;
1180 free (real_known_ptr);
1184 free (reg_equiv_mem);
1185 free (reg_equiv_init);
1186 free (reg_equiv_address);
1187 free (reg_max_ref_width);
1188 free (reg_old_renumber);
1189 free (pseudo_previous_regs);
1190 free (pseudo_forbidden_regs);
1192 CLEAR_HARD_REG_SET (used_spill_regs);
1193 for (i = 0; i < n_spills; i++)
1194 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1196 /* Free all the insn_chain structures at once. */
1197 obstack_free (&reload_obstack, reload_startobj);
1198 unused_insn_chains = 0;
1203 /* Yet another special case. Unfortunately, reg-stack forces people to
1204 write incorrect clobbers in asm statements. These clobbers must not
1205 cause the register to appear in bad_spill_regs, otherwise we'll call
1206 fatal_insn later. We clear the corresponding regnos in the live
1207 register sets to avoid this.
1208 The whole thing is rather sick, I'm afraid. */
1210 maybe_fix_stack_asms ()
1213 const char *constraints[MAX_RECOG_OPERANDS];
1214 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1215 struct insn_chain *chain;
1217 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1220 HARD_REG_SET clobbered, allowed;
1223 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1224 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1226 pat = PATTERN (chain->insn);
1227 if (GET_CODE (pat) != PARALLEL)
1230 CLEAR_HARD_REG_SET (clobbered);
1231 CLEAR_HARD_REG_SET (allowed);
1233 /* First, make a mask of all stack regs that are clobbered. */
1234 for (i = 0; i < XVECLEN (pat, 0); i++)
1236 rtx t = XVECEXP (pat, 0, i);
1237 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1238 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1241 /* Get the operand values and constraints out of the insn. */
1242 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1243 constraints, operand_mode);
1245 /* For every operand, see what registers are allowed. */
1246 for (i = 0; i < noperands; i++)
1248 const char *p = constraints[i];
1249 /* For every alternative, we compute the class of registers allowed
1250 for reloading in CLS, and merge its contents into the reg set
1252 int cls = (int) NO_REGS;
1258 if (c == '\0' || c == ',' || c == '#')
1260 /* End of one alternative - mark the regs in the current
1261 class, and reset the class. */
1262 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1267 } while (c != '\0' && c != ',');
1275 case '=': case '+': case '*': case '%': case '?': case '!':
1276 case '0': case '1': case '2': case '3': case '4': case 'm':
1277 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1278 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1279 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1281 #ifdef EXTRA_CONSTRAINT
1282 case 'Q': case 'R': case 'S': case 'T': case 'U':
1287 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1292 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1296 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1301 /* Those of the registers which are clobbered, but allowed by the
1302 constraints, must be usable as reload registers. So clear them
1303 out of the life information. */
1304 AND_HARD_REG_SET (allowed, clobbered);
1305 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1306 if (TEST_HARD_REG_BIT (allowed, i))
1308 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1309 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1316 /* Copy the global variables n_reloads and rld into the corresponding elts
1319 copy_reloads (chain)
1320 struct insn_chain *chain;
1322 chain->n_reloads = n_reloads;
1324 = (struct reload *) obstack_alloc (&reload_obstack,
1325 n_reloads * sizeof (struct reload));
1326 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1327 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1330 /* Walk the chain of insns, and determine for each whether it needs reloads
1331 and/or eliminations. Build the corresponding insns_need_reload list, and
1332 set something_needs_elimination as appropriate. */
1334 calculate_needs_all_insns (global)
1337 struct insn_chain **pprev_reload = &insns_need_reload;
1338 struct insn_chain *chain;
1340 something_needs_elimination = 0;
1342 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1343 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1345 rtx insn = chain->insn;
1347 /* Clear out the shortcuts. */
1348 chain->n_reloads = 0;
1349 chain->need_elim = 0;
1350 chain->need_reload = 0;
1351 chain->need_operand_change = 0;
1353 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1354 include REG_LABEL), we need to see what effects this has on the
1355 known offsets at labels. */
1357 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1358 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1359 && REG_NOTES (insn) != 0))
1360 set_label_offsets (insn, insn, 0);
1362 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1364 rtx old_body = PATTERN (insn);
1365 int old_code = INSN_CODE (insn);
1366 rtx old_notes = REG_NOTES (insn);
1367 int did_elimination = 0;
1368 int operands_changed = 0;
1369 rtx set = single_set (insn);
1371 /* Skip insns that only set an equivalence. */
1372 if (set && GET_CODE (SET_DEST (set)) == REG
1373 && reg_renumber[REGNO (SET_DEST (set))] < 0
1374 && reg_equiv_constant[REGNO (SET_DEST (set))])
1377 /* If needed, eliminate any eliminable registers. */
1378 if (num_eliminable || num_eliminable_invariants)
1379 did_elimination = eliminate_regs_in_insn (insn, 0);
1381 /* Analyze the instruction. */
1382 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1383 global, spill_reg_order);
1385 /* If a no-op set needs more than one reload, this is likely
1386 to be something that needs input address reloads. We
1387 can't get rid of this cleanly later, and it is of no use
1388 anyway, so discard it now.
1389 We only do this when expensive_optimizations is enabled,
1390 since this complements reload inheritance / output
1391 reload deletion, and it can make debugging harder. */
1392 if (flag_expensive_optimizations && n_reloads > 1)
1394 rtx set = single_set (insn);
1396 && SET_SRC (set) == SET_DEST (set)
1397 && GET_CODE (SET_SRC (set)) == REG
1398 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1400 PUT_CODE (insn, NOTE);
1401 NOTE_SOURCE_FILE (insn) = 0;
1402 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1407 update_eliminable_offsets ();
1409 /* Remember for later shortcuts which insns had any reloads or
1410 register eliminations. */
1411 chain->need_elim = did_elimination;
1412 chain->need_reload = n_reloads > 0;
1413 chain->need_operand_change = operands_changed;
1415 /* Discard any register replacements done. */
1416 if (did_elimination)
1418 obstack_free (&reload_obstack, reload_insn_firstobj);
1419 PATTERN (insn) = old_body;
1420 INSN_CODE (insn) = old_code;
1421 REG_NOTES (insn) = old_notes;
1422 something_needs_elimination = 1;
1425 something_needs_operands_changed |= operands_changed;
1429 copy_reloads (chain);
1430 *pprev_reload = chain;
1431 pprev_reload = &chain->next_need_reload;
1438 /* Comparison function for qsort to decide which of two reloads
1439 should be handled first. *P1 and *P2 are the reload numbers. */
1442 reload_reg_class_lower (r1p, r2p)
1446 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
1449 /* Consider required reloads before optional ones. */
1450 t = rld[r1].optional - rld[r2].optional;
1454 /* Count all solitary classes before non-solitary ones. */
1455 t = ((reg_class_size[(int) rld[r2].class] == 1)
1456 - (reg_class_size[(int) rld[r1].class] == 1));
1460 /* Aside from solitaires, consider all multi-reg groups first. */
1461 t = rld[r2].nregs - rld[r1].nregs;
1465 /* Consider reloads in order of increasing reg-class number. */
1466 t = (int) rld[r1].class - (int) rld[r2].class;
1470 /* If reloads are equally urgent, sort by reload number,
1471 so that the results of qsort leave nothing to chance. */
1475 /* The cost of spilling each hard reg. */
1476 static int spill_cost[FIRST_PSEUDO_REGISTER];
1478 /* When spilling multiple hard registers, we use SPILL_COST for the first
1479 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1480 only the first hard reg for a multi-reg pseudo. */
1481 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1483 /* Update the spill cost arrays, considering that pseudo REG is live. */
1488 int n_refs = REG_N_REFS (reg);
1489 int r = reg_renumber[reg];
1492 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1493 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1496 SET_REGNO_REG_SET (&pseudos_counted, reg);
1501 spill_add_cost[r] += n_refs;
1503 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1505 spill_cost[r + nregs] += n_refs;
1508 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1509 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1511 order_regs_for_reload (chain)
1512 struct insn_chain *chain;
1516 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
1518 memset (spill_cost, 0, sizeof spill_cost);
1519 memset (spill_add_cost, 0, sizeof spill_add_cost);
1521 /* Count number of uses of each hard reg by pseudo regs allocated to it
1522 and then order them by decreasing use. */
1524 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1526 /* Test the various reasons why we can't use a register for
1527 spilling in this insn. */
1529 || REGNO_REG_SET_P (&chain->live_throughout, i)
1530 || REGNO_REG_SET_P (&chain->dead_or_set, i))
1531 SET_HARD_REG_BIT (bad_spill_regs, i);
1533 /* Now find out which pseudos are allocated to it, and update
1535 CLEAR_REG_SET (&pseudos_counted);
1537 EXECUTE_IF_SET_IN_REG_SET
1538 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1542 EXECUTE_IF_SET_IN_REG_SET
1543 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1547 CLEAR_REG_SET (&pseudos_counted);
1550 /* Vector of reload-numbers showing the order in which the reloads should
1552 static short reload_order[MAX_RELOADS];
1554 /* This is used to keep track of the spill regs used in one insn. */
1555 static HARD_REG_SET used_spill_regs_local;
1557 /* We decided to spill hard register SPILLED, which has a size of
1558 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1559 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1560 update SPILL_COST/SPILL_ADD_COST. */
1562 count_spilled_pseudo (spilled, spilled_nregs, reg)
1563 int spilled, spilled_nregs, reg;
1565 int r = reg_renumber[reg];
1566 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1568 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1569 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1572 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1574 spill_add_cost[r] -= REG_N_REFS (reg);
1576 spill_cost[r + nregs] -= REG_N_REFS (reg);
1579 /* Find reload register to use for reload number ORDER. */
1582 find_reg (chain, order, dumpfile)
1583 struct insn_chain *chain;
1587 int rnum = reload_order[order];
1588 struct reload *rl = rld + rnum;
1589 int best_cost = INT_MAX;
1592 HARD_REG_SET not_usable;
1593 HARD_REG_SET used_by_other_reload;
1595 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1596 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1597 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1599 CLEAR_HARD_REG_SET (used_by_other_reload);
1600 for (i = 0; i < order; i++)
1602 int other = reload_order[i];
1603 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1604 for (j = 0; j < rld[other].nregs; j++)
1605 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1608 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1611 if (! TEST_HARD_REG_BIT (not_usable, regno)
1612 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1613 && HARD_REGNO_MODE_OK (regno, rl->mode))
1615 int this_cost = spill_cost[regno];
1617 int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1619 for (j = 1; j < this_nregs; j++)
1621 this_cost += spill_add_cost[regno + j];
1622 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1623 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1628 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1630 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1632 if (this_cost < best_cost
1633 /* Among registers with equal cost, prefer caller-saved ones, or
1634 use REG_ALLOC_ORDER if it is defined. */
1635 || (this_cost == best_cost
1636 #ifdef REG_ALLOC_ORDER
1637 && (inv_reg_alloc_order[regno]
1638 < inv_reg_alloc_order[best_reg])
1640 && call_used_regs[regno]
1641 && ! call_used_regs[best_reg]
1646 best_cost = this_cost;
1653 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1654 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1655 rl->regno = best_reg;
1657 EXECUTE_IF_SET_IN_REG_SET
1658 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1660 count_spilled_pseudo (best_reg, rl->nregs, j);
1662 EXECUTE_IF_SET_IN_REG_SET
1663 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1665 count_spilled_pseudo (best_reg, rl->nregs, j);
1668 for (i = 0; i < rl->nregs; i++)
1670 if (spill_cost[best_reg + i] != 0
1671 || spill_add_cost[best_reg + i] != 0)
1673 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1678 /* Find more reload regs to satisfy the remaining need of an insn, which
1680 Do it by ascending class number, since otherwise a reg
1681 might be spilled for a big class and might fail to count
1682 for a smaller class even though it belongs to that class. */
1685 find_reload_regs (chain, dumpfile)
1686 struct insn_chain *chain;
1691 /* In order to be certain of getting the registers we need,
1692 we must sort the reloads into order of increasing register class.
1693 Then our grabbing of reload registers will parallel the process
1694 that provided the reload registers. */
1695 for (i = 0; i < chain->n_reloads; i++)
1697 /* Show whether this reload already has a hard reg. */
1698 if (chain->rld[i].reg_rtx)
1700 int regno = REGNO (chain->rld[i].reg_rtx);
1701 chain->rld[i].regno = regno;
1702 chain->rld[i].nregs = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1705 chain->rld[i].regno = -1;
1706 reload_order[i] = i;
1709 n_reloads = chain->n_reloads;
1710 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1712 CLEAR_HARD_REG_SET (used_spill_regs_local);
1715 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1717 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1719 /* Compute the order of preference for hard registers to spill. */
1721 order_regs_for_reload (chain);
1723 for (i = 0; i < n_reloads; i++)
1725 int r = reload_order[i];
1727 /* Ignore reloads that got marked inoperative. */
1728 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1729 && ! rld[r].optional
1730 && rld[r].regno == -1)
1731 if (! find_reg (chain, i, dumpfile))
1733 spill_failure (chain->insn, rld[r].class);
1739 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1740 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1742 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1746 select_reload_regs (dumpfile)
1749 struct insn_chain *chain;
1751 /* Try to satisfy the needs for each insn. */
1752 for (chain = insns_need_reload; chain != 0;
1753 chain = chain->next_need_reload)
1754 find_reload_regs (chain, dumpfile);
1757 /* Delete all insns that were inserted by emit_caller_save_insns during
1760 delete_caller_save_insns ()
1762 struct insn_chain *c = reload_insn_chain;
1766 while (c != 0 && c->is_caller_save_insn)
1768 struct insn_chain *next = c->next;
1771 if (insn == BLOCK_HEAD (c->block))
1772 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1773 if (insn == BLOCK_END (c->block))
1774 BLOCK_END (c->block) = PREV_INSN (insn);
1775 if (c == reload_insn_chain)
1776 reload_insn_chain = next;
1778 if (NEXT_INSN (insn) != 0)
1779 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1780 if (PREV_INSN (insn) != 0)
1781 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1784 next->prev = c->prev;
1786 c->prev->next = next;
1787 c->next = unused_insn_chains;
1788 unused_insn_chains = c;
1796 /* Handle the failure to find a register to spill.
1797 INSN should be one of the insns which needed this particular spill reg. */
1800 spill_failure (insn, class)
1802 enum reg_class class;
1804 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1805 if (asm_noperands (PATTERN (insn)) >= 0)
1806 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1807 reg_class_names[class]);
1810 error ("Unable to find a register to spill in class `%s'.",
1811 reg_class_names[class]);
1812 fatal_insn ("This is the insn:", insn);
1816 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1817 data that is dead in INSN. */
1820 delete_dead_insn (insn)
1823 rtx prev = prev_real_insn (insn);
1826 /* If the previous insn sets a register that dies in our insn, delete it
1828 if (prev && GET_CODE (PATTERN (prev)) == SET
1829 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1830 && reg_mentioned_p (prev_dest, PATTERN (insn))
1831 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1832 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1833 delete_dead_insn (prev);
1835 PUT_CODE (insn, NOTE);
1836 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1837 NOTE_SOURCE_FILE (insn) = 0;
1840 /* Modify the home of pseudo-reg I.
1841 The new home is present in reg_renumber[I].
1843 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1844 or it may be -1, meaning there is none or it is not relevant.
1845 This is used so that all pseudos spilled from a given hard reg
1846 can share one stack slot. */
1849 alter_reg (i, from_reg)
1853 /* When outputting an inline function, this can happen
1854 for a reg that isn't actually used. */
1855 if (regno_reg_rtx[i] == 0)
1858 /* If the reg got changed to a MEM at rtl-generation time,
1860 if (GET_CODE (regno_reg_rtx[i]) != REG)
1863 /* Modify the reg-rtx to contain the new hard reg
1864 number or else to contain its pseudo reg number. */
1865 REGNO (regno_reg_rtx[i])
1866 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1868 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1869 allocate a stack slot for it. */
1871 if (reg_renumber[i] < 0
1872 && REG_N_REFS (i) > 0
1873 && reg_equiv_constant[i] == 0
1874 && reg_equiv_memory_loc[i] == 0)
1877 int inherent_size = PSEUDO_REGNO_BYTES (i);
1878 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1881 /* Each pseudo reg has an inherent size which comes from its own mode,
1882 and a total size which provides room for paradoxical subregs
1883 which refer to the pseudo reg in wider modes.
1885 We can use a slot already allocated if it provides both
1886 enough inherent space and enough total space.
1887 Otherwise, we allocate a new slot, making sure that it has no less
1888 inherent space, and no less total space, then the previous slot. */
1891 /* No known place to spill from => no slot to reuse. */
1892 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1893 inherent_size == total_size ? 0 : -1);
1894 if (BYTES_BIG_ENDIAN)
1895 /* Cancel the big-endian correction done in assign_stack_local.
1896 Get the address of the beginning of the slot.
1897 This is so we can do a big-endian correction unconditionally
1899 adjust = inherent_size - total_size;
1901 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1903 /* Reuse a stack slot if possible. */
1904 else if (spill_stack_slot[from_reg] != 0
1905 && spill_stack_slot_width[from_reg] >= total_size
1906 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1908 x = spill_stack_slot[from_reg];
1909 /* Allocate a bigger slot. */
1912 /* Compute maximum size needed, both for inherent size
1913 and for total size. */
1914 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1916 if (spill_stack_slot[from_reg])
1918 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1920 mode = GET_MODE (spill_stack_slot[from_reg]);
1921 if (spill_stack_slot_width[from_reg] > total_size)
1922 total_size = spill_stack_slot_width[from_reg];
1924 /* Make a slot with that size. */
1925 x = assign_stack_local (mode, total_size,
1926 inherent_size == total_size ? 0 : -1);
1928 if (BYTES_BIG_ENDIAN)
1930 /* Cancel the big-endian correction done in assign_stack_local.
1931 Get the address of the beginning of the slot.
1932 This is so we can do a big-endian correction unconditionally
1934 adjust = GET_MODE_SIZE (mode) - total_size;
1936 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1939 plus_constant (XEXP (x, 0), adjust));
1941 spill_stack_slot[from_reg] = stack_slot;
1942 spill_stack_slot_width[from_reg] = total_size;
1945 /* On a big endian machine, the "address" of the slot
1946 is the address of the low part that fits its inherent mode. */
1947 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1948 adjust += (total_size - inherent_size);
1950 /* If we have any adjustment to make, or if the stack slot is the
1951 wrong mode, make a new stack slot. */
1952 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1954 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1955 plus_constant (XEXP (x, 0), adjust));
1957 /* If this was shared among registers, must ensure we never
1958 set it readonly since that can cause scheduling
1959 problems. Note we would only have in this adjustment
1960 case in any event, since the code above doesn't set it. */
1963 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1966 /* Save the stack slot for later. */
1967 reg_equiv_memory_loc[i] = x;
1971 /* Mark the slots in regs_ever_live for the hard regs
1972 used by pseudo-reg number REGNO. */
1975 mark_home_live (regno)
1978 register int i, lim;
1979 i = reg_renumber[regno];
1982 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1984 regs_ever_live[i++] = 1;
1987 /* This function handles the tracking of elimination offsets around branches.
1989 X is a piece of RTL being scanned.
1991 INSN is the insn that it came from, if any.
1993 INITIAL_P is non-zero if we are to set the offset to be the initial
1994 offset and zero if we are setting the offset of the label to be the
1998 set_label_offsets (x, insn, initial_p)
2003 enum rtx_code code = GET_CODE (x);
2006 struct elim_table *p;
2011 if (LABEL_REF_NONLOCAL_P (x))
2016 /* ... fall through ... */
2019 /* If we know nothing about this label, set the desired offsets. Note
2020 that this sets the offset at a label to be the offset before a label
2021 if we don't know anything about the label. This is not correct for
2022 the label after a BARRIER, but is the best guess we can make. If
2023 we guessed wrong, we will suppress an elimination that might have
2024 been possible had we been able to guess correctly. */
2026 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2028 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2029 offsets_at[CODE_LABEL_NUMBER (x)][i]
2030 = (initial_p ? reg_eliminate[i].initial_offset
2031 : reg_eliminate[i].offset);
2032 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2035 /* Otherwise, if this is the definition of a label and it is
2036 preceded by a BARRIER, set our offsets to the known offset of
2040 && (tem = prev_nonnote_insn (insn)) != 0
2041 && GET_CODE (tem) == BARRIER)
2042 set_offsets_for_label (insn);
2044 /* If neither of the above cases is true, compare each offset
2045 with those previously recorded and suppress any eliminations
2046 where the offsets disagree. */
2048 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2049 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2050 != (initial_p ? reg_eliminate[i].initial_offset
2051 : reg_eliminate[i].offset))
2052 reg_eliminate[i].can_eliminate = 0;
2057 set_label_offsets (PATTERN (insn), insn, initial_p);
2059 /* ... fall through ... */
2063 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2064 and hence must have all eliminations at their initial offsets. */
2065 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2066 if (REG_NOTE_KIND (tem) == REG_LABEL)
2067 set_label_offsets (XEXP (tem, 0), insn, 1);
2072 /* Each of the labels in the address vector must be at their initial
2073 offsets. We want the first field for ADDR_VEC and the second
2074 field for ADDR_DIFF_VEC. */
2076 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2077 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2082 /* We only care about setting PC. If the source is not RETURN,
2083 IF_THEN_ELSE, or a label, disable any eliminations not at
2084 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2085 isn't one of those possibilities. For branches to a label,
2086 call ourselves recursively.
2088 Note that this can disable elimination unnecessarily when we have
2089 a non-local goto since it will look like a non-constant jump to
2090 someplace in the current function. This isn't a significant
2091 problem since such jumps will normally be when all elimination
2092 pairs are back to their initial offsets. */
2094 if (SET_DEST (x) != pc_rtx)
2097 switch (GET_CODE (SET_SRC (x)))
2104 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2108 tem = XEXP (SET_SRC (x), 1);
2109 if (GET_CODE (tem) == LABEL_REF)
2110 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2111 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2114 tem = XEXP (SET_SRC (x), 2);
2115 if (GET_CODE (tem) == LABEL_REF)
2116 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2117 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2125 /* If we reach here, all eliminations must be at their initial
2126 offset because we are doing a jump to a variable address. */
2127 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2128 if (p->offset != p->initial_offset)
2129 p->can_eliminate = 0;
2137 /* Scan X and replace any eliminable registers (such as fp) with a
2138 replacement (such as sp), plus an offset.
2140 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2141 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2142 MEM, we are allowed to replace a sum of a register and the constant zero
2143 with the register, which we cannot do outside a MEM. In addition, we need
2144 to record the fact that a register is referenced outside a MEM.
2146 If INSN is an insn, it is the insn containing X. If we replace a REG
2147 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2148 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2149 the REG is being modified.
2151 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2152 That's used when we eliminate in expressions stored in notes.
2153 This means, do not set ref_outside_mem even if the reference
2156 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2157 replacements done assuming all offsets are at their initial values. If
2158 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2159 encounter, return the actual location so that find_reloads will do
2160 the proper thing. */
2163 eliminate_regs (x, mem_mode, insn)
2165 enum machine_mode mem_mode;
2168 enum rtx_code code = GET_CODE (x);
2169 struct elim_table *ep;
2176 if (! current_function_decl)
2195 /* This is only for the benefit of the debugging backends, which call
2196 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2197 removed after CSE. */
2198 new = eliminate_regs (XEXP (x, 0), 0, insn);
2199 if (GET_CODE (new) == MEM)
2200 return XEXP (new, 0);
2206 /* First handle the case where we encounter a bare register that
2207 is eliminable. Replace it with a PLUS. */
2208 if (regno < FIRST_PSEUDO_REGISTER)
2210 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2212 if (ep->from_rtx == x && ep->can_eliminate)
2213 return plus_constant (ep->to_rtx, ep->previous_offset);
2216 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2217 && reg_equiv_constant[regno]
2218 && ! CONSTANT_P (reg_equiv_constant[regno]))
2219 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2223 /* You might think handling MINUS in a manner similar to PLUS is a
2224 good idea. It is not. It has been tried multiple times and every
2225 time the change has had to have been reverted.
2227 Other parts of reload know a PLUS is special (gen_reload for example)
2228 and require special code to handle code a reloaded PLUS operand.
2230 Also consider backends where the flags register is clobbered by a
2231 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2232 lea instruction comes to mind). If we try to reload a MINUS, we
2233 may kill the flags register that was holding a useful value.
2235 So, please before trying to handle MINUS, consider reload as a
2236 whole instead of this little section as well as the backend issues. */
2238 /* If this is the sum of an eliminable register and a constant, rework
2240 if (GET_CODE (XEXP (x, 0)) == REG
2241 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2242 && CONSTANT_P (XEXP (x, 1)))
2244 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2246 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2248 /* The only time we want to replace a PLUS with a REG (this
2249 occurs when the constant operand of the PLUS is the negative
2250 of the offset) is when we are inside a MEM. We won't want
2251 to do so at other times because that would change the
2252 structure of the insn in a way that reload can't handle.
2253 We special-case the commonest situation in
2254 eliminate_regs_in_insn, so just replace a PLUS with a
2255 PLUS here, unless inside a MEM. */
2256 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2257 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2260 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2261 plus_constant (XEXP (x, 1),
2262 ep->previous_offset));
2265 /* If the register is not eliminable, we are done since the other
2266 operand is a constant. */
2270 /* If this is part of an address, we want to bring any constant to the
2271 outermost PLUS. We will do this by doing register replacement in
2272 our operands and seeing if a constant shows up in one of them.
2274 Note that there is no risk of modifying the structure of the insn,
2275 since we only get called for its operands, thus we are either
2276 modifying the address inside a MEM, or something like an address
2277 operand of a load-address insn. */
2280 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2281 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2283 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2285 /* If one side is a PLUS and the other side is a pseudo that
2286 didn't get a hard register but has a reg_equiv_constant,
2287 we must replace the constant here since it may no longer
2288 be in the position of any operand. */
2289 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2290 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2291 && reg_renumber[REGNO (new1)] < 0
2292 && reg_equiv_constant != 0
2293 && reg_equiv_constant[REGNO (new1)] != 0)
2294 new1 = reg_equiv_constant[REGNO (new1)];
2295 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2296 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2297 && reg_renumber[REGNO (new0)] < 0
2298 && reg_equiv_constant[REGNO (new0)] != 0)
2299 new0 = reg_equiv_constant[REGNO (new0)];
2301 new = form_sum (new0, new1);
2303 /* As above, if we are not inside a MEM we do not want to
2304 turn a PLUS into something else. We might try to do so here
2305 for an addition of 0 if we aren't optimizing. */
2306 if (! mem_mode && GET_CODE (new) != PLUS)
2307 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2315 /* If this is the product of an eliminable register and a
2316 constant, apply the distribute law and move the constant out
2317 so that we have (plus (mult ..) ..). This is needed in order
2318 to keep load-address insns valid. This case is pathological.
2319 We ignore the possibility of overflow here. */
2320 if (GET_CODE (XEXP (x, 0)) == REG
2321 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2322 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2323 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2325 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2328 /* Refs inside notes don't count for this purpose. */
2329 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2330 || GET_CODE (insn) == INSN_LIST)))
2331 ep->ref_outside_mem = 1;
2334 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2335 ep->previous_offset * INTVAL (XEXP (x, 1)));
2338 /* ... fall through ... */
2342 /* See comments before PLUS about handling MINUS. */
2344 case DIV: case UDIV:
2345 case MOD: case UMOD:
2346 case AND: case IOR: case XOR:
2347 case ROTATERT: case ROTATE:
2348 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2350 case GE: case GT: case GEU: case GTU:
2351 case LE: case LT: case LEU: case LTU:
2353 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2355 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2357 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2358 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2363 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2366 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2367 if (new != XEXP (x, 0))
2369 /* If this is a REG_DEAD note, it is not valid anymore.
2370 Using the eliminated version could result in creating a
2371 REG_DEAD note for the stack or frame pointer. */
2372 if (GET_MODE (x) == REG_DEAD)
2374 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2377 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2381 /* ... fall through ... */
2384 /* Now do eliminations in the rest of the chain. If this was
2385 an EXPR_LIST, this might result in allocating more memory than is
2386 strictly needed, but it simplifies the code. */
2389 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2390 if (new != XEXP (x, 1))
2391 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2399 case STRICT_LOW_PART:
2401 case SIGN_EXTEND: case ZERO_EXTEND:
2402 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2403 case FLOAT: case FIX:
2404 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2408 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2409 if (new != XEXP (x, 0))
2410 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2414 /* Similar to above processing, but preserve SUBREG_WORD.
2415 Convert (subreg (mem)) to (mem) if not paradoxical.
2416 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2417 pseudo didn't get a hard reg, we must replace this with the
2418 eliminated version of the memory location because push_reloads
2419 may do the replacement in certain circumstances. */
2420 if (GET_CODE (SUBREG_REG (x)) == REG
2421 && (GET_MODE_SIZE (GET_MODE (x))
2422 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2423 && reg_equiv_memory_loc != 0
2424 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2426 new = SUBREG_REG (x);
2429 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2431 if (new != XEXP (x, 0))
2433 int x_size = GET_MODE_SIZE (GET_MODE (x));
2434 int new_size = GET_MODE_SIZE (GET_MODE (new));
2436 if (GET_CODE (new) == MEM
2437 && ((x_size < new_size
2438 #ifdef WORD_REGISTER_OPERATIONS
2439 /* On these machines, combine can create rtl of the form
2440 (set (subreg:m1 (reg:m2 R) 0) ...)
2441 where m1 < m2, and expects something interesting to
2442 happen to the entire word. Moreover, it will use the
2443 (reg:m2 R) later, expecting all bits to be preserved.
2444 So if the number of words is the same, preserve the
2445 subreg so that push_reloads can see it. */
2446 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2449 || (x_size == new_size))
2452 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2453 enum machine_mode mode = GET_MODE (x);
2455 if (BYTES_BIG_ENDIAN)
2456 offset += (MIN (UNITS_PER_WORD,
2457 GET_MODE_SIZE (GET_MODE (new)))
2458 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2460 PUT_MODE (new, mode);
2461 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2465 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2471 /* This is only for the benefit of the debugging backends, which call
2472 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2473 removed after CSE. */
2474 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2475 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2477 /* Our only special processing is to pass the mode of the MEM to our
2478 recursive call and copy the flags. While we are here, handle this
2479 case more efficiently. */
2480 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2481 if (new != XEXP (x, 0))
2483 new = gen_rtx_MEM (GET_MODE (x), new);
2484 new->volatil = x->volatil;
2485 new->unchanging = x->unchanging;
2486 new->in_struct = x->in_struct;
2502 /* Process each of our operands recursively. If any have changed, make a
2504 fmt = GET_RTX_FORMAT (code);
2505 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2509 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2510 if (new != XEXP (x, i) && ! copied)
2512 rtx new_x = rtx_alloc (code);
2513 bcopy ((char *) x, (char *) new_x,
2514 (sizeof (*new_x) - sizeof (new_x->fld)
2515 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2521 else if (*fmt == 'E')
2524 for (j = 0; j < XVECLEN (x, i); j++)
2526 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2527 if (new != XVECEXP (x, i, j) && ! copied_vec)
2529 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2533 rtx new_x = rtx_alloc (code);
2534 bcopy ((char *) x, (char *) new_x,
2535 (sizeof (*new_x) - sizeof (new_x->fld)
2536 + (sizeof (new_x->fld[0])
2537 * GET_RTX_LENGTH (code))));
2541 XVEC (x, i) = new_v;
2544 XVECEXP (x, i, j) = new;
2552 /* Scan rtx X for modifications of elimination target registers. Update
2553 the table of eliminables to reflect the changed state. MEM_MODE is
2554 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2557 elimination_effects (x, mem_mode)
2559 enum machine_mode mem_mode;
2562 enum rtx_code code = GET_CODE (x);
2563 struct elim_table *ep;
2589 /* First handle the case where we encounter a bare register that
2590 is eliminable. Replace it with a PLUS. */
2591 if (regno < FIRST_PSEUDO_REGISTER)
2593 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2595 if (ep->from_rtx == x && ep->can_eliminate)
2598 ep->ref_outside_mem = 1;
2603 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2604 && reg_equiv_constant[regno]
2605 && ! CONSTANT_P (reg_equiv_constant[regno]))
2606 elimination_effects (reg_equiv_constant[regno], mem_mode);
2613 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2614 if (ep->to_rtx == XEXP (x, 0))
2616 int size = GET_MODE_SIZE (mem_mode);
2618 /* If more bytes than MEM_MODE are pushed, account for them. */
2619 #ifdef PUSH_ROUNDING
2620 if (ep->to_rtx == stack_pointer_rtx)
2621 size = PUSH_ROUNDING (size);
2623 if (code == PRE_DEC || code == POST_DEC)
2629 /* Fall through to generic unary operation case. */
2630 case STRICT_LOW_PART:
2632 case SIGN_EXTEND: case ZERO_EXTEND:
2633 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2634 case FLOAT: case FIX:
2635 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2639 elimination_effects (XEXP (x, 0), mem_mode);
2643 if (GET_CODE (SUBREG_REG (x)) == REG
2644 && (GET_MODE_SIZE (GET_MODE (x))
2645 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2646 && reg_equiv_memory_loc != 0
2647 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2650 elimination_effects (SUBREG_REG (x), mem_mode);
2654 /* If using a register that is the source of an eliminate we still
2655 think can be performed, note it cannot be performed since we don't
2656 know how this register is used. */
2657 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2658 if (ep->from_rtx == XEXP (x, 0))
2659 ep->can_eliminate = 0;
2661 elimination_effects (XEXP (x, 0), mem_mode);
2665 /* If clobbering a register that is the replacement register for an
2666 elimination we still think can be performed, note that it cannot
2667 be performed. Otherwise, we need not be concerned about it. */
2668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2669 if (ep->to_rtx == XEXP (x, 0))
2670 ep->can_eliminate = 0;
2672 elimination_effects (XEXP (x, 0), mem_mode);
2676 /* Check for setting a register that we know about. */
2677 if (GET_CODE (SET_DEST (x)) == REG)
2679 /* See if this is setting the replacement register for an
2682 If DEST is the hard frame pointer, we do nothing because we
2683 assume that all assignments to the frame pointer are for
2684 non-local gotos and are being done at a time when they are valid
2685 and do not disturb anything else. Some machines want to
2686 eliminate a fake argument pointer (or even a fake frame pointer)
2687 with either the real frame or the stack pointer. Assignments to
2688 the hard frame pointer must not prevent this elimination. */
2690 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2692 if (ep->to_rtx == SET_DEST (x)
2693 && SET_DEST (x) != hard_frame_pointer_rtx)
2695 /* If it is being incremented, adjust the offset. Otherwise,
2696 this elimination can't be done. */
2697 rtx src = SET_SRC (x);
2699 if (GET_CODE (src) == PLUS
2700 && XEXP (src, 0) == SET_DEST (x)
2701 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2702 ep->offset -= INTVAL (XEXP (src, 1));
2704 ep->can_eliminate = 0;
2708 elimination_effects (SET_DEST (x), 0);
2709 elimination_effects (SET_SRC (x), 0);
2713 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2716 /* Our only special processing is to pass the mode of the MEM to our
2718 elimination_effects (XEXP (x, 0), GET_MODE (x));
2725 fmt = GET_RTX_FORMAT (code);
2726 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2729 elimination_effects (XEXP (x, i), mem_mode);
2730 else if (*fmt == 'E')
2731 for (j = 0; j < XVECLEN (x, i); j++)
2732 elimination_effects (XVECEXP (x, i, j), mem_mode);
2736 /* Descend through rtx X and verify that no references to eliminable registers
2737 remain. If any do remain, mark the involved register as not
2740 check_eliminable_occurrences (x)
2750 code = GET_CODE (x);
2752 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2754 struct elim_table *ep;
2756 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2757 if (ep->from_rtx == x && ep->can_eliminate)
2758 ep->can_eliminate = 0;
2762 fmt = GET_RTX_FORMAT (code);
2763 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2766 check_eliminable_occurrences (XEXP (x, i));
2767 else if (*fmt == 'E')
2770 for (j = 0; j < XVECLEN (x, i); j++)
2771 check_eliminable_occurrences (XVECEXP (x, i, j));
2776 /* Scan INSN and eliminate all eliminable registers in it.
2778 If REPLACE is nonzero, do the replacement destructively. Also
2779 delete the insn as dead it if it is setting an eliminable register.
2781 If REPLACE is zero, do all our allocations in reload_obstack.
2783 If no eliminations were done and this insn doesn't require any elimination
2784 processing (these are not identical conditions: it might be updating sp,
2785 but not referencing fp; this needs to be seen during reload_as_needed so
2786 that the offset between fp and sp can be taken into consideration), zero
2787 is returned. Otherwise, 1 is returned. */
2790 eliminate_regs_in_insn (insn, replace)
2794 int icode = recog_memoized (insn);
2795 rtx old_body = PATTERN (insn);
2796 int insn_is_asm = asm_noperands (old_body) >= 0;
2797 rtx old_set = single_set (insn);
2801 rtx substed_operand[MAX_RECOG_OPERANDS];
2802 rtx orig_operand[MAX_RECOG_OPERANDS];
2803 struct elim_table *ep;
2805 if (! insn_is_asm && icode < 0)
2807 if (GET_CODE (PATTERN (insn)) == USE
2808 || GET_CODE (PATTERN (insn)) == CLOBBER
2809 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2810 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2811 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2817 push_obstacks (&reload_obstack, &reload_obstack);
2819 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2820 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2822 /* Check for setting an eliminable register. */
2823 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2824 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2826 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2827 /* If this is setting the frame pointer register to the
2828 hardware frame pointer register and this is an elimination
2829 that will be done (tested above), this insn is really
2830 adjusting the frame pointer downward to compensate for
2831 the adjustment done before a nonlocal goto. */
2832 if (ep->from == FRAME_POINTER_REGNUM
2833 && ep->to == HARD_FRAME_POINTER_REGNUM)
2835 rtx src = SET_SRC (old_set);
2836 int offset = 0, ok = 0;
2837 rtx prev_insn, prev_set;
2839 if (src == ep->to_rtx)
2841 else if (GET_CODE (src) == PLUS
2842 && GET_CODE (XEXP (src, 0)) == CONST_INT
2843 && XEXP (src, 1) == ep->to_rtx)
2844 offset = INTVAL (XEXP (src, 0)), ok = 1;
2845 else if (GET_CODE (src) == PLUS
2846 && GET_CODE (XEXP (src, 1)) == CONST_INT
2847 && XEXP (src, 0) == ep->to_rtx)
2848 offset = INTVAL (XEXP (src, 1)), ok = 1;
2849 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2850 && (prev_set = single_set (prev_insn)) != 0
2851 && rtx_equal_p (SET_DEST (prev_set), src))
2853 src = SET_SRC (prev_set);
2854 if (src == ep->to_rtx)
2856 else if (GET_CODE (src) == PLUS
2857 && GET_CODE (XEXP (src, 0)) == CONST_INT
2858 && XEXP (src, 1) == ep->to_rtx)
2859 offset = INTVAL (XEXP (src, 0)), ok = 1;
2860 else if (GET_CODE (src) == PLUS
2861 && GET_CODE (XEXP (src, 1)) == CONST_INT
2862 && XEXP (src, 0) == ep->to_rtx)
2863 offset = INTVAL (XEXP (src, 1)), ok = 1;
2871 = plus_constant (ep->to_rtx, offset - ep->offset);
2873 /* First see if this insn remains valid when we
2874 make the change. If not, keep the INSN_CODE
2875 the same and let reload fit it up. */
2876 validate_change (insn, &SET_SRC (old_set), src, 1);
2877 validate_change (insn, &SET_DEST (old_set),
2879 if (! apply_change_group ())
2881 SET_SRC (old_set) = src;
2882 SET_DEST (old_set) = ep->to_rtx;
2892 /* In this case this insn isn't serving a useful purpose. We
2893 will delete it in reload_as_needed once we know that this
2894 elimination is, in fact, being done.
2896 If REPLACE isn't set, we can't delete this insn, but needn't
2897 process it since it won't be used unless something changes. */
2900 delete_dead_insn (insn);
2907 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2908 in the insn is the negative of the offset in FROM. Substitute
2909 (set (reg) (reg to)) for the insn and change its code.
2911 We have to do this here, rather than in eliminate_regs, so that we can
2912 change the insn code. */
2914 if (GET_CODE (SET_SRC (old_set)) == PLUS
2915 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2916 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
2917 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2919 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
2920 && ep->can_eliminate)
2922 /* We must stop at the first elimination that will be used.
2923 If this one would replace the PLUS with a REG, do it
2924 now. Otherwise, quit the loop and let eliminate_regs
2925 do its normal replacement. */
2926 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
2928 /* We assume here that we don't need a PARALLEL of
2929 any CLOBBERs for this assignment. There's not
2930 much we can do if we do need it. */
2931 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2934 INSN_CODE (insn) = -1;
2943 /* Determine the effects of this insn on elimination offsets. */
2944 elimination_effects (old_body, 0);
2946 /* Eliminate all eliminable registers occurring in operands that
2947 can be handled by reload. */
2948 extract_insn (insn);
2950 for (i = 0; i < recog_data.n_operands; i++)
2952 orig_operand[i] = recog_data.operand[i];
2953 substed_operand[i] = recog_data.operand[i];
2955 /* For an asm statement, every operand is eliminable. */
2956 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2958 /* Check for setting a register that we know about. */
2959 if (recog_data.operand_type[i] != OP_IN
2960 && GET_CODE (orig_operand[i]) == REG)
2962 /* If we are assigning to a register that can be eliminated, it
2963 must be as part of a PARALLEL, since the code above handles
2964 single SETs. We must indicate that we can no longer
2965 eliminate this reg. */
2966 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2968 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
2969 ep->can_eliminate = 0;
2972 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
2973 replace ? insn : NULL_RTX);
2974 if (substed_operand[i] != orig_operand[i])
2975 val = any_changes = 1;
2976 /* Terminate the search in check_eliminable_occurrences at
2978 *recog_data.operand_loc[i] = 0;
2980 /* If an output operand changed from a REG to a MEM and INSN is an
2981 insn, write a CLOBBER insn. */
2982 if (recog_data.operand_type[i] != OP_IN
2983 && GET_CODE (orig_operand[i]) == REG
2984 && GET_CODE (substed_operand[i]) == MEM
2986 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
2991 for (i = 0; i < recog_data.n_dups; i++)
2992 *recog_data.dup_loc[i]
2993 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
2995 /* If any eliminable remain, they aren't eliminable anymore. */
2996 check_eliminable_occurrences (old_body);
2998 /* Substitute the operands; the new values are in the substed_operand
3000 for (i = 0; i < recog_data.n_operands; i++)
3001 *recog_data.operand_loc[i] = substed_operand[i];
3002 for (i = 0; i < recog_data.n_dups; i++)
3003 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3005 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3006 re-recognize the insn. We do this in case we had a simple addition
3007 but now can do this as a load-address. This saves an insn in this
3009 If re-recognition fails, the old insn code number will still be used,
3010 and some register operands may have changed into PLUS expressions.
3011 These will be handled by find_reloads by loading them into a register
3016 /* If we aren't replacing things permanently and we changed something,
3017 make another copy to ensure that all the RTL is new. Otherwise
3018 things can go wrong if find_reload swaps commutative operands
3019 and one is inside RTL that has been copied while the other is not. */
3020 new_body = old_body;
3023 new_body = copy_insn (old_body);
3024 if (REG_NOTES (insn))
3025 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3027 PATTERN (insn) = new_body;
3029 /* If we had a move insn but now we don't, rerecognize it. This will
3030 cause spurious re-recognition if the old move had a PARALLEL since
3031 the new one still will, but we can't call single_set without
3032 having put NEW_BODY into the insn and the re-recognition won't
3033 hurt in this rare case. */
3034 /* ??? Why this huge if statement - why don't we just rerecognize the
3038 && ((GET_CODE (SET_SRC (old_set)) == REG
3039 && (GET_CODE (new_body) != SET
3040 || GET_CODE (SET_SRC (new_body)) != REG))
3041 /* If this was a load from or store to memory, compare
3042 the MEM in recog_data.operand to the one in the insn.
3043 If they are not equal, then rerecognize the insn. */
3045 && ((GET_CODE (SET_SRC (old_set)) == MEM
3046 && SET_SRC (old_set) != recog_data.operand[1])
3047 || (GET_CODE (SET_DEST (old_set)) == MEM
3048 && SET_DEST (old_set) != recog_data.operand[0])))
3049 /* If this was an add insn before, rerecognize. */
3050 || GET_CODE (SET_SRC (old_set)) == PLUS))
3052 int new_icode = recog (PATTERN (insn), insn, 0);
3054 INSN_CODE (insn) = icode;
3058 /* Restore the old body. If there were any changes to it, we made a copy
3059 of it while the changes were still in place, so we'll correctly return
3060 a modified insn below. */
3063 /* Restore the old body. */
3064 for (i = 0; i < recog_data.n_operands; i++)
3065 *recog_data.operand_loc[i] = orig_operand[i];
3066 for (i = 0; i < recog_data.n_dups; i++)
3067 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3070 /* Update all elimination pairs to reflect the status after the current
3071 insn. The changes we make were determined by the earlier call to
3072 elimination_effects.
3074 We also detect a cases where register elimination cannot be done,
3075 namely, if a register would be both changed and referenced outside a MEM
3076 in the resulting insn since such an insn is often undefined and, even if
3077 not, we cannot know what meaning will be given to it. Note that it is
3078 valid to have a register used in an address in an insn that changes it
3079 (presumably with a pre- or post-increment or decrement).
3081 If anything changes, return nonzero. */
3083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3085 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3086 ep->can_eliminate = 0;
3088 ep->ref_outside_mem = 0;
3090 if (ep->previous_offset != ep->offset)
3095 /* If we changed something, perform elimination in REG_NOTES. This is
3096 needed even when REPLACE is zero because a REG_DEAD note might refer
3097 to a register that we eliminate and could cause a different number
3098 of spill registers to be needed in the final reload pass than in
3100 if (val && REG_NOTES (insn) != 0)
3101 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3109 /* Loop through all elimination pairs.
3110 Recalculate the number not at initial offset.
3112 Compute the maximum offset (minimum offset if the stack does not
3113 grow downward) for each elimination pair. */
3116 update_eliminable_offsets ()
3118 struct elim_table *ep;
3120 num_not_at_initial_offset = 0;
3121 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3123 ep->previous_offset = ep->offset;
3124 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3125 num_not_at_initial_offset++;
3129 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3130 replacement we currently believe is valid, mark it as not eliminable if X
3131 modifies DEST in any way other than by adding a constant integer to it.
3133 If DEST is the frame pointer, we do nothing because we assume that
3134 all assignments to the hard frame pointer are nonlocal gotos and are being
3135 done at a time when they are valid and do not disturb anything else.
3136 Some machines want to eliminate a fake argument pointer with either the
3137 frame or stack pointer. Assignments to the hard frame pointer must not
3138 prevent this elimination.
3140 Called via note_stores from reload before starting its passes to scan
3141 the insns of the function. */
3144 mark_not_eliminable (dest, x, data)
3147 void *data ATTRIBUTE_UNUSED;
3149 register unsigned int i;
3151 /* A SUBREG of a hard register here is just changing its mode. We should
3152 not see a SUBREG of an eliminable hard register, but check just in
3154 if (GET_CODE (dest) == SUBREG)
3155 dest = SUBREG_REG (dest);
3157 if (dest == hard_frame_pointer_rtx)
3160 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3161 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3162 && (GET_CODE (x) != SET
3163 || GET_CODE (SET_SRC (x)) != PLUS
3164 || XEXP (SET_SRC (x), 0) != dest
3165 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3167 reg_eliminate[i].can_eliminate_previous
3168 = reg_eliminate[i].can_eliminate = 0;
3173 /* Verify that the initial elimination offsets did not change since the
3174 last call to set_initial_elim_offsets. This is used to catch cases
3175 where something illegal happened during reload_as_needed that could
3176 cause incorrect code to be generated if we did not check for it. */
3179 verify_initial_elim_offsets ()
3183 #ifdef ELIMINABLE_REGS
3184 struct elim_table *ep;
3186 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3188 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3189 if (t != ep->initial_offset)
3193 INITIAL_FRAME_POINTER_OFFSET (t);
3194 if (t != reg_eliminate[0].initial_offset)
3199 /* Reset all offsets on eliminable registers to their initial values. */
3201 set_initial_elim_offsets ()
3203 struct elim_table *ep = reg_eliminate;
3205 #ifdef ELIMINABLE_REGS
3206 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3208 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3209 ep->previous_offset = ep->offset = ep->initial_offset;
3212 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3213 ep->previous_offset = ep->offset = ep->initial_offset;
3216 num_not_at_initial_offset = 0;
3219 /* Initialize the known label offsets.
3220 Set a known offset for each forced label to be at the initial offset
3221 of each elimination. We do this because we assume that all
3222 computed jumps occur from a location where each elimination is
3223 at its initial offset.
3224 For all other labels, show that we don't know the offsets. */
3227 set_initial_label_offsets ()
3230 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3232 for (x = forced_labels; x; x = XEXP (x, 1))
3234 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3237 /* Set all elimination offsets to the known values for the code label given
3240 set_offsets_for_label (insn)
3244 int label_nr = CODE_LABEL_NUMBER (insn);
3245 struct elim_table *ep;
3247 num_not_at_initial_offset = 0;
3248 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3250 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3251 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3252 num_not_at_initial_offset++;
3256 /* See if anything that happened changes which eliminations are valid.
3257 For example, on the Sparc, whether or not the frame pointer can
3258 be eliminated can depend on what registers have been used. We need
3259 not check some conditions again (such as flag_omit_frame_pointer)
3260 since they can't have changed. */
3263 update_eliminables (pset)
3266 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3267 int previous_frame_pointer_needed = frame_pointer_needed;
3269 struct elim_table *ep;
3271 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3272 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3273 #ifdef ELIMINABLE_REGS
3274 || ! CAN_ELIMINATE (ep->from, ep->to)
3277 ep->can_eliminate = 0;
3279 /* Look for the case where we have discovered that we can't replace
3280 register A with register B and that means that we will now be
3281 trying to replace register A with register C. This means we can
3282 no longer replace register C with register B and we need to disable
3283 such an elimination, if it exists. This occurs often with A == ap,
3284 B == sp, and C == fp. */
3286 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3288 struct elim_table *op;
3289 register int new_to = -1;
3291 if (! ep->can_eliminate && ep->can_eliminate_previous)
3293 /* Find the current elimination for ep->from, if there is a
3295 for (op = reg_eliminate;
3296 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3297 if (op->from == ep->from && op->can_eliminate)
3303 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3305 for (op = reg_eliminate;
3306 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3307 if (op->from == new_to && op->to == ep->to)
3308 op->can_eliminate = 0;
3312 /* See if any registers that we thought we could eliminate the previous
3313 time are no longer eliminable. If so, something has changed and we
3314 must spill the register. Also, recompute the number of eliminable
3315 registers and see if the frame pointer is needed; it is if there is
3316 no elimination of the frame pointer that we can perform. */
3318 frame_pointer_needed = 1;
3319 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3321 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3322 && ep->to != HARD_FRAME_POINTER_REGNUM)
3323 frame_pointer_needed = 0;
3325 if (! ep->can_eliminate && ep->can_eliminate_previous)
3327 ep->can_eliminate_previous = 0;
3328 SET_HARD_REG_BIT (*pset, ep->from);
3333 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3334 /* If we didn't need a frame pointer last time, but we do now, spill
3335 the hard frame pointer. */
3336 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3337 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3341 /* Initialize the table of registers to eliminate. */
3345 struct elim_table *ep;
3346 #ifdef ELIMINABLE_REGS
3347 struct elim_table_1 *ep1;
3351 reg_eliminate = (struct elim_table *)
3352 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3354 /* Does this function require a frame pointer? */
3356 frame_pointer_needed = (! flag_omit_frame_pointer
3357 #ifdef EXIT_IGNORE_STACK
3358 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3359 and restore sp for alloca. So we can't eliminate
3360 the frame pointer in that case. At some point,
3361 we should improve this by emitting the
3362 sp-adjusting insns for this case. */
3363 || (current_function_calls_alloca
3364 && EXIT_IGNORE_STACK)
3366 || FRAME_POINTER_REQUIRED);
3370 #ifdef ELIMINABLE_REGS
3371 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3372 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3374 ep->from = ep1->from;
3376 ep->can_eliminate = ep->can_eliminate_previous
3377 = (CAN_ELIMINATE (ep->from, ep->to)
3378 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3381 reg_eliminate[0].from = reg_eliminate_1[0].from;
3382 reg_eliminate[0].to = reg_eliminate_1[0].to;
3383 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3384 = ! frame_pointer_needed;
3387 /* Count the number of eliminable registers and build the FROM and TO
3388 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3389 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3390 We depend on this. */
3391 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3393 num_eliminable += ep->can_eliminate;
3394 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3395 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3399 /* Kick all pseudos out of hard register REGNO.
3400 If DUMPFILE is nonzero, log actions taken on that file.
3402 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3403 because we found we can't eliminate some register. In the case, no pseudos
3404 are allowed to be in the register, even if they are only in a block that
3405 doesn't require spill registers, unlike the case when we are spilling this
3406 hard reg to produce another spill register.
3408 Return nonzero if any pseudos needed to be kicked out. */
3411 spill_hard_reg (regno, dumpfile, cant_eliminate)
3413 FILE *dumpfile ATTRIBUTE_UNUSED;
3420 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3421 regs_ever_live[regno] = 1;
3424 /* Spill every pseudo reg that was allocated to this reg
3425 or to something that overlaps this reg. */
3427 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3428 if (reg_renumber[i] >= 0
3429 && reg_renumber[i] <= regno
3431 + HARD_REGNO_NREGS (reg_renumber[i],
3432 PSEUDO_REGNO_MODE (i))
3434 SET_REGNO_REG_SET (&spilled_pseudos, i);
3437 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3438 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3440 ior_hard_reg_set (set1, set2)
3441 HARD_REG_SET *set1, *set2;
3443 IOR_HARD_REG_SET (*set1, *set2);
3446 /* After find_reload_regs has been run for all insn that need reloads,
3447 and/or spill_hard_regs was called, this function is used to actually
3448 spill pseudo registers and try to reallocate them. It also sets up the
3449 spill_regs array for use by choose_reload_regs. */
3452 finish_spills (global, dumpfile)
3456 struct insn_chain *chain;
3457 int something_changed = 0;
3460 /* Build the spill_regs array for the function. */
3461 /* If there are some registers still to eliminate and one of the spill regs
3462 wasn't ever used before, additional stack space may have to be
3463 allocated to store this register. Thus, we may have changed the offset
3464 between the stack and frame pointers, so mark that something has changed.
3466 One might think that we need only set VAL to 1 if this is a call-used
3467 register. However, the set of registers that must be saved by the
3468 prologue is not identical to the call-used set. For example, the
3469 register used by the call insn for the return PC is a call-used register,
3470 but must be saved by the prologue. */
3473 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3474 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3476 spill_reg_order[i] = n_spills;
3477 spill_regs[n_spills++] = i;
3478 if (num_eliminable && ! regs_ever_live[i])
3479 something_changed = 1;
3480 regs_ever_live[i] = 1;
3483 spill_reg_order[i] = -1;
3485 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3486 if (REGNO_REG_SET_P (&spilled_pseudos, i))
3488 /* Record the current hard register the pseudo is allocated to in
3489 pseudo_previous_regs so we avoid reallocating it to the same
3490 hard reg in a later pass. */
3491 if (reg_renumber[i] < 0)
3493 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3494 /* Mark it as no longer having a hard register home. */
3495 reg_renumber[i] = -1;
3496 /* We will need to scan everything again. */
3497 something_changed = 1;
3500 /* Retry global register allocation if possible. */
3503 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3504 /* For every insn that needs reloads, set the registers used as spill
3505 regs in pseudo_forbidden_regs for every pseudo live across the
3507 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3509 EXECUTE_IF_SET_IN_REG_SET
3510 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3512 ior_hard_reg_set (pseudo_forbidden_regs + i,
3513 &chain->used_spill_regs);
3515 EXECUTE_IF_SET_IN_REG_SET
3516 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3518 ior_hard_reg_set (pseudo_forbidden_regs + i,
3519 &chain->used_spill_regs);
3523 /* Retry allocating the spilled pseudos. For each reg, merge the
3524 various reg sets that indicate which hard regs can't be used,
3525 and call retry_global_alloc.
3526 We change spill_pseudos here to only contain pseudos that did not
3527 get a new hard register. */
3528 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3529 if (reg_old_renumber[i] != reg_renumber[i])
3531 HARD_REG_SET forbidden;
3532 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3533 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3534 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3535 retry_global_alloc (i, forbidden);
3536 if (reg_renumber[i] >= 0)
3537 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3541 /* Fix up the register information in the insn chain.
3542 This involves deleting those of the spilled pseudos which did not get
3543 a new hard register home from the live_{before,after} sets. */
3544 for (chain = reload_insn_chain; chain; chain = chain->next)
3546 HARD_REG_SET used_by_pseudos;
3547 HARD_REG_SET used_by_pseudos2;
3549 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3550 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3552 /* Mark any unallocated hard regs as available for spills. That
3553 makes inheritance work somewhat better. */
3554 if (chain->need_reload)
3556 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3557 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3558 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3560 /* Save the old value for the sanity test below. */
3561 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3563 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3564 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3565 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3566 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3568 /* Make sure we only enlarge the set. */
3569 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3575 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3576 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3578 int regno = reg_renumber[i];
3579 if (reg_old_renumber[i] == regno)
3582 alter_reg (i, reg_old_renumber[i]);
3583 reg_old_renumber[i] = regno;
3587 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3589 fprintf (dumpfile, " Register %d now in %d.\n\n",
3590 i, reg_renumber[i]);
3594 return something_changed;
3597 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3598 Also mark any hard registers used to store user variables as
3599 forbidden from being used for spill registers. */
3602 scan_paradoxical_subregs (x)
3606 register const char *fmt;
3607 register enum rtx_code code = GET_CODE (x);
3613 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3614 && REG_USERVAR_P (x))
3615 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3631 if (GET_CODE (SUBREG_REG (x)) == REG
3632 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3633 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3634 = GET_MODE_SIZE (GET_MODE (x));
3641 fmt = GET_RTX_FORMAT (code);
3642 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3645 scan_paradoxical_subregs (XEXP (x, i));
3646 else if (fmt[i] == 'E')
3649 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3650 scan_paradoxical_subregs (XVECEXP (x, i, j));
3655 /* Reload pseudo-registers into hard regs around each insn as needed.
3656 Additional register load insns are output before the insn that needs it
3657 and perhaps store insns after insns that modify the reloaded pseudo reg.
3659 reg_last_reload_reg and reg_reloaded_contents keep track of
3660 which registers are already available in reload registers.
3661 We update these for the reloads that we perform,
3662 as the insns are scanned. */
3665 reload_as_needed (live_known)
3668 struct insn_chain *chain;
3669 #if defined (AUTO_INC_DEC)
3674 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3675 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3676 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3677 reg_has_output_reload = (char *) xmalloc (max_regno);
3678 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3680 set_initial_elim_offsets ();
3682 for (chain = reload_insn_chain; chain; chain = chain->next)
3685 rtx insn = chain->insn;
3686 rtx old_next = NEXT_INSN (insn);
3688 /* If we pass a label, copy the offsets from the label information
3689 into the current offsets of each elimination. */
3690 if (GET_CODE (insn) == CODE_LABEL)
3691 set_offsets_for_label (insn);
3693 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3695 rtx oldpat = PATTERN (insn);
3697 /* If this is a USE and CLOBBER of a MEM, ensure that any
3698 references to eliminable registers have been removed. */
3700 if ((GET_CODE (PATTERN (insn)) == USE
3701 || GET_CODE (PATTERN (insn)) == CLOBBER)
3702 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3703 XEXP (XEXP (PATTERN (insn), 0), 0)
3704 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3705 GET_MODE (XEXP (PATTERN (insn), 0)),
3708 /* If we need to do register elimination processing, do so.
3709 This might delete the insn, in which case we are done. */
3710 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3712 eliminate_regs_in_insn (insn, 1);
3713 if (GET_CODE (insn) == NOTE)
3715 update_eliminable_offsets ();
3720 /* If need_elim is nonzero but need_reload is zero, one might think
3721 that we could simply set n_reloads to 0. However, find_reloads
3722 could have done some manipulation of the insn (such as swapping
3723 commutative operands), and these manipulations are lost during
3724 the first pass for every insn that needs register elimination.
3725 So the actions of find_reloads must be redone here. */
3727 if (! chain->need_elim && ! chain->need_reload
3728 && ! chain->need_operand_change)
3730 /* First find the pseudo regs that must be reloaded for this insn.
3731 This info is returned in the tables reload_... (see reload.h).
3732 Also modify the body of INSN by substituting RELOAD
3733 rtx's for those pseudo regs. */
3736 bzero (reg_has_output_reload, max_regno);
3737 CLEAR_HARD_REG_SET (reg_is_output_reload);
3739 find_reloads (insn, 1, spill_indirect_levels, live_known,
3743 if (num_eliminable && chain->need_elim)
3744 update_eliminable_offsets ();
3748 rtx next = NEXT_INSN (insn);
3751 prev = PREV_INSN (insn);
3753 /* Now compute which reload regs to reload them into. Perhaps
3754 reusing reload regs from previous insns, or else output
3755 load insns to reload them. Maybe output store insns too.
3756 Record the choices of reload reg in reload_reg_rtx. */
3757 choose_reload_regs (chain);
3759 /* Merge any reloads that we didn't combine for fear of
3760 increasing the number of spill registers needed but now
3761 discover can be safely merged. */
3762 if (SMALL_REGISTER_CLASSES)
3763 merge_assigned_reloads (insn);
3765 /* Generate the insns to reload operands into or out of
3766 their reload regs. */
3767 emit_reload_insns (chain);
3769 /* Substitute the chosen reload regs from reload_reg_rtx
3770 into the insn's body (or perhaps into the bodies of other
3771 load and store insn that we just made for reloading
3772 and that we moved the structure into). */
3775 /* If this was an ASM, make sure that all the reload insns
3776 we have generated are valid. If not, give an error
3779 if (asm_noperands (PATTERN (insn)) >= 0)
3780 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3781 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3782 && (recog_memoized (p) < 0
3783 || (extract_insn (p), ! constrain_operands (1))))
3785 error_for_asm (insn,
3786 "`asm' operand requires impossible reload");
3788 NOTE_SOURCE_FILE (p) = 0;
3789 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3792 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3793 is no longer validly lying around to save a future reload.
3794 Note that this does not detect pseudos that were reloaded
3795 for this insn in order to be stored in
3796 (obeying register constraints). That is correct; such reload
3797 registers ARE still valid. */
3798 note_stores (oldpat, forget_old_reloads_1, NULL);
3800 /* There may have been CLOBBER insns placed after INSN. So scan
3801 between INSN and NEXT and use them to forget old reloads. */
3802 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3803 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3804 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3807 /* Likewise for regs altered by auto-increment in this insn.
3808 REG_INC notes have been changed by reloading:
3809 find_reloads_address_1 records substitutions for them,
3810 which have been performed by subst_reloads above. */
3811 for (i = n_reloads - 1; i >= 0; i--)
3813 rtx in_reg = rld[i].in_reg;
3816 enum rtx_code code = GET_CODE (in_reg);
3817 /* PRE_INC / PRE_DEC will have the reload register ending up
3818 with the same value as the stack slot, but that doesn't
3819 hold true for POST_INC / POST_DEC. Either we have to
3820 convert the memory access to a true POST_INC / POST_DEC,
3821 or we can't use the reload register for inheritance. */
3822 if ((code == POST_INC || code == POST_DEC)
3823 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3824 REGNO (rld[i].reg_rtx))
3825 /* Make sure it is the inc/dec pseudo, and not
3826 some other (e.g. output operand) pseudo. */
3827 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3828 == REGNO (XEXP (in_reg, 0))))
3831 rtx reload_reg = rld[i].reg_rtx;
3832 enum machine_mode mode = GET_MODE (reload_reg);
3836 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3838 /* We really want to ignore REG_INC notes here, so
3839 use PATTERN (p) as argument to reg_set_p . */
3840 if (reg_set_p (reload_reg, PATTERN (p)))
3842 n = count_occurrences (PATTERN (p), reload_reg);
3847 n = validate_replace_rtx (reload_reg,
3848 gen_rtx (code, mode,
3852 /* We must also verify that the constraints
3853 are met after the replacement. */
3856 n = constrain_operands (1);
3860 /* If the constraints were not met, then
3861 undo the replacement. */
3864 validate_replace_rtx (gen_rtx (code, mode,
3876 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3878 /* Mark this as having an output reload so that the
3879 REG_INC processing code below won't invalidate
3880 the reload for inheritance. */
3881 SET_HARD_REG_BIT (reg_is_output_reload,
3882 REGNO (reload_reg));
3883 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3886 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3889 else if ((code == PRE_INC || code == PRE_DEC)
3890 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3891 REGNO (rld[i].reg_rtx))
3892 /* Make sure it is the inc/dec pseudo, and not
3893 some other (e.g. output operand) pseudo. */
3894 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3895 == REGNO (XEXP (in_reg, 0))))
3897 SET_HARD_REG_BIT (reg_is_output_reload,
3898 REGNO (rld[i].reg_rtx));
3899 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3903 /* If a pseudo that got a hard register is auto-incremented,
3904 we must purge records of copying it into pseudos without
3906 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3907 if (REG_NOTE_KIND (x) == REG_INC)
3909 /* See if this pseudo reg was reloaded in this insn.
3910 If so, its last-reload info is still valid
3911 because it is based on this insn's reload. */
3912 for (i = 0; i < n_reloads; i++)
3913 if (rld[i].out == XEXP (x, 0))
3917 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3921 /* A reload reg's contents are unknown after a label. */
3922 if (GET_CODE (insn) == CODE_LABEL)
3923 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3925 /* Don't assume a reload reg is still good after a call insn
3926 if it is a call-used reg. */
3927 else if (GET_CODE (insn) == CALL_INSN)
3928 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3932 free (reg_last_reload_reg);
3933 free (reg_has_output_reload);
3936 /* Discard all record of any value reloaded from X,
3937 or reloaded in X from someplace else;
3938 unless X is an output reload reg of the current insn.
3940 X may be a hard reg (the reload reg)
3941 or it may be a pseudo reg that was reloaded from. */
3944 forget_old_reloads_1 (x, ignored, data)
3946 rtx ignored ATTRIBUTE_UNUSED;
3947 void *data ATTRIBUTE_UNUSED;
3953 /* note_stores does give us subregs of hard regs. */
3954 while (GET_CODE (x) == SUBREG)
3956 offset += SUBREG_WORD (x);
3960 if (GET_CODE (x) != REG)
3963 regno = REGNO (x) + offset;
3965 if (regno >= FIRST_PSEUDO_REGISTER)
3970 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3971 /* Storing into a spilled-reg invalidates its contents.
3972 This can happen if a block-local pseudo is allocated to that reg
3973 and it wasn't spilled because this block's total need is 0.
3974 Then some insn might have an optional reload and use this reg. */
3975 for (i = 0; i < nr; i++)
3976 /* But don't do this if the reg actually serves as an output
3977 reload reg in the current instruction. */
3979 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
3980 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
3983 /* Since value of X has changed,
3984 forget any value previously copied from it. */
3987 /* But don't forget a copy if this is the output reload
3988 that establishes the copy's validity. */
3989 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3990 reg_last_reload_reg[regno + nr] = 0;
3993 /* The following HARD_REG_SETs indicate when each hard register is
3994 used for a reload of various parts of the current insn. */
3996 /* If reg is unavailable for all reloads. */
3997 static HARD_REG_SET reload_reg_unavailable;
3998 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3999 static HARD_REG_SET reload_reg_used;
4000 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4001 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4002 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4003 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4004 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4005 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4006 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4007 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4008 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4009 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4010 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4011 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4012 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4013 static HARD_REG_SET reload_reg_used_in_op_addr;
4014 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4015 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4016 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4017 static HARD_REG_SET reload_reg_used_in_insn;
4018 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4019 static HARD_REG_SET reload_reg_used_in_other_addr;
4021 /* If reg is in use as a reload reg for any sort of reload. */
4022 static HARD_REG_SET reload_reg_used_at_all;
4024 /* If reg is use as an inherited reload. We just mark the first register
4026 static HARD_REG_SET reload_reg_used_for_inherit;
4028 /* Records which hard regs are used in any way, either as explicit use or
4029 by being allocated to a pseudo during any point of the current insn. */
4030 static HARD_REG_SET reg_used_in_insn;
4032 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4033 TYPE. MODE is used to indicate how many consecutive regs are
4037 mark_reload_reg_in_use (regno, opnum, type, mode)
4040 enum reload_type type;
4041 enum machine_mode mode;
4043 int nregs = HARD_REGNO_NREGS (regno, mode);
4046 for (i = regno; i < nregs + regno; i++)
4051 SET_HARD_REG_BIT (reload_reg_used, i);
4054 case RELOAD_FOR_INPUT_ADDRESS:
4055 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4058 case RELOAD_FOR_INPADDR_ADDRESS:
4059 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4062 case RELOAD_FOR_OUTPUT_ADDRESS:
4063 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4066 case RELOAD_FOR_OUTADDR_ADDRESS:
4067 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4070 case RELOAD_FOR_OPERAND_ADDRESS:
4071 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4074 case RELOAD_FOR_OPADDR_ADDR:
4075 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4078 case RELOAD_FOR_OTHER_ADDRESS:
4079 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4082 case RELOAD_FOR_INPUT:
4083 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4086 case RELOAD_FOR_OUTPUT:
4087 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4090 case RELOAD_FOR_INSN:
4091 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4095 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4099 /* Similarly, but show REGNO is no longer in use for a reload. */
4102 clear_reload_reg_in_use (regno, opnum, type, mode)
4105 enum reload_type type;
4106 enum machine_mode mode;
4108 int nregs = HARD_REGNO_NREGS (regno, mode);
4109 int start_regno, end_regno;
4111 /* A complication is that for some reload types, inheritance might
4112 allow multiple reloads of the same types to share a reload register.
4113 We set check_opnum if we have to check only reloads with the same
4114 operand number, and check_any if we have to check all reloads. */
4115 int check_opnum = 0;
4117 HARD_REG_SET *used_in_set;
4122 used_in_set = &reload_reg_used;
4125 case RELOAD_FOR_INPUT_ADDRESS:
4126 used_in_set = &reload_reg_used_in_input_addr[opnum];
4129 case RELOAD_FOR_INPADDR_ADDRESS:
4131 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4134 case RELOAD_FOR_OUTPUT_ADDRESS:
4135 used_in_set = &reload_reg_used_in_output_addr[opnum];
4138 case RELOAD_FOR_OUTADDR_ADDRESS:
4140 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4143 case RELOAD_FOR_OPERAND_ADDRESS:
4144 used_in_set = &reload_reg_used_in_op_addr;
4147 case RELOAD_FOR_OPADDR_ADDR:
4149 used_in_set = &reload_reg_used_in_op_addr_reload;
4152 case RELOAD_FOR_OTHER_ADDRESS:
4153 used_in_set = &reload_reg_used_in_other_addr;
4157 case RELOAD_FOR_INPUT:
4158 used_in_set = &reload_reg_used_in_input[opnum];
4161 case RELOAD_FOR_OUTPUT:
4162 used_in_set = &reload_reg_used_in_output[opnum];
4165 case RELOAD_FOR_INSN:
4166 used_in_set = &reload_reg_used_in_insn;
4171 /* We resolve conflicts with remaining reloads of the same type by
4172 excluding the intervals of of reload registers by them from the
4173 interval of freed reload registers. Since we only keep track of
4174 one set of interval bounds, we might have to exclude somewhat
4175 more then what would be necessary if we used a HARD_REG_SET here.
4176 But this should only happen very infrequently, so there should
4177 be no reason to worry about it. */
4179 start_regno = regno;
4180 end_regno = regno + nregs;
4181 if (check_opnum || check_any)
4183 for (i = n_reloads - 1; i >= 0; i--)
4185 if (rld[i].when_needed == type
4186 && (check_any || rld[i].opnum == opnum)
4189 int conflict_start = true_regnum (rld[i].reg_rtx);
4192 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4194 /* If there is an overlap with the first to-be-freed register,
4195 adjust the interval start. */
4196 if (conflict_start <= start_regno && conflict_end > start_regno)
4197 start_regno = conflict_end;
4198 /* Otherwise, if there is a conflict with one of the other
4199 to-be-freed registers, adjust the interval end. */
4200 if (conflict_start > start_regno && conflict_start < end_regno)
4201 end_regno = conflict_start;
4205 for (i = start_regno; i < end_regno; i++)
4206 CLEAR_HARD_REG_BIT (*used_in_set, i);
4209 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4210 specified by OPNUM and TYPE. */
4213 reload_reg_free_p (regno, opnum, type)
4216 enum reload_type type;
4220 /* In use for a RELOAD_OTHER means it's not available for anything. */
4221 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4222 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4228 /* In use for anything means we can't use it for RELOAD_OTHER. */
4229 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4230 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4231 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4234 for (i = 0; i < reload_n_operands; i++)
4235 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4236 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4237 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4238 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4239 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4240 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4245 case RELOAD_FOR_INPUT:
4246 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4247 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4250 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4253 /* If it is used for some other input, can't use it. */
4254 for (i = 0; i < reload_n_operands; i++)
4255 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4258 /* If it is used in a later operand's address, can't use it. */
4259 for (i = opnum + 1; i < reload_n_operands; i++)
4260 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4261 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4266 case RELOAD_FOR_INPUT_ADDRESS:
4267 /* Can't use a register if it is used for an input address for this
4268 operand or used as an input in an earlier one. */
4269 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4270 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4273 for (i = 0; i < opnum; i++)
4274 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4279 case RELOAD_FOR_INPADDR_ADDRESS:
4280 /* Can't use a register if it is used for an input address
4281 for this operand or used as an input in an earlier
4283 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4286 for (i = 0; i < opnum; i++)
4287 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4292 case RELOAD_FOR_OUTPUT_ADDRESS:
4293 /* Can't use a register if it is used for an output address for this
4294 operand or used as an output in this or a later operand. */
4295 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4298 for (i = opnum; i < reload_n_operands; i++)
4299 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4304 case RELOAD_FOR_OUTADDR_ADDRESS:
4305 /* Can't use a register if it is used for an output address
4306 for this operand or used as an output in this or a
4308 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4311 for (i = opnum; i < reload_n_operands; i++)
4312 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4317 case RELOAD_FOR_OPERAND_ADDRESS:
4318 for (i = 0; i < reload_n_operands; i++)
4319 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4322 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4323 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4325 case RELOAD_FOR_OPADDR_ADDR:
4326 for (i = 0; i < reload_n_operands; i++)
4327 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4330 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4332 case RELOAD_FOR_OUTPUT:
4333 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4334 outputs, or an operand address for this or an earlier output. */
4335 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4338 for (i = 0; i < reload_n_operands; i++)
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4342 for (i = 0; i <= opnum; i++)
4343 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4344 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4349 case RELOAD_FOR_INSN:
4350 for (i = 0; i < reload_n_operands; i++)
4351 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4352 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4355 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4356 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4358 case RELOAD_FOR_OTHER_ADDRESS:
4359 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4364 /* Return 1 if the value in reload reg REGNO, as used by a reload
4365 needed for the part of the insn specified by OPNUM and TYPE,
4366 is still available in REGNO at the end of the insn.
4368 We can assume that the reload reg was already tested for availability
4369 at the time it is needed, and we should not check this again,
4370 in case the reg has already been marked in use. */
4373 reload_reg_reaches_end_p (regno, opnum, type)
4376 enum reload_type type;
4383 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4384 its value must reach the end. */
4387 /* If this use is for part of the insn,
4388 its value reaches if no subsequent part uses the same register.
4389 Just like the above function, don't try to do this with lots
4392 case RELOAD_FOR_OTHER_ADDRESS:
4393 /* Here we check for everything else, since these don't conflict
4394 with anything else and everything comes later. */
4396 for (i = 0; i < reload_n_operands; i++)
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4398 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4400 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4401 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4405 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4406 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4407 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4409 case RELOAD_FOR_INPUT_ADDRESS:
4410 case RELOAD_FOR_INPADDR_ADDRESS:
4411 /* Similar, except that we check only for this and subsequent inputs
4412 and the address of only subsequent inputs and we do not need
4413 to check for RELOAD_OTHER objects since they are known not to
4416 for (i = opnum; i < reload_n_operands; i++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4420 for (i = opnum + 1; i < reload_n_operands; i++)
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4422 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4425 for (i = 0; i < reload_n_operands; i++)
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4427 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4428 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4431 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4434 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4435 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4437 case RELOAD_FOR_INPUT:
4438 /* Similar to input address, except we start at the next operand for
4439 both input and input address and we do not check for
4440 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4443 for (i = opnum + 1; i < reload_n_operands; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4446 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4449 /* ... fall through ... */
4451 case RELOAD_FOR_OPERAND_ADDRESS:
4452 /* Check outputs and their addresses. */
4454 for (i = 0; i < reload_n_operands; i++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4456 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4457 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4462 case RELOAD_FOR_OPADDR_ADDR:
4463 for (i = 0; i < reload_n_operands; i++)
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4465 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4469 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4470 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4472 case RELOAD_FOR_INSN:
4473 /* These conflict with other outputs with RELOAD_OTHER. So
4474 we need only check for output addresses. */
4478 /* ... fall through ... */
4480 case RELOAD_FOR_OUTPUT:
4481 case RELOAD_FOR_OUTPUT_ADDRESS:
4482 case RELOAD_FOR_OUTADDR_ADDRESS:
4483 /* We already know these can't conflict with a later output. So the
4484 only thing to check are later output addresses. */
4485 for (i = opnum + 1; i < reload_n_operands; i++)
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4496 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4499 This function uses the same algorithm as reload_reg_free_p above. */
4502 reloads_conflict (r1, r2)
4505 enum reload_type r1_type = rld[r1].when_needed;
4506 enum reload_type r2_type = rld[r2].when_needed;
4507 int r1_opnum = rld[r1].opnum;
4508 int r2_opnum = rld[r2].opnum;
4510 /* RELOAD_OTHER conflicts with everything. */
4511 if (r2_type == RELOAD_OTHER)
4514 /* Otherwise, check conflicts differently for each type. */
4518 case RELOAD_FOR_INPUT:
4519 return (r2_type == RELOAD_FOR_INSN
4520 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4521 || r2_type == RELOAD_FOR_OPADDR_ADDR
4522 || r2_type == RELOAD_FOR_INPUT
4523 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4524 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4525 && r2_opnum > r1_opnum));
4527 case RELOAD_FOR_INPUT_ADDRESS:
4528 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4529 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4531 case RELOAD_FOR_INPADDR_ADDRESS:
4532 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4533 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4535 case RELOAD_FOR_OUTPUT_ADDRESS:
4536 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4537 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4539 case RELOAD_FOR_OUTADDR_ADDRESS:
4540 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4541 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4543 case RELOAD_FOR_OPERAND_ADDRESS:
4544 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4545 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4547 case RELOAD_FOR_OPADDR_ADDR:
4548 return (r2_type == RELOAD_FOR_INPUT
4549 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4551 case RELOAD_FOR_OUTPUT:
4552 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4553 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4554 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4555 && r2_opnum <= r1_opnum));
4557 case RELOAD_FOR_INSN:
4558 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4559 || r2_type == RELOAD_FOR_INSN
4560 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4562 case RELOAD_FOR_OTHER_ADDRESS:
4563 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4573 /* Indexed by reload number, 1 if incoming value
4574 inherited from previous insns. */
4575 char reload_inherited[MAX_RELOADS];
4577 /* For an inherited reload, this is the insn the reload was inherited from,
4578 if we know it. Otherwise, this is 0. */
4579 rtx reload_inheritance_insn[MAX_RELOADS];
4581 /* If non-zero, this is a place to get the value of the reload,
4582 rather than using reload_in. */
4583 rtx reload_override_in[MAX_RELOADS];
4585 /* For each reload, the hard register number of the register used,
4586 or -1 if we did not need a register for this reload. */
4587 int reload_spill_index[MAX_RELOADS];
4589 /* Return 1 if the value in reload reg REGNO, as used by a reload
4590 needed for the part of the insn specified by OPNUM and TYPE,
4591 may be used to load VALUE into it.
4593 Other read-only reloads with the same value do not conflict
4594 unless OUT is non-zero and these other reloads have to live while
4595 output reloads live.
4596 If OUT is CONST0_RTX, this is a special case: it means that the
4597 test should not be for using register REGNO as reload register, but
4598 for copying from register REGNO into the reload register.
4600 RELOADNUM is the number of the reload we want to load this value for;
4601 a reload does not conflict with itself.
4603 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4604 reloads that load an address for the very reload we are considering.
4606 The caller has to make sure that there is no conflict with the return
4609 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4610 ignore_address_reloads)
4613 enum reload_type type;
4616 int ignore_address_reloads;
4619 /* Set if we see an input reload that must not share its reload register
4620 with any new earlyclobber, but might otherwise share the reload
4621 register with an output or input-output reload. */
4622 int check_earlyclobber = 0;
4626 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4629 if (out == const0_rtx)
4635 /* We use some pseudo 'time' value to check if the lifetimes of the
4636 new register use would overlap with the one of a previous reload
4637 that is not read-only or uses a different value.
4638 The 'time' used doesn't have to be linear in any shape or form, just
4640 Some reload types use different 'buckets' for each operand.
4641 So there are MAX_RECOG_OPERANDS different time values for each
4643 We compute TIME1 as the time when the register for the prospective
4644 new reload ceases to be live, and TIME2 for each existing
4645 reload as the time when that the reload register of that reload
4647 Where there is little to be gained by exact lifetime calculations,
4648 we just make conservative assumptions, i.e. a longer lifetime;
4649 this is done in the 'default:' cases. */
4652 case RELOAD_FOR_OTHER_ADDRESS:
4653 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4654 time1 = copy ? 0 : 1;
4657 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4659 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4660 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4661 respectively, to the time values for these, we get distinct time
4662 values. To get distinct time values for each operand, we have to
4663 multiply opnum by at least three. We round that up to four because
4664 multiply by four is often cheaper. */
4665 case RELOAD_FOR_INPADDR_ADDRESS:
4666 time1 = opnum * 4 + 2;
4668 case RELOAD_FOR_INPUT_ADDRESS:
4669 time1 = opnum * 4 + 3;
4671 case RELOAD_FOR_INPUT:
4672 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4673 executes (inclusive). */
4674 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4676 case RELOAD_FOR_OPADDR_ADDR:
4678 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4679 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4681 case RELOAD_FOR_OPERAND_ADDRESS:
4682 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4684 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4686 case RELOAD_FOR_OUTADDR_ADDRESS:
4687 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4689 case RELOAD_FOR_OUTPUT_ADDRESS:
4690 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4693 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4696 for (i = 0; i < n_reloads; i++)
4698 rtx reg = rld[i].reg_rtx;
4699 if (reg && GET_CODE (reg) == REG
4700 && ((unsigned) regno - true_regnum (reg)
4701 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4704 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4705 || rld[i].out || out)
4708 switch (rld[i].when_needed)
4710 case RELOAD_FOR_OTHER_ADDRESS:
4713 case RELOAD_FOR_INPADDR_ADDRESS:
4714 /* find_reloads makes sure that a
4715 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4716 by at most one - the first -
4717 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4718 address reload is inherited, the address address reload
4719 goes away, so we can ignore this conflict. */
4720 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4721 && ignore_address_reloads
4722 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4723 Then the address address is still needed to store
4724 back the new address. */
4725 && ! rld[reloadnum].out)
4727 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4728 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4730 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4731 && ignore_address_reloads
4732 /* Unless we are reloading an auto_inc expression. */
4733 && ! rld[reloadnum].out)
4735 time2 = rld[i].opnum * 4 + 2;
4737 case RELOAD_FOR_INPUT_ADDRESS:
4738 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4739 && ignore_address_reloads
4740 && ! rld[reloadnum].out)
4742 time2 = rld[i].opnum * 4 + 3;
4744 case RELOAD_FOR_INPUT:
4745 time2 = rld[i].opnum * 4 + 4;
4746 check_earlyclobber = 1;
4748 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4749 == MAX_RECOG_OPERAND * 4 */
4750 case RELOAD_FOR_OPADDR_ADDR:
4751 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4752 && ignore_address_reloads
4753 && ! rld[reloadnum].out)
4755 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4757 case RELOAD_FOR_OPERAND_ADDRESS:
4758 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4759 check_earlyclobber = 1;
4761 case RELOAD_FOR_INSN:
4762 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4764 case RELOAD_FOR_OUTPUT:
4765 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4766 instruction is executed. */
4767 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4769 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4770 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4772 case RELOAD_FOR_OUTADDR_ADDRESS:
4773 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4774 && ignore_address_reloads
4775 && ! rld[reloadnum].out)
4777 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4779 case RELOAD_FOR_OUTPUT_ADDRESS:
4780 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4783 /* If there is no conflict in the input part, handle this
4784 like an output reload. */
4785 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4787 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4788 /* Earlyclobbered outputs must conflict with inputs. */
4789 if (earlyclobber_operand_p (rld[i].out))
4790 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4795 /* RELOAD_OTHER might be live beyond instruction execution,
4796 but this is not obvious when we set time2 = 1. So check
4797 here if there might be a problem with the new reload
4798 clobbering the register used by the RELOAD_OTHER. */
4806 && (! rld[i].in || rld[i].out
4807 || ! rtx_equal_p (rld[i].in, value)))
4808 || (out && rld[reloadnum].out_reg
4809 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4815 /* Earlyclobbered outputs must conflict with inputs. */
4816 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4822 /* Give an error message saying we failed to find a reload for INSN,
4823 and clear out reload R. */
4825 failed_reload (insn, r)
4829 if (asm_noperands (PATTERN (insn)) < 0)
4830 /* It's the compiler's fault. */
4831 fatal_insn ("Could not find a spill register", insn);
4833 /* It's the user's fault; the operand's mode and constraint
4834 don't match. Disable this reload so we don't crash in final. */
4835 error_for_asm (insn,
4836 "`asm' operand constraint incompatible with operand size");
4840 rld[r].optional = 1;
4841 rld[r].secondary_p = 1;
4844 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4845 for reload R. If it's valid, get an rtx for it. Return nonzero if
4848 set_reload_reg (i, r)
4852 rtx reg = spill_reg_rtx[i];
4854 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4855 spill_reg_rtx[i] = reg
4856 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4858 regno = true_regnum (reg);
4860 /* Detect when the reload reg can't hold the reload mode.
4861 This used to be one `if', but Sequent compiler can't handle that. */
4862 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4864 enum machine_mode test_mode = VOIDmode;
4866 test_mode = GET_MODE (rld[r].in);
4867 /* If rld[r].in has VOIDmode, it means we will load it
4868 in whatever mode the reload reg has: to wit, rld[r].mode.
4869 We have already tested that for validity. */
4870 /* Aside from that, we need to test that the expressions
4871 to reload from or into have modes which are valid for this
4872 reload register. Otherwise the reload insns would be invalid. */
4873 if (! (rld[r].in != 0 && test_mode != VOIDmode
4874 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4875 if (! (rld[r].out != 0
4876 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4878 /* The reg is OK. */
4881 /* Mark as in use for this insn the reload regs we use
4883 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4884 rld[r].when_needed, rld[r].mode);
4886 rld[r].reg_rtx = reg;
4887 reload_spill_index[r] = spill_regs[i];
4894 /* Find a spill register to use as a reload register for reload R.
4895 LAST_RELOAD is non-zero if this is the last reload for the insn being
4898 Set rld[R].reg_rtx to the register allocated.
4900 We return 1 if successful, or 0 if we couldn't find a spill reg and
4901 we didn't change anything. */
4904 allocate_reload_reg (chain, r, last_reload)
4905 struct insn_chain *chain ATTRIBUTE_UNUSED;
4911 /* If we put this reload ahead, thinking it is a group,
4912 then insist on finding a group. Otherwise we can grab a
4913 reg that some other reload needs.
4914 (That can happen when we have a 68000 DATA_OR_FP_REG
4915 which is a group of data regs or one fp reg.)
4916 We need not be so restrictive if there are no more reloads
4919 ??? Really it would be nicer to have smarter handling
4920 for that kind of reg class, where a problem like this is normal.
4921 Perhaps those classes should be avoided for reloading
4922 by use of more alternatives. */
4924 int force_group = rld[r].nregs > 1 && ! last_reload;
4926 /* If we want a single register and haven't yet found one,
4927 take any reg in the right class and not in use.
4928 If we want a consecutive group, here is where we look for it.
4930 We use two passes so we can first look for reload regs to
4931 reuse, which are already in use for other reloads in this insn,
4932 and only then use additional registers.
4933 I think that maximizing reuse is needed to make sure we don't
4934 run out of reload regs. Suppose we have three reloads, and
4935 reloads A and B can share regs. These need two regs.
4936 Suppose A and B are given different regs.
4937 That leaves none for C. */
4938 for (pass = 0; pass < 2; pass++)
4940 /* I is the index in spill_regs.
4941 We advance it round-robin between insns to use all spill regs
4942 equally, so that inherited reloads have a chance
4943 of leapfrogging each other. */
4947 for (count = 0; count < n_spills; count++)
4949 int class = (int) rld[r].class;
4955 regnum = spill_regs[i];
4957 if ((reload_reg_free_p (regnum, rld[r].opnum,
4960 /* We check reload_reg_used to make sure we
4961 don't clobber the return register. */
4962 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
4963 && reload_reg_free_for_value_p (regnum,
4968 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
4969 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
4970 /* Look first for regs to share, then for unshared. But
4971 don't share regs used for inherited reloads; they are
4972 the ones we want to preserve. */
4974 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4976 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4979 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
4980 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4981 (on 68000) got us two FP regs. If NR is 1,
4982 we would reject both of them. */
4985 /* If we need only one reg, we have already won. */
4988 /* But reject a single reg if we demand a group. */
4993 /* Otherwise check that as many consecutive regs as we need
4994 are available here. */
4997 int regno = regnum + nr - 1;
4998 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4999 && spill_reg_order[regno] >= 0
5000 && reload_reg_free_p (regno, rld[r].opnum,
5001 rld[r].when_needed)))
5010 /* If we found something on pass 1, omit pass 2. */
5011 if (count < n_spills)
5015 /* We should have found a spill register by now. */
5016 if (count >= n_spills)
5019 /* I is the index in SPILL_REG_RTX of the reload register we are to
5020 allocate. Get an rtx for it and find its register number. */
5022 return set_reload_reg (i, r);
5025 /* Initialize all the tables needed to allocate reload registers.
5026 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5027 is the array we use to restore the reg_rtx field for every reload. */
5029 choose_reload_regs_init (chain, save_reload_reg_rtx)
5030 struct insn_chain *chain;
5031 rtx *save_reload_reg_rtx;
5035 for (i = 0; i < n_reloads; i++)
5036 rld[i].reg_rtx = save_reload_reg_rtx[i];
5038 bzero (reload_inherited, MAX_RELOADS);
5039 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5040 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5042 CLEAR_HARD_REG_SET (reload_reg_used);
5043 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5044 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5045 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5046 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5047 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5049 CLEAR_HARD_REG_SET (reg_used_in_insn);
5052 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5053 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5054 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5055 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5056 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5057 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5059 for (i = 0; i < reload_n_operands; i++)
5061 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5062 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5063 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5064 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5065 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5066 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5069 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5071 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5073 for (i = 0; i < n_reloads; i++)
5074 /* If we have already decided to use a certain register,
5075 don't use it in another way. */
5077 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5078 rld[i].when_needed, rld[i].mode);
5081 /* Assign hard reg targets for the pseudo-registers we must reload
5082 into hard regs for this insn.
5083 Also output the instructions to copy them in and out of the hard regs.
5085 For machines with register classes, we are responsible for
5086 finding a reload reg in the proper class. */
5089 choose_reload_regs (chain)
5090 struct insn_chain *chain;
5092 rtx insn = chain->insn;
5094 int max_group_size = 1;
5095 enum reg_class group_class = NO_REGS;
5096 int pass, win, inheritance;
5098 rtx save_reload_reg_rtx[MAX_RELOADS];
5100 /* In order to be certain of getting the registers we need,
5101 we must sort the reloads into order of increasing register class.
5102 Then our grabbing of reload registers will parallel the process
5103 that provided the reload registers.
5105 Also note whether any of the reloads wants a consecutive group of regs.
5106 If so, record the maximum size of the group desired and what
5107 register class contains all the groups needed by this insn. */
5109 for (j = 0; j < n_reloads; j++)
5111 reload_order[j] = j;
5112 reload_spill_index[j] = -1;
5114 if (rld[j].nregs > 1)
5116 max_group_size = MAX (rld[j].nregs, max_group_size);
5117 group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
5120 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5124 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5126 /* If -O, try first with inheritance, then turning it off.
5127 If not -O, don't do inheritance.
5128 Using inheritance when not optimizing leads to paradoxes
5129 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5130 because one side of the comparison might be inherited. */
5132 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5134 choose_reload_regs_init (chain, save_reload_reg_rtx);
5136 /* Process the reloads in order of preference just found.
5137 Beyond this point, subregs can be found in reload_reg_rtx.
5139 This used to look for an existing reloaded home for all
5140 of the reloads, and only then perform any new reloads.
5141 But that could lose if the reloads were done out of reg-class order
5142 because a later reload with a looser constraint might have an old
5143 home in a register needed by an earlier reload with a tighter constraint.
5145 To solve this, we make two passes over the reloads, in the order
5146 described above. In the first pass we try to inherit a reload
5147 from a previous insn. If there is a later reload that needs a
5148 class that is a proper subset of the class being processed, we must
5149 also allocate a spill register during the first pass.
5151 Then make a second pass over the reloads to allocate any reloads
5152 that haven't been given registers yet. */
5154 for (j = 0; j < n_reloads; j++)
5156 register int r = reload_order[j];
5157 rtx search_equiv = NULL_RTX;
5159 /* Ignore reloads that got marked inoperative. */
5160 if (rld[r].out == 0 && rld[r].in == 0
5161 && ! rld[r].secondary_p)
5164 /* If find_reloads chose to use reload_in or reload_out as a reload
5165 register, we don't need to chose one. Otherwise, try even if it
5166 found one since we might save an insn if we find the value lying
5168 Try also when reload_in is a pseudo without a hard reg. */
5169 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5170 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5171 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5172 && GET_CODE (rld[r].in) != MEM
5173 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5176 #if 0 /* No longer needed for correct operation.
5177 It might give better code, or might not; worth an experiment? */
5178 /* If this is an optional reload, we can't inherit from earlier insns
5179 until we are sure that any non-optional reloads have been allocated.
5180 The following code takes advantage of the fact that optional reloads
5181 are at the end of reload_order. */
5182 if (rld[r].optional != 0)
5183 for (i = 0; i < j; i++)
5184 if ((rld[reload_order[i]].out != 0
5185 || rld[reload_order[i]].in != 0
5186 || rld[reload_order[i]].secondary_p)
5187 && ! rld[reload_order[i]].optional
5188 && rld[reload_order[i]].reg_rtx == 0)
5189 allocate_reload_reg (chain, reload_order[i], 0);
5192 /* First see if this pseudo is already available as reloaded
5193 for a previous insn. We cannot try to inherit for reloads
5194 that are smaller than the maximum number of registers needed
5195 for groups unless the register we would allocate cannot be used
5198 We could check here to see if this is a secondary reload for
5199 an object that is already in a register of the desired class.
5200 This would avoid the need for the secondary reload register.
5201 But this is complex because we can't easily determine what
5202 objects might want to be loaded via this reload. So let a
5203 register be allocated here. In `emit_reload_insns' we suppress
5204 one of the loads in the case described above. */
5209 register int regno = -1;
5210 enum machine_mode mode = VOIDmode;
5214 else if (GET_CODE (rld[r].in) == REG)
5216 regno = REGNO (rld[r].in);
5217 mode = GET_MODE (rld[r].in);
5219 else if (GET_CODE (rld[r].in_reg) == REG)
5221 regno = REGNO (rld[r].in_reg);
5222 mode = GET_MODE (rld[r].in_reg);
5224 else if (GET_CODE (rld[r].in_reg) == SUBREG
5225 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5227 word = SUBREG_WORD (rld[r].in_reg);
5228 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5229 if (regno < FIRST_PSEUDO_REGISTER)
5231 mode = GET_MODE (rld[r].in_reg);
5234 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5235 || GET_CODE (rld[r].in_reg) == PRE_DEC
5236 || GET_CODE (rld[r].in_reg) == POST_INC
5237 || GET_CODE (rld[r].in_reg) == POST_DEC)
5238 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5240 regno = REGNO (XEXP (rld[r].in_reg, 0));
5241 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5242 rld[r].out = rld[r].in;
5246 /* This won't work, since REGNO can be a pseudo reg number.
5247 Also, it takes much more hair to keep track of all the things
5248 that can invalidate an inherited reload of part of a pseudoreg. */
5249 else if (GET_CODE (rld[r].in) == SUBREG
5250 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5251 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5254 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5256 enum reg_class class = rld[r].class, last_class;
5257 rtx last_reg = reg_last_reload_reg[regno];
5259 i = REGNO (last_reg) + word;
5260 last_class = REGNO_REG_CLASS (i);
5261 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5262 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5263 && reg_reloaded_contents[i] == regno
5264 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5265 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5266 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5267 /* Even if we can't use this register as a reload
5268 register, we might use it for reload_override_in,
5269 if copying it to the desired class is cheap
5271 || ((REGISTER_MOVE_COST (last_class, class)
5272 < MEMORY_MOVE_COST (mode, class, 1))
5273 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5274 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5278 #ifdef SECONDARY_MEMORY_NEEDED
5279 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5284 && (rld[r].nregs == max_group_size
5285 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5287 && reload_reg_free_for_value_p (i, rld[r].opnum,
5292 /* If a group is needed, verify that all the subsequent
5293 registers still have their values intact. */
5295 = HARD_REGNO_NREGS (i, rld[r].mode);
5298 for (k = 1; k < nr; k++)
5299 if (reg_reloaded_contents[i + k] != regno
5300 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5307 last_reg = (GET_MODE (last_reg) == mode
5308 ? last_reg : gen_rtx_REG (mode, i));
5310 /* We found a register that contains the
5311 value we need. If this register is the
5312 same as an `earlyclobber' operand of the
5313 current insn, just mark it as a place to
5314 reload from since we can't use it as the
5315 reload register itself. */
5317 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5318 if (reg_overlap_mentioned_for_reload_p
5319 (reg_last_reload_reg[regno],
5320 reload_earlyclobbers[i1]))
5323 if (i1 != n_earlyclobbers
5324 || ! (reload_reg_free_for_value_p
5325 (i, rld[r].opnum, rld[r].when_needed,
5326 rld[r].in, rld[r].out, r, 1))
5327 /* Don't use it if we'd clobber a pseudo reg. */
5328 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5330 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5331 /* Don't clobber the frame pointer. */
5332 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5333 /* Don't really use the inherited spill reg
5334 if we need it wider than we've got it. */
5335 || (GET_MODE_SIZE (rld[r].mode)
5336 > GET_MODE_SIZE (mode))
5337 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5340 /* If find_reloads chose reload_out as reload
5341 register, stay with it - that leaves the
5342 inherited register for subsequent reloads. */
5343 || (rld[r].out && rld[r].reg_rtx
5344 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5346 reload_override_in[r] = last_reg;
5347 reload_inheritance_insn[r]
5348 = reg_reloaded_insn[i];
5353 /* We can use this as a reload reg. */
5354 /* Mark the register as in use for this part of
5356 mark_reload_reg_in_use (i,
5360 rld[r].reg_rtx = last_reg;
5361 reload_inherited[r] = 1;
5362 reload_inheritance_insn[r]
5363 = reg_reloaded_insn[i];
5364 reload_spill_index[r] = i;
5365 for (k = 0; k < nr; k++)
5366 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5374 /* Here's another way to see if the value is already lying around. */
5377 && ! reload_inherited[r]
5379 && (CONSTANT_P (rld[r].in)
5380 || GET_CODE (rld[r].in) == PLUS
5381 || GET_CODE (rld[r].in) == REG
5382 || GET_CODE (rld[r].in) == MEM)
5383 && (rld[r].nregs == max_group_size
5384 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5385 search_equiv = rld[r].in;
5386 /* If this is an output reload from a simple move insn, look
5387 if an equivalence for the input is available. */
5388 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5390 rtx set = single_set (insn);
5393 && rtx_equal_p (rld[r].out, SET_DEST (set))
5394 && CONSTANT_P (SET_SRC (set)))
5395 search_equiv = SET_SRC (set);
5401 = find_equiv_reg (search_equiv, insn, rld[r].class,
5402 -1, NULL_PTR, 0, rld[r].mode);
5407 if (GET_CODE (equiv) == REG)
5408 regno = REGNO (equiv);
5409 else if (GET_CODE (equiv) == SUBREG)
5411 /* This must be a SUBREG of a hard register.
5412 Make a new REG since this might be used in an
5413 address and not all machines support SUBREGs
5415 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5416 equiv = gen_rtx_REG (rld[r].mode, regno);
5422 /* If we found a spill reg, reject it unless it is free
5423 and of the desired class. */
5425 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5426 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5430 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5434 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5437 /* We found a register that contains the value we need.
5438 If this register is the same as an `earlyclobber' operand
5439 of the current insn, just mark it as a place to reload from
5440 since we can't use it as the reload register itself. */
5443 for (i = 0; i < n_earlyclobbers; i++)
5444 if (reg_overlap_mentioned_for_reload_p (equiv,
5445 reload_earlyclobbers[i]))
5447 reload_override_in[r] = equiv;
5452 /* If the equiv register we have found is explicitly clobbered
5453 in the current insn, it depends on the reload type if we
5454 can use it, use it for reload_override_in, or not at all.
5455 In particular, we then can't use EQUIV for a
5456 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5458 if (equiv != 0 && regno_clobbered_p (regno, insn))
5460 switch (rld[r].when_needed)
5462 case RELOAD_FOR_OTHER_ADDRESS:
5463 case RELOAD_FOR_INPADDR_ADDRESS:
5464 case RELOAD_FOR_INPUT_ADDRESS:
5465 case RELOAD_FOR_OPADDR_ADDR:
5468 case RELOAD_FOR_INPUT:
5469 case RELOAD_FOR_OPERAND_ADDRESS:
5470 reload_override_in[r] = equiv;
5478 /* If we found an equivalent reg, say no code need be generated
5479 to load it, and use it as our reload reg. */
5480 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5482 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5484 rld[r].reg_rtx = equiv;
5485 reload_inherited[r] = 1;
5487 /* If reg_reloaded_valid is not set for this register,
5488 there might be a stale spill_reg_store lying around.
5489 We must clear it, since otherwise emit_reload_insns
5490 might delete the store. */
5491 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5492 spill_reg_store[regno] = NULL_RTX;
5493 /* If any of the hard registers in EQUIV are spill
5494 registers, mark them as in use for this insn. */
5495 for (k = 0; k < nr; k++)
5497 i = spill_reg_order[regno + k];
5500 mark_reload_reg_in_use (regno, rld[r].opnum,
5503 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5510 /* If we found a register to use already, or if this is an optional
5511 reload, we are done. */
5512 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5515 #if 0 /* No longer needed for correct operation. Might or might not
5516 give better code on the average. Want to experiment? */
5518 /* See if there is a later reload that has a class different from our
5519 class that intersects our class or that requires less register
5520 than our reload. If so, we must allocate a register to this
5521 reload now, since that reload might inherit a previous reload
5522 and take the only available register in our class. Don't do this
5523 for optional reloads since they will force all previous reloads
5524 to be allocated. Also don't do this for reloads that have been
5527 for (i = j + 1; i < n_reloads; i++)
5529 int s = reload_order[i];
5531 if ((rld[s].in == 0 && rld[s].out == 0
5532 && ! rld[s].secondary_p)
5536 if ((rld[s].class != rld[r].class
5537 && reg_classes_intersect_p (rld[r].class,
5539 || rld[s].nregs < rld[r].nregs)
5546 allocate_reload_reg (chain, r, j == n_reloads - 1);
5550 /* Now allocate reload registers for anything non-optional that
5551 didn't get one yet. */
5552 for (j = 0; j < n_reloads; j++)
5554 register int r = reload_order[j];
5556 /* Ignore reloads that got marked inoperative. */
5557 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5560 /* Skip reloads that already have a register allocated or are
5562 if (rld[r].reg_rtx != 0 || rld[r].optional)
5565 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5569 /* If that loop got all the way, we have won. */
5576 /* Loop around and try without any inheritance. */
5581 /* First undo everything done by the failed attempt
5582 to allocate with inheritance. */
5583 choose_reload_regs_init (chain, save_reload_reg_rtx);
5585 /* Some sanity tests to verify that the reloads found in the first
5586 pass are identical to the ones we have now. */
5587 if (chain->n_reloads != n_reloads)
5590 for (i = 0; i < n_reloads; i++)
5592 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5594 if (chain->rld[i].when_needed != rld[i].when_needed)
5596 for (j = 0; j < n_spills; j++)
5597 if (spill_regs[j] == chain->rld[i].regno)
5598 if (! set_reload_reg (j, i))
5599 failed_reload (chain->insn, i);
5603 /* If we thought we could inherit a reload, because it seemed that
5604 nothing else wanted the same reload register earlier in the insn,
5605 verify that assumption, now that all reloads have been assigned.
5606 Likewise for reloads where reload_override_in has been set. */
5608 /* If doing expensive optimizations, do one preliminary pass that doesn't
5609 cancel any inheritance, but removes reloads that have been needed only
5610 for reloads that we know can be inherited. */
5611 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5613 for (j = 0; j < n_reloads; j++)
5615 register int r = reload_order[j];
5617 if (reload_inherited[r] && rld[r].reg_rtx)
5618 check_reg = rld[r].reg_rtx;
5619 else if (reload_override_in[r]
5620 && (GET_CODE (reload_override_in[r]) == REG
5621 || GET_CODE (reload_override_in[r]) == SUBREG))
5622 check_reg = reload_override_in[r];
5625 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5629 (reload_inherited[r]
5630 ? rld[r].out : const0_rtx),
5635 reload_inherited[r] = 0;
5636 reload_override_in[r] = 0;
5638 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5639 reload_override_in, then we do not need its related
5640 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5641 likewise for other reload types.
5642 We handle this by removing a reload when its only replacement
5643 is mentioned in reload_in of the reload we are going to inherit.
5644 A special case are auto_inc expressions; even if the input is
5645 inherited, we still need the address for the output. We can
5646 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5647 If we suceeded removing some reload and we are doing a preliminary
5648 pass just to remove such reloads, make another pass, since the
5649 removal of one reload might allow us to inherit another one. */
5651 && rld[r].out != rld[r].in
5652 && remove_address_replacements (rld[r].in) && pass)
5657 /* Now that reload_override_in is known valid,
5658 actually override reload_in. */
5659 for (j = 0; j < n_reloads; j++)
5660 if (reload_override_in[j])
5661 rld[j].in = reload_override_in[j];
5663 /* If this reload won't be done because it has been cancelled or is
5664 optional and not inherited, clear reload_reg_rtx so other
5665 routines (such as subst_reloads) don't get confused. */
5666 for (j = 0; j < n_reloads; j++)
5667 if (rld[j].reg_rtx != 0
5668 && ((rld[j].optional && ! reload_inherited[j])
5669 || (rld[j].in == 0 && rld[j].out == 0
5670 && ! rld[j].secondary_p)))
5672 int regno = true_regnum (rld[j].reg_rtx);
5674 if (spill_reg_order[regno] >= 0)
5675 clear_reload_reg_in_use (regno, rld[j].opnum,
5676 rld[j].when_needed, rld[j].mode);
5678 reload_spill_index[j] = -1;
5681 /* Record which pseudos and which spill regs have output reloads. */
5682 for (j = 0; j < n_reloads; j++)
5684 register int r = reload_order[j];
5686 i = reload_spill_index[r];
5688 /* I is nonneg if this reload uses a register.
5689 If rld[r].reg_rtx is 0, this is an optional reload
5690 that we opted to ignore. */
5691 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5692 && rld[r].reg_rtx != 0)
5694 register int nregno = REGNO (rld[r].out_reg);
5697 if (nregno < FIRST_PSEUDO_REGISTER)
5698 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5701 reg_has_output_reload[nregno + nr] = 1;
5705 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5707 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5710 if (rld[r].when_needed != RELOAD_OTHER
5711 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5712 && rld[r].when_needed != RELOAD_FOR_INSN)
5718 /* Deallocate the reload register for reload R. This is called from
5719 remove_address_replacements. */
5721 deallocate_reload_reg (r)
5726 if (! rld[r].reg_rtx)
5728 regno = true_regnum (rld[r].reg_rtx);
5730 if (spill_reg_order[regno] >= 0)
5731 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5733 reload_spill_index[r] = -1;
5736 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5737 reloads of the same item for fear that we might not have enough reload
5738 registers. However, normally they will get the same reload register
5739 and hence actually need not be loaded twice.
5741 Here we check for the most common case of this phenomenon: when we have
5742 a number of reloads for the same object, each of which were allocated
5743 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5744 reload, and is not modified in the insn itself. If we find such,
5745 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5746 This will not increase the number of spill registers needed and will
5747 prevent redundant code. */
5750 merge_assigned_reloads (insn)
5755 /* Scan all the reloads looking for ones that only load values and
5756 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5757 assigned and not modified by INSN. */
5759 for (i = 0; i < n_reloads; i++)
5761 int conflicting_input = 0;
5762 int max_input_address_opnum = -1;
5763 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5765 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5766 || rld[i].out != 0 || rld[i].reg_rtx == 0
5767 || reg_set_p (rld[i].reg_rtx, insn))
5770 /* Look at all other reloads. Ensure that the only use of this
5771 reload_reg_rtx is in a reload that just loads the same value
5772 as we do. Note that any secondary reloads must be of the identical
5773 class since the values, modes, and result registers are the
5774 same, so we need not do anything with any secondary reloads. */
5776 for (j = 0; j < n_reloads; j++)
5778 if (i == j || rld[j].reg_rtx == 0
5779 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5783 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5784 && rld[j].opnum > max_input_address_opnum)
5785 max_input_address_opnum = rld[j].opnum;
5787 /* If the reload regs aren't exactly the same (e.g, different modes)
5788 or if the values are different, we can't merge this reload.
5789 But if it is an input reload, we might still merge
5790 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5792 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5793 || rld[j].out != 0 || rld[j].in == 0
5794 || ! rtx_equal_p (rld[i].in, rld[j].in))
5796 if (rld[j].when_needed != RELOAD_FOR_INPUT
5797 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5798 || rld[i].opnum > rld[j].opnum)
5799 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5801 conflicting_input = 1;
5802 if (min_conflicting_input_opnum > rld[j].opnum)
5803 min_conflicting_input_opnum = rld[j].opnum;
5807 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5808 we, in fact, found any matching reloads. */
5811 && max_input_address_opnum <= min_conflicting_input_opnum)
5813 for (j = 0; j < n_reloads; j++)
5814 if (i != j && rld[j].reg_rtx != 0
5815 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5816 && (! conflicting_input
5817 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5818 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5820 rld[i].when_needed = RELOAD_OTHER;
5822 reload_spill_index[j] = -1;
5823 transfer_replacements (i, j);
5826 /* If this is now RELOAD_OTHER, look for any reloads that load
5827 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5828 if they were for inputs, RELOAD_OTHER for outputs. Note that
5829 this test is equivalent to looking for reloads for this operand
5832 if (rld[i].when_needed == RELOAD_OTHER)
5833 for (j = 0; j < n_reloads; j++)
5835 && rld[i].when_needed != RELOAD_OTHER
5836 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5839 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5840 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5841 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5847 /* These arrays are filled by emit_reload_insns and its subroutines. */
5848 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5849 static rtx other_input_address_reload_insns = 0;
5850 static rtx other_input_reload_insns = 0;
5851 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5852 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5853 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5854 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5855 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5856 static rtx operand_reload_insns = 0;
5857 static rtx other_operand_reload_insns = 0;
5858 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5860 /* Values to be put in spill_reg_store are put here first. */
5861 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5862 static HARD_REG_SET reg_reloaded_died;
5864 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5865 has the number J. OLD contains the value to be used as input. */
5867 emit_input_reload_insns (chain, rl, old, j)
5868 struct insn_chain *chain;
5873 rtx insn = chain->insn;
5874 register rtx reloadreg = rl->reg_rtx;
5875 rtx oldequiv_reg = 0;
5878 enum machine_mode mode;
5881 /* Determine the mode to reload in.
5882 This is very tricky because we have three to choose from.
5883 There is the mode the insn operand wants (rl->inmode).
5884 There is the mode of the reload register RELOADREG.
5885 There is the intrinsic mode of the operand, which we could find
5886 by stripping some SUBREGs.
5887 It turns out that RELOADREG's mode is irrelevant:
5888 we can change that arbitrarily.
5890 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5891 then the reload reg may not support QImode moves, so use SImode.
5892 If foo is in memory due to spilling a pseudo reg, this is safe,
5893 because the QImode value is in the least significant part of a
5894 slot big enough for a SImode. If foo is some other sort of
5895 memory reference, then it is impossible to reload this case,
5896 so previous passes had better make sure this never happens.
5898 Then consider a one-word union which has SImode and one of its
5899 members is a float, being fetched as (SUBREG:SF union:SI).
5900 We must fetch that as SFmode because we could be loading into
5901 a float-only register. In this case OLD's mode is correct.
5903 Consider an immediate integer: it has VOIDmode. Here we need
5904 to get a mode from something else.
5906 In some cases, there is a fourth mode, the operand's
5907 containing mode. If the insn specifies a containing mode for
5908 this operand, it overrides all others.
5910 I am not sure whether the algorithm here is always right,
5911 but it does the right things in those cases. */
5913 mode = GET_MODE (old);
5914 if (mode == VOIDmode)
5917 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5918 /* If we need a secondary register for this operation, see if
5919 the value is already in a register in that class. Don't
5920 do this if the secondary register will be used as a scratch
5923 if (rl->secondary_in_reload >= 0
5924 && rl->secondary_in_icode == CODE_FOR_nothing
5927 = find_equiv_reg (old, insn,
5928 rld[rl->secondary_in_reload].class,
5929 -1, NULL_PTR, 0, mode);
5932 /* If reloading from memory, see if there is a register
5933 that already holds the same value. If so, reload from there.
5934 We can pass 0 as the reload_reg_p argument because
5935 any other reload has either already been emitted,
5936 in which case find_equiv_reg will see the reload-insn,
5937 or has yet to be emitted, in which case it doesn't matter
5938 because we will use this equiv reg right away. */
5940 if (oldequiv == 0 && optimize
5941 && (GET_CODE (old) == MEM
5942 || (GET_CODE (old) == REG
5943 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5944 && reg_renumber[REGNO (old)] < 0)))
5945 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5946 -1, NULL_PTR, 0, mode);
5950 int regno = true_regnum (oldequiv);
5952 /* Don't use OLDEQUIV if any other reload changes it at an
5953 earlier stage of this insn or at this stage. */
5954 if (! reload_reg_free_for_value_p (regno, rl->opnum,
5956 rl->in, const0_rtx, j,
5960 /* If it is no cheaper to copy from OLDEQUIV into the
5961 reload register than it would be to move from memory,
5962 don't use it. Likewise, if we need a secondary register
5966 && ((REGNO_REG_CLASS (regno) != rl->class
5967 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5969 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
5970 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5971 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
5975 #ifdef SECONDARY_MEMORY_NEEDED
5976 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
5984 /* delete_output_reload is only invoked properly if old contains
5985 the original pseudo register. Since this is replaced with a
5986 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
5987 find the pseudo in RELOAD_IN_REG. */
5989 && reload_override_in[j]
5990 && GET_CODE (rl->in_reg) == REG)
5997 else if (GET_CODE (oldequiv) == REG)
5998 oldequiv_reg = oldequiv;
5999 else if (GET_CODE (oldequiv) == SUBREG)
6000 oldequiv_reg = SUBREG_REG (oldequiv);
6002 /* If we are reloading from a register that was recently stored in
6003 with an output-reload, see if we can prove there was
6004 actually no need to store the old value in it. */
6006 if (optimize && GET_CODE (oldequiv) == REG
6007 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6008 && spill_reg_store[REGNO (oldequiv)]
6009 && GET_CODE (old) == REG
6010 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6011 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6013 delete_output_reload (insn, j, REGNO (oldequiv));
6015 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6016 then load RELOADREG from OLDEQUIV. Note that we cannot use
6017 gen_lowpart_common since it can do the wrong thing when
6018 RELOADREG has a multi-word mode. Note that RELOADREG
6019 must always be a REG here. */
6021 if (GET_MODE (reloadreg) != mode)
6022 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6023 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6024 oldequiv = SUBREG_REG (oldequiv);
6025 if (GET_MODE (oldequiv) != VOIDmode
6026 && mode != GET_MODE (oldequiv))
6027 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6029 /* Switch to the right place to emit the reload insns. */
6030 switch (rl->when_needed)
6033 where = &other_input_reload_insns;
6035 case RELOAD_FOR_INPUT:
6036 where = &input_reload_insns[rl->opnum];
6038 case RELOAD_FOR_INPUT_ADDRESS:
6039 where = &input_address_reload_insns[rl->opnum];
6041 case RELOAD_FOR_INPADDR_ADDRESS:
6042 where = &inpaddr_address_reload_insns[rl->opnum];
6044 case RELOAD_FOR_OUTPUT_ADDRESS:
6045 where = &output_address_reload_insns[rl->opnum];
6047 case RELOAD_FOR_OUTADDR_ADDRESS:
6048 where = &outaddr_address_reload_insns[rl->opnum];
6050 case RELOAD_FOR_OPERAND_ADDRESS:
6051 where = &operand_reload_insns;
6053 case RELOAD_FOR_OPADDR_ADDR:
6054 where = &other_operand_reload_insns;
6056 case RELOAD_FOR_OTHER_ADDRESS:
6057 where = &other_input_address_reload_insns;
6063 push_to_sequence (*where);
6065 /* Auto-increment addresses must be reloaded in a special way. */
6066 if (rl->out && ! rl->out_reg)
6068 /* We are not going to bother supporting the case where a
6069 incremented register can't be copied directly from
6070 OLDEQUIV since this seems highly unlikely. */
6071 if (rl->secondary_in_reload >= 0)
6074 if (reload_inherited[j])
6075 oldequiv = reloadreg;
6077 old = XEXP (rl->in_reg, 0);
6079 if (optimize && GET_CODE (oldequiv) == REG
6080 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6081 && spill_reg_store[REGNO (oldequiv)]
6082 && GET_CODE (old) == REG
6083 && (dead_or_set_p (insn,
6084 spill_reg_stored_to[REGNO (oldequiv)])
6085 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6087 delete_output_reload (insn, j, REGNO (oldequiv));
6089 /* Prevent normal processing of this reload. */
6091 /* Output a special code sequence for this case. */
6092 new_spill_reg_store[REGNO (reloadreg)]
6093 = inc_for_reload (reloadreg, oldequiv, rl->out,
6097 /* If we are reloading a pseudo-register that was set by the previous
6098 insn, see if we can get rid of that pseudo-register entirely
6099 by redirecting the previous insn into our reload register. */
6101 else if (optimize && GET_CODE (old) == REG
6102 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6103 && dead_or_set_p (insn, old)
6104 /* This is unsafe if some other reload
6105 uses the same reg first. */
6106 && reload_reg_free_for_value_p (REGNO (reloadreg),
6112 rtx temp = PREV_INSN (insn);
6113 while (temp && GET_CODE (temp) == NOTE)
6114 temp = PREV_INSN (temp);
6116 && GET_CODE (temp) == INSN
6117 && GET_CODE (PATTERN (temp)) == SET
6118 && SET_DEST (PATTERN (temp)) == old
6119 /* Make sure we can access insn_operand_constraint. */
6120 && asm_noperands (PATTERN (temp)) < 0
6121 /* This is unsafe if prev insn rejects our reload reg. */
6122 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6124 /* This is unsafe if operand occurs more than once in current
6125 insn. Perhaps some occurrences aren't reloaded. */
6126 && count_occurrences (PATTERN (insn), old) == 1
6127 /* Don't risk splitting a matching pair of operands. */
6128 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6130 /* Store into the reload register instead of the pseudo. */
6131 SET_DEST (PATTERN (temp)) = reloadreg;
6133 /* If the previous insn is an output reload, the source is
6134 a reload register, and its spill_reg_store entry will
6135 contain the previous destination. This is now
6137 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6138 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6140 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6141 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6144 /* If these are the only uses of the pseudo reg,
6145 pretend for GDB it lives in the reload reg we used. */
6146 if (REG_N_DEATHS (REGNO (old)) == 1
6147 && REG_N_SETS (REGNO (old)) == 1)
6149 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6150 alter_reg (REGNO (old), -1);
6156 /* We can't do that, so output an insn to load RELOADREG. */
6158 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6159 /* If we have a secondary reload, pick up the secondary register
6160 and icode, if any. If OLDEQUIV and OLD are different or
6161 if this is an in-out reload, recompute whether or not we
6162 still need a secondary register and what the icode should
6163 be. If we still need a secondary register and the class or
6164 icode is different, go back to reloading from OLD if using
6165 OLDEQUIV means that we got the wrong type of register. We
6166 cannot have different class or icode due to an in-out reload
6167 because we don't make such reloads when both the input and
6168 output need secondary reload registers. */
6170 if (! special && rl->secondary_in_reload >= 0)
6172 rtx second_reload_reg = 0;
6173 int secondary_reload = rl->secondary_in_reload;
6174 rtx real_oldequiv = oldequiv;
6177 enum insn_code icode;
6179 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6180 and similarly for OLD.
6181 See comments in get_secondary_reload in reload.c. */
6182 /* If it is a pseudo that cannot be replaced with its
6183 equivalent MEM, we must fall back to reload_in, which
6184 will have all the necessary substitutions registered.
6185 Likewise for a pseudo that can't be replaced with its
6186 equivalent constant.
6188 Take extra care for subregs of such pseudos. Note that
6189 we cannot use reg_equiv_mem in this case because it is
6190 not in the right mode. */
6193 if (GET_CODE (tmp) == SUBREG)
6194 tmp = SUBREG_REG (tmp);
6195 if (GET_CODE (tmp) == REG
6196 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6197 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6198 || reg_equiv_constant[REGNO (tmp)] != 0))
6200 if (! reg_equiv_mem[REGNO (tmp)]
6201 || num_not_at_initial_offset
6202 || GET_CODE (oldequiv) == SUBREG)
6203 real_oldequiv = rl->in;
6205 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6209 if (GET_CODE (tmp) == SUBREG)
6210 tmp = SUBREG_REG (tmp);
6211 if (GET_CODE (tmp) == REG
6212 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6213 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6214 || reg_equiv_constant[REGNO (tmp)] != 0))
6216 if (! reg_equiv_mem[REGNO (tmp)]
6217 || num_not_at_initial_offset
6218 || GET_CODE (old) == SUBREG)
6221 real_old = reg_equiv_mem[REGNO (tmp)];
6224 second_reload_reg = rld[secondary_reload].reg_rtx;
6225 icode = rl->secondary_in_icode;
6227 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6228 || (rl->in != 0 && rl->out != 0))
6230 enum reg_class new_class
6231 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6232 mode, real_oldequiv);
6234 if (new_class == NO_REGS)
6235 second_reload_reg = 0;
6238 enum insn_code new_icode;
6239 enum machine_mode new_mode;
6241 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6242 REGNO (second_reload_reg)))
6243 oldequiv = old, real_oldequiv = real_old;
6246 new_icode = reload_in_optab[(int) mode];
6247 if (new_icode != CODE_FOR_nothing
6248 && ((insn_data[(int) new_icode].operand[0].predicate
6249 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6251 || (insn_data[(int) new_icode].operand[1].predicate
6252 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6253 (real_oldequiv, mode)))))
6254 new_icode = CODE_FOR_nothing;
6256 if (new_icode == CODE_FOR_nothing)
6259 new_mode = insn_data[(int) new_icode].operand[2].mode;
6261 if (GET_MODE (second_reload_reg) != new_mode)
6263 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6265 oldequiv = old, real_oldequiv = real_old;
6268 = gen_rtx_REG (new_mode,
6269 REGNO (second_reload_reg));
6275 /* If we still need a secondary reload register, check
6276 to see if it is being used as a scratch or intermediate
6277 register and generate code appropriately. If we need
6278 a scratch register, use REAL_OLDEQUIV since the form of
6279 the insn may depend on the actual address if it is
6282 if (second_reload_reg)
6284 if (icode != CODE_FOR_nothing)
6286 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6287 second_reload_reg));
6292 /* See if we need a scratch register to load the
6293 intermediate register (a tertiary reload). */
6294 enum insn_code tertiary_icode
6295 = rld[secondary_reload].secondary_in_icode;
6297 if (tertiary_icode != CODE_FOR_nothing)
6299 rtx third_reload_reg
6300 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6302 emit_insn ((GEN_FCN (tertiary_icode)
6303 (second_reload_reg, real_oldequiv,
6304 third_reload_reg)));
6307 gen_reload (second_reload_reg, real_oldequiv,
6311 oldequiv = second_reload_reg;
6317 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6319 rtx real_oldequiv = oldequiv;
6321 if ((GET_CODE (oldequiv) == REG
6322 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6323 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6324 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6325 || (GET_CODE (oldequiv) == SUBREG
6326 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6327 && (REGNO (SUBREG_REG (oldequiv))
6328 >= FIRST_PSEUDO_REGISTER)
6329 && ((reg_equiv_memory_loc
6330 [REGNO (SUBREG_REG (oldequiv))] != 0)
6331 || (reg_equiv_constant
6332 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6333 real_oldequiv = rl->in;
6334 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6338 /* End this sequence. */
6339 *where = get_insns ();
6342 /* Update reload_override_in so that delete_address_reloads_1
6343 can see the actual register usage. */
6345 reload_override_in[j] = oldequiv;
6348 /* Generate insns to for the output reload RL, which is for the insn described
6349 by CHAIN and has the number J. */
6351 emit_output_reload_insns (chain, rl, j)
6352 struct insn_chain *chain;
6356 rtx reloadreg = rl->reg_rtx;
6357 rtx insn = chain->insn;
6360 enum machine_mode mode = GET_MODE (old);
6363 if (rl->when_needed == RELOAD_OTHER)
6366 push_to_sequence (output_reload_insns[rl->opnum]);
6368 /* Determine the mode to reload in.
6369 See comments above (for input reloading). */
6371 if (mode == VOIDmode)
6373 /* VOIDmode should never happen for an output. */
6374 if (asm_noperands (PATTERN (insn)) < 0)
6375 /* It's the compiler's fault. */
6376 fatal_insn ("VOIDmode on an output", insn);
6377 error_for_asm (insn, "output operand is constant in `asm'");
6378 /* Prevent crash--use something we know is valid. */
6380 old = gen_rtx_REG (mode, REGNO (reloadreg));
6383 if (GET_MODE (reloadreg) != mode)
6384 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6386 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6388 /* If we need two reload regs, set RELOADREG to the intermediate
6389 one, since it will be stored into OLD. We might need a secondary
6390 register only for an input reload, so check again here. */
6392 if (rl->secondary_out_reload >= 0)
6396 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6397 && reg_equiv_mem[REGNO (old)] != 0)
6398 real_old = reg_equiv_mem[REGNO (old)];
6400 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6404 rtx second_reloadreg = reloadreg;
6405 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6407 /* See if RELOADREG is to be used as a scratch register
6408 or as an intermediate register. */
6409 if (rl->secondary_out_icode != CODE_FOR_nothing)
6411 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6412 (real_old, second_reloadreg, reloadreg)));
6417 /* See if we need both a scratch and intermediate reload
6420 int secondary_reload = rl->secondary_out_reload;
6421 enum insn_code tertiary_icode
6422 = rld[secondary_reload].secondary_out_icode;
6424 if (GET_MODE (reloadreg) != mode)
6425 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6427 if (tertiary_icode != CODE_FOR_nothing)
6430 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6433 /* Copy primary reload reg to secondary reload reg.
6434 (Note that these have been swapped above, then
6435 secondary reload reg to OLD using our insn. */
6437 /* If REAL_OLD is a paradoxical SUBREG, remove it
6438 and try to put the opposite SUBREG on
6440 if (GET_CODE (real_old) == SUBREG
6441 && (GET_MODE_SIZE (GET_MODE (real_old))
6442 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6443 && 0 != (tem = gen_lowpart_common
6444 (GET_MODE (SUBREG_REG (real_old)),
6446 real_old = SUBREG_REG (real_old), reloadreg = tem;
6448 gen_reload (reloadreg, second_reloadreg,
6449 rl->opnum, rl->when_needed);
6450 emit_insn ((GEN_FCN (tertiary_icode)
6451 (real_old, reloadreg, third_reloadreg)));
6456 /* Copy between the reload regs here and then to
6459 gen_reload (reloadreg, second_reloadreg,
6460 rl->opnum, rl->when_needed);
6466 /* Output the last reload insn. */
6471 /* Don't output the last reload if OLD is not the dest of
6472 INSN and is in the src and is clobbered by INSN. */
6473 if (! flag_expensive_optimizations
6474 || GET_CODE (old) != REG
6475 || !(set = single_set (insn))
6476 || rtx_equal_p (old, SET_DEST (set))
6477 || !reg_mentioned_p (old, SET_SRC (set))
6478 || !regno_clobbered_p (REGNO (old), insn))
6479 gen_reload (old, reloadreg, rl->opnum,
6483 /* Look at all insns we emitted, just to be safe. */
6484 for (p = get_insns (); p; p = NEXT_INSN (p))
6485 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6487 rtx pat = PATTERN (p);
6489 /* If this output reload doesn't come from a spill reg,
6490 clear any memory of reloaded copies of the pseudo reg.
6491 If this output reload comes from a spill reg,
6492 reg_has_output_reload will make this do nothing. */
6493 note_stores (pat, forget_old_reloads_1, NULL);
6495 if (reg_mentioned_p (rl->reg_rtx, pat))
6497 rtx set = single_set (insn);
6498 if (reload_spill_index[j] < 0
6500 && SET_SRC (set) == rl->reg_rtx)
6502 int src = REGNO (SET_SRC (set));
6504 reload_spill_index[j] = src;
6505 SET_HARD_REG_BIT (reg_is_output_reload, src);
6506 if (find_regno_note (insn, REG_DEAD, src))
6507 SET_HARD_REG_BIT (reg_reloaded_died, src);
6509 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6511 int s = rl->secondary_out_reload;
6512 set = single_set (p);
6513 /* If this reload copies only to the secondary reload
6514 register, the secondary reload does the actual
6516 if (s >= 0 && set == NULL_RTX)
6517 ; /* We can't tell what function the secondary reload
6518 has and where the actual store to the pseudo is
6519 made; leave new_spill_reg_store alone. */
6521 && SET_SRC (set) == rl->reg_rtx
6522 && SET_DEST (set) == rld[s].reg_rtx)
6524 /* Usually the next instruction will be the
6525 secondary reload insn; if we can confirm
6526 that it is, setting new_spill_reg_store to
6527 that insn will allow an extra optimization. */
6528 rtx s_reg = rld[s].reg_rtx;
6529 rtx next = NEXT_INSN (p);
6530 rld[s].out = rl->out;
6531 rld[s].out_reg = rl->out_reg;
6532 set = single_set (next);
6533 if (set && SET_SRC (set) == s_reg
6534 && ! new_spill_reg_store[REGNO (s_reg)])
6536 SET_HARD_REG_BIT (reg_is_output_reload,
6538 new_spill_reg_store[REGNO (s_reg)] = next;
6542 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6547 if (rl->when_needed == RELOAD_OTHER)
6549 emit_insns (other_output_reload_insns[rl->opnum]);
6550 other_output_reload_insns[rl->opnum] = get_insns ();
6553 output_reload_insns[rl->opnum] = get_insns ();
6558 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6559 and has the number J. */
6561 do_input_reload (chain, rl, j)
6562 struct insn_chain *chain;
6566 int expect_occurrences = 1;
6567 rtx insn = chain->insn;
6568 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6569 ? rl->in_reg : rl->in);
6572 /* AUTO_INC reloads need to be handled even if inherited. We got an
6573 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6574 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6575 && ! rtx_equal_p (rl->reg_rtx, old)
6576 && rl->reg_rtx != 0)
6578 emit_input_reload_insns (chain, rld + j, old, j);
6581 /* When inheriting a wider reload, we have a MEM in rl->in,
6582 e.g. inheriting a SImode output reload for
6583 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6584 if (optimize && reload_inherited[j] && rl->in
6585 && GET_CODE (rl->in) == MEM
6586 && GET_CODE (rl->in_reg) == MEM
6587 && reload_spill_index[j] >= 0
6588 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6591 = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1;
6593 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6596 /* If we are reloading a register that was recently stored in with an
6597 output-reload, see if we can prove there was
6598 actually no need to store the old value in it. */
6601 && (reload_inherited[j] || reload_override_in[j])
6603 && GET_CODE (rl->reg_rtx) == REG
6604 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6606 /* There doesn't seem to be any reason to restrict this to pseudos
6607 and doing so loses in the case where we are copying from a
6608 register of the wrong class. */
6609 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6610 >= FIRST_PSEUDO_REGISTER)
6612 /* The insn might have already some references to stackslots
6613 replaced by MEMs, while reload_out_reg still names the
6615 && (dead_or_set_p (insn,
6616 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6617 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6619 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6622 /* Do output reloading for reload RL, which is for the insn described by
6623 CHAIN and has the number J.
6624 ??? At some point we need to support handling output reloads of
6625 JUMP_INSNs or insns that set cc0. */
6627 do_output_reload (chain, rl, j)
6628 struct insn_chain *chain;
6633 rtx insn = chain->insn;
6634 /* If this is an output reload that stores something that is
6635 not loaded in this same reload, see if we can eliminate a previous
6637 rtx pseudo = rl->out_reg;
6640 && GET_CODE (pseudo) == REG
6641 && ! rtx_equal_p (rl->in_reg, pseudo)
6642 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6643 && reg_last_reload_reg[REGNO (pseudo)])
6645 int pseudo_no = REGNO (pseudo);
6646 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6648 /* We don't need to test full validity of last_regno for
6649 inherit here; we only want to know if the store actually
6650 matches the pseudo. */
6651 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6652 && reg_reloaded_contents[last_regno] == pseudo_no
6653 && spill_reg_store[last_regno]
6654 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6655 delete_output_reload (insn, j, last_regno);
6660 || rl->reg_rtx == old
6661 || rl->reg_rtx == 0)
6664 /* An output operand that dies right away does need a reload,
6665 but need not be copied from it. Show the new location in the
6667 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6668 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6670 XEXP (note, 0) = rl->reg_rtx;
6673 /* Likewise for a SUBREG of an operand that dies. */
6674 else if (GET_CODE (old) == SUBREG
6675 && GET_CODE (SUBREG_REG (old)) == REG
6676 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6679 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6683 else if (GET_CODE (old) == SCRATCH)
6684 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6685 but we don't want to make an output reload. */
6688 /* If is a JUMP_INSN, we can't support output reloads yet. */
6689 if (GET_CODE (insn) == JUMP_INSN)
6692 emit_output_reload_insns (chain, rld + j, j);
6695 /* Output insns to reload values in and out of the chosen reload regs. */
6698 emit_reload_insns (chain)
6699 struct insn_chain *chain;
6701 rtx insn = chain->insn;
6704 rtx following_insn = NEXT_INSN (insn);
6705 rtx before_insn = PREV_INSN (insn);
6707 CLEAR_HARD_REG_SET (reg_reloaded_died);
6709 for (j = 0; j < reload_n_operands; j++)
6710 input_reload_insns[j] = input_address_reload_insns[j]
6711 = inpaddr_address_reload_insns[j]
6712 = output_reload_insns[j] = output_address_reload_insns[j]
6713 = outaddr_address_reload_insns[j]
6714 = other_output_reload_insns[j] = 0;
6715 other_input_address_reload_insns = 0;
6716 other_input_reload_insns = 0;
6717 operand_reload_insns = 0;
6718 other_operand_reload_insns = 0;
6720 /* Now output the instructions to copy the data into and out of the
6721 reload registers. Do these in the order that the reloads were reported,
6722 since reloads of base and index registers precede reloads of operands
6723 and the operands may need the base and index registers reloaded. */
6725 for (j = 0; j < n_reloads; j++)
6728 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6729 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6731 do_input_reload (chain, rld + j, j);
6732 do_output_reload (chain, rld + j, j);
6735 /* Now write all the insns we made for reloads in the order expected by
6736 the allocation functions. Prior to the insn being reloaded, we write
6737 the following reloads:
6739 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6741 RELOAD_OTHER reloads.
6743 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6744 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6745 RELOAD_FOR_INPUT reload for the operand.
6747 RELOAD_FOR_OPADDR_ADDRS reloads.
6749 RELOAD_FOR_OPERAND_ADDRESS reloads.
6751 After the insn being reloaded, we write the following:
6753 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6754 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6755 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6756 reloads for the operand. The RELOAD_OTHER output reloads are
6757 output in descending order by reload number. */
6759 emit_insns_before (other_input_address_reload_insns, insn);
6760 emit_insns_before (other_input_reload_insns, insn);
6762 for (j = 0; j < reload_n_operands; j++)
6764 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6765 emit_insns_before (input_address_reload_insns[j], insn);
6766 emit_insns_before (input_reload_insns[j], insn);
6769 emit_insns_before (other_operand_reload_insns, insn);
6770 emit_insns_before (operand_reload_insns, insn);
6772 for (j = 0; j < reload_n_operands; j++)
6774 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6775 emit_insns_before (output_address_reload_insns[j], following_insn);
6776 emit_insns_before (output_reload_insns[j], following_insn);
6777 emit_insns_before (other_output_reload_insns[j], following_insn);
6780 /* Keep basic block info up to date. */
6783 if (BLOCK_HEAD (chain->block) == insn)
6784 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6785 if (BLOCK_END (chain->block) == insn)
6786 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6789 /* For all the spill regs newly reloaded in this instruction,
6790 record what they were reloaded from, so subsequent instructions
6791 can inherit the reloads.
6793 Update spill_reg_store for the reloads of this insn.
6794 Copy the elements that were updated in the loop above. */
6796 for (j = 0; j < n_reloads; j++)
6798 register int r = reload_order[j];
6799 register int i = reload_spill_index[r];
6801 /* If this is a non-inherited input reload from a pseudo, we must
6802 clear any memory of a previous store to the same pseudo. Only do
6803 something if there will not be an output reload for the pseudo
6805 if (rld[r].in_reg != 0
6806 && ! (reload_inherited[r] || reload_override_in[r]))
6808 rtx reg = rld[r].in_reg;
6810 if (GET_CODE (reg) == SUBREG)
6811 reg = SUBREG_REG (reg);
6813 if (GET_CODE (reg) == REG
6814 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6815 && ! reg_has_output_reload[REGNO (reg)])
6817 int nregno = REGNO (reg);
6819 if (reg_last_reload_reg[nregno])
6821 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6823 if (reg_reloaded_contents[last_regno] == nregno)
6824 spill_reg_store[last_regno] = 0;
6829 /* I is nonneg if this reload used a register.
6830 If rld[r].reg_rtx is 0, this is an optional reload
6831 that we opted to ignore. */
6833 if (i >= 0 && rld[r].reg_rtx != 0)
6836 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6838 int part_reaches_end = 0;
6839 int all_reaches_end = 1;
6841 /* For a multi register reload, we need to check if all or part
6842 of the value lives to the end. */
6843 for (k = 0; k < nr; k++)
6845 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6846 rld[r].when_needed))
6847 part_reaches_end = 1;
6849 all_reaches_end = 0;
6852 /* Ignore reloads that don't reach the end of the insn in
6854 if (all_reaches_end)
6856 /* First, clear out memory of what used to be in this spill reg.
6857 If consecutive registers are used, clear them all. */
6859 for (k = 0; k < nr; k++)
6860 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6862 /* Maybe the spill reg contains a copy of reload_out. */
6864 && (GET_CODE (rld[r].out) == REG
6868 || GET_CODE (rld[r].out_reg) == REG))
6870 rtx out = (GET_CODE (rld[r].out) == REG
6874 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6875 register int nregno = REGNO (out);
6876 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6877 : HARD_REGNO_NREGS (nregno,
6878 GET_MODE (rld[r].reg_rtx)));
6880 spill_reg_store[i] = new_spill_reg_store[i];
6881 spill_reg_stored_to[i] = out;
6882 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6884 /* If NREGNO is a hard register, it may occupy more than
6885 one register. If it does, say what is in the
6886 rest of the registers assuming that both registers
6887 agree on how many words the object takes. If not,
6888 invalidate the subsequent registers. */
6890 if (nregno < FIRST_PSEUDO_REGISTER)
6891 for (k = 1; k < nnr; k++)
6892 reg_last_reload_reg[nregno + k]
6894 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6895 REGNO (rld[r].reg_rtx) + k)
6898 /* Now do the inverse operation. */
6899 for (k = 0; k < nr; k++)
6901 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6902 reg_reloaded_contents[i + k]
6903 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6906 reg_reloaded_insn[i + k] = insn;
6907 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6911 /* Maybe the spill reg contains a copy of reload_in. Only do
6912 something if there will not be an output reload for
6913 the register being reloaded. */
6914 else if (rld[r].out_reg == 0
6916 && ((GET_CODE (rld[r].in) == REG
6917 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6918 && ! reg_has_output_reload[REGNO (rld[r].in)])
6919 || (GET_CODE (rld[r].in_reg) == REG
6920 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6921 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6923 register int nregno;
6926 if (GET_CODE (rld[r].in) == REG
6927 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6928 nregno = REGNO (rld[r].in);
6929 else if (GET_CODE (rld[r].in_reg) == REG)
6930 nregno = REGNO (rld[r].in_reg);
6932 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6934 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6935 : HARD_REGNO_NREGS (nregno,
6936 GET_MODE (rld[r].reg_rtx)));
6938 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6940 if (nregno < FIRST_PSEUDO_REGISTER)
6941 for (k = 1; k < nnr; k++)
6942 reg_last_reload_reg[nregno + k]
6944 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6945 REGNO (rld[r].reg_rtx) + k)
6948 /* Unless we inherited this reload, show we haven't
6949 recently done a store.
6950 Previous stores of inherited auto_inc expressions
6951 also have to be discarded. */
6952 if (! reload_inherited[r]
6953 || (rld[r].out && ! rld[r].out_reg))
6954 spill_reg_store[i] = 0;
6956 for (k = 0; k < nr; k++)
6958 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6959 reg_reloaded_contents[i + k]
6960 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6963 reg_reloaded_insn[i + k] = insn;
6964 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6969 /* However, if part of the reload reaches the end, then we must
6970 invalidate the old info for the part that survives to the end. */
6971 else if (part_reaches_end)
6973 for (k = 0; k < nr; k++)
6974 if (reload_reg_reaches_end_p (i + k,
6976 rld[r].when_needed))
6977 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6981 /* The following if-statement was #if 0'd in 1.34 (or before...).
6982 It's reenabled in 1.35 because supposedly nothing else
6983 deals with this problem. */
6985 /* If a register gets output-reloaded from a non-spill register,
6986 that invalidates any previous reloaded copy of it.
6987 But forget_old_reloads_1 won't get to see it, because
6988 it thinks only about the original insn. So invalidate it here. */
6989 if (i < 0 && rld[r].out != 0
6990 && (GET_CODE (rld[r].out) == REG
6991 || (GET_CODE (rld[r].out) == MEM
6992 && GET_CODE (rld[r].out_reg) == REG)))
6994 rtx out = (GET_CODE (rld[r].out) == REG
6995 ? rld[r].out : rld[r].out_reg);
6996 register int nregno = REGNO (out);
6997 if (nregno >= FIRST_PSEUDO_REGISTER)
6999 rtx src_reg, store_insn = NULL_RTX;
7001 reg_last_reload_reg[nregno] = 0;
7003 /* If we can find a hard register that is stored, record
7004 the storing insn so that we may delete this insn with
7005 delete_output_reload. */
7006 src_reg = rld[r].reg_rtx;
7008 /* If this is an optional reload, try to find the source reg
7009 from an input reload. */
7012 rtx set = single_set (insn);
7013 if (set && SET_DEST (set) == rld[r].out)
7017 src_reg = SET_SRC (set);
7019 for (k = 0; k < n_reloads; k++)
7021 if (rld[k].in == src_reg)
7023 src_reg = rld[k].reg_rtx;
7030 store_insn = new_spill_reg_store[REGNO (src_reg)];
7031 if (src_reg && GET_CODE (src_reg) == REG
7032 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7034 int src_regno = REGNO (src_reg);
7035 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7036 /* The place where to find a death note varies with
7037 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7038 necessarily checked exactly in the code that moves
7039 notes, so just check both locations. */
7040 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7042 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7045 spill_reg_store[src_regno + nr] = store_insn;
7046 spill_reg_stored_to[src_regno + nr] = out;
7047 reg_reloaded_contents[src_regno + nr] = nregno;
7048 reg_reloaded_insn[src_regno + nr] = store_insn;
7049 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7050 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7051 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7053 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7055 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7057 reg_last_reload_reg[nregno] = src_reg;
7062 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7064 while (num_regs-- > 0)
7065 reg_last_reload_reg[nregno + num_regs] = 0;
7069 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7072 /* Emit code to perform a reload from IN (which may be a reload register) to
7073 OUT (which may also be a reload register). IN or OUT is from operand
7074 OPNUM with reload type TYPE.
7076 Returns first insn emitted. */
7079 gen_reload (out, in, opnum, type)
7083 enum reload_type type;
7085 rtx last = get_last_insn ();
7088 /* If IN is a paradoxical SUBREG, remove it and try to put the
7089 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7090 if (GET_CODE (in) == SUBREG
7091 && (GET_MODE_SIZE (GET_MODE (in))
7092 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7093 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7094 in = SUBREG_REG (in), out = tem;
7095 else if (GET_CODE (out) == SUBREG
7096 && (GET_MODE_SIZE (GET_MODE (out))
7097 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7098 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7099 out = SUBREG_REG (out), in = tem;
7101 /* How to do this reload can get quite tricky. Normally, we are being
7102 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7103 register that didn't get a hard register. In that case we can just
7104 call emit_move_insn.
7106 We can also be asked to reload a PLUS that adds a register or a MEM to
7107 another register, constant or MEM. This can occur during frame pointer
7108 elimination and while reloading addresses. This case is handled by
7109 trying to emit a single insn to perform the add. If it is not valid,
7110 we use a two insn sequence.
7112 Finally, we could be called to handle an 'o' constraint by putting
7113 an address into a register. In that case, we first try to do this
7114 with a named pattern of "reload_load_address". If no such pattern
7115 exists, we just emit a SET insn and hope for the best (it will normally
7116 be valid on machines that use 'o').
7118 This entire process is made complex because reload will never
7119 process the insns we generate here and so we must ensure that
7120 they will fit their constraints and also by the fact that parts of
7121 IN might be being reloaded separately and replaced with spill registers.
7122 Because of this, we are, in some sense, just guessing the right approach
7123 here. The one listed above seems to work.
7125 ??? At some point, this whole thing needs to be rethought. */
7127 if (GET_CODE (in) == PLUS
7128 && (GET_CODE (XEXP (in, 0)) == REG
7129 || GET_CODE (XEXP (in, 0)) == SUBREG
7130 || GET_CODE (XEXP (in, 0)) == MEM)
7131 && (GET_CODE (XEXP (in, 1)) == REG
7132 || GET_CODE (XEXP (in, 1)) == SUBREG
7133 || CONSTANT_P (XEXP (in, 1))
7134 || GET_CODE (XEXP (in, 1)) == MEM))
7136 /* We need to compute the sum of a register or a MEM and another
7137 register, constant, or MEM, and put it into the reload
7138 register. The best possible way of doing this is if the machine
7139 has a three-operand ADD insn that accepts the required operands.
7141 The simplest approach is to try to generate such an insn and see if it
7142 is recognized and matches its constraints. If so, it can be used.
7144 It might be better not to actually emit the insn unless it is valid,
7145 but we need to pass the insn as an operand to `recog' and
7146 `extract_insn' and it is simpler to emit and then delete the insn if
7147 not valid than to dummy things up. */
7149 rtx op0, op1, tem, insn;
7152 op0 = find_replacement (&XEXP (in, 0));
7153 op1 = find_replacement (&XEXP (in, 1));
7155 /* Since constraint checking is strict, commutativity won't be
7156 checked, so we need to do that here to avoid spurious failure
7157 if the add instruction is two-address and the second operand
7158 of the add is the same as the reload reg, which is frequently
7159 the case. If the insn would be A = B + A, rearrange it so
7160 it will be A = A + B as constrain_operands expects. */
7162 if (GET_CODE (XEXP (in, 1)) == REG
7163 && REGNO (out) == REGNO (XEXP (in, 1)))
7164 tem = op0, op0 = op1, op1 = tem;
7166 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7167 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7169 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7170 code = recog_memoized (insn);
7174 extract_insn (insn);
7175 /* We want constrain operands to treat this insn strictly in
7176 its validity determination, i.e., the way it would after reload
7178 if (constrain_operands (1))
7182 delete_insns_since (last);
7184 /* If that failed, we must use a conservative two-insn sequence.
7186 Use a move to copy one operand into the reload register. Prefer
7187 to reload a constant, MEM or pseudo since the move patterns can
7188 handle an arbitrary operand. If OP1 is not a constant, MEM or
7189 pseudo and OP1 is not a valid operand for an add instruction, then
7192 After reloading one of the operands into the reload register, add
7193 the reload register to the output register.
7195 If there is another way to do this for a specific machine, a
7196 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7199 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7201 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7202 || (GET_CODE (op1) == REG
7203 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7204 || (code != CODE_FOR_nothing
7205 && ! ((*insn_data[code].operand[2].predicate)
7206 (op1, insn_data[code].operand[2].mode))))
7207 tem = op0, op0 = op1, op1 = tem;
7209 gen_reload (out, op0, opnum, type);
7211 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7212 This fixes a problem on the 32K where the stack pointer cannot
7213 be used as an operand of an add insn. */
7215 if (rtx_equal_p (op0, op1))
7218 insn = emit_insn (gen_add2_insn (out, op1));
7220 /* If that failed, copy the address register to the reload register.
7221 Then add the constant to the reload register. */
7223 code = recog_memoized (insn);
7227 extract_insn (insn);
7228 /* We want constrain operands to treat this insn strictly in
7229 its validity determination, i.e., the way it would after reload
7231 if (constrain_operands (1))
7233 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7235 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7240 delete_insns_since (last);
7242 gen_reload (out, op1, opnum, type);
7243 insn = emit_insn (gen_add2_insn (out, op0));
7244 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7247 #ifdef SECONDARY_MEMORY_NEEDED
7248 /* If we need a memory location to do the move, do it that way. */
7249 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7250 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7251 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7252 REGNO_REG_CLASS (REGNO (out)),
7255 /* Get the memory to use and rewrite both registers to its mode. */
7256 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7258 if (GET_MODE (loc) != GET_MODE (out))
7259 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7261 if (GET_MODE (loc) != GET_MODE (in))
7262 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7264 gen_reload (loc, in, opnum, type);
7265 gen_reload (out, loc, opnum, type);
7269 /* If IN is a simple operand, use gen_move_insn. */
7270 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7271 emit_insn (gen_move_insn (out, in));
7273 #ifdef HAVE_reload_load_address
7274 else if (HAVE_reload_load_address)
7275 emit_insn (gen_reload_load_address (out, in));
7278 /* Otherwise, just write (set OUT IN) and hope for the best. */
7280 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7282 /* Return the first insn emitted.
7283 We can not just return get_last_insn, because there may have
7284 been multiple instructions emitted. Also note that gen_move_insn may
7285 emit more than one insn itself, so we can not assume that there is one
7286 insn emitted per emit_insn_before call. */
7288 return last ? NEXT_INSN (last) : get_insns ();
7291 /* Delete a previously made output-reload
7292 whose result we now believe is not needed.
7293 First we double-check.
7295 INSN is the insn now being processed.
7296 LAST_RELOAD_REG is the hard register number for which we want to delete
7297 the last output reload.
7298 J is the reload-number that originally used REG. The caller has made
7299 certain that reload J doesn't use REG any longer for input. */
7302 delete_output_reload (insn, j, last_reload_reg)
7305 int last_reload_reg;
7307 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7308 rtx reg = spill_reg_stored_to[last_reload_reg];
7311 int n_inherited = 0;
7315 /* Get the raw pseudo-register referred to. */
7317 while (GET_CODE (reg) == SUBREG)
7318 reg = SUBREG_REG (reg);
7319 substed = reg_equiv_memory_loc[REGNO (reg)];
7321 /* This is unsafe if the operand occurs more often in the current
7322 insn than it is inherited. */
7323 for (k = n_reloads - 1; k >= 0; k--)
7325 rtx reg2 = rld[k].in;
7328 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7329 reg2 = rld[k].in_reg;
7331 if (rld[k].out && ! rld[k].out_reg)
7332 reg2 = XEXP (rld[k].in_reg, 0);
7334 while (GET_CODE (reg2) == SUBREG)
7335 reg2 = SUBREG_REG (reg2);
7336 if (rtx_equal_p (reg2, reg))
7338 if (reload_inherited[k] || reload_override_in[k] || k == j)
7341 reg2 = rld[k].out_reg;
7344 while (GET_CODE (reg2) == SUBREG)
7345 reg2 = XEXP (reg2, 0);
7346 if (rtx_equal_p (reg2, reg))
7353 n_occurrences = count_occurrences (PATTERN (insn), reg);
7355 n_occurrences += count_occurrences (PATTERN (insn), substed);
7356 if (n_occurrences > n_inherited)
7359 /* If the pseudo-reg we are reloading is no longer referenced
7360 anywhere between the store into it and here,
7361 and no jumps or labels intervene, then the value can get
7362 here through the reload reg alone.
7363 Otherwise, give up--return. */
7364 for (i1 = NEXT_INSN (output_reload_insn);
7365 i1 != insn; i1 = NEXT_INSN (i1))
7367 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7369 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7370 && reg_mentioned_p (reg, PATTERN (i1)))
7372 /* If this is USE in front of INSN, we only have to check that
7373 there are no more references than accounted for by inheritance. */
7374 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7376 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7377 i1 = NEXT_INSN (i1);
7379 if (n_occurrences <= n_inherited && i1 == insn)
7385 /* The caller has already checked that REG dies or is set in INSN.
7386 It has also checked that we are optimizing, and thus some inaccurancies
7387 in the debugging information are acceptable.
7388 So we could just delete output_reload_insn.
7389 But in some cases we can improve the debugging information without
7390 sacrificing optimization - maybe even improving the code:
7391 See if the pseudo reg has been completely replaced
7392 with reload regs. If so, delete the store insn
7393 and forget we had a stack slot for the pseudo. */
7394 if (rld[j].out != rld[j].in
7395 && REG_N_DEATHS (REGNO (reg)) == 1
7396 && REG_N_SETS (REGNO (reg)) == 1
7397 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7398 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7402 /* We know that it was used only between here
7403 and the beginning of the current basic block.
7404 (We also know that the last use before INSN was
7405 the output reload we are thinking of deleting, but never mind that.)
7406 Search that range; see if any ref remains. */
7407 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7409 rtx set = single_set (i2);
7411 /* Uses which just store in the pseudo don't count,
7412 since if they are the only uses, they are dead. */
7413 if (set != 0 && SET_DEST (set) == reg)
7415 if (GET_CODE (i2) == CODE_LABEL
7416 || GET_CODE (i2) == JUMP_INSN)
7418 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7419 && reg_mentioned_p (reg, PATTERN (i2)))
7421 /* Some other ref remains; just delete the output reload we
7423 delete_address_reloads (output_reload_insn, insn);
7424 PUT_CODE (output_reload_insn, NOTE);
7425 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7426 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7431 /* Delete the now-dead stores into this pseudo. */
7432 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7434 rtx set = single_set (i2);
7436 if (set != 0 && SET_DEST (set) == reg)
7438 delete_address_reloads (i2, insn);
7439 /* This might be a basic block head,
7440 thus don't use delete_insn. */
7441 PUT_CODE (i2, NOTE);
7442 NOTE_SOURCE_FILE (i2) = 0;
7443 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7445 if (GET_CODE (i2) == CODE_LABEL
7446 || GET_CODE (i2) == JUMP_INSN)
7450 /* For the debugging info,
7451 say the pseudo lives in this reload reg. */
7452 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7453 alter_reg (REGNO (reg), -1);
7455 delete_address_reloads (output_reload_insn, insn);
7456 PUT_CODE (output_reload_insn, NOTE);
7457 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7458 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7462 /* We are going to delete DEAD_INSN. Recursively delete loads of
7463 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7464 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7466 delete_address_reloads (dead_insn, current_insn)
7467 rtx dead_insn, current_insn;
7469 rtx set = single_set (dead_insn);
7470 rtx set2, dst, prev, next;
7473 rtx dst = SET_DEST (set);
7474 if (GET_CODE (dst) == MEM)
7475 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7477 /* If we deleted the store from a reloaded post_{in,de}c expression,
7478 we can delete the matching adds. */
7479 prev = PREV_INSN (dead_insn);
7480 next = NEXT_INSN (dead_insn);
7481 if (! prev || ! next)
7483 set = single_set (next);
7484 set2 = single_set (prev);
7486 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7487 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7488 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7490 dst = SET_DEST (set);
7491 if (! rtx_equal_p (dst, SET_DEST (set2))
7492 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7493 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7494 || (INTVAL (XEXP (SET_SRC (set), 1))
7495 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7501 /* Subfunction of delete_address_reloads: process registers found in X. */
7503 delete_address_reloads_1 (dead_insn, x, current_insn)
7504 rtx dead_insn, x, current_insn;
7506 rtx prev, set, dst, i2;
7508 enum rtx_code code = GET_CODE (x);
7512 const char *fmt= GET_RTX_FORMAT (code);
7513 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7516 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7517 else if (fmt[i] == 'E')
7519 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7520 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7527 if (spill_reg_order[REGNO (x)] < 0)
7530 /* Scan backwards for the insn that sets x. This might be a way back due
7532 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7534 code = GET_CODE (prev);
7535 if (code == CODE_LABEL || code == JUMP_INSN)
7537 if (GET_RTX_CLASS (code) != 'i')
7539 if (reg_set_p (x, PATTERN (prev)))
7541 if (reg_referenced_p (x, PATTERN (prev)))
7544 if (! prev || INSN_UID (prev) < reload_first_uid)
7546 /* Check that PREV only sets the reload register. */
7547 set = single_set (prev);
7550 dst = SET_DEST (set);
7551 if (GET_CODE (dst) != REG
7552 || ! rtx_equal_p (dst, x))
7554 if (! reg_set_p (dst, PATTERN (dead_insn)))
7556 /* Check if DST was used in a later insn -
7557 it might have been inherited. */
7558 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7560 if (GET_CODE (i2) == CODE_LABEL)
7562 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7564 if (reg_referenced_p (dst, PATTERN (i2)))
7566 /* If there is a reference to the register in the current insn,
7567 it might be loaded in a non-inherited reload. If no other
7568 reload uses it, that means the register is set before
7570 if (i2 == current_insn)
7572 for (j = n_reloads - 1; j >= 0; j--)
7573 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7574 || reload_override_in[j] == dst)
7576 for (j = n_reloads - 1; j >= 0; j--)
7577 if (rld[j].in && rld[j].reg_rtx == dst)
7584 if (GET_CODE (i2) == JUMP_INSN)
7586 /* If DST is still live at CURRENT_INSN, check if it is used for
7587 any reload. Note that even if CURRENT_INSN sets DST, we still
7588 have to check the reloads. */
7589 if (i2 == current_insn)
7591 for (j = n_reloads - 1; j >= 0; j--)
7592 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7593 || reload_override_in[j] == dst)
7595 /* ??? We can't finish the loop here, because dst might be
7596 allocated to a pseudo in this block if no reload in this
7597 block needs any of the clsses containing DST - see
7598 spill_hard_reg. There is no easy way to tell this, so we
7599 have to scan till the end of the basic block. */
7601 if (reg_set_p (dst, PATTERN (i2)))
7605 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7606 reg_reloaded_contents[REGNO (dst)] = -1;
7607 /* Can't use delete_insn here because PREV might be a basic block head. */
7608 PUT_CODE (prev, NOTE);
7609 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7610 NOTE_SOURCE_FILE (prev) = 0;
7613 /* Output reload-insns to reload VALUE into RELOADREG.
7614 VALUE is an autoincrement or autodecrement RTX whose operand
7615 is a register or memory location;
7616 so reloading involves incrementing that location.
7617 IN is either identical to VALUE, or some cheaper place to reload from.
7619 INC_AMOUNT is the number to increment or decrement by (always positive).
7620 This cannot be deduced from VALUE.
7622 Return the instruction that stores into RELOADREG. */
7625 inc_for_reload (reloadreg, in, value, inc_amount)
7630 /* REG or MEM to be copied and incremented. */
7631 rtx incloc = XEXP (value, 0);
7632 /* Nonzero if increment after copying. */
7633 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7639 rtx real_in = in == value ? XEXP (in, 0) : in;
7641 /* No hard register is equivalent to this register after
7642 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7643 we could inc/dec that register as well (maybe even using it for
7644 the source), but I'm not sure it's worth worrying about. */
7645 if (GET_CODE (incloc) == REG)
7646 reg_last_reload_reg[REGNO (incloc)] = 0;
7648 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7649 inc_amount = - inc_amount;
7651 inc = GEN_INT (inc_amount);
7653 /* If this is post-increment, first copy the location to the reload reg. */
7654 if (post && real_in != reloadreg)
7655 emit_insn (gen_move_insn (reloadreg, real_in));
7659 /* See if we can directly increment INCLOC. Use a method similar to
7660 that in gen_reload. */
7662 last = get_last_insn ();
7663 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7664 gen_rtx_PLUS (GET_MODE (incloc),
7667 code = recog_memoized (add_insn);
7670 extract_insn (add_insn);
7671 if (constrain_operands (1))
7673 /* If this is a pre-increment and we have incremented the value
7674 where it lives, copy the incremented value to RELOADREG to
7675 be used as an address. */
7678 emit_insn (gen_move_insn (reloadreg, incloc));
7683 delete_insns_since (last);
7686 /* If couldn't do the increment directly, must increment in RELOADREG.
7687 The way we do this depends on whether this is pre- or post-increment.
7688 For pre-increment, copy INCLOC to the reload register, increment it
7689 there, then save back. */
7693 if (in != reloadreg)
7694 emit_insn (gen_move_insn (reloadreg, real_in));
7695 emit_insn (gen_add2_insn (reloadreg, inc));
7696 store = emit_insn (gen_move_insn (incloc, reloadreg));
7701 Because this might be a jump insn or a compare, and because RELOADREG
7702 may not be available after the insn in an input reload, we must do
7703 the incrementation before the insn being reloaded for.
7705 We have already copied IN to RELOADREG. Increment the copy in
7706 RELOADREG, save that back, then decrement RELOADREG so it has
7707 the original value. */
7709 emit_insn (gen_add2_insn (reloadreg, inc));
7710 store = emit_insn (gen_move_insn (incloc, reloadreg));
7711 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7717 /* Return 1 if we are certain that the constraint-string STRING allows
7718 the hard register REG. Return 0 if we can't be sure of this. */
7721 constraint_accepts_reg_p (string, reg)
7726 int regno = true_regnum (reg);
7729 /* Initialize for first alternative. */
7731 /* Check that each alternative contains `g' or `r'. */
7733 switch (c = *string++)
7736 /* If an alternative lacks `g' or `r', we lose. */
7739 /* If an alternative lacks `g' or `r', we lose. */
7742 /* Initialize for next alternative. */
7747 /* Any general reg wins for this alternative. */
7748 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7752 /* Any reg in specified class wins for this alternative. */
7754 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7756 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7762 /* Return the number of places FIND appears within X, but don't count
7763 an occurrence if some SET_DEST is FIND. */
7766 count_occurrences (x, find)
7767 register rtx x, find;
7770 register enum rtx_code code;
7771 register const char *format_ptr;
7779 code = GET_CODE (x);
7794 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
7798 if (SET_DEST (x) == find)
7799 return count_occurrences (SET_SRC (x), find);
7806 format_ptr = GET_RTX_FORMAT (code);
7809 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7811 switch (*format_ptr++)
7814 count += count_occurrences (XEXP (x, i), find);
7818 if (XVEC (x, i) != NULL)
7820 for (j = 0; j < XVECLEN (x, i); j++)
7821 count += count_occurrences (XVECEXP (x, i, j), find);
7829 /* This array holds values which are equivalent to a hard register
7830 during reload_cse_regs. Each array element is an EXPR_LIST of
7831 values. Each time a hard register is set, we set the corresponding
7832 array element to the value. Each time a hard register is copied
7833 into memory, we add the memory location to the corresponding array
7834 element. We don't store values or memory addresses with side
7835 effects in this array.
7837 If the value is a CONST_INT, then the mode of the containing
7838 EXPR_LIST is the mode in which that CONST_INT was referenced.
7840 We sometimes clobber a specific entry in a list. In that case, we
7841 just set XEXP (list-entry, 0) to 0. */
7843 static rtx *reg_values;
7845 /* This is a preallocated REG rtx which we use as a temporary in
7846 reload_cse_invalidate_regno, so that we don't need to allocate a
7847 new one each time through a loop in that function. */
7849 static rtx invalidate_regno_rtx;
7851 /* Invalidate any entries in reg_values which depend on REGNO,
7852 including those for REGNO itself. This is called if REGNO is
7853 changing. If CLOBBER is true, then always forget anything we
7854 currently know about REGNO. MODE is the mode of the assignment to
7855 REGNO, which is used to determine how many hard registers are being
7856 changed. If MODE is VOIDmode, then only REGNO is being changed;
7857 this is used when invalidating call clobbered registers across a
7861 reload_cse_invalidate_regno (regno, mode, clobber)
7863 enum machine_mode mode;
7869 /* Our callers don't always go through true_regnum; we may see a
7870 pseudo-register here from a CLOBBER or the like. We probably
7871 won't ever see a pseudo-register that has a real register number,
7872 for we check anyhow for safety. */
7873 if (regno >= FIRST_PSEUDO_REGISTER)
7874 regno = reg_renumber[regno];
7878 if (mode == VOIDmode)
7879 endregno = regno + 1;
7881 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7884 for (i = regno; i < endregno; i++)
7887 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7891 for (x = reg_values[i]; x; x = XEXP (x, 1))
7893 if (XEXP (x, 0) != 0
7894 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7896 /* If this is the only entry on the list, clear
7897 reg_values[i]. Otherwise, just clear this entry on
7899 if (XEXP (x, 1) == 0 && x == reg_values[i])
7909 /* We must look at earlier registers, in case REGNO is part of a
7910 multi word value but is not the first register. If an earlier
7911 register has a value in a mode which overlaps REGNO, then we must
7912 invalidate that earlier register. Note that we do not need to
7913 check REGNO or later registers (we must not check REGNO itself,
7914 because we would incorrectly conclude that there was a conflict). */
7916 for (i = 0; i < regno; i++)
7920 for (x = reg_values[i]; x; x = XEXP (x, 1))
7922 if (XEXP (x, 0) != 0)
7924 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
7925 REGNO (invalidate_regno_rtx) = i;
7926 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7929 reload_cse_invalidate_regno (i, VOIDmode, 1);
7937 /* The memory at address MEM_BASE is being changed.
7938 Return whether this change will invalidate VAL. */
7941 reload_cse_mem_conflict_p (mem_base, val)
7949 code = GET_CODE (val);
7952 /* Get rid of a few simple cases quickly. */
7965 if (GET_MODE (mem_base) == BLKmode
7966 || GET_MODE (val) == BLKmode)
7968 if (anti_dependence (val, mem_base))
7970 /* The address may contain nested MEMs. */
7977 fmt = GET_RTX_FORMAT (code);
7979 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7983 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
7986 else if (fmt[i] == 'E')
7990 for (j = 0; j < XVECLEN (val, i); j++)
7991 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
7999 /* Invalidate any entries in reg_values which are changed because of a
8000 store to MEM_RTX. If this is called because of a non-const call
8001 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8004 reload_cse_invalidate_mem (mem_rtx)
8009 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8013 for (x = reg_values[i]; x; x = XEXP (x, 1))
8015 if (XEXP (x, 0) != 0
8016 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8018 /* If this is the only entry on the list, clear
8019 reg_values[i]. Otherwise, just clear this entry on
8021 if (XEXP (x, 1) == 0 && x == reg_values[i])
8032 /* Invalidate DEST, which is being assigned to or clobbered. The
8033 second parameter exists so that this function can be passed to
8034 note_stores; it is ignored. */
8037 reload_cse_invalidate_rtx (dest, ignore, data)
8039 rtx ignore ATTRIBUTE_UNUSED;
8040 void *data ATTRIBUTE_UNUSED;
8042 while (GET_CODE (dest) == STRICT_LOW_PART
8043 || GET_CODE (dest) == SIGN_EXTRACT
8044 || GET_CODE (dest) == ZERO_EXTRACT
8045 || GET_CODE (dest) == SUBREG)
8046 dest = XEXP (dest, 0);
8048 if (GET_CODE (dest) == REG)
8049 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8050 else if (GET_CODE (dest) == MEM)
8051 reload_cse_invalidate_mem (dest);
8054 /* Do a very simple CSE pass over the hard registers.
8056 This function detects no-op moves where we happened to assign two
8057 different pseudo-registers to the same hard register, and then
8058 copied one to the other. Reload will generate a useless
8059 instruction copying a register to itself.
8061 This function also detects cases where we load a value from memory
8062 into two different registers, and (if memory is more expensive than
8063 registers) changes it to simply copy the first register into the
8066 Another optimization is performed that scans the operands of each
8067 instruction to see whether the value is already available in a
8068 hard register. It then replaces the operand with the hard register
8069 if possible, much like an optional reload would. */
8072 reload_cse_regs_1 (first)
8080 init_alias_analysis ();
8082 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8083 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8085 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8086 free them when we are done. */
8087 push_obstacks (&reload_obstack, &reload_obstack);
8088 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8090 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8091 memory for a non-const call instruction. */
8092 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8094 /* This is used in reload_cse_invalidate_regno to avoid consing a
8095 new REG in a loop in that function. */
8096 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8098 for (insn = first; insn; insn = NEXT_INSN (insn))
8102 if (GET_CODE (insn) == CODE_LABEL)
8104 /* Forget all the register values at a code label. We don't
8105 try to do anything clever around jumps. */
8106 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8112 #ifdef NON_SAVING_SETJMP
8113 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8114 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8116 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8123 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8126 /* If this is a call instruction, forget anything stored in a
8127 call clobbered register, or, if this is not a const call, in
8129 if (GET_CODE (insn) == CALL_INSN)
8131 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8132 if (call_used_regs[i])
8133 reload_cse_invalidate_regno (i, VOIDmode, 1);
8135 if (! CONST_CALL_P (insn))
8136 reload_cse_invalidate_mem (callmem);
8140 /* Forget all the register values at a volatile asm. */
8141 if (GET_CODE (insn) == INSN
8142 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8143 && MEM_VOLATILE_P (PATTERN (insn)))
8144 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8147 body = PATTERN (insn);
8148 if (GET_CODE (body) == SET)
8151 if (reload_cse_noop_set_p (body, insn))
8153 /* If this sets the return value of the function, we must keep
8154 a USE around, in case this is in a different basic block
8155 than the final USE. Otherwise, we could loose important
8156 register lifeness information on SMALL_REGISTER_CLASSES
8157 machines, where return registers might be used as spills:
8158 subsequent passes assume that spill registers are dead at
8159 the end of a basic block. */
8160 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8163 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8164 INSN_CODE (insn) = -1;
8165 REG_NOTES (insn) = NULL_RTX;
8166 push_obstacks (&reload_obstack, &reload_obstack);
8170 PUT_CODE (insn, NOTE);
8171 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8172 NOTE_SOURCE_FILE (insn) = 0;
8175 /* We're done with this insn. */
8179 /* It's not a no-op, but we can try to simplify it. */
8180 count += reload_cse_simplify_set (body, insn);
8183 apply_change_group ();
8185 reload_cse_simplify_operands (insn);
8187 reload_cse_record_set (body, body);
8189 else if (GET_CODE (body) == PARALLEL)
8192 rtx value = NULL_RTX;
8194 /* If every action in a PARALLEL is a noop, we can delete
8195 the entire PARALLEL. */
8196 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8198 rtx part = XVECEXP (body, 0, i);
8199 if (GET_CODE (part) == SET)
8201 if (! reload_cse_noop_set_p (part, insn))
8203 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8207 value = SET_DEST (part);
8210 else if (GET_CODE (part) != CLOBBER)
8218 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8219 INSN_CODE (insn) = -1;
8220 REG_NOTES (insn) = NULL_RTX;
8221 push_obstacks (&reload_obstack, &reload_obstack);
8225 PUT_CODE (insn, NOTE);
8226 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8227 NOTE_SOURCE_FILE (insn) = 0;
8230 /* We're done with this insn. */
8234 /* It's not a no-op, but we can try to simplify it. */
8235 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8236 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8237 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8240 apply_change_group ();
8242 reload_cse_simplify_operands (insn);
8244 /* Look through the PARALLEL and record the values being
8245 set, if possible. Also handle any CLOBBERs. */
8246 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8248 rtx x = XVECEXP (body, 0, i);
8250 if (GET_CODE (x) == SET)
8251 reload_cse_record_set (x, body);
8253 note_stores (x, reload_cse_invalidate_rtx, NULL);
8257 note_stores (body, reload_cse_invalidate_rtx, NULL);
8260 /* Clobber any registers which appear in REG_INC notes. We
8261 could keep track of the changes to their values, but it is
8262 unlikely to help. */
8266 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8267 if (REG_NOTE_KIND (x) == REG_INC)
8268 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL);
8272 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8273 after we have processed the insn. */
8274 if (GET_CODE (insn) == CALL_INSN)
8278 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8279 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8280 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX,
8286 end_alias_analysis ();
8288 /* Free all the temporary structures we created, and go back to the
8289 regular obstacks. */
8290 obstack_free (&reload_obstack, firstobj);
8294 /* Call cse / combine like post-reload optimization phases.
8295 FIRST is the first instruction. */
8297 reload_cse_regs (first)
8300 reload_cse_regs_1 (first);
8302 reload_cse_move2add (first);
8303 if (flag_expensive_optimizations)
8304 reload_cse_regs_1 (first);
8307 /* Return whether the values known for REGNO are equal to VAL. MODE
8308 is the mode of the object that VAL is being copied to; this matters
8309 if VAL is a CONST_INT. */
8312 reload_cse_regno_equal_p (regno, val, mode)
8315 enum machine_mode mode;
8322 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8323 if (XEXP (x, 0) != 0
8324 && rtx_equal_p (XEXP (x, 0), val)
8325 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8326 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8327 && (GET_CODE (val) != CONST_INT
8328 || mode == GET_MODE (x)
8329 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8330 /* On a big endian machine if the value spans more than
8331 one register then this register holds the high part of
8332 it and we can't use it.
8334 ??? We should also compare with the high part of the
8336 && !(WORDS_BIG_ENDIAN
8337 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8338 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8339 GET_MODE_BITSIZE (GET_MODE (x))))))
8345 /* See whether a single set is a noop. SET is the set instruction we
8346 are should check, and INSN is the instruction from which it came. */
8349 reload_cse_noop_set_p (set, insn)
8351 rtx insn ATTRIBUTE_UNUSED;
8354 enum machine_mode dest_mode;
8358 src = SET_SRC (set);
8359 dest = SET_DEST (set);
8360 dest_mode = GET_MODE (dest);
8362 if (side_effects_p (src))
8365 dreg = true_regnum (dest);
8366 sreg = true_regnum (src);
8368 /* Check for setting a register to itself. In this case, we don't
8369 have to worry about REG_DEAD notes. */
8370 if (dreg >= 0 && dreg == sreg)
8376 /* Check for setting a register to itself. */
8380 /* Check for setting a register to a value which we already know
8381 is in the register. */
8382 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8385 /* Check for setting a register DREG to another register SREG
8386 where SREG is equal to a value which is already in DREG. */
8391 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8395 if (XEXP (x, 0) == 0)
8398 if (dest_mode == GET_MODE (x))
8400 else if (GET_MODE_BITSIZE (dest_mode)
8401 < GET_MODE_BITSIZE (GET_MODE (x)))
8402 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8407 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8415 else if (GET_CODE (dest) == MEM)
8417 /* Check for storing a register to memory when we know that the
8418 register is equivalent to the memory location. */
8420 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8421 && ! side_effects_p (dest))
8428 /* Try to simplify a single SET instruction. SET is the set pattern.
8429 INSN is the instruction it came from.
8430 This function only handles one case: if we set a register to a value
8431 which is not a register, we try to find that value in some other register
8432 and change the set into a register copy. */
8435 reload_cse_simplify_set (set, insn)
8441 enum machine_mode dest_mode;
8442 enum reg_class dclass;
8445 dreg = true_regnum (SET_DEST (set));
8449 src = SET_SRC (set);
8450 if (side_effects_p (src) || true_regnum (src) >= 0)
8453 dclass = REGNO_REG_CLASS (dreg);
8455 /* If memory loads are cheaper than register copies, don't change them. */
8456 if (GET_CODE (src) == MEM
8457 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8460 /* If the constant is cheaper than a register, don't change it. */
8461 if (CONSTANT_P (src)
8462 && rtx_cost (src, SET) < 2)
8465 dest_mode = GET_MODE (SET_DEST (set));
8466 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8469 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8470 && reload_cse_regno_equal_p (i, src, dest_mode))
8474 /* Pop back to the real obstacks while changing the insn. */
8477 validated = validate_change (insn, &SET_SRC (set),
8478 gen_rtx_REG (dest_mode, i), 1);
8480 /* Go back to the obstack we are using for temporary
8482 push_obstacks (&reload_obstack, &reload_obstack);
8491 /* Try to replace operands in INSN with equivalent values that are already
8492 in registers. This can be viewed as optional reloading.
8494 For each non-register operand in the insn, see if any hard regs are
8495 known to be equivalent to that operand. Record the alternatives which
8496 can accept these hard registers. Among all alternatives, select the
8497 ones which are better or equal to the one currently matching, where
8498 "better" is in terms of '?' and '!' constraints. Among the remaining
8499 alternatives, select the one which replaces most operands with
8503 reload_cse_simplify_operands (insn)
8508 const char *constraints[MAX_RECOG_OPERANDS];
8510 /* Vector recording how bad an alternative is. */
8511 int *alternative_reject;
8512 /* Vector recording how many registers can be introduced by choosing
8513 this alternative. */
8514 int *alternative_nregs;
8515 /* Array of vectors recording, for each operand and each alternative,
8516 which hard register to substitute, or -1 if the operand should be
8518 int *op_alt_regno[MAX_RECOG_OPERANDS];
8519 /* Array of alternatives, sorted in order of decreasing desirability. */
8520 int *alternative_order;
8521 rtx reg = gen_rtx_REG (VOIDmode, -1);
8523 extract_insn (insn);
8525 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8528 /* Figure out which alternative currently matches. */
8529 if (! constrain_operands (1))
8530 fatal_insn_not_found (insn);
8532 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8533 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8534 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8535 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8536 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8538 for (i = 0; i < recog_data.n_operands; i++)
8540 enum machine_mode mode;
8544 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8545 for (j = 0; j < recog_data.n_alternatives; j++)
8546 op_alt_regno[i][j] = -1;
8548 p = constraints[i] = recog_data.constraints[i];
8549 mode = recog_data.operand_mode[i];
8551 /* Add the reject values for each alternative given by the constraints
8552 for this operand. */
8560 alternative_reject[j] += 3;
8562 alternative_reject[j] += 300;
8565 /* We won't change operands which are already registers. We
8566 also don't want to modify output operands. */
8567 regno = true_regnum (recog_data.operand[i]);
8569 || constraints[i][0] == '='
8570 || constraints[i][0] == '+')
8573 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8575 int class = (int) NO_REGS;
8577 if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
8580 REGNO (reg) = regno;
8581 PUT_MODE (reg, mode);
8583 /* We found a register equal to this operand. Now look for all
8584 alternatives that can accept this register and have not been
8585 assigned a register they can use yet. */
8594 case '=': case '+': case '?':
8595 case '#': case '&': case '!':
8597 case '0': case '1': case '2': case '3': case '4':
8598 case '5': case '6': case '7': case '8': case '9':
8599 case 'm': case '<': case '>': case 'V': case 'o':
8600 case 'E': case 'F': case 'G': case 'H':
8601 case 's': case 'i': case 'n':
8602 case 'I': case 'J': case 'K': case 'L':
8603 case 'M': case 'N': case 'O': case 'P':
8604 #ifdef EXTRA_CONSTRAINT
8605 case 'Q': case 'R': case 'S': case 'T': case 'U':
8608 /* These don't say anything we care about. */
8612 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8617 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8620 case ',': case '\0':
8621 /* See if REGNO fits this alternative, and set it up as the
8622 replacement register if we don't have one for this
8623 alternative yet and the operand being replaced is not
8624 a cheap CONST_INT. */
8625 if (op_alt_regno[i][j] == -1
8626 && reg_fits_class_p (reg, class, 0, mode)
8627 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8628 || (rtx_cost (recog_data.operand[i], SET)
8629 > rtx_cost (reg, SET))))
8631 alternative_nregs[j]++;
8632 op_alt_regno[i][j] = regno;
8644 /* Record all alternatives which are better or equal to the currently
8645 matching one in the alternative_order array. */
8646 for (i = j = 0; i < recog_data.n_alternatives; i++)
8647 if (alternative_reject[i] <= alternative_reject[which_alternative])
8648 alternative_order[j++] = i;
8649 recog_data.n_alternatives = j;
8651 /* Sort it. Given a small number of alternatives, a dumb algorithm
8652 won't hurt too much. */
8653 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8656 int best_reject = alternative_reject[alternative_order[i]];
8657 int best_nregs = alternative_nregs[alternative_order[i]];
8660 for (j = i + 1; j < recog_data.n_alternatives; j++)
8662 int this_reject = alternative_reject[alternative_order[j]];
8663 int this_nregs = alternative_nregs[alternative_order[j]];
8665 if (this_reject < best_reject
8666 || (this_reject == best_reject && this_nregs < best_nregs))
8669 best_reject = this_reject;
8670 best_nregs = this_nregs;
8674 tmp = alternative_order[best];
8675 alternative_order[best] = alternative_order[i];
8676 alternative_order[i] = tmp;
8679 /* Substitute the operands as determined by op_alt_regno for the best
8681 j = alternative_order[0];
8683 /* Pop back to the real obstacks while changing the insn. */
8686 for (i = 0; i < recog_data.n_operands; i++)
8688 enum machine_mode mode = recog_data.operand_mode[i];
8689 if (op_alt_regno[i][j] == -1)
8692 validate_change (insn, recog_data.operand_loc[i],
8693 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8696 for (i = recog_data.n_dups - 1; i >= 0; i--)
8698 int op = recog_data.dup_num[i];
8699 enum machine_mode mode = recog_data.operand_mode[op];
8701 if (op_alt_regno[op][j] == -1)
8704 validate_change (insn, recog_data.dup_loc[i],
8705 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8708 /* Go back to the obstack we are using for temporary
8710 push_obstacks (&reload_obstack, &reload_obstack);
8712 return apply_change_group ();
8715 /* These two variables are used to pass information from
8716 reload_cse_record_set to reload_cse_check_clobber. */
8718 static int reload_cse_check_clobbered;
8719 static rtx reload_cse_check_src;
8721 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8722 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8723 second argument, which is passed by note_stores, is ignored. */
8726 reload_cse_check_clobber (dest, ignore, data)
8728 rtx ignore ATTRIBUTE_UNUSED;
8729 void *data ATTRIBUTE_UNUSED;
8731 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8732 reload_cse_check_clobbered = 1;
8735 /* Record the result of a SET instruction. SET is the set pattern.
8736 BODY is the pattern of the insn that it came from. */
8739 reload_cse_record_set (set, body)
8745 enum machine_mode dest_mode;
8747 dest = SET_DEST (set);
8748 src = SET_SRC (set);
8749 dreg = true_regnum (dest);
8750 sreg = true_regnum (src);
8751 dest_mode = GET_MODE (dest);
8753 /* Some machines don't define AUTO_INC_DEC, but they still use push
8754 instructions. We need to catch that case here in order to
8755 invalidate the stack pointer correctly. Note that invalidating
8756 the stack pointer is different from invalidating DEST. */
8758 while (GET_CODE (x) == SUBREG
8759 || GET_CODE (x) == ZERO_EXTRACT
8760 || GET_CODE (x) == SIGN_EXTRACT
8761 || GET_CODE (x) == STRICT_LOW_PART)
8763 if (push_operand (x, GET_MODE (x)))
8765 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL);
8766 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8770 /* We can only handle an assignment to a register, or a store of a
8771 register to a memory location. For other cases, we just clobber
8772 the destination. We also have to just clobber if there are side
8773 effects in SRC or DEST. */
8774 if ((dreg < 0 && GET_CODE (dest) != MEM)
8775 || side_effects_p (src)
8776 || side_effects_p (dest))
8778 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8783 /* We don't try to handle values involving CC, because it's a pain
8784 to keep track of when they have to be invalidated. */
8785 if (reg_mentioned_p (cc0_rtx, src)
8786 || reg_mentioned_p (cc0_rtx, dest))
8788 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8793 /* If BODY is a PARALLEL, then we need to see whether the source of
8794 SET is clobbered by some other instruction in the PARALLEL. */
8795 if (GET_CODE (body) == PARALLEL)
8799 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8803 x = XVECEXP (body, 0, i);
8807 reload_cse_check_clobbered = 0;
8808 reload_cse_check_src = src;
8809 note_stores (x, reload_cse_check_clobber, NULL);
8810 if (reload_cse_check_clobbered)
8812 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8822 /* This is an assignment to a register. Update the value we
8823 have stored for the register. */
8828 /* This is a copy from one register to another. Any values
8829 which were valid for SREG are now valid for DREG. If the
8830 mode changes, we use gen_lowpart_common to extract only
8831 the part of the value that is copied. */
8832 reg_values[dreg] = 0;
8833 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8837 if (XEXP (x, 0) == 0)
8839 if (dest_mode == GET_MODE (XEXP (x, 0)))
8841 else if (GET_MODE_BITSIZE (dest_mode)
8842 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8845 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8847 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
8852 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
8854 /* We've changed DREG, so invalidate any values held by other
8855 registers that depend upon it. */
8856 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8858 /* If this assignment changes more than one hard register,
8859 forget anything we know about the others. */
8860 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8861 reg_values[dreg + i] = 0;
8863 else if (GET_CODE (dest) == MEM)
8865 /* Invalidate conflicting memory locations. */
8866 reload_cse_invalidate_mem (dest);
8868 /* If we're storing a register to memory, add DEST to the list
8870 if (sreg >= 0 && ! side_effects_p (dest))
8871 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
8876 /* We should have bailed out earlier. */
8881 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8883 This code might also be useful when reload gave up on reg+reg addresssing
8884 because of clashes between the return register and INDEX_REG_CLASS. */
8886 /* The maximum number of uses of a register we can keep track of to
8887 replace them with reg+reg addressing. */
8888 #define RELOAD_COMBINE_MAX_USES 6
8890 /* INSN is the insn where a register has ben used, and USEP points to the
8891 location of the register within the rtl. */
8892 struct reg_use { rtx insn, *usep; };
8894 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8895 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8896 indicates where it becomes live again.
8897 Otherwise, USE_INDEX is the index of the last encountered use of the
8898 register (which is first among these we have seen since we scan backwards),
8899 OFFSET contains the constant offset that is added to the register in
8900 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8901 last, of these uses.
8902 STORE_RUID is always meaningful if we only want to use a value in a
8903 register in a different place: it denotes the next insn in the insn
8904 stream (i.e. the last ecountered) that sets or clobbers the register. */
8907 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8912 } reg_state[FIRST_PSEUDO_REGISTER];
8914 /* Reverse linear uid. This is increased in reload_combine while scanning
8915 the instructions from last to first. It is used to set last_label_ruid
8916 and the store_ruid / use_ruid fields in reg_state. */
8917 static int reload_combine_ruid;
8919 #define LABEL_LIVE(LABEL) \
8920 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8926 int first_index_reg = 1, last_index_reg = 0;
8928 int last_label_ruid;
8929 int min_labelno, n_labels;
8930 HARD_REG_SET ever_live_at_start, *label_live;
8932 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8933 reload has already used it where appropriate, so there is no use in
8934 trying to generate it now. */
8935 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8938 /* To avoid wasting too much time later searching for an index register,
8939 determine the minimum and maximum index register numbers. */
8940 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8942 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
8944 if (! last_index_reg)
8946 first_index_reg = i;
8949 /* If no index register is available, we can quit now. */
8950 if (first_index_reg > last_index_reg)
8953 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8954 information is a bit fuzzy immediately after reload, but it's
8955 still good enough to determine which registers are live at a jump
8957 min_labelno = get_first_label_num ();
8958 n_labels = max_label_num () - min_labelno;
8959 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8960 CLEAR_HARD_REG_SET (ever_live_at_start);
8961 for (i = n_basic_blocks - 1; i >= 0; i--)
8963 insn = BLOCK_HEAD (i);
8964 if (GET_CODE (insn) == CODE_LABEL)
8968 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
8969 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
8970 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8971 IOR_HARD_REG_SET (ever_live_at_start, live);
8975 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8976 last_label_ruid = reload_combine_ruid = 0;
8977 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8979 reg_state[i].store_ruid = reload_combine_ruid;
8981 reg_state[i].use_index = -1;
8983 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8986 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8990 /* We cannot do our optimization across labels. Invalidating all the use
8991 information we have would be costly, so we just note where the label
8992 is and then later disable any optimization that would cross it. */
8993 if (GET_CODE (insn) == CODE_LABEL)
8994 last_label_ruid = reload_combine_ruid;
8995 if (GET_CODE (insn) == BARRIER)
8997 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8998 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9000 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9002 reload_combine_ruid++;
9004 /* Look for (set (REGX) (CONST_INT))
9005 (set (REGX) (PLUS (REGX) (REGY)))
9007 ... (MEM (REGX)) ...
9009 (set (REGZ) (CONST_INT))
9011 ... (MEM (PLUS (REGZ) (REGY)))... .
9013 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9014 and that we know all uses of REGX before it dies. */
9015 set = single_set (insn);
9017 && GET_CODE (SET_DEST (set)) == REG
9018 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9019 GET_MODE (SET_DEST (set)))
9021 && GET_CODE (SET_SRC (set)) == PLUS
9022 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9023 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9024 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9026 rtx reg = SET_DEST (set);
9027 rtx plus = SET_SRC (set);
9028 rtx base = XEXP (plus, 1);
9029 rtx prev = prev_nonnote_insn (insn);
9030 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9031 int regno = REGNO (reg);
9032 rtx const_reg = NULL_RTX;
9033 rtx reg_sum = NULL_RTX;
9035 /* Now, we need an index register.
9036 We'll set index_reg to this index register, const_reg to the
9037 register that is to be loaded with the constant
9038 (denoted as REGZ in the substitution illustration above),
9039 and reg_sum to the register-register that we want to use to
9040 substitute uses of REG (typically in MEMs) with.
9041 First check REG and BASE for being index registers;
9042 we can use them even if they are not dead. */
9043 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9044 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9052 /* Otherwise, look for a free index register. Since we have
9053 checked above that neiter REG nor BASE are index registers,
9054 if we find anything at all, it will be different from these
9056 for (i = first_index_reg; i <= last_index_reg; i++)
9058 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9059 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9060 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9061 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9063 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9064 const_reg = index_reg;
9065 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9070 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9071 (REGY), i.e. BASE, is not clobbered before the last use we'll
9074 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9075 && rtx_equal_p (SET_DEST (prev_set), reg)
9076 && reg_state[regno].use_index >= 0
9077 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9082 /* Change destination register and - if necessary - the
9083 constant value in PREV, the constant loading instruction. */
9084 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9085 if (reg_state[regno].offset != const0_rtx)
9086 validate_change (prev,
9087 &SET_SRC (prev_set),
9088 GEN_INT (INTVAL (SET_SRC (prev_set))
9089 + INTVAL (reg_state[regno].offset)),
9091 /* Now for every use of REG that we have recorded, replace REG
9093 for (i = reg_state[regno].use_index;
9094 i < RELOAD_COMBINE_MAX_USES; i++)
9095 validate_change (reg_state[regno].reg_use[i].insn,
9096 reg_state[regno].reg_use[i].usep,
9099 if (apply_change_group ())
9103 /* Delete the reg-reg addition. */
9104 PUT_CODE (insn, NOTE);
9105 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9106 NOTE_SOURCE_FILE (insn) = 0;
9108 if (reg_state[regno].offset != const0_rtx)
9110 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9112 for (np = ®_NOTES (prev); *np; )
9114 if (REG_NOTE_KIND (*np) == REG_EQUAL
9115 || REG_NOTE_KIND (*np) == REG_EQUIV)
9116 *np = XEXP (*np, 1);
9118 np = &XEXP (*np, 1);
9121 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9122 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9127 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
9128 if (GET_CODE (insn) == CALL_INSN)
9132 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9134 if (call_used_regs[i])
9136 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9137 reg_state[i].store_ruid = reload_combine_ruid;
9140 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9141 link = XEXP (link, 1))
9143 rtx use = XEXP (link, 0);
9144 int regno = REGNO (XEXP (use, 0));
9145 if (GET_CODE (use) == CLOBBER)
9147 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9148 reg_state[regno].store_ruid = reload_combine_ruid;
9151 reg_state[regno].use_index = -1;
9154 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9156 /* Non-spill registers might be used at the call destination in
9157 some unknown fashion, so we have to mark the unknown use. */
9159 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9160 && JUMP_LABEL (insn))
9161 live = &LABEL_LIVE (JUMP_LABEL (insn));
9163 live = &ever_live_at_start;
9164 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9166 if (TEST_HARD_REG_BIT (*live, i))
9167 reg_state[i].use_index = -1;
9170 reload_combine_note_use (&PATTERN (insn), insn);
9171 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9173 if (REG_NOTE_KIND (note) == REG_INC
9174 && GET_CODE (XEXP (note, 0)) == REG)
9176 int regno = REGNO (XEXP (note, 0));
9178 reg_state[regno].store_ruid = reload_combine_ruid;
9179 reg_state[regno].use_index = -1;
9186 /* Check if DST is a register or a subreg of a register; if it is,
9187 update reg_state[regno].store_ruid and reg_state[regno].use_index
9188 accordingly. Called via note_stores from reload_combine. */
9190 reload_combine_note_store (dst, set, data)
9192 void *data ATTRIBUTE_UNUSED;
9196 enum machine_mode mode = GET_MODE (dst);
9198 if (GET_CODE (dst) == SUBREG)
9200 regno = SUBREG_WORD (dst);
9201 dst = SUBREG_REG (dst);
9203 if (GET_CODE (dst) != REG)
9205 regno += REGNO (dst);
9207 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9208 careful with registers / register parts that are not full words.
9210 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9211 if (GET_CODE (set) != SET
9212 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9213 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9214 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9216 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
9218 reg_state[i].use_index = -1;
9219 reg_state[i].store_ruid = reload_combine_ruid;
9224 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
9226 reg_state[i].store_ruid = reload_combine_ruid;
9227 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9232 /* XP points to a piece of rtl that has to be checked for any uses of
9234 *XP is the pattern of INSN, or a part of it.
9235 Called from reload_combine, and recursively by itself. */
9237 reload_combine_note_use (xp, insn)
9241 enum rtx_code code = x->code;
9244 rtx offset = const0_rtx; /* For the REG case below. */
9249 if (GET_CODE (SET_DEST (x)) == REG)
9251 reload_combine_note_use (&SET_SRC (x), insn);
9257 if (GET_CODE (SET_DEST (x)) == REG)
9262 /* We are interested in (plus (reg) (const_int)) . */
9263 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9265 offset = XEXP (x, 1);
9270 int regno = REGNO (x);
9273 /* Some spurious USEs of pseudo registers might remain.
9274 Just ignore them. */
9275 if (regno >= FIRST_PSEUDO_REGISTER)
9278 /* If this register is already used in some unknown fashion, we
9280 If we decrement the index from zero to -1, we can't store more
9281 uses, so this register becomes used in an unknown fashion. */
9282 use_index = --reg_state[regno].use_index;
9286 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9288 /* We have found another use for a register that is already
9289 used later. Check if the offsets match; if not, mark the
9290 register as used in an unknown fashion. */
9291 if (! rtx_equal_p (offset, reg_state[regno].offset))
9293 reg_state[regno].use_index = -1;
9299 /* This is the first use of this register we have seen since we
9300 marked it as dead. */
9301 reg_state[regno].offset = offset;
9302 reg_state[regno].use_ruid = reload_combine_ruid;
9304 reg_state[regno].reg_use[use_index].insn = insn;
9305 reg_state[regno].reg_use[use_index].usep = xp;
9313 /* Recursively process the components of X. */
9314 fmt = GET_RTX_FORMAT (code);
9315 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9318 reload_combine_note_use (&XEXP (x, i), insn);
9319 else if (fmt[i] == 'E')
9321 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9322 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9327 /* See if we can reduce the cost of a constant by replacing a move with
9329 /* We cannot do our optimization across labels. Invalidating all the
9330 information about register contents we have would be costly, so we
9331 use last_label_luid (local variable of reload_cse_move2add) to note
9332 where the label is and then later disable any optimization that would
9334 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9335 reg_set_luid[n] is larger than last_label_luid[n] . */
9336 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9337 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9338 reg_mode[n] to be valid.
9339 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9340 has been set to reg_offset[n] in mode reg_mode[n] .
9341 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9342 register n has been set to the sum of reg_offset[n] and register
9343 reg_base_reg[n], calculated in mode reg_mode[n] . */
9344 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9345 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9346 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9347 /* move2add_luid is linearily increased while scanning the instructions
9348 from first to last. It is used to set reg_set_luid in
9349 reload_cse_move2add and move2add_note_store. */
9350 static int move2add_luid;
9352 /* Generate a CONST_INT and force it in the range of MODE. */
9354 gen_mode_int (mode, value)
9355 enum machine_mode mode;
9356 HOST_WIDE_INT value;
9358 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9359 int width = GET_MODE_BITSIZE (mode);
9361 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9363 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9364 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9365 cval |= (HOST_WIDE_INT) -1 << width;
9367 return GEN_INT (cval);
9371 reload_cse_move2add (first)
9376 int last_label_luid;
9378 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9379 reg_set_luid[i] = 0;
9381 last_label_luid = 0;
9383 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9387 if (GET_CODE (insn) == CODE_LABEL)
9388 last_label_luid = move2add_luid;
9389 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9391 pat = PATTERN (insn);
9392 /* For simplicity, we only perform this optimization on
9393 straightforward SETs. */
9394 if (GET_CODE (pat) == SET
9395 && GET_CODE (SET_DEST (pat)) == REG)
9397 rtx reg = SET_DEST (pat);
9398 int regno = REGNO (reg);
9399 rtx src = SET_SRC (pat);
9401 /* Check if we have valid information on the contents of this
9402 register in the mode of REG. */
9403 /* ??? We don't know how zero / sign extension is handled, hence
9404 we can't go from a narrower to a wider mode. */
9405 if (reg_set_luid[regno] > last_label_luid
9406 && (GET_MODE_SIZE (GET_MODE (reg))
9407 <= GET_MODE_SIZE (reg_mode[regno]))
9408 && GET_CODE (reg_offset[regno]) == CONST_INT)
9410 /* Try to transform (set (REGX) (CONST_INT A))
9412 (set (REGX) (CONST_INT B))
9414 (set (REGX) (CONST_INT A))
9416 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9418 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9422 = gen_mode_int (GET_MODE (reg),
9423 INTVAL (src) - INTVAL (reg_offset[regno]));
9424 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9425 use (set (reg) (reg)) instead.
9426 We don't delete this insn, nor do we convert it into a
9427 note, to avoid losing register notes or the return
9428 value flag. jump2 already knowns how to get rid of
9430 if (new_src == const0_rtx)
9431 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9432 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9433 && have_add2_insn (GET_MODE (reg)))
9434 success = validate_change (insn, &PATTERN (insn),
9435 gen_add2_insn (reg, new_src), 0);
9436 reg_set_luid[regno] = move2add_luid;
9437 reg_mode[regno] = GET_MODE (reg);
9438 reg_offset[regno] = src;
9442 /* Try to transform (set (REGX) (REGY))
9443 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9446 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9449 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9451 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9452 else if (GET_CODE (src) == REG
9453 && reg_base_reg[regno] == REGNO (src)
9454 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9456 rtx next = next_nonnote_insn (insn);
9459 set = single_set (next);
9462 && SET_DEST (set) == reg
9463 && GET_CODE (SET_SRC (set)) == PLUS
9464 && XEXP (SET_SRC (set), 0) == reg
9465 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9467 rtx src3 = XEXP (SET_SRC (set), 1);
9469 = gen_mode_int (GET_MODE (reg),
9471 - INTVAL (reg_offset[regno]));
9474 if (new_src == const0_rtx)
9475 /* See above why we create (set (reg) (reg)) here. */
9477 = validate_change (next, &SET_SRC (set), reg, 0);
9478 else if ((rtx_cost (new_src, PLUS)
9479 < 2 + rtx_cost (src3, SET))
9480 && have_add2_insn (GET_MODE (reg)))
9482 = validate_change (next, &PATTERN (next),
9483 gen_add2_insn (reg, new_src), 0);
9486 /* INSN might be the first insn in a basic block
9487 if the preceding insn is a conditional jump
9488 or a possible-throwing call. */
9489 PUT_CODE (insn, NOTE);
9490 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9491 NOTE_SOURCE_FILE (insn) = 0;
9494 reg_set_luid[regno] = move2add_luid;
9495 reg_mode[regno] = GET_MODE (reg);
9496 reg_offset[regno] = src3;
9503 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9505 if (REG_NOTE_KIND (note) == REG_INC
9506 && GET_CODE (XEXP (note, 0)) == REG)
9508 /* Indicate that this register has been recently written to,
9509 but the exact contents are not available. */
9510 int regno = REGNO (XEXP (note, 0));
9511 if (regno < FIRST_PSEUDO_REGISTER)
9513 reg_set_luid[regno] = move2add_luid;
9514 reg_offset[regno] = note;
9518 note_stores (PATTERN (insn), move2add_note_store, NULL);
9519 /* If this is a CALL_INSN, all call used registers are stored with
9521 if (GET_CODE (insn) == CALL_INSN)
9523 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9525 if (call_used_regs[i])
9527 reg_set_luid[i] = move2add_luid;
9528 reg_offset[i] = insn; /* Invalidate contents. */
9535 /* SET is a SET or CLOBBER that sets DST.
9536 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9537 Called from reload_cse_move2add via note_stores. */
9539 move2add_note_store (dst, set, data)
9541 void *data ATTRIBUTE_UNUSED;
9546 enum machine_mode mode = GET_MODE (dst);
9547 if (GET_CODE (dst) == SUBREG)
9549 regno = SUBREG_WORD (dst);
9550 dst = SUBREG_REG (dst);
9552 if (GET_CODE (dst) != REG)
9555 regno += REGNO (dst);
9557 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9558 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9559 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9560 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9562 rtx src = SET_SRC (set);
9564 reg_mode[regno] = mode;
9565 switch (GET_CODE (src))
9569 rtx src0 = XEXP (src, 0);
9570 if (GET_CODE (src0) == REG)
9572 if (REGNO (src0) != regno
9573 || reg_offset[regno] != const0_rtx)
9575 reg_base_reg[regno] = REGNO (src0);
9576 reg_set_luid[regno] = move2add_luid;
9578 reg_offset[regno] = XEXP (src, 1);
9581 reg_set_luid[regno] = move2add_luid;
9582 reg_offset[regno] = set; /* Invalidate contents. */
9587 reg_base_reg[regno] = REGNO (SET_SRC (set));
9588 reg_offset[regno] = const0_rtx;
9589 reg_set_luid[regno] = move2add_luid;
9593 reg_base_reg[regno] = -1;
9594 reg_offset[regno] = SET_SRC (set);
9595 reg_set_luid[regno] = move2add_luid;
9601 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9603 /* Indicate that this register has been recently written to,
9604 but the exact contents are not available. */
9605 reg_set_luid[i] = move2add_luid;
9606 reg_offset[i] = dst;
9613 add_auto_inc_notes (insn, x)
9617 enum rtx_code code = GET_CODE (x);
9621 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9624 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9628 /* Scan all the operand sub-expressions. */
9629 fmt = GET_RTX_FORMAT (code);
9630 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9633 add_auto_inc_notes (insn, XEXP (x, i));
9634 else if (fmt[i] == 'E')
9635 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9636 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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