1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress = 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
260 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
293 static struct elim_table
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 int initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Non-zero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 int offset; /* Current offset between the two regs. */
302 int max_offset; /* Maximum offset between the two regs. */
303 int previous_offset; /* Offset at end of previous insn. */
304 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
305 rtx from_rtx; /* REG rtx for the register to be eliminated.
306 We cannot simply compare the number since
307 we might then spuriously replace a hard
308 register corresponding to a pseudo
309 assigned to the reg to be eliminated. */
310 rtx to_rtx; /* REG rtx for the replacement. */
313 /* If a set of eliminable registers was specified, define the table from it.
314 Otherwise, default to the normal case of the frame pointer being
315 replaced by the stack pointer. */
317 #ifdef ELIMINABLE_REGS
320 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
323 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
325 /* Record the number of pending eliminations that have an offset not equal
326 to their initial offset. If non-zero, we use a new copy of each
327 replacement result in any insns encountered. */
328 int num_not_at_initial_offset;
330 /* Count the number of registers that we may be able to eliminate. */
331 static int num_eliminable;
333 /* For each label, we record the offset of each elimination. If we reach
334 a label by more than one path and an offset differs, we cannot do the
335 elimination. This information is indexed by the number of the label.
336 The first table is an array of flags that records whether we have yet
337 encountered a label and the second table is an array of arrays, one
338 entry in the latter array for each elimination. */
340 static char *offsets_known_at;
341 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
343 /* Number of labels in the current function. */
345 static int num_labels;
347 struct hard_reg_n_uses
353 static void maybe_fix_stack_asms PROTO((void));
354 static void calculate_needs_all_insns PROTO((int));
355 static void calculate_needs PROTO((struct insn_chain *));
356 static void find_reload_regs PROTO((struct insn_chain *chain,
358 static void find_tworeg_group PROTO((struct insn_chain *, int,
360 static void find_group PROTO((struct insn_chain *, int,
362 static int possible_group_p PROTO((struct insn_chain *, int));
363 static void count_possible_groups PROTO((struct insn_chain *, int));
364 static int modes_equiv_for_class_p PROTO((enum machine_mode,
367 static void delete_caller_save_insns PROTO((void));
369 static void spill_failure PROTO((rtx));
370 static void new_spill_reg PROTO((struct insn_chain *, int, int,
372 static void maybe_mark_pseudo_spilled PROTO((int));
373 static void delete_dead_insn PROTO((rtx));
374 static void alter_reg PROTO((int, int));
375 static void set_label_offsets PROTO((rtx, rtx, int));
376 static int eliminate_regs_in_insn PROTO((rtx, int));
377 static void update_eliminable_offsets PROTO((void));
378 static void mark_not_eliminable PROTO((rtx, rtx));
379 static void set_initial_elim_offsets PROTO((void));
380 static void init_elim_table PROTO((void));
381 static void update_eliminables PROTO((HARD_REG_SET *));
382 static void spill_hard_reg PROTO((int, FILE *, int));
383 static int finish_spills PROTO((int, FILE *));
384 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
385 static void scan_paradoxical_subregs PROTO((rtx));
386 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
387 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
388 static void order_regs_for_reload PROTO((struct insn_chain *));
389 static void reload_as_needed PROTO((int));
390 static void forget_old_reloads_1 PROTO((rtx, rtx));
391 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
392 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
394 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
396 static int reload_reg_free_p PROTO((int, int, enum reload_type));
397 static int reload_reg_free_before_p PROTO((int, int, enum reload_type, int));
398 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int));
399 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
400 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
402 static void choose_reload_regs PROTO((struct insn_chain *));
403 static void merge_assigned_reloads PROTO((rtx));
404 static void emit_reload_insns PROTO((struct insn_chain *));
405 static void delete_output_reload PROTO((rtx, int, int));
406 static void delete_address_reloads PROTO((rtx, rtx));
407 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
408 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
409 static int constraint_accepts_reg_p PROTO((char *, rtx));
410 static void reload_cse_regs_1 PROTO((rtx));
411 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
412 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
413 static void reload_cse_invalidate_mem PROTO((rtx));
414 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
415 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
416 static int reload_cse_noop_set_p PROTO((rtx, rtx));
417 static int reload_cse_simplify_set PROTO((rtx, rtx));
418 static int reload_cse_simplify_operands PROTO((rtx));
419 static void reload_cse_check_clobber PROTO((rtx, rtx));
420 static void reload_cse_record_set PROTO((rtx, rtx));
421 static void reload_combine PROTO((void));
422 static void reload_combine_note_use PROTO((rtx *, rtx));
423 static void reload_combine_note_store PROTO((rtx, rtx));
424 static void reload_cse_move2add PROTO((rtx));
425 static void move2add_note_store PROTO((rtx, rtx));
427 /* Initialize the reload pass once per compilation. */
434 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
435 Set spill_indirect_levels to the number of levels such addressing is
436 permitted, zero if it is not permitted at all. */
439 = gen_rtx_MEM (Pmode,
441 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
443 spill_indirect_levels = 0;
445 while (memory_address_p (QImode, tem))
447 spill_indirect_levels++;
448 tem = gen_rtx_MEM (Pmode, tem);
451 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
453 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
454 indirect_symref_ok = memory_address_p (QImode, tem);
456 /* See if reg+reg is a valid (and offsettable) address. */
458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
460 tem = gen_rtx_PLUS (Pmode,
461 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
462 gen_rtx_REG (Pmode, i));
463 /* This way, we make sure that reg+reg is an offsettable address. */
464 tem = plus_constant (tem, 4);
466 if (memory_address_p (QImode, tem))
468 double_reg_address_ok = 1;
473 /* Initialize obstack for our rtl allocation. */
474 gcc_obstack_init (&reload_obstack);
475 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
478 /* List of insn chains that are currently unused. */
479 static struct insn_chain *unused_insn_chains = 0;
481 /* Allocate an empty insn_chain structure. */
485 struct insn_chain *c;
487 if (unused_insn_chains == 0)
489 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
490 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
491 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
495 c = unused_insn_chains;
496 unused_insn_chains = c->next;
498 c->is_caller_save_insn = 0;
499 c->need_operand_change = 0;
505 /* Small utility function to set all regs in hard reg set TO which are
506 allocated to pseudos in regset FROM. */
508 compute_use_by_pseudos (to, from)
513 EXECUTE_IF_SET_IN_REG_SET
514 (from, FIRST_PSEUDO_REGISTER, regno,
516 int r = reg_renumber[regno];
520 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
522 SET_HARD_REG_BIT (*to, r + nregs);
526 /* Global variables used by reload and its subroutines. */
528 /* Set during calculate_needs if an insn needs register elimination. */
529 static int something_needs_elimination;
530 /* Set during calculate_needs if an insn needs an operand changed. */
531 int something_needs_operands_changed;
533 /* Nonzero means we couldn't get enough spill regs. */
536 /* Main entry point for the reload pass.
538 FIRST is the first insn of the function being compiled.
540 GLOBAL nonzero means we were called from global_alloc
541 and should attempt to reallocate any pseudoregs that we
542 displace from hard regs we will use for reloads.
543 If GLOBAL is zero, we do not have enough information to do that,
544 so any pseudo reg that is spilled must go to the stack.
546 DUMPFILE is the global-reg debugging dump file stream, or 0.
547 If it is nonzero, messages are written to it to describe
548 which registers are seized as reload regs, which pseudo regs
549 are spilled from them, and where the pseudo regs are reallocated to.
551 Return value is nonzero if reload failed
552 and we must not do any more for this function. */
555 reload (first, global, dumpfile)
562 register struct elim_table *ep;
564 /* The two pointers used to track the true location of the memory used
565 for label offsets. */
566 char *real_known_ptr = NULL_PTR;
567 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
569 /* Make sure even insns with volatile mem refs are recognizable. */
574 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
576 /* Make sure that the last insn in the chain
577 is not something that needs reloading. */
578 emit_note (NULL_PTR, NOTE_INSN_DELETED);
580 /* Enable find_equiv_reg to distinguish insns made by reload. */
581 reload_first_uid = get_max_uid ();
583 #ifdef SECONDARY_MEMORY_NEEDED
584 /* Initialize the secondary memory table. */
585 clear_secondary_mem ();
588 /* We don't have a stack slot for any spill reg yet. */
589 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
590 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
592 /* Initialize the save area information for caller-save, in case some
596 /* Compute which hard registers are now in use
597 as homes for pseudo registers.
598 This is done here rather than (eg) in global_alloc
599 because this point is reached even if not optimizing. */
600 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
603 /* A function that receives a nonlocal goto must save all call-saved
605 if (current_function_has_nonlocal_label)
606 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
608 if (! call_used_regs[i] && ! fixed_regs[i])
609 regs_ever_live[i] = 1;
612 /* Find all the pseudo registers that didn't get hard regs
613 but do have known equivalent constants or memory slots.
614 These include parameters (known equivalent to parameter slots)
615 and cse'd or loop-moved constant memory addresses.
617 Record constant equivalents in reg_equiv_constant
618 so they will be substituted by find_reloads.
619 Record memory equivalents in reg_mem_equiv so they can
620 be substituted eventually by altering the REG-rtx's. */
622 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
623 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
624 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
625 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
626 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
627 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
628 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
629 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
630 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
631 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
632 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
633 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
634 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
635 bcopy (reg_renumber, reg_old_renumber, max_regno * sizeof (short));
636 pseudo_forbidden_regs
637 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
639 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
641 CLEAR_HARD_REG_SET (bad_spill_regs_global);
642 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
644 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
645 Also find all paradoxical subregs and find largest such for each pseudo.
646 On machines with small register classes, record hard registers that
647 are used for user variables. These can never be used for spills.
648 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
649 caller-saved registers must be marked live. */
651 for (insn = first; insn; insn = NEXT_INSN (insn))
653 rtx set = single_set (insn);
655 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
656 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
657 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
658 if (! call_used_regs[i])
659 regs_ever_live[i] = 1;
661 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
663 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
665 #ifdef LEGITIMATE_PIC_OPERAND_P
666 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
667 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
671 rtx x = XEXP (note, 0);
672 i = REGNO (SET_DEST (set));
673 if (i > LAST_VIRTUAL_REGISTER)
675 if (GET_CODE (x) == MEM)
677 /* If the operand is a PLUS, the MEM may be shared,
678 so make sure we have an unshared copy here. */
679 if (GET_CODE (XEXP (x, 0)) == PLUS)
682 reg_equiv_memory_loc[i] = x;
684 else if (CONSTANT_P (x))
686 if (LEGITIMATE_CONSTANT_P (x))
687 reg_equiv_constant[i] = x;
689 reg_equiv_memory_loc[i]
690 = force_const_mem (GET_MODE (SET_DEST (set)), x);
695 /* If this register is being made equivalent to a MEM
696 and the MEM is not SET_SRC, the equivalencing insn
697 is one with the MEM as a SET_DEST and it occurs later.
698 So don't mark this insn now. */
699 if (GET_CODE (x) != MEM
700 || rtx_equal_p (SET_SRC (set), x))
701 reg_equiv_init[i] = insn;
706 /* If this insn is setting a MEM from a register equivalent to it,
707 this is the equivalencing insn. */
708 else if (set && GET_CODE (SET_DEST (set)) == MEM
709 && GET_CODE (SET_SRC (set)) == REG
710 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
711 && rtx_equal_p (SET_DEST (set),
712 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
713 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
715 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
716 scan_paradoxical_subregs (PATTERN (insn));
721 num_labels = max_label_num () - get_first_label_num ();
723 /* Allocate the tables used to store offset information at labels. */
724 /* We used to use alloca here, but the size of what it would try to
725 allocate would occasionally cause it to exceed the stack limit and
726 cause a core dump. */
727 real_known_ptr = xmalloc (num_labels);
729 = (int (*)[NUM_ELIMINABLE_REGS])
730 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
732 offsets_known_at = real_known_ptr - get_first_label_num ();
734 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
736 /* Alter each pseudo-reg rtx to contain its hard reg number.
737 Assign stack slots to the pseudos that lack hard regs or equivalents.
738 Do not touch virtual registers. */
740 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
743 /* If we have some registers we think can be eliminated, scan all insns to
744 see if there is an insn that sets one of these registers to something
745 other than itself plus a constant. If so, the register cannot be
746 eliminated. Doing this scan here eliminates an extra pass through the
747 main reload loop in the most common case where register elimination
749 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
750 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
751 || GET_CODE (insn) == CALL_INSN)
752 note_stores (PATTERN (insn), mark_not_eliminable);
754 #ifndef REGISTER_CONSTRAINTS
755 /* If all the pseudo regs have hard regs,
756 except for those that are never referenced,
757 we know that no reloads are needed. */
758 /* But that is not true if there are register constraints, since
759 in that case some pseudos might be in the wrong kind of hard reg. */
761 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
762 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
765 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
767 free (real_known_ptr);
769 free (reg_equiv_constant);
770 free (reg_equiv_memory_loc);
771 free (reg_equiv_mem);
772 free (reg_equiv_init);
773 free (reg_equiv_address);
774 free (reg_max_ref_width);
775 free (reg_old_renumber);
776 free (pseudo_previous_regs);
777 free (pseudo_forbidden_regs);
782 maybe_fix_stack_asms ();
784 insns_need_reload = 0;
785 something_needs_elimination = 0;
787 /* Initialize to -1, which means take the first spill register. */
790 spilled_pseudos = ALLOCA_REG_SET ();
792 /* Spill any hard regs that we know we can't eliminate. */
793 CLEAR_HARD_REG_SET (used_spill_regs);
794 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
795 if (! ep->can_eliminate)
796 spill_hard_reg (ep->from, dumpfile, 1);
798 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
799 if (frame_pointer_needed)
800 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
802 finish_spills (global, dumpfile);
804 /* From now on, we need to emit any moves without making new pseudos. */
805 reload_in_progress = 1;
807 /* This loop scans the entire function each go-round
808 and repeats until one repetition spills no additional hard regs. */
811 int something_changed;
813 struct insn_chain *chain;
815 HOST_WIDE_INT starting_frame_size;
817 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
818 here because the stack size may be a part of the offset computation
819 for register elimination, and there might have been new stack slots
820 created in the last iteration of this loop. */
821 assign_stack_local (BLKmode, 0, 0);
823 starting_frame_size = get_frame_size ();
825 set_initial_elim_offsets ();
827 /* For each pseudo register that has an equivalent location defined,
828 try to eliminate any eliminable registers (such as the frame pointer)
829 assuming initial offsets for the replacement register, which
832 If the resulting location is directly addressable, substitute
833 the MEM we just got directly for the old REG.
835 If it is not addressable but is a constant or the sum of a hard reg
836 and constant, it is probably not addressable because the constant is
837 out of range, in that case record the address; we will generate
838 hairy code to compute the address in a register each time it is
839 needed. Similarly if it is a hard register, but one that is not
840 valid as an address register.
842 If the location is not addressable, but does not have one of the
843 above forms, assign a stack slot. We have to do this to avoid the
844 potential of producing lots of reloads if, e.g., a location involves
845 a pseudo that didn't get a hard register and has an equivalent memory
846 location that also involves a pseudo that didn't get a hard register.
848 Perhaps at some point we will improve reload_when_needed handling
849 so this problem goes away. But that's very hairy. */
851 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
852 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
854 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
856 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
858 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
859 else if (CONSTANT_P (XEXP (x, 0))
860 || (GET_CODE (XEXP (x, 0)) == REG
861 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
862 || (GET_CODE (XEXP (x, 0)) == PLUS
863 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
864 && (REGNO (XEXP (XEXP (x, 0), 0))
865 < FIRST_PSEUDO_REGISTER)
866 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
867 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
870 /* Make a new stack slot. Then indicate that something
871 changed so we go back and recompute offsets for
872 eliminable registers because the allocation of memory
873 below might change some offset. reg_equiv_{mem,address}
874 will be set up for this pseudo on the next pass around
876 reg_equiv_memory_loc[i] = 0;
877 reg_equiv_init[i] = 0;
882 if (caller_save_needed)
885 /* If we allocated another stack slot, redo elimination bookkeeping. */
886 if (starting_frame_size != get_frame_size ())
889 if (caller_save_needed)
891 save_call_clobbered_regs ();
892 /* That might have allocated new insn_chain structures. */
893 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
896 calculate_needs_all_insns (global);
898 CLEAR_REG_SET (spilled_pseudos);
901 something_changed = 0;
903 /* If we allocated any new memory locations, make another pass
904 since it might have changed elimination offsets. */
905 if (starting_frame_size != get_frame_size ())
906 something_changed = 1;
909 HARD_REG_SET to_spill;
910 CLEAR_HARD_REG_SET (to_spill);
911 update_eliminables (&to_spill);
912 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
913 if (TEST_HARD_REG_BIT (to_spill, i))
915 spill_hard_reg (i, dumpfile, 1);
920 CLEAR_HARD_REG_SET (used_spill_regs);
921 /* Try to satisfy the needs for each insn. */
922 for (chain = insns_need_reload; chain != 0;
923 chain = chain->next_need_reload)
924 find_reload_regs (chain, dumpfile);
929 if (insns_need_reload != 0 || did_spill)
930 something_changed |= finish_spills (global, dumpfile);
932 if (! something_changed)
935 if (caller_save_needed)
936 delete_caller_save_insns ();
939 /* If global-alloc was run, notify it of any register eliminations we have
942 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
943 if (ep->can_eliminate)
944 mark_elimination (ep->from, ep->to);
946 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
947 If that insn didn't set the register (i.e., it copied the register to
948 memory), just delete that insn instead of the equivalencing insn plus
949 anything now dead. If we call delete_dead_insn on that insn, we may
950 delete the insn that actually sets the register if the register die
951 there and that is incorrect. */
953 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
954 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
955 && GET_CODE (reg_equiv_init[i]) != NOTE)
957 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
958 delete_dead_insn (reg_equiv_init[i]);
961 PUT_CODE (reg_equiv_init[i], NOTE);
962 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
963 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
967 /* Use the reload registers where necessary
968 by generating move instructions to move the must-be-register
969 values into or out of the reload registers. */
971 if (insns_need_reload != 0 || something_needs_elimination
972 || something_needs_operands_changed)
973 reload_as_needed (global);
975 /* If we were able to eliminate the frame pointer, show that it is no
976 longer live at the start of any basic block. If it ls live by
977 virtue of being in a pseudo, that pseudo will be marked live
978 and hence the frame pointer will be known to be live via that
981 if (! frame_pointer_needed)
982 for (i = 0; i < n_basic_blocks; i++)
983 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
984 HARD_FRAME_POINTER_REGNUM);
986 /* Come here (with failure set nonzero) if we can't get enough spill regs
987 and we decide not to abort about it. */
990 reload_in_progress = 0;
992 /* Now eliminate all pseudo regs by modifying them into
993 their equivalent memory references.
994 The REG-rtx's for the pseudos are modified in place,
995 so all insns that used to refer to them now refer to memory.
997 For a reg that has a reg_equiv_address, all those insns
998 were changed by reloading so that no insns refer to it any longer;
999 but the DECL_RTL of a variable decl may refer to it,
1000 and if so this causes the debugging info to mention the variable. */
1002 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1006 int is_readonly = 0;
1008 if (reg_equiv_memory_loc[i])
1010 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1011 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1014 if (reg_equiv_mem[i])
1015 addr = XEXP (reg_equiv_mem[i], 0);
1017 if (reg_equiv_address[i])
1018 addr = reg_equiv_address[i];
1022 if (reg_renumber[i] < 0)
1024 rtx reg = regno_reg_rtx[i];
1025 XEXP (reg, 0) = addr;
1026 REG_USERVAR_P (reg) = 0;
1027 RTX_UNCHANGING_P (reg) = is_readonly;
1028 MEM_IN_STRUCT_P (reg) = in_struct;
1029 /* We have no alias information about this newly created
1031 MEM_ALIAS_SET (reg) = 0;
1032 PUT_CODE (reg, MEM);
1034 else if (reg_equiv_mem[i])
1035 XEXP (reg_equiv_mem[i], 0) = addr;
1039 /* Make a pass over all the insns and delete all USEs which we inserted
1040 only to tag a REG_EQUAL note on them. Also remove all REG_DEAD and
1041 REG_UNUSED notes. */
1043 for (insn = first; insn; insn = NEXT_INSN (insn))
1044 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1048 if (GET_CODE (PATTERN (insn)) == USE
1049 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1051 PUT_CODE (insn, NOTE);
1052 NOTE_SOURCE_FILE (insn) = 0;
1053 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1057 pnote = ®_NOTES (insn);
1060 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1061 || REG_NOTE_KIND (*pnote) == REG_UNUSED)
1062 *pnote = XEXP (*pnote, 1);
1064 pnote = &XEXP (*pnote, 1);
1068 /* If we are doing stack checking, give a warning if this function's
1069 frame size is larger than we expect. */
1070 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1072 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1074 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1075 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1076 size += UNITS_PER_WORD;
1078 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1079 warning ("frame size too large for reliable stack checking");
1082 /* Indicate that we no longer have known memory locations or constants. */
1083 if (reg_equiv_constant)
1084 free (reg_equiv_constant);
1085 reg_equiv_constant = 0;
1086 if (reg_equiv_memory_loc)
1087 free (reg_equiv_memory_loc);
1088 reg_equiv_memory_loc = 0;
1091 free (real_known_ptr);
1095 free (reg_equiv_mem);
1096 free (reg_equiv_init);
1097 free (reg_equiv_address);
1098 free (reg_max_ref_width);
1099 free (reg_old_renumber);
1100 free (pseudo_previous_regs);
1101 free (pseudo_forbidden_regs);
1103 FREE_REG_SET (spilled_pseudos);
1105 CLEAR_HARD_REG_SET (used_spill_regs);
1106 for (i = 0; i < n_spills; i++)
1107 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1109 /* Free all the insn_chain structures at once. */
1110 obstack_free (&reload_obstack, reload_startobj);
1111 unused_insn_chains = 0;
1116 /* Yet another special case. Unfortunately, reg-stack forces people to
1117 write incorrect clobbers in asm statements. These clobbers must not
1118 cause the register to appear in bad_spill_regs, otherwise we'll call
1119 fatal_insn later. We clear the corresponding regnos in the live
1120 register sets to avoid this.
1121 The whole thing is rather sick, I'm afraid. */
1123 maybe_fix_stack_asms ()
1126 char *constraints[MAX_RECOG_OPERANDS];
1127 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1128 struct insn_chain *chain;
1130 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1133 HARD_REG_SET clobbered, allowed;
1136 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1137 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1139 pat = PATTERN (chain->insn);
1140 if (GET_CODE (pat) != PARALLEL)
1143 CLEAR_HARD_REG_SET (clobbered);
1144 CLEAR_HARD_REG_SET (allowed);
1146 /* First, make a mask of all stack regs that are clobbered. */
1147 for (i = 0; i < XVECLEN (pat, 0); i++)
1149 rtx t = XVECEXP (pat, 0, i);
1150 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1151 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1154 /* Get the operand values and constraints out of the insn. */
1155 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1156 constraints, operand_mode);
1158 /* For every operand, see what registers are allowed. */
1159 for (i = 0; i < noperands; i++)
1161 char *p = constraints[i];
1162 /* For every alternative, we compute the class of registers allowed
1163 for reloading in CLS, and merge its contents into the reg set
1165 int cls = (int) NO_REGS;
1171 if (c == '\0' || c == ',' || c == '#')
1173 /* End of one alternative - mark the regs in the current
1174 class, and reset the class. */
1175 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1180 } while (c != '\0' && c != ',');
1188 case '=': case '+': case '*': case '%': case '?': case '!':
1189 case '0': case '1': case '2': case '3': case '4': case 'm':
1190 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1191 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1192 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1194 #ifdef EXTRA_CONSTRAINT
1195 case 'Q': case 'R': case 'S': case 'T': case 'U':
1200 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1205 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1209 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1214 /* Those of the registers which are clobbered, but allowed by the
1215 constraints, must be usable as reload registers. So clear them
1216 out of the life information. */
1217 AND_HARD_REG_SET (allowed, clobbered);
1218 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1219 if (TEST_HARD_REG_BIT (allowed, i))
1221 CLEAR_REGNO_REG_SET (chain->live_before, i);
1222 CLEAR_REGNO_REG_SET (chain->live_after, i);
1230 /* Walk the chain of insns, and determine for each whether it needs reloads
1231 and/or eliminations. Build the corresponding insns_need_reload list, and
1232 set something_needs_elimination as appropriate. */
1234 calculate_needs_all_insns (global)
1237 struct insn_chain **pprev_reload = &insns_need_reload;
1238 struct insn_chain **pchain;
1240 something_needs_elimination = 0;
1242 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1245 struct insn_chain *chain;
1250 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1251 include REG_LABEL), we need to see what effects this has on the
1252 known offsets at labels. */
1254 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1255 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1256 && REG_NOTES (insn) != 0))
1257 set_label_offsets (insn, insn, 0);
1259 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1261 rtx old_body = PATTERN (insn);
1262 int old_code = INSN_CODE (insn);
1263 rtx old_notes = REG_NOTES (insn);
1264 int did_elimination = 0;
1265 int operands_changed = 0;
1267 /* If needed, eliminate any eliminable registers. */
1269 did_elimination = eliminate_regs_in_insn (insn, 0);
1271 /* Analyze the instruction. */
1272 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1273 global, spill_reg_order);
1275 /* If a no-op set needs more than one reload, this is likely
1276 to be something that needs input address reloads. We
1277 can't get rid of this cleanly later, and it is of no use
1278 anyway, so discard it now.
1279 We only do this when expensive_optimizations is enabled,
1280 since this complements reload inheritance / output
1281 reload deletion, and it can make debugging harder. */
1282 if (flag_expensive_optimizations && n_reloads > 1)
1284 rtx set = single_set (insn);
1286 && SET_SRC (set) == SET_DEST (set)
1287 && GET_CODE (SET_SRC (set)) == REG
1288 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1290 PUT_CODE (insn, NOTE);
1291 NOTE_SOURCE_FILE (insn) = 0;
1292 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1297 update_eliminable_offsets ();
1299 /* Remember for later shortcuts which insns had any reloads or
1300 register eliminations. */
1301 chain->need_elim = did_elimination;
1302 chain->need_reload = n_reloads > 0;
1303 chain->need_operand_change = operands_changed;
1305 /* Discard any register replacements done. */
1306 if (did_elimination)
1308 obstack_free (&reload_obstack, reload_firstobj);
1309 PATTERN (insn) = old_body;
1310 INSN_CODE (insn) = old_code;
1311 REG_NOTES (insn) = old_notes;
1312 something_needs_elimination = 1;
1315 something_needs_operands_changed |= operands_changed;
1319 *pprev_reload = chain;
1320 pprev_reload = &chain->next_need_reload;
1322 calculate_needs (chain);
1329 /* Compute the most additional registers needed by one instruction,
1330 given by CHAIN. Collect information separately for each class of regs.
1332 To compute the number of reload registers of each class needed for an
1333 insn, we must simulate what choose_reload_regs can do. We do this by
1334 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1335 reloads are used in both. The input part uses those reloads,
1336 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1337 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1338 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1340 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1341 which are live for the entire output portion, and the maximum of all the
1342 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1344 The total number of registers needed is the maximum of the
1345 inputs and outputs. */
1348 calculate_needs (chain)
1349 struct insn_chain *chain;
1353 /* Each `struct needs' corresponds to one RELOAD_... type. */
1357 struct needs output;
1359 struct needs other_addr;
1360 struct needs op_addr;
1361 struct needs op_addr_reload;
1362 struct needs in_addr[MAX_RECOG_OPERANDS];
1363 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1364 struct needs out_addr[MAX_RECOG_OPERANDS];
1365 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1368 bzero ((char *) chain->group_size, sizeof chain->group_size);
1369 for (i = 0; i < N_REG_CLASSES; i++)
1370 chain->group_mode[i] = VOIDmode;
1371 bzero ((char *) &insn_needs, sizeof insn_needs);
1373 /* Count each reload once in every class
1374 containing the reload's own class. */
1376 for (i = 0; i < n_reloads; i++)
1378 register enum reg_class *p;
1379 enum reg_class class = reload_reg_class[i];
1381 enum machine_mode mode;
1382 struct needs *this_needs;
1384 /* Don't count the dummy reloads, for which one of the
1385 regs mentioned in the insn can be used for reloading.
1386 Don't count optional reloads.
1387 Don't count reloads that got combined with others. */
1388 if (reload_reg_rtx[i] != 0
1389 || reload_optional[i] != 0
1390 || (reload_out[i] == 0 && reload_in[i] == 0
1391 && ! reload_secondary_p[i]))
1394 mode = reload_inmode[i];
1395 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1396 mode = reload_outmode[i];
1397 size = CLASS_MAX_NREGS (class, mode);
1399 /* Decide which time-of-use to count this reload for. */
1400 switch (reload_when_needed[i])
1403 this_needs = &insn_needs.other;
1405 case RELOAD_FOR_INPUT:
1406 this_needs = &insn_needs.input;
1408 case RELOAD_FOR_OUTPUT:
1409 this_needs = &insn_needs.output;
1411 case RELOAD_FOR_INSN:
1412 this_needs = &insn_needs.insn;
1414 case RELOAD_FOR_OTHER_ADDRESS:
1415 this_needs = &insn_needs.other_addr;
1417 case RELOAD_FOR_INPUT_ADDRESS:
1418 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1420 case RELOAD_FOR_INPADDR_ADDRESS:
1421 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1423 case RELOAD_FOR_OUTPUT_ADDRESS:
1424 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1426 case RELOAD_FOR_OUTADDR_ADDRESS:
1427 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1429 case RELOAD_FOR_OPERAND_ADDRESS:
1430 this_needs = &insn_needs.op_addr;
1432 case RELOAD_FOR_OPADDR_ADDR:
1433 this_needs = &insn_needs.op_addr_reload;
1439 enum machine_mode other_mode, allocate_mode;
1441 /* Count number of groups needed separately from
1442 number of individual regs needed. */
1443 this_needs->groups[(int) class]++;
1444 p = reg_class_superclasses[(int) class];
1445 while (*p != LIM_REG_CLASSES)
1446 this_needs->groups[(int) *p++]++;
1448 /* Record size and mode of a group of this class. */
1449 /* If more than one size group is needed,
1450 make all groups the largest needed size. */
1451 if (chain->group_size[(int) class] < size)
1453 other_mode = chain->group_mode[(int) class];
1454 allocate_mode = mode;
1456 chain->group_size[(int) class] = size;
1457 chain->group_mode[(int) class] = mode;
1462 allocate_mode = chain->group_mode[(int) class];
1465 /* Crash if two dissimilar machine modes both need
1466 groups of consecutive regs of the same class. */
1468 if (other_mode != VOIDmode && other_mode != allocate_mode
1469 && ! modes_equiv_for_class_p (allocate_mode,
1471 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1476 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1477 p = reg_class_superclasses[(int) class];
1478 while (*p != LIM_REG_CLASSES)
1479 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1485 /* All reloads have been counted for this insn;
1486 now merge the various times of use.
1487 This sets insn_needs, etc., to the maximum total number
1488 of registers needed at any point in this insn. */
1490 for (i = 0; i < N_REG_CLASSES; i++)
1492 int j, in_max, out_max;
1494 /* Compute normal and nongroup needs. */
1495 for (j = 0; j <= 1; j++)
1498 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1500 in_max = MAX (in_max,
1501 (insn_needs.in_addr[k].regs[j][i]
1502 + insn_needs.in_addr_addr[k].regs[j][i]));
1503 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1504 out_max = MAX (out_max,
1505 insn_needs.out_addr_addr[k].regs[j][i]);
1508 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1509 and operand addresses but not things used to reload
1510 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1511 don't conflict with things needed to reload inputs or
1514 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1515 insn_needs.op_addr_reload.regs[j][i]),
1518 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1520 insn_needs.input.regs[j][i]
1521 = MAX (insn_needs.input.regs[j][i]
1522 + insn_needs.op_addr.regs[j][i]
1523 + insn_needs.insn.regs[j][i],
1524 in_max + insn_needs.input.regs[j][i]);
1526 insn_needs.output.regs[j][i] += out_max;
1527 insn_needs.other.regs[j][i]
1528 += MAX (MAX (insn_needs.input.regs[j][i],
1529 insn_needs.output.regs[j][i]),
1530 insn_needs.other_addr.regs[j][i]);
1534 /* Now compute group needs. */
1535 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1537 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1538 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1539 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1540 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1543 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1544 insn_needs.op_addr_reload.groups[i]),
1546 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1548 insn_needs.input.groups[i]
1549 = MAX (insn_needs.input.groups[i]
1550 + insn_needs.op_addr.groups[i]
1551 + insn_needs.insn.groups[i],
1552 in_max + insn_needs.input.groups[i]);
1554 insn_needs.output.groups[i] += out_max;
1555 insn_needs.other.groups[i]
1556 += MAX (MAX (insn_needs.input.groups[i],
1557 insn_needs.output.groups[i]),
1558 insn_needs.other_addr.groups[i]);
1561 /* Record the needs for later. */
1562 chain->need = insn_needs.other;
1565 /* Find a group of exactly 2 registers.
1567 First try to fill out the group by spilling a single register which
1568 would allow completion of the group.
1570 Then try to create a new group from a pair of registers, neither of
1571 which are explicitly used.
1573 Then try to create a group from any pair of registers. */
1576 find_tworeg_group (chain, class, dumpfile)
1577 struct insn_chain *chain;
1582 /* First, look for a register that will complete a group. */
1583 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1587 j = potential_reload_regs[i];
1588 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1589 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1590 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1591 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1592 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1593 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1594 /* We don't want one part of another group.
1595 We could get "two groups" that overlap! */
1596 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1597 || (j < FIRST_PSEUDO_REGISTER - 1
1598 && (other = j + 1, spill_reg_order[other] >= 0)
1599 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1600 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1601 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1602 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1603 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1605 register enum reg_class *p;
1607 /* We have found one that will complete a group,
1608 so count off one group as provided. */
1609 chain->need.groups[class]--;
1610 p = reg_class_superclasses[class];
1611 while (*p != LIM_REG_CLASSES)
1613 if (chain->group_size [(int) *p] <= chain->group_size [class])
1614 chain->need.groups[(int) *p]--;
1618 /* Indicate both these regs are part of a group. */
1619 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1620 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1624 /* We can't complete a group, so start one. */
1625 if (i == FIRST_PSEUDO_REGISTER)
1626 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1629 j = potential_reload_regs[i];
1630 /* Verify that J+1 is a potential reload reg. */
1631 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1632 if (potential_reload_regs[k] == j + 1)
1634 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1635 && k < FIRST_PSEUDO_REGISTER
1636 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1637 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1638 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1639 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1640 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1641 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1645 /* I should be the index in potential_reload_regs
1646 of the new reload reg we have found. */
1648 new_spill_reg (chain, i, class, 0, dumpfile);
1651 /* Find a group of more than 2 registers.
1652 Look for a sufficient sequence of unspilled registers, and spill them all
1656 find_group (chain, class, dumpfile)
1657 struct insn_chain *chain;
1663 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1665 int j = potential_reload_regs[i];
1668 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1669 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1672 /* Check each reg in the sequence. */
1673 for (k = 0; k < chain->group_size[class]; k++)
1674 if (! (spill_reg_order[j + k] < 0
1675 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1676 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1678 /* We got a full sequence, so spill them all. */
1679 if (k == chain->group_size[class])
1681 register enum reg_class *p;
1682 for (k = 0; k < chain->group_size[class]; k++)
1685 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1686 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1687 if (potential_reload_regs[idx] == j + k)
1689 new_spill_reg (chain, idx, class, 0, dumpfile);
1692 /* We have found one that will complete a group,
1693 so count off one group as provided. */
1694 chain->need.groups[class]--;
1695 p = reg_class_superclasses[class];
1696 while (*p != LIM_REG_CLASSES)
1698 if (chain->group_size [(int) *p]
1699 <= chain->group_size [class])
1700 chain->need.groups[(int) *p]--;
1707 /* There are no groups left. */
1708 spill_failure (chain->insn);
1712 /* If pseudo REG conflicts with one of our reload registers, mark it as
1715 maybe_mark_pseudo_spilled (reg)
1719 int r = reg_renumber[reg];
1724 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1725 for (i = 0; i < n_spills; i++)
1726 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1728 SET_REGNO_REG_SET (spilled_pseudos, reg);
1733 /* Find more reload regs to satisfy the remaining need of an insn, which
1735 Do it by ascending class number, since otherwise a reg
1736 might be spilled for a big class and might fail to count
1737 for a smaller class even though it belongs to that class.
1739 Count spilled regs in `spills', and add entries to
1740 `spill_regs' and `spill_reg_order'.
1742 ??? Note there is a problem here.
1743 When there is a need for a group in a high-numbered class,
1744 and also need for non-group regs that come from a lower class,
1745 the non-group regs are chosen first. If there aren't many regs,
1746 they might leave no room for a group.
1748 This was happening on the 386. To fix it, we added the code
1749 that calls possible_group_p, so that the lower class won't
1750 break up the last possible group.
1752 Really fixing the problem would require changes above
1753 in counting the regs already spilled, and in choose_reload_regs.
1754 It might be hard to avoid introducing bugs there. */
1757 find_reload_regs (chain, dumpfile)
1758 struct insn_chain *chain;
1762 short *group_needs = chain->need.groups;
1763 short *simple_needs = chain->need.regs[0];
1764 short *nongroup_needs = chain->need.regs[1];
1767 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1769 /* Compute the order of preference for hard registers to spill.
1770 Store them by decreasing preference in potential_reload_regs. */
1772 order_regs_for_reload (chain);
1774 /* So far, no hard regs have been spilled. */
1776 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1777 spill_reg_order[i] = -1;
1779 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1780 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1781 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1783 for (class = 0; class < N_REG_CLASSES; class++)
1785 /* First get the groups of registers.
1786 If we got single registers first, we might fragment
1788 while (group_needs[class] > 0)
1790 /* If any single spilled regs happen to form groups,
1791 count them now. Maybe we don't really need
1792 to spill another group. */
1793 count_possible_groups (chain, class);
1795 if (group_needs[class] <= 0)
1798 /* Groups of size 2, the only groups used on most machines,
1799 are treated specially. */
1800 if (chain->group_size[class] == 2)
1801 find_tworeg_group (chain, class, dumpfile);
1803 find_group (chain, class, dumpfile);
1808 /* Now similarly satisfy all need for single registers. */
1810 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1812 /* If we spilled enough regs, but they weren't counted
1813 against the non-group need, see if we can count them now.
1814 If so, we can avoid some actual spilling. */
1815 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1816 for (i = 0; i < n_spills; i++)
1818 int regno = spill_regs[i];
1819 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1820 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1821 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1822 && nongroup_needs[class] > 0)
1824 register enum reg_class *p;
1826 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1827 nongroup_needs[class]--;
1828 p = reg_class_superclasses[class];
1829 while (*p != LIM_REG_CLASSES)
1830 nongroup_needs[(int) *p++]--;
1834 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1837 /* Consider the potential reload regs that aren't
1838 yet in use as reload regs, in order of preference.
1839 Find the most preferred one that's in this class. */
1841 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1843 int regno = potential_reload_regs[i];
1845 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1846 /* If this reg will not be available for groups,
1847 pick one that does not foreclose possible groups.
1848 This is a kludge, and not very general,
1849 but it should be sufficient to make the 386 work,
1850 and the problem should not occur on machines with
1852 && (nongroup_needs[class] == 0
1853 || possible_group_p (chain, regno)))
1857 /* If we couldn't get a register, try to get one even if we
1858 might foreclose possible groups. This may cause problems
1859 later, but that's better than aborting now, since it is
1860 possible that we will, in fact, be able to form the needed
1861 group even with this allocation. */
1863 if (i >= FIRST_PSEUDO_REGISTER
1864 && asm_noperands (chain->insn) < 0)
1865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1866 if (potential_reload_regs[i] >= 0
1867 && TEST_HARD_REG_BIT (reg_class_contents[class],
1868 potential_reload_regs[i]))
1871 /* I should be the index in potential_reload_regs
1872 of the new reload reg we have found. */
1874 new_spill_reg (chain, i, class, 1, dumpfile);
1880 /* We know which hard regs to use, now mark the pseudos that live in them
1881 as needing to be kicked out. */
1882 EXECUTE_IF_SET_IN_REG_SET
1883 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1885 maybe_mark_pseudo_spilled (i);
1887 EXECUTE_IF_SET_IN_REG_SET
1888 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1890 maybe_mark_pseudo_spilled (i);
1893 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1897 dump_needs (chain, dumpfile)
1898 struct insn_chain *chain;
1901 static char *reg_class_names[] = REG_CLASS_NAMES;
1903 struct needs *n = &chain->need;
1905 for (i = 0; i < N_REG_CLASSES; i++)
1907 if (n->regs[i][0] > 0)
1909 ";; Need %d reg%s of class %s.\n",
1910 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
1911 reg_class_names[i]);
1912 if (n->regs[i][1] > 0)
1914 ";; Need %d nongroup reg%s of class %s.\n",
1915 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
1916 reg_class_names[i]);
1917 if (n->groups[i] > 0)
1919 ";; Need %d group%s (%smode) of class %s.\n",
1920 n->groups[i], n->groups[i] == 1 ? "" : "s",
1921 mode_name[(int) chain->group_mode[i]],
1922 reg_class_names[i]);
1926 /* Delete all insns that were inserted by emit_caller_save_insns during
1929 delete_caller_save_insns ()
1931 struct insn_chain *c = reload_insn_chain;
1935 while (c != 0 && c->is_caller_save_insn)
1937 struct insn_chain *next = c->next;
1940 if (insn == basic_block_head[c->block])
1941 basic_block_head[c->block] = NEXT_INSN (insn);
1942 if (insn == basic_block_end[c->block])
1943 basic_block_end[c->block] = PREV_INSN (insn);
1944 if (c == reload_insn_chain)
1945 reload_insn_chain = next;
1947 if (NEXT_INSN (insn) != 0)
1948 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1949 if (PREV_INSN (insn) != 0)
1950 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1953 next->prev = c->prev;
1955 c->prev->next = next;
1956 c->next = unused_insn_chains;
1957 unused_insn_chains = c;
1965 /* Nonzero if, after spilling reg REGNO for non-groups,
1966 it will still be possible to find a group if we still need one. */
1969 possible_group_p (chain, regno)
1970 struct insn_chain *chain;
1974 int class = (int) NO_REGS;
1976 for (i = 0; i < (int) N_REG_CLASSES; i++)
1977 if (chain->need.groups[i] > 0)
1983 if (class == (int) NO_REGS)
1986 /* Consider each pair of consecutive registers. */
1987 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1989 /* Ignore pairs that include reg REGNO. */
1990 if (i == regno || i + 1 == regno)
1993 /* Ignore pairs that are outside the class that needs the group.
1994 ??? Here we fail to handle the case where two different classes
1995 independently need groups. But this never happens with our
1996 current machine descriptions. */
1997 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1998 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2001 /* A pair of consecutive regs we can still spill does the trick. */
2002 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2003 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2004 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2007 /* A pair of one already spilled and one we can spill does it
2008 provided the one already spilled is not otherwise reserved. */
2009 if (spill_reg_order[i] < 0
2010 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2011 && spill_reg_order[i + 1] >= 0
2012 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2013 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2015 if (spill_reg_order[i + 1] < 0
2016 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2017 && spill_reg_order[i] >= 0
2018 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2019 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2026 /* Count any groups of CLASS that can be formed from the registers recently
2030 count_possible_groups (chain, class)
2031 struct insn_chain *chain;
2037 /* Now find all consecutive groups of spilled registers
2038 and mark each group off against the need for such groups.
2039 But don't count them against ordinary need, yet. */
2041 if (chain->group_size[class] == 0)
2044 CLEAR_HARD_REG_SET (new);
2046 /* Make a mask of all the regs that are spill regs in class I. */
2047 for (i = 0; i < n_spills; i++)
2049 int regno = spill_regs[i];
2051 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2052 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2053 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2054 SET_HARD_REG_BIT (new, regno);
2057 /* Find each consecutive group of them. */
2058 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2059 if (TEST_HARD_REG_BIT (new, i)
2060 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2061 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2063 for (j = 1; j < chain->group_size[class]; j++)
2064 if (! TEST_HARD_REG_BIT (new, i + j))
2067 if (j == chain->group_size[class])
2069 /* We found a group. Mark it off against this class's need for
2070 groups, and against each superclass too. */
2071 register enum reg_class *p;
2073 chain->need.groups[class]--;
2074 p = reg_class_superclasses[class];
2075 while (*p != LIM_REG_CLASSES)
2077 if (chain->group_size [(int) *p] <= chain->group_size [class])
2078 chain->need.groups[(int) *p]--;
2082 /* Don't count these registers again. */
2083 for (j = 0; j < chain->group_size[class]; j++)
2084 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2087 /* Skip to the last reg in this group. When i is incremented above,
2088 it will then point to the first reg of the next possible group. */
2093 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2094 another mode that needs to be reloaded for the same register class CLASS.
2095 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2096 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2098 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2099 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2100 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2101 causes unnecessary failures on machines requiring alignment of register
2102 groups when the two modes are different sizes, because the larger mode has
2103 more strict alignment rules than the smaller mode. */
2106 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2107 enum machine_mode allocate_mode, other_mode;
2108 enum reg_class class;
2111 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2113 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2114 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2115 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2121 /* Handle the failure to find a register to spill.
2122 INSN should be one of the insns which needed this particular spill reg. */
2125 spill_failure (insn)
2128 if (asm_noperands (PATTERN (insn)) >= 0)
2129 error_for_asm (insn, "`asm' needs too many reloads");
2131 fatal_insn ("Unable to find a register to spill.", insn);
2134 /* Add a new register to the tables of available spill-registers.
2135 CHAIN is the insn for which the register will be used; we decrease the
2137 I is the index of this register in potential_reload_regs.
2138 CLASS is the regclass whose need is being satisfied.
2139 NONGROUP is 0 if this register is part of a group.
2140 DUMPFILE is the same as the one that `reload' got. */
2143 new_spill_reg (chain, i, class, nongroup, dumpfile)
2144 struct insn_chain *chain;
2150 register enum reg_class *p;
2151 int regno = potential_reload_regs[i];
2153 if (i >= FIRST_PSEUDO_REGISTER)
2155 spill_failure (chain->insn);
2160 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2162 static char *reg_class_names[] = REG_CLASS_NAMES;
2164 if (asm_noperands (PATTERN (chain->insn)) < 0)
2166 /* The error message is still correct - we know only that it wasn't
2167 an asm statement that caused the problem, but one of the global
2168 registers declared by the users might have screwed us. */
2169 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2170 regno, reg_names[regno], reg_class_names[class]);
2171 error ("This may be due to a compiler bug or to impossible asm");
2172 error ("statements or clauses.");
2173 fatal_insn ("This is the instruction:", chain->insn);
2175 error_for_asm (chain->insn, "Invalid `asm' statement:");
2176 error_for_asm (chain->insn,
2177 "fixed or forbidden register %d (%s) was spilled for class %s.",
2178 regno, reg_names[regno], reg_class_names[class]);
2183 /* Make reg REGNO an additional reload reg. */
2185 potential_reload_regs[i] = -1;
2186 spill_regs[n_spills] = regno;
2187 spill_reg_order[regno] = n_spills;
2189 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2190 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2192 /* Clear off the needs we just satisfied. */
2194 chain->need.regs[0][class]--;
2195 p = reg_class_superclasses[class];
2196 while (*p != LIM_REG_CLASSES)
2197 chain->need.regs[0][(int) *p++]--;
2199 if (nongroup && chain->need.regs[1][class] > 0)
2201 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2202 chain->need.regs[1][class]--;
2203 p = reg_class_superclasses[class];
2204 while (*p != LIM_REG_CLASSES)
2205 chain->need.regs[1][(int) *p++]--;
2211 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2212 data that is dead in INSN. */
2215 delete_dead_insn (insn)
2218 rtx prev = prev_real_insn (insn);
2221 /* If the previous insn sets a register that dies in our insn, delete it
2223 if (prev && GET_CODE (PATTERN (prev)) == SET
2224 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2225 && reg_mentioned_p (prev_dest, PATTERN (insn))
2226 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2227 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2228 delete_dead_insn (prev);
2230 PUT_CODE (insn, NOTE);
2231 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2232 NOTE_SOURCE_FILE (insn) = 0;
2235 /* Modify the home of pseudo-reg I.
2236 The new home is present in reg_renumber[I].
2238 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2239 or it may be -1, meaning there is none or it is not relevant.
2240 This is used so that all pseudos spilled from a given hard reg
2241 can share one stack slot. */
2244 alter_reg (i, from_reg)
2248 /* When outputting an inline function, this can happen
2249 for a reg that isn't actually used. */
2250 if (regno_reg_rtx[i] == 0)
2253 /* If the reg got changed to a MEM at rtl-generation time,
2255 if (GET_CODE (regno_reg_rtx[i]) != REG)
2258 /* Modify the reg-rtx to contain the new hard reg
2259 number or else to contain its pseudo reg number. */
2260 REGNO (regno_reg_rtx[i])
2261 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2263 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2264 allocate a stack slot for it. */
2266 if (reg_renumber[i] < 0
2267 && REG_N_REFS (i) > 0
2268 && reg_equiv_constant[i] == 0
2269 && reg_equiv_memory_loc[i] == 0)
2272 int inherent_size = PSEUDO_REGNO_BYTES (i);
2273 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2276 /* Each pseudo reg has an inherent size which comes from its own mode,
2277 and a total size which provides room for paradoxical subregs
2278 which refer to the pseudo reg in wider modes.
2280 We can use a slot already allocated if it provides both
2281 enough inherent space and enough total space.
2282 Otherwise, we allocate a new slot, making sure that it has no less
2283 inherent space, and no less total space, then the previous slot. */
2286 /* No known place to spill from => no slot to reuse. */
2287 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2288 inherent_size == total_size ? 0 : -1);
2289 if (BYTES_BIG_ENDIAN)
2290 /* Cancel the big-endian correction done in assign_stack_local.
2291 Get the address of the beginning of the slot.
2292 This is so we can do a big-endian correction unconditionally
2294 adjust = inherent_size - total_size;
2296 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2298 /* Reuse a stack slot if possible. */
2299 else if (spill_stack_slot[from_reg] != 0
2300 && spill_stack_slot_width[from_reg] >= total_size
2301 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2303 x = spill_stack_slot[from_reg];
2304 /* Allocate a bigger slot. */
2307 /* Compute maximum size needed, both for inherent size
2308 and for total size. */
2309 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2311 if (spill_stack_slot[from_reg])
2313 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2315 mode = GET_MODE (spill_stack_slot[from_reg]);
2316 if (spill_stack_slot_width[from_reg] > total_size)
2317 total_size = spill_stack_slot_width[from_reg];
2319 /* Make a slot with that size. */
2320 x = assign_stack_local (mode, total_size,
2321 inherent_size == total_size ? 0 : -1);
2323 if (BYTES_BIG_ENDIAN)
2325 /* Cancel the big-endian correction done in assign_stack_local.
2326 Get the address of the beginning of the slot.
2327 This is so we can do a big-endian correction unconditionally
2329 adjust = GET_MODE_SIZE (mode) - total_size;
2331 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2334 plus_constant (XEXP (x, 0), adjust));
2336 spill_stack_slot[from_reg] = stack_slot;
2337 spill_stack_slot_width[from_reg] = total_size;
2340 /* On a big endian machine, the "address" of the slot
2341 is the address of the low part that fits its inherent mode. */
2342 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2343 adjust += (total_size - inherent_size);
2345 /* If we have any adjustment to make, or if the stack slot is the
2346 wrong mode, make a new stack slot. */
2347 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2349 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2350 plus_constant (XEXP (x, 0), adjust));
2352 /* If this was shared among registers, must ensure we never
2353 set it readonly since that can cause scheduling
2354 problems. Note we would only have in this adjustment
2355 case in any event, since the code above doesn't set it. */
2358 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2361 /* Save the stack slot for later. */
2362 reg_equiv_memory_loc[i] = x;
2366 /* Mark the slots in regs_ever_live for the hard regs
2367 used by pseudo-reg number REGNO. */
2370 mark_home_live (regno)
2373 register int i, lim;
2374 i = reg_renumber[regno];
2377 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2379 regs_ever_live[i++] = 1;
2382 /* This function handles the tracking of elimination offsets around branches.
2384 X is a piece of RTL being scanned.
2386 INSN is the insn that it came from, if any.
2388 INITIAL_P is non-zero if we are to set the offset to be the initial
2389 offset and zero if we are setting the offset of the label to be the
2393 set_label_offsets (x, insn, initial_p)
2398 enum rtx_code code = GET_CODE (x);
2401 struct elim_table *p;
2406 if (LABEL_REF_NONLOCAL_P (x))
2411 /* ... fall through ... */
2414 /* If we know nothing about this label, set the desired offsets. Note
2415 that this sets the offset at a label to be the offset before a label
2416 if we don't know anything about the label. This is not correct for
2417 the label after a BARRIER, but is the best guess we can make. If
2418 we guessed wrong, we will suppress an elimination that might have
2419 been possible had we been able to guess correctly. */
2421 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2423 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2424 offsets_at[CODE_LABEL_NUMBER (x)][i]
2425 = (initial_p ? reg_eliminate[i].initial_offset
2426 : reg_eliminate[i].offset);
2427 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2430 /* Otherwise, if this is the definition of a label and it is
2431 preceded by a BARRIER, set our offsets to the known offset of
2435 && (tem = prev_nonnote_insn (insn)) != 0
2436 && GET_CODE (tem) == BARRIER)
2438 num_not_at_initial_offset = 0;
2439 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2441 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2442 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2443 if (reg_eliminate[i].can_eliminate
2444 && (reg_eliminate[i].offset
2445 != reg_eliminate[i].initial_offset))
2446 num_not_at_initial_offset++;
2451 /* If neither of the above cases is true, compare each offset
2452 with those previously recorded and suppress any eliminations
2453 where the offsets disagree. */
2455 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2456 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2457 != (initial_p ? reg_eliminate[i].initial_offset
2458 : reg_eliminate[i].offset))
2459 reg_eliminate[i].can_eliminate = 0;
2464 set_label_offsets (PATTERN (insn), insn, initial_p);
2466 /* ... fall through ... */
2470 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2471 and hence must have all eliminations at their initial offsets. */
2472 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2473 if (REG_NOTE_KIND (tem) == REG_LABEL)
2474 set_label_offsets (XEXP (tem, 0), insn, 1);
2479 /* Each of the labels in the address vector must be at their initial
2480 offsets. We want the first field for ADDR_VEC and the second
2481 field for ADDR_DIFF_VEC. */
2483 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2484 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2489 /* We only care about setting PC. If the source is not RETURN,
2490 IF_THEN_ELSE, or a label, disable any eliminations not at
2491 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2492 isn't one of those possibilities. For branches to a label,
2493 call ourselves recursively.
2495 Note that this can disable elimination unnecessarily when we have
2496 a non-local goto since it will look like a non-constant jump to
2497 someplace in the current function. This isn't a significant
2498 problem since such jumps will normally be when all elimination
2499 pairs are back to their initial offsets. */
2501 if (SET_DEST (x) != pc_rtx)
2504 switch (GET_CODE (SET_SRC (x)))
2511 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2515 tem = XEXP (SET_SRC (x), 1);
2516 if (GET_CODE (tem) == LABEL_REF)
2517 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2518 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2521 tem = XEXP (SET_SRC (x), 2);
2522 if (GET_CODE (tem) == LABEL_REF)
2523 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2524 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2532 /* If we reach here, all eliminations must be at their initial
2533 offset because we are doing a jump to a variable address. */
2534 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2535 if (p->offset != p->initial_offset)
2536 p->can_eliminate = 0;
2544 /* Used for communication between the next two function to properly share
2545 the vector for an ASM_OPERANDS. */
2547 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2549 /* Scan X and replace any eliminable registers (such as fp) with a
2550 replacement (such as sp), plus an offset.
2552 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2553 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2554 MEM, we are allowed to replace a sum of a register and the constant zero
2555 with the register, which we cannot do outside a MEM. In addition, we need
2556 to record the fact that a register is referenced outside a MEM.
2558 If INSN is an insn, it is the insn containing X. If we replace a REG
2559 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2560 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2561 the REG is being modified.
2563 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2564 That's used when we eliminate in expressions stored in notes.
2565 This means, do not set ref_outside_mem even if the reference
2568 If we see a modification to a register we know about, take the
2569 appropriate action (see case SET, below).
2571 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2572 replacements done assuming all offsets are at their initial values. If
2573 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2574 encounter, return the actual location so that find_reloads will do
2575 the proper thing. */
2578 eliminate_regs (x, mem_mode, insn)
2580 enum machine_mode mem_mode;
2583 enum rtx_code code = GET_CODE (x);
2584 struct elim_table *ep;
2607 /* This is only for the benefit of the debugging backends, which call
2608 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2609 removed after CSE. */
2610 new = eliminate_regs (XEXP (x, 0), 0, insn);
2611 if (GET_CODE (new) == MEM)
2612 return XEXP (new, 0);
2618 /* First handle the case where we encounter a bare register that
2619 is eliminable. Replace it with a PLUS. */
2620 if (regno < FIRST_PSEUDO_REGISTER)
2622 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2624 if (ep->from_rtx == x && ep->can_eliminate)
2627 /* Refs inside notes don't count for this purpose. */
2628 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2629 || GET_CODE (insn) == INSN_LIST)))
2630 ep->ref_outside_mem = 1;
2631 return plus_constant (ep->to_rtx, ep->previous_offset);
2638 /* If this is the sum of an eliminable register and a constant, rework
2640 if (GET_CODE (XEXP (x, 0)) == REG
2641 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2642 && CONSTANT_P (XEXP (x, 1)))
2644 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2646 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2649 /* Refs inside notes don't count for this purpose. */
2650 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2651 || GET_CODE (insn) == INSN_LIST)))
2652 ep->ref_outside_mem = 1;
2654 /* The only time we want to replace a PLUS with a REG (this
2655 occurs when the constant operand of the PLUS is the negative
2656 of the offset) is when we are inside a MEM. We won't want
2657 to do so at other times because that would change the
2658 structure of the insn in a way that reload can't handle.
2659 We special-case the commonest situation in
2660 eliminate_regs_in_insn, so just replace a PLUS with a
2661 PLUS here, unless inside a MEM. */
2662 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2663 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2666 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2667 plus_constant (XEXP (x, 1),
2668 ep->previous_offset));
2671 /* If the register is not eliminable, we are done since the other
2672 operand is a constant. */
2676 /* If this is part of an address, we want to bring any constant to the
2677 outermost PLUS. We will do this by doing register replacement in
2678 our operands and seeing if a constant shows up in one of them.
2680 We assume here this is part of an address (or a "load address" insn)
2681 since an eliminable register is not likely to appear in any other
2684 If we have (plus (eliminable) (reg)), we want to produce
2685 (plus (plus (replacement) (reg) (const))). If this was part of a
2686 normal add insn, (plus (replacement) (reg)) will be pushed as a
2687 reload. This is the desired action. */
2690 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2691 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2693 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2695 /* If one side is a PLUS and the other side is a pseudo that
2696 didn't get a hard register but has a reg_equiv_constant,
2697 we must replace the constant here since it may no longer
2698 be in the position of any operand. */
2699 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2700 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2701 && reg_renumber[REGNO (new1)] < 0
2702 && reg_equiv_constant != 0
2703 && reg_equiv_constant[REGNO (new1)] != 0)
2704 new1 = reg_equiv_constant[REGNO (new1)];
2705 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2706 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2707 && reg_renumber[REGNO (new0)] < 0
2708 && reg_equiv_constant[REGNO (new0)] != 0)
2709 new0 = reg_equiv_constant[REGNO (new0)];
2711 new = form_sum (new0, new1);
2713 /* As above, if we are not inside a MEM we do not want to
2714 turn a PLUS into something else. We might try to do so here
2715 for an addition of 0 if we aren't optimizing. */
2716 if (! mem_mode && GET_CODE (new) != PLUS)
2717 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2725 /* If this is the product of an eliminable register and a
2726 constant, apply the distribute law and move the constant out
2727 so that we have (plus (mult ..) ..). This is needed in order
2728 to keep load-address insns valid. This case is pathological.
2729 We ignore the possibility of overflow here. */
2730 if (GET_CODE (XEXP (x, 0)) == REG
2731 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2732 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2733 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2735 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2738 /* Refs inside notes don't count for this purpose. */
2739 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2740 || GET_CODE (insn) == INSN_LIST)))
2741 ep->ref_outside_mem = 1;
2744 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2745 ep->previous_offset * INTVAL (XEXP (x, 1)));
2748 /* ... fall through ... */
2753 case DIV: case UDIV:
2754 case MOD: case UMOD:
2755 case AND: case IOR: case XOR:
2756 case ROTATERT: case ROTATE:
2757 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2759 case GE: case GT: case GEU: case GTU:
2760 case LE: case LT: case LEU: case LTU:
2762 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2764 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2766 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2767 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2772 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2775 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2776 if (new != XEXP (x, 0))
2777 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2780 /* ... fall through ... */
2783 /* Now do eliminations in the rest of the chain. If this was
2784 an EXPR_LIST, this might result in allocating more memory than is
2785 strictly needed, but it simplifies the code. */
2788 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2789 if (new != XEXP (x, 1))
2790 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2799 if (ep->to_rtx == XEXP (x, 0))
2801 int size = GET_MODE_SIZE (mem_mode);
2803 /* If more bytes than MEM_MODE are pushed, account for them. */
2804 #ifdef PUSH_ROUNDING
2805 if (ep->to_rtx == stack_pointer_rtx)
2806 size = PUSH_ROUNDING (size);
2808 if (code == PRE_DEC || code == POST_DEC)
2814 /* Fall through to generic unary operation case. */
2815 case STRICT_LOW_PART:
2817 case SIGN_EXTEND: case ZERO_EXTEND:
2818 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2819 case FLOAT: case FIX:
2820 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2824 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2825 if (new != XEXP (x, 0))
2826 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2830 /* Similar to above processing, but preserve SUBREG_WORD.
2831 Convert (subreg (mem)) to (mem) if not paradoxical.
2832 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2833 pseudo didn't get a hard reg, we must replace this with the
2834 eliminated version of the memory location because push_reloads
2835 may do the replacement in certain circumstances. */
2836 if (GET_CODE (SUBREG_REG (x)) == REG
2837 && (GET_MODE_SIZE (GET_MODE (x))
2838 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2839 && reg_equiv_memory_loc != 0
2840 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2843 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2846 /* If we didn't change anything, we must retain the pseudo. */
2847 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2848 new = SUBREG_REG (x);
2851 /* In this case, we must show that the pseudo is used in this
2852 insn so that delete_output_reload will do the right thing. */
2853 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2854 && GET_CODE (insn) != INSN_LIST)
2855 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
2858 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2860 /* Ensure NEW isn't shared in case we have to reload it. */
2861 new = copy_rtx (new);
2864 new = SUBREG_REG (x);
2868 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2870 if (new != XEXP (x, 0))
2872 int x_size = GET_MODE_SIZE (GET_MODE (x));
2873 int new_size = GET_MODE_SIZE (GET_MODE (new));
2875 if (GET_CODE (new) == MEM
2876 && ((x_size < new_size
2877 #ifdef WORD_REGISTER_OPERATIONS
2878 /* On these machines, combine can create rtl of the form
2879 (set (subreg:m1 (reg:m2 R) 0) ...)
2880 where m1 < m2, and expects something interesting to
2881 happen to the entire word. Moreover, it will use the
2882 (reg:m2 R) later, expecting all bits to be preserved.
2883 So if the number of words is the same, preserve the
2884 subreg so that push_reloads can see it. */
2885 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2888 || (x_size == new_size))
2891 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2892 enum machine_mode mode = GET_MODE (x);
2894 if (BYTES_BIG_ENDIAN)
2895 offset += (MIN (UNITS_PER_WORD,
2896 GET_MODE_SIZE (GET_MODE (new)))
2897 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2899 PUT_MODE (new, mode);
2900 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2904 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2910 /* If using a register that is the source of an eliminate we still
2911 think can be performed, note it cannot be performed since we don't
2912 know how this register is used. */
2913 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2914 if (ep->from_rtx == XEXP (x, 0))
2915 ep->can_eliminate = 0;
2917 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2918 if (new != XEXP (x, 0))
2919 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2923 /* If clobbering a register that is the replacement register for an
2924 elimination we still think can be performed, note that it cannot
2925 be performed. Otherwise, we need not be concerned about it. */
2926 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2927 if (ep->to_rtx == XEXP (x, 0))
2928 ep->can_eliminate = 0;
2930 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2931 if (new != XEXP (x, 0))
2932 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2938 /* Properly handle sharing input and constraint vectors. */
2939 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2941 /* When we come to a new vector not seen before,
2942 scan all its elements; keep the old vector if none
2943 of them changes; otherwise, make a copy. */
2944 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2945 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2946 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2947 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2950 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2951 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2954 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2955 new_asm_operands_vec = old_asm_operands_vec;
2957 new_asm_operands_vec
2958 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2961 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2962 if (new_asm_operands_vec == old_asm_operands_vec)
2965 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2966 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2967 ASM_OPERANDS_OUTPUT_IDX (x),
2968 new_asm_operands_vec,
2969 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2970 ASM_OPERANDS_SOURCE_FILE (x),
2971 ASM_OPERANDS_SOURCE_LINE (x));
2972 new->volatil = x->volatil;
2977 /* Check for setting a register that we know about. */
2978 if (GET_CODE (SET_DEST (x)) == REG)
2980 /* See if this is setting the replacement register for an
2983 If DEST is the hard frame pointer, we do nothing because we
2984 assume that all assignments to the frame pointer are for
2985 non-local gotos and are being done at a time when they are valid
2986 and do not disturb anything else. Some machines want to
2987 eliminate a fake argument pointer (or even a fake frame pointer)
2988 with either the real frame or the stack pointer. Assignments to
2989 the hard frame pointer must not prevent this elimination. */
2991 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2993 if (ep->to_rtx == SET_DEST (x)
2994 && SET_DEST (x) != hard_frame_pointer_rtx)
2996 /* If it is being incremented, adjust the offset. Otherwise,
2997 this elimination can't be done. */
2998 rtx src = SET_SRC (x);
3000 if (GET_CODE (src) == PLUS
3001 && XEXP (src, 0) == SET_DEST (x)
3002 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3003 ep->offset -= INTVAL (XEXP (src, 1));
3005 ep->can_eliminate = 0;
3008 /* Now check to see we are assigning to a register that can be
3009 eliminated. If so, it must be as part of a PARALLEL, since we
3010 will not have been called if this is a single SET. So indicate
3011 that we can no longer eliminate this reg. */
3012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3014 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3015 ep->can_eliminate = 0;
3018 /* Now avoid the loop below in this common case. */
3020 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3021 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3023 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3024 write a CLOBBER insn. */
3025 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3026 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3027 && GET_CODE (insn) != INSN_LIST)
3028 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3030 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3031 return gen_rtx_SET (VOIDmode, new0, new1);
3037 /* This is only for the benefit of the debugging backends, which call
3038 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3039 removed after CSE. */
3040 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3041 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3043 /* Our only special processing is to pass the mode of the MEM to our
3044 recursive call and copy the flags. While we are here, handle this
3045 case more efficiently. */
3046 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3047 if (new != XEXP (x, 0))
3049 new = gen_rtx_MEM (GET_MODE (x), new);
3050 new->volatil = x->volatil;
3051 new->unchanging = x->unchanging;
3052 new->in_struct = x->in_struct;
3062 /* Process each of our operands recursively. If any have changed, make a
3064 fmt = GET_RTX_FORMAT (code);
3065 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3069 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3070 if (new != XEXP (x, i) && ! copied)
3072 rtx new_x = rtx_alloc (code);
3073 bcopy ((char *) x, (char *) new_x,
3074 (sizeof (*new_x) - sizeof (new_x->fld)
3075 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3081 else if (*fmt == 'E')
3084 for (j = 0; j < XVECLEN (x, i); j++)
3086 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3087 if (new != XVECEXP (x, i, j) && ! copied_vec)
3089 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3093 rtx new_x = rtx_alloc (code);
3094 bcopy ((char *) x, (char *) new_x,
3095 (sizeof (*new_x) - sizeof (new_x->fld)
3096 + (sizeof (new_x->fld[0])
3097 * GET_RTX_LENGTH (code))));
3101 XVEC (x, i) = new_v;
3104 XVECEXP (x, i, j) = new;
3112 /* Scan INSN and eliminate all eliminable registers in it.
3114 If REPLACE is nonzero, do the replacement destructively. Also
3115 delete the insn as dead it if it is setting an eliminable register.
3117 If REPLACE is zero, do all our allocations in reload_obstack.
3119 If no eliminations were done and this insn doesn't require any elimination
3120 processing (these are not identical conditions: it might be updating sp,
3121 but not referencing fp; this needs to be seen during reload_as_needed so
3122 that the offset between fp and sp can be taken into consideration), zero
3123 is returned. Otherwise, 1 is returned. */
3126 eliminate_regs_in_insn (insn, replace)
3130 rtx old_body = PATTERN (insn);
3131 rtx old_set = single_set (insn);
3134 struct elim_table *ep;
3137 push_obstacks (&reload_obstack, &reload_obstack);
3139 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3140 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3142 /* Check for setting an eliminable register. */
3143 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3144 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3146 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3147 /* If this is setting the frame pointer register to the
3148 hardware frame pointer register and this is an elimination
3149 that will be done (tested above), this insn is really
3150 adjusting the frame pointer downward to compensate for
3151 the adjustment done before a nonlocal goto. */
3152 if (ep->from == FRAME_POINTER_REGNUM
3153 && ep->to == HARD_FRAME_POINTER_REGNUM)
3155 rtx src = SET_SRC (old_set);
3157 rtx prev_insn, prev_set;
3159 if (src == ep->to_rtx)
3161 else if (GET_CODE (src) == PLUS
3162 && GET_CODE (XEXP (src, 0)) == CONST_INT
3163 && XEXP (src, 1) == ep->to_rtx)
3164 offset = INTVAL (XEXP (src, 0)), ok = 1;
3165 else if (GET_CODE (src) == PLUS
3166 && GET_CODE (XEXP (src, 1)) == CONST_INT
3167 && XEXP (src, 0) == ep->to_rtx)
3168 offset = INTVAL (XEXP (src, 1)), ok = 1;
3169 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3170 && (prev_set = single_set (prev_insn)) != 0
3171 && rtx_equal_p (SET_DEST (prev_set), src))
3173 src = SET_SRC (prev_set);
3174 if (src == ep->to_rtx)
3176 else if (GET_CODE (src) == PLUS
3177 && GET_CODE (XEXP (src, 0)) == CONST_INT
3178 && XEXP (src, 1) == ep->to_rtx)
3179 offset = INTVAL (XEXP (src, 0)), ok = 1;
3180 else if (GET_CODE (src) == PLUS
3181 && GET_CODE (XEXP (src, 1)) == CONST_INT
3182 && XEXP (src, 0) == ep->to_rtx)
3183 offset = INTVAL (XEXP (src, 1)), ok = 1;
3191 = plus_constant (ep->to_rtx, offset - ep->offset);
3193 /* First see if this insn remains valid when we
3194 make the change. If not, keep the INSN_CODE
3195 the same and let reload fit it up. */
3196 validate_change (insn, &SET_SRC (old_set), src, 1);
3197 validate_change (insn, &SET_DEST (old_set),
3199 if (! apply_change_group ())
3201 SET_SRC (old_set) = src;
3202 SET_DEST (old_set) = ep->to_rtx;
3212 /* In this case this insn isn't serving a useful purpose. We
3213 will delete it in reload_as_needed once we know that this
3214 elimination is, in fact, being done.
3216 If REPLACE isn't set, we can't delete this insn, but needn't
3217 process it since it won't be used unless something changes. */
3219 delete_dead_insn (insn);
3224 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3225 in the insn is the negative of the offset in FROM. Substitute
3226 (set (reg) (reg to)) for the insn and change its code.
3228 We have to do this here, rather than in eliminate_regs, so that we can
3229 change the insn code. */
3231 if (GET_CODE (SET_SRC (old_set)) == PLUS
3232 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3233 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3234 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3236 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3237 && ep->can_eliminate)
3239 /* We must stop at the first elimination that will be used.
3240 If this one would replace the PLUS with a REG, do it
3241 now. Otherwise, quit the loop and let eliminate_regs
3242 do its normal replacement. */
3243 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3245 /* We assume here that we don't need a PARALLEL of
3246 any CLOBBERs for this assignment. There's not
3247 much we can do if we do need it. */
3248 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3251 INSN_CODE (insn) = -1;
3260 old_asm_operands_vec = 0;
3262 /* Replace the body of this insn with a substituted form. If we changed
3263 something, return non-zero.
3265 If we are replacing a body that was a (set X (plus Y Z)), try to
3266 re-recognize the insn. We do this in case we had a simple addition
3267 but now can do this as a load-address. This saves an insn in this
3270 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3271 if (new_body != old_body)
3273 /* If we aren't replacing things permanently and we changed something,
3274 make another copy to ensure that all the RTL is new. Otherwise
3275 things can go wrong if find_reload swaps commutative operands
3276 and one is inside RTL that has been copied while the other is not. */
3278 /* Don't copy an asm_operands because (1) there's no need and (2)
3279 copy_rtx can't do it properly when there are multiple outputs. */
3280 if (! replace && asm_noperands (old_body) < 0)
3281 new_body = copy_rtx (new_body);
3283 /* If we had a move insn but now we don't, rerecognize it. This will
3284 cause spurious re-recognition if the old move had a PARALLEL since
3285 the new one still will, but we can't call single_set without
3286 having put NEW_BODY into the insn and the re-recognition won't
3287 hurt in this rare case. */
3289 && ((GET_CODE (SET_SRC (old_set)) == REG
3290 && (GET_CODE (new_body) != SET
3291 || GET_CODE (SET_SRC (new_body)) != REG))
3292 /* If this was a load from or store to memory, compare
3293 the MEM in recog_operand to the one in the insn. If they
3294 are not equal, then rerecognize the insn. */
3296 && ((GET_CODE (SET_SRC (old_set)) == MEM
3297 && SET_SRC (old_set) != recog_operand[1])
3298 || (GET_CODE (SET_DEST (old_set)) == MEM
3299 && SET_DEST (old_set) != recog_operand[0])))
3300 /* If this was an add insn before, rerecognize. */
3301 || GET_CODE (SET_SRC (old_set)) == PLUS))
3303 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3304 /* If recognition fails, store the new body anyway.
3305 It's normal to have recognition failures here
3306 due to bizarre memory addresses; reloading will fix them. */
3307 PATTERN (insn) = new_body;
3310 PATTERN (insn) = new_body;
3315 /* Loop through all elimination pairs. See if any have changed.
3317 We also detect a cases where register elimination cannot be done,
3318 namely, if a register would be both changed and referenced outside a MEM
3319 in the resulting insn since such an insn is often undefined and, even if
3320 not, we cannot know what meaning will be given to it. Note that it is
3321 valid to have a register used in an address in an insn that changes it
3322 (presumably with a pre- or post-increment or decrement).
3324 If anything changes, return nonzero. */
3326 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3328 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3329 ep->can_eliminate = 0;
3331 ep->ref_outside_mem = 0;
3333 if (ep->previous_offset != ep->offset)
3338 /* If we changed something, perform elimination in REG_NOTES. This is
3339 needed even when REPLACE is zero because a REG_DEAD note might refer
3340 to a register that we eliminate and could cause a different number
3341 of spill registers to be needed in the final reload pass than in
3343 if (val && REG_NOTES (insn) != 0)
3344 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3352 /* Loop through all elimination pairs.
3353 Recalculate the number not at initial offset.
3355 Compute the maximum offset (minimum offset if the stack does not
3356 grow downward) for each elimination pair. */
3359 update_eliminable_offsets ()
3361 struct elim_table *ep;
3363 num_not_at_initial_offset = 0;
3364 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3366 ep->previous_offset = ep->offset;
3367 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3368 num_not_at_initial_offset++;
3370 #ifdef STACK_GROWS_DOWNWARD
3371 ep->max_offset = MAX (ep->max_offset, ep->offset);
3373 ep->max_offset = MIN (ep->max_offset, ep->offset);
3378 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3379 replacement we currently believe is valid, mark it as not eliminable if X
3380 modifies DEST in any way other than by adding a constant integer to it.
3382 If DEST is the frame pointer, we do nothing because we assume that
3383 all assignments to the hard frame pointer are nonlocal gotos and are being
3384 done at a time when they are valid and do not disturb anything else.
3385 Some machines want to eliminate a fake argument pointer with either the
3386 frame or stack pointer. Assignments to the hard frame pointer must not
3387 prevent this elimination.
3389 Called via note_stores from reload before starting its passes to scan
3390 the insns of the function. */
3393 mark_not_eliminable (dest, x)
3397 register unsigned int i;
3399 /* A SUBREG of a hard register here is just changing its mode. We should
3400 not see a SUBREG of an eliminable hard register, but check just in
3402 if (GET_CODE (dest) == SUBREG)
3403 dest = SUBREG_REG (dest);
3405 if (dest == hard_frame_pointer_rtx)
3408 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3409 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3410 && (GET_CODE (x) != SET
3411 || GET_CODE (SET_SRC (x)) != PLUS
3412 || XEXP (SET_SRC (x), 0) != dest
3413 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3415 reg_eliminate[i].can_eliminate_previous
3416 = reg_eliminate[i].can_eliminate = 0;
3421 /* Reset all offsets on eliminable registers to their initial values. */
3423 set_initial_elim_offsets ()
3427 #ifdef ELIMINABLE_REGS
3428 struct elim_table *ep;
3430 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3432 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3433 ep->previous_offset = ep->offset
3434 = ep->max_offset = ep->initial_offset;
3437 #ifdef INITIAL_FRAME_POINTER_OFFSET
3438 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3440 if (!FRAME_POINTER_REQUIRED)
3442 reg_eliminate[0].initial_offset = 0;
3444 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
3445 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3448 num_not_at_initial_offset = 0;
3450 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3452 /* Set a known offset for each forced label to be at the initial offset
3453 of each elimination. We do this because we assume that all
3454 computed jumps occur from a location where each elimination is
3455 at its initial offset. */
3457 for (x = forced_labels; x; x = XEXP (x, 1))
3459 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3462 /* See if anything that happened changes which eliminations are valid.
3463 For example, on the Sparc, whether or not the frame pointer can
3464 be eliminated can depend on what registers have been used. We need
3465 not check some conditions again (such as flag_omit_frame_pointer)
3466 since they can't have changed. */
3469 update_eliminables (pset)
3472 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3473 int previous_frame_pointer_needed = frame_pointer_needed;
3475 struct elim_table *ep;
3477 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3478 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3479 #ifdef ELIMINABLE_REGS
3480 || ! CAN_ELIMINATE (ep->from, ep->to)
3483 ep->can_eliminate = 0;
3485 /* Look for the case where we have discovered that we can't replace
3486 register A with register B and that means that we will now be
3487 trying to replace register A with register C. This means we can
3488 no longer replace register C with register B and we need to disable
3489 such an elimination, if it exists. This occurs often with A == ap,
3490 B == sp, and C == fp. */
3492 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3494 struct elim_table *op;
3495 register int new_to = -1;
3497 if (! ep->can_eliminate && ep->can_eliminate_previous)
3499 /* Find the current elimination for ep->from, if there is a
3501 for (op = reg_eliminate;
3502 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3503 if (op->from == ep->from && op->can_eliminate)
3509 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3511 for (op = reg_eliminate;
3512 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3513 if (op->from == new_to && op->to == ep->to)
3514 op->can_eliminate = 0;
3518 /* See if any registers that we thought we could eliminate the previous
3519 time are no longer eliminable. If so, something has changed and we
3520 must spill the register. Also, recompute the number of eliminable
3521 registers and see if the frame pointer is needed; it is if there is
3522 no elimination of the frame pointer that we can perform. */
3524 frame_pointer_needed = 1;
3525 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3527 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3528 && ep->to != HARD_FRAME_POINTER_REGNUM)
3529 frame_pointer_needed = 0;
3531 if (! ep->can_eliminate && ep->can_eliminate_previous)
3533 ep->can_eliminate_previous = 0;
3534 SET_HARD_REG_BIT (*pset, ep->from);
3539 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3540 /* If we didn't need a frame pointer last time, but we do now, spill
3541 the hard frame pointer. */
3542 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3543 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3547 /* Initialize the table of registers to eliminate. */
3551 struct elim_table *ep;
3553 /* Does this function require a frame pointer? */
3555 frame_pointer_needed = (! flag_omit_frame_pointer
3556 #ifdef EXIT_IGNORE_STACK
3557 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3558 and restore sp for alloca. So we can't eliminate
3559 the frame pointer in that case. At some point,
3560 we should improve this by emitting the
3561 sp-adjusting insns for this case. */
3562 || (current_function_calls_alloca
3563 && EXIT_IGNORE_STACK)
3565 || FRAME_POINTER_REQUIRED);
3569 #ifdef ELIMINABLE_REGS
3570 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3572 ep->can_eliminate = ep->can_eliminate_previous
3573 = (CAN_ELIMINATE (ep->from, ep->to)
3574 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3577 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3578 = ! frame_pointer_needed;
3581 /* Count the number of eliminable registers and build the FROM and TO
3582 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3583 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3584 We depend on this. */
3585 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3587 num_eliminable += ep->can_eliminate;
3588 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3589 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3593 /* Kick all pseudos out of hard register REGNO.
3594 If DUMPFILE is nonzero, log actions taken on that file.
3596 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3597 because we found we can't eliminate some register. In the case, no pseudos
3598 are allowed to be in the register, even if they are only in a block that
3599 doesn't require spill registers, unlike the case when we are spilling this
3600 hard reg to produce another spill register.
3602 Return nonzero if any pseudos needed to be kicked out. */
3605 spill_hard_reg (regno, dumpfile, cant_eliminate)
3614 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3615 regs_ever_live[regno] = 1;
3618 /* Spill every pseudo reg that was allocated to this reg
3619 or to something that overlaps this reg. */
3621 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3622 if (reg_renumber[i] >= 0
3623 && reg_renumber[i] <= regno
3625 + HARD_REGNO_NREGS (reg_renumber[i],
3626 PSEUDO_REGNO_MODE (i))
3628 SET_REGNO_REG_SET (spilled_pseudos, i);
3631 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3632 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3634 ior_hard_reg_set (set1, set2)
3635 HARD_REG_SET *set1, *set2;
3637 IOR_HARD_REG_SET (*set1, *set2);
3640 /* After find_reload_regs has been run for all insn that need reloads,
3641 and/or spill_hard_regs was called, this function is used to actually
3642 spill pseudo registers and try to reallocate them. It also sets up the
3643 spill_regs array for use by choose_reload_regs. */
3646 finish_spills (global, dumpfile)
3650 struct insn_chain *chain;
3651 int something_changed = 0;
3654 /* Build the spill_regs array for the function. */
3655 /* If there are some registers still to eliminate and one of the spill regs
3656 wasn't ever used before, additional stack space may have to be
3657 allocated to store this register. Thus, we may have changed the offset
3658 between the stack and frame pointers, so mark that something has changed.
3660 One might think that we need only set VAL to 1 if this is a call-used
3661 register. However, the set of registers that must be saved by the
3662 prologue is not identical to the call-used set. For example, the
3663 register used by the call insn for the return PC is a call-used register,
3664 but must be saved by the prologue. */
3667 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3668 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3670 spill_reg_order[i] = n_spills;
3671 spill_regs[n_spills++] = i;
3672 if (num_eliminable && ! regs_ever_live[i])
3673 something_changed = 1;
3674 regs_ever_live[i] = 1;
3677 spill_reg_order[i] = -1;
3679 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3680 if (REGNO_REG_SET_P (spilled_pseudos, i))
3682 /* Record the current hard register the pseudo is allocated to in
3683 pseudo_previous_regs so we avoid reallocating it to the same
3684 hard reg in a later pass. */
3685 if (reg_renumber[i] < 0)
3687 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3688 /* Mark it as no longer having a hard register home. */
3689 reg_renumber[i] = -1;
3690 /* We will need to scan everything again. */
3691 something_changed = 1;
3694 /* Retry global register allocation if possible. */
3697 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3698 /* For every insn that needs reloads, set the registers used as spill
3699 regs in pseudo_forbidden_regs for every pseudo live across the
3701 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3703 EXECUTE_IF_SET_IN_REG_SET
3704 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3706 ior_hard_reg_set (pseudo_forbidden_regs + i,
3707 &chain->used_spill_regs);
3709 EXECUTE_IF_SET_IN_REG_SET
3710 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3712 ior_hard_reg_set (pseudo_forbidden_regs + i,
3713 &chain->used_spill_regs);
3717 /* Retry allocating the spilled pseudos. For each reg, merge the
3718 various reg sets that indicate which hard regs can't be used,
3719 and call retry_global_alloc.
3720 We change spill_pseudos here to only contain pseudos that did not
3721 get a new hard register. */
3722 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3723 if (reg_old_renumber[i] != reg_renumber[i])
3725 HARD_REG_SET forbidden;
3726 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3727 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3728 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3729 retry_global_alloc (i, forbidden);
3730 if (reg_renumber[i] >= 0)
3731 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3735 /* Fix up the register information in the insn chain.
3736 This involves deleting those of the spilled pseudos which did not get
3737 a new hard register home from the live_{before,after} sets. */
3738 for (chain = reload_insn_chain; chain; chain = chain->next)
3740 HARD_REG_SET used_by_pseudos;
3741 HARD_REG_SET used_by_pseudos2;
3743 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3744 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3746 /* Mark any unallocated hard regs as available for spills. That
3747 makes inheritance work somewhat better. */
3748 if (chain->need_reload)
3750 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3751 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3752 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3754 /* Save the old value for the sanity test below. */
3755 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3757 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3758 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3759 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3760 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3762 /* Make sure we only enlarge the set. */
3763 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3769 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3770 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3772 int regno = reg_renumber[i];
3773 if (reg_old_renumber[i] == regno)
3776 alter_reg (i, reg_old_renumber[i]);
3777 reg_old_renumber[i] = regno;
3781 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3783 fprintf (dumpfile, " Register %d now in %d.\n\n",
3784 i, reg_renumber[i]);
3788 return something_changed;
3791 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3792 Also mark any hard registers used to store user variables as
3793 forbidden from being used for spill registers. */
3796 scan_paradoxical_subregs (x)
3801 register enum rtx_code code = GET_CODE (x);
3807 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3808 && REG_USERVAR_P (x))
3809 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3825 if (GET_CODE (SUBREG_REG (x)) == REG
3826 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3827 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3828 = GET_MODE_SIZE (GET_MODE (x));
3835 fmt = GET_RTX_FORMAT (code);
3836 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3839 scan_paradoxical_subregs (XEXP (x, i));
3840 else if (fmt[i] == 'E')
3843 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3844 scan_paradoxical_subregs (XVECEXP (x, i, j));
3850 hard_reg_use_compare (p1p, p2p)
3851 const GENERIC_PTR p1p;
3852 const GENERIC_PTR p2p;
3854 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
3855 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
3856 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
3857 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
3859 return p1->regno - p2->regno;
3864 if (p1->uses > p2->uses)
3866 if (p1->uses < p2->uses)
3868 /* If regs are equally good, sort by regno,
3869 so that the results of qsort leave nothing to chance. */
3870 return p1->regno - p2->regno;
3873 /* Used for communication between order_regs_for_reload and count_pseudo.
3874 Used to avoid counting one pseudo twice. */
3875 static regset pseudos_counted;
3877 /* Update the costs in N_USES, considering that pseudo REG is live. */
3879 count_pseudo (n_uses, reg)
3880 struct hard_reg_n_uses *n_uses;
3883 int r = reg_renumber[reg];
3886 if (REGNO_REG_SET_P (pseudos_counted, reg))
3888 SET_REGNO_REG_SET (pseudos_counted, reg);
3893 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
3895 n_uses[r++].uses += REG_N_REFS (reg);
3897 /* Choose the order to consider regs for use as reload registers
3898 based on how much trouble would be caused by spilling one.
3899 Store them in order of decreasing preference in potential_reload_regs. */
3902 order_regs_for_reload (chain)
3903 struct insn_chain *chain;
3907 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3909 pseudos_counted = ALLOCA_REG_SET ();
3911 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
3913 /* Count number of uses of each hard reg by pseudo regs allocated to it
3914 and then order them by decreasing use. */
3916 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3920 hard_reg_n_uses[i].regno = i;
3921 hard_reg_n_uses[i].uses = 0;
3923 /* Test the various reasons why we can't use a register for
3924 spilling in this insn. */
3926 || REGNO_REG_SET_P (chain->live_before, i)
3927 || REGNO_REG_SET_P (chain->live_after, i))
3929 SET_HARD_REG_BIT (bad_spill_regs, i);
3933 /* Now find out which pseudos are allocated to it, and update
3935 CLEAR_REG_SET (pseudos_counted);
3937 EXECUTE_IF_SET_IN_REG_SET
3938 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
3940 count_pseudo (hard_reg_n_uses, j);
3942 EXECUTE_IF_SET_IN_REG_SET
3943 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
3945 count_pseudo (hard_reg_n_uses, j);
3949 FREE_REG_SET (pseudos_counted);
3951 /* Prefer registers not so far used, for use in temporary loading.
3952 Among them, if REG_ALLOC_ORDER is defined, use that order.
3953 Otherwise, prefer registers not preserved by calls. */
3955 #ifdef REG_ALLOC_ORDER
3956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3958 int regno = reg_alloc_order[i];
3960 if (hard_reg_n_uses[regno].uses == 0
3961 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
3962 potential_reload_regs[o++] = regno;
3965 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3967 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
3968 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
3969 potential_reload_regs[o++] = i;
3971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3973 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
3974 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
3975 potential_reload_regs[o++] = i;
3979 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3980 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3982 /* Now add the regs that are already used,
3983 preferring those used less often. The fixed and otherwise forbidden
3984 registers will be at the end of this list. */
3986 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3987 if (hard_reg_n_uses[i].uses != 0
3988 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
3989 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3990 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3991 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
3992 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3995 /* Reload pseudo-registers into hard regs around each insn as needed.
3996 Additional register load insns are output before the insn that needs it
3997 and perhaps store insns after insns that modify the reloaded pseudo reg.
3999 reg_last_reload_reg and reg_reloaded_contents keep track of
4000 which registers are already available in reload registers.
4001 We update these for the reloads that we perform,
4002 as the insns are scanned. */
4005 reload_as_needed (live_known)
4008 struct insn_chain *chain;
4012 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4013 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4014 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4015 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4016 reg_has_output_reload = (char *) alloca (max_regno);
4017 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4019 /* Reset all offsets on eliminable registers to their initial values. */
4020 #ifdef ELIMINABLE_REGS
4021 for (i = 0; i < (int) NUM_ELIMINABLE_REGS; i++)
4023 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
4024 reg_eliminate[i].initial_offset);
4025 reg_eliminate[i].previous_offset
4026 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
4029 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
4030 reg_eliminate[0].previous_offset
4031 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
4034 num_not_at_initial_offset = 0;
4036 for (chain = reload_insn_chain; chain; chain = chain->next)
4039 rtx insn = chain->insn;
4040 rtx old_next = NEXT_INSN (insn);
4042 /* If we pass a label, copy the offsets from the label information
4043 into the current offsets of each elimination. */
4044 if (GET_CODE (insn) == CODE_LABEL)
4046 num_not_at_initial_offset = 0;
4047 for (i = 0; i < (int) NUM_ELIMINABLE_REGS; i++)
4049 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
4050 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
4051 if (reg_eliminate[i].can_eliminate
4052 && (reg_eliminate[i].offset
4053 != reg_eliminate[i].initial_offset))
4054 num_not_at_initial_offset++;
4058 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4060 rtx oldpat = PATTERN (insn);
4062 /* If this is a USE and CLOBBER of a MEM, ensure that any
4063 references to eliminable registers have been removed. */
4065 if ((GET_CODE (PATTERN (insn)) == USE
4066 || GET_CODE (PATTERN (insn)) == CLOBBER)
4067 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4068 XEXP (XEXP (PATTERN (insn), 0), 0)
4069 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4070 GET_MODE (XEXP (PATTERN (insn), 0)),
4073 /* If we need to do register elimination processing, do so.
4074 This might delete the insn, in which case we are done. */
4075 if (num_eliminable && chain->need_elim)
4077 eliminate_regs_in_insn (insn, 1);
4078 if (GET_CODE (insn) == NOTE)
4080 update_eliminable_offsets ();
4085 /* If need_elim is nonzero but need_reload is zero, one might think
4086 that we could simply set n_reloads to 0. However, find_reloads
4087 could have done some manipulation of the insn (such as swapping
4088 commutative operands), and these manipulations are lost during
4089 the first pass for every insn that needs register elimination.
4090 So the actions of find_reloads must be redone here. */
4092 if (! chain->need_elim && ! chain->need_reload
4093 && ! chain->need_operand_change)
4095 /* First find the pseudo regs that must be reloaded for this insn.
4096 This info is returned in the tables reload_... (see reload.h).
4097 Also modify the body of INSN by substituting RELOAD
4098 rtx's for those pseudo regs. */
4101 bzero (reg_has_output_reload, max_regno);
4102 CLEAR_HARD_REG_SET (reg_is_output_reload);
4104 find_reloads (insn, 1, spill_indirect_levels, live_known,
4108 if (num_eliminable && chain->need_elim)
4109 update_eliminable_offsets ();
4113 rtx next = NEXT_INSN (insn);
4116 prev = PREV_INSN (insn);
4118 /* Now compute which reload regs to reload them into. Perhaps
4119 reusing reload regs from previous insns, or else output
4120 load insns to reload them. Maybe output store insns too.
4121 Record the choices of reload reg in reload_reg_rtx. */
4122 choose_reload_regs (chain);
4124 /* Merge any reloads that we didn't combine for fear of
4125 increasing the number of spill registers needed but now
4126 discover can be safely merged. */
4127 if (SMALL_REGISTER_CLASSES)
4128 merge_assigned_reloads (insn);
4130 /* Generate the insns to reload operands into or out of
4131 their reload regs. */
4132 emit_reload_insns (chain);
4134 /* Substitute the chosen reload regs from reload_reg_rtx
4135 into the insn's body (or perhaps into the bodies of other
4136 load and store insn that we just made for reloading
4137 and that we moved the structure into). */
4140 /* If this was an ASM, make sure that all the reload insns
4141 we have generated are valid. If not, give an error
4144 if (asm_noperands (PATTERN (insn)) >= 0)
4145 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4146 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4147 && (recog_memoized (p) < 0
4148 || (insn_extract (p),
4149 ! constrain_operands (INSN_CODE (p), 1))))
4151 error_for_asm (insn,
4152 "`asm' operand requires impossible reload");
4154 NOTE_SOURCE_FILE (p) = 0;
4155 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4158 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4159 is no longer validly lying around to save a future reload.
4160 Note that this does not detect pseudos that were reloaded
4161 for this insn in order to be stored in
4162 (obeying register constraints). That is correct; such reload
4163 registers ARE still valid. */
4164 note_stores (oldpat, forget_old_reloads_1);
4166 /* There may have been CLOBBER insns placed after INSN. So scan
4167 between INSN and NEXT and use them to forget old reloads. */
4168 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4169 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4170 note_stores (PATTERN (x), forget_old_reloads_1);
4173 /* Likewise for regs altered by auto-increment in this insn.
4174 REG_INC notes have been changed by reloading:
4175 find_reloads_address_1 records substitutions for them,
4176 which have been performed by subst_reloads above. */
4177 for (i = n_reloads - 1; i >= 0; i--)
4179 rtx in_reg = reload_in_reg[i];
4182 enum rtx_code code = GET_CODE (in_reg);
4183 /* PRE_INC / PRE_DEC will have the reload register ending up
4184 with the same value as the stack slot, but that doesn't
4185 hold true for POST_INC / POST_DEC. Either we have to
4186 convert the memory access to a true POST_INC / POST_DEC,
4187 or we can't use the reload register for inheritance. */
4188 if ((code == POST_INC || code == POST_DEC)
4189 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4190 REGNO (reload_reg_rtx[i]))
4191 /* Make sure it is the inc/dec pseudo, and not
4192 some other (e.g. output operand) pseudo. */
4193 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4194 == REGNO (XEXP (in_reg, 0))))
4197 rtx reload_reg = reload_reg_rtx[i];
4198 enum machine_mode mode = GET_MODE (reload_reg);
4202 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4204 /* We really want to ignore REG_INC notes here, so
4205 use PATTERN (p) as argument to reg_set_p . */
4206 if (reg_set_p (reload_reg, PATTERN (p)))
4208 n = count_occurrences (PATTERN (p), reload_reg);
4212 n = validate_replace_rtx (reload_reg,
4213 gen_rtx (code, mode,
4218 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4221 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4225 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4226 /* Likewise for regs altered by auto-increment in this insn.
4227 But note that the reg-notes are not changed by reloading:
4228 they still contain the pseudo-regs, not the spill regs. */
4229 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4230 if (REG_NOTE_KIND (x) == REG_INC)
4232 /* See if this pseudo reg was reloaded in this insn.
4233 If so, its last-reload info is still valid
4234 because it is based on this insn's reload. */
4235 for (i = 0; i < n_reloads; i++)
4236 if (reload_out[i] == XEXP (x, 0))
4240 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4245 /* A reload reg's contents are unknown after a label. */
4246 if (GET_CODE (insn) == CODE_LABEL)
4247 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4249 /* Don't assume a reload reg is still good after a call insn
4250 if it is a call-used reg. */
4251 else if (GET_CODE (insn) == CALL_INSN)
4252 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4254 /* In case registers overlap, allow certain insns to invalidate
4255 particular hard registers. */
4257 #ifdef INSN_CLOBBERS_REGNO_P
4258 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4259 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4260 && INSN_CLOBBERS_REGNO_P (insn, i))
4261 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4270 /* Discard all record of any value reloaded from X,
4271 or reloaded in X from someplace else;
4272 unless X is an output reload reg of the current insn.
4274 X may be a hard reg (the reload reg)
4275 or it may be a pseudo reg that was reloaded from. */
4278 forget_old_reloads_1 (x, ignored)
4280 rtx ignored ATTRIBUTE_UNUSED;
4286 /* note_stores does give us subregs of hard regs. */
4287 while (GET_CODE (x) == SUBREG)
4289 offset += SUBREG_WORD (x);
4293 if (GET_CODE (x) != REG)
4296 regno = REGNO (x) + offset;
4298 if (regno >= FIRST_PSEUDO_REGISTER)
4303 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4304 /* Storing into a spilled-reg invalidates its contents.
4305 This can happen if a block-local pseudo is allocated to that reg
4306 and it wasn't spilled because this block's total need is 0.
4307 Then some insn might have an optional reload and use this reg. */
4308 for (i = 0; i < nr; i++)
4309 /* But don't do this if the reg actually serves as an output
4310 reload reg in the current instruction. */
4312 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4313 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4316 /* Since value of X has changed,
4317 forget any value previously copied from it. */
4320 /* But don't forget a copy if this is the output reload
4321 that establishes the copy's validity. */
4322 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4323 reg_last_reload_reg[regno + nr] = 0;
4326 /* For each reload, the mode of the reload register. */
4327 static enum machine_mode reload_mode[MAX_RELOADS];
4329 /* For each reload, the largest number of registers it will require. */
4330 static int reload_nregs[MAX_RELOADS];
4332 /* Comparison function for qsort to decide which of two reloads
4333 should be handled first. *P1 and *P2 are the reload numbers. */
4336 reload_reg_class_lower (r1p, r2p)
4337 const GENERIC_PTR r1p;
4338 const GENERIC_PTR r2p;
4340 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4343 /* Consider required reloads before optional ones. */
4344 t = reload_optional[r1] - reload_optional[r2];
4348 /* Count all solitary classes before non-solitary ones. */
4349 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4350 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4354 /* Aside from solitaires, consider all multi-reg groups first. */
4355 t = reload_nregs[r2] - reload_nregs[r1];
4359 /* Consider reloads in order of increasing reg-class number. */
4360 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4364 /* If reloads are equally urgent, sort by reload number,
4365 so that the results of qsort leave nothing to chance. */
4369 /* The following HARD_REG_SETs indicate when each hard register is
4370 used for a reload of various parts of the current insn. */
4372 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4373 static HARD_REG_SET reload_reg_used;
4374 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4375 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4376 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4377 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4378 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4379 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4380 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4381 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4382 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4383 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4384 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4385 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4386 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4387 static HARD_REG_SET reload_reg_used_in_op_addr;
4388 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4389 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4390 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4391 static HARD_REG_SET reload_reg_used_in_insn;
4392 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4393 static HARD_REG_SET reload_reg_used_in_other_addr;
4395 /* If reg is in use as a reload reg for any sort of reload. */
4396 static HARD_REG_SET reload_reg_used_at_all;
4398 /* If reg is use as an inherited reload. We just mark the first register
4400 static HARD_REG_SET reload_reg_used_for_inherit;
4402 /* Records which hard regs are allocated to a pseudo during any point of the
4404 static HARD_REG_SET reg_used_by_pseudo;
4406 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4407 TYPE. MODE is used to indicate how many consecutive regs are
4411 mark_reload_reg_in_use (regno, opnum, type, mode)
4414 enum reload_type type;
4415 enum machine_mode mode;
4417 int nregs = HARD_REGNO_NREGS (regno, mode);
4420 for (i = regno; i < nregs + regno; i++)
4425 SET_HARD_REG_BIT (reload_reg_used, i);
4428 case RELOAD_FOR_INPUT_ADDRESS:
4429 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4432 case RELOAD_FOR_INPADDR_ADDRESS:
4433 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4436 case RELOAD_FOR_OUTPUT_ADDRESS:
4437 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4440 case RELOAD_FOR_OUTADDR_ADDRESS:
4441 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4444 case RELOAD_FOR_OPERAND_ADDRESS:
4445 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4448 case RELOAD_FOR_OPADDR_ADDR:
4449 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4452 case RELOAD_FOR_OTHER_ADDRESS:
4453 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4456 case RELOAD_FOR_INPUT:
4457 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4460 case RELOAD_FOR_OUTPUT:
4461 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4464 case RELOAD_FOR_INSN:
4465 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4469 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4473 /* Similarly, but show REGNO is no longer in use for a reload. */
4476 clear_reload_reg_in_use (regno, opnum, type, mode)
4479 enum reload_type type;
4480 enum machine_mode mode;
4482 int nregs = HARD_REGNO_NREGS (regno, mode);
4483 int start_regno, end_regno;
4485 /* A complication is that for some reload types, inheritance might
4486 allow multiple reloads of the same types to share a reload register.
4487 We set check_opnum if we have to check only reloads with the same
4488 operand number, and check_any if we have to check all reloads. */
4489 int check_opnum = 0;
4491 HARD_REG_SET *used_in_set;
4496 used_in_set = &reload_reg_used;
4499 case RELOAD_FOR_INPUT_ADDRESS:
4500 used_in_set = &reload_reg_used_in_input_addr[opnum];
4503 case RELOAD_FOR_INPADDR_ADDRESS:
4505 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4508 case RELOAD_FOR_OUTPUT_ADDRESS:
4509 used_in_set = &reload_reg_used_in_output_addr[opnum];
4512 case RELOAD_FOR_OUTADDR_ADDRESS:
4514 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4517 case RELOAD_FOR_OPERAND_ADDRESS:
4518 used_in_set = &reload_reg_used_in_op_addr;
4521 case RELOAD_FOR_OPADDR_ADDR:
4523 used_in_set = &reload_reg_used_in_op_addr_reload;
4526 case RELOAD_FOR_OTHER_ADDRESS:
4527 used_in_set = &reload_reg_used_in_other_addr;
4531 case RELOAD_FOR_INPUT:
4532 used_in_set = &reload_reg_used_in_input[opnum];
4535 case RELOAD_FOR_OUTPUT:
4536 used_in_set = &reload_reg_used_in_output[opnum];
4539 case RELOAD_FOR_INSN:
4540 used_in_set = &reload_reg_used_in_insn;
4545 /* We resolve conflicts with remaining reloads of the same type by
4546 excluding the intervals of of reload registers by them from the
4547 interval of freed reload registers. Since we only keep track of
4548 one set of interval bounds, we might have to exclude somewhat
4549 more then what would be necessary if we used a HARD_REG_SET here.
4550 But this should only happen very infrequently, so there should
4551 be no reason to worry about it. */
4553 start_regno = regno;
4554 end_regno = regno + nregs;
4555 if (check_opnum || check_any)
4557 for (i = n_reloads - 1; i >= 0; i--)
4559 if (reload_when_needed[i] == type
4560 && (check_any || reload_opnum[i] == opnum)
4561 && reload_reg_rtx[i])
4563 int conflict_start = true_regnum (reload_reg_rtx[i]);
4566 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4568 /* If there is an overlap with the first to-be-freed register,
4569 adjust the interval start. */
4570 if (conflict_start <= start_regno && conflict_end > start_regno)
4571 start_regno = conflict_end;
4572 /* Otherwise, if there is a conflict with one of the other
4573 to-be-freed registers, adjust the interval end. */
4574 if (conflict_start > start_regno && conflict_start < end_regno)
4575 end_regno = conflict_start;
4579 for (i = start_regno; i < end_regno; i++)
4580 CLEAR_HARD_REG_BIT (*used_in_set, i);
4583 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4584 specified by OPNUM and TYPE. */
4587 reload_reg_free_p (regno, opnum, type)
4590 enum reload_type type;
4594 /* In use for a RELOAD_OTHER means it's not available for anything. */
4595 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4601 /* In use for anything means we can't use it for RELOAD_OTHER. */
4602 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4603 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4604 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4607 for (i = 0; i < reload_n_operands; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4611 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4612 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4613 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4618 case RELOAD_FOR_INPUT:
4619 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4626 /* If it is used for some other input, can't use it. */
4627 for (i = 0; i < reload_n_operands; i++)
4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4631 /* If it is used in a later operand's address, can't use it. */
4632 for (i = opnum + 1; i < reload_n_operands; i++)
4633 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4634 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4639 case RELOAD_FOR_INPUT_ADDRESS:
4640 /* Can't use a register if it is used for an input address for this
4641 operand or used as an input in an earlier one. */
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4646 for (i = 0; i < opnum; i++)
4647 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4652 case RELOAD_FOR_INPADDR_ADDRESS:
4653 /* Can't use a register if it is used for an input address
4654 for this operand or used as an input in an earlier
4656 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4659 for (i = 0; i < opnum; i++)
4660 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4665 case RELOAD_FOR_OUTPUT_ADDRESS:
4666 /* Can't use a register if it is used for an output address for this
4667 operand or used as an output in this or a later operand. */
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4671 for (i = opnum; i < reload_n_operands; i++)
4672 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4677 case RELOAD_FOR_OUTADDR_ADDRESS:
4678 /* Can't use a register if it is used for an output address
4679 for this operand or used as an output in this or a
4681 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4684 for (i = opnum; i < reload_n_operands; i++)
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4690 case RELOAD_FOR_OPERAND_ADDRESS:
4691 for (i = 0; i < reload_n_operands; i++)
4692 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4695 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4696 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4698 case RELOAD_FOR_OPADDR_ADDR:
4699 for (i = 0; i < reload_n_operands; i++)
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4703 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4705 case RELOAD_FOR_OUTPUT:
4706 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4707 outputs, or an operand address for this or an earlier output. */
4708 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4711 for (i = 0; i < reload_n_operands; i++)
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4715 for (i = 0; i <= opnum; i++)
4716 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4717 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4722 case RELOAD_FOR_INSN:
4723 for (i = 0; i < reload_n_operands; i++)
4724 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4725 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4728 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4729 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4731 case RELOAD_FOR_OTHER_ADDRESS:
4732 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4737 /* Return 1 if the value in reload reg REGNO, as used by a reload
4738 needed for the part of the insn specified by OPNUM and TYPE,
4739 is not in use for a reload in any prior part of the insn.
4741 We can assume that the reload reg was already tested for availability
4742 at the time it is needed, and we should not check this again,
4743 in case the reg has already been marked in use.
4745 However, if EQUIV is set, we are checking the availability of a register
4746 holding an equivalence to the value to be loaded into the reload register,
4747 not the availability of the reload register itself.
4749 This is still less stringent than what reload_reg_free_p checks; for
4750 example, compare the checks for RELOAD_OTHER. */
4753 reload_reg_free_before_p (regno, opnum, type, equiv)
4756 enum reload_type type;
4761 /* The code to handle EQUIV below is wrong.
4763 If we wnat to know if a value in a particular reload register is available
4764 at a particular point in time during reloading, we must check *all*
4765 prior reloads to see if they clobber the value.
4767 Note this is significantly different from determining when a register is
4768 free for usage in a reload!
4770 This change is temporary. It will go away. */
4776 case RELOAD_FOR_OTHER_ADDRESS:
4777 /* These always come first. */
4778 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno))
4783 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4785 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4787 /* If this use is for part of the insn,
4788 check the reg is not in use for any prior part. It is tempting
4789 to try to do this by falling through from objecs that occur
4790 later in the insn to ones that occur earlier, but that will not
4791 correctly take into account the fact that here we MUST ignore
4792 things that would prevent the register from being allocated in
4793 the first place, since we know that it was allocated. */
4795 case RELOAD_FOR_OUTPUT_ADDRESS:
4797 && TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4799 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4800 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4802 /* ... fall through ... */
4803 case RELOAD_FOR_OUTADDR_ADDRESS:
4805 && (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)
4806 || TEST_HARD_REG_BIT (reload_reg_used, regno)))
4808 /* Earlier reloads are for earlier outputs or their addresses,
4809 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4810 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4812 for (i = 0; i < opnum; i++)
4813 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4817 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4820 for (i = 0; i < reload_n_operands; i++)
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4824 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4827 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4828 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4829 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4830 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4832 case RELOAD_FOR_OUTPUT:
4833 case RELOAD_FOR_INSN:
4834 /* There is no reason to call this function for output reloads, thus
4835 anything we'd put here wouldn't be tested. So just abort. */
4838 case RELOAD_FOR_OPERAND_ADDRESS:
4839 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4842 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4846 /* ... fall through ... */
4848 case RELOAD_FOR_OPADDR_ADDR:
4851 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4852 || TEST_HARD_REG_BIT (reload_reg_used, regno))
4854 for (i = 0; i < reload_n_operands; i++)
4855 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4858 /* These can't conflict with inputs, or each other, so all we have to
4859 test is input addresses and the addresses of OTHER items. */
4861 for (i = 0; i < reload_n_operands; i++)
4862 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4863 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4866 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4868 case RELOAD_FOR_INPUT:
4869 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4872 /* The only things earlier are the address for this and
4873 earlier inputs, other inputs (which we know we don't conflict
4874 with), and addresses of RELOAD_OTHER objects.
4875 We can ignore the conflict with addresses of this operand, since
4876 when we inherit this operand, its address reloads are discarded. */
4878 for (i = 0; i < opnum; i++)
4879 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4880 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4883 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4885 case RELOAD_FOR_INPUT_ADDRESS:
4886 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4889 /* ... fall through ... */
4890 case RELOAD_FOR_INPADDR_ADDRESS:
4891 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4894 /* Similarly, all we have to check is for use in earlier inputs'
4896 for (i = 0; i < opnum; i++)
4897 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4898 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4901 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4906 /* Return 1 if the value in reload reg REGNO, as used by a reload
4907 needed for the part of the insn specified by OPNUM and TYPE,
4908 is still available in REGNO at the end of the insn.
4910 We can assume that the reload reg was already tested for availability
4911 at the time it is needed, and we should not check this again,
4912 in case the reg has already been marked in use. */
4915 reload_reg_reaches_end_p (regno, opnum, type)
4918 enum reload_type type;
4925 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4926 its value must reach the end. */
4929 /* If this use is for part of the insn,
4930 its value reaches if no subsequent part uses the same register.
4931 Just like the above function, don't try to do this with lots
4934 case RELOAD_FOR_OTHER_ADDRESS:
4935 /* Here we check for everything else, since these don't conflict
4936 with anything else and everything comes later. */
4938 for (i = 0; i < reload_n_operands; i++)
4939 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4940 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4941 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4942 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4943 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4944 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4947 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4948 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4949 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4951 case RELOAD_FOR_INPUT_ADDRESS:
4952 case RELOAD_FOR_INPADDR_ADDRESS:
4953 /* Similar, except that we check only for this and subsequent inputs
4954 and the address of only subsequent inputs and we do not need
4955 to check for RELOAD_OTHER objects since they are known not to
4958 for (i = opnum; i < reload_n_operands; i++)
4959 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4962 for (i = opnum + 1; i < reload_n_operands; i++)
4963 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4964 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4967 for (i = 0; i < reload_n_operands; i++)
4968 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4969 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4970 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4973 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4976 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4977 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4979 case RELOAD_FOR_INPUT:
4980 /* Similar to input address, except we start at the next operand for
4981 both input and input address and we do not check for
4982 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4985 for (i = opnum + 1; i < reload_n_operands; i++)
4986 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4987 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4988 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4991 /* ... fall through ... */
4993 case RELOAD_FOR_OPERAND_ADDRESS:
4994 /* Check outputs and their addresses. */
4996 for (i = 0; i < reload_n_operands; i++)
4997 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4998 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4999 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5004 case RELOAD_FOR_OPADDR_ADDR:
5005 for (i = 0; i < reload_n_operands; i++)
5006 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5007 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5008 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5011 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5012 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5014 case RELOAD_FOR_INSN:
5015 /* These conflict with other outputs with RELOAD_OTHER. So
5016 we need only check for output addresses. */
5020 /* ... fall through ... */
5022 case RELOAD_FOR_OUTPUT:
5023 case RELOAD_FOR_OUTPUT_ADDRESS:
5024 case RELOAD_FOR_OUTADDR_ADDRESS:
5025 /* We already know these can't conflict with a later output. So the
5026 only thing to check are later output addresses. */
5027 for (i = opnum + 1; i < reload_n_operands; i++)
5028 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5029 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5038 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5041 This function uses the same algorithm as reload_reg_free_p above. */
5044 reloads_conflict (r1, r2)
5047 enum reload_type r1_type = reload_when_needed[r1];
5048 enum reload_type r2_type = reload_when_needed[r2];
5049 int r1_opnum = reload_opnum[r1];
5050 int r2_opnum = reload_opnum[r2];
5052 /* RELOAD_OTHER conflicts with everything. */
5053 if (r2_type == RELOAD_OTHER)
5056 /* Otherwise, check conflicts differently for each type. */
5060 case RELOAD_FOR_INPUT:
5061 return (r2_type == RELOAD_FOR_INSN
5062 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5063 || r2_type == RELOAD_FOR_OPADDR_ADDR
5064 || r2_type == RELOAD_FOR_INPUT
5065 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5066 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5067 && r2_opnum > r1_opnum));
5069 case RELOAD_FOR_INPUT_ADDRESS:
5070 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5071 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5073 case RELOAD_FOR_INPADDR_ADDRESS:
5074 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5075 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5077 case RELOAD_FOR_OUTPUT_ADDRESS:
5078 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5079 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5081 case RELOAD_FOR_OUTADDR_ADDRESS:
5082 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5083 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5085 case RELOAD_FOR_OPERAND_ADDRESS:
5086 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5087 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5089 case RELOAD_FOR_OPADDR_ADDR:
5090 return (r2_type == RELOAD_FOR_INPUT
5091 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5093 case RELOAD_FOR_OUTPUT:
5094 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5095 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5096 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5097 && r2_opnum >= r1_opnum));
5099 case RELOAD_FOR_INSN:
5100 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5101 || r2_type == RELOAD_FOR_INSN
5102 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5104 case RELOAD_FOR_OTHER_ADDRESS:
5105 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5115 /* Vector of reload-numbers showing the order in which the reloads should
5117 short reload_order[MAX_RELOADS];
5119 /* Indexed by reload number, 1 if incoming value
5120 inherited from previous insns. */
5121 char reload_inherited[MAX_RELOADS];
5123 /* For an inherited reload, this is the insn the reload was inherited from,
5124 if we know it. Otherwise, this is 0. */
5125 rtx reload_inheritance_insn[MAX_RELOADS];
5127 /* If non-zero, this is a place to get the value of the reload,
5128 rather than using reload_in. */
5129 rtx reload_override_in[MAX_RELOADS];
5131 /* For each reload, the hard register number of the register used,
5132 or -1 if we did not need a register for this reload. */
5133 int reload_spill_index[MAX_RELOADS];
5135 /* Return 1 if the value in reload reg REGNO, as used by a reload
5136 needed for the part of the insn specified by OPNUM and TYPE,
5137 may be used to load VALUE into it.
5139 Other read-only reloads with the same value do not conflict
5140 unless OUT is non-zero and these other reloads have to live while
5141 output reloads live.
5143 RELOADNUM is the number of the reload we want to load this value for;
5144 a reload does not conflict with itself.
5146 The caller has to make sure that there is no conflict with the return
5149 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum)
5152 enum reload_type type;
5159 /* We use some pseudo 'time' value to check if the lifetimes of the
5160 new register use would overlap with the one of a previous reload
5161 that is not read-only or uses a different value.
5162 The 'time' used doesn't have to be linear in any shape or form, just
5164 Some reload types use different 'buckets' for each operand.
5165 So there are MAX_RECOG_OPERANDS different time values for each
5167 We compute TIME1 as the time when the register for the prospective
5168 new reload ceases to be live, and TIME2 for each existing
5169 reload as the time when that the reload register of that reload
5171 Where there is little to be gained by exact lifetime calculations,
5172 we just make conservative assumptions, i.e. a longer lifetime;
5173 this is done in the 'default:' cases. */
5176 case RELOAD_FOR_OTHER_ADDRESS:
5179 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5180 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5181 respectively, to the time values for these, we get distinct time
5182 values. To get distinct time values for each operand, we have to
5183 multiply opnum by at least three. We round that up to four because
5184 multiply by four is often cheaper. */
5185 case RELOAD_FOR_INPADDR_ADDRESS:
5186 time1 = opnum * 4 + 1;
5188 case RELOAD_FOR_INPUT_ADDRESS:
5189 time1 = opnum * 4 + 2;
5191 case RELOAD_FOR_OPADDR_ADDR:
5192 /* opnum * 4 + 3 < opnum * 4 + 4
5193 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5194 time1 = MAX_RECOG_OPERANDS * 4;
5196 case RELOAD_FOR_INPUT:
5197 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5198 instruction is executed. */
5199 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5201 case RELOAD_FOR_OPERAND_ADDRESS:
5202 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5204 time1 = MAX_RECOG_OPERANDS * 4 + 2;
5206 case RELOAD_FOR_OUTPUT_ADDRESS:
5207 time1 = MAX_RECOG_OPERANDS * 4 + 3 + opnum;
5210 time1 = MAX_RECOG_OPERANDS * 5 + 3;
5213 for (i = 0; i < n_reloads; i++)
5215 rtx reg = reload_reg_rtx[i];
5216 if (reg && GET_CODE (reg) == REG
5217 && ((unsigned) regno - true_regnum (reg)
5218 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5222 && reload_when_needed[i] != RELOAD_FOR_INPUT
5223 && reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
5224 && reload_when_needed[i] != RELOAD_FOR_INPADDR_ADDRESS)
5226 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5230 switch (reload_when_needed[i])
5232 case RELOAD_FOR_OTHER_ADDRESS:
5235 case RELOAD_FOR_INPADDR_ADDRESS:
5236 /* find_reloads makes sure that a
5237 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5238 by at most one - the first -
5239 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5240 address reload is inherited, the address address reload
5241 goes away, so we can ignore this conflict. */
5242 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1)
5244 time2 = reload_opnum[i] * 4 + 1;
5246 case RELOAD_FOR_INPUT_ADDRESS:
5247 time2 = reload_opnum[i] * 4 + 2;
5249 case RELOAD_FOR_INPUT:
5250 time2 = reload_opnum[i] * 4 + 3;
5252 case RELOAD_FOR_OPADDR_ADDR:
5253 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1)
5255 time2 = MAX_RECOG_OPERANDS * 4;
5257 case RELOAD_FOR_OPERAND_ADDRESS:
5258 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5260 case RELOAD_FOR_OUTPUT:
5261 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5262 instruction is executed. */
5263 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5265 case RELOAD_FOR_OUTADDR_ADDRESS:
5266 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1)
5269 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5270 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5271 case RELOAD_FOR_OUTPUT_ADDRESS:
5272 time2 = MAX_RECOG_OPERANDS * 4 + 3 + reload_opnum[i];
5275 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5277 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5291 /* Find a spill register to use as a reload register for reload R.
5292 LAST_RELOAD is non-zero if this is the last reload for the insn being
5295 Set reload_reg_rtx[R] to the register allocated.
5297 If NOERROR is nonzero, we return 1 if successful,
5298 or 0 if we couldn't find a spill reg and we didn't change anything. */
5301 allocate_reload_reg (chain, r, last_reload, noerror)
5302 struct insn_chain *chain;
5307 rtx insn = chain->insn;
5308 int i, pass, count, regno;
5311 /* If we put this reload ahead, thinking it is a group,
5312 then insist on finding a group. Otherwise we can grab a
5313 reg that some other reload needs.
5314 (That can happen when we have a 68000 DATA_OR_FP_REG
5315 which is a group of data regs or one fp reg.)
5316 We need not be so restrictive if there are no more reloads
5319 ??? Really it would be nicer to have smarter handling
5320 for that kind of reg class, where a problem like this is normal.
5321 Perhaps those classes should be avoided for reloading
5322 by use of more alternatives. */
5324 int force_group = reload_nregs[r] > 1 && ! last_reload;
5326 /* If we want a single register and haven't yet found one,
5327 take any reg in the right class and not in use.
5328 If we want a consecutive group, here is where we look for it.
5330 We use two passes so we can first look for reload regs to
5331 reuse, which are already in use for other reloads in this insn,
5332 and only then use additional registers.
5333 I think that maximizing reuse is needed to make sure we don't
5334 run out of reload regs. Suppose we have three reloads, and
5335 reloads A and B can share regs. These need two regs.
5336 Suppose A and B are given different regs.
5337 That leaves none for C. */
5338 for (pass = 0; pass < 2; pass++)
5340 /* I is the index in spill_regs.
5341 We advance it round-robin between insns to use all spill regs
5342 equally, so that inherited reloads have a chance
5343 of leapfrogging each other. Don't do this, however, when we have
5344 group needs and failure would be fatal; if we only have a relatively
5345 small number of spill registers, and more than one of them has
5346 group needs, then by starting in the middle, we may end up
5347 allocating the first one in such a way that we are not left with
5348 sufficient groups to handle the rest. */
5350 if (noerror || ! force_group)
5355 for (count = 0; count < n_spills; count++)
5357 int class = (int) reload_reg_class[r];
5363 regnum = spill_regs[i];
5365 if ((reload_reg_free_p (regnum, reload_opnum[r],
5366 reload_when_needed[r])
5368 /* We check reload_reg_used to make sure we
5369 don't clobber the return register. */
5370 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5371 && reload_reg_free_for_value_p (regnum,
5373 reload_when_needed[r],
5376 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5377 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5378 /* Look first for regs to share, then for unshared. But
5379 don't share regs used for inherited reloads; they are
5380 the ones we want to preserve. */
5382 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5384 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5387 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5388 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5389 (on 68000) got us two FP regs. If NR is 1,
5390 we would reject both of them. */
5392 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5393 /* If we need only one reg, we have already won. */
5396 /* But reject a single reg if we demand a group. */
5401 /* Otherwise check that as many consecutive regs as we need
5403 Also, don't use for a group registers that are
5404 needed for nongroups. */
5405 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5408 regno = regnum + nr - 1;
5409 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5410 && spill_reg_order[regno] >= 0
5411 && reload_reg_free_p (regno, reload_opnum[r],
5412 reload_when_needed[r])
5413 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5423 /* If we found something on pass 1, omit pass 2. */
5424 if (count < n_spills)
5428 /* We should have found a spill register by now. */
5429 if (count == n_spills)
5436 /* I is the index in SPILL_REG_RTX of the reload register we are to
5437 allocate. Get an rtx for it and find its register number. */
5439 new = spill_reg_rtx[i];
5441 if (new == 0 || GET_MODE (new) != reload_mode[r])
5442 spill_reg_rtx[i] = new
5443 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5445 regno = true_regnum (new);
5447 /* Detect when the reload reg can't hold the reload mode.
5448 This used to be one `if', but Sequent compiler can't handle that. */
5449 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5451 enum machine_mode test_mode = VOIDmode;
5453 test_mode = GET_MODE (reload_in[r]);
5454 /* If reload_in[r] has VOIDmode, it means we will load it
5455 in whatever mode the reload reg has: to wit, reload_mode[r].
5456 We have already tested that for validity. */
5457 /* Aside from that, we need to test that the expressions
5458 to reload from or into have modes which are valid for this
5459 reload register. Otherwise the reload insns would be invalid. */
5460 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5461 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5462 if (! (reload_out[r] != 0
5463 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5465 /* The reg is OK. */
5468 /* Mark as in use for this insn the reload regs we use
5470 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5471 reload_when_needed[r], reload_mode[r]);
5473 reload_reg_rtx[r] = new;
5474 reload_spill_index[r] = spill_regs[i];
5479 /* The reg is not OK. */
5484 if (asm_noperands (PATTERN (insn)) < 0)
5485 /* It's the compiler's fault. */
5486 fatal_insn ("Could not find a spill register", insn);
5488 /* It's the user's fault; the operand's mode and constraint
5489 don't match. Disable this reload so we don't crash in final. */
5490 error_for_asm (insn,
5491 "`asm' operand constraint incompatible with operand size");
5494 reload_reg_rtx[r] = 0;
5495 reload_optional[r] = 1;
5496 reload_secondary_p[r] = 1;
5501 /* Assign hard reg targets for the pseudo-registers we must reload
5502 into hard regs for this insn.
5503 Also output the instructions to copy them in and out of the hard regs.
5505 For machines with register classes, we are responsible for
5506 finding a reload reg in the proper class. */
5509 choose_reload_regs (chain)
5510 struct insn_chain *chain;
5512 rtx insn = chain->insn;
5514 int max_group_size = 1;
5515 enum reg_class group_class = NO_REGS;
5519 rtx save_reload_reg_rtx[MAX_RELOADS];
5520 char save_reload_inherited[MAX_RELOADS];
5521 rtx save_reload_inheritance_insn[MAX_RELOADS];
5522 rtx save_reload_override_in[MAX_RELOADS];
5523 int save_reload_spill_index[MAX_RELOADS];
5524 HARD_REG_SET save_reload_reg_used;
5525 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5526 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5527 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5528 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5529 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5530 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5531 HARD_REG_SET save_reload_reg_used_in_op_addr;
5532 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5533 HARD_REG_SET save_reload_reg_used_in_insn;
5534 HARD_REG_SET save_reload_reg_used_in_other_addr;
5535 HARD_REG_SET save_reload_reg_used_at_all;
5537 bzero (reload_inherited, MAX_RELOADS);
5538 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5539 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5541 CLEAR_HARD_REG_SET (reload_reg_used);
5542 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5543 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5544 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5545 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5546 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5548 CLEAR_HARD_REG_SET (reg_used_by_pseudo);
5549 compute_use_by_pseudos (®_used_by_pseudo, chain->live_before);
5550 compute_use_by_pseudos (®_used_by_pseudo, chain->live_after);
5552 for (i = 0; i < reload_n_operands; i++)
5554 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5555 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5556 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5557 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5558 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5559 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5562 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5564 #if 0 /* Not needed, now that we can always retry without inheritance. */
5565 /* See if we have more mandatory reloads than spill regs.
5566 If so, then we cannot risk optimizations that could prevent
5567 reloads from sharing one spill register.
5569 Since we will try finding a better register than reload_reg_rtx
5570 unless it is equal to reload_in or reload_out, count such reloads. */
5574 for (j = 0; j < n_reloads; j++)
5575 if (! reload_optional[j]
5576 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5577 && (reload_reg_rtx[j] == 0
5578 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5579 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5586 /* In order to be certain of getting the registers we need,
5587 we must sort the reloads into order of increasing register class.
5588 Then our grabbing of reload registers will parallel the process
5589 that provided the reload registers.
5591 Also note whether any of the reloads wants a consecutive group of regs.
5592 If so, record the maximum size of the group desired and what
5593 register class contains all the groups needed by this insn. */
5595 for (j = 0; j < n_reloads; j++)
5597 reload_order[j] = j;
5598 reload_spill_index[j] = -1;
5601 = (reload_inmode[j] == VOIDmode
5602 || (GET_MODE_SIZE (reload_outmode[j])
5603 > GET_MODE_SIZE (reload_inmode[j])))
5604 ? reload_outmode[j] : reload_inmode[j];
5606 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5608 if (reload_nregs[j] > 1)
5610 max_group_size = MAX (reload_nregs[j], max_group_size);
5611 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5614 /* If we have already decided to use a certain register,
5615 don't use it in another way. */
5616 if (reload_reg_rtx[j])
5617 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5618 reload_when_needed[j], reload_mode[j]);
5622 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5624 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5625 sizeof reload_reg_rtx);
5626 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5627 bcopy ((char *) reload_inheritance_insn,
5628 (char *) save_reload_inheritance_insn,
5629 sizeof reload_inheritance_insn);
5630 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5631 sizeof reload_override_in);
5632 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5633 sizeof reload_spill_index);
5634 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5635 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5636 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5637 reload_reg_used_in_op_addr);
5639 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5640 reload_reg_used_in_op_addr_reload);
5642 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5643 reload_reg_used_in_insn);
5644 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5645 reload_reg_used_in_other_addr);
5647 for (i = 0; i < reload_n_operands; i++)
5649 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5650 reload_reg_used_in_output[i]);
5651 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5652 reload_reg_used_in_input[i]);
5653 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5654 reload_reg_used_in_input_addr[i]);
5655 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5656 reload_reg_used_in_inpaddr_addr[i]);
5657 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5658 reload_reg_used_in_output_addr[i]);
5659 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5660 reload_reg_used_in_outaddr_addr[i]);
5663 /* If -O, try first with inheritance, then turning it off.
5664 If not -O, don't do inheritance.
5665 Using inheritance when not optimizing leads to paradoxes
5666 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5667 because one side of the comparison might be inherited. */
5669 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5671 /* Process the reloads in order of preference just found.
5672 Beyond this point, subregs can be found in reload_reg_rtx.
5674 This used to look for an existing reloaded home for all
5675 of the reloads, and only then perform any new reloads.
5676 But that could lose if the reloads were done out of reg-class order
5677 because a later reload with a looser constraint might have an old
5678 home in a register needed by an earlier reload with a tighter constraint.
5680 To solve this, we make two passes over the reloads, in the order
5681 described above. In the first pass we try to inherit a reload
5682 from a previous insn. If there is a later reload that needs a
5683 class that is a proper subset of the class being processed, we must
5684 also allocate a spill register during the first pass.
5686 Then make a second pass over the reloads to allocate any reloads
5687 that haven't been given registers yet. */
5689 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5691 for (j = 0; j < n_reloads; j++)
5693 register int r = reload_order[j];
5695 /* Ignore reloads that got marked inoperative. */
5696 if (reload_out[r] == 0 && reload_in[r] == 0
5697 && ! reload_secondary_p[r])
5700 /* If find_reloads chose to use reload_in or reload_out as a reload
5701 register, we don't need to chose one. Otherwise, try even if it
5702 found one since we might save an insn if we find the value lying
5704 Try also when reload_in is a pseudo without a hard reg. */
5705 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5706 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5707 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5708 && GET_CODE (reload_in[r]) != MEM
5709 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5712 #if 0 /* No longer needed for correct operation.
5713 It might give better code, or might not; worth an experiment? */
5714 /* If this is an optional reload, we can't inherit from earlier insns
5715 until we are sure that any non-optional reloads have been allocated.
5716 The following code takes advantage of the fact that optional reloads
5717 are at the end of reload_order. */
5718 if (reload_optional[r] != 0)
5719 for (i = 0; i < j; i++)
5720 if ((reload_out[reload_order[i]] != 0
5721 || reload_in[reload_order[i]] != 0
5722 || reload_secondary_p[reload_order[i]])
5723 && ! reload_optional[reload_order[i]]
5724 && reload_reg_rtx[reload_order[i]] == 0)
5725 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5728 /* First see if this pseudo is already available as reloaded
5729 for a previous insn. We cannot try to inherit for reloads
5730 that are smaller than the maximum number of registers needed
5731 for groups unless the register we would allocate cannot be used
5734 We could check here to see if this is a secondary reload for
5735 an object that is already in a register of the desired class.
5736 This would avoid the need for the secondary reload register.
5737 But this is complex because we can't easily determine what
5738 objects might want to be loaded via this reload. So let a
5739 register be allocated here. In `emit_reload_insns' we suppress
5740 one of the loads in the case described above. */
5745 register int regno = -1;
5746 enum machine_mode mode;
5748 if (reload_in[r] == 0)
5750 else if (GET_CODE (reload_in[r]) == REG)
5752 regno = REGNO (reload_in[r]);
5753 mode = GET_MODE (reload_in[r]);
5755 else if (GET_CODE (reload_in_reg[r]) == REG)
5757 regno = REGNO (reload_in_reg[r]);
5758 mode = GET_MODE (reload_in_reg[r]);
5760 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5761 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5763 word = SUBREG_WORD (reload_in_reg[r]);
5764 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5765 if (regno < FIRST_PSEUDO_REGISTER)
5767 mode = GET_MODE (reload_in_reg[r]);
5770 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5771 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5772 || GET_CODE (reload_in_reg[r]) == POST_INC
5773 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5774 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5776 regno = REGNO (XEXP (reload_in_reg[r], 0));
5777 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5778 reload_out[r] = reload_in[r];
5782 /* This won't work, since REGNO can be a pseudo reg number.
5783 Also, it takes much more hair to keep track of all the things
5784 that can invalidate an inherited reload of part of a pseudoreg. */
5785 else if (GET_CODE (reload_in[r]) == SUBREG
5786 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5787 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5790 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5792 enum reg_class class = reload_reg_class[r], last_class;
5793 rtx last_reg = reg_last_reload_reg[regno];
5795 i = REGNO (last_reg) + word;
5796 last_class = REGNO_REG_CLASS (i);
5797 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5798 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5799 && reg_reloaded_contents[i] == regno
5800 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5801 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5802 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5803 /* Even if we can't use this register as a reload
5804 register, we might use it for reload_override_in,
5805 if copying it to the desired class is cheap
5807 || ((REGISTER_MOVE_COST (last_class, class)
5808 < MEMORY_MOVE_COST (mode, class, 1))
5809 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5810 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5814 #ifdef SECONDARY_MEMORY_NEEDED
5815 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5820 && (reload_nregs[r] == max_group_size
5821 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5823 && ((reload_reg_free_p (i, reload_opnum[r],
5824 reload_when_needed[r])
5825 && reload_reg_free_before_p (i, reload_opnum[r],
5826 reload_when_needed[r],
5828 || reload_reg_free_for_value_p (i, reload_opnum[r],
5829 reload_when_needed[r],
5833 /* If a group is needed, verify that all the subsequent
5834 registers still have their values intact. */
5836 = HARD_REGNO_NREGS (i, reload_mode[r]);
5839 for (k = 1; k < nr; k++)
5840 if (reg_reloaded_contents[i + k] != regno
5841 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5848 last_reg = (GET_MODE (last_reg) == mode
5849 ? last_reg : gen_rtx_REG (mode, i));
5851 /* We found a register that contains the
5852 value we need. If this register is the
5853 same as an `earlyclobber' operand of the
5854 current insn, just mark it as a place to
5855 reload from since we can't use it as the
5856 reload register itself. */
5858 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5859 if (reg_overlap_mentioned_for_reload_p
5860 (reg_last_reload_reg[regno],
5861 reload_earlyclobbers[i1]))
5864 if (i1 != n_earlyclobbers
5865 /* Don't use it if we'd clobber a pseudo reg. */
5866 || (! TEST_HARD_REG_BIT (reg_used_by_pseudo, i)
5868 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5869 /* Don't really use the inherited spill reg
5870 if we need it wider than we've got it. */
5871 || (GET_MODE_SIZE (reload_mode[r])
5872 > GET_MODE_SIZE (mode))
5873 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5876 /* If find_reloads chose reload_out as reload
5877 register, stay with it - that leaves the
5878 inherited register for subsequent reloads. */
5879 || (reload_out[r] && reload_reg_rtx[r]
5880 && rtx_equal_p (reload_out[r],
5881 reload_reg_rtx[r])))
5883 reload_override_in[r] = last_reg;
5884 reload_inheritance_insn[r]
5885 = reg_reloaded_insn[i];
5890 /* We can use this as a reload reg. */
5891 /* Mark the register as in use for this part of
5893 mark_reload_reg_in_use (i,
5895 reload_when_needed[r],
5897 reload_reg_rtx[r] = last_reg;
5898 reload_inherited[r] = 1;
5899 reload_inheritance_insn[r]
5900 = reg_reloaded_insn[i];
5901 reload_spill_index[r] = i;
5902 for (k = 0; k < nr; k++)
5903 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5911 /* Here's another way to see if the value is already lying around. */
5913 && reload_in[r] != 0
5914 && ! reload_inherited[r]
5915 && reload_out[r] == 0
5916 && (CONSTANT_P (reload_in[r])
5917 || GET_CODE (reload_in[r]) == PLUS
5918 || GET_CODE (reload_in[r]) == REG
5919 || GET_CODE (reload_in[r]) == MEM)
5920 && (reload_nregs[r] == max_group_size
5921 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5924 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5925 -1, NULL_PTR, 0, reload_mode[r]);
5930 if (GET_CODE (equiv) == REG)
5931 regno = REGNO (equiv);
5932 else if (GET_CODE (equiv) == SUBREG)
5934 /* This must be a SUBREG of a hard register.
5935 Make a new REG since this might be used in an
5936 address and not all machines support SUBREGs
5938 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5939 equiv = gen_rtx_REG (reload_mode[r], regno);
5945 /* If we found a spill reg, reject it unless it is free
5946 and of the desired class. */
5948 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5949 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
5950 reload_when_needed[r],
5953 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5957 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5960 /* We found a register that contains the value we need.
5961 If this register is the same as an `earlyclobber' operand
5962 of the current insn, just mark it as a place to reload from
5963 since we can't use it as the reload register itself. */
5966 for (i = 0; i < n_earlyclobbers; i++)
5967 if (reg_overlap_mentioned_for_reload_p (equiv,
5968 reload_earlyclobbers[i]))
5970 reload_override_in[r] = equiv;
5975 /* If the equiv register we have found is explicitly clobbered
5976 in the current insn, it depends on the reload type if we
5977 can use it, use it for reload_override_in, or not at all.
5978 In particular, we then can't use EQUIV for a
5979 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5981 if (equiv != 0 && regno_clobbered_p (regno, insn))
5983 switch (reload_when_needed[r])
5985 case RELOAD_FOR_OTHER_ADDRESS:
5986 case RELOAD_FOR_INPADDR_ADDRESS:
5987 case RELOAD_FOR_INPUT_ADDRESS:
5988 case RELOAD_FOR_OPADDR_ADDR:
5991 case RELOAD_FOR_INPUT:
5992 case RELOAD_FOR_OPERAND_ADDRESS:
5993 reload_override_in[r] = equiv;
6001 /* If we found an equivalent reg, say no code need be generated
6002 to load it, and use it as our reload reg. */
6003 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6005 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6007 reload_reg_rtx[r] = equiv;
6008 reload_inherited[r] = 1;
6010 /* If reg_reloaded_valid is not set for this register,
6011 there might be a stale spill_reg_store lying around.
6012 We must clear it, since otherwise emit_reload_insns
6013 might delete the store. */
6014 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6015 spill_reg_store[regno] = NULL_RTX;
6016 /* If any of the hard registers in EQUIV are spill
6017 registers, mark them as in use for this insn. */
6018 for (k = 0; k < nr; k++)
6020 i = spill_reg_order[regno + k];
6023 mark_reload_reg_in_use (regno, reload_opnum[r],
6024 reload_when_needed[r],
6026 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6033 /* If we found a register to use already, or if this is an optional
6034 reload, we are done. */
6035 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6038 #if 0 /* No longer needed for correct operation. Might or might not
6039 give better code on the average. Want to experiment? */
6041 /* See if there is a later reload that has a class different from our
6042 class that intersects our class or that requires less register
6043 than our reload. If so, we must allocate a register to this
6044 reload now, since that reload might inherit a previous reload
6045 and take the only available register in our class. Don't do this
6046 for optional reloads since they will force all previous reloads
6047 to be allocated. Also don't do this for reloads that have been
6050 for (i = j + 1; i < n_reloads; i++)
6052 int s = reload_order[i];
6054 if ((reload_in[s] == 0 && reload_out[s] == 0
6055 && ! reload_secondary_p[s])
6056 || reload_optional[s])
6059 if ((reload_reg_class[s] != reload_reg_class[r]
6060 && reg_classes_intersect_p (reload_reg_class[r],
6061 reload_reg_class[s]))
6062 || reload_nregs[s] < reload_nregs[r])
6069 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6073 /* Now allocate reload registers for anything non-optional that
6074 didn't get one yet. */
6075 for (j = 0; j < n_reloads; j++)
6077 register int r = reload_order[j];
6079 /* Ignore reloads that got marked inoperative. */
6080 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6083 /* Skip reloads that already have a register allocated or are
6085 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6088 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6092 /* If that loop got all the way, we have won. */
6096 /* Loop around and try without any inheritance. */
6097 /* First undo everything done by the failed attempt
6098 to allocate with inheritance. */
6099 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6100 sizeof reload_reg_rtx);
6101 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6102 sizeof reload_inherited);
6103 bcopy ((char *) save_reload_inheritance_insn,
6104 (char *) reload_inheritance_insn,
6105 sizeof reload_inheritance_insn);
6106 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6107 sizeof reload_override_in);
6108 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6109 sizeof reload_spill_index);
6110 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6111 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6112 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6113 save_reload_reg_used_in_op_addr);
6114 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6115 save_reload_reg_used_in_op_addr_reload);
6116 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6117 save_reload_reg_used_in_insn);
6118 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6119 save_reload_reg_used_in_other_addr);
6121 for (i = 0; i < reload_n_operands; i++)
6123 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6124 save_reload_reg_used_in_input[i]);
6125 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6126 save_reload_reg_used_in_output[i]);
6127 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6128 save_reload_reg_used_in_input_addr[i]);
6129 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6130 save_reload_reg_used_in_inpaddr_addr[i]);
6131 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6132 save_reload_reg_used_in_output_addr[i]);
6133 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6134 save_reload_reg_used_in_outaddr_addr[i]);
6138 /* If we thought we could inherit a reload, because it seemed that
6139 nothing else wanted the same reload register earlier in the insn,
6140 verify that assumption, now that all reloads have been assigned.
6141 Likewise for reloads where reload_override_in has been set. */
6143 /* If doing expensive optimizations, do one preliminary pass that doesn't
6144 cancel any inheritance, but removes reloads that have been needed only
6145 for reloads that we know can be inherited. */
6146 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6148 for (j = 0; j < n_reloads; j++)
6150 register int r = reload_order[j];
6152 if (reload_inherited[r] && reload_reg_rtx[r])
6153 check_reg = reload_reg_rtx[r];
6154 else if (reload_override_in[r]
6155 && (GET_CODE (reload_override_in[r]) == REG
6156 || GET_CODE (reload_override_in[r]) == SUBREG))
6157 check_reg = reload_override_in[r];
6160 if (! (reload_reg_free_before_p (true_regnum (check_reg),
6161 reload_opnum[r], reload_when_needed[r],
6162 ! reload_inherited[r])
6163 || reload_reg_free_for_value_p (true_regnum (check_reg),
6165 reload_when_needed[r],
6171 reload_inherited[r] = 0;
6172 reload_override_in[r] = 0;
6174 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6175 reload_override_in, then we do not need its related
6176 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6177 likewise for other reload types.
6178 We handle this by removing a reload when its only replacement
6179 is mentioned in reload_in of the reload we are going to inherit.
6180 A special case are auto_inc expressions; even if the input is
6181 inherited, we still need the address for the output. We can
6182 recognize them because they have RELOAD_OUT set but not
6184 If we suceeded removing some reload and we are doing a preliminary
6185 pass just to remove such reloads, make another pass, since the
6186 removal of one reload might allow us to inherit another one. */
6187 else if ((! reload_out[r] || reload_out_reg[r])
6188 && remove_address_replacements (reload_in[r]) && pass)
6193 /* Now that reload_override_in is known valid,
6194 actually override reload_in. */
6195 for (j = 0; j < n_reloads; j++)
6196 if (reload_override_in[j])
6197 reload_in[j] = reload_override_in[j];
6199 /* If this reload won't be done because it has been cancelled or is
6200 optional and not inherited, clear reload_reg_rtx so other
6201 routines (such as subst_reloads) don't get confused. */
6202 for (j = 0; j < n_reloads; j++)
6203 if (reload_reg_rtx[j] != 0
6204 && ((reload_optional[j] && ! reload_inherited[j])
6205 || (reload_in[j] == 0 && reload_out[j] == 0
6206 && ! reload_secondary_p[j])))
6208 int regno = true_regnum (reload_reg_rtx[j]);
6210 if (spill_reg_order[regno] >= 0)
6211 clear_reload_reg_in_use (regno, reload_opnum[j],
6212 reload_when_needed[j], reload_mode[j]);
6213 reload_reg_rtx[j] = 0;
6216 /* Record which pseudos and which spill regs have output reloads. */
6217 for (j = 0; j < n_reloads; j++)
6219 register int r = reload_order[j];
6221 i = reload_spill_index[r];
6223 /* I is nonneg if this reload uses a register.
6224 If reload_reg_rtx[r] is 0, this is an optional reload
6225 that we opted to ignore. */
6226 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6227 && reload_reg_rtx[r] != 0)
6229 register int nregno = REGNO (reload_out_reg[r]);
6232 if (nregno < FIRST_PSEUDO_REGISTER)
6233 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6236 reg_has_output_reload[nregno + nr] = 1;
6240 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6242 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6245 if (reload_when_needed[r] != RELOAD_OTHER
6246 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6247 && reload_when_needed[r] != RELOAD_FOR_INSN)
6253 /* Deallocate the reload register for reload R. This is called from
6254 remove_address_replacements. */
6256 deallocate_reload_reg (r)
6261 if (! reload_reg_rtx[r])
6263 regno = true_regnum (reload_reg_rtx[r]);
6264 reload_reg_rtx[r] = 0;
6265 if (spill_reg_order[regno] >= 0)
6266 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6268 reload_spill_index[r] = -1;
6271 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6272 reloads of the same item for fear that we might not have enough reload
6273 registers. However, normally they will get the same reload register
6274 and hence actually need not be loaded twice.
6276 Here we check for the most common case of this phenomenon: when we have
6277 a number of reloads for the same object, each of which were allocated
6278 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6279 reload, and is not modified in the insn itself. If we find such,
6280 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6281 This will not increase the number of spill registers needed and will
6282 prevent redundant code. */
6285 merge_assigned_reloads (insn)
6290 /* Scan all the reloads looking for ones that only load values and
6291 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6292 assigned and not modified by INSN. */
6294 for (i = 0; i < n_reloads; i++)
6296 int conflicting_input = 0;
6297 int max_input_address_opnum = -1;
6298 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6300 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6301 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6302 || reg_set_p (reload_reg_rtx[i], insn))
6305 /* Look at all other reloads. Ensure that the only use of this
6306 reload_reg_rtx is in a reload that just loads the same value
6307 as we do. Note that any secondary reloads must be of the identical
6308 class since the values, modes, and result registers are the
6309 same, so we need not do anything with any secondary reloads. */
6311 for (j = 0; j < n_reloads; j++)
6313 if (i == j || reload_reg_rtx[j] == 0
6314 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6318 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6319 && reload_opnum[j] > max_input_address_opnum)
6320 max_input_address_opnum = reload_opnum[j];
6322 /* If the reload regs aren't exactly the same (e.g, different modes)
6323 or if the values are different, we can't merge this reload.
6324 But if it is an input reload, we might still merge
6325 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6327 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6328 || reload_out[j] != 0 || reload_in[j] == 0
6329 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6331 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6332 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6333 || reload_opnum[i] > reload_opnum[j])
6334 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6336 conflicting_input = 1;
6337 if (min_conflicting_input_opnum > reload_opnum[j])
6338 min_conflicting_input_opnum = reload_opnum[j];
6342 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6343 we, in fact, found any matching reloads. */
6346 && max_input_address_opnum <= min_conflicting_input_opnum)
6348 for (j = 0; j < n_reloads; j++)
6349 if (i != j && reload_reg_rtx[j] != 0
6350 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6351 && (! conflicting_input
6352 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6353 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6355 reload_when_needed[i] = RELOAD_OTHER;
6357 reload_spill_index[j] = -1;
6358 transfer_replacements (i, j);
6361 /* If this is now RELOAD_OTHER, look for any reloads that load
6362 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6363 if they were for inputs, RELOAD_OTHER for outputs. Note that
6364 this test is equivalent to looking for reloads for this operand
6367 if (reload_when_needed[i] == RELOAD_OTHER)
6368 for (j = 0; j < n_reloads; j++)
6369 if (reload_in[j] != 0
6370 && reload_when_needed[i] != RELOAD_OTHER
6371 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6373 reload_when_needed[j]
6374 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6375 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6376 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6382 /* Output insns to reload values in and out of the chosen reload regs. */
6385 emit_reload_insns (chain)
6386 struct insn_chain *chain;
6388 rtx insn = chain->insn;
6391 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6392 rtx other_input_address_reload_insns = 0;
6393 rtx other_input_reload_insns = 0;
6394 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6395 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6396 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6397 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6398 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6399 rtx operand_reload_insns = 0;
6400 rtx other_operand_reload_insns = 0;
6401 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6402 rtx following_insn = NEXT_INSN (insn);
6403 rtx before_insn = PREV_INSN (insn);
6405 /* Values to be put in spill_reg_store are put here first. */
6406 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6407 HARD_REG_SET reg_reloaded_died;
6409 CLEAR_HARD_REG_SET (reg_reloaded_died);
6411 for (j = 0; j < reload_n_operands; j++)
6412 input_reload_insns[j] = input_address_reload_insns[j]
6413 = inpaddr_address_reload_insns[j]
6414 = output_reload_insns[j] = output_address_reload_insns[j]
6415 = outaddr_address_reload_insns[j]
6416 = other_output_reload_insns[j] = 0;
6418 /* Now output the instructions to copy the data into and out of the
6419 reload registers. Do these in the order that the reloads were reported,
6420 since reloads of base and index registers precede reloads of operands
6421 and the operands may need the base and index registers reloaded. */
6423 for (j = 0; j < n_reloads; j++)
6426 rtx oldequiv_reg = 0;
6427 rtx this_reload_insn = 0;
6428 int expect_occurrences = 1;
6430 if (reload_reg_rtx[j]
6431 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6432 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6434 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6435 ? reload_in_reg[j] : reload_in[j]);
6438 /* AUTO_INC reloads need to be handled even if inherited. We got an
6439 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6440 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6441 && ! rtx_equal_p (reload_reg_rtx[j], old)
6442 && reload_reg_rtx[j] != 0)
6444 register rtx reloadreg = reload_reg_rtx[j];
6446 enum machine_mode mode;
6449 /* Determine the mode to reload in.
6450 This is very tricky because we have three to choose from.
6451 There is the mode the insn operand wants (reload_inmode[J]).
6452 There is the mode of the reload register RELOADREG.
6453 There is the intrinsic mode of the operand, which we could find
6454 by stripping some SUBREGs.
6455 It turns out that RELOADREG's mode is irrelevant:
6456 we can change that arbitrarily.
6458 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6459 then the reload reg may not support QImode moves, so use SImode.
6460 If foo is in memory due to spilling a pseudo reg, this is safe,
6461 because the QImode value is in the least significant part of a
6462 slot big enough for a SImode. If foo is some other sort of
6463 memory reference, then it is impossible to reload this case,
6464 so previous passes had better make sure this never happens.
6466 Then consider a one-word union which has SImode and one of its
6467 members is a float, being fetched as (SUBREG:SF union:SI).
6468 We must fetch that as SFmode because we could be loading into
6469 a float-only register. In this case OLD's mode is correct.
6471 Consider an immediate integer: it has VOIDmode. Here we need
6472 to get a mode from something else.
6474 In some cases, there is a fourth mode, the operand's
6475 containing mode. If the insn specifies a containing mode for
6476 this operand, it overrides all others.
6478 I am not sure whether the algorithm here is always right,
6479 but it does the right things in those cases. */
6481 mode = GET_MODE (old);
6482 if (mode == VOIDmode)
6483 mode = reload_inmode[j];
6485 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6486 /* If we need a secondary register for this operation, see if
6487 the value is already in a register in that class. Don't
6488 do this if the secondary register will be used as a scratch
6491 if (reload_secondary_in_reload[j] >= 0
6492 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6495 = find_equiv_reg (old, insn,
6496 reload_reg_class[reload_secondary_in_reload[j]],
6497 -1, NULL_PTR, 0, mode);
6500 /* If reloading from memory, see if there is a register
6501 that already holds the same value. If so, reload from there.
6502 We can pass 0 as the reload_reg_p argument because
6503 any other reload has either already been emitted,
6504 in which case find_equiv_reg will see the reload-insn,
6505 or has yet to be emitted, in which case it doesn't matter
6506 because we will use this equiv reg right away. */
6508 if (oldequiv == 0 && optimize
6509 && (GET_CODE (old) == MEM
6510 || (GET_CODE (old) == REG
6511 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6512 && reg_renumber[REGNO (old)] < 0)))
6513 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6514 -1, NULL_PTR, 0, mode);
6518 int regno = true_regnum (oldequiv);
6520 /* If OLDEQUIV is a spill register, don't use it for this
6521 if any other reload needs it at an earlier stage of this insn
6522 or at this stage. */
6523 if (spill_reg_order[regno] >= 0
6524 && (! reload_reg_free_p (regno, reload_opnum[j],
6525 reload_when_needed[j])
6526 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6527 reload_when_needed[j], 1)))
6530 /* If OLDEQUIV is not a spill register,
6531 don't use it if any other reload wants it. */
6532 if (spill_reg_order[regno] < 0)
6535 for (k = 0; k < n_reloads; k++)
6536 if (reload_reg_rtx[k] != 0 && k != j
6537 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6545 /* If it is no cheaper to copy from OLDEQUIV into the
6546 reload register than it would be to move from memory,
6547 don't use it. Likewise, if we need a secondary register
6551 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6552 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6553 reload_reg_class[j])
6554 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6555 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6556 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6560 #ifdef SECONDARY_MEMORY_NEEDED
6561 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6562 reload_reg_class[j],
6569 /* delete_output_reload is only invoked properly if old contains
6570 the original pseudo register. Since this is replaced with a
6571 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6572 find the pseudo in RELOAD_IN_REG. */
6574 && reload_override_in[j]
6575 && GET_CODE (reload_in_reg[j]) == REG)
6578 old = reload_in_reg[j];
6582 else if (GET_CODE (oldequiv) == REG)
6583 oldequiv_reg = oldequiv;
6584 else if (GET_CODE (oldequiv) == SUBREG)
6585 oldequiv_reg = SUBREG_REG (oldequiv);
6587 /* If we are reloading from a register that was recently stored in
6588 with an output-reload, see if we can prove there was
6589 actually no need to store the old value in it. */
6591 if (optimize && GET_CODE (oldequiv) == REG
6592 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6593 && spill_reg_store[REGNO (oldequiv)]
6594 && GET_CODE (old) == REG
6595 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6596 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6597 reload_out_reg[j])))
6598 delete_output_reload (insn, j, REGNO (oldequiv));
6600 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6601 then load RELOADREG from OLDEQUIV. Note that we cannot use
6602 gen_lowpart_common since it can do the wrong thing when
6603 RELOADREG has a multi-word mode. Note that RELOADREG
6604 must always be a REG here. */
6606 if (GET_MODE (reloadreg) != mode)
6607 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6608 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6609 oldequiv = SUBREG_REG (oldequiv);
6610 if (GET_MODE (oldequiv) != VOIDmode
6611 && mode != GET_MODE (oldequiv))
6612 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6614 /* Switch to the right place to emit the reload insns. */
6615 switch (reload_when_needed[j])
6618 where = &other_input_reload_insns;
6620 case RELOAD_FOR_INPUT:
6621 where = &input_reload_insns[reload_opnum[j]];
6623 case RELOAD_FOR_INPUT_ADDRESS:
6624 where = &input_address_reload_insns[reload_opnum[j]];
6626 case RELOAD_FOR_INPADDR_ADDRESS:
6627 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6629 case RELOAD_FOR_OUTPUT_ADDRESS:
6630 where = &output_address_reload_insns[reload_opnum[j]];
6632 case RELOAD_FOR_OUTADDR_ADDRESS:
6633 where = &outaddr_address_reload_insns[reload_opnum[j]];
6635 case RELOAD_FOR_OPERAND_ADDRESS:
6636 where = &operand_reload_insns;
6638 case RELOAD_FOR_OPADDR_ADDR:
6639 where = &other_operand_reload_insns;
6641 case RELOAD_FOR_OTHER_ADDRESS:
6642 where = &other_input_address_reload_insns;
6648 push_to_sequence (*where);
6651 /* Auto-increment addresses must be reloaded in a special way. */
6652 if (reload_out[j] && ! reload_out_reg[j])
6654 /* We are not going to bother supporting the case where a
6655 incremented register can't be copied directly from
6656 OLDEQUIV since this seems highly unlikely. */
6657 if (reload_secondary_in_reload[j] >= 0)
6660 if (reload_inherited[j])
6661 oldequiv = reloadreg;
6663 old = XEXP (reload_in_reg[j], 0);
6665 if (optimize && GET_CODE (oldequiv) == REG
6666 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6667 && spill_reg_store[REGNO (oldequiv)]
6668 && GET_CODE (old) == REG
6669 && (dead_or_set_p (insn,
6670 spill_reg_stored_to[REGNO (oldequiv)])
6671 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6673 delete_output_reload (insn, j, REGNO (oldequiv));
6675 /* Prevent normal processing of this reload. */
6677 /* Output a special code sequence for this case. */
6678 new_spill_reg_store[REGNO (reloadreg)]
6679 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6683 /* If we are reloading a pseudo-register that was set by the previous
6684 insn, see if we can get rid of that pseudo-register entirely
6685 by redirecting the previous insn into our reload register. */
6687 else if (optimize && GET_CODE (old) == REG
6688 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6689 && dead_or_set_p (insn, old)
6690 /* This is unsafe if some other reload
6691 uses the same reg first. */
6692 && reload_reg_free_before_p (REGNO (reloadreg),
6694 reload_when_needed[j], 0))
6696 rtx temp = PREV_INSN (insn);
6697 while (temp && GET_CODE (temp) == NOTE)
6698 temp = PREV_INSN (temp);
6700 && GET_CODE (temp) == INSN
6701 && GET_CODE (PATTERN (temp)) == SET
6702 && SET_DEST (PATTERN (temp)) == old
6703 /* Make sure we can access insn_operand_constraint. */
6704 && asm_noperands (PATTERN (temp)) < 0
6705 /* This is unsafe if prev insn rejects our reload reg. */
6706 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6708 /* This is unsafe if operand occurs more than once in current
6709 insn. Perhaps some occurrences aren't reloaded. */
6710 && count_occurrences (PATTERN (insn), old) == 1
6711 /* Don't risk splitting a matching pair of operands. */
6712 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6714 /* Store into the reload register instead of the pseudo. */
6715 SET_DEST (PATTERN (temp)) = reloadreg;
6716 /* If these are the only uses of the pseudo reg,
6717 pretend for GDB it lives in the reload reg we used. */
6718 if (REG_N_DEATHS (REGNO (old)) == 1
6719 && REG_N_SETS (REGNO (old)) == 1)
6721 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6722 alter_reg (REGNO (old), -1);
6728 /* We can't do that, so output an insn to load RELOADREG. */
6732 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6733 rtx second_reload_reg = 0;
6734 enum insn_code icode;
6736 /* If we have a secondary reload, pick up the secondary register
6737 and icode, if any. If OLDEQUIV and OLD are different or
6738 if this is an in-out reload, recompute whether or not we
6739 still need a secondary register and what the icode should
6740 be. If we still need a secondary register and the class or
6741 icode is different, go back to reloading from OLD if using
6742 OLDEQUIV means that we got the wrong type of register. We
6743 cannot have different class or icode due to an in-out reload
6744 because we don't make such reloads when both the input and
6745 output need secondary reload registers. */
6747 if (reload_secondary_in_reload[j] >= 0)
6749 int secondary_reload = reload_secondary_in_reload[j];
6750 rtx real_oldequiv = oldequiv;
6753 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6754 and similarly for OLD.
6755 See comments in get_secondary_reload in reload.c. */
6756 /* If it is a pseudo that cannot be replaced with its
6757 equivalent MEM, we must fall back to reload_in, which
6758 will have all the necessary substitutions registered. */
6760 if (GET_CODE (oldequiv) == REG
6761 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6762 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6764 if (reg_equiv_address[REGNO (oldequiv)]
6765 || num_not_at_initial_offset)
6766 real_oldequiv = reload_in[j];
6768 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6771 if (GET_CODE (old) == REG
6772 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6773 && reg_equiv_memory_loc[REGNO (old)] != 0)
6775 if (reg_equiv_address[REGNO (old)]
6776 || num_not_at_initial_offset)
6777 real_old = reload_in[j];
6779 real_old = reg_equiv_mem[REGNO (old)];
6782 second_reload_reg = reload_reg_rtx[secondary_reload];
6783 icode = reload_secondary_in_icode[j];
6785 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6786 || (reload_in[j] != 0 && reload_out[j] != 0))
6788 enum reg_class new_class
6789 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6790 mode, real_oldequiv);
6792 if (new_class == NO_REGS)
6793 second_reload_reg = 0;
6796 enum insn_code new_icode;
6797 enum machine_mode new_mode;
6799 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6800 REGNO (second_reload_reg)))
6801 oldequiv = old, real_oldequiv = real_old;
6804 new_icode = reload_in_optab[(int) mode];
6805 if (new_icode != CODE_FOR_nothing
6806 && ((insn_operand_predicate[(int) new_icode][0]
6807 && ! ((*insn_operand_predicate[(int) new_icode][0])
6809 || (insn_operand_predicate[(int) new_icode][1]
6810 && ! ((*insn_operand_predicate[(int) new_icode][1])
6811 (real_oldequiv, mode)))))
6812 new_icode = CODE_FOR_nothing;
6814 if (new_icode == CODE_FOR_nothing)
6817 new_mode = insn_operand_mode[(int) new_icode][2];
6819 if (GET_MODE (second_reload_reg) != new_mode)
6821 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6823 oldequiv = old, real_oldequiv = real_old;
6826 = gen_rtx_REG (new_mode,
6827 REGNO (second_reload_reg));
6833 /* If we still need a secondary reload register, check
6834 to see if it is being used as a scratch or intermediate
6835 register and generate code appropriately. If we need
6836 a scratch register, use REAL_OLDEQUIV since the form of
6837 the insn may depend on the actual address if it is
6840 if (second_reload_reg)
6842 if (icode != CODE_FOR_nothing)
6844 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6845 second_reload_reg));
6850 /* See if we need a scratch register to load the
6851 intermediate register (a tertiary reload). */
6852 enum insn_code tertiary_icode
6853 = reload_secondary_in_icode[secondary_reload];
6855 if (tertiary_icode != CODE_FOR_nothing)
6857 rtx third_reload_reg
6858 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6860 emit_insn ((GEN_FCN (tertiary_icode)
6861 (second_reload_reg, real_oldequiv,
6862 third_reload_reg)));
6865 gen_reload (second_reload_reg, real_oldequiv,
6867 reload_when_needed[j]);
6869 oldequiv = second_reload_reg;
6875 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6877 rtx real_oldequiv = oldequiv;
6879 if ((GET_CODE (oldequiv) == REG
6880 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6881 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6882 || (GET_CODE (oldequiv) == SUBREG
6883 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6884 && (REGNO (SUBREG_REG (oldequiv))
6885 >= FIRST_PSEUDO_REGISTER)
6886 && (reg_equiv_memory_loc
6887 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6888 real_oldequiv = reload_in[j];
6889 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
6890 reload_when_needed[j]);
6895 this_reload_insn = get_last_insn ();
6896 /* End this sequence. */
6897 *where = get_insns ();
6900 /* Update reload_override_in so that delete_address_reloads_1
6901 can see the actual register usage. */
6903 reload_override_in[j] = oldequiv;
6906 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6907 e.g. inheriting a SImode output reload for
6908 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6909 if (optimize && reload_inherited[j] && reload_in[j]
6910 && GET_CODE (reload_in[j]) == MEM
6911 && GET_CODE (reload_in_reg[j]) == MEM
6912 && reload_spill_index[j] >= 0
6913 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6916 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6918 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6921 /* If we are reloading a register that was recently stored in with an
6922 output-reload, see if we can prove there was
6923 actually no need to store the old value in it. */
6926 && (reload_inherited[j] || reload_override_in[j])
6927 && reload_reg_rtx[j]
6928 && GET_CODE (reload_reg_rtx[j]) == REG
6929 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
6931 /* There doesn't seem to be any reason to restrict this to pseudos
6932 and doing so loses in the case where we are copying from a
6933 register of the wrong class. */
6934 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6935 >= FIRST_PSEUDO_REGISTER
6937 /* The insn might have already some references to stackslots
6938 replaced by MEMs, while reload_out_reg still names the
6940 && (dead_or_set_p (insn,
6941 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6942 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
6943 reload_out_reg[j])))
6944 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
6946 /* Input-reloading is done. Now do output-reloading,
6947 storing the value from the reload-register after the main insn
6948 if reload_out[j] is nonzero.
6950 ??? At some point we need to support handling output reloads of
6951 JUMP_INSNs or insns that set cc0. */
6953 /* If this is an output reload that stores something that is
6954 not loaded in this same reload, see if we can eliminate a previous
6957 rtx pseudo = reload_out_reg[j];
6960 && GET_CODE (pseudo) == REG
6961 && ! rtx_equal_p (reload_in_reg[j], pseudo)
6962 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6963 && reg_last_reload_reg[REGNO (pseudo)])
6965 int pseudo_no = REGNO (pseudo);
6966 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6968 /* We don't need to test full validity of last_regno for
6969 inherit here; we only want to know if the store actually
6970 matches the pseudo. */
6971 if (reg_reloaded_contents[last_regno] == pseudo_no
6972 && spill_reg_store[last_regno]
6973 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6974 delete_output_reload (insn, j, last_regno);
6978 old = reload_out_reg[j];
6980 && reload_reg_rtx[j] != old
6981 && reload_reg_rtx[j] != 0)
6983 register rtx reloadreg = reload_reg_rtx[j];
6984 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6985 register rtx second_reloadreg = 0;
6988 enum machine_mode mode;
6991 /* An output operand that dies right away does need a reload,
6992 but need not be copied from it. Show the new location in the
6994 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6995 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6997 XEXP (note, 0) = reload_reg_rtx[j];
7000 /* Likewise for a SUBREG of an operand that dies. */
7001 else if (GET_CODE (old) == SUBREG
7002 && GET_CODE (SUBREG_REG (old)) == REG
7003 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7006 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7010 else if (GET_CODE (old) == SCRATCH)
7011 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7012 but we don't want to make an output reload. */
7016 /* Strip off of OLD any size-increasing SUBREGs such as
7017 (SUBREG:SI foo:QI 0). */
7019 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7020 && (GET_MODE_SIZE (GET_MODE (old))
7021 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7022 old = SUBREG_REG (old);
7025 /* If is a JUMP_INSN, we can't support output reloads yet. */
7026 if (GET_CODE (insn) == JUMP_INSN)
7029 if (reload_when_needed[j] == RELOAD_OTHER)
7032 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7034 old = reload_out[j];
7036 /* Determine the mode to reload in.
7037 See comments above (for input reloading). */
7039 mode = GET_MODE (old);
7040 if (mode == VOIDmode)
7042 /* VOIDmode should never happen for an output. */
7043 if (asm_noperands (PATTERN (insn)) < 0)
7044 /* It's the compiler's fault. */
7045 fatal_insn ("VOIDmode on an output", insn);
7046 error_for_asm (insn, "output operand is constant in `asm'");
7047 /* Prevent crash--use something we know is valid. */
7049 old = gen_rtx_REG (mode, REGNO (reloadreg));
7052 if (GET_MODE (reloadreg) != mode)
7053 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7055 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7057 /* If we need two reload regs, set RELOADREG to the intermediate
7058 one, since it will be stored into OLD. We might need a secondary
7059 register only for an input reload, so check again here. */
7061 if (reload_secondary_out_reload[j] >= 0)
7065 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7066 && reg_equiv_mem[REGNO (old)] != 0)
7067 real_old = reg_equiv_mem[REGNO (old)];
7069 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7073 second_reloadreg = reloadreg;
7074 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7076 /* See if RELOADREG is to be used as a scratch register
7077 or as an intermediate register. */
7078 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7080 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7081 (real_old, second_reloadreg, reloadreg)));
7086 /* See if we need both a scratch and intermediate reload
7089 int secondary_reload = reload_secondary_out_reload[j];
7090 enum insn_code tertiary_icode
7091 = reload_secondary_out_icode[secondary_reload];
7093 if (GET_MODE (reloadreg) != mode)
7094 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7096 if (tertiary_icode != CODE_FOR_nothing)
7099 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7102 /* Copy primary reload reg to secondary reload reg.
7103 (Note that these have been swapped above, then
7104 secondary reload reg to OLD using our insn. */
7106 /* If REAL_OLD is a paradoxical SUBREG, remove it
7107 and try to put the opposite SUBREG on
7109 if (GET_CODE (real_old) == SUBREG
7110 && (GET_MODE_SIZE (GET_MODE (real_old))
7111 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7112 && 0 != (tem = gen_lowpart_common
7113 (GET_MODE (SUBREG_REG (real_old)),
7115 real_old = SUBREG_REG (real_old), reloadreg = tem;
7117 gen_reload (reloadreg, second_reloadreg,
7118 reload_opnum[j], reload_when_needed[j]);
7119 emit_insn ((GEN_FCN (tertiary_icode)
7120 (real_old, reloadreg, third_reloadreg)));
7125 /* Copy between the reload regs here and then to
7128 gen_reload (reloadreg, second_reloadreg,
7129 reload_opnum[j], reload_when_needed[j]);
7135 /* Output the last reload insn. */
7140 /* Don't output the last reload if OLD is not the dest of
7141 INSN and is in the src and is clobbered by INSN. */
7142 if (! flag_expensive_optimizations
7143 || GET_CODE (old) != REG
7144 || !(set = single_set (insn))
7145 || rtx_equal_p (old, SET_DEST (set))
7146 || !reg_mentioned_p (old, SET_SRC (set))
7147 || !regno_clobbered_p (REGNO (old), insn))
7148 gen_reload (old, reloadreg, reload_opnum[j],
7149 reload_when_needed[j]);
7152 /* Look at all insns we emitted, just to be safe. */
7153 for (p = get_insns (); p; p = NEXT_INSN (p))
7154 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7156 rtx pat = PATTERN (p);
7158 /* If this output reload doesn't come from a spill reg,
7159 clear any memory of reloaded copies of the pseudo reg.
7160 If this output reload comes from a spill reg,
7161 reg_has_output_reload will make this do nothing. */
7162 note_stores (pat, forget_old_reloads_1);
7164 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7166 rtx set = single_set (insn);
7167 if (reload_spill_index[j] < 0
7169 && SET_SRC (set) == reload_reg_rtx[j])
7171 int src = REGNO (SET_SRC (set));
7173 reload_spill_index[j] = src;
7174 SET_HARD_REG_BIT (reg_is_output_reload, src);
7175 if (find_regno_note (insn, REG_DEAD, src))
7176 SET_HARD_REG_BIT (reg_reloaded_died, src);
7178 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7180 int s = reload_secondary_out_reload[j];
7181 set = single_set (p);
7182 /* If this reload copies only to the secondary reload
7183 register, the secondary reload does the actual
7185 if (s >= 0 && set == NULL_RTX)
7186 ; /* We can't tell what function the secondary reload
7187 has and where the actual store to the pseudo is
7188 made; leave new_spill_reg_store alone. */
7190 && SET_SRC (set) == reload_reg_rtx[j]
7191 && SET_DEST (set) == reload_reg_rtx[s])
7193 /* Usually the next instruction will be the
7194 secondary reload insn; if we can confirm
7195 that it is, setting new_spill_reg_store to
7196 that insn will allow an extra optimization. */
7197 rtx s_reg = reload_reg_rtx[s];
7198 rtx next = NEXT_INSN (p);
7199 reload_out[s] = reload_out[j];
7200 reload_out_reg[s] = reload_out_reg[j];
7201 set = single_set (next);
7202 if (set && SET_SRC (set) == s_reg
7203 && ! new_spill_reg_store[REGNO (s_reg)])
7205 SET_HARD_REG_BIT (reg_is_output_reload,
7207 new_spill_reg_store[REGNO (s_reg)] = next;
7211 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7216 if (reload_when_needed[j] == RELOAD_OTHER)
7218 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7219 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7222 output_reload_insns[reload_opnum[j]] = get_insns ();
7228 /* Now write all the insns we made for reloads in the order expected by
7229 the allocation functions. Prior to the insn being reloaded, we write
7230 the following reloads:
7232 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7234 RELOAD_OTHER reloads.
7236 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7237 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7238 RELOAD_FOR_INPUT reload for the operand.
7240 RELOAD_FOR_OPADDR_ADDRS reloads.
7242 RELOAD_FOR_OPERAND_ADDRESS reloads.
7244 After the insn being reloaded, we write the following:
7246 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7247 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7248 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7249 reloads for the operand. The RELOAD_OTHER output reloads are
7250 output in descending order by reload number. */
7252 emit_insns_before (other_input_address_reload_insns, insn);
7253 emit_insns_before (other_input_reload_insns, insn);
7255 for (j = 0; j < reload_n_operands; j++)
7257 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7258 emit_insns_before (input_address_reload_insns[j], insn);
7259 emit_insns_before (input_reload_insns[j], insn);
7262 emit_insns_before (other_operand_reload_insns, insn);
7263 emit_insns_before (operand_reload_insns, insn);
7265 for (j = 0; j < reload_n_operands; j++)
7267 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7268 emit_insns_before (output_address_reload_insns[j], following_insn);
7269 emit_insns_before (output_reload_insns[j], following_insn);
7270 emit_insns_before (other_output_reload_insns[j], following_insn);
7273 /* Keep basic block info up to date. */
7276 if (basic_block_head[chain->block] == insn)
7277 basic_block_head[chain->block] = NEXT_INSN (before_insn);
7278 if (basic_block_end[chain->block] == insn)
7279 basic_block_end[chain->block] = PREV_INSN (following_insn);
7282 /* For all the spill regs newly reloaded in this instruction,
7283 record what they were reloaded from, so subsequent instructions
7284 can inherit the reloads.
7286 Update spill_reg_store for the reloads of this insn.
7287 Copy the elements that were updated in the loop above. */
7289 for (j = 0; j < n_reloads; j++)
7291 register int r = reload_order[j];
7292 register int i = reload_spill_index[r];
7294 /* I is nonneg if this reload used a register.
7295 If reload_reg_rtx[r] is 0, this is an optional reload
7296 that we opted to ignore. */
7298 if (i >= 0 && reload_reg_rtx[r] != 0)
7301 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7303 int part_reaches_end = 0;
7304 int all_reaches_end = 1;
7306 /* For a multi register reload, we need to check if all or part
7307 of the value lives to the end. */
7308 for (k = 0; k < nr; k++)
7310 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7311 reload_when_needed[r]))
7312 part_reaches_end = 1;
7314 all_reaches_end = 0;
7317 /* Ignore reloads that don't reach the end of the insn in
7319 if (all_reaches_end)
7321 /* First, clear out memory of what used to be in this spill reg.
7322 If consecutive registers are used, clear them all. */
7324 for (k = 0; k < nr; k++)
7325 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7327 /* Maybe the spill reg contains a copy of reload_out. */
7328 if (reload_out[r] != 0
7329 && (GET_CODE (reload_out[r]) == REG
7331 || ! reload_out_reg[r]
7333 || GET_CODE (reload_out_reg[r]) == REG))
7335 rtx out = (GET_CODE (reload_out[r]) == REG
7339 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7340 register int nregno = REGNO (out);
7341 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7342 : HARD_REGNO_NREGS (nregno,
7343 GET_MODE (reload_reg_rtx[r])));
7345 spill_reg_store[i] = new_spill_reg_store[i];
7346 spill_reg_stored_to[i] = out;
7347 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7349 /* If NREGNO is a hard register, it may occupy more than
7350 one register. If it does, say what is in the
7351 rest of the registers assuming that both registers
7352 agree on how many words the object takes. If not,
7353 invalidate the subsequent registers. */
7355 if (nregno < FIRST_PSEUDO_REGISTER)
7356 for (k = 1; k < nnr; k++)
7357 reg_last_reload_reg[nregno + k]
7359 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7360 REGNO (reload_reg_rtx[r]) + k)
7363 /* Now do the inverse operation. */
7364 for (k = 0; k < nr; k++)
7366 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7367 reg_reloaded_contents[i + k]
7368 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7371 reg_reloaded_insn[i + k] = insn;
7372 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7376 /* Maybe the spill reg contains a copy of reload_in. Only do
7377 something if there will not be an output reload for
7378 the register being reloaded. */
7379 else if (reload_out_reg[r] == 0
7380 && reload_in[r] != 0
7381 && ((GET_CODE (reload_in[r]) == REG
7382 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7383 && ! reg_has_output_reload[REGNO (reload_in[r])])
7384 || (GET_CODE (reload_in_reg[r]) == REG
7385 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7386 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7388 register int nregno;
7391 if (GET_CODE (reload_in[r]) == REG
7392 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7393 nregno = REGNO (reload_in[r]);
7394 else if (GET_CODE (reload_in_reg[r]) == REG)
7395 nregno = REGNO (reload_in_reg[r]);
7397 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7399 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7400 : HARD_REGNO_NREGS (nregno,
7401 GET_MODE (reload_reg_rtx[r])));
7403 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7405 if (nregno < FIRST_PSEUDO_REGISTER)
7406 for (k = 1; k < nnr; k++)
7407 reg_last_reload_reg[nregno + k]
7409 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7410 REGNO (reload_reg_rtx[r]) + k)
7413 /* Unless we inherited this reload, show we haven't
7414 recently done a store.
7415 Previous stores of inherited auto_inc expressions
7416 also have to be discarded. */
7417 if (! reload_inherited[r]
7418 || (reload_out[r] && ! reload_out_reg[r]))
7419 spill_reg_store[i] = 0;
7421 for (k = 0; k < nr; k++)
7423 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7424 reg_reloaded_contents[i + k]
7425 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7428 reg_reloaded_insn[i + k] = insn;
7429 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7434 /* However, if part of the reload reaches the end, then we must
7435 invalidate the old info for the part that survives to the end. */
7436 else if (part_reaches_end)
7438 for (k = 0; k < nr; k++)
7439 if (reload_reg_reaches_end_p (i + k,
7441 reload_when_needed[r]))
7442 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7446 /* The following if-statement was #if 0'd in 1.34 (or before...).
7447 It's reenabled in 1.35 because supposedly nothing else
7448 deals with this problem. */
7450 /* If a register gets output-reloaded from a non-spill register,
7451 that invalidates any previous reloaded copy of it.
7452 But forget_old_reloads_1 won't get to see it, because
7453 it thinks only about the original insn. So invalidate it here. */
7454 if (i < 0 && reload_out[r] != 0
7455 && (GET_CODE (reload_out[r]) == REG
7456 || (GET_CODE (reload_out[r]) == MEM
7457 && GET_CODE (reload_out_reg[r]) == REG)))
7459 rtx out = (GET_CODE (reload_out[r]) == REG
7460 ? reload_out[r] : reload_out_reg[r]);
7461 register int nregno = REGNO (out);
7462 if (nregno >= FIRST_PSEUDO_REGISTER)
7464 rtx src_reg, store_insn;
7466 reg_last_reload_reg[nregno] = 0;
7468 /* If we can find a hard register that is stored, record
7469 the storing insn so that we may delete this insn with
7470 delete_output_reload. */
7471 src_reg = reload_reg_rtx[r];
7473 /* If this is an optional reload, try to find the source reg
7474 from an input reload. */
7477 rtx set = single_set (insn);
7478 if (SET_DEST (set) == reload_out[r])
7482 src_reg = SET_SRC (set);
7484 for (k = 0; k < n_reloads; k++)
7486 if (reload_in[k] == src_reg)
7488 src_reg = reload_reg_rtx[k];
7495 store_insn = new_spill_reg_store[REGNO (src_reg)];
7496 if (src_reg && GET_CODE (src_reg) == REG
7497 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7499 int src_regno = REGNO (src_reg);
7500 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7501 /* The place where to find a death note varies with
7502 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7503 necessarily checked exactly in the code that moves
7504 notes, so just check both locations. */
7505 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7507 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7510 spill_reg_store[src_regno + nr] = store_insn;
7511 spill_reg_stored_to[src_regno + nr] = out;
7512 reg_reloaded_contents[src_regno + nr] = nregno;
7513 reg_reloaded_insn[src_regno + nr] = store_insn;
7514 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7515 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7517 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7519 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7521 reg_last_reload_reg[nregno] = src_reg;
7526 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7528 while (num_regs-- > 0)
7529 reg_last_reload_reg[nregno + num_regs] = 0;
7533 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7536 /* Emit code to perform a reload from IN (which may be a reload register) to
7537 OUT (which may also be a reload register). IN or OUT is from operand
7538 OPNUM with reload type TYPE.
7540 Returns first insn emitted. */
7543 gen_reload (out, in, opnum, type)
7547 enum reload_type type;
7549 rtx last = get_last_insn ();
7552 /* If IN is a paradoxical SUBREG, remove it and try to put the
7553 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7554 if (GET_CODE (in) == SUBREG
7555 && (GET_MODE_SIZE (GET_MODE (in))
7556 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7557 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7558 in = SUBREG_REG (in), out = tem;
7559 else if (GET_CODE (out) == SUBREG
7560 && (GET_MODE_SIZE (GET_MODE (out))
7561 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7562 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7563 out = SUBREG_REG (out), in = tem;
7565 /* How to do this reload can get quite tricky. Normally, we are being
7566 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7567 register that didn't get a hard register. In that case we can just
7568 call emit_move_insn.
7570 We can also be asked to reload a PLUS that adds a register or a MEM to
7571 another register, constant or MEM. This can occur during frame pointer
7572 elimination and while reloading addresses. This case is handled by
7573 trying to emit a single insn to perform the add. If it is not valid,
7574 we use a two insn sequence.
7576 Finally, we could be called to handle an 'o' constraint by putting
7577 an address into a register. In that case, we first try to do this
7578 with a named pattern of "reload_load_address". If no such pattern
7579 exists, we just emit a SET insn and hope for the best (it will normally
7580 be valid on machines that use 'o').
7582 This entire process is made complex because reload will never
7583 process the insns we generate here and so we must ensure that
7584 they will fit their constraints and also by the fact that parts of
7585 IN might be being reloaded separately and replaced with spill registers.
7586 Because of this, we are, in some sense, just guessing the right approach
7587 here. The one listed above seems to work.
7589 ??? At some point, this whole thing needs to be rethought. */
7591 if (GET_CODE (in) == PLUS
7592 && (GET_CODE (XEXP (in, 0)) == REG
7593 || GET_CODE (XEXP (in, 0)) == SUBREG
7594 || GET_CODE (XEXP (in, 0)) == MEM)
7595 && (GET_CODE (XEXP (in, 1)) == REG
7596 || GET_CODE (XEXP (in, 1)) == SUBREG
7597 || CONSTANT_P (XEXP (in, 1))
7598 || GET_CODE (XEXP (in, 1)) == MEM))
7600 /* We need to compute the sum of a register or a MEM and another
7601 register, constant, or MEM, and put it into the reload
7602 register. The best possible way of doing this is if the machine
7603 has a three-operand ADD insn that accepts the required operands.
7605 The simplest approach is to try to generate such an insn and see if it
7606 is recognized and matches its constraints. If so, it can be used.
7608 It might be better not to actually emit the insn unless it is valid,
7609 but we need to pass the insn as an operand to `recog' and
7610 `insn_extract' and it is simpler to emit and then delete the insn if
7611 not valid than to dummy things up. */
7613 rtx op0, op1, tem, insn;
7616 op0 = find_replacement (&XEXP (in, 0));
7617 op1 = find_replacement (&XEXP (in, 1));
7619 /* Since constraint checking is strict, commutativity won't be
7620 checked, so we need to do that here to avoid spurious failure
7621 if the add instruction is two-address and the second operand
7622 of the add is the same as the reload reg, which is frequently
7623 the case. If the insn would be A = B + A, rearrange it so
7624 it will be A = A + B as constrain_operands expects. */
7626 if (GET_CODE (XEXP (in, 1)) == REG
7627 && REGNO (out) == REGNO (XEXP (in, 1)))
7628 tem = op0, op0 = op1, op1 = tem;
7630 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7631 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7633 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7634 code = recog_memoized (insn);
7638 insn_extract (insn);
7639 /* We want constrain operands to treat this insn strictly in
7640 its validity determination, i.e., the way it would after reload
7642 if (constrain_operands (code, 1))
7646 delete_insns_since (last);
7648 /* If that failed, we must use a conservative two-insn sequence.
7649 use move to copy constant, MEM, or pseudo register to the reload
7650 register since "move" will be able to handle an arbitrary operand,
7651 unlike add which can't, in general. Then add the registers.
7653 If there is another way to do this for a specific machine, a
7654 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7657 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7658 || (GET_CODE (op1) == REG
7659 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7660 tem = op0, op0 = op1, op1 = tem;
7662 gen_reload (out, op0, opnum, type);
7664 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7665 This fixes a problem on the 32K where the stack pointer cannot
7666 be used as an operand of an add insn. */
7668 if (rtx_equal_p (op0, op1))
7671 insn = emit_insn (gen_add2_insn (out, op1));
7673 /* If that failed, copy the address register to the reload register.
7674 Then add the constant to the reload register. */
7676 code = recog_memoized (insn);
7680 insn_extract (insn);
7681 /* We want constrain operands to treat this insn strictly in
7682 its validity determination, i.e., the way it would after reload
7684 if (constrain_operands (code, 1))
7686 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7688 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7693 delete_insns_since (last);
7695 gen_reload (out, op1, opnum, type);
7696 insn = emit_insn (gen_add2_insn (out, op0));
7697 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7700 #ifdef SECONDARY_MEMORY_NEEDED
7701 /* If we need a memory location to do the move, do it that way. */
7702 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7703 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7704 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7705 REGNO_REG_CLASS (REGNO (out)),
7708 /* Get the memory to use and rewrite both registers to its mode. */
7709 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7711 if (GET_MODE (loc) != GET_MODE (out))
7712 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7714 if (GET_MODE (loc) != GET_MODE (in))
7715 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7717 gen_reload (loc, in, opnum, type);
7718 gen_reload (out, loc, opnum, type);
7722 /* If IN is a simple operand, use gen_move_insn. */
7723 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7724 emit_insn (gen_move_insn (out, in));
7726 #ifdef HAVE_reload_load_address
7727 else if (HAVE_reload_load_address)
7728 emit_insn (gen_reload_load_address (out, in));
7731 /* Otherwise, just write (set OUT IN) and hope for the best. */
7733 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7735 /* Return the first insn emitted.
7736 We can not just return get_last_insn, because there may have
7737 been multiple instructions emitted. Also note that gen_move_insn may
7738 emit more than one insn itself, so we can not assume that there is one
7739 insn emitted per emit_insn_before call. */
7741 return last ? NEXT_INSN (last) : get_insns ();
7744 /* Delete a previously made output-reload
7745 whose result we now believe is not needed.
7746 First we double-check.
7748 INSN is the insn now being processed.
7749 LAST_RELOAD_REG is the hard register number for which we want to delete
7750 the last output reload.
7751 J is the reload-number that originally used REG. The caller has made
7752 certain that reload J doesn't use REG any longer for input. */
7755 delete_output_reload (insn, j, last_reload_reg)
7758 int last_reload_reg;
7760 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7761 rtx reg = spill_reg_stored_to[last_reload_reg];
7764 int n_inherited = 0;
7768 /* Get the raw pseudo-register referred to. */
7770 while (GET_CODE (reg) == SUBREG)
7771 reg = SUBREG_REG (reg);
7772 substed = reg_equiv_memory_loc[REGNO (reg)];
7774 /* This is unsafe if the operand occurs more often in the current
7775 insn than it is inherited. */
7776 for (k = n_reloads - 1; k >= 0; k--)
7778 rtx reg2 = reload_in[k];
7781 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7782 reg2 = reload_in_reg[k];
7784 if (reload_out[k] && ! reload_out_reg[k])
7785 reg2 = XEXP (reload_in_reg[k], 0);
7787 while (GET_CODE (reg2) == SUBREG)
7788 reg2 = SUBREG_REG (reg2);
7789 if (rtx_equal_p (reg2, reg))
7790 if (reload_inherited[k] || reload_override_in[k] || k == j)
7793 reg2 = reload_out_reg[k];
7796 while (GET_CODE (reg2) == SUBREG)
7797 reg2 = XEXP (reg2, 0);
7798 if (rtx_equal_p (reg2, reg))
7804 n_occurrences = count_occurrences (PATTERN (insn), reg);
7806 n_occurrences += count_occurrences (PATTERN (insn), substed);
7807 if (n_occurrences > n_inherited)
7810 /* If the pseudo-reg we are reloading is no longer referenced
7811 anywhere between the store into it and here,
7812 and no jumps or labels intervene, then the value can get
7813 here through the reload reg alone.
7814 Otherwise, give up--return. */
7815 for (i1 = NEXT_INSN (output_reload_insn);
7816 i1 != insn; i1 = NEXT_INSN (i1))
7818 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7820 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7821 && reg_mentioned_p (reg, PATTERN (i1)))
7823 /* If this is USE in front of INSN, we only have to check that
7824 there are no more references than accounted for by inheritance. */
7825 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7827 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7828 i1 = NEXT_INSN (i1);
7830 if (n_occurrences <= n_inherited && i1 == insn)
7836 /* The caller has already checked that REG dies or is set in INSN.
7837 It has also checked that we are optimizing, and thus some inaccurancies
7838 in the debugging information are acceptable.
7839 So we could just delete output_reload_insn.
7840 But in some cases we can improve the debugging information without
7841 sacrificing optimization - maybe even improving the code:
7842 See if the pseudo reg has been completely replaced
7843 with reload regs. If so, delete the store insn
7844 and forget we had a stack slot for the pseudo. */
7845 if (reload_out[j] != reload_in[j]
7846 && REG_N_DEATHS (REGNO (reg)) == 1
7847 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7848 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7852 /* We know that it was used only between here
7853 and the beginning of the current basic block.
7854 (We also know that the last use before INSN was
7855 the output reload we are thinking of deleting, but never mind that.)
7856 Search that range; see if any ref remains. */
7857 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7859 rtx set = single_set (i2);
7861 /* Uses which just store in the pseudo don't count,
7862 since if they are the only uses, they are dead. */
7863 if (set != 0 && SET_DEST (set) == reg)
7865 if (GET_CODE (i2) == CODE_LABEL
7866 || GET_CODE (i2) == JUMP_INSN)
7868 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7869 && reg_mentioned_p (reg, PATTERN (i2)))
7871 /* Some other ref remains; just delete the output reload we
7873 delete_address_reloads (output_reload_insn, insn);
7874 PUT_CODE (output_reload_insn, NOTE);
7875 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7876 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7881 /* Delete the now-dead stores into this pseudo. */
7882 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7884 rtx set = single_set (i2);
7886 if (set != 0 && SET_DEST (set) == reg)
7888 delete_address_reloads (i2, insn);
7889 /* This might be a basic block head,
7890 thus don't use delete_insn. */
7891 PUT_CODE (i2, NOTE);
7892 NOTE_SOURCE_FILE (i2) = 0;
7893 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7895 if (GET_CODE (i2) == CODE_LABEL
7896 || GET_CODE (i2) == JUMP_INSN)
7900 /* For the debugging info,
7901 say the pseudo lives in this reload reg. */
7902 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7903 alter_reg (REGNO (reg), -1);
7905 delete_address_reloads (output_reload_insn, insn);
7906 PUT_CODE (output_reload_insn, NOTE);
7907 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7908 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7912 /* We are going to delete DEAD_INSN. Recursively delete loads of
7913 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7914 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7916 delete_address_reloads (dead_insn, current_insn)
7917 rtx dead_insn, current_insn;
7919 rtx set = single_set (dead_insn);
7920 rtx set2, dst, prev, next;
7923 rtx dst = SET_DEST (set);
7924 if (GET_CODE (dst) == MEM)
7925 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7927 /* If we deleted the store from a reloaded post_{in,de}c expression,
7928 we can delete the matching adds. */
7929 prev = PREV_INSN (dead_insn);
7930 next = NEXT_INSN (dead_insn);
7931 if (! prev || ! next)
7933 set = single_set (next);
7934 set2 = single_set (prev);
7936 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7937 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7938 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7940 dst = SET_DEST (set);
7941 if (! rtx_equal_p (dst, SET_DEST (set2))
7942 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7943 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7944 || (INTVAL (XEXP (SET_SRC (set), 1))
7945 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7951 /* Subfunction of delete_address_reloads: process registers found in X. */
7953 delete_address_reloads_1 (dead_insn, x, current_insn)
7954 rtx dead_insn, x, current_insn;
7956 rtx prev, set, dst, i2;
7958 enum rtx_code code = GET_CODE (x);
7962 char *fmt= GET_RTX_FORMAT (code);
7963 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7966 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7967 else if (fmt[i] == 'E')
7969 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7970 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7977 if (spill_reg_order[REGNO (x)] < 0)
7980 /* Scan backwards for the insn that sets x. This might be a way back due
7982 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7984 code = GET_CODE (prev);
7985 if (code == CODE_LABEL || code == JUMP_INSN)
7987 if (GET_RTX_CLASS (code) != 'i')
7989 if (reg_set_p (x, PATTERN (prev)))
7991 if (reg_referenced_p (x, PATTERN (prev)))
7994 if (! prev || INSN_UID (prev) < reload_first_uid)
7996 /* Check that PREV only sets the reload register. */
7997 set = single_set (prev);
8000 dst = SET_DEST (set);
8001 if (GET_CODE (dst) != REG
8002 || ! rtx_equal_p (dst, x))
8004 if (! reg_set_p (dst, PATTERN (dead_insn)))
8006 /* Check if DST was used in a later insn -
8007 it might have been inherited. */
8008 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8010 if (GET_CODE (i2) == CODE_LABEL)
8012 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8014 if (reg_referenced_p (dst, PATTERN (i2)))
8016 /* If there is a reference to the register in the current insn,
8017 it might be loaded in a non-inherited reload. If no other
8018 reload uses it, that means the register is set before
8020 if (i2 == current_insn)
8022 for (j = n_reloads - 1; j >= 0; j--)
8023 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8024 || reload_override_in[j] == dst)
8026 for (j = n_reloads - 1; j >= 0; j--)
8027 if (reload_in[j] && reload_reg_rtx[j] == dst)
8034 if (GET_CODE (i2) == JUMP_INSN)
8036 if (reg_set_p (dst, PATTERN (i2)))
8038 /* If DST is still live at CURRENT_INSN, check if it is used for
8040 if (i2 == current_insn)
8042 for (j = n_reloads - 1; j >= 0; j--)
8043 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8044 || reload_override_in[j] == dst)
8046 /* ??? We can't finish the loop here, because dst might be
8047 allocated to a pseudo in this block if no reload in this
8048 block needs any of the clsses containing DST - see
8049 spill_hard_reg. There is no easy way to tell this, so we
8050 have to scan till the end of the basic block. */
8054 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8055 reg_reloaded_contents[REGNO (dst)] = -1;
8056 /* Can't use delete_insn here because PREV might be a basic block head. */
8057 PUT_CODE (prev, NOTE);
8058 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8059 NOTE_SOURCE_FILE (prev) = 0;
8062 /* Output reload-insns to reload VALUE into RELOADREG.
8063 VALUE is an autoincrement or autodecrement RTX whose operand
8064 is a register or memory location;
8065 so reloading involves incrementing that location.
8066 IN is either identical to VALUE, or some cheaper place to reload from.
8068 INC_AMOUNT is the number to increment or decrement by (always positive).
8069 This cannot be deduced from VALUE.
8071 Return the instruction that stores into RELOADREG. */
8074 inc_for_reload (reloadreg, in, value, inc_amount)
8079 /* REG or MEM to be copied and incremented. */
8080 rtx incloc = XEXP (value, 0);
8081 /* Nonzero if increment after copying. */
8082 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8088 rtx real_in = in == value ? XEXP (in, 0) : in;
8090 /* No hard register is equivalent to this register after
8091 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8092 we could inc/dec that register as well (maybe even using it for
8093 the source), but I'm not sure it's worth worrying about. */
8094 if (GET_CODE (incloc) == REG)
8095 reg_last_reload_reg[REGNO (incloc)] = 0;
8097 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8098 inc_amount = - inc_amount;
8100 inc = GEN_INT (inc_amount);
8102 /* If this is post-increment, first copy the location to the reload reg. */
8103 if (post && real_in != reloadreg)
8104 emit_insn (gen_move_insn (reloadreg, real_in));
8108 /* See if we can directly increment INCLOC. Use a method similar to
8109 that in gen_reload. */
8111 last = get_last_insn ();
8112 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8113 gen_rtx_PLUS (GET_MODE (incloc),
8116 code = recog_memoized (add_insn);
8119 insn_extract (add_insn);
8120 if (constrain_operands (code, 1))
8122 /* If this is a pre-increment and we have incremented the value
8123 where it lives, copy the incremented value to RELOADREG to
8124 be used as an address. */
8127 emit_insn (gen_move_insn (reloadreg, incloc));
8132 delete_insns_since (last);
8135 /* If couldn't do the increment directly, must increment in RELOADREG.
8136 The way we do this depends on whether this is pre- or post-increment.
8137 For pre-increment, copy INCLOC to the reload register, increment it
8138 there, then save back. */
8142 if (in != reloadreg)
8143 emit_insn (gen_move_insn (reloadreg, real_in));
8144 emit_insn (gen_add2_insn (reloadreg, inc));
8145 store = emit_insn (gen_move_insn (incloc, reloadreg));
8150 Because this might be a jump insn or a compare, and because RELOADREG
8151 may not be available after the insn in an input reload, we must do
8152 the incrementation before the insn being reloaded for.
8154 We have already copied IN to RELOADREG. Increment the copy in
8155 RELOADREG, save that back, then decrement RELOADREG so it has
8156 the original value. */
8158 emit_insn (gen_add2_insn (reloadreg, inc));
8159 store = emit_insn (gen_move_insn (incloc, reloadreg));
8160 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8166 /* Return 1 if we are certain that the constraint-string STRING allows
8167 the hard register REG. Return 0 if we can't be sure of this. */
8170 constraint_accepts_reg_p (string, reg)
8175 int regno = true_regnum (reg);
8178 /* Initialize for first alternative. */
8180 /* Check that each alternative contains `g' or `r'. */
8182 switch (c = *string++)
8185 /* If an alternative lacks `g' or `r', we lose. */
8188 /* If an alternative lacks `g' or `r', we lose. */
8191 /* Initialize for next alternative. */
8196 /* Any general reg wins for this alternative. */
8197 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8201 /* Any reg in specified class wins for this alternative. */
8203 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8205 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8211 /* Return the number of places FIND appears within X, but don't count
8212 an occurrence if some SET_DEST is FIND. */
8215 count_occurrences (x, find)
8216 register rtx x, find;
8219 register enum rtx_code code;
8220 register char *format_ptr;
8228 code = GET_CODE (x);
8243 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8247 if (SET_DEST (x) == find)
8248 return count_occurrences (SET_SRC (x), find);
8255 format_ptr = GET_RTX_FORMAT (code);
8258 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8260 switch (*format_ptr++)
8263 count += count_occurrences (XEXP (x, i), find);
8267 if (XVEC (x, i) != NULL)
8269 for (j = 0; j < XVECLEN (x, i); j++)
8270 count += count_occurrences (XVECEXP (x, i, j), find);
8278 /* This array holds values which are equivalent to a hard register
8279 during reload_cse_regs. Each array element is an EXPR_LIST of
8280 values. Each time a hard register is set, we set the corresponding
8281 array element to the value. Each time a hard register is copied
8282 into memory, we add the memory location to the corresponding array
8283 element. We don't store values or memory addresses with side
8284 effects in this array.
8286 If the value is a CONST_INT, then the mode of the containing
8287 EXPR_LIST is the mode in which that CONST_INT was referenced.
8289 We sometimes clobber a specific entry in a list. In that case, we
8290 just set XEXP (list-entry, 0) to 0. */
8292 static rtx *reg_values;
8294 /* This is a preallocated REG rtx which we use as a temporary in
8295 reload_cse_invalidate_regno, so that we don't need to allocate a
8296 new one each time through a loop in that function. */
8298 static rtx invalidate_regno_rtx;
8300 /* Invalidate any entries in reg_values which depend on REGNO,
8301 including those for REGNO itself. This is called if REGNO is
8302 changing. If CLOBBER is true, then always forget anything we
8303 currently know about REGNO. MODE is the mode of the assignment to
8304 REGNO, which is used to determine how many hard registers are being
8305 changed. If MODE is VOIDmode, then only REGNO is being changed;
8306 this is used when invalidating call clobbered registers across a
8310 reload_cse_invalidate_regno (regno, mode, clobber)
8312 enum machine_mode mode;
8318 /* Our callers don't always go through true_regnum; we may see a
8319 pseudo-register here from a CLOBBER or the like. We probably
8320 won't ever see a pseudo-register that has a real register number,
8321 for we check anyhow for safety. */
8322 if (regno >= FIRST_PSEUDO_REGISTER)
8323 regno = reg_renumber[regno];
8327 if (mode == VOIDmode)
8328 endregno = regno + 1;
8330 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8333 for (i = regno; i < endregno; i++)
8336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8340 for (x = reg_values[i]; x; x = XEXP (x, 1))
8342 if (XEXP (x, 0) != 0
8343 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8345 /* If this is the only entry on the list, clear
8346 reg_values[i]. Otherwise, just clear this entry on
8348 if (XEXP (x, 1) == 0 && x == reg_values[i])
8358 /* We must look at earlier registers, in case REGNO is part of a
8359 multi word value but is not the first register. If an earlier
8360 register has a value in a mode which overlaps REGNO, then we must
8361 invalidate that earlier register. Note that we do not need to
8362 check REGNO or later registers (we must not check REGNO itself,
8363 because we would incorrectly conclude that there was a conflict). */
8365 for (i = 0; i < regno; i++)
8369 for (x = reg_values[i]; x; x = XEXP (x, 1))
8371 if (XEXP (x, 0) != 0)
8373 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8374 REGNO (invalidate_regno_rtx) = i;
8375 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8378 reload_cse_invalidate_regno (i, VOIDmode, 1);
8386 /* The memory at address MEM_BASE is being changed.
8387 Return whether this change will invalidate VAL. */
8390 reload_cse_mem_conflict_p (mem_base, val)
8398 code = GET_CODE (val);
8401 /* Get rid of a few simple cases quickly. */
8414 if (GET_MODE (mem_base) == BLKmode
8415 || GET_MODE (val) == BLKmode)
8417 if (anti_dependence (val, mem_base))
8419 /* The address may contain nested MEMs. */
8426 fmt = GET_RTX_FORMAT (code);
8428 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8432 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8435 else if (fmt[i] == 'E')
8439 for (j = 0; j < XVECLEN (val, i); j++)
8440 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8448 /* Invalidate any entries in reg_values which are changed because of a
8449 store to MEM_RTX. If this is called because of a non-const call
8450 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8453 reload_cse_invalidate_mem (mem_rtx)
8458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8462 for (x = reg_values[i]; x; x = XEXP (x, 1))
8464 if (XEXP (x, 0) != 0
8465 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8467 /* If this is the only entry on the list, clear
8468 reg_values[i]. Otherwise, just clear this entry on
8470 if (XEXP (x, 1) == 0 && x == reg_values[i])
8481 /* Invalidate DEST, which is being assigned to or clobbered. The
8482 second parameter exists so that this function can be passed to
8483 note_stores; it is ignored. */
8486 reload_cse_invalidate_rtx (dest, ignore)
8488 rtx ignore ATTRIBUTE_UNUSED;
8490 while (GET_CODE (dest) == STRICT_LOW_PART
8491 || GET_CODE (dest) == SIGN_EXTRACT
8492 || GET_CODE (dest) == ZERO_EXTRACT
8493 || GET_CODE (dest) == SUBREG)
8494 dest = XEXP (dest, 0);
8496 if (GET_CODE (dest) == REG)
8497 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8498 else if (GET_CODE (dest) == MEM)
8499 reload_cse_invalidate_mem (dest);
8502 /* Do a very simple CSE pass over the hard registers.
8504 This function detects no-op moves where we happened to assign two
8505 different pseudo-registers to the same hard register, and then
8506 copied one to the other. Reload will generate a useless
8507 instruction copying a register to itself.
8509 This function also detects cases where we load a value from memory
8510 into two different registers, and (if memory is more expensive than
8511 registers) changes it to simply copy the first register into the
8514 Another optimization is performed that scans the operands of each
8515 instruction to see whether the value is already available in a
8516 hard register. It then replaces the operand with the hard register
8517 if possible, much like an optional reload would. */
8520 reload_cse_regs_1 (first)
8528 init_alias_analysis ();
8530 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8531 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8533 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8534 free them when we are done. */
8535 push_obstacks (&reload_obstack, &reload_obstack);
8536 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8538 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8539 memory for a non-const call instruction. */
8540 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8542 /* This is used in reload_cse_invalidate_regno to avoid consing a
8543 new REG in a loop in that function. */
8544 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8546 for (insn = first; insn; insn = NEXT_INSN (insn))
8550 if (GET_CODE (insn) == CODE_LABEL)
8552 /* Forget all the register values at a code label. We don't
8553 try to do anything clever around jumps. */
8554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8560 #ifdef NON_SAVING_SETJMP
8561 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8562 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8564 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8571 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8574 /* If this is a call instruction, forget anything stored in a
8575 call clobbered register, or, if this is not a const call, in
8577 if (GET_CODE (insn) == CALL_INSN)
8579 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8580 if (call_used_regs[i])
8581 reload_cse_invalidate_regno (i, VOIDmode, 1);
8583 if (! CONST_CALL_P (insn))
8584 reload_cse_invalidate_mem (callmem);
8587 body = PATTERN (insn);
8588 if (GET_CODE (body) == SET)
8591 if (reload_cse_noop_set_p (body, insn))
8593 /* If this sets the return value of the function, we must keep
8594 a USE around, in case this is in a different basic block
8595 than the final USE. Otherwise, we could loose important
8596 register lifeness information on SMALL_REGISTER_CLASSES
8597 machines, where return registers might be used as spills:
8598 subsequent passes assume that spill registers are dead at
8599 the end of a basic block. */
8600 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8603 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8604 INSN_CODE (insn) = -1;
8605 REG_NOTES (insn) = NULL_RTX;
8606 push_obstacks (&reload_obstack, &reload_obstack);
8610 PUT_CODE (insn, NOTE);
8611 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8612 NOTE_SOURCE_FILE (insn) = 0;
8615 /* We're done with this insn. */
8619 /* It's not a no-op, but we can try to simplify it. */
8620 count += reload_cse_simplify_set (body, insn);
8623 apply_change_group ();
8625 reload_cse_simplify_operands (insn);
8627 reload_cse_record_set (body, body);
8629 else if (GET_CODE (body) == PARALLEL)
8632 rtx value = NULL_RTX;
8634 /* If every action in a PARALLEL is a noop, we can delete
8635 the entire PARALLEL. */
8636 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8638 rtx part = XVECEXP (body, 0, i);
8639 if (GET_CODE (part) == SET)
8641 if (! reload_cse_noop_set_p (part, insn))
8643 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8647 value = SET_DEST (part);
8650 else if (GET_CODE (part) != CLOBBER)
8658 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8659 INSN_CODE (insn) = -1;
8660 REG_NOTES (insn) = NULL_RTX;
8661 push_obstacks (&reload_obstack, &reload_obstack);
8665 PUT_CODE (insn, NOTE);
8666 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8667 NOTE_SOURCE_FILE (insn) = 0;
8670 /* We're done with this insn. */
8674 /* It's not a no-op, but we can try to simplify it. */
8675 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8676 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8677 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8680 apply_change_group ();
8682 reload_cse_simplify_operands (insn);
8684 /* Look through the PARALLEL and record the values being
8685 set, if possible. Also handle any CLOBBERs. */
8686 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8688 rtx x = XVECEXP (body, 0, i);
8690 if (GET_CODE (x) == SET)
8691 reload_cse_record_set (x, body);
8693 note_stores (x, reload_cse_invalidate_rtx);
8697 note_stores (body, reload_cse_invalidate_rtx);
8700 /* Clobber any registers which appear in REG_INC notes. We
8701 could keep track of the changes to their values, but it is
8702 unlikely to help. */
8706 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8707 if (REG_NOTE_KIND (x) == REG_INC)
8708 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8712 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8713 after we have processed the insn. */
8714 if (GET_CODE (insn) == CALL_INSN)
8718 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8719 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8720 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8724 /* Free all the temporary structures we created, and go back to the
8725 regular obstacks. */
8726 obstack_free (&reload_obstack, firstobj);
8730 /* Call cse / combine like post-reload optimization phases.
8731 FIRST is the first instruction. */
8733 reload_cse_regs (first)
8736 reload_cse_regs_1 (first);
8738 reload_cse_move2add (first);
8739 if (flag_expensive_optimizations)
8740 reload_cse_regs_1 (first);
8743 /* Return whether the values known for REGNO are equal to VAL. MODE
8744 is the mode of the object that VAL is being copied to; this matters
8745 if VAL is a CONST_INT. */
8748 reload_cse_regno_equal_p (regno, val, mode)
8751 enum machine_mode mode;
8758 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8759 if (XEXP (x, 0) != 0
8760 && rtx_equal_p (XEXP (x, 0), val)
8761 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8762 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8763 && (GET_CODE (val) != CONST_INT
8764 || mode == GET_MODE (x)
8765 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8766 /* On a big endian machine if the value spans more than
8767 one register then this register holds the high part of
8768 it and we can't use it.
8770 ??? We should also compare with the high part of the
8772 && !(WORDS_BIG_ENDIAN
8773 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8774 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8775 GET_MODE_BITSIZE (GET_MODE (x))))))
8781 /* See whether a single set is a noop. SET is the set instruction we
8782 are should check, and INSN is the instruction from which it came. */
8785 reload_cse_noop_set_p (set, insn)
8790 enum machine_mode dest_mode;
8794 src = SET_SRC (set);
8795 dest = SET_DEST (set);
8796 dest_mode = GET_MODE (dest);
8798 if (side_effects_p (src))
8801 dreg = true_regnum (dest);
8802 sreg = true_regnum (src);
8804 /* Check for setting a register to itself. In this case, we don't
8805 have to worry about REG_DEAD notes. */
8806 if (dreg >= 0 && dreg == sreg)
8812 /* Check for setting a register to itself. */
8816 /* Check for setting a register to a value which we already know
8817 is in the register. */
8818 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8821 /* Check for setting a register DREG to another register SREG
8822 where SREG is equal to a value which is already in DREG. */
8827 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8831 if (XEXP (x, 0) == 0)
8834 if (dest_mode == GET_MODE (x))
8836 else if (GET_MODE_BITSIZE (dest_mode)
8837 < GET_MODE_BITSIZE (GET_MODE (x)))
8838 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8843 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8851 else if (GET_CODE (dest) == MEM)
8853 /* Check for storing a register to memory when we know that the
8854 register is equivalent to the memory location. */
8856 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8857 && ! side_effects_p (dest))
8864 /* Try to simplify a single SET instruction. SET is the set pattern.
8865 INSN is the instruction it came from.
8866 This function only handles one case: if we set a register to a value
8867 which is not a register, we try to find that value in some other register
8868 and change the set into a register copy. */
8871 reload_cse_simplify_set (set, insn)
8877 enum machine_mode dest_mode;
8878 enum reg_class dclass;
8881 dreg = true_regnum (SET_DEST (set));
8885 src = SET_SRC (set);
8886 if (side_effects_p (src) || true_regnum (src) >= 0)
8889 dclass = REGNO_REG_CLASS (dreg);
8891 /* If memory loads are cheaper than register copies, don't change them. */
8892 if (GET_CODE (src) == MEM
8893 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8896 /* If the constant is cheaper than a register, don't change it. */
8897 if (CONSTANT_P (src)
8898 && rtx_cost (src, SET) < 2)
8901 dest_mode = GET_MODE (SET_DEST (set));
8902 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8905 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8906 && reload_cse_regno_equal_p (i, src, dest_mode))
8910 /* Pop back to the real obstacks while changing the insn. */
8913 validated = validate_change (insn, &SET_SRC (set),
8914 gen_rtx_REG (dest_mode, i), 1);
8916 /* Go back to the obstack we are using for temporary
8918 push_obstacks (&reload_obstack, &reload_obstack);
8927 /* Try to replace operands in INSN with equivalent values that are already
8928 in registers. This can be viewed as optional reloading.
8930 For each non-register operand in the insn, see if any hard regs are
8931 known to be equivalent to that operand. Record the alternatives which
8932 can accept these hard registers. Among all alternatives, select the
8933 ones which are better or equal to the one currently matching, where
8934 "better" is in terms of '?' and '!' constraints. Among the remaining
8935 alternatives, select the one which replaces most operands with
8939 reload_cse_simplify_operands (insn)
8942 #ifdef REGISTER_CONSTRAINTS
8943 int insn_code_number, n_operands, n_alternatives;
8946 char *constraints[MAX_RECOG_OPERANDS];
8948 /* Vector recording how bad an alternative is. */
8949 int *alternative_reject;
8950 /* Vector recording how many registers can be introduced by choosing
8951 this alternative. */
8952 int *alternative_nregs;
8953 /* Array of vectors recording, for each operand and each alternative,
8954 which hard register to substitute, or -1 if the operand should be
8956 int *op_alt_regno[MAX_RECOG_OPERANDS];
8957 /* Array of alternatives, sorted in order of decreasing desirability. */
8958 int *alternative_order;
8959 rtx reg = gen_rtx_REG (VOIDmode, -1);
8961 /* Find out some information about this insn. */
8962 insn_code_number = recog_memoized (insn);
8963 /* We don't modify asm instructions. */
8964 if (insn_code_number < 0)
8967 n_operands = insn_n_operands[insn_code_number];
8968 n_alternatives = insn_n_alternatives[insn_code_number];
8970 if (n_alternatives == 0 || n_operands == 0)
8972 insn_extract (insn);
8974 /* Figure out which alternative currently matches. */
8975 if (! constrain_operands (insn_code_number, 1))
8976 fatal_insn_not_found (insn);
8978 alternative_reject = (int *) alloca (n_alternatives * sizeof (int));
8979 alternative_nregs = (int *) alloca (n_alternatives * sizeof (int));
8980 alternative_order = (int *) alloca (n_alternatives * sizeof (int));
8981 bzero ((char *)alternative_reject, n_alternatives * sizeof (int));
8982 bzero ((char *)alternative_nregs, n_alternatives * sizeof (int));
8984 for (i = 0; i < n_operands; i++)
8986 enum machine_mode mode;
8990 op_alt_regno[i] = (int *) alloca (n_alternatives * sizeof (int));
8991 for (j = 0; j < n_alternatives; j++)
8992 op_alt_regno[i][j] = -1;
8994 p = constraints[i] = insn_operand_constraint[insn_code_number][i];
8995 mode = insn_operand_mode[insn_code_number][i];
8997 /* Add the reject values for each alternative given by the constraints
8998 for this operand. */
9006 alternative_reject[j] += 3;
9008 alternative_reject[j] += 300;
9011 /* We won't change operands which are already registers. We
9012 also don't want to modify output operands. */
9013 regno = true_regnum (recog_operand[i]);
9015 || constraints[i][0] == '='
9016 || constraints[i][0] == '+')
9019 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9021 int class = (int) NO_REGS;
9023 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9026 REGNO (reg) = regno;
9027 PUT_MODE (reg, mode);
9029 /* We found a register equal to this operand. Now look for all
9030 alternatives that can accept this register and have not been
9031 assigned a register they can use yet. */
9040 case '=': case '+': case '?':
9041 case '#': case '&': case '!':
9043 case '0': case '1': case '2': case '3': case '4':
9044 case 'm': case '<': case '>': case 'V': case 'o':
9045 case 'E': case 'F': case 'G': case 'H':
9046 case 's': case 'i': case 'n':
9047 case 'I': case 'J': case 'K': case 'L':
9048 case 'M': case 'N': case 'O': case 'P':
9049 #ifdef EXTRA_CONSTRAINT
9050 case 'Q': case 'R': case 'S': case 'T': case 'U':
9053 /* These don't say anything we care about. */
9057 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9062 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9065 case ',': case '\0':
9066 /* See if REGNO fits this alternative, and set it up as the
9067 replacement register if we don't have one for this
9068 alternative yet and the operand being replaced is not
9069 a cheap CONST_INT. */
9070 if (op_alt_regno[i][j] == -1
9071 && reg_fits_class_p (reg, class, 0, mode)
9072 && (GET_CODE (recog_operand[i]) != CONST_INT
9073 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9075 alternative_nregs[j]++;
9076 op_alt_regno[i][j] = regno;
9088 /* Record all alternatives which are better or equal to the currently
9089 matching one in the alternative_order array. */
9090 for (i = j = 0; i < n_alternatives; i++)
9091 if (alternative_reject[i] <= alternative_reject[which_alternative])
9092 alternative_order[j++] = i;
9095 /* Sort it. Given a small number of alternatives, a dumb algorithm
9096 won't hurt too much. */
9097 for (i = 0; i < n_alternatives - 1; i++)
9100 int best_reject = alternative_reject[alternative_order[i]];
9101 int best_nregs = alternative_nregs[alternative_order[i]];
9104 for (j = i + 1; j < n_alternatives; j++)
9106 int this_reject = alternative_reject[alternative_order[j]];
9107 int this_nregs = alternative_nregs[alternative_order[j]];
9109 if (this_reject < best_reject
9110 || (this_reject == best_reject && this_nregs < best_nregs))
9113 best_reject = this_reject;
9114 best_nregs = this_nregs;
9118 tmp = alternative_order[best];
9119 alternative_order[best] = alternative_order[i];
9120 alternative_order[i] = tmp;
9123 /* Substitute the operands as determined by op_alt_regno for the best
9125 j = alternative_order[0];
9127 /* Pop back to the real obstacks while changing the insn. */
9130 for (i = 0; i < n_operands; i++)
9132 enum machine_mode mode = insn_operand_mode[insn_code_number][i];
9133 if (op_alt_regno[i][j] == -1)
9136 validate_change (insn, recog_operand_loc[i],
9137 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9140 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
9142 int op = recog_dup_num[i];
9143 enum machine_mode mode = insn_operand_mode[insn_code_number][op];
9145 if (op_alt_regno[op][j] == -1)
9148 validate_change (insn, recog_dup_loc[i],
9149 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9152 /* Go back to the obstack we are using for temporary
9154 push_obstacks (&reload_obstack, &reload_obstack);
9156 return apply_change_group ();
9162 /* These two variables are used to pass information from
9163 reload_cse_record_set to reload_cse_check_clobber. */
9165 static int reload_cse_check_clobbered;
9166 static rtx reload_cse_check_src;
9168 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9169 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9170 second argument, which is passed by note_stores, is ignored. */
9173 reload_cse_check_clobber (dest, ignore)
9175 rtx ignore ATTRIBUTE_UNUSED;
9177 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9178 reload_cse_check_clobbered = 1;
9181 /* Record the result of a SET instruction. SET is the set pattern.
9182 BODY is the pattern of the insn that it came from. */
9185 reload_cse_record_set (set, body)
9191 enum machine_mode dest_mode;
9193 dest = SET_DEST (set);
9194 src = SET_SRC (set);
9195 dreg = true_regnum (dest);
9196 sreg = true_regnum (src);
9197 dest_mode = GET_MODE (dest);
9199 /* Some machines don't define AUTO_INC_DEC, but they still use push
9200 instructions. We need to catch that case here in order to
9201 invalidate the stack pointer correctly. Note that invalidating
9202 the stack pointer is different from invalidating DEST. */
9204 while (GET_CODE (x) == SUBREG
9205 || GET_CODE (x) == ZERO_EXTRACT
9206 || GET_CODE (x) == SIGN_EXTRACT
9207 || GET_CODE (x) == STRICT_LOW_PART)
9209 if (push_operand (x, GET_MODE (x)))
9211 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9212 reload_cse_invalidate_rtx (dest, NULL_RTX);
9216 /* We can only handle an assignment to a register, or a store of a
9217 register to a memory location. For other cases, we just clobber
9218 the destination. We also have to just clobber if there are side
9219 effects in SRC or DEST. */
9220 if ((dreg < 0 && GET_CODE (dest) != MEM)
9221 || side_effects_p (src)
9222 || side_effects_p (dest))
9224 reload_cse_invalidate_rtx (dest, NULL_RTX);
9229 /* We don't try to handle values involving CC, because it's a pain
9230 to keep track of when they have to be invalidated. */
9231 if (reg_mentioned_p (cc0_rtx, src)
9232 || reg_mentioned_p (cc0_rtx, dest))
9234 reload_cse_invalidate_rtx (dest, NULL_RTX);
9239 /* If BODY is a PARALLEL, then we need to see whether the source of
9240 SET is clobbered by some other instruction in the PARALLEL. */
9241 if (GET_CODE (body) == PARALLEL)
9245 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9249 x = XVECEXP (body, 0, i);
9253 reload_cse_check_clobbered = 0;
9254 reload_cse_check_src = src;
9255 note_stores (x, reload_cse_check_clobber);
9256 if (reload_cse_check_clobbered)
9258 reload_cse_invalidate_rtx (dest, NULL_RTX);
9268 /* This is an assignment to a register. Update the value we
9269 have stored for the register. */
9274 /* This is a copy from one register to another. Any values
9275 which were valid for SREG are now valid for DREG. If the
9276 mode changes, we use gen_lowpart_common to extract only
9277 the part of the value that is copied. */
9278 reg_values[dreg] = 0;
9279 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9283 if (XEXP (x, 0) == 0)
9285 if (dest_mode == GET_MODE (XEXP (x, 0)))
9287 else if (GET_MODE_BITSIZE (dest_mode)
9288 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9291 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9293 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9298 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9300 /* We've changed DREG, so invalidate any values held by other
9301 registers that depend upon it. */
9302 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9304 /* If this assignment changes more than one hard register,
9305 forget anything we know about the others. */
9306 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9307 reg_values[dreg + i] = 0;
9309 else if (GET_CODE (dest) == MEM)
9311 /* Invalidate conflicting memory locations. */
9312 reload_cse_invalidate_mem (dest);
9314 /* If we're storing a register to memory, add DEST to the list
9316 if (sreg >= 0 && ! side_effects_p (dest))
9317 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9322 /* We should have bailed out earlier. */
9327 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9329 This code might also be useful when reload gave up on reg+reg addresssing
9330 because of clashes between the return register and INDEX_REG_CLASS. */
9332 /* The maximum number of uses of a register we can keep track of to
9333 replace them with reg+reg addressing. */
9334 #define RELOAD_COMBINE_MAX_USES 6
9336 /* INSN is the insn where a register has ben used, and USEP points to the
9337 location of the register within the rtl. */
9338 struct reg_use { rtx insn, *usep; };
9340 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9341 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9342 indicates where it becomes live again.
9343 Otherwise, USE_INDEX is the index of the last encountered use of the
9344 register (which is first among these we have seen since we scan backwards),
9345 OFFSET contains the constant offset that is added to the register in
9346 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9347 last, of these uses. */
9350 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9355 } reg_state[FIRST_PSEUDO_REGISTER];
9357 /* Reverse linear uid. This is increased in reload_combine while scanning
9358 the instructions from last to first. It is used to set last_label_ruid
9359 and the store_ruid / use_ruid fields in reg_state. */
9360 static int reload_combine_ruid;
9366 int first_index_reg = 1, last_index_reg = 0;
9368 int last_label_ruid;
9370 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9371 reload has already used it where appropriate, so there is no use in
9372 trying to generate it now. */
9373 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9376 /* To avoid wasting too much time later searching for an index register,
9377 determine the minimum and maximum index register numbers. */
9378 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9380 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9382 if (! last_index_reg)
9384 first_index_reg = i;
9387 /* If no index register is available, we can quit now. */
9388 if (first_index_reg > last_index_reg)
9391 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9392 last_label_ruid = reload_combine_ruid = 0;
9393 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9396 reg_state[i].use_index = -1;
9399 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9400 reg_state[i].store_ruid = reload_combine_ruid;
9404 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9408 /* We cannot do our optimization across labels. Invalidating all the use
9409 information we have would be costly, so we just note where the label
9410 is and then later disable any optimization that would cross it. */
9411 if (GET_CODE (insn) == CODE_LABEL)
9412 last_label_ruid = reload_combine_ruid;
9413 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9415 reload_combine_ruid++;
9417 /* Look for (set (REGX) (CONST_INT))
9418 (set (REGX) (PLUS (REGX) (REGY)))
9420 ... (MEM (REGX)) ...
9422 (set (REGZ) (CONST_INT))
9424 ... (MEM (PLUS (REGZ) (REGY)))... .
9426 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9427 and that we know all uses of REGX before it dies. */
9428 set = single_set (insn);
9430 && GET_CODE (SET_DEST (set)) == REG
9431 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9432 GET_MODE (SET_DEST (set)))
9434 && GET_CODE (SET_SRC (set)) == PLUS
9435 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9436 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9437 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9439 rtx reg = SET_DEST (set);
9440 rtx plus = SET_SRC (set);
9441 rtx base = XEXP (plus, 1);
9442 rtx prev = prev_nonnote_insn (insn);
9443 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9444 int regno = REGNO (reg);
9446 rtx reg_sum = NULL_RTX;
9448 /* Now, we need an index register.
9449 We'll set index_reg to this index register, const_reg to the
9450 register that is to be loaded with the constant
9451 (denoted as REGZ in the substitution illustration above),
9452 and reg_sum to the register-register that we want to use to
9453 substitute uses of REG (typically in MEMs) with.
9454 First check REG and BASE for being index registers;
9455 we can use them even if they are not dead. */
9456 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9457 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9465 /* Otherwise, look for a free index register. Since we have
9466 checked above that neiter REG nor BASE are index registers,
9467 if we find anything at all, it will be different from these
9469 for (i = first_index_reg; i <= last_index_reg; i++)
9471 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9472 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9473 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9474 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9476 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9477 const_reg = index_reg;
9478 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9484 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9485 && rtx_equal_p (SET_DEST (prev_set), reg)
9486 && reg_state[regno].use_index >= 0
9491 /* Change destination register and - if necessary - the
9492 constant value in PREV, the constant loading instruction. */
9493 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9494 if (reg_state[regno].offset != const0_rtx)
9495 validate_change (prev,
9496 &SET_SRC (prev_set),
9497 GEN_INT (INTVAL (SET_SRC (prev_set))
9498 + INTVAL (reg_state[regno].offset)),
9500 /* Now for every use of REG that we have recorded, replace REG
9502 for (i = reg_state[regno].use_index;
9503 i < RELOAD_COMBINE_MAX_USES; i++)
9504 validate_change (reg_state[regno].reg_use[i].insn,
9505 reg_state[regno].reg_use[i].usep,
9508 if (apply_change_group ())
9512 /* Delete the reg-reg addition. */
9513 PUT_CODE (insn, NOTE);
9514 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9515 NOTE_SOURCE_FILE (insn) = 0;
9517 if (reg_state[regno].offset != const0_rtx)
9519 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9521 for (np = ®_NOTES (prev); *np; )
9523 if (REG_NOTE_KIND (*np) == REG_EQUAL
9524 || REG_NOTE_KIND (*np) == REG_EQUIV)
9525 *np = XEXP (*np, 1);
9527 np = &XEXP (*np, 1);
9530 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9531 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9536 note_stores (PATTERN (insn), reload_combine_note_store);
9537 if (GET_CODE (insn) == CALL_INSN)
9541 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9543 if (call_used_regs[i])
9545 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9546 reg_state[i].store_ruid = reload_combine_ruid;
9549 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9550 link = XEXP (link, 1))
9552 rtx use = XEXP (link, 0);
9553 int regno = REGNO (XEXP (use, 0));
9554 if (GET_CODE (use) == CLOBBER)
9556 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9557 reg_state[regno].store_ruid = reload_combine_ruid;
9560 reg_state[regno].use_index = -1;
9563 if (GET_CODE (insn) == JUMP_INSN)
9565 /* Non-spill registers might be used at the call destination in
9566 some unknown fashion, so we have to mark the unknown use. */
9567 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9570 reg_state[i].use_index = -1;
9573 reload_combine_note_use (&PATTERN (insn), insn);
9574 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9576 if (REG_NOTE_KIND (note) == REG_INC
9577 && GET_CODE (XEXP (note, 0)) == REG)
9578 reg_state[REGNO (XEXP (note, 0))].use_index = -1;
9583 /* Check if DST is a register or a subreg of a register; if it is,
9584 update reg_state[regno].store_ruid and reg_state[regno].use_index
9585 accordingly. Called via note_stores from reload_combine.
9586 The second argument, SET, is ignored. */
9588 reload_combine_note_store (dst, set)
9589 rtx dst, set ATTRIBUTE_UNUSED;
9593 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9595 if (GET_CODE (dst) == SUBREG)
9597 regno = SUBREG_WORD (dst);
9598 dst = SUBREG_REG (dst);
9600 if (GET_CODE (dst) != REG)
9602 regno += REGNO (dst);
9603 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9604 careful with registers / register parts that are not full words. */
9605 if (size < (unsigned) UNITS_PER_WORD)
9606 reg_state[regno].use_index = -1;
9609 for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
9611 reg_state[i].store_ruid = reload_combine_ruid;
9612 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9617 /* XP points to a piece of rtl that has to be checked for any uses of
9619 *XP is the pattern of INSN, or a part of it.
9620 Called from reload_combine, and recursively by itself. */
9622 reload_combine_note_use (xp, insn)
9626 enum rtx_code code = x->code;
9629 rtx offset = const0_rtx; /* For the REG case below. */
9634 if (GET_CODE (SET_DEST (x)) == REG)
9636 reload_combine_note_use (&SET_SRC (x), insn);
9642 if (GET_CODE (SET_DEST (x)) == REG)
9647 /* We are interested in (plus (reg) (const_int)) . */
9648 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9650 offset = XEXP (x, 1);
9655 int regno = REGNO (x);
9658 /* Some spurious USEs of pseudo registers might remain.
9659 Just ignore them. */
9660 if (regno >= FIRST_PSEUDO_REGISTER)
9663 /* If this register is already used in some unknown fashion, we
9665 If we decrement the index from zero to -1, we can't store more
9666 uses, so this register becomes used in an unknown fashion. */
9667 use_index = --reg_state[regno].use_index;
9671 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9673 /* We have found another use for a register that is already
9674 used later. Check if the offsets match; if not, mark the
9675 register as used in an unknown fashion. */
9676 if (! rtx_equal_p (offset, reg_state[regno].offset))
9678 reg_state[regno].use_index = -1;
9684 /* This is the first use of this register we have seen since we
9685 marked it as dead. */
9686 reg_state[regno].offset = offset;
9687 reg_state[regno].use_ruid = reload_combine_ruid;
9689 reg_state[regno].reg_use[use_index].insn = insn;
9690 reg_state[regno].reg_use[use_index].usep = xp;
9698 /* Recursively process the components of X. */
9699 fmt = GET_RTX_FORMAT (code);
9700 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9703 reload_combine_note_use (&XEXP (x, i), insn);
9704 else if (fmt[i] == 'E')
9706 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9707 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9712 /* See if we can reduce the cost of a constant by replacing a move with
9714 /* We cannot do our optimization across labels. Invalidating all the
9715 information about register contents we have would be costly, so we
9716 use last_label_luid (local variable of reload_cse_move2add) to note
9717 where the label is and then later disable any optimization that would
9719 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9720 reg_set_luid[n] is larger than last_label_luid[n] . */
9721 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9722 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9723 reg_mode[n] to be valid.
9724 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9725 has been set to reg_offset[n] in mode reg_mode[n] .
9726 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9727 register n has been set to the sum of reg_offset[n] and register
9728 reg_base_reg[n], calculated in mode reg_mode[n] . */
9729 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9730 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9731 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9732 /* move2add_luid is linearily increased while scanning the instructions
9733 from first to last. It is used to set reg_set_luid in
9734 reload_cse_move2add and move2add_note_store. */
9735 static int move2add_luid;
9738 reload_cse_move2add (first)
9743 int last_label_luid;
9745 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9746 reg_set_luid[i] = 0;
9748 last_label_luid = 0;
9750 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9754 if (GET_CODE (insn) == CODE_LABEL)
9755 last_label_luid = move2add_luid;
9756 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9758 pat = PATTERN (insn);
9759 /* For simplicity, we only perform this optimization on
9760 straightforward SETs. */
9761 if (GET_CODE (pat) == SET
9762 && GET_CODE (SET_DEST (pat)) == REG)
9764 rtx reg = SET_DEST (pat);
9765 int regno = REGNO (reg);
9766 rtx src = SET_SRC (pat);
9768 /* Check if we have valid information on the contents of this
9769 register in the mode of REG. */
9770 /* ??? We don't know how zero / sign extension is handled, hence
9771 we can't go from a narrower to a wider mode. */
9772 if (reg_set_luid[regno] > last_label_luid
9773 && (GET_MODE_SIZE (GET_MODE (reg))
9774 <= GET_MODE_SIZE (reg_mode[regno]))
9775 && GET_CODE (reg_offset[regno]) == CONST_INT)
9777 /* Try to transform (set (REGX) (CONST_INT A))
9779 (set (REGX) (CONST_INT B))
9781 (set (REGX) (CONST_INT A))
9783 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9785 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9788 rtx new_src = GEN_INT (INTVAL (src)
9789 - INTVAL (reg_offset[regno]));
9790 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9791 use (set (reg) (reg)) instead.
9792 We don't delete this insn, nor do we convert it into a
9793 note, to avoid losing register notes or the return
9794 value flag. jump2 already knowns how to get rid of
9796 if (new_src == const0_rtx)
9797 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9798 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9799 && have_add2_insn (GET_MODE (reg)))
9800 success = validate_change (insn, &PATTERN (insn),
9801 gen_add2_insn (reg, new_src), 0);
9802 reg_set_luid[regno] = move2add_luid;
9803 reg_mode[regno] = GET_MODE (reg);
9804 reg_offset[regno] = src;
9808 /* Try to transform (set (REGX) (REGY))
9809 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9812 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9815 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9817 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9818 else if (GET_CODE (src) == REG
9819 && reg_base_reg[regno] == REGNO (src)
9820 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9822 rtx next = next_nonnote_insn (insn);
9825 set = single_set (next);
9828 && SET_DEST (set) == reg
9829 && GET_CODE (SET_SRC (set)) == PLUS
9830 && XEXP (SET_SRC (set), 0) == reg
9831 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9833 rtx src3 = XEXP (SET_SRC (set), 1);
9834 rtx new_src = GEN_INT (INTVAL (src3)
9835 - INTVAL (reg_offset[regno]));
9838 if (new_src == const0_rtx)
9839 /* See above why we create (set (reg) (reg)) here. */
9841 = validate_change (next, &SET_SRC (set), reg, 0);
9842 else if ((rtx_cost (new_src, PLUS)
9843 < 2 + rtx_cost (src3, SET))
9844 && have_add2_insn (GET_MODE (reg)))
9846 = validate_change (next, &PATTERN (next),
9847 gen_add2_insn (reg, new_src), 0);
9850 /* INSN might be the first insn in a basic block
9851 if the preceding insn is a conditional jump
9852 or a possible-throwing call. */
9853 PUT_CODE (insn, NOTE);
9854 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9855 NOTE_SOURCE_FILE (insn) = 0;
9858 reg_set_luid[regno] = move2add_luid;
9859 reg_mode[regno] = GET_MODE (reg);
9860 reg_offset[regno] = src3;
9867 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9869 if (REG_NOTE_KIND (note) == REG_INC
9870 && GET_CODE (XEXP (note, 0)) == REG)
9872 /* Indicate that this register has been recently written to,
9873 but the exact contents are not available. */
9874 int regno = REGNO (XEXP (note, 0));
9875 if (regno < FIRST_PSEUDO_REGISTER)
9877 reg_set_luid[regno] = move2add_luid;
9878 reg_offset[regno] = note;
9882 note_stores (PATTERN (insn), move2add_note_store);
9883 /* If this is a CALL_INSN, all call used registers are stored with
9885 if (GET_CODE (insn) == CALL_INSN)
9887 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9889 if (call_used_regs[i])
9891 reg_set_luid[i] = move2add_luid;
9892 reg_offset[i] = insn; /* Invalidate contents. */
9899 /* SET is a SET or CLOBBER that sets DST.
9900 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9901 Called from reload_cse_move2add via note_stores. */
9903 move2add_note_store (dst, set)
9909 enum machine_mode mode = GET_MODE (dst);
9910 if (GET_CODE (dst) == SUBREG)
9912 regno = SUBREG_WORD (dst);
9913 dst = SUBREG_REG (dst);
9915 if (GET_CODE (dst) != REG)
9918 regno += REGNO (dst);
9920 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
9922 rtx src = SET_SRC (set);
9924 reg_mode[regno] = mode;
9925 switch (GET_CODE (src))
9929 rtx src0 = XEXP (src, 0);
9930 if (GET_CODE (src0) == REG)
9932 if (REGNO (src0) != regno
9933 || reg_offset[regno] != const0_rtx)
9935 reg_base_reg[regno] = REGNO (src0);
9936 reg_set_luid[regno] = move2add_luid;
9938 reg_offset[regno] = XEXP (src, 1);
9941 reg_set_luid[regno] = move2add_luid;
9942 reg_offset[regno] = set; /* Invalidate contents. */
9947 reg_base_reg[regno] = REGNO (SET_SRC (set));
9948 reg_offset[regno] = const0_rtx;
9949 reg_set_luid[regno] = move2add_luid;
9953 reg_base_reg[regno] = -1;
9954 reg_offset[regno] = SET_SRC (set);
9955 reg_set_luid[regno] = move2add_luid;
9961 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9963 /* Indicate that this register has been recently written to,
9964 but the exact contents are not available. */
9965 reg_set_luid[i] = move2add_luid;
9966 reg_offset[i] = dst;