1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #define LOCAL_REGNO(REGNO) 0
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx *reg_equiv_memory_loc;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs[FIRST_PSEUDO_REGISTER];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET *pseudo_previous_regs;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET *pseudo_forbidden_regs;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg;
216 /* Nonzero if indirect addressing is supported on the machine; this means
217 that spilling (REG n) does not require reloading it into a register in
218 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
219 value indicates the level of indirect addressing supported, e.g., two
220 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
222 static char spill_indirect_levels;
224 /* Nonzero if indirect addressing is supported when the innermost MEM is
225 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
226 which these are valid is the same as spill_indirect_levels, above. */
227 char indirect_symref_ok;
229 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
233 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
235 /* Width allocated so far for that stack slot. */
236 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
238 /* Record which pseudos needed to be spilled. */
239 static regset_head spilled_pseudos;
241 /* Used for communication between order_regs_for_reload and count_pseudo.
242 Used to avoid counting one pseudo twice. */
243 static regset_head pseudos_counted;
245 /* First uid used by insns created by reload in this function.
246 Used in find_equiv_reg. */
247 int reload_first_uid;
249 /* Flag set by local-alloc or global-alloc if anything is live in
250 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* Set to 1 while reload_as_needed is operating.
254 Required by some machines to handle any generated moves differently. */
255 int reload_in_progress = 0;
257 /* These arrays record the insn_code of insns that may be needed to
258 perform input and output reloads of special objects. They provide a
259 place to pass a scratch register. */
260 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
261 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
263 /* This obstack is used for allocation of rtl during register elimination.
264 The allocated storage can be freed once find_reloads has processed the
266 struct obstack reload_obstack;
268 /* Points to the beginning of the reload_obstack. All insn_chain structures
269 are allocated first. */
270 char *reload_startobj;
272 /* The point after all insn_chain structures. Used to quickly deallocate
273 memory allocated in copy_reloads during calculate_needs_all_insns. */
274 char *reload_firstobj;
276 /* This points before all local rtl generated by register elimination.
277 Used to quickly free all memory after processing one insn. */
278 static char *reload_insn_firstobj;
280 /* List of insn_chain instructions, one for every insn that reload needs to
282 struct insn_chain *reload_insn_chain;
284 /* List of all insns needing reloads. */
285 static struct insn_chain *insns_need_reload;
287 /* This structure is used to record information about register eliminations.
288 Each array entry describes one possible way of eliminating a register
289 in favor of another. If there is more than one way of eliminating a
290 particular register, the most preferred should be specified first. */
294 int from; /* Register number to be eliminated. */
295 int to; /* Register number used as replacement. */
296 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
297 int can_eliminate; /* Nonzero if this elimination can be done. */
298 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
299 insns made by reload. */
300 HOST_WIDE_INT offset; /* Current offset between the two regs. */
301 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
302 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
303 rtx from_rtx; /* REG rtx for the register to be eliminated.
304 We cannot simply compare the number since
305 we might then spuriously replace a hard
306 register corresponding to a pseudo
307 assigned to the reg to be eliminated. */
308 rtx to_rtx; /* REG rtx for the replacement. */
311 static struct elim_table *reg_eliminate = 0;
313 /* This is an intermediate structure to initialize the table. It has
314 exactly the members provided by ELIMINABLE_REGS. */
315 static const struct elim_table_1
319 } reg_eliminate_1[] =
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If nonzero, we use a new copy of each
335 replacement result in any insns encountered. */
336 int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
340 /* And the number of registers that are equivalent to a constant that
341 can be eliminated to frame_pointer / arg_pointer + constant. */
342 static int num_eliminable_invariants;
344 /* For each label, we record the offset of each elimination. If we reach
345 a label by more than one path and an offset differs, we cannot do the
346 elimination. This information is indexed by the difference of the
347 number of the label and the first label number. We can't offset the
348 pointer itself as this can cause problems on machines with segmented
349 memory. The first table is an array of flags that records whether we
350 have yet encountered a label and the second table is an array of arrays,
351 one entry in the latter array for each elimination. */
353 static int first_label_num;
354 static char *offsets_known_at;
355 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
357 /* Number of labels in the current function. */
359 static int num_labels;
361 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
362 static void maybe_fix_stack_asms (void);
363 static void copy_reloads (struct insn_chain *);
364 static void calculate_needs_all_insns (int);
365 static int find_reg (struct insn_chain *, int);
366 static void find_reload_regs (struct insn_chain *);
367 static void select_reload_regs (void);
368 static void delete_caller_save_insns (void);
370 static void spill_failure (rtx, enum reg_class);
371 static void count_spilled_pseudo (int, int, int);
372 static void delete_dead_insn (rtx);
373 static void alter_reg (int, int);
374 static void set_label_offsets (rtx, rtx, int);
375 static void check_eliminable_occurrences (rtx);
376 static void elimination_effects (rtx, enum machine_mode);
377 static int eliminate_regs_in_insn (rtx, int);
378 static void update_eliminable_offsets (void);
379 static void mark_not_eliminable (rtx, rtx, void *);
380 static void set_initial_elim_offsets (void);
381 static void verify_initial_elim_offsets (void);
382 static void set_initial_label_offsets (void);
383 static void set_offsets_for_label (rtx);
384 static void init_elim_table (void);
385 static void update_eliminables (HARD_REG_SET *);
386 static void spill_hard_reg (unsigned int, int);
387 static int finish_spills (int);
388 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
389 static void scan_paradoxical_subregs (rtx);
390 static void count_pseudo (int);
391 static void order_regs_for_reload (struct insn_chain *);
392 static void reload_as_needed (int);
393 static void forget_old_reloads_1 (rtx, rtx, void *);
394 static int reload_reg_class_lower (const void *, const void *);
395 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
397 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
399 static int reload_reg_free_p (unsigned int, int, enum reload_type);
400 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
402 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
404 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
405 static int allocate_reload_reg (struct insn_chain *, int, int);
406 static int conflicts_with_override (rtx);
407 static void failed_reload (rtx, int);
408 static int set_reload_reg (int, int);
409 static void choose_reload_regs_init (struct insn_chain *, rtx *);
410 static void choose_reload_regs (struct insn_chain *);
411 static void merge_assigned_reloads (rtx);
412 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
414 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
416 static void do_input_reload (struct insn_chain *, struct reload *, int);
417 static void do_output_reload (struct insn_chain *, struct reload *, int);
418 static void emit_reload_insns (struct insn_chain *);
419 static void delete_output_reload (rtx, int, int);
420 static void delete_address_reloads (rtx, rtx);
421 static void delete_address_reloads_1 (rtx, rtx, rtx);
422 static rtx inc_for_reload (rtx, rtx, rtx, int);
424 static void add_auto_inc_notes (rtx, rtx);
426 static void copy_eh_notes (rtx, rtx);
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode,
443 LAST_VIRTUAL_REGISTER + 1),
445 spill_indirect_levels = 0;
447 while (memory_address_p (QImode, tem))
449 spill_indirect_levels++;
450 tem = gen_rtx_MEM (Pmode, tem);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
456 indirect_symref_ok = memory_address_p (QImode, tem);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
462 tem = gen_rtx_PLUS (Pmode,
463 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
464 gen_rtx_REG (Pmode, i));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem = plus_constant (tem, 4);
469 if (memory_address_p (QImode, tem))
471 double_reg_address_ok = 1;
476 /* Initialize obstack for our rtl allocation. */
477 gcc_obstack_init (&reload_obstack);
478 reload_startobj = obstack_alloc (&reload_obstack, 0);
480 INIT_REG_SET (&spilled_pseudos);
481 INIT_REG_SET (&pseudos_counted);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain *unused_insn_chains = 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain *c;
493 if (unused_insn_chains == 0)
495 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
496 INIT_REG_SET (&c->live_throughout);
497 INIT_REG_SET (&c->dead_or_set);
501 c = unused_insn_chains;
502 unused_insn_chains = c->next;
504 c->is_caller_save_insn = 0;
505 c->need_operand_change = 0;
511 /* Small utility function to set all regs in hard reg set TO which are
512 allocated to pseudos in regset FROM. */
515 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
519 EXECUTE_IF_SET_IN_REG_SET
520 (from, FIRST_PSEUDO_REGISTER, regno,
522 int r = reg_renumber[regno];
527 /* reload_combine uses the information from
528 BASIC_BLOCK->global_live_at_start, which might still
529 contain registers that have not actually been allocated
530 since they have an equivalence. */
531 if (! reload_completed)
536 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
538 SET_HARD_REG_BIT (*to, r + nregs);
543 /* Replace all pseudos found in LOC with their corresponding
547 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
560 unsigned int regno = REGNO (x);
562 if (regno < FIRST_PSEUDO_REGISTER)
565 x = eliminate_regs (x, mem_mode, usage);
569 replace_pseudos_in (loc, mem_mode, usage);
573 if (reg_equiv_constant[regno])
574 *loc = reg_equiv_constant[regno];
575 else if (reg_equiv_mem[regno])
576 *loc = reg_equiv_mem[regno];
577 else if (reg_equiv_address[regno])
578 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
579 else if (GET_CODE (regno_reg_rtx[regno]) != REG
580 || REGNO (regno_reg_rtx[regno]) != regno)
581 *loc = regno_reg_rtx[regno];
587 else if (code == MEM)
589 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
593 /* Process each of our operands recursively. */
594 fmt = GET_RTX_FORMAT (code);
595 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
597 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
598 else if (*fmt == 'E')
599 for (j = 0; j < XVECLEN (x, i); j++)
600 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
604 /* Global variables used by reload and its subroutines. */
606 /* Set during calculate_needs if an insn needs register elimination. */
607 static int something_needs_elimination;
608 /* Set during calculate_needs if an insn needs an operand changed. */
609 int something_needs_operands_changed;
611 /* Nonzero means we couldn't get enough spill regs. */
614 /* Main entry point for the reload pass.
616 FIRST is the first insn of the function being compiled.
618 GLOBAL nonzero means we were called from global_alloc
619 and should attempt to reallocate any pseudoregs that we
620 displace from hard regs we will use for reloads.
621 If GLOBAL is zero, we do not have enough information to do that,
622 so any pseudo reg that is spilled must go to the stack.
624 Return value is nonzero if reload failed
625 and we must not do any more for this function. */
628 reload (rtx first, int global)
632 struct elim_table *ep;
635 /* Make sure even insns with volatile mem refs are recognizable. */
640 reload_firstobj = obstack_alloc (&reload_obstack, 0);
642 /* Make sure that the last insn in the chain
643 is not something that needs reloading. */
644 emit_note (NOTE_INSN_DELETED);
646 /* Enable find_equiv_reg to distinguish insns made by reload. */
647 reload_first_uid = get_max_uid ();
649 #ifdef SECONDARY_MEMORY_NEEDED
650 /* Initialize the secondary memory table. */
651 clear_secondary_mem ();
654 /* We don't have a stack slot for any spill reg yet. */
655 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
656 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
658 /* Initialize the save area information for caller-save, in case some
662 /* Compute which hard registers are now in use
663 as homes for pseudo registers.
664 This is done here rather than (eg) in global_alloc
665 because this point is reached even if not optimizing. */
666 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
669 /* A function that receives a nonlocal goto must save all call-saved
671 if (current_function_has_nonlocal_label)
672 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
673 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
674 regs_ever_live[i] = 1;
676 /* Find all the pseudo registers that didn't get hard regs
677 but do have known equivalent constants or memory slots.
678 These include parameters (known equivalent to parameter slots)
679 and cse'd or loop-moved constant memory addresses.
681 Record constant equivalents in reg_equiv_constant
682 so they will be substituted by find_reloads.
683 Record memory equivalents in reg_mem_equiv so they can
684 be substituted eventually by altering the REG-rtx's. */
686 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
687 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
688 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
689 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
690 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
691 reg_old_renumber = xcalloc (max_regno, sizeof (short));
692 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
693 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
694 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
696 CLEAR_HARD_REG_SET (bad_spill_regs_global);
698 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
699 Also find all paradoxical subregs and find largest such for each pseudo.
700 On machines with small register classes, record hard registers that
701 are used for user variables. These can never be used for spills.
702 Also look for a "constant" REG_SETJMP. This means that all
703 caller-saved registers must be marked live. */
705 num_eliminable_invariants = 0;
706 for (insn = first; insn; insn = NEXT_INSN (insn))
708 rtx set = single_set (insn);
710 /* We may introduce USEs that we want to remove at the end, so
711 we'll mark them with QImode. Make sure there are no
712 previously-marked insns left by say regmove. */
713 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
714 && GET_MODE (insn) != VOIDmode)
715 PUT_MODE (insn, VOIDmode);
717 if (GET_CODE (insn) == CALL_INSN
718 && find_reg_note (insn, REG_SETJMP, NULL))
719 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
720 if (! call_used_regs[i])
721 regs_ever_live[i] = 1;
723 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
725 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
727 #ifdef LEGITIMATE_PIC_OPERAND_P
728 && (! function_invariant_p (XEXP (note, 0))
730 /* A function invariant is often CONSTANT_P but may
731 include a register. We promise to only pass
732 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
733 || (CONSTANT_P (XEXP (note, 0))
734 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
738 rtx x = XEXP (note, 0);
739 i = REGNO (SET_DEST (set));
740 if (i > LAST_VIRTUAL_REGISTER)
742 /* It can happen that a REG_EQUIV note contains a MEM
743 that is not a legitimate memory operand. As later
744 stages of reload assume that all addresses found
745 in the reg_equiv_* arrays were originally legitimate,
746 we ignore such REG_EQUIV notes. */
747 if (memory_operand (x, VOIDmode))
749 /* Always unshare the equivalence, so we can
750 substitute into this insn without touching the
752 reg_equiv_memory_loc[i] = copy_rtx (x);
754 else if (function_invariant_p (x))
756 if (GET_CODE (x) == PLUS)
758 /* This is PLUS of frame pointer and a constant,
759 and might be shared. Unshare it. */
760 reg_equiv_constant[i] = copy_rtx (x);
761 num_eliminable_invariants++;
763 else if (x == frame_pointer_rtx
764 || x == arg_pointer_rtx)
766 reg_equiv_constant[i] = x;
767 num_eliminable_invariants++;
769 else if (LEGITIMATE_CONSTANT_P (x))
770 reg_equiv_constant[i] = x;
773 reg_equiv_memory_loc[i]
774 = force_const_mem (GET_MODE (SET_DEST (set)), x);
775 if (!reg_equiv_memory_loc[i])
782 /* If this register is being made equivalent to a MEM
783 and the MEM is not SET_SRC, the equivalencing insn
784 is one with the MEM as a SET_DEST and it occurs later.
785 So don't mark this insn now. */
786 if (GET_CODE (x) != MEM
787 || rtx_equal_p (SET_SRC (set), x))
789 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
794 /* If this insn is setting a MEM from a register equivalent to it,
795 this is the equivalencing insn. */
796 else if (set && GET_CODE (SET_DEST (set)) == MEM
797 && GET_CODE (SET_SRC (set)) == REG
798 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
799 && rtx_equal_p (SET_DEST (set),
800 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
801 reg_equiv_init[REGNO (SET_SRC (set))]
802 = gen_rtx_INSN_LIST (VOIDmode, insn,
803 reg_equiv_init[REGNO (SET_SRC (set))]);
806 scan_paradoxical_subregs (PATTERN (insn));
811 first_label_num = get_first_label_num ();
812 num_labels = max_label_num () - first_label_num;
814 /* Allocate the tables used to store offset information at labels. */
815 /* We used to use alloca here, but the size of what it would try to
816 allocate would occasionally cause it to exceed the stack limit and
817 cause a core dump. */
818 offsets_known_at = xmalloc (num_labels);
819 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
821 /* Alter each pseudo-reg rtx to contain its hard reg number.
822 Assign stack slots to the pseudos that lack hard regs or equivalents.
823 Do not touch virtual registers. */
825 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
828 /* If we have some registers we think can be eliminated, scan all insns to
829 see if there is an insn that sets one of these registers to something
830 other than itself plus a constant. If so, the register cannot be
831 eliminated. Doing this scan here eliminates an extra pass through the
832 main reload loop in the most common case where register elimination
834 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
835 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
836 || GET_CODE (insn) == CALL_INSN)
837 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
839 maybe_fix_stack_asms ();
841 insns_need_reload = 0;
842 something_needs_elimination = 0;
844 /* Initialize to -1, which means take the first spill register. */
847 /* Spill any hard regs that we know we can't eliminate. */
848 CLEAR_HARD_REG_SET (used_spill_regs);
849 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
850 if (! ep->can_eliminate)
851 spill_hard_reg (ep->from, 1);
853 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
854 if (frame_pointer_needed)
855 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
857 finish_spills (global);
859 /* From now on, we may need to generate moves differently. We may also
860 allow modifications of insns which cause them to not be recognized.
861 Any such modifications will be cleaned up during reload itself. */
862 reload_in_progress = 1;
864 /* This loop scans the entire function each go-round
865 and repeats until one repetition spills no additional hard regs. */
868 int something_changed;
871 HOST_WIDE_INT starting_frame_size;
873 /* Round size of stack frame to stack_alignment_needed. This must be done
874 here because the stack size may be a part of the offset computation
875 for register elimination, and there might have been new stack slots
876 created in the last iteration of this loop. */
877 if (cfun->stack_alignment_needed)
878 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
880 starting_frame_size = get_frame_size ();
882 set_initial_elim_offsets ();
883 set_initial_label_offsets ();
885 /* For each pseudo register that has an equivalent location defined,
886 try to eliminate any eliminable registers (such as the frame pointer)
887 assuming initial offsets for the replacement register, which
890 If the resulting location is directly addressable, substitute
891 the MEM we just got directly for the old REG.
893 If it is not addressable but is a constant or the sum of a hard reg
894 and constant, it is probably not addressable because the constant is
895 out of range, in that case record the address; we will generate
896 hairy code to compute the address in a register each time it is
897 needed. Similarly if it is a hard register, but one that is not
898 valid as an address register.
900 If the location is not addressable, but does not have one of the
901 above forms, assign a stack slot. We have to do this to avoid the
902 potential of producing lots of reloads if, e.g., a location involves
903 a pseudo that didn't get a hard register and has an equivalent memory
904 location that also involves a pseudo that didn't get a hard register.
906 Perhaps at some point we will improve reload_when_needed handling
907 so this problem goes away. But that's very hairy. */
909 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
910 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
912 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
913 enum reg_class class = MODE_BASE_REG_CLASS (GET_MODE (x));
915 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
917 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
918 else if ((CONSTANT_P (XEXP (x, 0))
919 && LEGITIMATE_CONSTANT_P (XEXP (x, 0))
920 && PREFERRED_RELOAD_CLASS (XEXP (x, 0), class) != NO_REGS)
921 || (GET_CODE (XEXP (x, 0)) == REG
922 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
923 || (GET_CODE (XEXP (x, 0)) == PLUS
924 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
925 && (REGNO (XEXP (XEXP (x, 0), 0))
926 < FIRST_PSEUDO_REGISTER)
927 && (CONSTANT_P (XEXP (XEXP (x, 0), 1))
928 && LEGITIMATE_CONSTANT_P (XEXP (XEXP (x, 0), 1))
929 && PREFERRED_RELOAD_CLASS (XEXP (XEXP (x, 0), 1), class)
931 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
934 /* Make a new stack slot. Then indicate that something
935 changed so we go back and recompute offsets for
936 eliminable registers because the allocation of memory
937 below might change some offset. reg_equiv_{mem,address}
938 will be set up for this pseudo on the next pass around
940 reg_equiv_memory_loc[i] = 0;
941 reg_equiv_init[i] = 0;
946 if (caller_save_needed)
949 /* If we allocated another stack slot, redo elimination bookkeeping. */
950 if (starting_frame_size != get_frame_size ())
953 if (caller_save_needed)
955 save_call_clobbered_regs ();
956 /* That might have allocated new insn_chain structures. */
957 reload_firstobj = obstack_alloc (&reload_obstack, 0);
960 calculate_needs_all_insns (global);
962 CLEAR_REG_SET (&spilled_pseudos);
965 something_changed = 0;
967 /* If we allocated any new memory locations, make another pass
968 since it might have changed elimination offsets. */
969 if (starting_frame_size != get_frame_size ())
970 something_changed = 1;
973 HARD_REG_SET to_spill;
974 CLEAR_HARD_REG_SET (to_spill);
975 update_eliminables (&to_spill);
976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
977 if (TEST_HARD_REG_BIT (to_spill, i))
979 spill_hard_reg (i, 1);
982 /* Regardless of the state of spills, if we previously had
983 a register that we thought we could eliminate, but now can
984 not eliminate, we must run another pass.
986 Consider pseudos which have an entry in reg_equiv_* which
987 reference an eliminable register. We must make another pass
988 to update reg_equiv_* so that we do not substitute in the
989 old value from when we thought the elimination could be
991 something_changed = 1;
995 select_reload_regs ();
999 if (insns_need_reload != 0 || did_spill)
1000 something_changed |= finish_spills (global);
1002 if (! something_changed)
1005 if (caller_save_needed)
1006 delete_caller_save_insns ();
1008 obstack_free (&reload_obstack, reload_firstobj);
1011 /* If global-alloc was run, notify it of any register eliminations we have
1014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1015 if (ep->can_eliminate)
1016 mark_elimination (ep->from, ep->to);
1018 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1019 If that insn didn't set the register (i.e., it copied the register to
1020 memory), just delete that insn instead of the equivalencing insn plus
1021 anything now dead. If we call delete_dead_insn on that insn, we may
1022 delete the insn that actually sets the register if the register dies
1023 there and that is incorrect. */
1025 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1027 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1030 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1032 rtx equiv_insn = XEXP (list, 0);
1034 /* If we already deleted the insn or if it may trap, we can't
1035 delete it. The latter case shouldn't happen, but can
1036 if an insn has a variable address, gets a REG_EH_REGION
1037 note added to it, and then gets converted into an load
1038 from a constant address. */
1039 if (GET_CODE (equiv_insn) == NOTE
1040 || can_throw_internal (equiv_insn))
1042 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1043 delete_dead_insn (equiv_insn);
1046 PUT_CODE (equiv_insn, NOTE);
1047 NOTE_SOURCE_FILE (equiv_insn) = 0;
1048 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1054 /* Use the reload registers where necessary
1055 by generating move instructions to move the must-be-register
1056 values into or out of the reload registers. */
1058 if (insns_need_reload != 0 || something_needs_elimination
1059 || something_needs_operands_changed)
1061 HOST_WIDE_INT old_frame_size = get_frame_size ();
1063 reload_as_needed (global);
1065 if (old_frame_size != get_frame_size ())
1069 verify_initial_elim_offsets ();
1072 /* If we were able to eliminate the frame pointer, show that it is no
1073 longer live at the start of any basic block. If it ls live by
1074 virtue of being in a pseudo, that pseudo will be marked live
1075 and hence the frame pointer will be known to be live via that
1078 if (! frame_pointer_needed)
1080 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1081 HARD_FRAME_POINTER_REGNUM);
1083 /* Come here (with failure set nonzero) if we can't get enough spill regs
1084 and we decide not to abort about it. */
1087 CLEAR_REG_SET (&spilled_pseudos);
1088 reload_in_progress = 0;
1090 /* Now eliminate all pseudo regs by modifying them into
1091 their equivalent memory references.
1092 The REG-rtx's for the pseudos are modified in place,
1093 so all insns that used to refer to them now refer to memory.
1095 For a reg that has a reg_equiv_address, all those insns
1096 were changed by reloading so that no insns refer to it any longer;
1097 but the DECL_RTL of a variable decl may refer to it,
1098 and if so this causes the debugging info to mention the variable. */
1100 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1104 if (reg_equiv_mem[i])
1105 addr = XEXP (reg_equiv_mem[i], 0);
1107 if (reg_equiv_address[i])
1108 addr = reg_equiv_address[i];
1112 if (reg_renumber[i] < 0)
1114 rtx reg = regno_reg_rtx[i];
1116 REG_USERVAR_P (reg) = 0;
1117 PUT_CODE (reg, MEM);
1118 XEXP (reg, 0) = addr;
1119 if (reg_equiv_memory_loc[i])
1120 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1123 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1124 = MEM_SCALAR_P (reg) = 0;
1125 MEM_ATTRS (reg) = 0;
1128 else if (reg_equiv_mem[i])
1129 XEXP (reg_equiv_mem[i], 0) = addr;
1133 /* We must set reload_completed now since the cleanup_subreg_operands call
1134 below will re-recognize each insn and reload may have generated insns
1135 which are only valid during and after reload. */
1136 reload_completed = 1;
1138 /* Make a pass over all the insns and delete all USEs which we inserted
1139 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1140 notes. Delete all CLOBBER insns, except those that refer to the return
1141 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1142 from misarranging variable-array code, and simplify (subreg (reg))
1143 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1144 are no longer useful or accurate. Strip and regenerate REG_INC notes
1145 that may have been moved around. */
1147 for (insn = first; insn; insn = NEXT_INSN (insn))
1152 if (GET_CODE (insn) == CALL_INSN)
1153 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1154 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1156 if ((GET_CODE (PATTERN (insn)) == USE
1157 /* We mark with QImode USEs introduced by reload itself. */
1158 && (GET_MODE (insn) == QImode
1159 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1160 || (GET_CODE (PATTERN (insn)) == CLOBBER
1161 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1162 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1163 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1164 && XEXP (XEXP (PATTERN (insn), 0), 0)
1165 != stack_pointer_rtx))
1166 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1167 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1173 /* Some CLOBBERs may survive until here and still reference unassigned
1174 pseudos with const equivalent, which may in turn cause ICE in later
1175 passes if the reference remains in place. */
1176 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1177 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1178 VOIDmode, PATTERN (insn));
1180 pnote = ®_NOTES (insn);
1183 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1184 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1185 || REG_NOTE_KIND (*pnote) == REG_INC
1186 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1187 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1188 *pnote = XEXP (*pnote, 1);
1190 pnote = &XEXP (*pnote, 1);
1194 add_auto_inc_notes (insn, PATTERN (insn));
1197 /* And simplify (subreg (reg)) if it appears as an operand. */
1198 cleanup_subreg_operands (insn);
1201 /* If we are doing stack checking, give a warning if this function's
1202 frame size is larger than we expect. */
1203 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1205 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1206 static int verbose_warned = 0;
1208 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1209 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1210 size += UNITS_PER_WORD;
1212 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1214 warning ("frame size too large for reliable stack checking");
1215 if (! verbose_warned)
1217 warning ("try reducing the number of local variables");
1223 /* Indicate that we no longer have known memory locations or constants. */
1224 if (reg_equiv_constant)
1225 free (reg_equiv_constant);
1226 reg_equiv_constant = 0;
1227 if (reg_equiv_memory_loc)
1228 free (reg_equiv_memory_loc);
1229 reg_equiv_memory_loc = 0;
1231 if (offsets_known_at)
1232 free (offsets_known_at);
1236 free (reg_equiv_mem);
1237 free (reg_equiv_init);
1238 free (reg_equiv_address);
1239 free (reg_max_ref_width);
1240 free (reg_old_renumber);
1241 free (pseudo_previous_regs);
1242 free (pseudo_forbidden_regs);
1244 CLEAR_HARD_REG_SET (used_spill_regs);
1245 for (i = 0; i < n_spills; i++)
1246 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1248 /* Free all the insn_chain structures at once. */
1249 obstack_free (&reload_obstack, reload_startobj);
1250 unused_insn_chains = 0;
1251 fixup_abnormal_edges ();
1253 /* Replacing pseudos with their memory equivalents might have
1254 created shared rtx. Subsequent passes would get confused
1255 by this, so unshare everything here. */
1256 unshare_all_rtl_again (first);
1261 /* Yet another special case. Unfortunately, reg-stack forces people to
1262 write incorrect clobbers in asm statements. These clobbers must not
1263 cause the register to appear in bad_spill_regs, otherwise we'll call
1264 fatal_insn later. We clear the corresponding regnos in the live
1265 register sets to avoid this.
1266 The whole thing is rather sick, I'm afraid. */
1269 maybe_fix_stack_asms (void)
1272 const char *constraints[MAX_RECOG_OPERANDS];
1273 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1274 struct insn_chain *chain;
1276 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1279 HARD_REG_SET clobbered, allowed;
1282 if (! INSN_P (chain->insn)
1283 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1285 pat = PATTERN (chain->insn);
1286 if (GET_CODE (pat) != PARALLEL)
1289 CLEAR_HARD_REG_SET (clobbered);
1290 CLEAR_HARD_REG_SET (allowed);
1292 /* First, make a mask of all stack regs that are clobbered. */
1293 for (i = 0; i < XVECLEN (pat, 0); i++)
1295 rtx t = XVECEXP (pat, 0, i);
1296 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1297 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1300 /* Get the operand values and constraints out of the insn. */
1301 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1302 constraints, operand_mode);
1304 /* For every operand, see what registers are allowed. */
1305 for (i = 0; i < noperands; i++)
1307 const char *p = constraints[i];
1308 /* For every alternative, we compute the class of registers allowed
1309 for reloading in CLS, and merge its contents into the reg set
1311 int cls = (int) NO_REGS;
1317 if (c == '\0' || c == ',' || c == '#')
1319 /* End of one alternative - mark the regs in the current
1320 class, and reset the class. */
1321 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1327 } while (c != '\0' && c != ',');
1335 case '=': case '+': case '*': case '%': case '?': case '!':
1336 case '0': case '1': case '2': case '3': case '4': case 'm':
1337 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1338 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1339 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1344 cls = (int) reg_class_subunion[cls]
1345 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1350 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1354 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1355 cls = (int) reg_class_subunion[cls]
1356 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1358 cls = (int) reg_class_subunion[cls]
1359 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1361 p += CONSTRAINT_LEN (c, p);
1364 /* Those of the registers which are clobbered, but allowed by the
1365 constraints, must be usable as reload registers. So clear them
1366 out of the life information. */
1367 AND_HARD_REG_SET (allowed, clobbered);
1368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1369 if (TEST_HARD_REG_BIT (allowed, i))
1371 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1372 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1379 /* Copy the global variables n_reloads and rld into the corresponding elts
1382 copy_reloads (struct insn_chain *chain)
1384 chain->n_reloads = n_reloads;
1385 chain->rld = obstack_alloc (&reload_obstack,
1386 n_reloads * sizeof (struct reload));
1387 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1388 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1391 /* Walk the chain of insns, and determine for each whether it needs reloads
1392 and/or eliminations. Build the corresponding insns_need_reload list, and
1393 set something_needs_elimination as appropriate. */
1395 calculate_needs_all_insns (int global)
1397 struct insn_chain **pprev_reload = &insns_need_reload;
1398 struct insn_chain *chain, *next = 0;
1400 something_needs_elimination = 0;
1402 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1403 for (chain = reload_insn_chain; chain != 0; chain = next)
1405 rtx insn = chain->insn;
1409 /* Clear out the shortcuts. */
1410 chain->n_reloads = 0;
1411 chain->need_elim = 0;
1412 chain->need_reload = 0;
1413 chain->need_operand_change = 0;
1415 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1416 include REG_LABEL), we need to see what effects this has on the
1417 known offsets at labels. */
1419 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1420 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1421 set_label_offsets (insn, insn, 0);
1425 rtx old_body = PATTERN (insn);
1426 int old_code = INSN_CODE (insn);
1427 rtx old_notes = REG_NOTES (insn);
1428 int did_elimination = 0;
1429 int operands_changed = 0;
1430 rtx set = single_set (insn);
1432 /* Skip insns that only set an equivalence. */
1433 if (set && GET_CODE (SET_DEST (set)) == REG
1434 && reg_renumber[REGNO (SET_DEST (set))] < 0
1435 && reg_equiv_constant[REGNO (SET_DEST (set))])
1438 /* If needed, eliminate any eliminable registers. */
1439 if (num_eliminable || num_eliminable_invariants)
1440 did_elimination = eliminate_regs_in_insn (insn, 0);
1442 /* Analyze the instruction. */
1443 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1444 global, spill_reg_order);
1446 /* If a no-op set needs more than one reload, this is likely
1447 to be something that needs input address reloads. We
1448 can't get rid of this cleanly later, and it is of no use
1449 anyway, so discard it now.
1450 We only do this when expensive_optimizations is enabled,
1451 since this complements reload inheritance / output
1452 reload deletion, and it can make debugging harder. */
1453 if (flag_expensive_optimizations && n_reloads > 1)
1455 rtx set = single_set (insn);
1457 && SET_SRC (set) == SET_DEST (set)
1458 && GET_CODE (SET_SRC (set)) == REG
1459 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1462 /* Delete it from the reload chain. */
1464 chain->prev->next = next;
1466 reload_insn_chain = next;
1468 next->prev = chain->prev;
1469 chain->next = unused_insn_chains;
1470 unused_insn_chains = chain;
1475 update_eliminable_offsets ();
1477 /* Remember for later shortcuts which insns had any reloads or
1478 register eliminations. */
1479 chain->need_elim = did_elimination;
1480 chain->need_reload = n_reloads > 0;
1481 chain->need_operand_change = operands_changed;
1483 /* Discard any register replacements done. */
1484 if (did_elimination)
1486 obstack_free (&reload_obstack, reload_insn_firstobj);
1487 PATTERN (insn) = old_body;
1488 INSN_CODE (insn) = old_code;
1489 REG_NOTES (insn) = old_notes;
1490 something_needs_elimination = 1;
1493 something_needs_operands_changed |= operands_changed;
1497 copy_reloads (chain);
1498 *pprev_reload = chain;
1499 pprev_reload = &chain->next_need_reload;
1506 /* Comparison function for qsort to decide which of two reloads
1507 should be handled first. *P1 and *P2 are the reload numbers. */
1510 reload_reg_class_lower (const void *r1p, const void *r2p)
1512 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1515 /* Consider required reloads before optional ones. */
1516 t = rld[r1].optional - rld[r2].optional;
1520 /* Count all solitary classes before non-solitary ones. */
1521 t = ((reg_class_size[(int) rld[r2].class] == 1)
1522 - (reg_class_size[(int) rld[r1].class] == 1));
1526 /* Aside from solitaires, consider all multi-reg groups first. */
1527 t = rld[r2].nregs - rld[r1].nregs;
1531 /* Consider reloads in order of increasing reg-class number. */
1532 t = (int) rld[r1].class - (int) rld[r2].class;
1536 /* If reloads are equally urgent, sort by reload number,
1537 so that the results of qsort leave nothing to chance. */
1541 /* The cost of spilling each hard reg. */
1542 static int spill_cost[FIRST_PSEUDO_REGISTER];
1544 /* When spilling multiple hard registers, we use SPILL_COST for the first
1545 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1546 only the first hard reg for a multi-reg pseudo. */
1547 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1549 /* Update the spill cost arrays, considering that pseudo REG is live. */
1552 count_pseudo (int reg)
1554 int freq = REG_FREQ (reg);
1555 int r = reg_renumber[reg];
1558 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1559 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1562 SET_REGNO_REG_SET (&pseudos_counted, reg);
1567 spill_add_cost[r] += freq;
1569 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1571 spill_cost[r + nregs] += freq;
1574 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1575 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1578 order_regs_for_reload (struct insn_chain *chain)
1581 HARD_REG_SET used_by_pseudos;
1582 HARD_REG_SET used_by_pseudos2;
1584 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1586 memset (spill_cost, 0, sizeof spill_cost);
1587 memset (spill_add_cost, 0, sizeof spill_add_cost);
1589 /* Count number of uses of each hard reg by pseudo regs allocated to it
1590 and then order them by decreasing use. First exclude hard registers
1591 that are live in or across this insn. */
1593 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1594 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1595 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1596 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1598 /* Now find out which pseudos are allocated to it, and update
1600 CLEAR_REG_SET (&pseudos_counted);
1602 EXECUTE_IF_SET_IN_REG_SET
1603 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1607 EXECUTE_IF_SET_IN_REG_SET
1608 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1612 CLEAR_REG_SET (&pseudos_counted);
1615 /* Vector of reload-numbers showing the order in which the reloads should
1617 static short reload_order[MAX_RELOADS];
1619 /* This is used to keep track of the spill regs used in one insn. */
1620 static HARD_REG_SET used_spill_regs_local;
1622 /* We decided to spill hard register SPILLED, which has a size of
1623 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1624 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1625 update SPILL_COST/SPILL_ADD_COST. */
1628 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1630 int r = reg_renumber[reg];
1631 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1633 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1634 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1637 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1639 spill_add_cost[r] -= REG_FREQ (reg);
1641 spill_cost[r + nregs] -= REG_FREQ (reg);
1644 /* Find reload register to use for reload number ORDER. */
1647 find_reg (struct insn_chain *chain, int order)
1649 int rnum = reload_order[order];
1650 struct reload *rl = rld + rnum;
1651 int best_cost = INT_MAX;
1655 HARD_REG_SET not_usable;
1656 HARD_REG_SET used_by_other_reload;
1658 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1659 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1660 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1662 CLEAR_HARD_REG_SET (used_by_other_reload);
1663 for (k = 0; k < order; k++)
1665 int other = reload_order[k];
1667 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1668 for (j = 0; j < rld[other].nregs; j++)
1669 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1672 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1674 unsigned int regno = i;
1676 if (! TEST_HARD_REG_BIT (not_usable, regno)
1677 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1678 && HARD_REGNO_MODE_OK (regno, rl->mode))
1680 int this_cost = spill_cost[regno];
1682 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1684 for (j = 1; j < this_nregs; j++)
1686 this_cost += spill_add_cost[regno + j];
1687 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1688 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1693 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1695 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1697 if (this_cost < best_cost
1698 /* Among registers with equal cost, prefer caller-saved ones, or
1699 use REG_ALLOC_ORDER if it is defined. */
1700 || (this_cost == best_cost
1701 #ifdef REG_ALLOC_ORDER
1702 && (inv_reg_alloc_order[regno]
1703 < inv_reg_alloc_order[best_reg])
1705 && call_used_regs[regno]
1706 && ! call_used_regs[best_reg]
1711 best_cost = this_cost;
1719 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1721 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1722 rl->regno = best_reg;
1724 EXECUTE_IF_SET_IN_REG_SET
1725 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1727 count_spilled_pseudo (best_reg, rl->nregs, j);
1730 EXECUTE_IF_SET_IN_REG_SET
1731 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1733 count_spilled_pseudo (best_reg, rl->nregs, j);
1736 for (i = 0; i < rl->nregs; i++)
1738 if (spill_cost[best_reg + i] != 0
1739 || spill_add_cost[best_reg + i] != 0)
1741 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1746 /* Find more reload regs to satisfy the remaining need of an insn, which
1748 Do it by ascending class number, since otherwise a reg
1749 might be spilled for a big class and might fail to count
1750 for a smaller class even though it belongs to that class. */
1753 find_reload_regs (struct insn_chain *chain)
1757 /* In order to be certain of getting the registers we need,
1758 we must sort the reloads into order of increasing register class.
1759 Then our grabbing of reload registers will parallel the process
1760 that provided the reload registers. */
1761 for (i = 0; i < chain->n_reloads; i++)
1763 /* Show whether this reload already has a hard reg. */
1764 if (chain->rld[i].reg_rtx)
1766 int regno = REGNO (chain->rld[i].reg_rtx);
1767 chain->rld[i].regno = regno;
1769 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1772 chain->rld[i].regno = -1;
1773 reload_order[i] = i;
1776 n_reloads = chain->n_reloads;
1777 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1779 CLEAR_HARD_REG_SET (used_spill_regs_local);
1782 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1784 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1786 /* Compute the order of preference for hard registers to spill. */
1788 order_regs_for_reload (chain);
1790 for (i = 0; i < n_reloads; i++)
1792 int r = reload_order[i];
1794 /* Ignore reloads that got marked inoperative. */
1795 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1796 && ! rld[r].optional
1797 && rld[r].regno == -1)
1798 if (! find_reg (chain, i))
1800 spill_failure (chain->insn, rld[r].class);
1806 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1807 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1809 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1813 select_reload_regs (void)
1815 struct insn_chain *chain;
1817 /* Try to satisfy the needs for each insn. */
1818 for (chain = insns_need_reload; chain != 0;
1819 chain = chain->next_need_reload)
1820 find_reload_regs (chain);
1823 /* Delete all insns that were inserted by emit_caller_save_insns during
1826 delete_caller_save_insns (void)
1828 struct insn_chain *c = reload_insn_chain;
1832 while (c != 0 && c->is_caller_save_insn)
1834 struct insn_chain *next = c->next;
1837 if (c == reload_insn_chain)
1838 reload_insn_chain = next;
1842 next->prev = c->prev;
1844 c->prev->next = next;
1845 c->next = unused_insn_chains;
1846 unused_insn_chains = c;
1854 /* Handle the failure to find a register to spill.
1855 INSN should be one of the insns which needed this particular spill reg. */
1858 spill_failure (rtx insn, enum reg_class class)
1860 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1861 if (asm_noperands (PATTERN (insn)) >= 0)
1862 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1863 reg_class_names[class]);
1866 error ("unable to find a register to spill in class `%s'",
1867 reg_class_names[class]);
1868 fatal_insn ("this is the insn:", insn);
1872 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1873 data that is dead in INSN. */
1876 delete_dead_insn (rtx insn)
1878 rtx prev = prev_real_insn (insn);
1881 /* If the previous insn sets a register that dies in our insn, delete it
1883 if (prev && GET_CODE (PATTERN (prev)) == SET
1884 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1885 && reg_mentioned_p (prev_dest, PATTERN (insn))
1886 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1887 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1888 delete_dead_insn (prev);
1890 PUT_CODE (insn, NOTE);
1891 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1892 NOTE_SOURCE_FILE (insn) = 0;
1895 /* Modify the home of pseudo-reg I.
1896 The new home is present in reg_renumber[I].
1898 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1899 or it may be -1, meaning there is none or it is not relevant.
1900 This is used so that all pseudos spilled from a given hard reg
1901 can share one stack slot. */
1904 alter_reg (int i, int from_reg)
1906 /* When outputting an inline function, this can happen
1907 for a reg that isn't actually used. */
1908 if (regno_reg_rtx[i] == 0)
1911 /* If the reg got changed to a MEM at rtl-generation time,
1913 if (GET_CODE (regno_reg_rtx[i]) != REG)
1916 /* Modify the reg-rtx to contain the new hard reg
1917 number or else to contain its pseudo reg number. */
1918 REGNO (regno_reg_rtx[i])
1919 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1921 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1922 allocate a stack slot for it. */
1924 if (reg_renumber[i] < 0
1925 && REG_N_REFS (i) > 0
1926 && reg_equiv_constant[i] == 0
1927 && reg_equiv_memory_loc[i] == 0)
1930 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1931 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1934 /* Each pseudo reg has an inherent size which comes from its own mode,
1935 and a total size which provides room for paradoxical subregs
1936 which refer to the pseudo reg in wider modes.
1938 We can use a slot already allocated if it provides both
1939 enough inherent space and enough total space.
1940 Otherwise, we allocate a new slot, making sure that it has no less
1941 inherent space, and no less total space, then the previous slot. */
1944 /* No known place to spill from => no slot to reuse. */
1945 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1946 inherent_size == total_size ? 0 : -1);
1947 if (BYTES_BIG_ENDIAN)
1948 /* Cancel the big-endian correction done in assign_stack_local.
1949 Get the address of the beginning of the slot.
1950 This is so we can do a big-endian correction unconditionally
1952 adjust = inherent_size - total_size;
1954 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1956 /* Nothing can alias this slot except this pseudo. */
1957 set_mem_alias_set (x, new_alias_set ());
1960 /* Reuse a stack slot if possible. */
1961 else if (spill_stack_slot[from_reg] != 0
1962 && spill_stack_slot_width[from_reg] >= total_size
1963 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1965 x = spill_stack_slot[from_reg];
1967 /* Allocate a bigger slot. */
1970 /* Compute maximum size needed, both for inherent size
1971 and for total size. */
1972 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1975 if (spill_stack_slot[from_reg])
1977 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1979 mode = GET_MODE (spill_stack_slot[from_reg]);
1980 if (spill_stack_slot_width[from_reg] > total_size)
1981 total_size = spill_stack_slot_width[from_reg];
1984 /* Make a slot with that size. */
1985 x = assign_stack_local (mode, total_size,
1986 inherent_size == total_size ? 0 : -1);
1989 /* All pseudos mapped to this slot can alias each other. */
1990 if (spill_stack_slot[from_reg])
1991 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1993 set_mem_alias_set (x, new_alias_set ());
1995 if (BYTES_BIG_ENDIAN)
1997 /* Cancel the big-endian correction done in assign_stack_local.
1998 Get the address of the beginning of the slot.
1999 This is so we can do a big-endian correction unconditionally
2001 adjust = GET_MODE_SIZE (mode) - total_size;
2004 = adjust_address_nv (x, mode_for_size (total_size
2010 spill_stack_slot[from_reg] = stack_slot;
2011 spill_stack_slot_width[from_reg] = total_size;
2014 /* On a big endian machine, the "address" of the slot
2015 is the address of the low part that fits its inherent mode. */
2016 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2017 adjust += (total_size - inherent_size);
2019 /* If we have any adjustment to make, or if the stack slot is the
2020 wrong mode, make a new stack slot. */
2021 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2023 /* If we have a decl for the original register, set it for the
2024 memory. If this is a shared MEM, make a copy. */
2025 if (REG_EXPR (regno_reg_rtx[i])
2026 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2028 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2030 /* We can do this only for the DECLs home pseudo, not for
2031 any copies of it, since otherwise when the stack slot
2032 is reused, nonoverlapping_memrefs_p might think they
2034 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2036 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2039 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2043 /* Save the stack slot for later. */
2044 reg_equiv_memory_loc[i] = x;
2048 /* Mark the slots in regs_ever_live for the hard regs
2049 used by pseudo-reg number REGNO. */
2052 mark_home_live (int regno)
2056 i = reg_renumber[regno];
2059 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2061 regs_ever_live[i++] = 1;
2064 /* This function handles the tracking of elimination offsets around branches.
2066 X is a piece of RTL being scanned.
2068 INSN is the insn that it came from, if any.
2070 INITIAL_P is nonzero if we are to set the offset to be the initial
2071 offset and zero if we are setting the offset of the label to be the
2075 set_label_offsets (rtx x, rtx insn, int initial_p)
2077 enum rtx_code code = GET_CODE (x);
2080 struct elim_table *p;
2085 if (LABEL_REF_NONLOCAL_P (x))
2090 /* ... fall through ... */
2093 /* If we know nothing about this label, set the desired offsets. Note
2094 that this sets the offset at a label to be the offset before a label
2095 if we don't know anything about the label. This is not correct for
2096 the label after a BARRIER, but is the best guess we can make. If
2097 we guessed wrong, we will suppress an elimination that might have
2098 been possible had we been able to guess correctly. */
2100 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2102 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2103 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2104 = (initial_p ? reg_eliminate[i].initial_offset
2105 : reg_eliminate[i].offset);
2106 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2109 /* Otherwise, if this is the definition of a label and it is
2110 preceded by a BARRIER, set our offsets to the known offset of
2114 && (tem = prev_nonnote_insn (insn)) != 0
2115 && GET_CODE (tem) == BARRIER)
2116 set_offsets_for_label (insn);
2118 /* If neither of the above cases is true, compare each offset
2119 with those previously recorded and suppress any eliminations
2120 where the offsets disagree. */
2122 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2123 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2124 != (initial_p ? reg_eliminate[i].initial_offset
2125 : reg_eliminate[i].offset))
2126 reg_eliminate[i].can_eliminate = 0;
2131 set_label_offsets (PATTERN (insn), insn, initial_p);
2133 /* ... fall through ... */
2137 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2138 and hence must have all eliminations at their initial offsets. */
2139 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2140 if (REG_NOTE_KIND (tem) == REG_LABEL)
2141 set_label_offsets (XEXP (tem, 0), insn, 1);
2147 /* Each of the labels in the parallel or address vector must be
2148 at their initial offsets. We want the first field for PARALLEL
2149 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2151 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2152 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2157 /* We only care about setting PC. If the source is not RETURN,
2158 IF_THEN_ELSE, or a label, disable any eliminations not at
2159 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2160 isn't one of those possibilities. For branches to a label,
2161 call ourselves recursively.
2163 Note that this can disable elimination unnecessarily when we have
2164 a non-local goto since it will look like a non-constant jump to
2165 someplace in the current function. This isn't a significant
2166 problem since such jumps will normally be when all elimination
2167 pairs are back to their initial offsets. */
2169 if (SET_DEST (x) != pc_rtx)
2172 switch (GET_CODE (SET_SRC (x)))
2179 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2183 tem = XEXP (SET_SRC (x), 1);
2184 if (GET_CODE (tem) == LABEL_REF)
2185 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2186 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2189 tem = XEXP (SET_SRC (x), 2);
2190 if (GET_CODE (tem) == LABEL_REF)
2191 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2192 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2200 /* If we reach here, all eliminations must be at their initial
2201 offset because we are doing a jump to a variable address. */
2202 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2203 if (p->offset != p->initial_offset)
2204 p->can_eliminate = 0;
2212 /* Scan X and replace any eliminable registers (such as fp) with a
2213 replacement (such as sp), plus an offset.
2215 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2216 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2217 MEM, we are allowed to replace a sum of a register and the constant zero
2218 with the register, which we cannot do outside a MEM. In addition, we need
2219 to record the fact that a register is referenced outside a MEM.
2221 If INSN is an insn, it is the insn containing X. If we replace a REG
2222 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2223 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2224 the REG is being modified.
2226 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2227 That's used when we eliminate in expressions stored in notes.
2228 This means, do not set ref_outside_mem even if the reference
2231 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2232 replacements done assuming all offsets are at their initial values. If
2233 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2234 encounter, return the actual location so that find_reloads will do
2235 the proper thing. */
2238 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2240 enum rtx_code code = GET_CODE (x);
2241 struct elim_table *ep;
2248 if (! current_function_decl)
2268 /* This is only for the benefit of the debugging backends, which call
2269 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2270 removed after CSE. */
2271 new = eliminate_regs (XEXP (x, 0), 0, insn);
2272 if (GET_CODE (new) == MEM)
2273 return XEXP (new, 0);
2279 /* First handle the case where we encounter a bare register that
2280 is eliminable. Replace it with a PLUS. */
2281 if (regno < FIRST_PSEUDO_REGISTER)
2283 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2285 if (ep->from_rtx == x && ep->can_eliminate)
2286 return plus_constant (ep->to_rtx, ep->previous_offset);
2289 else if (reg_renumber && reg_renumber[regno] < 0
2290 && reg_equiv_constant && reg_equiv_constant[regno]
2291 && ! CONSTANT_P (reg_equiv_constant[regno]))
2292 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2296 /* You might think handling MINUS in a manner similar to PLUS is a
2297 good idea. It is not. It has been tried multiple times and every
2298 time the change has had to have been reverted.
2300 Other parts of reload know a PLUS is special (gen_reload for example)
2301 and require special code to handle code a reloaded PLUS operand.
2303 Also consider backends where the flags register is clobbered by a
2304 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2305 lea instruction comes to mind). If we try to reload a MINUS, we
2306 may kill the flags register that was holding a useful value.
2308 So, please before trying to handle MINUS, consider reload as a
2309 whole instead of this little section as well as the backend issues. */
2311 /* If this is the sum of an eliminable register and a constant, rework
2313 if (GET_CODE (XEXP (x, 0)) == REG
2314 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2315 && CONSTANT_P (XEXP (x, 1)))
2317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2319 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2321 /* The only time we want to replace a PLUS with a REG (this
2322 occurs when the constant operand of the PLUS is the negative
2323 of the offset) is when we are inside a MEM. We won't want
2324 to do so at other times because that would change the
2325 structure of the insn in a way that reload can't handle.
2326 We special-case the commonest situation in
2327 eliminate_regs_in_insn, so just replace a PLUS with a
2328 PLUS here, unless inside a MEM. */
2329 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2330 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2333 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2334 plus_constant (XEXP (x, 1),
2335 ep->previous_offset));
2338 /* If the register is not eliminable, we are done since the other
2339 operand is a constant. */
2343 /* If this is part of an address, we want to bring any constant to the
2344 outermost PLUS. We will do this by doing register replacement in
2345 our operands and seeing if a constant shows up in one of them.
2347 Note that there is no risk of modifying the structure of the insn,
2348 since we only get called for its operands, thus we are either
2349 modifying the address inside a MEM, or something like an address
2350 operand of a load-address insn. */
2353 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2354 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2356 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2358 /* If one side is a PLUS and the other side is a pseudo that
2359 didn't get a hard register but has a reg_equiv_constant,
2360 we must replace the constant here since it may no longer
2361 be in the position of any operand. */
2362 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2363 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2364 && reg_renumber[REGNO (new1)] < 0
2365 && reg_equiv_constant != 0
2366 && reg_equiv_constant[REGNO (new1)] != 0)
2367 new1 = reg_equiv_constant[REGNO (new1)];
2368 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2369 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2370 && reg_renumber[REGNO (new0)] < 0
2371 && reg_equiv_constant[REGNO (new0)] != 0)
2372 new0 = reg_equiv_constant[REGNO (new0)];
2374 new = form_sum (new0, new1);
2376 /* As above, if we are not inside a MEM we do not want to
2377 turn a PLUS into something else. We might try to do so here
2378 for an addition of 0 if we aren't optimizing. */
2379 if (! mem_mode && GET_CODE (new) != PLUS)
2380 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2388 /* If this is the product of an eliminable register and a
2389 constant, apply the distribute law and move the constant out
2390 so that we have (plus (mult ..) ..). This is needed in order
2391 to keep load-address insns valid. This case is pathological.
2392 We ignore the possibility of overflow here. */
2393 if (GET_CODE (XEXP (x, 0)) == REG
2394 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2395 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2396 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2398 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2401 /* Refs inside notes don't count for this purpose. */
2402 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2403 || GET_CODE (insn) == INSN_LIST)))
2404 ep->ref_outside_mem = 1;
2407 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2408 ep->previous_offset * INTVAL (XEXP (x, 1)));
2411 /* ... fall through ... */
2415 /* See comments before PLUS about handling MINUS. */
2417 case DIV: case UDIV:
2418 case MOD: case UMOD:
2419 case AND: case IOR: case XOR:
2420 case ROTATERT: case ROTATE:
2421 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2423 case GE: case GT: case GEU: case GTU:
2424 case LE: case LT: case LEU: case LTU:
2426 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2428 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2430 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2431 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2436 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2439 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2440 if (new != XEXP (x, 0))
2442 /* If this is a REG_DEAD note, it is not valid anymore.
2443 Using the eliminated version could result in creating a
2444 REG_DEAD note for the stack or frame pointer. */
2445 if (GET_MODE (x) == REG_DEAD)
2447 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2450 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2454 /* ... fall through ... */
2457 /* Now do eliminations in the rest of the chain. If this was
2458 an EXPR_LIST, this might result in allocating more memory than is
2459 strictly needed, but it simplifies the code. */
2462 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2463 if (new != XEXP (x, 1))
2465 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2473 case STRICT_LOW_PART:
2475 case SIGN_EXTEND: case ZERO_EXTEND:
2476 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2477 case FLOAT: case FIX:
2478 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2486 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2487 if (new != XEXP (x, 0))
2488 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2492 /* Similar to above processing, but preserve SUBREG_BYTE.
2493 Convert (subreg (mem)) to (mem) if not paradoxical.
2494 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2495 pseudo didn't get a hard reg, we must replace this with the
2496 eliminated version of the memory location because push_reload
2497 may do the replacement in certain circumstances. */
2498 if (GET_CODE (SUBREG_REG (x)) == REG
2499 && (GET_MODE_SIZE (GET_MODE (x))
2500 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2501 && reg_equiv_memory_loc != 0
2502 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2504 new = SUBREG_REG (x);
2507 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2509 if (new != SUBREG_REG (x))
2511 int x_size = GET_MODE_SIZE (GET_MODE (x));
2512 int new_size = GET_MODE_SIZE (GET_MODE (new));
2514 if (GET_CODE (new) == MEM
2515 && ((x_size < new_size
2516 #ifdef WORD_REGISTER_OPERATIONS
2517 /* On these machines, combine can create rtl of the form
2518 (set (subreg:m1 (reg:m2 R) 0) ...)
2519 where m1 < m2, and expects something interesting to
2520 happen to the entire word. Moreover, it will use the
2521 (reg:m2 R) later, expecting all bits to be preserved.
2522 So if the number of words is the same, preserve the
2523 subreg so that push_reload can see it. */
2524 && ! ((x_size - 1) / UNITS_PER_WORD
2525 == (new_size -1 ) / UNITS_PER_WORD)
2528 || x_size == new_size)
2530 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2532 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2538 /* This is only for the benefit of the debugging backends, which call
2539 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2540 removed after CSE. */
2541 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2542 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2544 /* Our only special processing is to pass the mode of the MEM to our
2545 recursive call and copy the flags. While we are here, handle this
2546 case more efficiently. */
2548 replace_equiv_address_nv (x,
2549 eliminate_regs (XEXP (x, 0),
2550 GET_MODE (x), insn));
2553 /* Handle insn_list USE that a call to a pure function may generate. */
2554 new = eliminate_regs (XEXP (x, 0), 0, insn);
2555 if (new != XEXP (x, 0))
2556 return gen_rtx_USE (GET_MODE (x), new);
2568 /* Process each of our operands recursively. If any have changed, make a
2570 fmt = GET_RTX_FORMAT (code);
2571 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2575 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2576 if (new != XEXP (x, i) && ! copied)
2578 rtx new_x = rtx_alloc (code);
2579 memcpy (new_x, x, RTX_SIZE (code));
2585 else if (*fmt == 'E')
2588 for (j = 0; j < XVECLEN (x, i); j++)
2590 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2591 if (new != XVECEXP (x, i, j) && ! copied_vec)
2593 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2597 rtx new_x = rtx_alloc (code);
2598 memcpy (new_x, x, RTX_SIZE (code));
2602 XVEC (x, i) = new_v;
2605 XVECEXP (x, i, j) = new;
2613 /* Scan rtx X for modifications of elimination target registers. Update
2614 the table of eliminables to reflect the changed state. MEM_MODE is
2615 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2618 elimination_effects (rtx x, enum machine_mode mem_mode)
2620 enum rtx_code code = GET_CODE (x);
2621 struct elim_table *ep;
2648 /* First handle the case where we encounter a bare register that
2649 is eliminable. Replace it with a PLUS. */
2650 if (regno < FIRST_PSEUDO_REGISTER)
2652 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2654 if (ep->from_rtx == x && ep->can_eliminate)
2657 ep->ref_outside_mem = 1;
2662 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2663 && reg_equiv_constant[regno]
2664 && ! function_invariant_p (reg_equiv_constant[regno]))
2665 elimination_effects (reg_equiv_constant[regno], mem_mode);
2674 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2675 if (ep->to_rtx == XEXP (x, 0))
2677 int size = GET_MODE_SIZE (mem_mode);
2679 /* If more bytes than MEM_MODE are pushed, account for them. */
2680 #ifdef PUSH_ROUNDING
2681 if (ep->to_rtx == stack_pointer_rtx)
2682 size = PUSH_ROUNDING (size);
2684 if (code == PRE_DEC || code == POST_DEC)
2686 else if (code == PRE_INC || code == POST_INC)
2688 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2689 && GET_CODE (XEXP (x, 1)) == PLUS
2690 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2691 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2692 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2695 /* These two aren't unary operators. */
2696 if (code == POST_MODIFY || code == PRE_MODIFY)
2699 /* Fall through to generic unary operation case. */
2700 case STRICT_LOW_PART:
2702 case SIGN_EXTEND: case ZERO_EXTEND:
2703 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2704 case FLOAT: case FIX:
2705 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2713 elimination_effects (XEXP (x, 0), mem_mode);
2717 if (GET_CODE (SUBREG_REG (x)) == REG
2718 && (GET_MODE_SIZE (GET_MODE (x))
2719 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2720 && reg_equiv_memory_loc != 0
2721 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2724 elimination_effects (SUBREG_REG (x), mem_mode);
2728 /* If using a register that is the source of an eliminate we still
2729 think can be performed, note it cannot be performed since we don't
2730 know how this register is used. */
2731 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2732 if (ep->from_rtx == XEXP (x, 0))
2733 ep->can_eliminate = 0;
2735 elimination_effects (XEXP (x, 0), mem_mode);
2739 /* If clobbering a register that is the replacement register for an
2740 elimination we still think can be performed, note that it cannot
2741 be performed. Otherwise, we need not be concerned about it. */
2742 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2743 if (ep->to_rtx == XEXP (x, 0))
2744 ep->can_eliminate = 0;
2746 elimination_effects (XEXP (x, 0), mem_mode);
2750 /* Check for setting a register that we know about. */
2751 if (GET_CODE (SET_DEST (x)) == REG)
2753 /* See if this is setting the replacement register for an
2756 If DEST is the hard frame pointer, we do nothing because we
2757 assume that all assignments to the frame pointer are for
2758 non-local gotos and are being done at a time when they are valid
2759 and do not disturb anything else. Some machines want to
2760 eliminate a fake argument pointer (or even a fake frame pointer)
2761 with either the real frame or the stack pointer. Assignments to
2762 the hard frame pointer must not prevent this elimination. */
2764 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2766 if (ep->to_rtx == SET_DEST (x)
2767 && SET_DEST (x) != hard_frame_pointer_rtx)
2769 /* If it is being incremented, adjust the offset. Otherwise,
2770 this elimination can't be done. */
2771 rtx src = SET_SRC (x);
2773 if (GET_CODE (src) == PLUS
2774 && XEXP (src, 0) == SET_DEST (x)
2775 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2776 ep->offset -= INTVAL (XEXP (src, 1));
2778 ep->can_eliminate = 0;
2782 elimination_effects (SET_DEST (x), 0);
2783 elimination_effects (SET_SRC (x), 0);
2787 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2790 /* Our only special processing is to pass the mode of the MEM to our
2792 elimination_effects (XEXP (x, 0), GET_MODE (x));
2799 fmt = GET_RTX_FORMAT (code);
2800 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2803 elimination_effects (XEXP (x, i), mem_mode);
2804 else if (*fmt == 'E')
2805 for (j = 0; j < XVECLEN (x, i); j++)
2806 elimination_effects (XVECEXP (x, i, j), mem_mode);
2810 /* Descend through rtx X and verify that no references to eliminable registers
2811 remain. If any do remain, mark the involved register as not
2815 check_eliminable_occurrences (rtx x)
2824 code = GET_CODE (x);
2826 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2828 struct elim_table *ep;
2830 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2831 if (ep->from_rtx == x && ep->can_eliminate)
2832 ep->can_eliminate = 0;
2836 fmt = GET_RTX_FORMAT (code);
2837 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2840 check_eliminable_occurrences (XEXP (x, i));
2841 else if (*fmt == 'E')
2844 for (j = 0; j < XVECLEN (x, i); j++)
2845 check_eliminable_occurrences (XVECEXP (x, i, j));
2850 /* Scan INSN and eliminate all eliminable registers in it.
2852 If REPLACE is nonzero, do the replacement destructively. Also
2853 delete the insn as dead it if it is setting an eliminable register.
2855 If REPLACE is zero, do all our allocations in reload_obstack.
2857 If no eliminations were done and this insn doesn't require any elimination
2858 processing (these are not identical conditions: it might be updating sp,
2859 but not referencing fp; this needs to be seen during reload_as_needed so
2860 that the offset between fp and sp can be taken into consideration), zero
2861 is returned. Otherwise, 1 is returned. */
2864 eliminate_regs_in_insn (rtx insn, int replace)
2866 int icode = recog_memoized (insn);
2867 rtx old_body = PATTERN (insn);
2868 int insn_is_asm = asm_noperands (old_body) >= 0;
2869 rtx old_set = single_set (insn);
2873 rtx substed_operand[MAX_RECOG_OPERANDS];
2874 rtx orig_operand[MAX_RECOG_OPERANDS];
2875 struct elim_table *ep;
2877 if (! insn_is_asm && icode < 0)
2879 if (GET_CODE (PATTERN (insn)) == USE
2880 || GET_CODE (PATTERN (insn)) == CLOBBER
2881 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2882 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2883 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2888 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2889 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2891 /* Check for setting an eliminable register. */
2892 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2893 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2895 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2896 /* If this is setting the frame pointer register to the
2897 hardware frame pointer register and this is an elimination
2898 that will be done (tested above), this insn is really
2899 adjusting the frame pointer downward to compensate for
2900 the adjustment done before a nonlocal goto. */
2901 if (ep->from == FRAME_POINTER_REGNUM
2902 && ep->to == HARD_FRAME_POINTER_REGNUM)
2904 rtx base = SET_SRC (old_set);
2905 rtx base_insn = insn;
2906 HOST_WIDE_INT offset = 0;
2908 while (base != ep->to_rtx)
2910 rtx prev_insn, prev_set;
2912 if (GET_CODE (base) == PLUS
2913 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2915 offset += INTVAL (XEXP (base, 1));
2916 base = XEXP (base, 0);
2918 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2919 && (prev_set = single_set (prev_insn)) != 0
2920 && rtx_equal_p (SET_DEST (prev_set), base))
2922 base = SET_SRC (prev_set);
2923 base_insn = prev_insn;
2929 if (base == ep->to_rtx)
2932 = plus_constant (ep->to_rtx, offset - ep->offset);
2934 new_body = old_body;
2937 new_body = copy_insn (old_body);
2938 if (REG_NOTES (insn))
2939 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2941 PATTERN (insn) = new_body;
2942 old_set = single_set (insn);
2944 /* First see if this insn remains valid when we
2945 make the change. If not, keep the INSN_CODE
2946 the same and let reload fit it up. */
2947 validate_change (insn, &SET_SRC (old_set), src, 1);
2948 validate_change (insn, &SET_DEST (old_set),
2950 if (! apply_change_group ())
2952 SET_SRC (old_set) = src;
2953 SET_DEST (old_set) = ep->to_rtx;
2962 /* In this case this insn isn't serving a useful purpose. We
2963 will delete it in reload_as_needed once we know that this
2964 elimination is, in fact, being done.
2966 If REPLACE isn't set, we can't delete this insn, but needn't
2967 process it since it won't be used unless something changes. */
2970 delete_dead_insn (insn);
2978 /* We allow one special case which happens to work on all machines we
2979 currently support: a single set with the source being a PLUS of an
2980 eliminable register and a constant. */
2982 && GET_CODE (SET_DEST (old_set)) == REG
2983 && GET_CODE (SET_SRC (old_set)) == PLUS
2984 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2985 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2986 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2988 rtx reg = XEXP (SET_SRC (old_set), 0);
2989 HOST_WIDE_INT offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2991 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2992 if (ep->from_rtx == reg && ep->can_eliminate)
2994 offset += ep->offset;
2999 /* We assume here that if we need a PARALLEL with
3000 CLOBBERs for this assignment, we can do with the
3001 MATCH_SCRATCHes that add_clobbers allocates.
3002 There's not much we can do if that doesn't work. */
3003 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3007 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3010 rtvec vec = rtvec_alloc (num_clobbers + 1);
3012 vec->elem[0] = PATTERN (insn);
3013 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3014 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3016 if (INSN_CODE (insn) < 0)
3021 new_body = old_body;
3024 new_body = copy_insn (old_body);
3025 if (REG_NOTES (insn))
3026 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3028 PATTERN (insn) = new_body;
3029 old_set = single_set (insn);
3031 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3032 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3035 /* This can't have an effect on elimination offsets, so skip right
3041 /* Determine the effects of this insn on elimination offsets. */
3042 elimination_effects (old_body, 0);
3044 /* Eliminate all eliminable registers occurring in operands that
3045 can be handled by reload. */
3046 extract_insn (insn);
3047 for (i = 0; i < recog_data.n_operands; i++)
3049 orig_operand[i] = recog_data.operand[i];
3050 substed_operand[i] = recog_data.operand[i];
3052 /* For an asm statement, every operand is eliminable. */
3053 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3055 /* Check for setting a register that we know about. */
3056 if (recog_data.operand_type[i] != OP_IN
3057 && GET_CODE (orig_operand[i]) == REG)
3059 /* If we are assigning to a register that can be eliminated, it
3060 must be as part of a PARALLEL, since the code above handles
3061 single SETs. We must indicate that we can no longer
3062 eliminate this reg. */
3063 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3065 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3066 ep->can_eliminate = 0;
3069 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3070 replace ? insn : NULL_RTX);
3071 if (substed_operand[i] != orig_operand[i])
3073 /* Terminate the search in check_eliminable_occurrences at
3075 *recog_data.operand_loc[i] = 0;
3077 /* If an output operand changed from a REG to a MEM and INSN is an
3078 insn, write a CLOBBER insn. */
3079 if (recog_data.operand_type[i] != OP_IN
3080 && GET_CODE (orig_operand[i]) == REG
3081 && GET_CODE (substed_operand[i]) == MEM
3083 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3088 for (i = 0; i < recog_data.n_dups; i++)
3089 *recog_data.dup_loc[i]
3090 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3092 /* If any eliminable remain, they aren't eliminable anymore. */
3093 check_eliminable_occurrences (old_body);
3095 /* Substitute the operands; the new values are in the substed_operand
3097 for (i = 0; i < recog_data.n_operands; i++)
3098 *recog_data.operand_loc[i] = substed_operand[i];
3099 for (i = 0; i < recog_data.n_dups; i++)
3100 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3102 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3103 re-recognize the insn. We do this in case we had a simple addition
3104 but now can do this as a load-address. This saves an insn in this
3106 If re-recognition fails, the old insn code number will still be used,
3107 and some register operands may have changed into PLUS expressions.
3108 These will be handled by find_reloads by loading them into a register
3113 /* If we aren't replacing things permanently and we changed something,
3114 make another copy to ensure that all the RTL is new. Otherwise
3115 things can go wrong if find_reload swaps commutative operands
3116 and one is inside RTL that has been copied while the other is not. */
3117 new_body = old_body;
3120 new_body = copy_insn (old_body);
3121 if (REG_NOTES (insn))
3122 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3124 PATTERN (insn) = new_body;
3126 /* If we had a move insn but now we don't, rerecognize it. This will
3127 cause spurious re-recognition if the old move had a PARALLEL since
3128 the new one still will, but we can't call single_set without
3129 having put NEW_BODY into the insn and the re-recognition won't
3130 hurt in this rare case. */
3131 /* ??? Why this huge if statement - why don't we just rerecognize the
3135 && ((GET_CODE (SET_SRC (old_set)) == REG
3136 && (GET_CODE (new_body) != SET
3137 || GET_CODE (SET_SRC (new_body)) != REG))
3138 /* If this was a load from or store to memory, compare
3139 the MEM in recog_data.operand to the one in the insn.
3140 If they are not equal, then rerecognize the insn. */
3142 && ((GET_CODE (SET_SRC (old_set)) == MEM
3143 && SET_SRC (old_set) != recog_data.operand[1])
3144 || (GET_CODE (SET_DEST (old_set)) == MEM
3145 && SET_DEST (old_set) != recog_data.operand[0])))
3146 /* If this was an add insn before, rerecognize. */
3147 || GET_CODE (SET_SRC (old_set)) == PLUS))
3149 int new_icode = recog (PATTERN (insn), insn, 0);
3151 INSN_CODE (insn) = icode;
3155 /* Restore the old body. If there were any changes to it, we made a copy
3156 of it while the changes were still in place, so we'll correctly return
3157 a modified insn below. */
3160 /* Restore the old body. */
3161 for (i = 0; i < recog_data.n_operands; i++)
3162 *recog_data.operand_loc[i] = orig_operand[i];
3163 for (i = 0; i < recog_data.n_dups; i++)
3164 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3167 /* Update all elimination pairs to reflect the status after the current
3168 insn. The changes we make were determined by the earlier call to
3169 elimination_effects.
3171 We also detect cases where register elimination cannot be done,
3172 namely, if a register would be both changed and referenced outside a MEM
3173 in the resulting insn since such an insn is often undefined and, even if
3174 not, we cannot know what meaning will be given to it. Note that it is
3175 valid to have a register used in an address in an insn that changes it
3176 (presumably with a pre- or post-increment or decrement).
3178 If anything changes, return nonzero. */
3180 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3182 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3183 ep->can_eliminate = 0;
3185 ep->ref_outside_mem = 0;
3187 if (ep->previous_offset != ep->offset)
3192 /* If we changed something, perform elimination in REG_NOTES. This is
3193 needed even when REPLACE is zero because a REG_DEAD note might refer
3194 to a register that we eliminate and could cause a different number
3195 of spill registers to be needed in the final reload pass than in
3197 if (val && REG_NOTES (insn) != 0)
3198 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3203 /* Loop through all elimination pairs.
3204 Recalculate the number not at initial offset.
3206 Compute the maximum offset (minimum offset if the stack does not
3207 grow downward) for each elimination pair. */
3210 update_eliminable_offsets (void)
3212 struct elim_table *ep;
3214 num_not_at_initial_offset = 0;
3215 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3217 ep->previous_offset = ep->offset;
3218 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3219 num_not_at_initial_offset++;
3223 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3224 replacement we currently believe is valid, mark it as not eliminable if X
3225 modifies DEST in any way other than by adding a constant integer to it.
3227 If DEST is the frame pointer, we do nothing because we assume that
3228 all assignments to the hard frame pointer are nonlocal gotos and are being
3229 done at a time when they are valid and do not disturb anything else.
3230 Some machines want to eliminate a fake argument pointer with either the
3231 frame or stack pointer. Assignments to the hard frame pointer must not
3232 prevent this elimination.
3234 Called via note_stores from reload before starting its passes to scan
3235 the insns of the function. */
3238 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3242 /* A SUBREG of a hard register here is just changing its mode. We should
3243 not see a SUBREG of an eliminable hard register, but check just in
3245 if (GET_CODE (dest) == SUBREG)
3246 dest = SUBREG_REG (dest);
3248 if (dest == hard_frame_pointer_rtx)
3251 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3252 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3253 && (GET_CODE (x) != SET
3254 || GET_CODE (SET_SRC (x)) != PLUS
3255 || XEXP (SET_SRC (x), 0) != dest
3256 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3258 reg_eliminate[i].can_eliminate_previous
3259 = reg_eliminate[i].can_eliminate = 0;
3264 /* Verify that the initial elimination offsets did not change since the
3265 last call to set_initial_elim_offsets. This is used to catch cases
3266 where something illegal happened during reload_as_needed that could
3267 cause incorrect code to be generated if we did not check for it. */
3270 verify_initial_elim_offsets (void)
3274 #ifdef ELIMINABLE_REGS
3275 struct elim_table *ep;
3277 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3279 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3280 if (t != ep->initial_offset)
3284 INITIAL_FRAME_POINTER_OFFSET (t);
3285 if (t != reg_eliminate[0].initial_offset)
3290 /* Reset all offsets on eliminable registers to their initial values. */
3293 set_initial_elim_offsets (void)
3295 struct elim_table *ep = reg_eliminate;
3297 #ifdef ELIMINABLE_REGS
3298 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3300 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3301 ep->previous_offset = ep->offset = ep->initial_offset;
3304 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3305 ep->previous_offset = ep->offset = ep->initial_offset;
3308 num_not_at_initial_offset = 0;
3311 /* Initialize the known label offsets.
3312 Set a known offset for each forced label to be at the initial offset
3313 of each elimination. We do this because we assume that all
3314 computed jumps occur from a location where each elimination is
3315 at its initial offset.
3316 For all other labels, show that we don't know the offsets. */
3319 set_initial_label_offsets (void)
3322 memset (offsets_known_at, 0, num_labels);
3324 for (x = forced_labels; x; x = XEXP (x, 1))
3326 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3329 /* Set all elimination offsets to the known values for the code label given
3333 set_offsets_for_label (rtx insn)
3336 int label_nr = CODE_LABEL_NUMBER (insn);
3337 struct elim_table *ep;
3339 num_not_at_initial_offset = 0;
3340 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3342 ep->offset = ep->previous_offset
3343 = offsets_at[label_nr - first_label_num][i];
3344 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3345 num_not_at_initial_offset++;
3349 /* See if anything that happened changes which eliminations are valid.
3350 For example, on the SPARC, whether or not the frame pointer can
3351 be eliminated can depend on what registers have been used. We need
3352 not check some conditions again (such as flag_omit_frame_pointer)
3353 since they can't have changed. */
3356 update_eliminables (HARD_REG_SET *pset)
3358 int previous_frame_pointer_needed = frame_pointer_needed;
3359 struct elim_table *ep;
3361 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3362 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3363 #ifdef ELIMINABLE_REGS
3364 || ! CAN_ELIMINATE (ep->from, ep->to)
3367 ep->can_eliminate = 0;
3369 /* Look for the case where we have discovered that we can't replace
3370 register A with register B and that means that we will now be
3371 trying to replace register A with register C. This means we can
3372 no longer replace register C with register B and we need to disable
3373 such an elimination, if it exists. This occurs often with A == ap,
3374 B == sp, and C == fp. */
3376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3378 struct elim_table *op;
3381 if (! ep->can_eliminate && ep->can_eliminate_previous)
3383 /* Find the current elimination for ep->from, if there is a
3385 for (op = reg_eliminate;
3386 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3387 if (op->from == ep->from && op->can_eliminate)
3393 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3395 for (op = reg_eliminate;
3396 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3397 if (op->from == new_to && op->to == ep->to)
3398 op->can_eliminate = 0;
3402 /* See if any registers that we thought we could eliminate the previous
3403 time are no longer eliminable. If so, something has changed and we
3404 must spill the register. Also, recompute the number of eliminable
3405 registers and see if the frame pointer is needed; it is if there is
3406 no elimination of the frame pointer that we can perform. */
3408 frame_pointer_needed = 1;
3409 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3411 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3412 && ep->to != HARD_FRAME_POINTER_REGNUM)
3413 frame_pointer_needed = 0;
3415 if (! ep->can_eliminate && ep->can_eliminate_previous)
3417 ep->can_eliminate_previous = 0;
3418 SET_HARD_REG_BIT (*pset, ep->from);
3423 /* If we didn't need a frame pointer last time, but we do now, spill
3424 the hard frame pointer. */
3425 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3426 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3429 /* Initialize the table of registers to eliminate. */
3432 init_elim_table (void)
3434 struct elim_table *ep;
3435 #ifdef ELIMINABLE_REGS
3436 const struct elim_table_1 *ep1;
3440 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3442 /* Does this function require a frame pointer? */
3444 frame_pointer_needed = (! flag_omit_frame_pointer
3445 #ifdef EXIT_IGNORE_STACK
3446 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3447 and restore sp for alloca. So we can't eliminate
3448 the frame pointer in that case. At some point,
3449 we should improve this by emitting the
3450 sp-adjusting insns for this case. */
3451 || (current_function_calls_alloca
3452 && EXIT_IGNORE_STACK)
3454 || FRAME_POINTER_REQUIRED);
3458 #ifdef ELIMINABLE_REGS
3459 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3460 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3462 ep->from = ep1->from;
3464 ep->can_eliminate = ep->can_eliminate_previous
3465 = (CAN_ELIMINATE (ep->from, ep->to)
3466 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3469 reg_eliminate[0].from = reg_eliminate_1[0].from;
3470 reg_eliminate[0].to = reg_eliminate_1[0].to;
3471 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3472 = ! frame_pointer_needed;
3475 /* Count the number of eliminable registers and build the FROM and TO
3476 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3477 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3478 We depend on this. */
3479 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3481 num_eliminable += ep->can_eliminate;
3482 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3483 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3487 /* Kick all pseudos out of hard register REGNO.
3489 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3490 because we found we can't eliminate some register. In the case, no pseudos
3491 are allowed to be in the register, even if they are only in a block that
3492 doesn't require spill registers, unlike the case when we are spilling this
3493 hard reg to produce another spill register.
3495 Return nonzero if any pseudos needed to be kicked out. */
3498 spill_hard_reg (unsigned int regno, int cant_eliminate)
3504 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3505 regs_ever_live[regno] = 1;
3508 /* Spill every pseudo reg that was allocated to this reg
3509 or to something that overlaps this reg. */
3511 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3512 if (reg_renumber[i] >= 0
3513 && (unsigned int) reg_renumber[i] <= regno
3514 && ((unsigned int) reg_renumber[i]
3515 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3516 PSEUDO_REGNO_MODE (i))
3518 SET_REGNO_REG_SET (&spilled_pseudos, i);
3521 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3522 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3525 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3527 IOR_HARD_REG_SET (*set1, *set2);
3530 /* After find_reload_regs has been run for all insn that need reloads,
3531 and/or spill_hard_regs was called, this function is used to actually
3532 spill pseudo registers and try to reallocate them. It also sets up the
3533 spill_regs array for use by choose_reload_regs. */
3536 finish_spills (int global)
3538 struct insn_chain *chain;
3539 int something_changed = 0;
3542 /* Build the spill_regs array for the function. */
3543 /* If there are some registers still to eliminate and one of the spill regs
3544 wasn't ever used before, additional stack space may have to be
3545 allocated to store this register. Thus, we may have changed the offset
3546 between the stack and frame pointers, so mark that something has changed.
3548 One might think that we need only set VAL to 1 if this is a call-used
3549 register. However, the set of registers that must be saved by the
3550 prologue is not identical to the call-used set. For example, the
3551 register used by the call insn for the return PC is a call-used register,
3552 but must be saved by the prologue. */
3555 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3556 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3558 spill_reg_order[i] = n_spills;
3559 spill_regs[n_spills++] = i;
3560 if (num_eliminable && ! regs_ever_live[i])
3561 something_changed = 1;
3562 regs_ever_live[i] = 1;
3565 spill_reg_order[i] = -1;
3567 EXECUTE_IF_SET_IN_REG_SET
3568 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3570 /* Record the current hard register the pseudo is allocated to in
3571 pseudo_previous_regs so we avoid reallocating it to the same
3572 hard reg in a later pass. */
3573 if (reg_renumber[i] < 0)
3576 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3577 /* Mark it as no longer having a hard register home. */
3578 reg_renumber[i] = -1;
3579 /* We will need to scan everything again. */
3580 something_changed = 1;
3583 /* Retry global register allocation if possible. */
3586 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3587 /* For every insn that needs reloads, set the registers used as spill
3588 regs in pseudo_forbidden_regs for every pseudo live across the
3590 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3592 EXECUTE_IF_SET_IN_REG_SET
3593 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3595 ior_hard_reg_set (pseudo_forbidden_regs + i,
3596 &chain->used_spill_regs);
3598 EXECUTE_IF_SET_IN_REG_SET
3599 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3601 ior_hard_reg_set (pseudo_forbidden_regs + i,
3602 &chain->used_spill_regs);
3606 /* Retry allocating the spilled pseudos. For each reg, merge the
3607 various reg sets that indicate which hard regs can't be used,
3608 and call retry_global_alloc.
3609 We change spill_pseudos here to only contain pseudos that did not
3610 get a new hard register. */
3611 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3612 if (reg_old_renumber[i] != reg_renumber[i])
3614 HARD_REG_SET forbidden;
3615 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3616 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3617 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3618 retry_global_alloc (i, forbidden);
3619 if (reg_renumber[i] >= 0)
3620 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3624 /* Fix up the register information in the insn chain.
3625 This involves deleting those of the spilled pseudos which did not get
3626 a new hard register home from the live_{before,after} sets. */
3627 for (chain = reload_insn_chain; chain; chain = chain->next)
3629 HARD_REG_SET used_by_pseudos;
3630 HARD_REG_SET used_by_pseudos2;
3632 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3633 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3635 /* Mark any unallocated hard regs as available for spills. That
3636 makes inheritance work somewhat better. */
3637 if (chain->need_reload)
3639 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3640 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3641 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3643 /* Save the old value for the sanity test below. */
3644 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3646 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3647 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3648 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3649 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3651 /* Make sure we only enlarge the set. */
3652 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3658 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3659 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3661 int regno = reg_renumber[i];
3662 if (reg_old_renumber[i] == regno)
3665 alter_reg (i, reg_old_renumber[i]);
3666 reg_old_renumber[i] = regno;
3670 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3672 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3673 i, reg_renumber[i]);
3677 return something_changed;
3680 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3681 Also mark any hard registers used to store user variables as
3682 forbidden from being used for spill registers. */
3685 scan_paradoxical_subregs (rtx x)
3689 enum rtx_code code = GET_CODE (x);
3695 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3696 && REG_USERVAR_P (x))
3697 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3706 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3714 if (GET_CODE (SUBREG_REG (x)) == REG
3715 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3716 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3717 = GET_MODE_SIZE (GET_MODE (x));
3724 fmt = GET_RTX_FORMAT (code);
3725 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3728 scan_paradoxical_subregs (XEXP (x, i));
3729 else if (fmt[i] == 'E')
3732 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3733 scan_paradoxical_subregs (XVECEXP (x, i, j));
3738 /* Reload pseudo-registers into hard regs around each insn as needed.
3739 Additional register load insns are output before the insn that needs it
3740 and perhaps store insns after insns that modify the reloaded pseudo reg.
3742 reg_last_reload_reg and reg_reloaded_contents keep track of
3743 which registers are already available in reload registers.
3744 We update these for the reloads that we perform,
3745 as the insns are scanned. */
3748 reload_as_needed (int live_known)
3750 struct insn_chain *chain;
3751 #if defined (AUTO_INC_DEC)
3756 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3757 memset (spill_reg_store, 0, sizeof spill_reg_store);
3758 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3759 reg_has_output_reload = xmalloc (max_regno);
3760 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3762 set_initial_elim_offsets ();
3764 for (chain = reload_insn_chain; chain; chain = chain->next)
3767 rtx insn = chain->insn;
3768 rtx old_next = NEXT_INSN (insn);
3770 /* If we pass a label, copy the offsets from the label information
3771 into the current offsets of each elimination. */
3772 if (GET_CODE (insn) == CODE_LABEL)
3773 set_offsets_for_label (insn);
3775 else if (INSN_P (insn))
3777 rtx oldpat = copy_rtx (PATTERN (insn));
3779 /* If this is a USE and CLOBBER of a MEM, ensure that any
3780 references to eliminable registers have been removed. */
3782 if ((GET_CODE (PATTERN (insn)) == USE
3783 || GET_CODE (PATTERN (insn)) == CLOBBER)
3784 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3785 XEXP (XEXP (PATTERN (insn), 0), 0)
3786 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3787 GET_MODE (XEXP (PATTERN (insn), 0)),
3790 /* If we need to do register elimination processing, do so.
3791 This might delete the insn, in which case we are done. */
3792 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3794 eliminate_regs_in_insn (insn, 1);
3795 if (GET_CODE (insn) == NOTE)
3797 update_eliminable_offsets ();
3802 /* If need_elim is nonzero but need_reload is zero, one might think
3803 that we could simply set n_reloads to 0. However, find_reloads
3804 could have done some manipulation of the insn (such as swapping
3805 commutative operands), and these manipulations are lost during
3806 the first pass for every insn that needs register elimination.
3807 So the actions of find_reloads must be redone here. */
3809 if (! chain->need_elim && ! chain->need_reload
3810 && ! chain->need_operand_change)
3812 /* First find the pseudo regs that must be reloaded for this insn.
3813 This info is returned in the tables reload_... (see reload.h).
3814 Also modify the body of INSN by substituting RELOAD
3815 rtx's for those pseudo regs. */
3818 memset (reg_has_output_reload, 0, max_regno);
3819 CLEAR_HARD_REG_SET (reg_is_output_reload);
3821 find_reloads (insn, 1, spill_indirect_levels, live_known,
3827 rtx next = NEXT_INSN (insn);
3830 prev = PREV_INSN (insn);
3832 /* Now compute which reload regs to reload them into. Perhaps
3833 reusing reload regs from previous insns, or else output
3834 load insns to reload them. Maybe output store insns too.
3835 Record the choices of reload reg in reload_reg_rtx. */
3836 choose_reload_regs (chain);
3838 /* Merge any reloads that we didn't combine for fear of
3839 increasing the number of spill registers needed but now
3840 discover can be safely merged. */
3841 if (SMALL_REGISTER_CLASSES)
3842 merge_assigned_reloads (insn);
3844 /* Generate the insns to reload operands into or out of
3845 their reload regs. */
3846 emit_reload_insns (chain);
3848 /* Substitute the chosen reload regs from reload_reg_rtx
3849 into the insn's body (or perhaps into the bodies of other
3850 load and store insn that we just made for reloading
3851 and that we moved the structure into). */
3852 subst_reloads (insn);
3854 /* If this was an ASM, make sure that all the reload insns
3855 we have generated are valid. If not, give an error
3858 if (asm_noperands (PATTERN (insn)) >= 0)
3859 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3860 if (p != insn && INSN_P (p)
3861 && GET_CODE (PATTERN (p)) != USE
3862 && (recog_memoized (p) < 0
3863 || (extract_insn (p), ! constrain_operands (1))))
3865 error_for_asm (insn,
3866 "`asm' operand requires impossible reload");
3871 if (num_eliminable && chain->need_elim)
3872 update_eliminable_offsets ();
3874 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3875 is no longer validly lying around to save a future reload.
3876 Note that this does not detect pseudos that were reloaded
3877 for this insn in order to be stored in
3878 (obeying register constraints). That is correct; such reload
3879 registers ARE still valid. */
3880 note_stores (oldpat, forget_old_reloads_1, NULL);
3882 /* There may have been CLOBBER insns placed after INSN. So scan
3883 between INSN and NEXT and use them to forget old reloads. */
3884 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3885 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3886 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3889 /* Likewise for regs altered by auto-increment in this insn.
3890 REG_INC notes have been changed by reloading:
3891 find_reloads_address_1 records substitutions for them,
3892 which have been performed by subst_reloads above. */
3893 for (i = n_reloads - 1; i >= 0; i--)
3895 rtx in_reg = rld[i].in_reg;
3898 enum rtx_code code = GET_CODE (in_reg);
3899 /* PRE_INC / PRE_DEC will have the reload register ending up
3900 with the same value as the stack slot, but that doesn't
3901 hold true for POST_INC / POST_DEC. Either we have to
3902 convert the memory access to a true POST_INC / POST_DEC,
3903 or we can't use the reload register for inheritance. */
3904 if ((code == POST_INC || code == POST_DEC)
3905 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3906 REGNO (rld[i].reg_rtx))
3907 /* Make sure it is the inc/dec pseudo, and not
3908 some other (e.g. output operand) pseudo. */
3909 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3910 == REGNO (XEXP (in_reg, 0))))
3913 rtx reload_reg = rld[i].reg_rtx;
3914 enum machine_mode mode = GET_MODE (reload_reg);
3918 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3920 /* We really want to ignore REG_INC notes here, so
3921 use PATTERN (p) as argument to reg_set_p . */
3922 if (reg_set_p (reload_reg, PATTERN (p)))
3924 n = count_occurrences (PATTERN (p), reload_reg, 0);
3929 n = validate_replace_rtx (reload_reg,
3930 gen_rtx (code, mode,
3934 /* We must also verify that the constraints
3935 are met after the replacement. */
3938 n = constrain_operands (1);
3942 /* If the constraints were not met, then
3943 undo the replacement. */
3946 validate_replace_rtx (gen_rtx (code, mode,
3958 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3960 /* Mark this as having an output reload so that the
3961 REG_INC processing code below won't invalidate
3962 the reload for inheritance. */
3963 SET_HARD_REG_BIT (reg_is_output_reload,
3964 REGNO (reload_reg));
3965 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3968 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3971 else if ((code == PRE_INC || code == PRE_DEC)
3972 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3973 REGNO (rld[i].reg_rtx))
3974 /* Make sure it is the inc/dec pseudo, and not
3975 some other (e.g. output operand) pseudo. */
3976 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3977 == REGNO (XEXP (in_reg, 0))))
3979 SET_HARD_REG_BIT (reg_is_output_reload,
3980 REGNO (rld[i].reg_rtx));
3981 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3985 /* If a pseudo that got a hard register is auto-incremented,
3986 we must purge records of copying it into pseudos without
3988 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3989 if (REG_NOTE_KIND (x) == REG_INC)
3991 /* See if this pseudo reg was reloaded in this insn.
3992 If so, its last-reload info is still valid
3993 because it is based on this insn's reload. */
3994 for (i = 0; i < n_reloads; i++)
3995 if (rld[i].out == XEXP (x, 0))
3999 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4003 /* A reload reg's contents are unknown after a label. */
4004 if (GET_CODE (insn) == CODE_LABEL)
4005 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4007 /* Don't assume a reload reg is still good after a call insn
4008 if it is a call-used reg. */
4009 else if (GET_CODE (insn) == CALL_INSN)
4010 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4014 free (reg_last_reload_reg);
4015 free (reg_has_output_reload);
4018 /* Discard all record of any value reloaded from X,
4019 or reloaded in X from someplace else;
4020 unless X is an output reload reg of the current insn.
4022 X may be a hard reg (the reload reg)
4023 or it may be a pseudo reg that was reloaded from. */
4026 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4027 void *data ATTRIBUTE_UNUSED)
4032 /* note_stores does give us subregs of hard regs,
4033 subreg_regno_offset will abort if it is not a hard reg. */
4034 while (GET_CODE (x) == SUBREG)
4036 /* We ignore the subreg offset when calculating the regno,
4037 because we are using the entire underlying hard register
4042 if (GET_CODE (x) != REG)
4047 if (regno >= FIRST_PSEUDO_REGISTER)
4053 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4054 /* Storing into a spilled-reg invalidates its contents.
4055 This can happen if a block-local pseudo is allocated to that reg
4056 and it wasn't spilled because this block's total need is 0.
4057 Then some insn might have an optional reload and use this reg. */
4058 for (i = 0; i < nr; i++)
4059 /* But don't do this if the reg actually serves as an output
4060 reload reg in the current instruction. */
4062 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4064 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4065 spill_reg_store[regno + i] = 0;
4069 /* Since value of X has changed,
4070 forget any value previously copied from it. */
4073 /* But don't forget a copy if this is the output reload
4074 that establishes the copy's validity. */
4075 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4076 reg_last_reload_reg[regno + nr] = 0;
4079 /* The following HARD_REG_SETs indicate when each hard register is
4080 used for a reload of various parts of the current insn. */
4082 /* If reg is unavailable for all reloads. */
4083 static HARD_REG_SET reload_reg_unavailable;
4084 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4085 static HARD_REG_SET reload_reg_used;
4086 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4087 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4088 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4089 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4090 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4091 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4092 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4093 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4094 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4095 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4096 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4097 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4098 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4099 static HARD_REG_SET reload_reg_used_in_op_addr;
4100 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4101 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4102 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4103 static HARD_REG_SET reload_reg_used_in_insn;
4104 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4105 static HARD_REG_SET reload_reg_used_in_other_addr;
4107 /* If reg is in use as a reload reg for any sort of reload. */
4108 static HARD_REG_SET reload_reg_used_at_all;
4110 /* If reg is use as an inherited reload. We just mark the first register
4112 static HARD_REG_SET reload_reg_used_for_inherit;
4114 /* Records which hard regs are used in any way, either as explicit use or
4115 by being allocated to a pseudo during any point of the current insn. */
4116 static HARD_REG_SET reg_used_in_insn;
4118 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4119 TYPE. MODE is used to indicate how many consecutive regs are
4123 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4124 enum machine_mode mode)
4126 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4129 for (i = regno; i < nregs + regno; i++)
4134 SET_HARD_REG_BIT (reload_reg_used, i);
4137 case RELOAD_FOR_INPUT_ADDRESS:
4138 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4141 case RELOAD_FOR_INPADDR_ADDRESS:
4142 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4145 case RELOAD_FOR_OUTPUT_ADDRESS:
4146 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4149 case RELOAD_FOR_OUTADDR_ADDRESS:
4150 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4153 case RELOAD_FOR_OPERAND_ADDRESS:
4154 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4157 case RELOAD_FOR_OPADDR_ADDR:
4158 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4161 case RELOAD_FOR_OTHER_ADDRESS:
4162 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4165 case RELOAD_FOR_INPUT:
4166 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4169 case RELOAD_FOR_OUTPUT:
4170 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4173 case RELOAD_FOR_INSN:
4174 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4178 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4182 /* Similarly, but show REGNO is no longer in use for a reload. */
4185 clear_reload_reg_in_use (unsigned int regno, int opnum,
4186 enum reload_type type, enum machine_mode mode)
4188 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4189 unsigned int start_regno, end_regno, r;
4191 /* A complication is that for some reload types, inheritance might
4192 allow multiple reloads of the same types to share a reload register.
4193 We set check_opnum if we have to check only reloads with the same
4194 operand number, and check_any if we have to check all reloads. */
4195 int check_opnum = 0;
4197 HARD_REG_SET *used_in_set;
4202 used_in_set = &reload_reg_used;
4205 case RELOAD_FOR_INPUT_ADDRESS:
4206 used_in_set = &reload_reg_used_in_input_addr[opnum];
4209 case RELOAD_FOR_INPADDR_ADDRESS:
4211 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4214 case RELOAD_FOR_OUTPUT_ADDRESS:
4215 used_in_set = &reload_reg_used_in_output_addr[opnum];
4218 case RELOAD_FOR_OUTADDR_ADDRESS:
4220 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4223 case RELOAD_FOR_OPERAND_ADDRESS:
4224 used_in_set = &reload_reg_used_in_op_addr;
4227 case RELOAD_FOR_OPADDR_ADDR:
4229 used_in_set = &reload_reg_used_in_op_addr_reload;
4232 case RELOAD_FOR_OTHER_ADDRESS:
4233 used_in_set = &reload_reg_used_in_other_addr;
4237 case RELOAD_FOR_INPUT:
4238 used_in_set = &reload_reg_used_in_input[opnum];
4241 case RELOAD_FOR_OUTPUT:
4242 used_in_set = &reload_reg_used_in_output[opnum];
4245 case RELOAD_FOR_INSN:
4246 used_in_set = &reload_reg_used_in_insn;
4251 /* We resolve conflicts with remaining reloads of the same type by
4252 excluding the intervals of reload registers by them from the
4253 interval of freed reload registers. Since we only keep track of
4254 one set of interval bounds, we might have to exclude somewhat
4255 more than what would be necessary if we used a HARD_REG_SET here.
4256 But this should only happen very infrequently, so there should
4257 be no reason to worry about it. */
4259 start_regno = regno;
4260 end_regno = regno + nregs;
4261 if (check_opnum || check_any)
4263 for (i = n_reloads - 1; i >= 0; i--)
4265 if (rld[i].when_needed == type
4266 && (check_any || rld[i].opnum == opnum)
4269 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4270 unsigned int conflict_end
4272 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4274 /* If there is an overlap with the first to-be-freed register,
4275 adjust the interval start. */
4276 if (conflict_start <= start_regno && conflict_end > start_regno)
4277 start_regno = conflict_end;
4278 /* Otherwise, if there is a conflict with one of the other
4279 to-be-freed registers, adjust the interval end. */
4280 if (conflict_start > start_regno && conflict_start < end_regno)
4281 end_regno = conflict_start;
4286 for (r = start_regno; r < end_regno; r++)
4287 CLEAR_HARD_REG_BIT (*used_in_set, r);
4290 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4291 specified by OPNUM and TYPE. */
4294 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4298 /* In use for a RELOAD_OTHER means it's not available for anything. */
4299 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4300 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4306 /* In use for anything means we can't use it for RELOAD_OTHER. */
4307 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4308 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4309 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4312 for (i = 0; i < reload_n_operands; i++)
4313 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4314 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4315 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4316 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4317 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4318 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4323 case RELOAD_FOR_INPUT:
4324 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4325 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4328 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4331 /* If it is used for some other input, can't use it. */
4332 for (i = 0; i < reload_n_operands; i++)
4333 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4336 /* If it is used in a later operand's address, can't use it. */
4337 for (i = opnum + 1; i < reload_n_operands; i++)
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4339 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4344 case RELOAD_FOR_INPUT_ADDRESS:
4345 /* Can't use a register if it is used for an input address for this
4346 operand or used as an input in an earlier one. */
4347 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4348 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4351 for (i = 0; i < opnum; i++)
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4357 case RELOAD_FOR_INPADDR_ADDRESS:
4358 /* Can't use a register if it is used for an input address
4359 for this operand or used as an input in an earlier
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4364 for (i = 0; i < opnum; i++)
4365 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4370 case RELOAD_FOR_OUTPUT_ADDRESS:
4371 /* Can't use a register if it is used for an output address for this
4372 operand or used as an output in this or a later operand. Note
4373 that multiple output operands are emitted in reverse order, so
4374 the conflicting ones are those with lower indices. */
4375 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4378 for (i = 0; i <= opnum; i++)
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4384 case RELOAD_FOR_OUTADDR_ADDRESS:
4385 /* Can't use a register if it is used for an output address
4386 for this operand or used as an output in this or a
4387 later operand. Note that multiple output operands are
4388 emitted in reverse order, so the conflicting ones are
4389 those with lower indices. */
4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4393 for (i = 0; i <= opnum; i++)
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4399 case RELOAD_FOR_OPERAND_ADDRESS:
4400 for (i = 0; i < reload_n_operands; i++)
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4404 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4405 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4407 case RELOAD_FOR_OPADDR_ADDR:
4408 for (i = 0; i < reload_n_operands; i++)
4409 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4412 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4414 case RELOAD_FOR_OUTPUT:
4415 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4416 outputs, or an operand address for this or an earlier output.
4417 Note that multiple output operands are emitted in reverse order,
4418 so the conflicting ones are those with higher indices. */
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4422 for (i = 0; i < reload_n_operands; i++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4426 for (i = opnum; i < reload_n_operands; i++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4428 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4433 case RELOAD_FOR_INSN:
4434 for (i = 0; i < reload_n_operands; i++)
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4439 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4440 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4442 case RELOAD_FOR_OTHER_ADDRESS:
4443 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4448 /* Return 1 if the value in reload reg REGNO, as used by a reload
4449 needed for the part of the insn specified by OPNUM and TYPE,
4450 is still available in REGNO at the end of the insn.
4452 We can assume that the reload reg was already tested for availability
4453 at the time it is needed, and we should not check this again,
4454 in case the reg has already been marked in use. */
4457 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4464 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4465 its value must reach the end. */
4468 /* If this use is for part of the insn,
4469 its value reaches if no subsequent part uses the same register.
4470 Just like the above function, don't try to do this with lots
4473 case RELOAD_FOR_OTHER_ADDRESS:
4474 /* Here we check for everything else, since these don't conflict
4475 with anything else and everything comes later. */
4477 for (i = 0; i < reload_n_operands; i++)
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4479 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4480 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4481 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4483 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4486 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4487 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4488 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4490 case RELOAD_FOR_INPUT_ADDRESS:
4491 case RELOAD_FOR_INPADDR_ADDRESS:
4492 /* Similar, except that we check only for this and subsequent inputs
4493 and the address of only subsequent inputs and we do not need
4494 to check for RELOAD_OTHER objects since they are known not to
4497 for (i = opnum; i < reload_n_operands; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4501 for (i = opnum + 1; i < reload_n_operands; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4506 for (i = 0; i < reload_n_operands; i++)
4507 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4508 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4515 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4516 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4517 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4519 case RELOAD_FOR_INPUT:
4520 /* Similar to input address, except we start at the next operand for
4521 both input and input address and we do not check for
4522 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4525 for (i = opnum + 1; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4531 /* ... fall through ... */
4533 case RELOAD_FOR_OPERAND_ADDRESS:
4534 /* Check outputs and their addresses. */
4536 for (i = 0; i < reload_n_operands; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4538 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4542 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4544 case RELOAD_FOR_OPADDR_ADDR:
4545 for (i = 0; i < reload_n_operands; i++)
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4551 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4552 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4553 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4555 case RELOAD_FOR_INSN:
4556 /* These conflict with other outputs with RELOAD_OTHER. So
4557 we need only check for output addresses. */
4559 opnum = reload_n_operands;
4561 /* ... fall through ... */
4563 case RELOAD_FOR_OUTPUT:
4564 case RELOAD_FOR_OUTPUT_ADDRESS:
4565 case RELOAD_FOR_OUTADDR_ADDRESS:
4566 /* We already know these can't conflict with a later output. So the
4567 only thing to check are later output addresses.
4568 Note that multiple output operands are emitted in reverse order,
4569 so the conflicting ones are those with lower indices. */
4570 for (i = 0; i < opnum; i++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4581 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4584 This function uses the same algorithm as reload_reg_free_p above. */
4587 reloads_conflict (int r1, int r2)
4589 enum reload_type r1_type = rld[r1].when_needed;
4590 enum reload_type r2_type = rld[r2].when_needed;
4591 int r1_opnum = rld[r1].opnum;
4592 int r2_opnum = rld[r2].opnum;
4594 /* RELOAD_OTHER conflicts with everything. */
4595 if (r2_type == RELOAD_OTHER)
4598 /* Otherwise, check conflicts differently for each type. */
4602 case RELOAD_FOR_INPUT:
4603 return (r2_type == RELOAD_FOR_INSN
4604 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4605 || r2_type == RELOAD_FOR_OPADDR_ADDR
4606 || r2_type == RELOAD_FOR_INPUT
4607 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4608 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4609 && r2_opnum > r1_opnum));
4611 case RELOAD_FOR_INPUT_ADDRESS:
4612 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4613 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4615 case RELOAD_FOR_INPADDR_ADDRESS:
4616 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4617 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4619 case RELOAD_FOR_OUTPUT_ADDRESS:
4620 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4621 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4623 case RELOAD_FOR_OUTADDR_ADDRESS:
4624 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4625 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4627 case RELOAD_FOR_OPERAND_ADDRESS:
4628 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4629 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4631 case RELOAD_FOR_OPADDR_ADDR:
4632 return (r2_type == RELOAD_FOR_INPUT
4633 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4635 case RELOAD_FOR_OUTPUT:
4636 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4637 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4638 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4639 && r2_opnum >= r1_opnum));
4641 case RELOAD_FOR_INSN:
4642 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4643 || r2_type == RELOAD_FOR_INSN
4644 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4646 case RELOAD_FOR_OTHER_ADDRESS:
4647 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4657 /* Indexed by reload number, 1 if incoming value
4658 inherited from previous insns. */
4659 char reload_inherited[MAX_RELOADS];
4661 /* For an inherited reload, this is the insn the reload was inherited from,
4662 if we know it. Otherwise, this is 0. */
4663 rtx reload_inheritance_insn[MAX_RELOADS];
4665 /* If nonzero, this is a place to get the value of the reload,
4666 rather than using reload_in. */
4667 rtx reload_override_in[MAX_RELOADS];
4669 /* For each reload, the hard register number of the register used,
4670 or -1 if we did not need a register for this reload. */
4671 int reload_spill_index[MAX_RELOADS];
4673 /* Subroutine of free_for_value_p, used to check a single register.
4674 START_REGNO is the starting regno of the full reload register
4675 (possibly comprising multiple hard registers) that we are considering. */
4678 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4679 enum reload_type type, rtx value, rtx out,
4680 int reloadnum, int ignore_address_reloads)
4683 /* Set if we see an input reload that must not share its reload register
4684 with any new earlyclobber, but might otherwise share the reload
4685 register with an output or input-output reload. */
4686 int check_earlyclobber = 0;
4690 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4693 if (out == const0_rtx)
4699 /* We use some pseudo 'time' value to check if the lifetimes of the
4700 new register use would overlap with the one of a previous reload
4701 that is not read-only or uses a different value.
4702 The 'time' used doesn't have to be linear in any shape or form, just
4704 Some reload types use different 'buckets' for each operand.
4705 So there are MAX_RECOG_OPERANDS different time values for each
4707 We compute TIME1 as the time when the register for the prospective
4708 new reload ceases to be live, and TIME2 for each existing
4709 reload as the time when that the reload register of that reload
4711 Where there is little to be gained by exact lifetime calculations,
4712 we just make conservative assumptions, i.e. a longer lifetime;
4713 this is done in the 'default:' cases. */
4716 case RELOAD_FOR_OTHER_ADDRESS:
4717 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4718 time1 = copy ? 0 : 1;
4721 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4723 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4724 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4725 respectively, to the time values for these, we get distinct time
4726 values. To get distinct time values for each operand, we have to
4727 multiply opnum by at least three. We round that up to four because
4728 multiply by four is often cheaper. */
4729 case RELOAD_FOR_INPADDR_ADDRESS:
4730 time1 = opnum * 4 + 2;
4732 case RELOAD_FOR_INPUT_ADDRESS:
4733 time1 = opnum * 4 + 3;
4735 case RELOAD_FOR_INPUT:
4736 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4737 executes (inclusive). */
4738 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4740 case RELOAD_FOR_OPADDR_ADDR:
4742 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4743 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4745 case RELOAD_FOR_OPERAND_ADDRESS:
4746 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4748 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4750 case RELOAD_FOR_OUTADDR_ADDRESS:
4751 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4753 case RELOAD_FOR_OUTPUT_ADDRESS:
4754 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4757 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4760 for (i = 0; i < n_reloads; i++)
4762 rtx reg = rld[i].reg_rtx;
4763 if (reg && GET_CODE (reg) == REG
4764 && ((unsigned) regno - true_regnum (reg)
4765 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4768 rtx other_input = rld[i].in;
4770 /* If the other reload loads the same input value, that
4771 will not cause a conflict only if it's loading it into
4772 the same register. */
4773 if (true_regnum (reg) != start_regno)
4774 other_input = NULL_RTX;
4775 if (! other_input || ! rtx_equal_p (other_input, value)
4776 || rld[i].out || out)
4779 switch (rld[i].when_needed)
4781 case RELOAD_FOR_OTHER_ADDRESS:
4784 case RELOAD_FOR_INPADDR_ADDRESS:
4785 /* find_reloads makes sure that a
4786 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4787 by at most one - the first -
4788 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4789 address reload is inherited, the address address reload
4790 goes away, so we can ignore this conflict. */
4791 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4792 && ignore_address_reloads
4793 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4794 Then the address address is still needed to store
4795 back the new address. */
4796 && ! rld[reloadnum].out)
4798 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4799 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4801 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4802 && ignore_address_reloads
4803 /* Unless we are reloading an auto_inc expression. */
4804 && ! rld[reloadnum].out)
4806 time2 = rld[i].opnum * 4 + 2;
4808 case RELOAD_FOR_INPUT_ADDRESS:
4809 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4810 && ignore_address_reloads
4811 && ! rld[reloadnum].out)
4813 time2 = rld[i].opnum * 4 + 3;
4815 case RELOAD_FOR_INPUT:
4816 time2 = rld[i].opnum * 4 + 4;
4817 check_earlyclobber = 1;
4819 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4820 == MAX_RECOG_OPERAND * 4 */
4821 case RELOAD_FOR_OPADDR_ADDR:
4822 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4823 && ignore_address_reloads
4824 && ! rld[reloadnum].out)
4826 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4828 case RELOAD_FOR_OPERAND_ADDRESS:
4829 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4830 check_earlyclobber = 1;
4832 case RELOAD_FOR_INSN:
4833 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4835 case RELOAD_FOR_OUTPUT:
4836 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4837 instruction is executed. */
4838 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4840 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4841 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4843 case RELOAD_FOR_OUTADDR_ADDRESS:
4844 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4845 && ignore_address_reloads
4846 && ! rld[reloadnum].out)
4848 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4850 case RELOAD_FOR_OUTPUT_ADDRESS:
4851 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4854 /* If there is no conflict in the input part, handle this
4855 like an output reload. */
4856 if (! rld[i].in || rtx_equal_p (other_input, value))
4858 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4859 /* Earlyclobbered outputs must conflict with inputs. */
4860 if (earlyclobber_operand_p (rld[i].out))
4861 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4866 /* RELOAD_OTHER might be live beyond instruction execution,
4867 but this is not obvious when we set time2 = 1. So check
4868 here if there might be a problem with the new reload
4869 clobbering the register used by the RELOAD_OTHER. */
4877 && (! rld[i].in || rld[i].out
4878 || ! rtx_equal_p (other_input, value)))
4879 || (out && rld[reloadnum].out_reg
4880 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4886 /* Earlyclobbered outputs must conflict with inputs. */
4887 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4893 /* Return 1 if the value in reload reg REGNO, as used by a reload
4894 needed for the part of the insn specified by OPNUM and TYPE,
4895 may be used to load VALUE into it.
4897 MODE is the mode in which the register is used, this is needed to
4898 determine how many hard regs to test.
4900 Other read-only reloads with the same value do not conflict
4901 unless OUT is nonzero and these other reloads have to live while
4902 output reloads live.
4903 If OUT is CONST0_RTX, this is a special case: it means that the
4904 test should not be for using register REGNO as reload register, but
4905 for copying from register REGNO into the reload register.
4907 RELOADNUM is the number of the reload we want to load this value for;
4908 a reload does not conflict with itself.
4910 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4911 reloads that load an address for the very reload we are considering.
4913 The caller has to make sure that there is no conflict with the return
4917 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4918 enum reload_type type, rtx value, rtx out, int reloadnum,
4919 int ignore_address_reloads)
4921 int nregs = HARD_REGNO_NREGS (regno, mode);
4923 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4924 value, out, reloadnum,
4925 ignore_address_reloads))
4930 /* Determine whether the reload reg X overlaps any rtx'es used for
4931 overriding inheritance. Return nonzero if so. */
4934 conflicts_with_override (rtx x)
4937 for (i = 0; i < n_reloads; i++)
4938 if (reload_override_in[i]
4939 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4944 /* Give an error message saying we failed to find a reload for INSN,
4945 and clear out reload R. */
4947 failed_reload (rtx insn, int r)
4949 if (asm_noperands (PATTERN (insn)) < 0)
4950 /* It's the compiler's fault. */
4951 fatal_insn ("could not find a spill register", insn);
4953 /* It's the user's fault; the operand's mode and constraint
4954 don't match. Disable this reload so we don't crash in final. */
4955 error_for_asm (insn,
4956 "`asm' operand constraint incompatible with operand size");
4960 rld[r].optional = 1;
4961 rld[r].secondary_p = 1;
4964 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4965 for reload R. If it's valid, get an rtx for it. Return nonzero if
4968 set_reload_reg (int i, int r)
4971 rtx reg = spill_reg_rtx[i];
4973 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4974 spill_reg_rtx[i] = reg
4975 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4977 regno = true_regnum (reg);
4979 /* Detect when the reload reg can't hold the reload mode.
4980 This used to be one `if', but Sequent compiler can't handle that. */
4981 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4983 enum machine_mode test_mode = VOIDmode;
4985 test_mode = GET_MODE (rld[r].in);
4986 /* If rld[r].in has VOIDmode, it means we will load it
4987 in whatever mode the reload reg has: to wit, rld[r].mode.
4988 We have already tested that for validity. */
4989 /* Aside from that, we need to test that the expressions
4990 to reload from or into have modes which are valid for this
4991 reload register. Otherwise the reload insns would be invalid. */
4992 if (! (rld[r].in != 0 && test_mode != VOIDmode
4993 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4994 if (! (rld[r].out != 0
4995 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4997 /* The reg is OK. */
5000 /* Mark as in use for this insn the reload regs we use
5002 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5003 rld[r].when_needed, rld[r].mode);
5005 rld[r].reg_rtx = reg;
5006 reload_spill_index[r] = spill_regs[i];
5013 /* Find a spill register to use as a reload register for reload R.
5014 LAST_RELOAD is nonzero if this is the last reload for the insn being
5017 Set rld[R].reg_rtx to the register allocated.
5019 We return 1 if successful, or 0 if we couldn't find a spill reg and
5020 we didn't change anything. */
5023 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5028 /* If we put this reload ahead, thinking it is a group,
5029 then insist on finding a group. Otherwise we can grab a
5030 reg that some other reload needs.
5031 (That can happen when we have a 68000 DATA_OR_FP_REG
5032 which is a group of data regs or one fp reg.)
5033 We need not be so restrictive if there are no more reloads
5036 ??? Really it would be nicer to have smarter handling
5037 for that kind of reg class, where a problem like this is normal.
5038 Perhaps those classes should be avoided for reloading
5039 by use of more alternatives. */
5041 int force_group = rld[r].nregs > 1 && ! last_reload;
5043 /* If we want a single register and haven't yet found one,
5044 take any reg in the right class and not in use.
5045 If we want a consecutive group, here is where we look for it.
5047 We use two passes so we can first look for reload regs to
5048 reuse, which are already in use for other reloads in this insn,
5049 and only then use additional registers.
5050 I think that maximizing reuse is needed to make sure we don't
5051 run out of reload regs. Suppose we have three reloads, and
5052 reloads A and B can share regs. These need two regs.
5053 Suppose A and B are given different regs.
5054 That leaves none for C. */
5055 for (pass = 0; pass < 2; pass++)
5057 /* I is the index in spill_regs.
5058 We advance it round-robin between insns to use all spill regs
5059 equally, so that inherited reloads have a chance
5060 of leapfrogging each other. */
5064 for (count = 0; count < n_spills; count++)
5066 int class = (int) rld[r].class;
5072 regnum = spill_regs[i];
5074 if ((reload_reg_free_p (regnum, rld[r].opnum,
5077 /* We check reload_reg_used to make sure we
5078 don't clobber the return register. */
5079 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5080 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5081 rld[r].when_needed, rld[r].in,
5083 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5084 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5085 /* Look first for regs to share, then for unshared. But
5086 don't share regs used for inherited reloads; they are
5087 the ones we want to preserve. */
5089 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5091 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5094 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5095 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5096 (on 68000) got us two FP regs. If NR is 1,
5097 we would reject both of them. */
5100 /* If we need only one reg, we have already won. */
5103 /* But reject a single reg if we demand a group. */
5108 /* Otherwise check that as many consecutive regs as we need
5109 are available here. */
5112 int regno = regnum + nr - 1;
5113 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5114 && spill_reg_order[regno] >= 0
5115 && reload_reg_free_p (regno, rld[r].opnum,
5116 rld[r].when_needed)))
5125 /* If we found something on pass 1, omit pass 2. */
5126 if (count < n_spills)
5130 /* We should have found a spill register by now. */
5131 if (count >= n_spills)
5134 /* I is the index in SPILL_REG_RTX of the reload register we are to
5135 allocate. Get an rtx for it and find its register number. */
5137 return set_reload_reg (i, r);
5140 /* Initialize all the tables needed to allocate reload registers.
5141 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5142 is the array we use to restore the reg_rtx field for every reload. */
5145 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5149 for (i = 0; i < n_reloads; i++)
5150 rld[i].reg_rtx = save_reload_reg_rtx[i];
5152 memset (reload_inherited, 0, MAX_RELOADS);
5153 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5154 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5156 CLEAR_HARD_REG_SET (reload_reg_used);
5157 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5158 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5159 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5160 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5161 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5163 CLEAR_HARD_REG_SET (reg_used_in_insn);
5166 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5167 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5168 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5169 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5170 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5171 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5174 for (i = 0; i < reload_n_operands; i++)
5176 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5177 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5178 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5179 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5180 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5181 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5184 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5186 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5188 for (i = 0; i < n_reloads; i++)
5189 /* If we have already decided to use a certain register,
5190 don't use it in another way. */
5192 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5193 rld[i].when_needed, rld[i].mode);
5196 /* Assign hard reg targets for the pseudo-registers we must reload
5197 into hard regs for this insn.
5198 Also output the instructions to copy them in and out of the hard regs.
5200 For machines with register classes, we are responsible for
5201 finding a reload reg in the proper class. */
5204 choose_reload_regs (struct insn_chain *chain)
5206 rtx insn = chain->insn;
5208 unsigned int max_group_size = 1;
5209 enum reg_class group_class = NO_REGS;
5210 int pass, win, inheritance;
5212 rtx save_reload_reg_rtx[MAX_RELOADS];
5214 /* In order to be certain of getting the registers we need,
5215 we must sort the reloads into order of increasing register class.
5216 Then our grabbing of reload registers will parallel the process
5217 that provided the reload registers.
5219 Also note whether any of the reloads wants a consecutive group of regs.
5220 If so, record the maximum size of the group desired and what
5221 register class contains all the groups needed by this insn. */
5223 for (j = 0; j < n_reloads; j++)
5225 reload_order[j] = j;
5226 reload_spill_index[j] = -1;
5228 if (rld[j].nregs > 1)
5230 max_group_size = MAX (rld[j].nregs, max_group_size);
5232 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5235 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5239 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5241 /* If -O, try first with inheritance, then turning it off.
5242 If not -O, don't do inheritance.
5243 Using inheritance when not optimizing leads to paradoxes
5244 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5245 because one side of the comparison might be inherited. */
5247 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5249 choose_reload_regs_init (chain, save_reload_reg_rtx);
5251 /* Process the reloads in order of preference just found.
5252 Beyond this point, subregs can be found in reload_reg_rtx.
5254 This used to look for an existing reloaded home for all of the
5255 reloads, and only then perform any new reloads. But that could lose
5256 if the reloads were done out of reg-class order because a later
5257 reload with a looser constraint might have an old home in a register
5258 needed by an earlier reload with a tighter constraint.
5260 To solve this, we make two passes over the reloads, in the order
5261 described above. In the first pass we try to inherit a reload
5262 from a previous insn. If there is a later reload that needs a
5263 class that is a proper subset of the class being processed, we must
5264 also allocate a spill register during the first pass.
5266 Then make a second pass over the reloads to allocate any reloads
5267 that haven't been given registers yet. */
5269 for (j = 0; j < n_reloads; j++)
5271 int r = reload_order[j];
5272 rtx search_equiv = NULL_RTX;
5274 /* Ignore reloads that got marked inoperative. */
5275 if (rld[r].out == 0 && rld[r].in == 0
5276 && ! rld[r].secondary_p)
5279 /* If find_reloads chose to use reload_in or reload_out as a reload
5280 register, we don't need to chose one. Otherwise, try even if it
5281 found one since we might save an insn if we find the value lying
5283 Try also when reload_in is a pseudo without a hard reg. */
5284 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5285 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5286 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5287 && GET_CODE (rld[r].in) != MEM
5288 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5291 #if 0 /* No longer needed for correct operation.
5292 It might give better code, or might not; worth an experiment? */
5293 /* If this is an optional reload, we can't inherit from earlier insns
5294 until we are sure that any non-optional reloads have been allocated.
5295 The following code takes advantage of the fact that optional reloads
5296 are at the end of reload_order. */
5297 if (rld[r].optional != 0)
5298 for (i = 0; i < j; i++)
5299 if ((rld[reload_order[i]].out != 0
5300 || rld[reload_order[i]].in != 0
5301 || rld[reload_order[i]].secondary_p)
5302 && ! rld[reload_order[i]].optional
5303 && rld[reload_order[i]].reg_rtx == 0)
5304 allocate_reload_reg (chain, reload_order[i], 0);
5307 /* First see if this pseudo is already available as reloaded
5308 for a previous insn. We cannot try to inherit for reloads
5309 that are smaller than the maximum number of registers needed
5310 for groups unless the register we would allocate cannot be used
5313 We could check here to see if this is a secondary reload for
5314 an object that is already in a register of the desired class.
5315 This would avoid the need for the secondary reload register.
5316 But this is complex because we can't easily determine what
5317 objects might want to be loaded via this reload. So let a
5318 register be allocated here. In `emit_reload_insns' we suppress
5319 one of the loads in the case described above. */
5325 enum machine_mode mode = VOIDmode;
5329 else if (GET_CODE (rld[r].in) == REG)
5331 regno = REGNO (rld[r].in);
5332 mode = GET_MODE (rld[r].in);
5334 else if (GET_CODE (rld[r].in_reg) == REG)
5336 regno = REGNO (rld[r].in_reg);
5337 mode = GET_MODE (rld[r].in_reg);
5339 else if (GET_CODE (rld[r].in_reg) == SUBREG
5340 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5342 byte = SUBREG_BYTE (rld[r].in_reg);
5343 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5344 if (regno < FIRST_PSEUDO_REGISTER)
5345 regno = subreg_regno (rld[r].in_reg);
5346 mode = GET_MODE (rld[r].in_reg);
5349 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5350 || GET_CODE (rld[r].in_reg) == PRE_DEC
5351 || GET_CODE (rld[r].in_reg) == POST_INC
5352 || GET_CODE (rld[r].in_reg) == POST_DEC)
5353 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5355 regno = REGNO (XEXP (rld[r].in_reg, 0));
5356 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5357 rld[r].out = rld[r].in;
5361 /* This won't work, since REGNO can be a pseudo reg number.
5362 Also, it takes much more hair to keep track of all the things
5363 that can invalidate an inherited reload of part of a pseudoreg. */
5364 else if (GET_CODE (rld[r].in) == SUBREG
5365 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5366 regno = subreg_regno (rld[r].in);
5369 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5371 enum reg_class class = rld[r].class, last_class;
5372 rtx last_reg = reg_last_reload_reg[regno];
5373 enum machine_mode need_mode;
5375 i = REGNO (last_reg);
5376 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5377 last_class = REGNO_REG_CLASS (i);
5383 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5384 GET_MODE_CLASS (mode));
5387 #ifdef CANNOT_CHANGE_MODE_CLASS
5388 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5392 (GET_MODE_SIZE (GET_MODE (last_reg))
5393 >= GET_MODE_SIZE (need_mode))
5394 #ifdef CANNOT_CHANGE_MODE_CLASS
5397 && reg_reloaded_contents[i] == regno
5398 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5399 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5400 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5401 /* Even if we can't use this register as a reload
5402 register, we might use it for reload_override_in,
5403 if copying it to the desired class is cheap
5405 || ((REGISTER_MOVE_COST (mode, last_class, class)
5406 < MEMORY_MOVE_COST (mode, class, 1))
5407 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5408 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5412 #ifdef SECONDARY_MEMORY_NEEDED
5413 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5418 && (rld[r].nregs == max_group_size
5419 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5421 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5422 rld[r].when_needed, rld[r].in,
5425 /* If a group is needed, verify that all the subsequent
5426 registers still have their values intact. */
5427 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5430 for (k = 1; k < nr; k++)
5431 if (reg_reloaded_contents[i + k] != regno
5432 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5440 last_reg = (GET_MODE (last_reg) == mode
5441 ? last_reg : gen_rtx_REG (mode, i));
5444 for (k = 0; k < nr; k++)
5445 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5448 /* We found a register that contains the
5449 value we need. If this register is the
5450 same as an `earlyclobber' operand of the
5451 current insn, just mark it as a place to
5452 reload from since we can't use it as the
5453 reload register itself. */
5455 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5456 if (reg_overlap_mentioned_for_reload_p
5457 (reg_last_reload_reg[regno],
5458 reload_earlyclobbers[i1]))
5461 if (i1 != n_earlyclobbers
5462 || ! (free_for_value_p (i, rld[r].mode,
5464 rld[r].when_needed, rld[r].in,
5466 /* Don't use it if we'd clobber a pseudo reg. */
5467 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5469 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5470 /* Don't clobber the frame pointer. */
5471 || (i == HARD_FRAME_POINTER_REGNUM
5472 && frame_pointer_needed
5474 /* Don't really use the inherited spill reg
5475 if we need it wider than we've got it. */
5476 || (GET_MODE_SIZE (rld[r].mode)
5477 > GET_MODE_SIZE (mode))
5480 /* If find_reloads chose reload_out as reload
5481 register, stay with it - that leaves the
5482 inherited register for subsequent reloads. */
5483 || (rld[r].out && rld[r].reg_rtx
5484 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5486 if (! rld[r].optional)
5488 reload_override_in[r] = last_reg;
5489 reload_inheritance_insn[r]
5490 = reg_reloaded_insn[i];
5496 /* We can use this as a reload reg. */
5497 /* Mark the register as in use for this part of
5499 mark_reload_reg_in_use (i,
5503 rld[r].reg_rtx = last_reg;
5504 reload_inherited[r] = 1;
5505 reload_inheritance_insn[r]
5506 = reg_reloaded_insn[i];
5507 reload_spill_index[r] = i;
5508 for (k = 0; k < nr; k++)
5509 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5517 /* Here's another way to see if the value is already lying around. */
5520 && ! reload_inherited[r]
5522 && (CONSTANT_P (rld[r].in)
5523 || GET_CODE (rld[r].in) == PLUS
5524 || GET_CODE (rld[r].in) == REG
5525 || GET_CODE (rld[r].in) == MEM)
5526 && (rld[r].nregs == max_group_size
5527 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5528 search_equiv = rld[r].in;
5529 /* If this is an output reload from a simple move insn, look
5530 if an equivalence for the input is available. */
5531 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5533 rtx set = single_set (insn);
5536 && rtx_equal_p (rld[r].out, SET_DEST (set))
5537 && CONSTANT_P (SET_SRC (set)))
5538 search_equiv = SET_SRC (set);
5544 = find_equiv_reg (search_equiv, insn, rld[r].class,
5545 -1, NULL, 0, rld[r].mode);
5550 if (GET_CODE (equiv) == REG)
5551 regno = REGNO (equiv);
5552 else if (GET_CODE (equiv) == SUBREG)
5554 /* This must be a SUBREG of a hard register.
5555 Make a new REG since this might be used in an
5556 address and not all machines support SUBREGs
5558 regno = subreg_regno (equiv);
5559 equiv = gen_rtx_REG (rld[r].mode, regno);
5565 /* If we found a spill reg, reject it unless it is free
5566 and of the desired class. */
5570 int bad_for_class = 0;
5571 int max_regno = regno + rld[r].nregs;
5573 for (i = regno; i < max_regno; i++)
5575 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5577 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5582 && ! free_for_value_p (regno, rld[r].mode,
5583 rld[r].opnum, rld[r].when_needed,
5584 rld[r].in, rld[r].out, r, 1))
5589 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5592 /* We found a register that contains the value we need.
5593 If this register is the same as an `earlyclobber' operand
5594 of the current insn, just mark it as a place to reload from
5595 since we can't use it as the reload register itself. */
5598 for (i = 0; i < n_earlyclobbers; i++)
5599 if (reg_overlap_mentioned_for_reload_p (equiv,
5600 reload_earlyclobbers[i]))
5602 if (! rld[r].optional)
5603 reload_override_in[r] = equiv;
5608 /* If the equiv register we have found is explicitly clobbered
5609 in the current insn, it depends on the reload type if we
5610 can use it, use it for reload_override_in, or not at all.
5611 In particular, we then can't use EQUIV for a
5612 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5616 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5617 switch (rld[r].when_needed)
5619 case RELOAD_FOR_OTHER_ADDRESS:
5620 case RELOAD_FOR_INPADDR_ADDRESS:
5621 case RELOAD_FOR_INPUT_ADDRESS:
5622 case RELOAD_FOR_OPADDR_ADDR:
5625 case RELOAD_FOR_INPUT:
5626 case RELOAD_FOR_OPERAND_ADDRESS:
5627 if (! rld[r].optional)
5628 reload_override_in[r] = equiv;
5634 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5635 switch (rld[r].when_needed)
5637 case RELOAD_FOR_OTHER_ADDRESS:
5638 case RELOAD_FOR_INPADDR_ADDRESS:
5639 case RELOAD_FOR_INPUT_ADDRESS:
5640 case RELOAD_FOR_OPADDR_ADDR:
5641 case RELOAD_FOR_OPERAND_ADDRESS:
5642 case RELOAD_FOR_INPUT:
5645 if (! rld[r].optional)
5646 reload_override_in[r] = equiv;
5654 /* If we found an equivalent reg, say no code need be generated
5655 to load it, and use it as our reload reg. */
5657 && (regno != HARD_FRAME_POINTER_REGNUM
5658 || !frame_pointer_needed))
5660 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5662 rld[r].reg_rtx = equiv;
5663 reload_inherited[r] = 1;
5665 /* If reg_reloaded_valid is not set for this register,
5666 there might be a stale spill_reg_store lying around.
5667 We must clear it, since otherwise emit_reload_insns
5668 might delete the store. */
5669 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5670 spill_reg_store[regno] = NULL_RTX;
5671 /* If any of the hard registers in EQUIV are spill
5672 registers, mark them as in use for this insn. */
5673 for (k = 0; k < nr; k++)
5675 i = spill_reg_order[regno + k];
5678 mark_reload_reg_in_use (regno, rld[r].opnum,
5681 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5688 /* If we found a register to use already, or if this is an optional
5689 reload, we are done. */
5690 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5694 /* No longer needed for correct operation. Might or might
5695 not give better code on the average. Want to experiment? */
5697 /* See if there is a later reload that has a class different from our
5698 class that intersects our class or that requires less register
5699 than our reload. If so, we must allocate a register to this
5700 reload now, since that reload might inherit a previous reload
5701 and take the only available register in our class. Don't do this
5702 for optional reloads since they will force all previous reloads
5703 to be allocated. Also don't do this for reloads that have been
5706 for (i = j + 1; i < n_reloads; i++)
5708 int s = reload_order[i];
5710 if ((rld[s].in == 0 && rld[s].out == 0
5711 && ! rld[s].secondary_p)
5715 if ((rld[s].class != rld[r].class
5716 && reg_classes_intersect_p (rld[r].class,
5718 || rld[s].nregs < rld[r].nregs)
5725 allocate_reload_reg (chain, r, j == n_reloads - 1);
5729 /* Now allocate reload registers for anything non-optional that
5730 didn't get one yet. */
5731 for (j = 0; j < n_reloads; j++)
5733 int r = reload_order[j];
5735 /* Ignore reloads that got marked inoperative. */
5736 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5739 /* Skip reloads that already have a register allocated or are
5741 if (rld[r].reg_rtx != 0 || rld[r].optional)
5744 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5748 /* If that loop got all the way, we have won. */
5755 /* Loop around and try without any inheritance. */
5760 /* First undo everything done by the failed attempt
5761 to allocate with inheritance. */
5762 choose_reload_regs_init (chain, save_reload_reg_rtx);
5764 /* Some sanity tests to verify that the reloads found in the first
5765 pass are identical to the ones we have now. */
5766 if (chain->n_reloads != n_reloads)
5769 for (i = 0; i < n_reloads; i++)
5771 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5773 if (chain->rld[i].when_needed != rld[i].when_needed)
5775 for (j = 0; j < n_spills; j++)
5776 if (spill_regs[j] == chain->rld[i].regno)
5777 if (! set_reload_reg (j, i))
5778 failed_reload (chain->insn, i);
5782 /* If we thought we could inherit a reload, because it seemed that
5783 nothing else wanted the same reload register earlier in the insn,
5784 verify that assumption, now that all reloads have been assigned.
5785 Likewise for reloads where reload_override_in has been set. */
5787 /* If doing expensive optimizations, do one preliminary pass that doesn't
5788 cancel any inheritance, but removes reloads that have been needed only
5789 for reloads that we know can be inherited. */
5790 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5792 for (j = 0; j < n_reloads; j++)
5794 int r = reload_order[j];
5796 if (reload_inherited[r] && rld[r].reg_rtx)
5797 check_reg = rld[r].reg_rtx;
5798 else if (reload_override_in[r]
5799 && (GET_CODE (reload_override_in[r]) == REG
5800 || GET_CODE (reload_override_in[r]) == SUBREG))
5801 check_reg = reload_override_in[r];
5804 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5805 rld[r].opnum, rld[r].when_needed, rld[r].in,
5806 (reload_inherited[r]
5807 ? rld[r].out : const0_rtx),
5812 reload_inherited[r] = 0;
5813 reload_override_in[r] = 0;
5815 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5816 reload_override_in, then we do not need its related
5817 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5818 likewise for other reload types.
5819 We handle this by removing a reload when its only replacement
5820 is mentioned in reload_in of the reload we are going to inherit.
5821 A special case are auto_inc expressions; even if the input is
5822 inherited, we still need the address for the output. We can
5823 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5824 If we succeeded removing some reload and we are doing a preliminary
5825 pass just to remove such reloads, make another pass, since the
5826 removal of one reload might allow us to inherit another one. */
5828 && rld[r].out != rld[r].in
5829 && remove_address_replacements (rld[r].in) && pass)
5834 /* Now that reload_override_in is known valid,
5835 actually override reload_in. */
5836 for (j = 0; j < n_reloads; j++)
5837 if (reload_override_in[j])
5838 rld[j].in = reload_override_in[j];
5840 /* If this reload won't be done because it has been canceled or is
5841 optional and not inherited, clear reload_reg_rtx so other
5842 routines (such as subst_reloads) don't get confused. */
5843 for (j = 0; j < n_reloads; j++)
5844 if (rld[j].reg_rtx != 0
5845 && ((rld[j].optional && ! reload_inherited[j])
5846 || (rld[j].in == 0 && rld[j].out == 0
5847 && ! rld[j].secondary_p)))
5849 int regno = true_regnum (rld[j].reg_rtx);
5851 if (spill_reg_order[regno] >= 0)
5852 clear_reload_reg_in_use (regno, rld[j].opnum,
5853 rld[j].when_needed, rld[j].mode);
5855 reload_spill_index[j] = -1;
5858 /* Record which pseudos and which spill regs have output reloads. */
5859 for (j = 0; j < n_reloads; j++)
5861 int r = reload_order[j];
5863 i = reload_spill_index[r];
5865 /* I is nonneg if this reload uses a register.
5866 If rld[r].reg_rtx is 0, this is an optional reload
5867 that we opted to ignore. */
5868 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5869 && rld[r].reg_rtx != 0)
5871 int nregno = REGNO (rld[r].out_reg);
5874 if (nregno < FIRST_PSEUDO_REGISTER)
5875 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5878 reg_has_output_reload[nregno + nr] = 1;
5882 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5884 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5887 if (rld[r].when_needed != RELOAD_OTHER
5888 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5889 && rld[r].when_needed != RELOAD_FOR_INSN)
5895 /* Deallocate the reload register for reload R. This is called from
5896 remove_address_replacements. */
5899 deallocate_reload_reg (int r)
5903 if (! rld[r].reg_rtx)
5905 regno = true_regnum (rld[r].reg_rtx);
5907 if (spill_reg_order[regno] >= 0)
5908 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5910 reload_spill_index[r] = -1;
5913 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5914 reloads of the same item for fear that we might not have enough reload
5915 registers. However, normally they will get the same reload register
5916 and hence actually need not be loaded twice.
5918 Here we check for the most common case of this phenomenon: when we have
5919 a number of reloads for the same object, each of which were allocated
5920 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5921 reload, and is not modified in the insn itself. If we find such,
5922 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5923 This will not increase the number of spill registers needed and will
5924 prevent redundant code. */
5927 merge_assigned_reloads (rtx insn)
5931 /* Scan all the reloads looking for ones that only load values and
5932 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5933 assigned and not modified by INSN. */
5935 for (i = 0; i < n_reloads; i++)
5937 int conflicting_input = 0;
5938 int max_input_address_opnum = -1;
5939 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5941 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5942 || rld[i].out != 0 || rld[i].reg_rtx == 0
5943 || reg_set_p (rld[i].reg_rtx, insn))
5946 /* Look at all other reloads. Ensure that the only use of this
5947 reload_reg_rtx is in a reload that just loads the same value
5948 as we do. Note that any secondary reloads must be of the identical
5949 class since the values, modes, and result registers are the
5950 same, so we need not do anything with any secondary reloads. */
5952 for (j = 0; j < n_reloads; j++)
5954 if (i == j || rld[j].reg_rtx == 0
5955 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5959 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5960 && rld[j].opnum > max_input_address_opnum)
5961 max_input_address_opnum = rld[j].opnum;
5963 /* If the reload regs aren't exactly the same (e.g, different modes)
5964 or if the values are different, we can't merge this reload.
5965 But if it is an input reload, we might still merge
5966 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5968 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5969 || rld[j].out != 0 || rld[j].in == 0
5970 || ! rtx_equal_p (rld[i].in, rld[j].in))
5972 if (rld[j].when_needed != RELOAD_FOR_INPUT
5973 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5974 || rld[i].opnum > rld[j].opnum)
5975 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5977 conflicting_input = 1;
5978 if (min_conflicting_input_opnum > rld[j].opnum)
5979 min_conflicting_input_opnum = rld[j].opnum;
5983 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5984 we, in fact, found any matching reloads. */
5987 && max_input_address_opnum <= min_conflicting_input_opnum)
5989 for (j = 0; j < n_reloads; j++)
5990 if (i != j && rld[j].reg_rtx != 0
5991 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5992 && (! conflicting_input
5993 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5994 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5996 rld[i].when_needed = RELOAD_OTHER;
5998 reload_spill_index[j] = -1;
5999 transfer_replacements (i, j);
6002 /* If this is now RELOAD_OTHER, look for any reloads that load
6003 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6004 if they were for inputs, RELOAD_OTHER for outputs. Note that
6005 this test is equivalent to looking for reloads for this operand
6007 /* We must take special care when there are two or more reloads to
6008 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6009 same value or a part of it; we must not change its type if there
6010 is a conflicting input. */
6012 if (rld[i].when_needed == RELOAD_OTHER)
6013 for (j = 0; j < n_reloads; j++)
6015 && rld[j].when_needed != RELOAD_OTHER
6016 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6017 && (! conflicting_input
6018 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6019 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6020 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6026 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6027 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6028 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6030 /* Check to see if we accidentally converted two reloads
6031 that use the same reload register with different inputs
6032 to the same type. If so, the resulting code won't work,
6035 for (k = 0; k < j; k++)
6036 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6037 && rld[k].when_needed == rld[j].when_needed
6038 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6039 && ! rtx_equal_p (rld[k].in, rld[j].in))
6046 /* These arrays are filled by emit_reload_insns and its subroutines. */
6047 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6048 static rtx other_input_address_reload_insns = 0;
6049 static rtx other_input_reload_insns = 0;
6050 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6051 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6052 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6053 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6054 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6055 static rtx operand_reload_insns = 0;
6056 static rtx other_operand_reload_insns = 0;
6057 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6059 /* Values to be put in spill_reg_store are put here first. */
6060 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6061 static HARD_REG_SET reg_reloaded_died;
6063 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6064 has the number J. OLD contains the value to be used as input. */
6067 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6070 rtx insn = chain->insn;
6071 rtx reloadreg = rl->reg_rtx;
6072 rtx oldequiv_reg = 0;
6075 enum machine_mode mode;
6078 /* Determine the mode to reload in.
6079 This is very tricky because we have three to choose from.
6080 There is the mode the insn operand wants (rl->inmode).
6081 There is the mode of the reload register RELOADREG.
6082 There is the intrinsic mode of the operand, which we could find
6083 by stripping some SUBREGs.
6084 It turns out that RELOADREG's mode is irrelevant:
6085 we can change that arbitrarily.
6087 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6088 then the reload reg may not support QImode moves, so use SImode.
6089 If foo is in memory due to spilling a pseudo reg, this is safe,
6090 because the QImode value is in the least significant part of a
6091 slot big enough for a SImode. If foo is some other sort of
6092 memory reference, then it is impossible to reload this case,
6093 so previous passes had better make sure this never happens.
6095 Then consider a one-word union which has SImode and one of its
6096 members is a float, being fetched as (SUBREG:SF union:SI).
6097 We must fetch that as SFmode because we could be loading into
6098 a float-only register. In this case OLD's mode is correct.
6100 Consider an immediate integer: it has VOIDmode. Here we need
6101 to get a mode from something else.
6103 In some cases, there is a fourth mode, the operand's
6104 containing mode. If the insn specifies a containing mode for
6105 this operand, it overrides all others.
6107 I am not sure whether the algorithm here is always right,
6108 but it does the right things in those cases. */
6110 mode = GET_MODE (old);
6111 if (mode == VOIDmode)
6114 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6115 /* If we need a secondary register for this operation, see if
6116 the value is already in a register in that class. Don't
6117 do this if the secondary register will be used as a scratch
6120 if (rl->secondary_in_reload >= 0
6121 && rl->secondary_in_icode == CODE_FOR_nothing
6124 = find_equiv_reg (old, insn,
6125 rld[rl->secondary_in_reload].class,
6129 /* If reloading from memory, see if there is a register
6130 that already holds the same value. If so, reload from there.
6131 We can pass 0 as the reload_reg_p argument because
6132 any other reload has either already been emitted,
6133 in which case find_equiv_reg will see the reload-insn,
6134 or has yet to be emitted, in which case it doesn't matter
6135 because we will use this equiv reg right away. */
6137 if (oldequiv == 0 && optimize
6138 && (GET_CODE (old) == MEM
6139 || (GET_CODE (old) == REG
6140 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6141 && reg_renumber[REGNO (old)] < 0)))
6142 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6146 unsigned int regno = true_regnum (oldequiv);
6148 /* Don't use OLDEQUIV if any other reload changes it at an
6149 earlier stage of this insn or at this stage. */
6150 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6151 rl->in, const0_rtx, j, 0))
6154 /* If it is no cheaper to copy from OLDEQUIV into the
6155 reload register than it would be to move from memory,
6156 don't use it. Likewise, if we need a secondary register
6160 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6161 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6163 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6164 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6165 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6169 #ifdef SECONDARY_MEMORY_NEEDED
6170 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6178 /* delete_output_reload is only invoked properly if old contains
6179 the original pseudo register. Since this is replaced with a
6180 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6181 find the pseudo in RELOAD_IN_REG. */
6183 && reload_override_in[j]
6184 && GET_CODE (rl->in_reg) == REG)
6191 else if (GET_CODE (oldequiv) == REG)
6192 oldequiv_reg = oldequiv;
6193 else if (GET_CODE (oldequiv) == SUBREG)
6194 oldequiv_reg = SUBREG_REG (oldequiv);
6196 /* If we are reloading from a register that was recently stored in
6197 with an output-reload, see if we can prove there was
6198 actually no need to store the old value in it. */
6200 if (optimize && GET_CODE (oldequiv) == REG
6201 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6202 && spill_reg_store[REGNO (oldequiv)]
6203 && GET_CODE (old) == REG
6204 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6205 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6207 delete_output_reload (insn, j, REGNO (oldequiv));
6209 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6210 then load RELOADREG from OLDEQUIV. Note that we cannot use
6211 gen_lowpart_common since it can do the wrong thing when
6212 RELOADREG has a multi-word mode. Note that RELOADREG
6213 must always be a REG here. */
6215 if (GET_MODE (reloadreg) != mode)
6216 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6217 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6218 oldequiv = SUBREG_REG (oldequiv);
6219 if (GET_MODE (oldequiv) != VOIDmode
6220 && mode != GET_MODE (oldequiv))
6221 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6223 /* Switch to the right place to emit the reload insns. */
6224 switch (rl->when_needed)
6227 where = &other_input_reload_insns;
6229 case RELOAD_FOR_INPUT:
6230 where = &input_reload_insns[rl->opnum];
6232 case RELOAD_FOR_INPUT_ADDRESS:
6233 where = &input_address_reload_insns[rl->opnum];
6235 case RELOAD_FOR_INPADDR_ADDRESS:
6236 where = &inpaddr_address_reload_insns[rl->opnum];
6238 case RELOAD_FOR_OUTPUT_ADDRESS:
6239 where = &output_address_reload_insns[rl->opnum];
6241 case RELOAD_FOR_OUTADDR_ADDRESS:
6242 where = &outaddr_address_reload_insns[rl->opnum];
6244 case RELOAD_FOR_OPERAND_ADDRESS:
6245 where = &operand_reload_insns;
6247 case RELOAD_FOR_OPADDR_ADDR:
6248 where = &other_operand_reload_insns;
6250 case RELOAD_FOR_OTHER_ADDRESS:
6251 where = &other_input_address_reload_insns;
6257 push_to_sequence (*where);
6259 /* Auto-increment addresses must be reloaded in a special way. */
6260 if (rl->out && ! rl->out_reg)
6262 /* We are not going to bother supporting the case where a
6263 incremented register can't be copied directly from
6264 OLDEQUIV since this seems highly unlikely. */
6265 if (rl->secondary_in_reload >= 0)
6268 if (reload_inherited[j])
6269 oldequiv = reloadreg;
6271 old = XEXP (rl->in_reg, 0);
6273 if (optimize && GET_CODE (oldequiv) == REG
6274 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6275 && spill_reg_store[REGNO (oldequiv)]
6276 && GET_CODE (old) == REG
6277 && (dead_or_set_p (insn,
6278 spill_reg_stored_to[REGNO (oldequiv)])
6279 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6281 delete_output_reload (insn, j, REGNO (oldequiv));
6283 /* Prevent normal processing of this reload. */
6285 /* Output a special code sequence for this case. */
6286 new_spill_reg_store[REGNO (reloadreg)]
6287 = inc_for_reload (reloadreg, oldequiv, rl->out,
6291 /* If we are reloading a pseudo-register that was set by the previous
6292 insn, see if we can get rid of that pseudo-register entirely
6293 by redirecting the previous insn into our reload register. */
6295 else if (optimize && GET_CODE (old) == REG
6296 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6297 && dead_or_set_p (insn, old)
6298 /* This is unsafe if some other reload
6299 uses the same reg first. */
6300 && ! conflicts_with_override (reloadreg)
6301 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6302 rl->when_needed, old, rl->out, j, 0))
6304 rtx temp = PREV_INSN (insn);
6305 while (temp && GET_CODE (temp) == NOTE)
6306 temp = PREV_INSN (temp);
6308 && GET_CODE (temp) == INSN
6309 && GET_CODE (PATTERN (temp)) == SET
6310 && SET_DEST (PATTERN (temp)) == old
6311 /* Make sure we can access insn_operand_constraint. */
6312 && asm_noperands (PATTERN (temp)) < 0
6313 /* This is unsafe if operand occurs more than once in current
6314 insn. Perhaps some occurrences aren't reloaded. */
6315 && count_occurrences (PATTERN (insn), old, 0) == 1)
6317 rtx old = SET_DEST (PATTERN (temp));
6318 /* Store into the reload register instead of the pseudo. */
6319 SET_DEST (PATTERN (temp)) = reloadreg;
6321 /* Verify that resulting insn is valid. */
6322 extract_insn (temp);
6323 if (constrain_operands (1))
6325 /* If the previous insn is an output reload, the source is
6326 a reload register, and its spill_reg_store entry will
6327 contain the previous destination. This is now
6329 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6330 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6332 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6333 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6336 /* If these are the only uses of the pseudo reg,
6337 pretend for GDB it lives in the reload reg we used. */
6338 if (REG_N_DEATHS (REGNO (old)) == 1
6339 && REG_N_SETS (REGNO (old)) == 1)
6341 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6342 alter_reg (REGNO (old), -1);
6348 SET_DEST (PATTERN (temp)) = old;
6353 /* We can't do that, so output an insn to load RELOADREG. */
6355 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6356 /* If we have a secondary reload, pick up the secondary register
6357 and icode, if any. If OLDEQUIV and OLD are different or
6358 if this is an in-out reload, recompute whether or not we
6359 still need a secondary register and what the icode should
6360 be. If we still need a secondary register and the class or
6361 icode is different, go back to reloading from OLD if using
6362 OLDEQUIV means that we got the wrong type of register. We
6363 cannot have different class or icode due to an in-out reload
6364 because we don't make such reloads when both the input and
6365 output need secondary reload registers. */
6367 if (! special && rl->secondary_in_reload >= 0)
6369 rtx second_reload_reg = 0;
6370 int secondary_reload = rl->secondary_in_reload;
6371 rtx real_oldequiv = oldequiv;
6374 enum insn_code icode;
6376 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6377 and similarly for OLD.
6378 See comments in get_secondary_reload in reload.c. */
6379 /* If it is a pseudo that cannot be replaced with its
6380 equivalent MEM, we must fall back to reload_in, which
6381 will have all the necessary substitutions registered.
6382 Likewise for a pseudo that can't be replaced with its
6383 equivalent constant.
6385 Take extra care for subregs of such pseudos. Note that
6386 we cannot use reg_equiv_mem in this case because it is
6387 not in the right mode. */
6390 if (GET_CODE (tmp) == SUBREG)
6391 tmp = SUBREG_REG (tmp);
6392 if (GET_CODE (tmp) == REG
6393 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6394 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6395 || reg_equiv_constant[REGNO (tmp)] != 0))
6397 if (! reg_equiv_mem[REGNO (tmp)]
6398 || num_not_at_initial_offset
6399 || GET_CODE (oldequiv) == SUBREG)
6400 real_oldequiv = rl->in;
6402 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6406 if (GET_CODE (tmp) == SUBREG)
6407 tmp = SUBREG_REG (tmp);
6408 if (GET_CODE (tmp) == REG
6409 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6410 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6411 || reg_equiv_constant[REGNO (tmp)] != 0))
6413 if (! reg_equiv_mem[REGNO (tmp)]
6414 || num_not_at_initial_offset
6415 || GET_CODE (old) == SUBREG)
6418 real_old = reg_equiv_mem[REGNO (tmp)];
6421 second_reload_reg = rld[secondary_reload].reg_rtx;
6422 icode = rl->secondary_in_icode;
6424 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6425 || (rl->in != 0 && rl->out != 0))
6427 enum reg_class new_class
6428 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6429 mode, real_oldequiv);
6431 if (new_class == NO_REGS)
6432 second_reload_reg = 0;
6435 enum insn_code new_icode;
6436 enum machine_mode new_mode;
6438 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6439 REGNO (second_reload_reg)))
6440 oldequiv = old, real_oldequiv = real_old;
6443 new_icode = reload_in_optab[(int) mode];
6444 if (new_icode != CODE_FOR_nothing
6445 && ((insn_data[(int) new_icode].operand[0].predicate
6446 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6448 || (insn_data[(int) new_icode].operand[1].predicate
6449 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6450 (real_oldequiv, mode)))))
6451 new_icode = CODE_FOR_nothing;
6453 if (new_icode == CODE_FOR_nothing)
6456 new_mode = insn_data[(int) new_icode].operand[2].mode;
6458 if (GET_MODE (second_reload_reg) != new_mode)
6460 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6462 oldequiv = old, real_oldequiv = real_old;
6465 = reload_adjust_reg_for_mode (second_reload_reg,
6472 /* If we still need a secondary reload register, check
6473 to see if it is being used as a scratch or intermediate
6474 register and generate code appropriately. If we need
6475 a scratch register, use REAL_OLDEQUIV since the form of
6476 the insn may depend on the actual address if it is
6479 if (second_reload_reg)
6481 if (icode != CODE_FOR_nothing)
6483 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6484 second_reload_reg));
6489 /* See if we need a scratch register to load the
6490 intermediate register (a tertiary reload). */
6491 enum insn_code tertiary_icode
6492 = rld[secondary_reload].secondary_in_icode;
6494 if (tertiary_icode != CODE_FOR_nothing)
6496 rtx third_reload_reg
6497 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6499 emit_insn ((GEN_FCN (tertiary_icode)
6500 (second_reload_reg, real_oldequiv,
6501 third_reload_reg)));
6504 gen_reload (second_reload_reg, real_oldequiv,
6508 oldequiv = second_reload_reg;
6514 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6516 rtx real_oldequiv = oldequiv;
6518 if ((GET_CODE (oldequiv) == REG
6519 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6520 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6521 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6522 || (GET_CODE (oldequiv) == SUBREG
6523 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6524 && (REGNO (SUBREG_REG (oldequiv))
6525 >= FIRST_PSEUDO_REGISTER)
6526 && ((reg_equiv_memory_loc
6527 [REGNO (SUBREG_REG (oldequiv))] != 0)
6528 || (reg_equiv_constant
6529 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6530 || (CONSTANT_P (oldequiv)
6531 && (PREFERRED_RELOAD_CLASS (oldequiv,
6532 REGNO_REG_CLASS (REGNO (reloadreg)))
6534 real_oldequiv = rl->in;
6535 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6539 if (flag_non_call_exceptions)
6540 copy_eh_notes (insn, get_insns ());
6542 /* End this sequence. */
6543 *where = get_insns ();
6546 /* Update reload_override_in so that delete_address_reloads_1
6547 can see the actual register usage. */
6549 reload_override_in[j] = oldequiv;
6552 /* Generate insns to for the output reload RL, which is for the insn described
6553 by CHAIN and has the number J. */
6555 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6558 rtx reloadreg = rl->reg_rtx;
6559 rtx insn = chain->insn;
6562 enum machine_mode mode = GET_MODE (old);
6565 if (rl->when_needed == RELOAD_OTHER)
6568 push_to_sequence (output_reload_insns[rl->opnum]);
6570 /* Determine the mode to reload in.
6571 See comments above (for input reloading). */
6573 if (mode == VOIDmode)
6575 /* VOIDmode should never happen for an output. */
6576 if (asm_noperands (PATTERN (insn)) < 0)
6577 /* It's the compiler's fault. */
6578 fatal_insn ("VOIDmode on an output", insn);
6579 error_for_asm (insn, "output operand is constant in `asm'");
6580 /* Prevent crash--use something we know is valid. */
6582 old = gen_rtx_REG (mode, REGNO (reloadreg));
6585 if (GET_MODE (reloadreg) != mode)
6586 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6588 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6590 /* If we need two reload regs, set RELOADREG to the intermediate
6591 one, since it will be stored into OLD. We might need a secondary
6592 register only for an input reload, so check again here. */
6594 if (rl->secondary_out_reload >= 0)
6598 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6599 && reg_equiv_mem[REGNO (old)] != 0)
6600 real_old = reg_equiv_mem[REGNO (old)];
6602 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6606 rtx second_reloadreg = reloadreg;
6607 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6609 /* See if RELOADREG is to be used as a scratch register
6610 or as an intermediate register. */
6611 if (rl->secondary_out_icode != CODE_FOR_nothing)
6613 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6614 (real_old, second_reloadreg, reloadreg)));
6619 /* See if we need both a scratch and intermediate reload
6622 int secondary_reload = rl->secondary_out_reload;
6623 enum insn_code tertiary_icode
6624 = rld[secondary_reload].secondary_out_icode;
6626 if (GET_MODE (reloadreg) != mode)
6627 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6629 if (tertiary_icode != CODE_FOR_nothing)
6632 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6635 /* Copy primary reload reg to secondary reload reg.
6636 (Note that these have been swapped above, then
6637 secondary reload reg to OLD using our insn.) */
6639 /* If REAL_OLD is a paradoxical SUBREG, remove it
6640 and try to put the opposite SUBREG on
6642 if (GET_CODE (real_old) == SUBREG
6643 && (GET_MODE_SIZE (GET_MODE (real_old))
6644 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6645 && 0 != (tem = gen_lowpart_common
6646 (GET_MODE (SUBREG_REG (real_old)),
6648 real_old = SUBREG_REG (real_old), reloadreg = tem;
6650 gen_reload (reloadreg, second_reloadreg,
6651 rl->opnum, rl->when_needed);
6652 emit_insn ((GEN_FCN (tertiary_icode)
6653 (real_old, reloadreg, third_reloadreg)));
6658 /* Copy between the reload regs here and then to
6661 gen_reload (reloadreg, second_reloadreg,
6662 rl->opnum, rl->when_needed);
6668 /* Output the last reload insn. */
6673 /* Don't output the last reload if OLD is not the dest of
6674 INSN and is in the src and is clobbered by INSN. */
6675 if (! flag_expensive_optimizations
6676 || GET_CODE (old) != REG
6677 || !(set = single_set (insn))
6678 || rtx_equal_p (old, SET_DEST (set))
6679 || !reg_mentioned_p (old, SET_SRC (set))
6680 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6681 gen_reload (old, reloadreg, rl->opnum,
6685 /* Look at all insns we emitted, just to be safe. */
6686 for (p = get_insns (); p; p = NEXT_INSN (p))
6689 rtx pat = PATTERN (p);
6691 /* If this output reload doesn't come from a spill reg,
6692 clear any memory of reloaded copies of the pseudo reg.
6693 If this output reload comes from a spill reg,
6694 reg_has_output_reload will make this do nothing. */
6695 note_stores (pat, forget_old_reloads_1, NULL);
6697 if (reg_mentioned_p (rl->reg_rtx, pat))
6699 rtx set = single_set (insn);
6700 if (reload_spill_index[j] < 0
6702 && SET_SRC (set) == rl->reg_rtx)
6704 int src = REGNO (SET_SRC (set));
6706 reload_spill_index[j] = src;
6707 SET_HARD_REG_BIT (reg_is_output_reload, src);
6708 if (find_regno_note (insn, REG_DEAD, src))
6709 SET_HARD_REG_BIT (reg_reloaded_died, src);
6711 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6713 int s = rl->secondary_out_reload;
6714 set = single_set (p);
6715 /* If this reload copies only to the secondary reload
6716 register, the secondary reload does the actual
6718 if (s >= 0 && set == NULL_RTX)
6719 /* We can't tell what function the secondary reload
6720 has and where the actual store to the pseudo is
6721 made; leave new_spill_reg_store alone. */
6724 && SET_SRC (set) == rl->reg_rtx
6725 && SET_DEST (set) == rld[s].reg_rtx)
6727 /* Usually the next instruction will be the
6728 secondary reload insn; if we can confirm
6729 that it is, setting new_spill_reg_store to
6730 that insn will allow an extra optimization. */
6731 rtx s_reg = rld[s].reg_rtx;
6732 rtx next = NEXT_INSN (p);
6733 rld[s].out = rl->out;
6734 rld[s].out_reg = rl->out_reg;
6735 set = single_set (next);
6736 if (set && SET_SRC (set) == s_reg
6737 && ! new_spill_reg_store[REGNO (s_reg)])
6739 SET_HARD_REG_BIT (reg_is_output_reload,
6741 new_spill_reg_store[REGNO (s_reg)] = next;
6745 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6750 if (rl->when_needed == RELOAD_OTHER)
6752 emit_insn (other_output_reload_insns[rl->opnum]);
6753 other_output_reload_insns[rl->opnum] = get_insns ();
6756 output_reload_insns[rl->opnum] = get_insns ();
6758 if (flag_non_call_exceptions)
6759 copy_eh_notes (insn, get_insns ());
6764 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6765 and has the number J. */
6767 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6769 rtx insn = chain->insn;
6770 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6771 ? rl->in_reg : rl->in);
6774 /* AUTO_INC reloads need to be handled even if inherited. We got an
6775 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6776 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6777 && ! rtx_equal_p (rl->reg_rtx, old)
6778 && rl->reg_rtx != 0)
6779 emit_input_reload_insns (chain, rld + j, old, j);
6781 /* When inheriting a wider reload, we have a MEM in rl->in,
6782 e.g. inheriting a SImode output reload for
6783 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6784 if (optimize && reload_inherited[j] && rl->in
6785 && GET_CODE (rl->in) == MEM
6786 && GET_CODE (rl->in_reg) == MEM
6787 && reload_spill_index[j] >= 0
6788 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6789 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6791 /* If we are reloading a register that was recently stored in with an
6792 output-reload, see if we can prove there was
6793 actually no need to store the old value in it. */
6796 && (reload_inherited[j] || reload_override_in[j])
6798 && GET_CODE (rl->reg_rtx) == REG
6799 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6801 /* There doesn't seem to be any reason to restrict this to pseudos
6802 and doing so loses in the case where we are copying from a
6803 register of the wrong class. */
6804 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6805 >= FIRST_PSEUDO_REGISTER)
6807 /* The insn might have already some references to stackslots
6808 replaced by MEMs, while reload_out_reg still names the
6810 && (dead_or_set_p (insn,
6811 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6812 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6814 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6817 /* Do output reloading for reload RL, which is for the insn described by
6818 CHAIN and has the number J.
6819 ??? At some point we need to support handling output reloads of
6820 JUMP_INSNs or insns that set cc0. */
6822 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6825 rtx insn = chain->insn;
6826 /* If this is an output reload that stores something that is
6827 not loaded in this same reload, see if we can eliminate a previous
6829 rtx pseudo = rl->out_reg;
6833 && GET_CODE (pseudo) == REG
6834 && ! rtx_equal_p (rl->in_reg, pseudo)
6835 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6836 && reg_last_reload_reg[REGNO (pseudo)])
6838 int pseudo_no = REGNO (pseudo);
6839 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6841 /* We don't need to test full validity of last_regno for
6842 inherit here; we only want to know if the store actually
6843 matches the pseudo. */
6844 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6845 && reg_reloaded_contents[last_regno] == pseudo_no
6846 && spill_reg_store[last_regno]
6847 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6848 delete_output_reload (insn, j, last_regno);
6853 || rl->reg_rtx == old
6854 || rl->reg_rtx == 0)
6857 /* An output operand that dies right away does need a reload,
6858 but need not be copied from it. Show the new location in the
6860 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6861 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6863 XEXP (note, 0) = rl->reg_rtx;
6866 /* Likewise for a SUBREG of an operand that dies. */
6867 else if (GET_CODE (old) == SUBREG
6868 && GET_CODE (SUBREG_REG (old)) == REG
6869 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6872 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6876 else if (GET_CODE (old) == SCRATCH)
6877 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6878 but we don't want to make an output reload. */
6881 /* If is a JUMP_INSN, we can't support output reloads yet. */
6882 if (GET_CODE (insn) == JUMP_INSN)
6885 emit_output_reload_insns (chain, rld + j, j);
6888 /* Output insns to reload values in and out of the chosen reload regs. */
6891 emit_reload_insns (struct insn_chain *chain)
6893 rtx insn = chain->insn;
6897 CLEAR_HARD_REG_SET (reg_reloaded_died);
6899 for (j = 0; j < reload_n_operands; j++)
6900 input_reload_insns[j] = input_address_reload_insns[j]
6901 = inpaddr_address_reload_insns[j]
6902 = output_reload_insns[j] = output_address_reload_insns[j]
6903 = outaddr_address_reload_insns[j]
6904 = other_output_reload_insns[j] = 0;
6905 other_input_address_reload_insns = 0;
6906 other_input_reload_insns = 0;
6907 operand_reload_insns = 0;
6908 other_operand_reload_insns = 0;
6910 /* Dump reloads into the dump file. */
6913 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6914 debug_reload_to_stream (rtl_dump_file);
6917 /* Now output the instructions to copy the data into and out of the
6918 reload registers. Do these in the order that the reloads were reported,
6919 since reloads of base and index registers precede reloads of operands
6920 and the operands may need the base and index registers reloaded. */
6922 for (j = 0; j < n_reloads; j++)
6925 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6926 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6928 do_input_reload (chain, rld + j, j);
6929 do_output_reload (chain, rld + j, j);
6932 /* Now write all the insns we made for reloads in the order expected by
6933 the allocation functions. Prior to the insn being reloaded, we write
6934 the following reloads:
6936 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6938 RELOAD_OTHER reloads.
6940 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6941 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6942 RELOAD_FOR_INPUT reload for the operand.
6944 RELOAD_FOR_OPADDR_ADDRS reloads.
6946 RELOAD_FOR_OPERAND_ADDRESS reloads.
6948 After the insn being reloaded, we write the following:
6950 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6951 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6952 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6953 reloads for the operand. The RELOAD_OTHER output reloads are
6954 output in descending order by reload number. */
6956 emit_insn_before (other_input_address_reload_insns, insn);
6957 emit_insn_before (other_input_reload_insns, insn);
6959 for (j = 0; j < reload_n_operands; j++)
6961 emit_insn_before (inpaddr_address_reload_insns[j], insn);
6962 emit_insn_before (input_address_reload_insns[j], insn);
6963 emit_insn_before (input_reload_insns[j], insn);
6966 emit_insn_before (other_operand_reload_insns, insn);
6967 emit_insn_before (operand_reload_insns, insn);
6969 for (j = 0; j < reload_n_operands; j++)
6971 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
6972 x = emit_insn_after (output_address_reload_insns[j], x);
6973 x = emit_insn_after (output_reload_insns[j], x);
6974 emit_insn_after (other_output_reload_insns[j], x);
6977 /* For all the spill regs newly reloaded in this instruction,
6978 record what they were reloaded from, so subsequent instructions
6979 can inherit the reloads.
6981 Update spill_reg_store for the reloads of this insn.
6982 Copy the elements that were updated in the loop above. */
6984 for (j = 0; j < n_reloads; j++)
6986 int r = reload_order[j];
6987 int i = reload_spill_index[r];
6989 /* If this is a non-inherited input reload from a pseudo, we must
6990 clear any memory of a previous store to the same pseudo. Only do
6991 something if there will not be an output reload for the pseudo
6993 if (rld[r].in_reg != 0
6994 && ! (reload_inherited[r] || reload_override_in[r]))
6996 rtx reg = rld[r].in_reg;
6998 if (GET_CODE (reg) == SUBREG)
6999 reg = SUBREG_REG (reg);
7001 if (GET_CODE (reg) == REG
7002 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7003 && ! reg_has_output_reload[REGNO (reg)])
7005 int nregno = REGNO (reg);
7007 if (reg_last_reload_reg[nregno])
7009 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7011 if (reg_reloaded_contents[last_regno] == nregno)
7012 spill_reg_store[last_regno] = 0;
7017 /* I is nonneg if this reload used a register.
7018 If rld[r].reg_rtx is 0, this is an optional reload
7019 that we opted to ignore. */
7021 if (i >= 0 && rld[r].reg_rtx != 0)
7023 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7025 int part_reaches_end = 0;
7026 int all_reaches_end = 1;
7028 /* For a multi register reload, we need to check if all or part
7029 of the value lives to the end. */
7030 for (k = 0; k < nr; k++)
7032 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7033 rld[r].when_needed))
7034 part_reaches_end = 1;
7036 all_reaches_end = 0;
7039 /* Ignore reloads that don't reach the end of the insn in
7041 if (all_reaches_end)
7043 /* First, clear out memory of what used to be in this spill reg.
7044 If consecutive registers are used, clear them all. */
7046 for (k = 0; k < nr; k++)
7047 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7049 /* Maybe the spill reg contains a copy of reload_out. */
7051 && (GET_CODE (rld[r].out) == REG
7055 || GET_CODE (rld[r].out_reg) == REG))
7057 rtx out = (GET_CODE (rld[r].out) == REG
7061 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7062 int nregno = REGNO (out);
7063 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7064 : HARD_REGNO_NREGS (nregno,
7065 GET_MODE (rld[r].reg_rtx)));
7067 spill_reg_store[i] = new_spill_reg_store[i];
7068 spill_reg_stored_to[i] = out;
7069 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7071 /* If NREGNO is a hard register, it may occupy more than
7072 one register. If it does, say what is in the
7073 rest of the registers assuming that both registers
7074 agree on how many words the object takes. If not,
7075 invalidate the subsequent registers. */
7077 if (nregno < FIRST_PSEUDO_REGISTER)
7078 for (k = 1; k < nnr; k++)
7079 reg_last_reload_reg[nregno + k]
7081 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7084 /* Now do the inverse operation. */
7085 for (k = 0; k < nr; k++)
7087 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7088 reg_reloaded_contents[i + k]
7089 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7092 reg_reloaded_insn[i + k] = insn;
7093 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7097 /* Maybe the spill reg contains a copy of reload_in. Only do
7098 something if there will not be an output reload for
7099 the register being reloaded. */
7100 else if (rld[r].out_reg == 0
7102 && ((GET_CODE (rld[r].in) == REG
7103 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7104 && ! reg_has_output_reload[REGNO (rld[r].in)])
7105 || (GET_CODE (rld[r].in_reg) == REG
7106 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7107 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7112 if (GET_CODE (rld[r].in) == REG
7113 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7114 nregno = REGNO (rld[r].in);
7115 else if (GET_CODE (rld[r].in_reg) == REG)
7116 nregno = REGNO (rld[r].in_reg);
7118 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7120 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7121 : HARD_REGNO_NREGS (nregno,
7122 GET_MODE (rld[r].reg_rtx)));
7124 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7126 if (nregno < FIRST_PSEUDO_REGISTER)
7127 for (k = 1; k < nnr; k++)
7128 reg_last_reload_reg[nregno + k]
7130 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7133 /* Unless we inherited this reload, show we haven't
7134 recently done a store.
7135 Previous stores of inherited auto_inc expressions
7136 also have to be discarded. */
7137 if (! reload_inherited[r]
7138 || (rld[r].out && ! rld[r].out_reg))
7139 spill_reg_store[i] = 0;
7141 for (k = 0; k < nr; k++)
7143 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7144 reg_reloaded_contents[i + k]
7145 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7148 reg_reloaded_insn[i + k] = insn;
7149 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7154 /* However, if part of the reload reaches the end, then we must
7155 invalidate the old info for the part that survives to the end. */
7156 else if (part_reaches_end)
7158 for (k = 0; k < nr; k++)
7159 if (reload_reg_reaches_end_p (i + k,
7161 rld[r].when_needed))
7162 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7166 /* The following if-statement was #if 0'd in 1.34 (or before...).
7167 It's reenabled in 1.35 because supposedly nothing else
7168 deals with this problem. */
7170 /* If a register gets output-reloaded from a non-spill register,
7171 that invalidates any previous reloaded copy of it.
7172 But forget_old_reloads_1 won't get to see it, because
7173 it thinks only about the original insn. So invalidate it here. */
7174 if (i < 0 && rld[r].out != 0
7175 && (GET_CODE (rld[r].out) == REG
7176 || (GET_CODE (rld[r].out) == MEM
7177 && GET_CODE (rld[r].out_reg) == REG)))
7179 rtx out = (GET_CODE (rld[r].out) == REG
7180 ? rld[r].out : rld[r].out_reg);
7181 int nregno = REGNO (out);
7182 if (nregno >= FIRST_PSEUDO_REGISTER)
7184 rtx src_reg, store_insn = NULL_RTX;
7186 reg_last_reload_reg[nregno] = 0;
7188 /* If we can find a hard register that is stored, record
7189 the storing insn so that we may delete this insn with
7190 delete_output_reload. */
7191 src_reg = rld[r].reg_rtx;
7193 /* If this is an optional reload, try to find the source reg
7194 from an input reload. */
7197 rtx set = single_set (insn);
7198 if (set && SET_DEST (set) == rld[r].out)
7202 src_reg = SET_SRC (set);
7204 for (k = 0; k < n_reloads; k++)
7206 if (rld[k].in == src_reg)
7208 src_reg = rld[k].reg_rtx;
7215 store_insn = new_spill_reg_store[REGNO (src_reg)];
7216 if (src_reg && GET_CODE (src_reg) == REG
7217 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7219 int src_regno = REGNO (src_reg);
7220 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7221 /* The place where to find a death note varies with
7222 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7223 necessarily checked exactly in the code that moves
7224 notes, so just check both locations. */
7225 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7226 if (! note && store_insn)
7227 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7230 spill_reg_store[src_regno + nr] = store_insn;
7231 spill_reg_stored_to[src_regno + nr] = out;
7232 reg_reloaded_contents[src_regno + nr] = nregno;
7233 reg_reloaded_insn[src_regno + nr] = store_insn;
7234 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7235 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7236 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7238 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7240 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7242 reg_last_reload_reg[nregno] = src_reg;
7247 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7249 while (num_regs-- > 0)
7250 reg_last_reload_reg[nregno + num_regs] = 0;
7254 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7257 /* Emit code to perform a reload from IN (which may be a reload register) to
7258 OUT (which may also be a reload register). IN or OUT is from operand
7259 OPNUM with reload type TYPE.
7261 Returns first insn emitted. */
7264 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7266 rtx last = get_last_insn ();
7269 /* If IN is a paradoxical SUBREG, remove it and try to put the
7270 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7271 if (GET_CODE (in) == SUBREG
7272 && (GET_MODE_SIZE (GET_MODE (in))
7273 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7274 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7275 in = SUBREG_REG (in), out = tem;
7276 else if (GET_CODE (out) == SUBREG
7277 && (GET_MODE_SIZE (GET_MODE (out))
7278 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7279 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7280 out = SUBREG_REG (out), in = tem;
7282 /* How to do this reload can get quite tricky. Normally, we are being
7283 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7284 register that didn't get a hard register. In that case we can just
7285 call emit_move_insn.
7287 We can also be asked to reload a PLUS that adds a register or a MEM to
7288 another register, constant or MEM. This can occur during frame pointer
7289 elimination and while reloading addresses. This case is handled by
7290 trying to emit a single insn to perform the add. If it is not valid,
7291 we use a two insn sequence.
7293 Finally, we could be called to handle an 'o' constraint by putting
7294 an address into a register. In that case, we first try to do this
7295 with a named pattern of "reload_load_address". If no such pattern
7296 exists, we just emit a SET insn and hope for the best (it will normally
7297 be valid on machines that use 'o').
7299 This entire process is made complex because reload will never
7300 process the insns we generate here and so we must ensure that
7301 they will fit their constraints and also by the fact that parts of
7302 IN might be being reloaded separately and replaced with spill registers.
7303 Because of this, we are, in some sense, just guessing the right approach
7304 here. The one listed above seems to work.
7306 ??? At some point, this whole thing needs to be rethought. */
7308 if (GET_CODE (in) == PLUS
7309 && (GET_CODE (XEXP (in, 0)) == REG
7310 || GET_CODE (XEXP (in, 0)) == SUBREG
7311 || GET_CODE (XEXP (in, 0)) == MEM)
7312 && (GET_CODE (XEXP (in, 1)) == REG
7313 || GET_CODE (XEXP (in, 1)) == SUBREG
7314 || CONSTANT_P (XEXP (in, 1))
7315 || GET_CODE (XEXP (in, 1)) == MEM))
7317 /* We need to compute the sum of a register or a MEM and another
7318 register, constant, or MEM, and put it into the reload
7319 register. The best possible way of doing this is if the machine
7320 has a three-operand ADD insn that accepts the required operands.
7322 The simplest approach is to try to generate such an insn and see if it
7323 is recognized and matches its constraints. If so, it can be used.
7325 It might be better not to actually emit the insn unless it is valid,
7326 but we need to pass the insn as an operand to `recog' and
7327 `extract_insn' and it is simpler to emit and then delete the insn if
7328 not valid than to dummy things up. */
7330 rtx op0, op1, tem, insn;
7333 op0 = find_replacement (&XEXP (in, 0));
7334 op1 = find_replacement (&XEXP (in, 1));
7336 /* Since constraint checking is strict, commutativity won't be
7337 checked, so we need to do that here to avoid spurious failure
7338 if the add instruction is two-address and the second operand
7339 of the add is the same as the reload reg, which is frequently
7340 the case. If the insn would be A = B + A, rearrange it so
7341 it will be A = A + B as constrain_operands expects. */
7343 if (GET_CODE (XEXP (in, 1)) == REG
7344 && REGNO (out) == REGNO (XEXP (in, 1)))
7345 tem = op0, op0 = op1, op1 = tem;
7347 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7348 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7350 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7351 code = recog_memoized (insn);
7355 extract_insn (insn);
7356 /* We want constrain operands to treat this insn strictly in
7357 its validity determination, i.e., the way it would after reload
7359 if (constrain_operands (1))
7363 delete_insns_since (last);
7365 /* If that failed, we must use a conservative two-insn sequence.
7367 Use a move to copy one operand into the reload register. Prefer
7368 to reload a constant, MEM or pseudo since the move patterns can
7369 handle an arbitrary operand. If OP1 is not a constant, MEM or
7370 pseudo and OP1 is not a valid operand for an add instruction, then
7373 After reloading one of the operands into the reload register, add
7374 the reload register to the output register.
7376 If there is another way to do this for a specific machine, a
7377 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7380 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7382 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7383 || (GET_CODE (op1) == REG
7384 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7385 || (code != CODE_FOR_nothing
7386 && ! ((*insn_data[code].operand[2].predicate)
7387 (op1, insn_data[code].operand[2].mode))))
7388 tem = op0, op0 = op1, op1 = tem;
7390 gen_reload (out, op0, opnum, type);
7392 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7393 This fixes a problem on the 32K where the stack pointer cannot
7394 be used as an operand of an add insn. */
7396 if (rtx_equal_p (op0, op1))
7399 insn = emit_insn (gen_add2_insn (out, op1));
7401 /* If that failed, copy the address register to the reload register.
7402 Then add the constant to the reload register. */
7404 code = recog_memoized (insn);
7408 extract_insn (insn);
7409 /* We want constrain operands to treat this insn strictly in
7410 its validity determination, i.e., the way it would after reload
7412 if (constrain_operands (1))
7414 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7416 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7421 delete_insns_since (last);
7423 gen_reload (out, op1, opnum, type);
7424 insn = emit_insn (gen_add2_insn (out, op0));
7425 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7428 #ifdef SECONDARY_MEMORY_NEEDED
7429 /* If we need a memory location to do the move, do it that way. */
7430 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7431 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7432 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7433 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7434 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7435 REGNO_REG_CLASS (reg_or_subregno (out)),
7438 /* Get the memory to use and rewrite both registers to its mode. */
7439 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7441 if (GET_MODE (loc) != GET_MODE (out))
7442 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7444 if (GET_MODE (loc) != GET_MODE (in))
7445 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7447 gen_reload (loc, in, opnum, type);
7448 gen_reload (out, loc, opnum, type);
7452 /* If IN is a simple operand, use gen_move_insn. */
7453 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7454 emit_insn (gen_move_insn (out, in));
7456 #ifdef HAVE_reload_load_address
7457 else if (HAVE_reload_load_address)
7458 emit_insn (gen_reload_load_address (out, in));
7461 /* Otherwise, just write (set OUT IN) and hope for the best. */
7463 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7465 /* Return the first insn emitted.
7466 We can not just return get_last_insn, because there may have
7467 been multiple instructions emitted. Also note that gen_move_insn may
7468 emit more than one insn itself, so we can not assume that there is one
7469 insn emitted per emit_insn_before call. */
7471 return last ? NEXT_INSN (last) : get_insns ();
7474 /* Delete a previously made output-reload whose result we now believe
7475 is not needed. First we double-check.
7477 INSN is the insn now being processed.
7478 LAST_RELOAD_REG is the hard register number for which we want to delete
7479 the last output reload.
7480 J is the reload-number that originally used REG. The caller has made
7481 certain that reload J doesn't use REG any longer for input. */
7484 delete_output_reload (rtx insn, int j, int last_reload_reg)
7486 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7487 rtx reg = spill_reg_stored_to[last_reload_reg];
7490 int n_inherited = 0;
7494 /* It is possible that this reload has been only used to set another reload
7495 we eliminated earlier and thus deleted this instruction too. */
7496 if (INSN_DELETED_P (output_reload_insn))
7499 /* Get the raw pseudo-register referred to. */
7501 while (GET_CODE (reg) == SUBREG)
7502 reg = SUBREG_REG (reg);
7503 substed = reg_equiv_memory_loc[REGNO (reg)];
7505 /* This is unsafe if the operand occurs more often in the current
7506 insn than it is inherited. */
7507 for (k = n_reloads - 1; k >= 0; k--)
7509 rtx reg2 = rld[k].in;
7512 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7513 reg2 = rld[k].in_reg;
7515 if (rld[k].out && ! rld[k].out_reg)
7516 reg2 = XEXP (rld[k].in_reg, 0);
7518 while (GET_CODE (reg2) == SUBREG)
7519 reg2 = SUBREG_REG (reg2);
7520 if (rtx_equal_p (reg2, reg))
7522 if (reload_inherited[k] || reload_override_in[k] || k == j)
7525 reg2 = rld[k].out_reg;
7528 while (GET_CODE (reg2) == SUBREG)
7529 reg2 = XEXP (reg2, 0);
7530 if (rtx_equal_p (reg2, reg))
7537 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7539 n_occurrences += count_occurrences (PATTERN (insn),
7540 eliminate_regs (substed, 0,
7542 if (n_occurrences > n_inherited)
7545 /* If the pseudo-reg we are reloading is no longer referenced
7546 anywhere between the store into it and here,
7547 and no jumps or labels intervene, then the value can get
7548 here through the reload reg alone.
7549 Otherwise, give up--return. */
7550 for (i1 = NEXT_INSN (output_reload_insn);
7551 i1 != insn; i1 = NEXT_INSN (i1))
7553 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7555 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7556 && reg_mentioned_p (reg, PATTERN (i1)))
7558 /* If this is USE in front of INSN, we only have to check that
7559 there are no more references than accounted for by inheritance. */
7560 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7562 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7563 i1 = NEXT_INSN (i1);
7565 if (n_occurrences <= n_inherited && i1 == insn)
7571 /* We will be deleting the insn. Remove the spill reg information. */
7572 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7574 spill_reg_store[last_reload_reg + k] = 0;
7575 spill_reg_stored_to[last_reload_reg + k] = 0;
7578 /* The caller has already checked that REG dies or is set in INSN.
7579 It has also checked that we are optimizing, and thus some
7580 inaccuracies in the debugging information are acceptable.
7581 So we could just delete output_reload_insn. But in some cases
7582 we can improve the debugging information without sacrificing
7583 optimization - maybe even improving the code: See if the pseudo
7584 reg has been completely replaced with reload regs. If so, delete
7585 the store insn and forget we had a stack slot for the pseudo. */
7586 if (rld[j].out != rld[j].in
7587 && REG_N_DEATHS (REGNO (reg)) == 1
7588 && REG_N_SETS (REGNO (reg)) == 1
7589 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7590 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7594 /* We know that it was used only between here and the beginning of
7595 the current basic block. (We also know that the last use before
7596 INSN was the output reload we are thinking of deleting, but never
7597 mind that.) Search that range; see if any ref remains. */
7598 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7600 rtx set = single_set (i2);
7602 /* Uses which just store in the pseudo don't count,
7603 since if they are the only uses, they are dead. */
7604 if (set != 0 && SET_DEST (set) == reg)
7606 if (GET_CODE (i2) == CODE_LABEL
7607 || GET_CODE (i2) == JUMP_INSN)
7609 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7610 && reg_mentioned_p (reg, PATTERN (i2)))
7612 /* Some other ref remains; just delete the output reload we
7614 delete_address_reloads (output_reload_insn, insn);
7615 delete_insn (output_reload_insn);
7620 /* Delete the now-dead stores into this pseudo. Note that this
7621 loop also takes care of deleting output_reload_insn. */
7622 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7624 rtx set = single_set (i2);
7626 if (set != 0 && SET_DEST (set) == reg)
7628 delete_address_reloads (i2, insn);
7631 if (GET_CODE (i2) == CODE_LABEL
7632 || GET_CODE (i2) == JUMP_INSN)
7636 /* For the debugging info, say the pseudo lives in this reload reg. */
7637 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7638 alter_reg (REGNO (reg), -1);
7642 delete_address_reloads (output_reload_insn, insn);
7643 delete_insn (output_reload_insn);
7647 /* We are going to delete DEAD_INSN. Recursively delete loads of
7648 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7649 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7651 delete_address_reloads (rtx dead_insn, rtx current_insn)
7653 rtx set = single_set (dead_insn);
7654 rtx set2, dst, prev, next;
7657 rtx dst = SET_DEST (set);
7658 if (GET_CODE (dst) == MEM)
7659 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7661 /* If we deleted the store from a reloaded post_{in,de}c expression,
7662 we can delete the matching adds. */
7663 prev = PREV_INSN (dead_insn);
7664 next = NEXT_INSN (dead_insn);
7665 if (! prev || ! next)
7667 set = single_set (next);
7668 set2 = single_set (prev);
7670 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7671 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7672 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7674 dst = SET_DEST (set);
7675 if (! rtx_equal_p (dst, SET_DEST (set2))
7676 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7677 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7678 || (INTVAL (XEXP (SET_SRC (set), 1))
7679 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7681 delete_related_insns (prev);
7682 delete_related_insns (next);
7685 /* Subfunction of delete_address_reloads: process registers found in X. */
7687 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7689 rtx prev, set, dst, i2;
7691 enum rtx_code code = GET_CODE (x);
7695 const char *fmt = GET_RTX_FORMAT (code);
7696 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7699 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7700 else if (fmt[i] == 'E')
7702 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7703 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7710 if (spill_reg_order[REGNO (x)] < 0)
7713 /* Scan backwards for the insn that sets x. This might be a way back due
7715 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7717 code = GET_CODE (prev);
7718 if (code == CODE_LABEL || code == JUMP_INSN)
7720 if (GET_RTX_CLASS (code) != 'i')
7722 if (reg_set_p (x, PATTERN (prev)))
7724 if (reg_referenced_p (x, PATTERN (prev)))
7727 if (! prev || INSN_UID (prev) < reload_first_uid)
7729 /* Check that PREV only sets the reload register. */
7730 set = single_set (prev);
7733 dst = SET_DEST (set);
7734 if (GET_CODE (dst) != REG
7735 || ! rtx_equal_p (dst, x))
7737 if (! reg_set_p (dst, PATTERN (dead_insn)))
7739 /* Check if DST was used in a later insn -
7740 it might have been inherited. */
7741 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7743 if (GET_CODE (i2) == CODE_LABEL)
7747 if (reg_referenced_p (dst, PATTERN (i2)))
7749 /* If there is a reference to the register in the current insn,
7750 it might be loaded in a non-inherited reload. If no other
7751 reload uses it, that means the register is set before
7753 if (i2 == current_insn)
7755 for (j = n_reloads - 1; j >= 0; j--)
7756 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7757 || reload_override_in[j] == dst)
7759 for (j = n_reloads - 1; j >= 0; j--)
7760 if (rld[j].in && rld[j].reg_rtx == dst)
7767 if (GET_CODE (i2) == JUMP_INSN)
7769 /* If DST is still live at CURRENT_INSN, check if it is used for
7770 any reload. Note that even if CURRENT_INSN sets DST, we still
7771 have to check the reloads. */
7772 if (i2 == current_insn)
7774 for (j = n_reloads - 1; j >= 0; j--)
7775 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7776 || reload_override_in[j] == dst)
7778 /* ??? We can't finish the loop here, because dst might be
7779 allocated to a pseudo in this block if no reload in this
7780 block needs any of the classes containing DST - see
7781 spill_hard_reg. There is no easy way to tell this, so we
7782 have to scan till the end of the basic block. */
7784 if (reg_set_p (dst, PATTERN (i2)))
7788 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7789 reg_reloaded_contents[REGNO (dst)] = -1;
7793 /* Output reload-insns to reload VALUE into RELOADREG.
7794 VALUE is an autoincrement or autodecrement RTX whose operand
7795 is a register or memory location;
7796 so reloading involves incrementing that location.
7797 IN is either identical to VALUE, or some cheaper place to reload from.
7799 INC_AMOUNT is the number to increment or decrement by (always positive).
7800 This cannot be deduced from VALUE.
7802 Return the instruction that stores into RELOADREG. */
7805 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7807 /* REG or MEM to be copied and incremented. */
7808 rtx incloc = XEXP (value, 0);
7809 /* Nonzero if increment after copying. */
7810 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7816 rtx real_in = in == value ? XEXP (in, 0) : in;
7818 /* No hard register is equivalent to this register after
7819 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7820 we could inc/dec that register as well (maybe even using it for
7821 the source), but I'm not sure it's worth worrying about. */
7822 if (GET_CODE (incloc) == REG)
7823 reg_last_reload_reg[REGNO (incloc)] = 0;
7825 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7826 inc_amount = -inc_amount;
7828 inc = GEN_INT (inc_amount);
7830 /* If this is post-increment, first copy the location to the reload reg. */
7831 if (post && real_in != reloadreg)
7832 emit_insn (gen_move_insn (reloadreg, real_in));
7836 /* See if we can directly increment INCLOC. Use a method similar to
7837 that in gen_reload. */
7839 last = get_last_insn ();
7840 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7841 gen_rtx_PLUS (GET_MODE (incloc),
7844 code = recog_memoized (add_insn);
7847 extract_insn (add_insn);
7848 if (constrain_operands (1))
7850 /* If this is a pre-increment and we have incremented the value
7851 where it lives, copy the incremented value to RELOADREG to
7852 be used as an address. */
7855 emit_insn (gen_move_insn (reloadreg, incloc));
7860 delete_insns_since (last);
7863 /* If couldn't do the increment directly, must increment in RELOADREG.
7864 The way we do this depends on whether this is pre- or post-increment.
7865 For pre-increment, copy INCLOC to the reload register, increment it
7866 there, then save back. */
7870 if (in != reloadreg)
7871 emit_insn (gen_move_insn (reloadreg, real_in));
7872 emit_insn (gen_add2_insn (reloadreg, inc));
7873 store = emit_insn (gen_move_insn (incloc, reloadreg));
7878 Because this might be a jump insn or a compare, and because RELOADREG
7879 may not be available after the insn in an input reload, we must do
7880 the incrementation before the insn being reloaded for.
7882 We have already copied IN to RELOADREG. Increment the copy in
7883 RELOADREG, save that back, then decrement RELOADREG so it has
7884 the original value. */
7886 emit_insn (gen_add2_insn (reloadreg, inc));
7887 store = emit_insn (gen_move_insn (incloc, reloadreg));
7888 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7896 add_auto_inc_notes (rtx insn, rtx x)
7898 enum rtx_code code = GET_CODE (x);
7902 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7905 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7909 /* Scan all the operand sub-expressions. */
7910 fmt = GET_RTX_FORMAT (code);
7911 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7914 add_auto_inc_notes (insn, XEXP (x, i));
7915 else if (fmt[i] == 'E')
7916 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7917 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7922 /* Copy EH notes from an insn to its reloads. */
7924 copy_eh_notes (rtx insn, rtx x)
7926 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7929 for (; x != 0; x = NEXT_INSN (x))
7931 if (may_trap_p (PATTERN (x)))
7933 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7939 /* This is used by reload pass, that does emit some instructions after
7940 abnormal calls moving basic block end, but in fact it wants to emit
7941 them on the edge. Looks for abnormal call edges, find backward the
7942 proper call and fix the damage.
7944 Similar handle instructions throwing exceptions internally. */
7946 fixup_abnormal_edges (void)
7948 bool inserted = false;
7955 /* Look for cases we are interested in - calls or instructions causing
7957 for (e = bb->succ; e; e = e->succ_next)
7959 if (e->flags & EDGE_ABNORMAL_CALL)
7961 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
7962 == (EDGE_ABNORMAL | EDGE_EH))
7965 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
7967 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
7969 for (e = bb->succ; e; e = e->succ_next)
7970 if (e->flags & EDGE_FALLTHRU)
7972 /* Get past the new insns generated. Allow notes, as the insns may
7973 be already deleted. */
7974 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
7975 && !can_throw_internal (insn)
7976 && insn != bb->head)
7977 insn = PREV_INSN (insn);
7978 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
7982 insn = NEXT_INSN (insn);
7983 while (insn && insn != stop)
7985 next = NEXT_INSN (insn);
7990 /* Sometimes there's still the return value USE.
7991 If it's placed after a trapping call (i.e. that
7992 call is the last insn anyway), we have no fallthru
7993 edge. Simply delete this use and don't try to insert
7994 on the non-existent edge. */
7995 if (GET_CODE (PATTERN (insn)) != USE)
7997 /* We're not deleting it, we're moving it. */
7998 INSN_DELETED_P (insn) = 0;
7999 PREV_INSN (insn) = NULL_RTX;
8000 NEXT_INSN (insn) = NULL_RTX;
8002 insert_insn_on_edge (insn, e);
8009 /* We've possibly turned single trapping insn into multiple ones. */
8010 if (flag_non_call_exceptions)
8013 blocks = sbitmap_alloc (last_basic_block);
8014 sbitmap_ones (blocks);
8015 find_many_sub_basic_blocks (blocks);
8018 commit_edge_insertions ();
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