1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress = 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
260 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 int initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Non-zero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 int offset; /* Current offset between the two regs. */
302 int previous_offset; /* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table * reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If non-zero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
342 /* For each label, we record the offset of each elimination. If we reach
343 a label by more than one path and an offset differs, we cannot do the
344 elimination. This information is indexed by the number of the label.
345 The first table is an array of flags that records whether we have yet
346 encountered a label and the second table is an array of arrays, one
347 entry in the latter array for each elimination. */
349 static char *offsets_known_at;
350 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
352 /* Number of labels in the current function. */
354 static int num_labels;
356 struct hard_reg_n_uses
362 static void maybe_fix_stack_asms PROTO((void));
363 static void calculate_needs_all_insns PROTO((int));
364 static void calculate_needs PROTO((struct insn_chain *));
365 static void find_reload_regs PROTO((struct insn_chain *chain,
367 static void find_tworeg_group PROTO((struct insn_chain *, int,
369 static void find_group PROTO((struct insn_chain *, int,
371 static int possible_group_p PROTO((struct insn_chain *, int));
372 static void count_possible_groups PROTO((struct insn_chain *, int));
373 static int modes_equiv_for_class_p PROTO((enum machine_mode,
376 static void delete_caller_save_insns PROTO((void));
378 static void spill_failure PROTO((rtx));
379 static void new_spill_reg PROTO((struct insn_chain *, int, int,
381 static void maybe_mark_pseudo_spilled PROTO((int));
382 static void delete_dead_insn PROTO((rtx));
383 static void alter_reg PROTO((int, int));
384 static void set_label_offsets PROTO((rtx, rtx, int));
385 static int eliminate_regs_in_insn PROTO((rtx, int));
386 static void update_eliminable_offsets PROTO((void));
387 static void mark_not_eliminable PROTO((rtx, rtx));
388 static void set_initial_elim_offsets PROTO((void));
389 static void verify_initial_elim_offsets PROTO((void));
390 static void set_initial_label_offsets PROTO((void));
391 static void set_offsets_for_label PROTO((rtx));
392 static void init_elim_table PROTO((void));
393 static void update_eliminables PROTO((HARD_REG_SET *));
394 static void spill_hard_reg PROTO((int, FILE *, int));
395 static int finish_spills PROTO((int, FILE *));
396 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PROTO((rtx));
398 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
399 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
400 static void order_regs_for_reload PROTO((struct insn_chain *));
401 static void reload_as_needed PROTO((int));
402 static void forget_old_reloads_1 PROTO((rtx, rtx));
403 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
404 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
406 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
408 static int reload_reg_free_p PROTO((int, int, enum reload_type));
409 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
410 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
411 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
413 static void choose_reload_regs PROTO((struct insn_chain *));
414 static void merge_assigned_reloads PROTO((rtx));
415 static void emit_reload_insns PROTO((struct insn_chain *));
416 static void delete_output_reload PROTO((rtx, int, int));
417 static void delete_address_reloads PROTO((rtx, rtx));
418 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
419 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
420 static int constraint_accepts_reg_p PROTO((char *, rtx));
421 static void reload_cse_regs_1 PROTO((rtx));
422 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
423 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
424 static void reload_cse_invalidate_mem PROTO((rtx));
425 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
426 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
427 static int reload_cse_noop_set_p PROTO((rtx, rtx));
428 static int reload_cse_simplify_set PROTO((rtx, rtx));
429 static int reload_cse_simplify_operands PROTO((rtx));
430 static void reload_cse_check_clobber PROTO((rtx, rtx));
431 static void reload_cse_record_set PROTO((rtx, rtx));
432 static void reload_combine PROTO((void));
433 static void reload_combine_note_use PROTO((rtx *, rtx));
434 static void reload_combine_note_store PROTO((rtx, rtx));
435 static void reload_cse_move2add PROTO((rtx));
436 static void move2add_note_store PROTO((rtx, rtx));
438 /* Initialize the reload pass once per compilation. */
445 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
446 Set spill_indirect_levels to the number of levels such addressing is
447 permitted, zero if it is not permitted at all. */
450 = gen_rtx_MEM (Pmode,
452 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
454 spill_indirect_levels = 0;
456 while (memory_address_p (QImode, tem))
458 spill_indirect_levels++;
459 tem = gen_rtx_MEM (Pmode, tem);
462 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
464 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
465 indirect_symref_ok = memory_address_p (QImode, tem);
467 /* See if reg+reg is a valid (and offsettable) address. */
469 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
471 tem = gen_rtx_PLUS (Pmode,
472 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
473 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
489 /* List of insn chains that are currently unused. */
490 static struct insn_chain *unused_insn_chains = 0;
492 /* Allocate an empty insn_chain structure. */
496 struct insn_chain *c;
498 if (unused_insn_chains == 0)
500 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
501 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
502 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
506 c = unused_insn_chains;
507 unused_insn_chains = c->next;
509 c->is_caller_save_insn = 0;
510 c->need_operand_change = 0;
516 /* Small utility function to set all regs in hard reg set TO which are
517 allocated to pseudos in regset FROM. */
519 compute_use_by_pseudos (to, from)
524 EXECUTE_IF_SET_IN_REG_SET
525 (from, FIRST_PSEUDO_REGISTER, regno,
527 int r = reg_renumber[regno];
531 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
533 SET_HARD_REG_BIT (*to, r + nregs);
537 /* Global variables used by reload and its subroutines. */
539 /* Set during calculate_needs if an insn needs register elimination. */
540 static int something_needs_elimination;
541 /* Set during calculate_needs if an insn needs an operand changed. */
542 int something_needs_operands_changed;
544 /* Nonzero means we couldn't get enough spill regs. */
547 /* Main entry point for the reload pass.
549 FIRST is the first insn of the function being compiled.
551 GLOBAL nonzero means we were called from global_alloc
552 and should attempt to reallocate any pseudoregs that we
553 displace from hard regs we will use for reloads.
554 If GLOBAL is zero, we do not have enough information to do that,
555 so any pseudo reg that is spilled must go to the stack.
557 DUMPFILE is the global-reg debugging dump file stream, or 0.
558 If it is nonzero, messages are written to it to describe
559 which registers are seized as reload regs, which pseudo regs
560 are spilled from them, and where the pseudo regs are reallocated to.
562 Return value is nonzero if reload failed
563 and we must not do any more for this function. */
566 reload (first, global, dumpfile)
573 register struct elim_table *ep;
575 /* The two pointers used to track the true location of the memory used
576 for label offsets. */
577 char *real_known_ptr = NULL_PTR;
578 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
580 /* Make sure even insns with volatile mem refs are recognizable. */
585 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
587 /* Make sure that the last insn in the chain
588 is not something that needs reloading. */
589 emit_note (NULL_PTR, NOTE_INSN_DELETED);
591 /* Enable find_equiv_reg to distinguish insns made by reload. */
592 reload_first_uid = get_max_uid ();
594 #ifdef SECONDARY_MEMORY_NEEDED
595 /* Initialize the secondary memory table. */
596 clear_secondary_mem ();
599 /* We don't have a stack slot for any spill reg yet. */
600 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
601 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
603 /* Initialize the save area information for caller-save, in case some
607 /* Compute which hard registers are now in use
608 as homes for pseudo registers.
609 This is done here rather than (eg) in global_alloc
610 because this point is reached even if not optimizing. */
611 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
614 /* A function that receives a nonlocal goto must save all call-saved
616 if (current_function_has_nonlocal_label)
617 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
619 if (! call_used_regs[i] && ! fixed_regs[i])
620 regs_ever_live[i] = 1;
623 /* Find all the pseudo registers that didn't get hard regs
624 but do have known equivalent constants or memory slots.
625 These include parameters (known equivalent to parameter slots)
626 and cse'd or loop-moved constant memory addresses.
628 Record constant equivalents in reg_equiv_constant
629 so they will be substituted by find_reloads.
630 Record memory equivalents in reg_mem_equiv so they can
631 be substituted eventually by altering the REG-rtx's. */
633 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
634 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
635 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
636 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
637 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
638 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
639 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
640 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
641 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
642 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
643 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
644 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
645 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
646 bcopy (reg_renumber, reg_old_renumber, max_regno * sizeof (short));
647 pseudo_forbidden_regs
648 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
650 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
652 CLEAR_HARD_REG_SET (bad_spill_regs_global);
653 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
655 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
656 Also find all paradoxical subregs and find largest such for each pseudo.
657 On machines with small register classes, record hard registers that
658 are used for user variables. These can never be used for spills.
659 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
660 caller-saved registers must be marked live. */
662 for (insn = first; insn; insn = NEXT_INSN (insn))
664 rtx set = single_set (insn);
666 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
667 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
668 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
669 if (! call_used_regs[i])
670 regs_ever_live[i] = 1;
672 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
674 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
676 #ifdef LEGITIMATE_PIC_OPERAND_P
677 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
678 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
682 rtx x = XEXP (note, 0);
683 i = REGNO (SET_DEST (set));
684 if (i > LAST_VIRTUAL_REGISTER)
686 if (GET_CODE (x) == MEM)
688 /* If the operand is a PLUS, the MEM may be shared,
689 so make sure we have an unshared copy here. */
690 if (GET_CODE (XEXP (x, 0)) == PLUS)
693 reg_equiv_memory_loc[i] = x;
695 else if (CONSTANT_P (x))
697 if (LEGITIMATE_CONSTANT_P (x))
698 reg_equiv_constant[i] = x;
700 reg_equiv_memory_loc[i]
701 = force_const_mem (GET_MODE (SET_DEST (set)), x);
706 /* If this register is being made equivalent to a MEM
707 and the MEM is not SET_SRC, the equivalencing insn
708 is one with the MEM as a SET_DEST and it occurs later.
709 So don't mark this insn now. */
710 if (GET_CODE (x) != MEM
711 || rtx_equal_p (SET_SRC (set), x))
713 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
718 /* If this insn is setting a MEM from a register equivalent to it,
719 this is the equivalencing insn. */
720 else if (set && GET_CODE (SET_DEST (set)) == MEM
721 && GET_CODE (SET_SRC (set)) == REG
722 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
723 && rtx_equal_p (SET_DEST (set),
724 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
725 reg_equiv_init[REGNO (SET_SRC (set))]
726 = gen_rtx_INSN_LIST (VOIDmode, insn,
727 reg_equiv_init[REGNO (SET_SRC (set))]);
729 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
730 scan_paradoxical_subregs (PATTERN (insn));
735 num_labels = max_label_num () - get_first_label_num ();
737 /* Allocate the tables used to store offset information at labels. */
738 /* We used to use alloca here, but the size of what it would try to
739 allocate would occasionally cause it to exceed the stack limit and
740 cause a core dump. */
741 real_known_ptr = xmalloc (num_labels);
743 = (int (*)[NUM_ELIMINABLE_REGS])
744 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
746 offsets_known_at = real_known_ptr - get_first_label_num ();
748 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
750 /* Alter each pseudo-reg rtx to contain its hard reg number.
751 Assign stack slots to the pseudos that lack hard regs or equivalents.
752 Do not touch virtual registers. */
754 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
757 /* If we have some registers we think can be eliminated, scan all insns to
758 see if there is an insn that sets one of these registers to something
759 other than itself plus a constant. If so, the register cannot be
760 eliminated. Doing this scan here eliminates an extra pass through the
761 main reload loop in the most common case where register elimination
763 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
764 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
765 || GET_CODE (insn) == CALL_INSN)
766 note_stores (PATTERN (insn), mark_not_eliminable);
768 #ifndef REGISTER_CONSTRAINTS
769 /* If all the pseudo regs have hard regs,
770 except for those that are never referenced,
771 we know that no reloads are needed. */
772 /* But that is not true if there are register constraints, since
773 in that case some pseudos might be in the wrong kind of hard reg. */
775 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
776 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
779 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
781 free (real_known_ptr);
783 free (reg_equiv_constant);
784 free (reg_equiv_memory_loc);
785 free (reg_equiv_mem);
786 free (reg_equiv_init);
787 free (reg_equiv_address);
788 free (reg_max_ref_width);
789 free (reg_old_renumber);
790 free (pseudo_previous_regs);
791 free (pseudo_forbidden_regs);
796 maybe_fix_stack_asms ();
798 insns_need_reload = 0;
799 something_needs_elimination = 0;
801 /* Initialize to -1, which means take the first spill register. */
804 spilled_pseudos = ALLOCA_REG_SET ();
806 /* Spill any hard regs that we know we can't eliminate. */
807 CLEAR_HARD_REG_SET (used_spill_regs);
808 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
809 if (! ep->can_eliminate)
810 spill_hard_reg (ep->from, dumpfile, 1);
812 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
813 if (frame_pointer_needed)
814 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
816 finish_spills (global, dumpfile);
818 /* From now on, we need to emit any moves without making new pseudos. */
819 reload_in_progress = 1;
821 /* This loop scans the entire function each go-round
822 and repeats until one repetition spills no additional hard regs. */
825 int something_changed;
827 struct insn_chain *chain;
829 HOST_WIDE_INT starting_frame_size;
831 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
832 here because the stack size may be a part of the offset computation
833 for register elimination, and there might have been new stack slots
834 created in the last iteration of this loop. */
835 assign_stack_local (BLKmode, 0, 0);
837 starting_frame_size = get_frame_size ();
839 set_initial_elim_offsets ();
840 set_initial_label_offsets ();
842 /* For each pseudo register that has an equivalent location defined,
843 try to eliminate any eliminable registers (such as the frame pointer)
844 assuming initial offsets for the replacement register, which
847 If the resulting location is directly addressable, substitute
848 the MEM we just got directly for the old REG.
850 If it is not addressable but is a constant or the sum of a hard reg
851 and constant, it is probably not addressable because the constant is
852 out of range, in that case record the address; we will generate
853 hairy code to compute the address in a register each time it is
854 needed. Similarly if it is a hard register, but one that is not
855 valid as an address register.
857 If the location is not addressable, but does not have one of the
858 above forms, assign a stack slot. We have to do this to avoid the
859 potential of producing lots of reloads if, e.g., a location involves
860 a pseudo that didn't get a hard register and has an equivalent memory
861 location that also involves a pseudo that didn't get a hard register.
863 Perhaps at some point we will improve reload_when_needed handling
864 so this problem goes away. But that's very hairy. */
866 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
867 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
869 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
871 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
873 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
874 else if (CONSTANT_P (XEXP (x, 0))
875 || (GET_CODE (XEXP (x, 0)) == REG
876 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
877 || (GET_CODE (XEXP (x, 0)) == PLUS
878 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
879 && (REGNO (XEXP (XEXP (x, 0), 0))
880 < FIRST_PSEUDO_REGISTER)
881 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
882 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
885 /* Make a new stack slot. Then indicate that something
886 changed so we go back and recompute offsets for
887 eliminable registers because the allocation of memory
888 below might change some offset. reg_equiv_{mem,address}
889 will be set up for this pseudo on the next pass around
891 reg_equiv_memory_loc[i] = 0;
892 reg_equiv_init[i] = 0;
897 if (caller_save_needed)
900 /* If we allocated another stack slot, redo elimination bookkeeping. */
901 if (starting_frame_size != get_frame_size ())
904 if (caller_save_needed)
906 save_call_clobbered_regs ();
907 /* That might have allocated new insn_chain structures. */
908 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
911 calculate_needs_all_insns (global);
913 CLEAR_REG_SET (spilled_pseudos);
916 something_changed = 0;
918 /* If we allocated any new memory locations, make another pass
919 since it might have changed elimination offsets. */
920 if (starting_frame_size != get_frame_size ())
921 something_changed = 1;
924 HARD_REG_SET to_spill;
925 CLEAR_HARD_REG_SET (to_spill);
926 update_eliminables (&to_spill);
927 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
928 if (TEST_HARD_REG_BIT (to_spill, i))
930 spill_hard_reg (i, dumpfile, 1);
933 /* Regardless of the state of spills, if we previously had
934 a register that we thought we could eliminate, but no can
935 not eliminate, we must run another pass.
937 Consider pseudos which have an entry in reg_equiv_* which
938 reference an eliminable register. We must make another pass
939 to update reg_equiv_* so that we do not substitute in the
940 old value from when we thought the elimination could be
942 something_changed = 1;
946 CLEAR_HARD_REG_SET (used_spill_regs);
947 /* Try to satisfy the needs for each insn. */
948 for (chain = insns_need_reload; chain != 0;
949 chain = chain->next_need_reload)
950 find_reload_regs (chain, dumpfile);
955 if (insns_need_reload != 0 || did_spill)
956 something_changed |= finish_spills (global, dumpfile);
958 if (! something_changed)
961 if (caller_save_needed)
962 delete_caller_save_insns ();
965 /* If global-alloc was run, notify it of any register eliminations we have
968 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
969 if (ep->can_eliminate)
970 mark_elimination (ep->from, ep->to);
972 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
973 If that insn didn't set the register (i.e., it copied the register to
974 memory), just delete that insn instead of the equivalencing insn plus
975 anything now dead. If we call delete_dead_insn on that insn, we may
976 delete the insn that actually sets the register if the register dies
977 there and that is incorrect. */
979 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
981 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
984 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
986 rtx equiv_insn = XEXP (list, 0);
987 if (GET_CODE (equiv_insn) == NOTE)
989 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
990 delete_dead_insn (equiv_insn);
993 PUT_CODE (equiv_insn, NOTE);
994 NOTE_SOURCE_FILE (equiv_insn) = 0;
995 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1001 /* Use the reload registers where necessary
1002 by generating move instructions to move the must-be-register
1003 values into or out of the reload registers. */
1005 if (insns_need_reload != 0 || something_needs_elimination
1006 || something_needs_operands_changed)
1008 int old_frame_size = get_frame_size ();
1010 reload_as_needed (global);
1012 if (old_frame_size != get_frame_size ())
1016 verify_initial_elim_offsets ();
1019 /* If we were able to eliminate the frame pointer, show that it is no
1020 longer live at the start of any basic block. If it ls live by
1021 virtue of being in a pseudo, that pseudo will be marked live
1022 and hence the frame pointer will be known to be live via that
1025 if (! frame_pointer_needed)
1026 for (i = 0; i < n_basic_blocks; i++)
1027 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
1028 HARD_FRAME_POINTER_REGNUM);
1030 /* Come here (with failure set nonzero) if we can't get enough spill regs
1031 and we decide not to abort about it. */
1034 reload_in_progress = 0;
1036 /* Now eliminate all pseudo regs by modifying them into
1037 their equivalent memory references.
1038 The REG-rtx's for the pseudos are modified in place,
1039 so all insns that used to refer to them now refer to memory.
1041 For a reg that has a reg_equiv_address, all those insns
1042 were changed by reloading so that no insns refer to it any longer;
1043 but the DECL_RTL of a variable decl may refer to it,
1044 and if so this causes the debugging info to mention the variable. */
1046 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1050 int is_readonly = 0;
1052 if (reg_equiv_memory_loc[i])
1054 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1055 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1058 if (reg_equiv_mem[i])
1059 addr = XEXP (reg_equiv_mem[i], 0);
1061 if (reg_equiv_address[i])
1062 addr = reg_equiv_address[i];
1066 if (reg_renumber[i] < 0)
1068 rtx reg = regno_reg_rtx[i];
1069 XEXP (reg, 0) = addr;
1070 REG_USERVAR_P (reg) = 0;
1071 RTX_UNCHANGING_P (reg) = is_readonly;
1072 MEM_IN_STRUCT_P (reg) = in_struct;
1073 /* We have no alias information about this newly created
1075 MEM_ALIAS_SET (reg) = 0;
1076 PUT_CODE (reg, MEM);
1078 else if (reg_equiv_mem[i])
1079 XEXP (reg_equiv_mem[i], 0) = addr;
1083 /* We've finished reloading. This reload_completed must be set before we
1084 perform instruction splitting below. */
1085 reload_completed = 1;
1087 /* Make a pass over all the insns and delete all USEs which we inserted
1088 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1089 notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands. */
1091 for (insn = first; insn; insn = NEXT_INSN (insn))
1092 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1096 if ((GET_CODE (PATTERN (insn)) == USE
1097 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1098 || GET_CODE (PATTERN (insn)) == CLOBBER)
1100 PUT_CODE (insn, NOTE);
1101 NOTE_SOURCE_FILE (insn) = 0;
1102 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1106 pnote = ®_NOTES (insn);
1109 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1110 || REG_NOTE_KIND (*pnote) == REG_UNUSED)
1111 *pnote = XEXP (*pnote, 1);
1113 pnote = &XEXP (*pnote, 1);
1116 /* And simplify (subreg (reg)) if it appears as an operand. */
1117 cleanup_subreg_operands (insn);
1119 /* If optimizing and we are performing instruction scheduling after
1120 reload, then go ahead and split insns now since we are about to
1121 recompute flow information anyway. */
1122 if (optimize && flag_schedule_insns_after_reload)
1126 last = try_split (PATTERN (insn), insn, 1);
1130 PUT_CODE (insn, NOTE);
1131 NOTE_SOURCE_FILE (insn) = 0;
1132 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1138 /* If we are doing stack checking, give a warning if this function's
1139 frame size is larger than we expect. */
1140 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1142 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1144 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1145 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1146 size += UNITS_PER_WORD;
1148 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1149 warning ("frame size too large for reliable stack checking");
1152 /* Indicate that we no longer have known memory locations or constants. */
1153 if (reg_equiv_constant)
1154 free (reg_equiv_constant);
1155 reg_equiv_constant = 0;
1156 if (reg_equiv_memory_loc)
1157 free (reg_equiv_memory_loc);
1158 reg_equiv_memory_loc = 0;
1161 free (real_known_ptr);
1165 free (reg_equiv_mem);
1166 free (reg_equiv_init);
1167 free (reg_equiv_address);
1168 free (reg_max_ref_width);
1169 free (reg_old_renumber);
1170 free (pseudo_previous_regs);
1171 free (pseudo_forbidden_regs);
1173 FREE_REG_SET (spilled_pseudos);
1175 CLEAR_HARD_REG_SET (used_spill_regs);
1176 for (i = 0; i < n_spills; i++)
1177 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1179 /* Free all the insn_chain structures at once. */
1180 obstack_free (&reload_obstack, reload_startobj);
1181 unused_insn_chains = 0;
1186 /* Yet another special case. Unfortunately, reg-stack forces people to
1187 write incorrect clobbers in asm statements. These clobbers must not
1188 cause the register to appear in bad_spill_regs, otherwise we'll call
1189 fatal_insn later. We clear the corresponding regnos in the live
1190 register sets to avoid this.
1191 The whole thing is rather sick, I'm afraid. */
1193 maybe_fix_stack_asms ()
1196 char *constraints[MAX_RECOG_OPERANDS];
1197 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1198 struct insn_chain *chain;
1200 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1203 HARD_REG_SET clobbered, allowed;
1206 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1207 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1209 pat = PATTERN (chain->insn);
1210 if (GET_CODE (pat) != PARALLEL)
1213 CLEAR_HARD_REG_SET (clobbered);
1214 CLEAR_HARD_REG_SET (allowed);
1216 /* First, make a mask of all stack regs that are clobbered. */
1217 for (i = 0; i < XVECLEN (pat, 0); i++)
1219 rtx t = XVECEXP (pat, 0, i);
1220 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1221 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1224 /* Get the operand values and constraints out of the insn. */
1225 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1226 constraints, operand_mode);
1228 /* For every operand, see what registers are allowed. */
1229 for (i = 0; i < noperands; i++)
1231 char *p = constraints[i];
1232 /* For every alternative, we compute the class of registers allowed
1233 for reloading in CLS, and merge its contents into the reg set
1235 int cls = (int) NO_REGS;
1241 if (c == '\0' || c == ',' || c == '#')
1243 /* End of one alternative - mark the regs in the current
1244 class, and reset the class. */
1245 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1250 } while (c != '\0' && c != ',');
1258 case '=': case '+': case '*': case '%': case '?': case '!':
1259 case '0': case '1': case '2': case '3': case '4': case 'm':
1260 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1261 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1262 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1264 #ifdef EXTRA_CONSTRAINT
1265 case 'Q': case 'R': case 'S': case 'T': case 'U':
1270 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1275 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1279 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1284 /* Those of the registers which are clobbered, but allowed by the
1285 constraints, must be usable as reload registers. So clear them
1286 out of the life information. */
1287 AND_HARD_REG_SET (allowed, clobbered);
1288 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1289 if (TEST_HARD_REG_BIT (allowed, i))
1291 CLEAR_REGNO_REG_SET (chain->live_before, i);
1292 CLEAR_REGNO_REG_SET (chain->live_after, i);
1300 /* Walk the chain of insns, and determine for each whether it needs reloads
1301 and/or eliminations. Build the corresponding insns_need_reload list, and
1302 set something_needs_elimination as appropriate. */
1304 calculate_needs_all_insns (global)
1307 struct insn_chain **pprev_reload = &insns_need_reload;
1308 struct insn_chain **pchain;
1310 something_needs_elimination = 0;
1312 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1315 struct insn_chain *chain;
1320 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1321 include REG_LABEL), we need to see what effects this has on the
1322 known offsets at labels. */
1324 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1325 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1326 && REG_NOTES (insn) != 0))
1327 set_label_offsets (insn, insn, 0);
1329 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1331 rtx old_body = PATTERN (insn);
1332 int old_code = INSN_CODE (insn);
1333 rtx old_notes = REG_NOTES (insn);
1334 int did_elimination = 0;
1335 int operands_changed = 0;
1337 /* If needed, eliminate any eliminable registers. */
1339 did_elimination = eliminate_regs_in_insn (insn, 0);
1341 /* Analyze the instruction. */
1342 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1343 global, spill_reg_order);
1345 /* If a no-op set needs more than one reload, this is likely
1346 to be something that needs input address reloads. We
1347 can't get rid of this cleanly later, and it is of no use
1348 anyway, so discard it now.
1349 We only do this when expensive_optimizations is enabled,
1350 since this complements reload inheritance / output
1351 reload deletion, and it can make debugging harder. */
1352 if (flag_expensive_optimizations && n_reloads > 1)
1354 rtx set = single_set (insn);
1356 && SET_SRC (set) == SET_DEST (set)
1357 && GET_CODE (SET_SRC (set)) == REG
1358 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1360 PUT_CODE (insn, NOTE);
1361 NOTE_SOURCE_FILE (insn) = 0;
1362 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1367 update_eliminable_offsets ();
1369 /* Remember for later shortcuts which insns had any reloads or
1370 register eliminations. */
1371 chain->need_elim = did_elimination;
1372 chain->need_reload = n_reloads > 0;
1373 chain->need_operand_change = operands_changed;
1375 /* Discard any register replacements done. */
1376 if (did_elimination)
1378 obstack_free (&reload_obstack, reload_firstobj);
1379 PATTERN (insn) = old_body;
1380 INSN_CODE (insn) = old_code;
1381 REG_NOTES (insn) = old_notes;
1382 something_needs_elimination = 1;
1385 something_needs_operands_changed |= operands_changed;
1389 *pprev_reload = chain;
1390 pprev_reload = &chain->next_need_reload;
1392 calculate_needs (chain);
1399 /* Compute the most additional registers needed by one instruction,
1400 given by CHAIN. Collect information separately for each class of regs.
1402 To compute the number of reload registers of each class needed for an
1403 insn, we must simulate what choose_reload_regs can do. We do this by
1404 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1405 reloads are used in both. The input part uses those reloads,
1406 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1407 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1408 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1410 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1411 which are live for the entire output portion, and the maximum of all the
1412 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1414 The total number of registers needed is the maximum of the
1415 inputs and outputs. */
1418 calculate_needs (chain)
1419 struct insn_chain *chain;
1423 /* Each `struct needs' corresponds to one RELOAD_... type. */
1427 struct needs output;
1429 struct needs other_addr;
1430 struct needs op_addr;
1431 struct needs op_addr_reload;
1432 struct needs in_addr[MAX_RECOG_OPERANDS];
1433 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1434 struct needs out_addr[MAX_RECOG_OPERANDS];
1435 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1438 bzero ((char *) chain->group_size, sizeof chain->group_size);
1439 for (i = 0; i < N_REG_CLASSES; i++)
1440 chain->group_mode[i] = VOIDmode;
1441 bzero ((char *) &insn_needs, sizeof insn_needs);
1443 /* Count each reload once in every class
1444 containing the reload's own class. */
1446 for (i = 0; i < n_reloads; i++)
1448 register enum reg_class *p;
1449 enum reg_class class = reload_reg_class[i];
1451 enum machine_mode mode;
1452 struct needs *this_needs;
1454 /* Don't count the dummy reloads, for which one of the
1455 regs mentioned in the insn can be used for reloading.
1456 Don't count optional reloads.
1457 Don't count reloads that got combined with others. */
1458 if (reload_reg_rtx[i] != 0
1459 || reload_optional[i] != 0
1460 || (reload_out[i] == 0 && reload_in[i] == 0
1461 && ! reload_secondary_p[i]))
1464 mode = reload_inmode[i];
1465 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1466 mode = reload_outmode[i];
1467 size = CLASS_MAX_NREGS (class, mode);
1469 /* Decide which time-of-use to count this reload for. */
1470 switch (reload_when_needed[i])
1473 this_needs = &insn_needs.other;
1475 case RELOAD_FOR_INPUT:
1476 this_needs = &insn_needs.input;
1478 case RELOAD_FOR_OUTPUT:
1479 this_needs = &insn_needs.output;
1481 case RELOAD_FOR_INSN:
1482 this_needs = &insn_needs.insn;
1484 case RELOAD_FOR_OTHER_ADDRESS:
1485 this_needs = &insn_needs.other_addr;
1487 case RELOAD_FOR_INPUT_ADDRESS:
1488 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1490 case RELOAD_FOR_INPADDR_ADDRESS:
1491 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1493 case RELOAD_FOR_OUTPUT_ADDRESS:
1494 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1496 case RELOAD_FOR_OUTADDR_ADDRESS:
1497 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1499 case RELOAD_FOR_OPERAND_ADDRESS:
1500 this_needs = &insn_needs.op_addr;
1502 case RELOAD_FOR_OPADDR_ADDR:
1503 this_needs = &insn_needs.op_addr_reload;
1509 enum machine_mode other_mode, allocate_mode;
1511 /* Count number of groups needed separately from
1512 number of individual regs needed. */
1513 this_needs->groups[(int) class]++;
1514 p = reg_class_superclasses[(int) class];
1515 while (*p != LIM_REG_CLASSES)
1516 this_needs->groups[(int) *p++]++;
1518 /* Record size and mode of a group of this class. */
1519 /* If more than one size group is needed,
1520 make all groups the largest needed size. */
1521 if (chain->group_size[(int) class] < size)
1523 other_mode = chain->group_mode[(int) class];
1524 allocate_mode = mode;
1526 chain->group_size[(int) class] = size;
1527 chain->group_mode[(int) class] = mode;
1532 allocate_mode = chain->group_mode[(int) class];
1535 /* Crash if two dissimilar machine modes both need
1536 groups of consecutive regs of the same class. */
1538 if (other_mode != VOIDmode && other_mode != allocate_mode
1539 && ! modes_equiv_for_class_p (allocate_mode,
1541 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1546 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1547 p = reg_class_superclasses[(int) class];
1548 while (*p != LIM_REG_CLASSES)
1549 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1555 /* All reloads have been counted for this insn;
1556 now merge the various times of use.
1557 This sets insn_needs, etc., to the maximum total number
1558 of registers needed at any point in this insn. */
1560 for (i = 0; i < N_REG_CLASSES; i++)
1562 int j, in_max, out_max;
1564 /* Compute normal and nongroup needs. */
1565 for (j = 0; j <= 1; j++)
1568 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1570 in_max = MAX (in_max,
1571 (insn_needs.in_addr[k].regs[j][i]
1572 + insn_needs.in_addr_addr[k].regs[j][i]));
1573 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1574 out_max = MAX (out_max,
1575 insn_needs.out_addr_addr[k].regs[j][i]);
1578 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1579 and operand addresses but not things used to reload
1580 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1581 don't conflict with things needed to reload inputs or
1584 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1585 insn_needs.op_addr_reload.regs[j][i]),
1588 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1590 insn_needs.input.regs[j][i]
1591 = MAX (insn_needs.input.regs[j][i]
1592 + insn_needs.op_addr.regs[j][i]
1593 + insn_needs.insn.regs[j][i],
1594 in_max + insn_needs.input.regs[j][i]);
1596 insn_needs.output.regs[j][i] += out_max;
1597 insn_needs.other.regs[j][i]
1598 += MAX (MAX (insn_needs.input.regs[j][i],
1599 insn_needs.output.regs[j][i]),
1600 insn_needs.other_addr.regs[j][i]);
1604 /* Now compute group needs. */
1605 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1607 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1608 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1609 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1610 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1613 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1614 insn_needs.op_addr_reload.groups[i]),
1616 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1618 insn_needs.input.groups[i]
1619 = MAX (insn_needs.input.groups[i]
1620 + insn_needs.op_addr.groups[i]
1621 + insn_needs.insn.groups[i],
1622 in_max + insn_needs.input.groups[i]);
1624 insn_needs.output.groups[i] += out_max;
1625 insn_needs.other.groups[i]
1626 += MAX (MAX (insn_needs.input.groups[i],
1627 insn_needs.output.groups[i]),
1628 insn_needs.other_addr.groups[i]);
1631 /* Record the needs for later. */
1632 chain->need = insn_needs.other;
1635 /* Find a group of exactly 2 registers.
1637 First try to fill out the group by spilling a single register which
1638 would allow completion of the group.
1640 Then try to create a new group from a pair of registers, neither of
1641 which are explicitly used.
1643 Then try to create a group from any pair of registers. */
1646 find_tworeg_group (chain, class, dumpfile)
1647 struct insn_chain *chain;
1652 /* First, look for a register that will complete a group. */
1653 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1657 j = potential_reload_regs[i];
1658 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1659 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1660 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1661 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1662 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1663 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1664 /* We don't want one part of another group.
1665 We could get "two groups" that overlap! */
1666 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1667 || (j < FIRST_PSEUDO_REGISTER - 1
1668 && (other = j + 1, spill_reg_order[other] >= 0)
1669 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1670 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1671 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1672 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1673 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1675 register enum reg_class *p;
1677 /* We have found one that will complete a group,
1678 so count off one group as provided. */
1679 chain->need.groups[class]--;
1680 p = reg_class_superclasses[class];
1681 while (*p != LIM_REG_CLASSES)
1683 if (chain->group_size [(int) *p] <= chain->group_size [class])
1684 chain->need.groups[(int) *p]--;
1688 /* Indicate both these regs are part of a group. */
1689 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1690 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1694 /* We can't complete a group, so start one. */
1695 if (i == FIRST_PSEUDO_REGISTER)
1696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1699 j = potential_reload_regs[i];
1700 /* Verify that J+1 is a potential reload reg. */
1701 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1702 if (potential_reload_regs[k] == j + 1)
1704 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1705 && k < FIRST_PSEUDO_REGISTER
1706 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1707 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1708 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1709 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1710 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1711 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1715 /* I should be the index in potential_reload_regs
1716 of the new reload reg we have found. */
1718 new_spill_reg (chain, i, class, 0, dumpfile);
1721 /* Find a group of more than 2 registers.
1722 Look for a sufficient sequence of unspilled registers, and spill them all
1726 find_group (chain, class, dumpfile)
1727 struct insn_chain *chain;
1733 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1735 int j = potential_reload_regs[i];
1738 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1739 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1742 /* Check each reg in the sequence. */
1743 for (k = 0; k < chain->group_size[class]; k++)
1744 if (! (spill_reg_order[j + k] < 0
1745 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1746 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1748 /* We got a full sequence, so spill them all. */
1749 if (k == chain->group_size[class])
1751 register enum reg_class *p;
1752 for (k = 0; k < chain->group_size[class]; k++)
1755 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1756 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1757 if (potential_reload_regs[idx] == j + k)
1759 new_spill_reg (chain, idx, class, 0, dumpfile);
1762 /* We have found one that will complete a group,
1763 so count off one group as provided. */
1764 chain->need.groups[class]--;
1765 p = reg_class_superclasses[class];
1766 while (*p != LIM_REG_CLASSES)
1768 if (chain->group_size [(int) *p]
1769 <= chain->group_size [class])
1770 chain->need.groups[(int) *p]--;
1777 /* There are no groups left. */
1778 spill_failure (chain->insn);
1782 /* If pseudo REG conflicts with one of our reload registers, mark it as
1785 maybe_mark_pseudo_spilled (reg)
1789 int r = reg_renumber[reg];
1794 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1795 for (i = 0; i < n_spills; i++)
1796 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1798 SET_REGNO_REG_SET (spilled_pseudos, reg);
1803 /* Find more reload regs to satisfy the remaining need of an insn, which
1805 Do it by ascending class number, since otherwise a reg
1806 might be spilled for a big class and might fail to count
1807 for a smaller class even though it belongs to that class.
1809 Count spilled regs in `spills', and add entries to
1810 `spill_regs' and `spill_reg_order'.
1812 ??? Note there is a problem here.
1813 When there is a need for a group in a high-numbered class,
1814 and also need for non-group regs that come from a lower class,
1815 the non-group regs are chosen first. If there aren't many regs,
1816 they might leave no room for a group.
1818 This was happening on the 386. To fix it, we added the code
1819 that calls possible_group_p, so that the lower class won't
1820 break up the last possible group.
1822 Really fixing the problem would require changes above
1823 in counting the regs already spilled, and in choose_reload_regs.
1824 It might be hard to avoid introducing bugs there. */
1827 find_reload_regs (chain, dumpfile)
1828 struct insn_chain *chain;
1832 short *group_needs = chain->need.groups;
1833 short *simple_needs = chain->need.regs[0];
1834 short *nongroup_needs = chain->need.regs[1];
1837 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1839 /* Compute the order of preference for hard registers to spill.
1840 Store them by decreasing preference in potential_reload_regs. */
1842 order_regs_for_reload (chain);
1844 /* So far, no hard regs have been spilled. */
1846 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1847 spill_reg_order[i] = -1;
1849 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1850 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1851 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1853 for (class = 0; class < N_REG_CLASSES; class++)
1855 /* First get the groups of registers.
1856 If we got single registers first, we might fragment
1858 while (group_needs[class] > 0)
1860 /* If any single spilled regs happen to form groups,
1861 count them now. Maybe we don't really need
1862 to spill another group. */
1863 count_possible_groups (chain, class);
1865 if (group_needs[class] <= 0)
1868 /* Groups of size 2, the only groups used on most machines,
1869 are treated specially. */
1870 if (chain->group_size[class] == 2)
1871 find_tworeg_group (chain, class, dumpfile);
1873 find_group (chain, class, dumpfile);
1878 /* Now similarly satisfy all need for single registers. */
1880 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1882 /* If we spilled enough regs, but they weren't counted
1883 against the non-group need, see if we can count them now.
1884 If so, we can avoid some actual spilling. */
1885 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1886 for (i = 0; i < n_spills; i++)
1888 int regno = spill_regs[i];
1889 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1890 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1891 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1892 && nongroup_needs[class] > 0)
1894 register enum reg_class *p;
1896 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1897 nongroup_needs[class]--;
1898 p = reg_class_superclasses[class];
1899 while (*p != LIM_REG_CLASSES)
1900 nongroup_needs[(int) *p++]--;
1904 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1907 /* Consider the potential reload regs that aren't
1908 yet in use as reload regs, in order of preference.
1909 Find the most preferred one that's in this class. */
1911 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1913 int regno = potential_reload_regs[i];
1915 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1916 /* If this reg will not be available for groups,
1917 pick one that does not foreclose possible groups.
1918 This is a kludge, and not very general,
1919 but it should be sufficient to make the 386 work,
1920 and the problem should not occur on machines with
1922 && (nongroup_needs[class] == 0
1923 || possible_group_p (chain, regno)))
1927 /* If we couldn't get a register, try to get one even if we
1928 might foreclose possible groups. This may cause problems
1929 later, but that's better than aborting now, since it is
1930 possible that we will, in fact, be able to form the needed
1931 group even with this allocation. */
1933 if (i >= FIRST_PSEUDO_REGISTER
1934 && asm_noperands (chain->insn) < 0)
1935 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1936 if (potential_reload_regs[i] >= 0
1937 && TEST_HARD_REG_BIT (reg_class_contents[class],
1938 potential_reload_regs[i]))
1941 /* I should be the index in potential_reload_regs
1942 of the new reload reg we have found. */
1944 new_spill_reg (chain, i, class, 1, dumpfile);
1950 /* We know which hard regs to use, now mark the pseudos that live in them
1951 as needing to be kicked out. */
1952 EXECUTE_IF_SET_IN_REG_SET
1953 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1955 maybe_mark_pseudo_spilled (i);
1957 EXECUTE_IF_SET_IN_REG_SET
1958 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1960 maybe_mark_pseudo_spilled (i);
1963 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1967 dump_needs (chain, dumpfile)
1968 struct insn_chain *chain;
1971 static char *reg_class_names[] = REG_CLASS_NAMES;
1973 struct needs *n = &chain->need;
1975 for (i = 0; i < N_REG_CLASSES; i++)
1977 if (n->regs[i][0] > 0)
1979 ";; Need %d reg%s of class %s.\n",
1980 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
1981 reg_class_names[i]);
1982 if (n->regs[i][1] > 0)
1984 ";; Need %d nongroup reg%s of class %s.\n",
1985 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
1986 reg_class_names[i]);
1987 if (n->groups[i] > 0)
1989 ";; Need %d group%s (%smode) of class %s.\n",
1990 n->groups[i], n->groups[i] == 1 ? "" : "s",
1991 mode_name[(int) chain->group_mode[i]],
1992 reg_class_names[i]);
1996 /* Delete all insns that were inserted by emit_caller_save_insns during
1999 delete_caller_save_insns ()
2001 struct insn_chain *c = reload_insn_chain;
2005 while (c != 0 && c->is_caller_save_insn)
2007 struct insn_chain *next = c->next;
2010 if (insn == basic_block_head[c->block])
2011 basic_block_head[c->block] = NEXT_INSN (insn);
2012 if (insn == basic_block_end[c->block])
2013 basic_block_end[c->block] = PREV_INSN (insn);
2014 if (c == reload_insn_chain)
2015 reload_insn_chain = next;
2017 if (NEXT_INSN (insn) != 0)
2018 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2019 if (PREV_INSN (insn) != 0)
2020 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2023 next->prev = c->prev;
2025 c->prev->next = next;
2026 c->next = unused_insn_chains;
2027 unused_insn_chains = c;
2035 /* Nonzero if, after spilling reg REGNO for non-groups,
2036 it will still be possible to find a group if we still need one. */
2039 possible_group_p (chain, regno)
2040 struct insn_chain *chain;
2044 int class = (int) NO_REGS;
2046 for (i = 0; i < (int) N_REG_CLASSES; i++)
2047 if (chain->need.groups[i] > 0)
2053 if (class == (int) NO_REGS)
2056 /* Consider each pair of consecutive registers. */
2057 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2059 /* Ignore pairs that include reg REGNO. */
2060 if (i == regno || i + 1 == regno)
2063 /* Ignore pairs that are outside the class that needs the group.
2064 ??? Here we fail to handle the case where two different classes
2065 independently need groups. But this never happens with our
2066 current machine descriptions. */
2067 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2068 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2071 /* A pair of consecutive regs we can still spill does the trick. */
2072 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2073 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2074 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2077 /* A pair of one already spilled and one we can spill does it
2078 provided the one already spilled is not otherwise reserved. */
2079 if (spill_reg_order[i] < 0
2080 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2081 && spill_reg_order[i + 1] >= 0
2082 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2083 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2085 if (spill_reg_order[i + 1] < 0
2086 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2087 && spill_reg_order[i] >= 0
2088 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2089 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2096 /* Count any groups of CLASS that can be formed from the registers recently
2100 count_possible_groups (chain, class)
2101 struct insn_chain *chain;
2107 /* Now find all consecutive groups of spilled registers
2108 and mark each group off against the need for such groups.
2109 But don't count them against ordinary need, yet. */
2111 if (chain->group_size[class] == 0)
2114 CLEAR_HARD_REG_SET (new);
2116 /* Make a mask of all the regs that are spill regs in class I. */
2117 for (i = 0; i < n_spills; i++)
2119 int regno = spill_regs[i];
2121 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2122 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2123 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2124 SET_HARD_REG_BIT (new, regno);
2127 /* Find each consecutive group of them. */
2128 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2129 if (TEST_HARD_REG_BIT (new, i)
2130 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2131 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2133 for (j = 1; j < chain->group_size[class]; j++)
2134 if (! TEST_HARD_REG_BIT (new, i + j))
2137 if (j == chain->group_size[class])
2139 /* We found a group. Mark it off against this class's need for
2140 groups, and against each superclass too. */
2141 register enum reg_class *p;
2143 chain->need.groups[class]--;
2144 p = reg_class_superclasses[class];
2145 while (*p != LIM_REG_CLASSES)
2147 if (chain->group_size [(int) *p] <= chain->group_size [class])
2148 chain->need.groups[(int) *p]--;
2152 /* Don't count these registers again. */
2153 for (j = 0; j < chain->group_size[class]; j++)
2154 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2157 /* Skip to the last reg in this group. When i is incremented above,
2158 it will then point to the first reg of the next possible group. */
2163 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2164 another mode that needs to be reloaded for the same register class CLASS.
2165 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2166 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2168 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2169 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2170 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2171 causes unnecessary failures on machines requiring alignment of register
2172 groups when the two modes are different sizes, because the larger mode has
2173 more strict alignment rules than the smaller mode. */
2176 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2177 enum machine_mode allocate_mode, other_mode;
2178 enum reg_class class;
2181 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2183 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2184 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2185 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2191 /* Handle the failure to find a register to spill.
2192 INSN should be one of the insns which needed this particular spill reg. */
2195 spill_failure (insn)
2198 if (asm_noperands (PATTERN (insn)) >= 0)
2199 error_for_asm (insn, "`asm' needs too many reloads");
2201 fatal_insn ("Unable to find a register to spill.", insn);
2204 /* Add a new register to the tables of available spill-registers.
2205 CHAIN is the insn for which the register will be used; we decrease the
2207 I is the index of this register in potential_reload_regs.
2208 CLASS is the regclass whose need is being satisfied.
2209 NONGROUP is 0 if this register is part of a group.
2210 DUMPFILE is the same as the one that `reload' got. */
2213 new_spill_reg (chain, i, class, nongroup, dumpfile)
2214 struct insn_chain *chain;
2220 register enum reg_class *p;
2221 int regno = potential_reload_regs[i];
2223 if (i >= FIRST_PSEUDO_REGISTER)
2225 spill_failure (chain->insn);
2230 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2232 static char *reg_class_names[] = REG_CLASS_NAMES;
2234 if (asm_noperands (PATTERN (chain->insn)) < 0)
2236 /* The error message is still correct - we know only that it wasn't
2237 an asm statement that caused the problem, but one of the global
2238 registers declared by the users might have screwed us. */
2239 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2240 regno, reg_names[regno], reg_class_names[class]);
2241 error ("This may be due to a compiler bug or to impossible asm");
2242 error ("statements or clauses.");
2243 fatal_insn ("This is the instruction:", chain->insn);
2245 error_for_asm (chain->insn, "Invalid `asm' statement:");
2246 error_for_asm (chain->insn,
2247 "fixed or forbidden register %d (%s) was spilled for class %s.",
2248 regno, reg_names[regno], reg_class_names[class]);
2253 /* Make reg REGNO an additional reload reg. */
2255 potential_reload_regs[i] = -1;
2256 spill_regs[n_spills] = regno;
2257 spill_reg_order[regno] = n_spills;
2259 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2260 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2262 /* Clear off the needs we just satisfied. */
2264 chain->need.regs[0][class]--;
2265 p = reg_class_superclasses[class];
2266 while (*p != LIM_REG_CLASSES)
2267 chain->need.regs[0][(int) *p++]--;
2269 if (nongroup && chain->need.regs[1][class] > 0)
2271 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2272 chain->need.regs[1][class]--;
2273 p = reg_class_superclasses[class];
2274 while (*p != LIM_REG_CLASSES)
2275 chain->need.regs[1][(int) *p++]--;
2281 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2282 data that is dead in INSN. */
2285 delete_dead_insn (insn)
2288 rtx prev = prev_real_insn (insn);
2291 /* If the previous insn sets a register that dies in our insn, delete it
2293 if (prev && GET_CODE (PATTERN (prev)) == SET
2294 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2295 && reg_mentioned_p (prev_dest, PATTERN (insn))
2296 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2297 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2298 delete_dead_insn (prev);
2300 PUT_CODE (insn, NOTE);
2301 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2302 NOTE_SOURCE_FILE (insn) = 0;
2305 /* Modify the home of pseudo-reg I.
2306 The new home is present in reg_renumber[I].
2308 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2309 or it may be -1, meaning there is none or it is not relevant.
2310 This is used so that all pseudos spilled from a given hard reg
2311 can share one stack slot. */
2314 alter_reg (i, from_reg)
2318 /* When outputting an inline function, this can happen
2319 for a reg that isn't actually used. */
2320 if (regno_reg_rtx[i] == 0)
2323 /* If the reg got changed to a MEM at rtl-generation time,
2325 if (GET_CODE (regno_reg_rtx[i]) != REG)
2328 /* Modify the reg-rtx to contain the new hard reg
2329 number or else to contain its pseudo reg number. */
2330 REGNO (regno_reg_rtx[i])
2331 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2333 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2334 allocate a stack slot for it. */
2336 if (reg_renumber[i] < 0
2337 && REG_N_REFS (i) > 0
2338 && reg_equiv_constant[i] == 0
2339 && reg_equiv_memory_loc[i] == 0)
2342 int inherent_size = PSEUDO_REGNO_BYTES (i);
2343 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2346 /* Each pseudo reg has an inherent size which comes from its own mode,
2347 and a total size which provides room for paradoxical subregs
2348 which refer to the pseudo reg in wider modes.
2350 We can use a slot already allocated if it provides both
2351 enough inherent space and enough total space.
2352 Otherwise, we allocate a new slot, making sure that it has no less
2353 inherent space, and no less total space, then the previous slot. */
2356 /* No known place to spill from => no slot to reuse. */
2357 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2358 inherent_size == total_size ? 0 : -1);
2359 if (BYTES_BIG_ENDIAN)
2360 /* Cancel the big-endian correction done in assign_stack_local.
2361 Get the address of the beginning of the slot.
2362 This is so we can do a big-endian correction unconditionally
2364 adjust = inherent_size - total_size;
2366 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2368 /* Reuse a stack slot if possible. */
2369 else if (spill_stack_slot[from_reg] != 0
2370 && spill_stack_slot_width[from_reg] >= total_size
2371 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2373 x = spill_stack_slot[from_reg];
2374 /* Allocate a bigger slot. */
2377 /* Compute maximum size needed, both for inherent size
2378 and for total size. */
2379 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2381 if (spill_stack_slot[from_reg])
2383 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2385 mode = GET_MODE (spill_stack_slot[from_reg]);
2386 if (spill_stack_slot_width[from_reg] > total_size)
2387 total_size = spill_stack_slot_width[from_reg];
2389 /* Make a slot with that size. */
2390 x = assign_stack_local (mode, total_size,
2391 inherent_size == total_size ? 0 : -1);
2393 if (BYTES_BIG_ENDIAN)
2395 /* Cancel the big-endian correction done in assign_stack_local.
2396 Get the address of the beginning of the slot.
2397 This is so we can do a big-endian correction unconditionally
2399 adjust = GET_MODE_SIZE (mode) - total_size;
2401 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2404 plus_constant (XEXP (x, 0), adjust));
2406 spill_stack_slot[from_reg] = stack_slot;
2407 spill_stack_slot_width[from_reg] = total_size;
2410 /* On a big endian machine, the "address" of the slot
2411 is the address of the low part that fits its inherent mode. */
2412 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2413 adjust += (total_size - inherent_size);
2415 /* If we have any adjustment to make, or if the stack slot is the
2416 wrong mode, make a new stack slot. */
2417 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2419 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2420 plus_constant (XEXP (x, 0), adjust));
2422 /* If this was shared among registers, must ensure we never
2423 set it readonly since that can cause scheduling
2424 problems. Note we would only have in this adjustment
2425 case in any event, since the code above doesn't set it. */
2428 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2431 /* Save the stack slot for later. */
2432 reg_equiv_memory_loc[i] = x;
2436 /* Mark the slots in regs_ever_live for the hard regs
2437 used by pseudo-reg number REGNO. */
2440 mark_home_live (regno)
2443 register int i, lim;
2444 i = reg_renumber[regno];
2447 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2449 regs_ever_live[i++] = 1;
2452 /* This function handles the tracking of elimination offsets around branches.
2454 X is a piece of RTL being scanned.
2456 INSN is the insn that it came from, if any.
2458 INITIAL_P is non-zero if we are to set the offset to be the initial
2459 offset and zero if we are setting the offset of the label to be the
2463 set_label_offsets (x, insn, initial_p)
2468 enum rtx_code code = GET_CODE (x);
2471 struct elim_table *p;
2476 if (LABEL_REF_NONLOCAL_P (x))
2481 /* ... fall through ... */
2484 /* If we know nothing about this label, set the desired offsets. Note
2485 that this sets the offset at a label to be the offset before a label
2486 if we don't know anything about the label. This is not correct for
2487 the label after a BARRIER, but is the best guess we can make. If
2488 we guessed wrong, we will suppress an elimination that might have
2489 been possible had we been able to guess correctly. */
2491 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2493 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2494 offsets_at[CODE_LABEL_NUMBER (x)][i]
2495 = (initial_p ? reg_eliminate[i].initial_offset
2496 : reg_eliminate[i].offset);
2497 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2500 /* Otherwise, if this is the definition of a label and it is
2501 preceded by a BARRIER, set our offsets to the known offset of
2505 && (tem = prev_nonnote_insn (insn)) != 0
2506 && GET_CODE (tem) == BARRIER)
2507 set_offsets_for_label (insn);
2509 /* If neither of the above cases is true, compare each offset
2510 with those previously recorded and suppress any eliminations
2511 where the offsets disagree. */
2513 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2514 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2515 != (initial_p ? reg_eliminate[i].initial_offset
2516 : reg_eliminate[i].offset))
2517 reg_eliminate[i].can_eliminate = 0;
2522 set_label_offsets (PATTERN (insn), insn, initial_p);
2524 /* ... fall through ... */
2528 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2529 and hence must have all eliminations at their initial offsets. */
2530 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2531 if (REG_NOTE_KIND (tem) == REG_LABEL)
2532 set_label_offsets (XEXP (tem, 0), insn, 1);
2537 /* Each of the labels in the address vector must be at their initial
2538 offsets. We want the first field for ADDR_VEC and the second
2539 field for ADDR_DIFF_VEC. */
2541 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2542 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2547 /* We only care about setting PC. If the source is not RETURN,
2548 IF_THEN_ELSE, or a label, disable any eliminations not at
2549 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2550 isn't one of those possibilities. For branches to a label,
2551 call ourselves recursively.
2553 Note that this can disable elimination unnecessarily when we have
2554 a non-local goto since it will look like a non-constant jump to
2555 someplace in the current function. This isn't a significant
2556 problem since such jumps will normally be when all elimination
2557 pairs are back to their initial offsets. */
2559 if (SET_DEST (x) != pc_rtx)
2562 switch (GET_CODE (SET_SRC (x)))
2569 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2573 tem = XEXP (SET_SRC (x), 1);
2574 if (GET_CODE (tem) == LABEL_REF)
2575 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2576 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2579 tem = XEXP (SET_SRC (x), 2);
2580 if (GET_CODE (tem) == LABEL_REF)
2581 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2582 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2590 /* If we reach here, all eliminations must be at their initial
2591 offset because we are doing a jump to a variable address. */
2592 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2593 if (p->offset != p->initial_offset)
2594 p->can_eliminate = 0;
2602 /* Used for communication between the next two function to properly share
2603 the vector for an ASM_OPERANDS. */
2605 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2607 /* Scan X and replace any eliminable registers (such as fp) with a
2608 replacement (such as sp), plus an offset.
2610 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2611 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2612 MEM, we are allowed to replace a sum of a register and the constant zero
2613 with the register, which we cannot do outside a MEM. In addition, we need
2614 to record the fact that a register is referenced outside a MEM.
2616 If INSN is an insn, it is the insn containing X. If we replace a REG
2617 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2618 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2619 the REG is being modified.
2621 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2622 That's used when we eliminate in expressions stored in notes.
2623 This means, do not set ref_outside_mem even if the reference
2626 If we see a modification to a register we know about, take the
2627 appropriate action (see case SET, below).
2629 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2630 replacements done assuming all offsets are at their initial values. If
2631 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2632 encounter, return the actual location so that find_reloads will do
2633 the proper thing. */
2636 eliminate_regs (x, mem_mode, insn)
2638 enum machine_mode mem_mode;
2641 enum rtx_code code = GET_CODE (x);
2642 struct elim_table *ep;
2649 /* We can reach here without reload being run if we have an variable
2650 definition in a file with no functions (for exmaple). Ensure we
2651 have a valid elimination table in such cases. */
2652 if (reg_eliminate == NULL)
2671 /* This is only for the benefit of the debugging backends, which call
2672 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2673 removed after CSE. */
2674 new = eliminate_regs (XEXP (x, 0), 0, insn);
2675 if (GET_CODE (new) == MEM)
2676 return XEXP (new, 0);
2682 /* First handle the case where we encounter a bare register that
2683 is eliminable. Replace it with a PLUS. */
2684 if (regno < FIRST_PSEUDO_REGISTER)
2686 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2688 if (ep->from_rtx == x && ep->can_eliminate)
2691 /* Refs inside notes don't count for this purpose. */
2692 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2693 || GET_CODE (insn) == INSN_LIST)))
2694 ep->ref_outside_mem = 1;
2695 return plus_constant (ep->to_rtx, ep->previous_offset);
2702 /* If this is the sum of an eliminable register and a constant, rework
2704 if (GET_CODE (XEXP (x, 0)) == REG
2705 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2706 && CONSTANT_P (XEXP (x, 1)))
2708 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2710 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2713 /* Refs inside notes don't count for this purpose. */
2714 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2715 || GET_CODE (insn) == INSN_LIST)))
2716 ep->ref_outside_mem = 1;
2718 /* The only time we want to replace a PLUS with a REG (this
2719 occurs when the constant operand of the PLUS is the negative
2720 of the offset) is when we are inside a MEM. We won't want
2721 to do so at other times because that would change the
2722 structure of the insn in a way that reload can't handle.
2723 We special-case the commonest situation in
2724 eliminate_regs_in_insn, so just replace a PLUS with a
2725 PLUS here, unless inside a MEM. */
2726 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2727 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2730 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2731 plus_constant (XEXP (x, 1),
2732 ep->previous_offset));
2735 /* If the register is not eliminable, we are done since the other
2736 operand is a constant. */
2740 /* If this is part of an address, we want to bring any constant to the
2741 outermost PLUS. We will do this by doing register replacement in
2742 our operands and seeing if a constant shows up in one of them.
2744 We assume here this is part of an address (or a "load address" insn)
2745 since an eliminable register is not likely to appear in any other
2748 If we have (plus (eliminable) (reg)), we want to produce
2749 (plus (plus (replacement) (reg) (const))). If this was part of a
2750 normal add insn, (plus (replacement) (reg)) will be pushed as a
2751 reload. This is the desired action. */
2754 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2755 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2757 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2759 /* If one side is a PLUS and the other side is a pseudo that
2760 didn't get a hard register but has a reg_equiv_constant,
2761 we must replace the constant here since it may no longer
2762 be in the position of any operand. */
2763 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2764 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2765 && reg_renumber[REGNO (new1)] < 0
2766 && reg_equiv_constant != 0
2767 && reg_equiv_constant[REGNO (new1)] != 0)
2768 new1 = reg_equiv_constant[REGNO (new1)];
2769 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2770 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2771 && reg_renumber[REGNO (new0)] < 0
2772 && reg_equiv_constant[REGNO (new0)] != 0)
2773 new0 = reg_equiv_constant[REGNO (new0)];
2775 new = form_sum (new0, new1);
2777 /* As above, if we are not inside a MEM we do not want to
2778 turn a PLUS into something else. We might try to do so here
2779 for an addition of 0 if we aren't optimizing. */
2780 if (! mem_mode && GET_CODE (new) != PLUS)
2781 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2789 /* If this is the product of an eliminable register and a
2790 constant, apply the distribute law and move the constant out
2791 so that we have (plus (mult ..) ..). This is needed in order
2792 to keep load-address insns valid. This case is pathological.
2793 We ignore the possibility of overflow here. */
2794 if (GET_CODE (XEXP (x, 0)) == REG
2795 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2796 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2797 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2799 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2802 /* Refs inside notes don't count for this purpose. */
2803 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2804 || GET_CODE (insn) == INSN_LIST)))
2805 ep->ref_outside_mem = 1;
2808 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2809 ep->previous_offset * INTVAL (XEXP (x, 1)));
2812 /* ... fall through ... */
2817 case DIV: case UDIV:
2818 case MOD: case UMOD:
2819 case AND: case IOR: case XOR:
2820 case ROTATERT: case ROTATE:
2821 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2823 case GE: case GT: case GEU: case GTU:
2824 case LE: case LT: case LEU: case LTU:
2826 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2828 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2830 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2831 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2836 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2839 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2840 if (new != XEXP (x, 0))
2841 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2844 /* ... fall through ... */
2847 /* Now do eliminations in the rest of the chain. If this was
2848 an EXPR_LIST, this might result in allocating more memory than is
2849 strictly needed, but it simplifies the code. */
2852 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2853 if (new != XEXP (x, 1))
2854 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2863 if (ep->to_rtx == XEXP (x, 0))
2865 int size = GET_MODE_SIZE (mem_mode);
2867 /* If more bytes than MEM_MODE are pushed, account for them. */
2868 #ifdef PUSH_ROUNDING
2869 if (ep->to_rtx == stack_pointer_rtx)
2870 size = PUSH_ROUNDING (size);
2872 if (code == PRE_DEC || code == POST_DEC)
2878 /* Fall through to generic unary operation case. */
2879 case STRICT_LOW_PART:
2881 case SIGN_EXTEND: case ZERO_EXTEND:
2882 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2883 case FLOAT: case FIX:
2884 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2888 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2889 if (new != XEXP (x, 0))
2890 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2894 /* Similar to above processing, but preserve SUBREG_WORD.
2895 Convert (subreg (mem)) to (mem) if not paradoxical.
2896 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2897 pseudo didn't get a hard reg, we must replace this with the
2898 eliminated version of the memory location because push_reloads
2899 may do the replacement in certain circumstances. */
2900 if (GET_CODE (SUBREG_REG (x)) == REG
2901 && (GET_MODE_SIZE (GET_MODE (x))
2902 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2903 && reg_equiv_memory_loc != 0
2904 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2907 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2910 /* If we didn't change anything, we must retain the pseudo. */
2911 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2912 new = SUBREG_REG (x);
2915 /* In this case, we must show that the pseudo is used in this
2916 insn so that delete_output_reload will do the right thing. */
2917 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2918 && GET_CODE (insn) != INSN_LIST)
2919 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
2922 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2924 /* Ensure NEW isn't shared in case we have to reload it. */
2925 new = copy_rtx (new);
2928 new = SUBREG_REG (x);
2932 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2934 if (new != XEXP (x, 0))
2936 int x_size = GET_MODE_SIZE (GET_MODE (x));
2937 int new_size = GET_MODE_SIZE (GET_MODE (new));
2939 if (GET_CODE (new) == MEM
2940 && ((x_size < new_size
2941 #ifdef WORD_REGISTER_OPERATIONS
2942 /* On these machines, combine can create rtl of the form
2943 (set (subreg:m1 (reg:m2 R) 0) ...)
2944 where m1 < m2, and expects something interesting to
2945 happen to the entire word. Moreover, it will use the
2946 (reg:m2 R) later, expecting all bits to be preserved.
2947 So if the number of words is the same, preserve the
2948 subreg so that push_reloads can see it. */
2949 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2952 || (x_size == new_size))
2955 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2956 enum machine_mode mode = GET_MODE (x);
2958 if (BYTES_BIG_ENDIAN)
2959 offset += (MIN (UNITS_PER_WORD,
2960 GET_MODE_SIZE (GET_MODE (new)))
2961 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2963 PUT_MODE (new, mode);
2964 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2968 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2974 /* If using a register that is the source of an eliminate we still
2975 think can be performed, note it cannot be performed since we don't
2976 know how this register is used. */
2977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2978 if (ep->from_rtx == XEXP (x, 0))
2979 ep->can_eliminate = 0;
2981 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2982 if (new != XEXP (x, 0))
2983 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2987 /* If clobbering a register that is the replacement register for an
2988 elimination we still think can be performed, note that it cannot
2989 be performed. Otherwise, we need not be concerned about it. */
2990 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2991 if (ep->to_rtx == XEXP (x, 0))
2992 ep->can_eliminate = 0;
2994 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2995 if (new != XEXP (x, 0))
2996 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3002 /* Properly handle sharing input and constraint vectors. */
3003 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3005 /* When we come to a new vector not seen before,
3006 scan all its elements; keep the old vector if none
3007 of them changes; otherwise, make a copy. */
3008 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3009 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3010 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3011 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3014 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3015 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3018 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3019 new_asm_operands_vec = old_asm_operands_vec;
3021 new_asm_operands_vec
3022 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3025 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3026 if (new_asm_operands_vec == old_asm_operands_vec)
3029 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3030 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3031 ASM_OPERANDS_OUTPUT_IDX (x),
3032 new_asm_operands_vec,
3033 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3034 ASM_OPERANDS_SOURCE_FILE (x),
3035 ASM_OPERANDS_SOURCE_LINE (x));
3036 new->volatil = x->volatil;
3041 /* Check for setting a register that we know about. */
3042 if (GET_CODE (SET_DEST (x)) == REG)
3044 /* See if this is setting the replacement register for an
3047 If DEST is the hard frame pointer, we do nothing because we
3048 assume that all assignments to the frame pointer are for
3049 non-local gotos and are being done at a time when they are valid
3050 and do not disturb anything else. Some machines want to
3051 eliminate a fake argument pointer (or even a fake frame pointer)
3052 with either the real frame or the stack pointer. Assignments to
3053 the hard frame pointer must not prevent this elimination. */
3055 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3057 if (ep->to_rtx == SET_DEST (x)
3058 && SET_DEST (x) != hard_frame_pointer_rtx)
3060 /* If it is being incremented, adjust the offset. Otherwise,
3061 this elimination can't be done. */
3062 rtx src = SET_SRC (x);
3064 if (GET_CODE (src) == PLUS
3065 && XEXP (src, 0) == SET_DEST (x)
3066 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3067 ep->offset -= INTVAL (XEXP (src, 1));
3069 ep->can_eliminate = 0;
3072 /* Now check to see we are assigning to a register that can be
3073 eliminated. If so, it must be as part of a PARALLEL, since we
3074 will not have been called if this is a single SET. So indicate
3075 that we can no longer eliminate this reg. */
3076 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3078 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3079 ep->can_eliminate = 0;
3082 /* Now avoid the loop below in this common case. */
3084 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3085 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3087 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3088 write a CLOBBER insn. */
3089 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3090 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3091 && GET_CODE (insn) != INSN_LIST)
3092 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3094 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3095 return gen_rtx_SET (VOIDmode, new0, new1);
3101 /* This is only for the benefit of the debugging backends, which call
3102 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3103 removed after CSE. */
3104 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3105 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3107 /* Our only special processing is to pass the mode of the MEM to our
3108 recursive call and copy the flags. While we are here, handle this
3109 case more efficiently. */
3110 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3111 if (new != XEXP (x, 0))
3113 new = gen_rtx_MEM (GET_MODE (x), new);
3114 new->volatil = x->volatil;
3115 new->unchanging = x->unchanging;
3116 new->in_struct = x->in_struct;
3126 /* Process each of our operands recursively. If any have changed, make a
3128 fmt = GET_RTX_FORMAT (code);
3129 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3133 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3134 if (new != XEXP (x, i) && ! copied)
3136 rtx new_x = rtx_alloc (code);
3137 bcopy ((char *) x, (char *) new_x,
3138 (sizeof (*new_x) - sizeof (new_x->fld)
3139 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3145 else if (*fmt == 'E')
3148 for (j = 0; j < XVECLEN (x, i); j++)
3150 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3151 if (new != XVECEXP (x, i, j) && ! copied_vec)
3153 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3157 rtx new_x = rtx_alloc (code);
3158 bcopy ((char *) x, (char *) new_x,
3159 (sizeof (*new_x) - sizeof (new_x->fld)
3160 + (sizeof (new_x->fld[0])
3161 * GET_RTX_LENGTH (code))));
3165 XVEC (x, i) = new_v;
3168 XVECEXP (x, i, j) = new;
3176 /* Scan INSN and eliminate all eliminable registers in it.
3178 If REPLACE is nonzero, do the replacement destructively. Also
3179 delete the insn as dead it if it is setting an eliminable register.
3181 If REPLACE is zero, do all our allocations in reload_obstack.
3183 If no eliminations were done and this insn doesn't require any elimination
3184 processing (these are not identical conditions: it might be updating sp,
3185 but not referencing fp; this needs to be seen during reload_as_needed so
3186 that the offset between fp and sp can be taken into consideration), zero
3187 is returned. Otherwise, 1 is returned. */
3190 eliminate_regs_in_insn (insn, replace)
3194 rtx old_body = PATTERN (insn);
3195 rtx old_set = single_set (insn);
3198 struct elim_table *ep;
3201 push_obstacks (&reload_obstack, &reload_obstack);
3203 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3204 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3206 /* Check for setting an eliminable register. */
3207 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3208 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3210 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3211 /* If this is setting the frame pointer register to the
3212 hardware frame pointer register and this is an elimination
3213 that will be done (tested above), this insn is really
3214 adjusting the frame pointer downward to compensate for
3215 the adjustment done before a nonlocal goto. */
3216 if (ep->from == FRAME_POINTER_REGNUM
3217 && ep->to == HARD_FRAME_POINTER_REGNUM)
3219 rtx src = SET_SRC (old_set);
3221 rtx prev_insn, prev_set;
3223 if (src == ep->to_rtx)
3225 else if (GET_CODE (src) == PLUS
3226 && GET_CODE (XEXP (src, 0)) == CONST_INT
3227 && XEXP (src, 1) == ep->to_rtx)
3228 offset = INTVAL (XEXP (src, 0)), ok = 1;
3229 else if (GET_CODE (src) == PLUS
3230 && GET_CODE (XEXP (src, 1)) == CONST_INT
3231 && XEXP (src, 0) == ep->to_rtx)
3232 offset = INTVAL (XEXP (src, 1)), ok = 1;
3233 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3234 && (prev_set = single_set (prev_insn)) != 0
3235 && rtx_equal_p (SET_DEST (prev_set), src))
3237 src = SET_SRC (prev_set);
3238 if (src == ep->to_rtx)
3240 else if (GET_CODE (src) == PLUS
3241 && GET_CODE (XEXP (src, 0)) == CONST_INT
3242 && XEXP (src, 1) == ep->to_rtx)
3243 offset = INTVAL (XEXP (src, 0)), ok = 1;
3244 else if (GET_CODE (src) == PLUS
3245 && GET_CODE (XEXP (src, 1)) == CONST_INT
3246 && XEXP (src, 0) == ep->to_rtx)
3247 offset = INTVAL (XEXP (src, 1)), ok = 1;
3255 = plus_constant (ep->to_rtx, offset - ep->offset);
3257 /* First see if this insn remains valid when we
3258 make the change. If not, keep the INSN_CODE
3259 the same and let reload fit it up. */
3260 validate_change (insn, &SET_SRC (old_set), src, 1);
3261 validate_change (insn, &SET_DEST (old_set),
3263 if (! apply_change_group ())
3265 SET_SRC (old_set) = src;
3266 SET_DEST (old_set) = ep->to_rtx;
3276 /* In this case this insn isn't serving a useful purpose. We
3277 will delete it in reload_as_needed once we know that this
3278 elimination is, in fact, being done.
3280 If REPLACE isn't set, we can't delete this insn, but needn't
3281 process it since it won't be used unless something changes. */
3283 delete_dead_insn (insn);
3288 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3289 in the insn is the negative of the offset in FROM. Substitute
3290 (set (reg) (reg to)) for the insn and change its code.
3292 We have to do this here, rather than in eliminate_regs, so that we can
3293 change the insn code. */
3295 if (GET_CODE (SET_SRC (old_set)) == PLUS
3296 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3297 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3298 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3300 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3301 && ep->can_eliminate)
3303 /* We must stop at the first elimination that will be used.
3304 If this one would replace the PLUS with a REG, do it
3305 now. Otherwise, quit the loop and let eliminate_regs
3306 do its normal replacement. */
3307 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3309 /* We assume here that we don't need a PARALLEL of
3310 any CLOBBERs for this assignment. There's not
3311 much we can do if we do need it. */
3312 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3315 INSN_CODE (insn) = -1;
3324 old_asm_operands_vec = 0;
3326 /* Replace the body of this insn with a substituted form. If we changed
3327 something, return non-zero.
3329 If we are replacing a body that was a (set X (plus Y Z)), try to
3330 re-recognize the insn. We do this in case we had a simple addition
3331 but now can do this as a load-address. This saves an insn in this
3334 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3335 if (new_body != old_body)
3337 /* If we aren't replacing things permanently and we changed something,
3338 make another copy to ensure that all the RTL is new. Otherwise
3339 things can go wrong if find_reload swaps commutative operands
3340 and one is inside RTL that has been copied while the other is not. */
3342 /* Don't copy an asm_operands because (1) there's no need and (2)
3343 copy_rtx can't do it properly when there are multiple outputs. */
3344 if (! replace && asm_noperands (old_body) < 0)
3345 new_body = copy_rtx (new_body);
3347 /* If we had a move insn but now we don't, rerecognize it. This will
3348 cause spurious re-recognition if the old move had a PARALLEL since
3349 the new one still will, but we can't call single_set without
3350 having put NEW_BODY into the insn and the re-recognition won't
3351 hurt in this rare case. */
3353 && ((GET_CODE (SET_SRC (old_set)) == REG
3354 && (GET_CODE (new_body) != SET
3355 || GET_CODE (SET_SRC (new_body)) != REG))
3356 /* If this was a load from or store to memory, compare
3357 the MEM in recog_operand to the one in the insn. If they
3358 are not equal, then rerecognize the insn. */
3360 && ((GET_CODE (SET_SRC (old_set)) == MEM
3361 && SET_SRC (old_set) != recog_operand[1])
3362 || (GET_CODE (SET_DEST (old_set)) == MEM
3363 && SET_DEST (old_set) != recog_operand[0])))
3364 /* If this was an add insn before, rerecognize. */
3365 || GET_CODE (SET_SRC (old_set)) == PLUS))
3367 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3368 /* If recognition fails, store the new body anyway.
3369 It's normal to have recognition failures here
3370 due to bizarre memory addresses; reloading will fix them. */
3371 PATTERN (insn) = new_body;
3374 PATTERN (insn) = new_body;
3379 /* Loop through all elimination pairs. See if any have changed.
3381 We also detect a cases where register elimination cannot be done,
3382 namely, if a register would be both changed and referenced outside a MEM
3383 in the resulting insn since such an insn is often undefined and, even if
3384 not, we cannot know what meaning will be given to it. Note that it is
3385 valid to have a register used in an address in an insn that changes it
3386 (presumably with a pre- or post-increment or decrement).
3388 If anything changes, return nonzero. */
3390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3392 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3393 ep->can_eliminate = 0;
3395 ep->ref_outside_mem = 0;
3397 if (ep->previous_offset != ep->offset)
3402 /* If we changed something, perform elimination in REG_NOTES. This is
3403 needed even when REPLACE is zero because a REG_DEAD note might refer
3404 to a register that we eliminate and could cause a different number
3405 of spill registers to be needed in the final reload pass than in
3407 if (val && REG_NOTES (insn) != 0)
3408 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3416 /* Loop through all elimination pairs.
3417 Recalculate the number not at initial offset.
3419 Compute the maximum offset (minimum offset if the stack does not
3420 grow downward) for each elimination pair. */
3423 update_eliminable_offsets ()
3425 struct elim_table *ep;
3427 num_not_at_initial_offset = 0;
3428 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3430 ep->previous_offset = ep->offset;
3431 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3432 num_not_at_initial_offset++;
3436 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3437 replacement we currently believe is valid, mark it as not eliminable if X
3438 modifies DEST in any way other than by adding a constant integer to it.
3440 If DEST is the frame pointer, we do nothing because we assume that
3441 all assignments to the hard frame pointer are nonlocal gotos and are being
3442 done at a time when they are valid and do not disturb anything else.
3443 Some machines want to eliminate a fake argument pointer with either the
3444 frame or stack pointer. Assignments to the hard frame pointer must not
3445 prevent this elimination.
3447 Called via note_stores from reload before starting its passes to scan
3448 the insns of the function. */
3451 mark_not_eliminable (dest, x)
3455 register unsigned int i;
3457 /* A SUBREG of a hard register here is just changing its mode. We should
3458 not see a SUBREG of an eliminable hard register, but check just in
3460 if (GET_CODE (dest) == SUBREG)
3461 dest = SUBREG_REG (dest);
3463 if (dest == hard_frame_pointer_rtx)
3466 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3467 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3468 && (GET_CODE (x) != SET
3469 || GET_CODE (SET_SRC (x)) != PLUS
3470 || XEXP (SET_SRC (x), 0) != dest
3471 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3473 reg_eliminate[i].can_eliminate_previous
3474 = reg_eliminate[i].can_eliminate = 0;
3479 /* Verify that the initial elimination offsets did not change since the
3480 last call to set_initial_elim_offsets. This is used to catch cases
3481 where something illegal happened during reload_as_needed that could
3482 cause incorrect code to be generated if we did not check for it. */
3484 verify_initial_elim_offsets ()
3488 #ifdef ELIMINABLE_REGS
3489 struct elim_table *ep;
3491 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3493 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3494 if (t != ep->initial_offset)
3498 INITIAL_FRAME_POINTER_OFFSET (t);
3499 if (t != reg_eliminate[0].initial_offset)
3504 /* Reset all offsets on eliminable registers to their initial values. */
3506 set_initial_elim_offsets ()
3508 struct elim_table *ep = reg_eliminate;
3510 #ifdef ELIMINABLE_REGS
3511 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3513 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3514 ep->previous_offset = ep->offset = ep->initial_offset;
3517 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3518 ep->previous_offset = ep->offset = ep->initial_offset;
3521 num_not_at_initial_offset = 0;
3524 /* Initialize the known label offsets.
3525 Set a known offset for each forced label to be at the initial offset
3526 of each elimination. We do this because we assume that all
3527 computed jumps occur from a location where each elimination is
3528 at its initial offset.
3529 For all other labels, show that we don't know the offsets. */
3532 set_initial_label_offsets ()
3535 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3537 for (x = forced_labels; x; x = XEXP (x, 1))
3539 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3542 /* Set all elimination offsets to the known values for the code label given
3545 set_offsets_for_label (insn)
3549 int label_nr = CODE_LABEL_NUMBER (insn);
3550 struct elim_table *ep;
3552 num_not_at_initial_offset = 0;
3553 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3555 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3556 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3557 num_not_at_initial_offset++;
3561 /* See if anything that happened changes which eliminations are valid.
3562 For example, on the Sparc, whether or not the frame pointer can
3563 be eliminated can depend on what registers have been used. We need
3564 not check some conditions again (such as flag_omit_frame_pointer)
3565 since they can't have changed. */
3568 update_eliminables (pset)
3571 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3572 int previous_frame_pointer_needed = frame_pointer_needed;
3574 struct elim_table *ep;
3576 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3577 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3578 #ifdef ELIMINABLE_REGS
3579 || ! CAN_ELIMINATE (ep->from, ep->to)
3582 ep->can_eliminate = 0;
3584 /* Look for the case where we have discovered that we can't replace
3585 register A with register B and that means that we will now be
3586 trying to replace register A with register C. This means we can
3587 no longer replace register C with register B and we need to disable
3588 such an elimination, if it exists. This occurs often with A == ap,
3589 B == sp, and C == fp. */
3591 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3593 struct elim_table *op;
3594 register int new_to = -1;
3596 if (! ep->can_eliminate && ep->can_eliminate_previous)
3598 /* Find the current elimination for ep->from, if there is a
3600 for (op = reg_eliminate;
3601 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3602 if (op->from == ep->from && op->can_eliminate)
3608 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3610 for (op = reg_eliminate;
3611 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3612 if (op->from == new_to && op->to == ep->to)
3613 op->can_eliminate = 0;
3617 /* See if any registers that we thought we could eliminate the previous
3618 time are no longer eliminable. If so, something has changed and we
3619 must spill the register. Also, recompute the number of eliminable
3620 registers and see if the frame pointer is needed; it is if there is
3621 no elimination of the frame pointer that we can perform. */
3623 frame_pointer_needed = 1;
3624 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3626 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3627 && ep->to != HARD_FRAME_POINTER_REGNUM)
3628 frame_pointer_needed = 0;
3630 if (! ep->can_eliminate && ep->can_eliminate_previous)
3632 ep->can_eliminate_previous = 0;
3633 SET_HARD_REG_BIT (*pset, ep->from);
3638 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3639 /* If we didn't need a frame pointer last time, but we do now, spill
3640 the hard frame pointer. */
3641 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3642 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3646 /* Initialize the table of registers to eliminate. */
3650 struct elim_table *ep;
3651 #ifdef ELIMINABLE_REGS
3652 struct elim_table_1 *ep1;
3657 reg_eliminate = (struct elim_table *)
3658 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3659 bzero ((PTR) reg_eliminate,
3660 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3663 /* Does this function require a frame pointer? */
3665 frame_pointer_needed = (! flag_omit_frame_pointer
3666 #ifdef EXIT_IGNORE_STACK
3667 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3668 and restore sp for alloca. So we can't eliminate
3669 the frame pointer in that case. At some point,
3670 we should improve this by emitting the
3671 sp-adjusting insns for this case. */
3672 || (current_function_calls_alloca
3673 && EXIT_IGNORE_STACK)
3675 || FRAME_POINTER_REQUIRED);
3679 #ifdef ELIMINABLE_REGS
3680 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3681 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3683 ep->from = ep1->from;
3685 ep->can_eliminate = ep->can_eliminate_previous
3686 = (CAN_ELIMINATE (ep->from, ep->to)
3687 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3690 reg_eliminate[0].from = reg_eliminate_1[0].from;
3691 reg_eliminate[0].to = reg_eliminate_1[0].to;
3692 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3693 = ! frame_pointer_needed;
3696 /* Count the number of eliminable registers and build the FROM and TO
3697 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3698 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3699 We depend on this. */
3700 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3702 num_eliminable += ep->can_eliminate;
3703 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3704 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3708 /* Kick all pseudos out of hard register REGNO.
3709 If DUMPFILE is nonzero, log actions taken on that file.
3711 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3712 because we found we can't eliminate some register. In the case, no pseudos
3713 are allowed to be in the register, even if they are only in a block that
3714 doesn't require spill registers, unlike the case when we are spilling this
3715 hard reg to produce another spill register.
3717 Return nonzero if any pseudos needed to be kicked out. */
3720 spill_hard_reg (regno, dumpfile, cant_eliminate)
3729 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3730 regs_ever_live[regno] = 1;
3733 /* Spill every pseudo reg that was allocated to this reg
3734 or to something that overlaps this reg. */
3736 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3737 if (reg_renumber[i] >= 0
3738 && reg_renumber[i] <= regno
3740 + HARD_REGNO_NREGS (reg_renumber[i],
3741 PSEUDO_REGNO_MODE (i))
3743 SET_REGNO_REG_SET (spilled_pseudos, i);
3746 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3747 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3749 ior_hard_reg_set (set1, set2)
3750 HARD_REG_SET *set1, *set2;
3752 IOR_HARD_REG_SET (*set1, *set2);
3755 /* After find_reload_regs has been run for all insn that need reloads,
3756 and/or spill_hard_regs was called, this function is used to actually
3757 spill pseudo registers and try to reallocate them. It also sets up the
3758 spill_regs array for use by choose_reload_regs. */
3761 finish_spills (global, dumpfile)
3765 struct insn_chain *chain;
3766 int something_changed = 0;
3769 /* Build the spill_regs array for the function. */
3770 /* If there are some registers still to eliminate and one of the spill regs
3771 wasn't ever used before, additional stack space may have to be
3772 allocated to store this register. Thus, we may have changed the offset
3773 between the stack and frame pointers, so mark that something has changed.
3775 One might think that we need only set VAL to 1 if this is a call-used
3776 register. However, the set of registers that must be saved by the
3777 prologue is not identical to the call-used set. For example, the
3778 register used by the call insn for the return PC is a call-used register,
3779 but must be saved by the prologue. */
3782 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3783 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3785 spill_reg_order[i] = n_spills;
3786 spill_regs[n_spills++] = i;
3787 if (num_eliminable && ! regs_ever_live[i])
3788 something_changed = 1;
3789 regs_ever_live[i] = 1;
3792 spill_reg_order[i] = -1;
3794 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3795 if (REGNO_REG_SET_P (spilled_pseudos, i))
3797 /* Record the current hard register the pseudo is allocated to in
3798 pseudo_previous_regs so we avoid reallocating it to the same
3799 hard reg in a later pass. */
3800 if (reg_renumber[i] < 0)
3802 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3803 /* Mark it as no longer having a hard register home. */
3804 reg_renumber[i] = -1;
3805 /* We will need to scan everything again. */
3806 something_changed = 1;
3809 /* Retry global register allocation if possible. */
3812 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3813 /* For every insn that needs reloads, set the registers used as spill
3814 regs in pseudo_forbidden_regs for every pseudo live across the
3816 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3818 EXECUTE_IF_SET_IN_REG_SET
3819 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3821 ior_hard_reg_set (pseudo_forbidden_regs + i,
3822 &chain->used_spill_regs);
3824 EXECUTE_IF_SET_IN_REG_SET
3825 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3827 ior_hard_reg_set (pseudo_forbidden_regs + i,
3828 &chain->used_spill_regs);
3832 /* Retry allocating the spilled pseudos. For each reg, merge the
3833 various reg sets that indicate which hard regs can't be used,
3834 and call retry_global_alloc.
3835 We change spill_pseudos here to only contain pseudos that did not
3836 get a new hard register. */
3837 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3838 if (reg_old_renumber[i] != reg_renumber[i])
3840 HARD_REG_SET forbidden;
3841 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3842 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3843 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3844 retry_global_alloc (i, forbidden);
3845 if (reg_renumber[i] >= 0)
3846 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3850 /* Fix up the register information in the insn chain.
3851 This involves deleting those of the spilled pseudos which did not get
3852 a new hard register home from the live_{before,after} sets. */
3853 for (chain = reload_insn_chain; chain; chain = chain->next)
3855 HARD_REG_SET used_by_pseudos;
3856 HARD_REG_SET used_by_pseudos2;
3858 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3859 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3861 /* Mark any unallocated hard regs as available for spills. That
3862 makes inheritance work somewhat better. */
3863 if (chain->need_reload)
3865 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3866 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3867 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3869 /* Save the old value for the sanity test below. */
3870 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3872 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3873 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3874 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3875 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3877 /* Make sure we only enlarge the set. */
3878 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3884 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3885 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3887 int regno = reg_renumber[i];
3888 if (reg_old_renumber[i] == regno)
3891 alter_reg (i, reg_old_renumber[i]);
3892 reg_old_renumber[i] = regno;
3896 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3898 fprintf (dumpfile, " Register %d now in %d.\n\n",
3899 i, reg_renumber[i]);
3903 return something_changed;
3906 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3907 Also mark any hard registers used to store user variables as
3908 forbidden from being used for spill registers. */
3911 scan_paradoxical_subregs (x)
3916 register enum rtx_code code = GET_CODE (x);
3922 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3923 && REG_USERVAR_P (x))
3924 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3940 if (GET_CODE (SUBREG_REG (x)) == REG
3941 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3942 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3943 = GET_MODE_SIZE (GET_MODE (x));
3950 fmt = GET_RTX_FORMAT (code);
3951 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3954 scan_paradoxical_subregs (XEXP (x, i));
3955 else if (fmt[i] == 'E')
3958 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3959 scan_paradoxical_subregs (XVECEXP (x, i, j));
3965 hard_reg_use_compare (p1p, p2p)
3966 const GENERIC_PTR p1p;
3967 const GENERIC_PTR p2p;
3969 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
3970 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
3971 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
3972 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
3974 return p1->regno - p2->regno;
3979 if (p1->uses > p2->uses)
3981 if (p1->uses < p2->uses)
3983 /* If regs are equally good, sort by regno,
3984 so that the results of qsort leave nothing to chance. */
3985 return p1->regno - p2->regno;
3988 /* Used for communication between order_regs_for_reload and count_pseudo.
3989 Used to avoid counting one pseudo twice. */
3990 static regset pseudos_counted;
3992 /* Update the costs in N_USES, considering that pseudo REG is live. */
3994 count_pseudo (n_uses, reg)
3995 struct hard_reg_n_uses *n_uses;
3998 int r = reg_renumber[reg];
4001 if (REGNO_REG_SET_P (pseudos_counted, reg))
4003 SET_REGNO_REG_SET (pseudos_counted, reg);
4008 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4010 n_uses[r++].uses += REG_N_REFS (reg);
4012 /* Choose the order to consider regs for use as reload registers
4013 based on how much trouble would be caused by spilling one.
4014 Store them in order of decreasing preference in potential_reload_regs. */
4017 order_regs_for_reload (chain)
4018 struct insn_chain *chain;
4022 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4024 pseudos_counted = ALLOCA_REG_SET ();
4026 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4028 /* Count number of uses of each hard reg by pseudo regs allocated to it
4029 and then order them by decreasing use. */
4031 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4035 hard_reg_n_uses[i].regno = i;
4036 hard_reg_n_uses[i].uses = 0;
4038 /* Test the various reasons why we can't use a register for
4039 spilling in this insn. */
4041 || REGNO_REG_SET_P (chain->live_before, i)
4042 || REGNO_REG_SET_P (chain->live_after, i))
4044 SET_HARD_REG_BIT (bad_spill_regs, i);
4048 /* Now find out which pseudos are allocated to it, and update
4050 CLEAR_REG_SET (pseudos_counted);
4052 EXECUTE_IF_SET_IN_REG_SET
4053 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4055 count_pseudo (hard_reg_n_uses, j);
4057 EXECUTE_IF_SET_IN_REG_SET
4058 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4060 count_pseudo (hard_reg_n_uses, j);
4064 FREE_REG_SET (pseudos_counted);
4066 /* Prefer registers not so far used, for use in temporary loading.
4067 Among them, if REG_ALLOC_ORDER is defined, use that order.
4068 Otherwise, prefer registers not preserved by calls. */
4070 #ifdef REG_ALLOC_ORDER
4071 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4073 int regno = reg_alloc_order[i];
4075 if (hard_reg_n_uses[regno].uses == 0
4076 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4077 potential_reload_regs[o++] = regno;
4080 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4082 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4083 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4084 potential_reload_regs[o++] = i;
4086 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4088 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4089 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4090 potential_reload_regs[o++] = i;
4094 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4095 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4097 /* Now add the regs that are already used,
4098 preferring those used less often. The fixed and otherwise forbidden
4099 registers will be at the end of this list. */
4101 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4102 if (hard_reg_n_uses[i].uses != 0
4103 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4104 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4105 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4106 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4107 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4110 /* Reload pseudo-registers into hard regs around each insn as needed.
4111 Additional register load insns are output before the insn that needs it
4112 and perhaps store insns after insns that modify the reloaded pseudo reg.
4114 reg_last_reload_reg and reg_reloaded_contents keep track of
4115 which registers are already available in reload registers.
4116 We update these for the reloads that we perform,
4117 as the insns are scanned. */
4120 reload_as_needed (live_known)
4123 struct insn_chain *chain;
4127 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4128 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4129 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4130 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4131 reg_has_output_reload = (char *) alloca (max_regno);
4132 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4134 set_initial_elim_offsets ();
4136 for (chain = reload_insn_chain; chain; chain = chain->next)
4139 rtx insn = chain->insn;
4140 rtx old_next = NEXT_INSN (insn);
4142 /* If we pass a label, copy the offsets from the label information
4143 into the current offsets of each elimination. */
4144 if (GET_CODE (insn) == CODE_LABEL)
4145 set_offsets_for_label (insn);
4147 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4149 rtx oldpat = PATTERN (insn);
4151 /* If this is a USE and CLOBBER of a MEM, ensure that any
4152 references to eliminable registers have been removed. */
4154 if ((GET_CODE (PATTERN (insn)) == USE
4155 || GET_CODE (PATTERN (insn)) == CLOBBER)
4156 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4157 XEXP (XEXP (PATTERN (insn), 0), 0)
4158 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4159 GET_MODE (XEXP (PATTERN (insn), 0)),
4162 /* If we need to do register elimination processing, do so.
4163 This might delete the insn, in which case we are done. */
4164 if (num_eliminable && chain->need_elim)
4166 eliminate_regs_in_insn (insn, 1);
4167 if (GET_CODE (insn) == NOTE)
4169 update_eliminable_offsets ();
4174 /* If need_elim is nonzero but need_reload is zero, one might think
4175 that we could simply set n_reloads to 0. However, find_reloads
4176 could have done some manipulation of the insn (such as swapping
4177 commutative operands), and these manipulations are lost during
4178 the first pass for every insn that needs register elimination.
4179 So the actions of find_reloads must be redone here. */
4181 if (! chain->need_elim && ! chain->need_reload
4182 && ! chain->need_operand_change)
4184 /* First find the pseudo regs that must be reloaded for this insn.
4185 This info is returned in the tables reload_... (see reload.h).
4186 Also modify the body of INSN by substituting RELOAD
4187 rtx's for those pseudo regs. */
4190 bzero (reg_has_output_reload, max_regno);
4191 CLEAR_HARD_REG_SET (reg_is_output_reload);
4193 find_reloads (insn, 1, spill_indirect_levels, live_known,
4197 if (num_eliminable && chain->need_elim)
4198 update_eliminable_offsets ();
4202 rtx next = NEXT_INSN (insn);
4205 prev = PREV_INSN (insn);
4207 /* Now compute which reload regs to reload them into. Perhaps
4208 reusing reload regs from previous insns, or else output
4209 load insns to reload them. Maybe output store insns too.
4210 Record the choices of reload reg in reload_reg_rtx. */
4211 choose_reload_regs (chain);
4213 /* Merge any reloads that we didn't combine for fear of
4214 increasing the number of spill registers needed but now
4215 discover can be safely merged. */
4216 if (SMALL_REGISTER_CLASSES)
4217 merge_assigned_reloads (insn);
4219 /* Generate the insns to reload operands into or out of
4220 their reload regs. */
4221 emit_reload_insns (chain);
4223 /* Substitute the chosen reload regs from reload_reg_rtx
4224 into the insn's body (or perhaps into the bodies of other
4225 load and store insn that we just made for reloading
4226 and that we moved the structure into). */
4229 /* If this was an ASM, make sure that all the reload insns
4230 we have generated are valid. If not, give an error
4233 if (asm_noperands (PATTERN (insn)) >= 0)
4234 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4235 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4236 && (recog_memoized (p) < 0
4237 || (extract_insn (p), ! constrain_operands (1))))
4239 error_for_asm (insn,
4240 "`asm' operand requires impossible reload");
4242 NOTE_SOURCE_FILE (p) = 0;
4243 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4246 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4247 is no longer validly lying around to save a future reload.
4248 Note that this does not detect pseudos that were reloaded
4249 for this insn in order to be stored in
4250 (obeying register constraints). That is correct; such reload
4251 registers ARE still valid. */
4252 note_stores (oldpat, forget_old_reloads_1);
4254 /* There may have been CLOBBER insns placed after INSN. So scan
4255 between INSN and NEXT and use them to forget old reloads. */
4256 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4257 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4258 note_stores (PATTERN (x), forget_old_reloads_1);
4261 /* Likewise for regs altered by auto-increment in this insn.
4262 REG_INC notes have been changed by reloading:
4263 find_reloads_address_1 records substitutions for them,
4264 which have been performed by subst_reloads above. */
4265 for (i = n_reloads - 1; i >= 0; i--)
4267 rtx in_reg = reload_in_reg[i];
4270 enum rtx_code code = GET_CODE (in_reg);
4271 /* PRE_INC / PRE_DEC will have the reload register ending up
4272 with the same value as the stack slot, but that doesn't
4273 hold true for POST_INC / POST_DEC. Either we have to
4274 convert the memory access to a true POST_INC / POST_DEC,
4275 or we can't use the reload register for inheritance. */
4276 if ((code == POST_INC || code == POST_DEC)
4277 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4278 REGNO (reload_reg_rtx[i]))
4279 /* Make sure it is the inc/dec pseudo, and not
4280 some other (e.g. output operand) pseudo. */
4281 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4282 == REGNO (XEXP (in_reg, 0))))
4285 rtx reload_reg = reload_reg_rtx[i];
4286 enum machine_mode mode = GET_MODE (reload_reg);
4290 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4292 /* We really want to ignore REG_INC notes here, so
4293 use PATTERN (p) as argument to reg_set_p . */
4294 if (reg_set_p (reload_reg, PATTERN (p)))
4296 n = count_occurrences (PATTERN (p), reload_reg);
4300 n = validate_replace_rtx (reload_reg,
4301 gen_rtx (code, mode,
4306 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4309 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4313 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4314 /* Likewise for regs altered by auto-increment in this insn.
4315 But note that the reg-notes are not changed by reloading:
4316 they still contain the pseudo-regs, not the spill regs. */
4317 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4318 if (REG_NOTE_KIND (x) == REG_INC)
4320 /* See if this pseudo reg was reloaded in this insn.
4321 If so, its last-reload info is still valid
4322 because it is based on this insn's reload. */
4323 for (i = 0; i < n_reloads; i++)
4324 if (reload_out[i] == XEXP (x, 0))
4328 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4333 /* A reload reg's contents are unknown after a label. */
4334 if (GET_CODE (insn) == CODE_LABEL)
4335 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4337 /* Don't assume a reload reg is still good after a call insn
4338 if it is a call-used reg. */
4339 else if (GET_CODE (insn) == CALL_INSN)
4340 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4342 /* In case registers overlap, allow certain insns to invalidate
4343 particular hard registers. */
4345 #ifdef INSN_CLOBBERS_REGNO_P
4346 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4347 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4348 && INSN_CLOBBERS_REGNO_P (insn, i))
4349 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4358 /* Discard all record of any value reloaded from X,
4359 or reloaded in X from someplace else;
4360 unless X is an output reload reg of the current insn.
4362 X may be a hard reg (the reload reg)
4363 or it may be a pseudo reg that was reloaded from. */
4366 forget_old_reloads_1 (x, ignored)
4368 rtx ignored ATTRIBUTE_UNUSED;
4374 /* note_stores does give us subregs of hard regs. */
4375 while (GET_CODE (x) == SUBREG)
4377 offset += SUBREG_WORD (x);
4381 if (GET_CODE (x) != REG)
4384 regno = REGNO (x) + offset;
4386 if (regno >= FIRST_PSEUDO_REGISTER)
4391 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4392 /* Storing into a spilled-reg invalidates its contents.
4393 This can happen if a block-local pseudo is allocated to that reg
4394 and it wasn't spilled because this block's total need is 0.
4395 Then some insn might have an optional reload and use this reg. */
4396 for (i = 0; i < nr; i++)
4397 /* But don't do this if the reg actually serves as an output
4398 reload reg in the current instruction. */
4400 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4401 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4404 /* Since value of X has changed,
4405 forget any value previously copied from it. */
4408 /* But don't forget a copy if this is the output reload
4409 that establishes the copy's validity. */
4410 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4411 reg_last_reload_reg[regno + nr] = 0;
4414 /* For each reload, the mode of the reload register. */
4415 static enum machine_mode reload_mode[MAX_RELOADS];
4417 /* For each reload, the largest number of registers it will require. */
4418 static int reload_nregs[MAX_RELOADS];
4420 /* Comparison function for qsort to decide which of two reloads
4421 should be handled first. *P1 and *P2 are the reload numbers. */
4424 reload_reg_class_lower (r1p, r2p)
4425 const GENERIC_PTR r1p;
4426 const GENERIC_PTR r2p;
4428 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4431 /* Consider required reloads before optional ones. */
4432 t = reload_optional[r1] - reload_optional[r2];
4436 /* Count all solitary classes before non-solitary ones. */
4437 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4438 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4442 /* Aside from solitaires, consider all multi-reg groups first. */
4443 t = reload_nregs[r2] - reload_nregs[r1];
4447 /* Consider reloads in order of increasing reg-class number. */
4448 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4452 /* If reloads are equally urgent, sort by reload number,
4453 so that the results of qsort leave nothing to chance. */
4457 /* The following HARD_REG_SETs indicate when each hard register is
4458 used for a reload of various parts of the current insn. */
4460 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4461 static HARD_REG_SET reload_reg_used;
4462 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4463 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4464 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4465 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4466 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4467 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4468 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4469 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4470 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4471 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4472 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4473 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4474 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4475 static HARD_REG_SET reload_reg_used_in_op_addr;
4476 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4477 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4478 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4479 static HARD_REG_SET reload_reg_used_in_insn;
4480 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4481 static HARD_REG_SET reload_reg_used_in_other_addr;
4483 /* If reg is in use as a reload reg for any sort of reload. */
4484 static HARD_REG_SET reload_reg_used_at_all;
4486 /* If reg is use as an inherited reload. We just mark the first register
4488 static HARD_REG_SET reload_reg_used_for_inherit;
4490 /* Records which hard regs are allocated to a pseudo during any point of the
4492 static HARD_REG_SET reg_used_by_pseudo;
4494 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4495 TYPE. MODE is used to indicate how many consecutive regs are
4499 mark_reload_reg_in_use (regno, opnum, type, mode)
4502 enum reload_type type;
4503 enum machine_mode mode;
4505 int nregs = HARD_REGNO_NREGS (regno, mode);
4508 for (i = regno; i < nregs + regno; i++)
4513 SET_HARD_REG_BIT (reload_reg_used, i);
4516 case RELOAD_FOR_INPUT_ADDRESS:
4517 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4520 case RELOAD_FOR_INPADDR_ADDRESS:
4521 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4524 case RELOAD_FOR_OUTPUT_ADDRESS:
4525 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4528 case RELOAD_FOR_OUTADDR_ADDRESS:
4529 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4532 case RELOAD_FOR_OPERAND_ADDRESS:
4533 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4536 case RELOAD_FOR_OPADDR_ADDR:
4537 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4540 case RELOAD_FOR_OTHER_ADDRESS:
4541 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4544 case RELOAD_FOR_INPUT:
4545 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4548 case RELOAD_FOR_OUTPUT:
4549 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4552 case RELOAD_FOR_INSN:
4553 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4557 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4561 /* Similarly, but show REGNO is no longer in use for a reload. */
4564 clear_reload_reg_in_use (regno, opnum, type, mode)
4567 enum reload_type type;
4568 enum machine_mode mode;
4570 int nregs = HARD_REGNO_NREGS (regno, mode);
4571 int start_regno, end_regno;
4573 /* A complication is that for some reload types, inheritance might
4574 allow multiple reloads of the same types to share a reload register.
4575 We set check_opnum if we have to check only reloads with the same
4576 operand number, and check_any if we have to check all reloads. */
4577 int check_opnum = 0;
4579 HARD_REG_SET *used_in_set;
4584 used_in_set = &reload_reg_used;
4587 case RELOAD_FOR_INPUT_ADDRESS:
4588 used_in_set = &reload_reg_used_in_input_addr[opnum];
4591 case RELOAD_FOR_INPADDR_ADDRESS:
4593 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4596 case RELOAD_FOR_OUTPUT_ADDRESS:
4597 used_in_set = &reload_reg_used_in_output_addr[opnum];
4600 case RELOAD_FOR_OUTADDR_ADDRESS:
4602 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4605 case RELOAD_FOR_OPERAND_ADDRESS:
4606 used_in_set = &reload_reg_used_in_op_addr;
4609 case RELOAD_FOR_OPADDR_ADDR:
4611 used_in_set = &reload_reg_used_in_op_addr_reload;
4614 case RELOAD_FOR_OTHER_ADDRESS:
4615 used_in_set = &reload_reg_used_in_other_addr;
4619 case RELOAD_FOR_INPUT:
4620 used_in_set = &reload_reg_used_in_input[opnum];
4623 case RELOAD_FOR_OUTPUT:
4624 used_in_set = &reload_reg_used_in_output[opnum];
4627 case RELOAD_FOR_INSN:
4628 used_in_set = &reload_reg_used_in_insn;
4633 /* We resolve conflicts with remaining reloads of the same type by
4634 excluding the intervals of of reload registers by them from the
4635 interval of freed reload registers. Since we only keep track of
4636 one set of interval bounds, we might have to exclude somewhat
4637 more then what would be necessary if we used a HARD_REG_SET here.
4638 But this should only happen very infrequently, so there should
4639 be no reason to worry about it. */
4641 start_regno = regno;
4642 end_regno = regno + nregs;
4643 if (check_opnum || check_any)
4645 for (i = n_reloads - 1; i >= 0; i--)
4647 if (reload_when_needed[i] == type
4648 && (check_any || reload_opnum[i] == opnum)
4649 && reload_reg_rtx[i])
4651 int conflict_start = true_regnum (reload_reg_rtx[i]);
4654 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4656 /* If there is an overlap with the first to-be-freed register,
4657 adjust the interval start. */
4658 if (conflict_start <= start_regno && conflict_end > start_regno)
4659 start_regno = conflict_end;
4660 /* Otherwise, if there is a conflict with one of the other
4661 to-be-freed registers, adjust the interval end. */
4662 if (conflict_start > start_regno && conflict_start < end_regno)
4663 end_regno = conflict_start;
4667 for (i = start_regno; i < end_regno; i++)
4668 CLEAR_HARD_REG_BIT (*used_in_set, i);
4671 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4672 specified by OPNUM and TYPE. */
4675 reload_reg_free_p (regno, opnum, type)
4678 enum reload_type type;
4682 /* In use for a RELOAD_OTHER means it's not available for anything. */
4683 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4689 /* In use for anything means we can't use it for RELOAD_OTHER. */
4690 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4691 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4692 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4695 for (i = 0; i < reload_n_operands; i++)
4696 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4697 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4698 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4699 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4700 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4701 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4706 case RELOAD_FOR_INPUT:
4707 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4708 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4711 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4714 /* If it is used for some other input, can't use it. */
4715 for (i = 0; i < reload_n_operands; i++)
4716 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4719 /* If it is used in a later operand's address, can't use it. */
4720 for (i = opnum + 1; i < reload_n_operands; i++)
4721 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4722 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4727 case RELOAD_FOR_INPUT_ADDRESS:
4728 /* Can't use a register if it is used for an input address for this
4729 operand or used as an input in an earlier one. */
4730 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4731 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4734 for (i = 0; i < opnum; i++)
4735 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4740 case RELOAD_FOR_INPADDR_ADDRESS:
4741 /* Can't use a register if it is used for an input address
4742 for this operand or used as an input in an earlier
4744 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4747 for (i = 0; i < opnum; i++)
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4753 case RELOAD_FOR_OUTPUT_ADDRESS:
4754 /* Can't use a register if it is used for an output address for this
4755 operand or used as an output in this or a later operand. */
4756 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4759 for (i = opnum; i < reload_n_operands; i++)
4760 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4765 case RELOAD_FOR_OUTADDR_ADDRESS:
4766 /* Can't use a register if it is used for an output address
4767 for this operand or used as an output in this or a
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4772 for (i = opnum; i < reload_n_operands; i++)
4773 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4778 case RELOAD_FOR_OPERAND_ADDRESS:
4779 for (i = 0; i < reload_n_operands; i++)
4780 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4783 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4784 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4786 case RELOAD_FOR_OPADDR_ADDR:
4787 for (i = 0; i < reload_n_operands; i++)
4788 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4791 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4793 case RELOAD_FOR_OUTPUT:
4794 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4795 outputs, or an operand address for this or an earlier output. */
4796 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4799 for (i = 0; i < reload_n_operands; i++)
4800 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4803 for (i = 0; i <= opnum; i++)
4804 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4805 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4810 case RELOAD_FOR_INSN:
4811 for (i = 0; i < reload_n_operands; i++)
4812 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4813 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4816 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4817 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4819 case RELOAD_FOR_OTHER_ADDRESS:
4820 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4825 /* Return 1 if the value in reload reg REGNO, as used by a reload
4826 needed for the part of the insn specified by OPNUM and TYPE,
4827 is still available in REGNO at the end of the insn.
4829 We can assume that the reload reg was already tested for availability
4830 at the time it is needed, and we should not check this again,
4831 in case the reg has already been marked in use. */
4834 reload_reg_reaches_end_p (regno, opnum, type)
4837 enum reload_type type;
4844 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4845 its value must reach the end. */
4848 /* If this use is for part of the insn,
4849 its value reaches if no subsequent part uses the same register.
4850 Just like the above function, don't try to do this with lots
4853 case RELOAD_FOR_OTHER_ADDRESS:
4854 /* Here we check for everything else, since these don't conflict
4855 with anything else and everything comes later. */
4857 for (i = 0; i < reload_n_operands; i++)
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4859 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4860 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4861 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4862 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4863 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4866 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4867 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4868 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4870 case RELOAD_FOR_INPUT_ADDRESS:
4871 case RELOAD_FOR_INPADDR_ADDRESS:
4872 /* Similar, except that we check only for this and subsequent inputs
4873 and the address of only subsequent inputs and we do not need
4874 to check for RELOAD_OTHER objects since they are known not to
4877 for (i = opnum; i < reload_n_operands; i++)
4878 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4881 for (i = opnum + 1; i < reload_n_operands; i++)
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4883 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4886 for (i = 0; i < reload_n_operands; i++)
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4888 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4892 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4895 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4896 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4898 case RELOAD_FOR_INPUT:
4899 /* Similar to input address, except we start at the next operand for
4900 both input and input address and we do not check for
4901 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4904 for (i = opnum + 1; i < reload_n_operands; i++)
4905 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4906 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4907 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4910 /* ... fall through ... */
4912 case RELOAD_FOR_OPERAND_ADDRESS:
4913 /* Check outputs and their addresses. */
4915 for (i = 0; i < reload_n_operands; i++)
4916 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4917 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4918 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4923 case RELOAD_FOR_OPADDR_ADDR:
4924 for (i = 0; i < reload_n_operands; i++)
4925 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4926 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4927 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4930 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4931 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4933 case RELOAD_FOR_INSN:
4934 /* These conflict with other outputs with RELOAD_OTHER. So
4935 we need only check for output addresses. */
4939 /* ... fall through ... */
4941 case RELOAD_FOR_OUTPUT:
4942 case RELOAD_FOR_OUTPUT_ADDRESS:
4943 case RELOAD_FOR_OUTADDR_ADDRESS:
4944 /* We already know these can't conflict with a later output. So the
4945 only thing to check are later output addresses. */
4946 for (i = opnum + 1; i < reload_n_operands; i++)
4947 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4948 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4957 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4960 This function uses the same algorithm as reload_reg_free_p above. */
4963 reloads_conflict (r1, r2)
4966 enum reload_type r1_type = reload_when_needed[r1];
4967 enum reload_type r2_type = reload_when_needed[r2];
4968 int r1_opnum = reload_opnum[r1];
4969 int r2_opnum = reload_opnum[r2];
4971 /* RELOAD_OTHER conflicts with everything. */
4972 if (r2_type == RELOAD_OTHER)
4975 /* Otherwise, check conflicts differently for each type. */
4979 case RELOAD_FOR_INPUT:
4980 return (r2_type == RELOAD_FOR_INSN
4981 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4982 || r2_type == RELOAD_FOR_OPADDR_ADDR
4983 || r2_type == RELOAD_FOR_INPUT
4984 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4985 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4986 && r2_opnum > r1_opnum));
4988 case RELOAD_FOR_INPUT_ADDRESS:
4989 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4990 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4992 case RELOAD_FOR_INPADDR_ADDRESS:
4993 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4994 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4996 case RELOAD_FOR_OUTPUT_ADDRESS:
4997 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4998 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5000 case RELOAD_FOR_OUTADDR_ADDRESS:
5001 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5002 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5004 case RELOAD_FOR_OPERAND_ADDRESS:
5005 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5006 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5008 case RELOAD_FOR_OPADDR_ADDR:
5009 return (r2_type == RELOAD_FOR_INPUT
5010 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5012 case RELOAD_FOR_OUTPUT:
5013 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5014 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5015 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5016 && r2_opnum >= r1_opnum));
5018 case RELOAD_FOR_INSN:
5019 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5020 || r2_type == RELOAD_FOR_INSN
5021 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5023 case RELOAD_FOR_OTHER_ADDRESS:
5024 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5034 /* Vector of reload-numbers showing the order in which the reloads should
5036 short reload_order[MAX_RELOADS];
5038 /* Indexed by reload number, 1 if incoming value
5039 inherited from previous insns. */
5040 char reload_inherited[MAX_RELOADS];
5042 /* For an inherited reload, this is the insn the reload was inherited from,
5043 if we know it. Otherwise, this is 0. */
5044 rtx reload_inheritance_insn[MAX_RELOADS];
5046 /* If non-zero, this is a place to get the value of the reload,
5047 rather than using reload_in. */
5048 rtx reload_override_in[MAX_RELOADS];
5050 /* For each reload, the hard register number of the register used,
5051 or -1 if we did not need a register for this reload. */
5052 int reload_spill_index[MAX_RELOADS];
5054 /* Return 1 if the value in reload reg REGNO, as used by a reload
5055 needed for the part of the insn specified by OPNUM and TYPE,
5056 may be used to load VALUE into it.
5058 Other read-only reloads with the same value do not conflict
5059 unless OUT is non-zero and these other reloads have to live while
5060 output reloads live.
5061 If OUT is CONST0_RTX, this is a special case: it means that the
5062 test should not be for using register REGNO as reload register, but
5063 for copying from register REGNO into the reload register.
5065 RELOADNUM is the number of the reload we want to load this value for;
5066 a reload does not conflict with itself.
5068 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5069 reloads that load an address for the very reload we are considering.
5071 The caller has to make sure that there is no conflict with the return
5074 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5075 ignore_address_reloads)
5078 enum reload_type type;
5081 int ignore_address_reloads;
5087 if (out == const0_rtx)
5093 /* We use some pseudo 'time' value to check if the lifetimes of the
5094 new register use would overlap with the one of a previous reload
5095 that is not read-only or uses a different value.
5096 The 'time' used doesn't have to be linear in any shape or form, just
5098 Some reload types use different 'buckets' for each operand.
5099 So there are MAX_RECOG_OPERANDS different time values for each
5101 We compute TIME1 as the time when the register for the prospective
5102 new reload ceases to be live, and TIME2 for each existing
5103 reload as the time when that the reload register of that reload
5105 Where there is little to be gained by exact lifetime calculations,
5106 we just make conservative assumptions, i.e. a longer lifetime;
5107 this is done in the 'default:' cases. */
5110 case RELOAD_FOR_OTHER_ADDRESS:
5114 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5116 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5117 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5118 respectively, to the time values for these, we get distinct time
5119 values. To get distinct time values for each operand, we have to
5120 multiply opnum by at least three. We round that up to four because
5121 multiply by four is often cheaper. */
5122 case RELOAD_FOR_INPADDR_ADDRESS:
5123 time1 = opnum * 4 + 2;
5125 case RELOAD_FOR_INPUT_ADDRESS:
5126 time1 = opnum * 4 + 3;
5128 case RELOAD_FOR_INPUT:
5129 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5130 executes (inclusive). */
5131 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5133 case RELOAD_FOR_OPADDR_ADDR:
5135 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5136 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5138 case RELOAD_FOR_OPERAND_ADDRESS:
5139 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5141 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5143 case RELOAD_FOR_OUTADDR_ADDRESS:
5144 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5146 case RELOAD_FOR_OUTPUT_ADDRESS:
5147 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5150 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5153 for (i = 0; i < n_reloads; i++)
5155 rtx reg = reload_reg_rtx[i];
5156 if (reg && GET_CODE (reg) == REG
5157 && ((unsigned) regno - true_regnum (reg)
5158 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5161 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5162 || reload_out[i] || out)
5165 switch (reload_when_needed[i])
5167 case RELOAD_FOR_OTHER_ADDRESS:
5170 case RELOAD_FOR_INPADDR_ADDRESS:
5171 /* find_reloads makes sure that a
5172 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5173 by at most one - the first -
5174 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5175 address reload is inherited, the address address reload
5176 goes away, so we can ignore this conflict. */
5177 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5178 && ignore_address_reloads
5179 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5180 Then the address address is still needed to store
5181 back the new address. */
5182 && ! reload_out[reloadnum])
5184 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5185 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5187 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5188 && ignore_address_reloads
5189 /* Unless we are reloading an auto_inc expression. */
5190 && ! reload_out[reloadnum])
5192 time2 = reload_opnum[i] * 4 + 2;
5194 case RELOAD_FOR_INPUT_ADDRESS:
5195 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5196 && ignore_address_reloads
5197 && ! reload_out[reloadnum])
5199 time2 = reload_opnum[i] * 4 + 3;
5201 case RELOAD_FOR_INPUT:
5202 time2 = reload_opnum[i] * 4 + 4;
5204 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5205 == MAX_RECOG_OPERAND * 4 */
5206 case RELOAD_FOR_OPADDR_ADDR:
5207 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5208 && ignore_address_reloads
5209 && ! reload_out[reloadnum])
5211 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5213 case RELOAD_FOR_OPERAND_ADDRESS:
5214 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5216 case RELOAD_FOR_INSN:
5217 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5219 case RELOAD_FOR_OUTPUT:
5220 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5221 instruction is executed. */
5222 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5224 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5225 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5227 case RELOAD_FOR_OUTADDR_ADDRESS:
5228 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5229 && ignore_address_reloads
5230 && ! reload_out[reloadnum])
5232 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
5234 case RELOAD_FOR_OUTPUT_ADDRESS:
5235 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
5238 /* If there is no conflict in the input part, handle this
5239 like an output reload. */
5240 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5242 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5246 /* RELOAD_OTHER might be live beyond instruction execution,
5247 but this is not obvious when we set time2 = 1. So check
5248 here if there might be a problem with the new reload
5249 clobbering the register used by the RELOAD_OTHER. */
5257 && (! reload_in[i] || reload_out[i]
5258 || ! rtx_equal_p (reload_in[i], value)))
5259 || (out && reload_out_reg[reloadnum]
5260 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5268 /* Find a spill register to use as a reload register for reload R.
5269 LAST_RELOAD is non-zero if this is the last reload for the insn being
5272 Set reload_reg_rtx[R] to the register allocated.
5274 If NOERROR is nonzero, we return 1 if successful,
5275 or 0 if we couldn't find a spill reg and we didn't change anything. */
5278 allocate_reload_reg (chain, r, last_reload, noerror)
5279 struct insn_chain *chain;
5284 rtx insn = chain->insn;
5285 int i, pass, count, regno;
5288 /* If we put this reload ahead, thinking it is a group,
5289 then insist on finding a group. Otherwise we can grab a
5290 reg that some other reload needs.
5291 (That can happen when we have a 68000 DATA_OR_FP_REG
5292 which is a group of data regs or one fp reg.)
5293 We need not be so restrictive if there are no more reloads
5296 ??? Really it would be nicer to have smarter handling
5297 for that kind of reg class, where a problem like this is normal.
5298 Perhaps those classes should be avoided for reloading
5299 by use of more alternatives. */
5301 int force_group = reload_nregs[r] > 1 && ! last_reload;
5303 /* If we want a single register and haven't yet found one,
5304 take any reg in the right class and not in use.
5305 If we want a consecutive group, here is where we look for it.
5307 We use two passes so we can first look for reload regs to
5308 reuse, which are already in use for other reloads in this insn,
5309 and only then use additional registers.
5310 I think that maximizing reuse is needed to make sure we don't
5311 run out of reload regs. Suppose we have three reloads, and
5312 reloads A and B can share regs. These need two regs.
5313 Suppose A and B are given different regs.
5314 That leaves none for C. */
5315 for (pass = 0; pass < 2; pass++)
5317 /* I is the index in spill_regs.
5318 We advance it round-robin between insns to use all spill regs
5319 equally, so that inherited reloads have a chance
5320 of leapfrogging each other. Don't do this, however, when we have
5321 group needs and failure would be fatal; if we only have a relatively
5322 small number of spill registers, and more than one of them has
5323 group needs, then by starting in the middle, we may end up
5324 allocating the first one in such a way that we are not left with
5325 sufficient groups to handle the rest. */
5327 if (noerror || ! force_group)
5332 for (count = 0; count < n_spills; count++)
5334 int class = (int) reload_reg_class[r];
5340 regnum = spill_regs[i];
5342 if ((reload_reg_free_p (regnum, reload_opnum[r],
5343 reload_when_needed[r])
5345 /* We check reload_reg_used to make sure we
5346 don't clobber the return register. */
5347 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5348 && reload_reg_free_for_value_p (regnum,
5350 reload_when_needed[r],
5352 reload_out[r], r, 1)))
5353 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5354 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5355 /* Look first for regs to share, then for unshared. But
5356 don't share regs used for inherited reloads; they are
5357 the ones we want to preserve. */
5359 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5361 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5364 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5365 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5366 (on 68000) got us two FP regs. If NR is 1,
5367 we would reject both of them. */
5369 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5370 /* If we need only one reg, we have already won. */
5373 /* But reject a single reg if we demand a group. */
5378 /* Otherwise check that as many consecutive regs as we need
5380 Also, don't use for a group registers that are
5381 needed for nongroups. */
5382 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5385 regno = regnum + nr - 1;
5386 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5387 && spill_reg_order[regno] >= 0
5388 && reload_reg_free_p (regno, reload_opnum[r],
5389 reload_when_needed[r])
5390 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5400 /* If we found something on pass 1, omit pass 2. */
5401 if (count < n_spills)
5405 /* We should have found a spill register by now. */
5406 if (count == n_spills)
5413 /* I is the index in SPILL_REG_RTX of the reload register we are to
5414 allocate. Get an rtx for it and find its register number. */
5416 new = spill_reg_rtx[i];
5418 if (new == 0 || GET_MODE (new) != reload_mode[r])
5419 spill_reg_rtx[i] = new
5420 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5422 regno = true_regnum (new);
5424 /* Detect when the reload reg can't hold the reload mode.
5425 This used to be one `if', but Sequent compiler can't handle that. */
5426 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5428 enum machine_mode test_mode = VOIDmode;
5430 test_mode = GET_MODE (reload_in[r]);
5431 /* If reload_in[r] has VOIDmode, it means we will load it
5432 in whatever mode the reload reg has: to wit, reload_mode[r].
5433 We have already tested that for validity. */
5434 /* Aside from that, we need to test that the expressions
5435 to reload from or into have modes which are valid for this
5436 reload register. Otherwise the reload insns would be invalid. */
5437 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5438 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5439 if (! (reload_out[r] != 0
5440 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5442 /* The reg is OK. */
5445 /* Mark as in use for this insn the reload regs we use
5447 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5448 reload_when_needed[r], reload_mode[r]);
5450 reload_reg_rtx[r] = new;
5451 reload_spill_index[r] = spill_regs[i];
5456 /* The reg is not OK. */
5461 if (asm_noperands (PATTERN (insn)) < 0)
5462 /* It's the compiler's fault. */
5463 fatal_insn ("Could not find a spill register", insn);
5465 /* It's the user's fault; the operand's mode and constraint
5466 don't match. Disable this reload so we don't crash in final. */
5467 error_for_asm (insn,
5468 "`asm' operand constraint incompatible with operand size");
5471 reload_reg_rtx[r] = 0;
5472 reload_optional[r] = 1;
5473 reload_secondary_p[r] = 1;
5478 /* Assign hard reg targets for the pseudo-registers we must reload
5479 into hard regs for this insn.
5480 Also output the instructions to copy them in and out of the hard regs.
5482 For machines with register classes, we are responsible for
5483 finding a reload reg in the proper class. */
5486 choose_reload_regs (chain)
5487 struct insn_chain *chain;
5489 rtx insn = chain->insn;
5491 int max_group_size = 1;
5492 enum reg_class group_class = NO_REGS;
5496 rtx save_reload_reg_rtx[MAX_RELOADS];
5497 char save_reload_inherited[MAX_RELOADS];
5498 rtx save_reload_inheritance_insn[MAX_RELOADS];
5499 rtx save_reload_override_in[MAX_RELOADS];
5500 int save_reload_spill_index[MAX_RELOADS];
5501 HARD_REG_SET save_reload_reg_used;
5502 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5503 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5504 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5505 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5506 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5507 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5508 HARD_REG_SET save_reload_reg_used_in_op_addr;
5509 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5510 HARD_REG_SET save_reload_reg_used_in_insn;
5511 HARD_REG_SET save_reload_reg_used_in_other_addr;
5512 HARD_REG_SET save_reload_reg_used_at_all;
5514 bzero (reload_inherited, MAX_RELOADS);
5515 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5516 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5518 CLEAR_HARD_REG_SET (reload_reg_used);
5519 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5520 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5521 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5522 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5523 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5525 CLEAR_HARD_REG_SET (reg_used_by_pseudo);
5526 compute_use_by_pseudos (®_used_by_pseudo, chain->live_before);
5527 compute_use_by_pseudos (®_used_by_pseudo, chain->live_after);
5529 for (i = 0; i < reload_n_operands; i++)
5531 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5532 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5533 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5534 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5535 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5536 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5539 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5541 #if 0 /* Not needed, now that we can always retry without inheritance. */
5542 /* See if we have more mandatory reloads than spill regs.
5543 If so, then we cannot risk optimizations that could prevent
5544 reloads from sharing one spill register.
5546 Since we will try finding a better register than reload_reg_rtx
5547 unless it is equal to reload_in or reload_out, count such reloads. */
5551 for (j = 0; j < n_reloads; j++)
5552 if (! reload_optional[j]
5553 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5554 && (reload_reg_rtx[j] == 0
5555 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5556 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5563 /* In order to be certain of getting the registers we need,
5564 we must sort the reloads into order of increasing register class.
5565 Then our grabbing of reload registers will parallel the process
5566 that provided the reload registers.
5568 Also note whether any of the reloads wants a consecutive group of regs.
5569 If so, record the maximum size of the group desired and what
5570 register class contains all the groups needed by this insn. */
5572 for (j = 0; j < n_reloads; j++)
5574 reload_order[j] = j;
5575 reload_spill_index[j] = -1;
5578 = (reload_inmode[j] == VOIDmode
5579 || (GET_MODE_SIZE (reload_outmode[j])
5580 > GET_MODE_SIZE (reload_inmode[j])))
5581 ? reload_outmode[j] : reload_inmode[j];
5583 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5585 if (reload_nregs[j] > 1)
5587 max_group_size = MAX (reload_nregs[j], max_group_size);
5588 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5591 /* If we have already decided to use a certain register,
5592 don't use it in another way. */
5593 if (reload_reg_rtx[j])
5594 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5595 reload_when_needed[j], reload_mode[j]);
5599 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5601 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5602 sizeof reload_reg_rtx);
5603 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5604 bcopy ((char *) reload_inheritance_insn,
5605 (char *) save_reload_inheritance_insn,
5606 sizeof reload_inheritance_insn);
5607 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5608 sizeof reload_override_in);
5609 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5610 sizeof reload_spill_index);
5611 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5612 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5613 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5614 reload_reg_used_in_op_addr);
5616 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5617 reload_reg_used_in_op_addr_reload);
5619 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5620 reload_reg_used_in_insn);
5621 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5622 reload_reg_used_in_other_addr);
5624 for (i = 0; i < reload_n_operands; i++)
5626 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5627 reload_reg_used_in_output[i]);
5628 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5629 reload_reg_used_in_input[i]);
5630 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5631 reload_reg_used_in_input_addr[i]);
5632 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5633 reload_reg_used_in_inpaddr_addr[i]);
5634 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5635 reload_reg_used_in_output_addr[i]);
5636 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5637 reload_reg_used_in_outaddr_addr[i]);
5640 /* If -O, try first with inheritance, then turning it off.
5641 If not -O, don't do inheritance.
5642 Using inheritance when not optimizing leads to paradoxes
5643 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5644 because one side of the comparison might be inherited. */
5646 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5648 /* Process the reloads in order of preference just found.
5649 Beyond this point, subregs can be found in reload_reg_rtx.
5651 This used to look for an existing reloaded home for all
5652 of the reloads, and only then perform any new reloads.
5653 But that could lose if the reloads were done out of reg-class order
5654 because a later reload with a looser constraint might have an old
5655 home in a register needed by an earlier reload with a tighter constraint.
5657 To solve this, we make two passes over the reloads, in the order
5658 described above. In the first pass we try to inherit a reload
5659 from a previous insn. If there is a later reload that needs a
5660 class that is a proper subset of the class being processed, we must
5661 also allocate a spill register during the first pass.
5663 Then make a second pass over the reloads to allocate any reloads
5664 that haven't been given registers yet. */
5666 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5668 for (j = 0; j < n_reloads; j++)
5670 register int r = reload_order[j];
5672 /* Ignore reloads that got marked inoperative. */
5673 if (reload_out[r] == 0 && reload_in[r] == 0
5674 && ! reload_secondary_p[r])
5677 /* If find_reloads chose to use reload_in or reload_out as a reload
5678 register, we don't need to chose one. Otherwise, try even if it
5679 found one since we might save an insn if we find the value lying
5681 Try also when reload_in is a pseudo without a hard reg. */
5682 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5683 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5684 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5685 && GET_CODE (reload_in[r]) != MEM
5686 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5689 #if 0 /* No longer needed for correct operation.
5690 It might give better code, or might not; worth an experiment? */
5691 /* If this is an optional reload, we can't inherit from earlier insns
5692 until we are sure that any non-optional reloads have been allocated.
5693 The following code takes advantage of the fact that optional reloads
5694 are at the end of reload_order. */
5695 if (reload_optional[r] != 0)
5696 for (i = 0; i < j; i++)
5697 if ((reload_out[reload_order[i]] != 0
5698 || reload_in[reload_order[i]] != 0
5699 || reload_secondary_p[reload_order[i]])
5700 && ! reload_optional[reload_order[i]]
5701 && reload_reg_rtx[reload_order[i]] == 0)
5702 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5705 /* First see if this pseudo is already available as reloaded
5706 for a previous insn. We cannot try to inherit for reloads
5707 that are smaller than the maximum number of registers needed
5708 for groups unless the register we would allocate cannot be used
5711 We could check here to see if this is a secondary reload for
5712 an object that is already in a register of the desired class.
5713 This would avoid the need for the secondary reload register.
5714 But this is complex because we can't easily determine what
5715 objects might want to be loaded via this reload. So let a
5716 register be allocated here. In `emit_reload_insns' we suppress
5717 one of the loads in the case described above. */
5722 register int regno = -1;
5723 enum machine_mode mode;
5725 if (reload_in[r] == 0)
5727 else if (GET_CODE (reload_in[r]) == REG)
5729 regno = REGNO (reload_in[r]);
5730 mode = GET_MODE (reload_in[r]);
5732 else if (GET_CODE (reload_in_reg[r]) == REG)
5734 regno = REGNO (reload_in_reg[r]);
5735 mode = GET_MODE (reload_in_reg[r]);
5737 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5738 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5740 word = SUBREG_WORD (reload_in_reg[r]);
5741 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5742 if (regno < FIRST_PSEUDO_REGISTER)
5744 mode = GET_MODE (reload_in_reg[r]);
5747 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5748 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5749 || GET_CODE (reload_in_reg[r]) == POST_INC
5750 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5751 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5753 regno = REGNO (XEXP (reload_in_reg[r], 0));
5754 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5755 reload_out[r] = reload_in[r];
5759 /* This won't work, since REGNO can be a pseudo reg number.
5760 Also, it takes much more hair to keep track of all the things
5761 that can invalidate an inherited reload of part of a pseudoreg. */
5762 else if (GET_CODE (reload_in[r]) == SUBREG
5763 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5764 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5767 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5769 enum reg_class class = reload_reg_class[r], last_class;
5770 rtx last_reg = reg_last_reload_reg[regno];
5772 i = REGNO (last_reg) + word;
5773 last_class = REGNO_REG_CLASS (i);
5774 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5775 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5776 && reg_reloaded_contents[i] == regno
5777 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5778 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5779 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5780 /* Even if we can't use this register as a reload
5781 register, we might use it for reload_override_in,
5782 if copying it to the desired class is cheap
5784 || ((REGISTER_MOVE_COST (last_class, class)
5785 < MEMORY_MOVE_COST (mode, class, 1))
5786 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5787 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5791 #ifdef SECONDARY_MEMORY_NEEDED
5792 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5797 && (reload_nregs[r] == max_group_size
5798 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5800 && reload_reg_free_for_value_p (i, reload_opnum[r],
5801 reload_when_needed[r],
5805 /* If a group is needed, verify that all the subsequent
5806 registers still have their values intact. */
5808 = HARD_REGNO_NREGS (i, reload_mode[r]);
5811 for (k = 1; k < nr; k++)
5812 if (reg_reloaded_contents[i + k] != regno
5813 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5820 last_reg = (GET_MODE (last_reg) == mode
5821 ? last_reg : gen_rtx_REG (mode, i));
5823 /* We found a register that contains the
5824 value we need. If this register is the
5825 same as an `earlyclobber' operand of the
5826 current insn, just mark it as a place to
5827 reload from since we can't use it as the
5828 reload register itself. */
5830 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5831 if (reg_overlap_mentioned_for_reload_p
5832 (reg_last_reload_reg[regno],
5833 reload_earlyclobbers[i1]))
5836 if (i1 != n_earlyclobbers
5837 || ! (reload_reg_free_for_value_p
5838 (i, reload_opnum[r], reload_when_needed[r],
5839 reload_in[r], reload_out[r], r, 1))
5840 /* Don't use it if we'd clobber a pseudo reg. */
5841 || (TEST_HARD_REG_BIT (reg_used_by_pseudo, i)
5843 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5844 /* Don't really use the inherited spill reg
5845 if we need it wider than we've got it. */
5846 || (GET_MODE_SIZE (reload_mode[r])
5847 > GET_MODE_SIZE (mode))
5848 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5851 /* If find_reloads chose reload_out as reload
5852 register, stay with it - that leaves the
5853 inherited register for subsequent reloads. */
5854 || (reload_out[r] && reload_reg_rtx[r]
5855 && rtx_equal_p (reload_out[r],
5856 reload_reg_rtx[r])))
5858 reload_override_in[r] = last_reg;
5859 reload_inheritance_insn[r]
5860 = reg_reloaded_insn[i];
5865 /* We can use this as a reload reg. */
5866 /* Mark the register as in use for this part of
5868 mark_reload_reg_in_use (i,
5870 reload_when_needed[r],
5872 reload_reg_rtx[r] = last_reg;
5873 reload_inherited[r] = 1;
5874 reload_inheritance_insn[r]
5875 = reg_reloaded_insn[i];
5876 reload_spill_index[r] = i;
5877 for (k = 0; k < nr; k++)
5878 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5886 /* Here's another way to see if the value is already lying around. */
5888 && reload_in[r] != 0
5889 && ! reload_inherited[r]
5890 && reload_out[r] == 0
5891 && (CONSTANT_P (reload_in[r])
5892 || GET_CODE (reload_in[r]) == PLUS
5893 || GET_CODE (reload_in[r]) == REG
5894 || GET_CODE (reload_in[r]) == MEM)
5895 && (reload_nregs[r] == max_group_size
5896 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5899 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5900 -1, NULL_PTR, 0, reload_mode[r]);
5905 if (GET_CODE (equiv) == REG)
5906 regno = REGNO (equiv);
5907 else if (GET_CODE (equiv) == SUBREG)
5909 /* This must be a SUBREG of a hard register.
5910 Make a new REG since this might be used in an
5911 address and not all machines support SUBREGs
5913 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5914 equiv = gen_rtx_REG (reload_mode[r], regno);
5920 /* If we found a spill reg, reject it unless it is free
5921 and of the desired class. */
5923 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5924 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
5925 reload_when_needed[r],
5927 reload_out[r], r, 1))
5928 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5932 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5935 /* We found a register that contains the value we need.
5936 If this register is the same as an `earlyclobber' operand
5937 of the current insn, just mark it as a place to reload from
5938 since we can't use it as the reload register itself. */
5941 for (i = 0; i < n_earlyclobbers; i++)
5942 if (reg_overlap_mentioned_for_reload_p (equiv,
5943 reload_earlyclobbers[i]))
5945 reload_override_in[r] = equiv;
5950 /* If the equiv register we have found is explicitly clobbered
5951 in the current insn, it depends on the reload type if we
5952 can use it, use it for reload_override_in, or not at all.
5953 In particular, we then can't use EQUIV for a
5954 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5956 if (equiv != 0 && regno_clobbered_p (regno, insn))
5958 switch (reload_when_needed[r])
5960 case RELOAD_FOR_OTHER_ADDRESS:
5961 case RELOAD_FOR_INPADDR_ADDRESS:
5962 case RELOAD_FOR_INPUT_ADDRESS:
5963 case RELOAD_FOR_OPADDR_ADDR:
5966 case RELOAD_FOR_INPUT:
5967 case RELOAD_FOR_OPERAND_ADDRESS:
5968 reload_override_in[r] = equiv;
5976 /* If we found an equivalent reg, say no code need be generated
5977 to load it, and use it as our reload reg. */
5978 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5980 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5982 reload_reg_rtx[r] = equiv;
5983 reload_inherited[r] = 1;
5985 /* If reg_reloaded_valid is not set for this register,
5986 there might be a stale spill_reg_store lying around.
5987 We must clear it, since otherwise emit_reload_insns
5988 might delete the store. */
5989 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5990 spill_reg_store[regno] = NULL_RTX;
5991 /* If any of the hard registers in EQUIV are spill
5992 registers, mark them as in use for this insn. */
5993 for (k = 0; k < nr; k++)
5995 i = spill_reg_order[regno + k];
5998 mark_reload_reg_in_use (regno, reload_opnum[r],
5999 reload_when_needed[r],
6001 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6008 /* If we found a register to use already, or if this is an optional
6009 reload, we are done. */
6010 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6013 #if 0 /* No longer needed for correct operation. Might or might not
6014 give better code on the average. Want to experiment? */
6016 /* See if there is a later reload that has a class different from our
6017 class that intersects our class or that requires less register
6018 than our reload. If so, we must allocate a register to this
6019 reload now, since that reload might inherit a previous reload
6020 and take the only available register in our class. Don't do this
6021 for optional reloads since they will force all previous reloads
6022 to be allocated. Also don't do this for reloads that have been
6025 for (i = j + 1; i < n_reloads; i++)
6027 int s = reload_order[i];
6029 if ((reload_in[s] == 0 && reload_out[s] == 0
6030 && ! reload_secondary_p[s])
6031 || reload_optional[s])
6034 if ((reload_reg_class[s] != reload_reg_class[r]
6035 && reg_classes_intersect_p (reload_reg_class[r],
6036 reload_reg_class[s]))
6037 || reload_nregs[s] < reload_nregs[r])
6044 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6048 /* Now allocate reload registers for anything non-optional that
6049 didn't get one yet. */
6050 for (j = 0; j < n_reloads; j++)
6052 register int r = reload_order[j];
6054 /* Ignore reloads that got marked inoperative. */
6055 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6058 /* Skip reloads that already have a register allocated or are
6060 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6063 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6067 /* If that loop got all the way, we have won. */
6071 /* Loop around and try without any inheritance. */
6072 /* First undo everything done by the failed attempt
6073 to allocate with inheritance. */
6074 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6075 sizeof reload_reg_rtx);
6076 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6077 sizeof reload_inherited);
6078 bcopy ((char *) save_reload_inheritance_insn,
6079 (char *) reload_inheritance_insn,
6080 sizeof reload_inheritance_insn);
6081 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6082 sizeof reload_override_in);
6083 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6084 sizeof reload_spill_index);
6085 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6086 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6087 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6088 save_reload_reg_used_in_op_addr);
6089 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6090 save_reload_reg_used_in_op_addr_reload);
6091 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6092 save_reload_reg_used_in_insn);
6093 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6094 save_reload_reg_used_in_other_addr);
6096 for (i = 0; i < reload_n_operands; i++)
6098 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6099 save_reload_reg_used_in_input[i]);
6100 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6101 save_reload_reg_used_in_output[i]);
6102 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6103 save_reload_reg_used_in_input_addr[i]);
6104 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6105 save_reload_reg_used_in_inpaddr_addr[i]);
6106 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6107 save_reload_reg_used_in_output_addr[i]);
6108 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6109 save_reload_reg_used_in_outaddr_addr[i]);
6113 /* If we thought we could inherit a reload, because it seemed that
6114 nothing else wanted the same reload register earlier in the insn,
6115 verify that assumption, now that all reloads have been assigned.
6116 Likewise for reloads where reload_override_in has been set. */
6118 /* If doing expensive optimizations, do one preliminary pass that doesn't
6119 cancel any inheritance, but removes reloads that have been needed only
6120 for reloads that we know can be inherited. */
6121 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6123 for (j = 0; j < n_reloads; j++)
6125 register int r = reload_order[j];
6127 if (reload_inherited[r] && reload_reg_rtx[r])
6128 check_reg = reload_reg_rtx[r];
6129 else if (reload_override_in[r]
6130 && (GET_CODE (reload_override_in[r]) == REG
6131 || GET_CODE (reload_override_in[r]) == SUBREG))
6132 check_reg = reload_override_in[r];
6135 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6137 reload_when_needed[r],
6139 (reload_inherited[r]
6140 ? reload_out[r] : const0_rtx),
6145 reload_inherited[r] = 0;
6146 reload_override_in[r] = 0;
6148 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6149 reload_override_in, then we do not need its related
6150 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6151 likewise for other reload types.
6152 We handle this by removing a reload when its only replacement
6153 is mentioned in reload_in of the reload we are going to inherit.
6154 A special case are auto_inc expressions; even if the input is
6155 inherited, we still need the address for the output. We can
6156 recognize them because they have RELOAD_OUT set but not
6158 If we suceeded removing some reload and we are doing a preliminary
6159 pass just to remove such reloads, make another pass, since the
6160 removal of one reload might allow us to inherit another one. */
6161 else if ((! reload_out[r] || reload_out_reg[r])
6162 && remove_address_replacements (reload_in[r]) && pass)
6167 /* Now that reload_override_in is known valid,
6168 actually override reload_in. */
6169 for (j = 0; j < n_reloads; j++)
6170 if (reload_override_in[j])
6171 reload_in[j] = reload_override_in[j];
6173 /* If this reload won't be done because it has been cancelled or is
6174 optional and not inherited, clear reload_reg_rtx so other
6175 routines (such as subst_reloads) don't get confused. */
6176 for (j = 0; j < n_reloads; j++)
6177 if (reload_reg_rtx[j] != 0
6178 && ((reload_optional[j] && ! reload_inherited[j])
6179 || (reload_in[j] == 0 && reload_out[j] == 0
6180 && ! reload_secondary_p[j])))
6182 int regno = true_regnum (reload_reg_rtx[j]);
6184 if (spill_reg_order[regno] >= 0)
6185 clear_reload_reg_in_use (regno, reload_opnum[j],
6186 reload_when_needed[j], reload_mode[j]);
6187 reload_reg_rtx[j] = 0;
6190 /* Record which pseudos and which spill regs have output reloads. */
6191 for (j = 0; j < n_reloads; j++)
6193 register int r = reload_order[j];
6195 i = reload_spill_index[r];
6197 /* I is nonneg if this reload uses a register.
6198 If reload_reg_rtx[r] is 0, this is an optional reload
6199 that we opted to ignore. */
6200 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6201 && reload_reg_rtx[r] != 0)
6203 register int nregno = REGNO (reload_out_reg[r]);
6206 if (nregno < FIRST_PSEUDO_REGISTER)
6207 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6210 reg_has_output_reload[nregno + nr] = 1;
6214 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6216 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6219 if (reload_when_needed[r] != RELOAD_OTHER
6220 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6221 && reload_when_needed[r] != RELOAD_FOR_INSN)
6227 /* Deallocate the reload register for reload R. This is called from
6228 remove_address_replacements. */
6230 deallocate_reload_reg (r)
6235 if (! reload_reg_rtx[r])
6237 regno = true_regnum (reload_reg_rtx[r]);
6238 reload_reg_rtx[r] = 0;
6239 if (spill_reg_order[regno] >= 0)
6240 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6242 reload_spill_index[r] = -1;
6245 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6246 reloads of the same item for fear that we might not have enough reload
6247 registers. However, normally they will get the same reload register
6248 and hence actually need not be loaded twice.
6250 Here we check for the most common case of this phenomenon: when we have
6251 a number of reloads for the same object, each of which were allocated
6252 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6253 reload, and is not modified in the insn itself. If we find such,
6254 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6255 This will not increase the number of spill registers needed and will
6256 prevent redundant code. */
6259 merge_assigned_reloads (insn)
6264 /* Scan all the reloads looking for ones that only load values and
6265 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6266 assigned and not modified by INSN. */
6268 for (i = 0; i < n_reloads; i++)
6270 int conflicting_input = 0;
6271 int max_input_address_opnum = -1;
6272 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6274 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6275 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6276 || reg_set_p (reload_reg_rtx[i], insn))
6279 /* Look at all other reloads. Ensure that the only use of this
6280 reload_reg_rtx is in a reload that just loads the same value
6281 as we do. Note that any secondary reloads must be of the identical
6282 class since the values, modes, and result registers are the
6283 same, so we need not do anything with any secondary reloads. */
6285 for (j = 0; j < n_reloads; j++)
6287 if (i == j || reload_reg_rtx[j] == 0
6288 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6292 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6293 && reload_opnum[j] > max_input_address_opnum)
6294 max_input_address_opnum = reload_opnum[j];
6296 /* If the reload regs aren't exactly the same (e.g, different modes)
6297 or if the values are different, we can't merge this reload.
6298 But if it is an input reload, we might still merge
6299 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6301 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6302 || reload_out[j] != 0 || reload_in[j] == 0
6303 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6305 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6306 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6307 || reload_opnum[i] > reload_opnum[j])
6308 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6310 conflicting_input = 1;
6311 if (min_conflicting_input_opnum > reload_opnum[j])
6312 min_conflicting_input_opnum = reload_opnum[j];
6316 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6317 we, in fact, found any matching reloads. */
6320 && max_input_address_opnum <= min_conflicting_input_opnum)
6322 for (j = 0; j < n_reloads; j++)
6323 if (i != j && reload_reg_rtx[j] != 0
6324 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6325 && (! conflicting_input
6326 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6327 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6329 reload_when_needed[i] = RELOAD_OTHER;
6331 reload_spill_index[j] = -1;
6332 transfer_replacements (i, j);
6335 /* If this is now RELOAD_OTHER, look for any reloads that load
6336 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6337 if they were for inputs, RELOAD_OTHER for outputs. Note that
6338 this test is equivalent to looking for reloads for this operand
6341 if (reload_when_needed[i] == RELOAD_OTHER)
6342 for (j = 0; j < n_reloads; j++)
6343 if (reload_in[j] != 0
6344 && reload_when_needed[i] != RELOAD_OTHER
6345 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6347 reload_when_needed[j]
6348 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6349 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6350 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6356 /* Output insns to reload values in and out of the chosen reload regs. */
6359 emit_reload_insns (chain)
6360 struct insn_chain *chain;
6362 rtx insn = chain->insn;
6365 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6366 rtx other_input_address_reload_insns = 0;
6367 rtx other_input_reload_insns = 0;
6368 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6369 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6370 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6371 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6372 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6373 rtx operand_reload_insns = 0;
6374 rtx other_operand_reload_insns = 0;
6375 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6376 rtx following_insn = NEXT_INSN (insn);
6377 rtx before_insn = PREV_INSN (insn);
6379 /* Values to be put in spill_reg_store are put here first. */
6380 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6381 HARD_REG_SET reg_reloaded_died;
6383 CLEAR_HARD_REG_SET (reg_reloaded_died);
6385 for (j = 0; j < reload_n_operands; j++)
6386 input_reload_insns[j] = input_address_reload_insns[j]
6387 = inpaddr_address_reload_insns[j]
6388 = output_reload_insns[j] = output_address_reload_insns[j]
6389 = outaddr_address_reload_insns[j]
6390 = other_output_reload_insns[j] = 0;
6392 /* Now output the instructions to copy the data into and out of the
6393 reload registers. Do these in the order that the reloads were reported,
6394 since reloads of base and index registers precede reloads of operands
6395 and the operands may need the base and index registers reloaded. */
6397 for (j = 0; j < n_reloads; j++)
6400 rtx oldequiv_reg = 0;
6401 rtx this_reload_insn = 0;
6402 int expect_occurrences = 1;
6404 if (reload_reg_rtx[j]
6405 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6406 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6408 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6409 ? reload_in_reg[j] : reload_in[j]);
6412 /* AUTO_INC reloads need to be handled even if inherited. We got an
6413 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6414 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6415 && ! rtx_equal_p (reload_reg_rtx[j], old)
6416 && reload_reg_rtx[j] != 0)
6418 register rtx reloadreg = reload_reg_rtx[j];
6420 enum machine_mode mode;
6423 /* Determine the mode to reload in.
6424 This is very tricky because we have three to choose from.
6425 There is the mode the insn operand wants (reload_inmode[J]).
6426 There is the mode of the reload register RELOADREG.
6427 There is the intrinsic mode of the operand, which we could find
6428 by stripping some SUBREGs.
6429 It turns out that RELOADREG's mode is irrelevant:
6430 we can change that arbitrarily.
6432 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6433 then the reload reg may not support QImode moves, so use SImode.
6434 If foo is in memory due to spilling a pseudo reg, this is safe,
6435 because the QImode value is in the least significant part of a
6436 slot big enough for a SImode. If foo is some other sort of
6437 memory reference, then it is impossible to reload this case,
6438 so previous passes had better make sure this never happens.
6440 Then consider a one-word union which has SImode and one of its
6441 members is a float, being fetched as (SUBREG:SF union:SI).
6442 We must fetch that as SFmode because we could be loading into
6443 a float-only register. In this case OLD's mode is correct.
6445 Consider an immediate integer: it has VOIDmode. Here we need
6446 to get a mode from something else.
6448 In some cases, there is a fourth mode, the operand's
6449 containing mode. If the insn specifies a containing mode for
6450 this operand, it overrides all others.
6452 I am not sure whether the algorithm here is always right,
6453 but it does the right things in those cases. */
6455 mode = GET_MODE (old);
6456 if (mode == VOIDmode)
6457 mode = reload_inmode[j];
6459 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6460 /* If we need a secondary register for this operation, see if
6461 the value is already in a register in that class. Don't
6462 do this if the secondary register will be used as a scratch
6465 if (reload_secondary_in_reload[j] >= 0
6466 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6469 = find_equiv_reg (old, insn,
6470 reload_reg_class[reload_secondary_in_reload[j]],
6471 -1, NULL_PTR, 0, mode);
6474 /* If reloading from memory, see if there is a register
6475 that already holds the same value. If so, reload from there.
6476 We can pass 0 as the reload_reg_p argument because
6477 any other reload has either already been emitted,
6478 in which case find_equiv_reg will see the reload-insn,
6479 or has yet to be emitted, in which case it doesn't matter
6480 because we will use this equiv reg right away. */
6482 if (oldequiv == 0 && optimize
6483 && (GET_CODE (old) == MEM
6484 || (GET_CODE (old) == REG
6485 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6486 && reg_renumber[REGNO (old)] < 0)))
6487 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6488 -1, NULL_PTR, 0, mode);
6492 int regno = true_regnum (oldequiv);
6494 /* Don't use OLDEQUIV if any other reload changes it at an
6495 earlier stage of this insn or at this stage. */
6496 if (! reload_reg_free_for_value_p (regno, reload_opnum[j],
6497 reload_when_needed[j],
6498 reload_in[j], const0_rtx, j,
6502 /* If it is no cheaper to copy from OLDEQUIV into the
6503 reload register than it would be to move from memory,
6504 don't use it. Likewise, if we need a secondary register
6508 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6509 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6510 reload_reg_class[j])
6511 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6512 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6513 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6517 #ifdef SECONDARY_MEMORY_NEEDED
6518 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6519 reload_reg_class[j],
6526 /* delete_output_reload is only invoked properly if old contains
6527 the original pseudo register. Since this is replaced with a
6528 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6529 find the pseudo in RELOAD_IN_REG. */
6531 && reload_override_in[j]
6532 && GET_CODE (reload_in_reg[j]) == REG)
6535 old = reload_in_reg[j];
6539 else if (GET_CODE (oldequiv) == REG)
6540 oldequiv_reg = oldequiv;
6541 else if (GET_CODE (oldequiv) == SUBREG)
6542 oldequiv_reg = SUBREG_REG (oldequiv);
6544 /* If we are reloading from a register that was recently stored in
6545 with an output-reload, see if we can prove there was
6546 actually no need to store the old value in it. */
6548 if (optimize && GET_CODE (oldequiv) == REG
6549 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6550 && spill_reg_store[REGNO (oldequiv)]
6551 && GET_CODE (old) == REG
6552 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6553 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6554 reload_out_reg[j])))
6555 delete_output_reload (insn, j, REGNO (oldequiv));
6557 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6558 then load RELOADREG from OLDEQUIV. Note that we cannot use
6559 gen_lowpart_common since it can do the wrong thing when
6560 RELOADREG has a multi-word mode. Note that RELOADREG
6561 must always be a REG here. */
6563 if (GET_MODE (reloadreg) != mode)
6564 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6565 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6566 oldequiv = SUBREG_REG (oldequiv);
6567 if (GET_MODE (oldequiv) != VOIDmode
6568 && mode != GET_MODE (oldequiv))
6569 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6571 /* Switch to the right place to emit the reload insns. */
6572 switch (reload_when_needed[j])
6575 where = &other_input_reload_insns;
6577 case RELOAD_FOR_INPUT:
6578 where = &input_reload_insns[reload_opnum[j]];
6580 case RELOAD_FOR_INPUT_ADDRESS:
6581 where = &input_address_reload_insns[reload_opnum[j]];
6583 case RELOAD_FOR_INPADDR_ADDRESS:
6584 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6586 case RELOAD_FOR_OUTPUT_ADDRESS:
6587 where = &output_address_reload_insns[reload_opnum[j]];
6589 case RELOAD_FOR_OUTADDR_ADDRESS:
6590 where = &outaddr_address_reload_insns[reload_opnum[j]];
6592 case RELOAD_FOR_OPERAND_ADDRESS:
6593 where = &operand_reload_insns;
6595 case RELOAD_FOR_OPADDR_ADDR:
6596 where = &other_operand_reload_insns;
6598 case RELOAD_FOR_OTHER_ADDRESS:
6599 where = &other_input_address_reload_insns;
6605 push_to_sequence (*where);
6608 /* Auto-increment addresses must be reloaded in a special way. */
6609 if (reload_out[j] && ! reload_out_reg[j])
6611 /* We are not going to bother supporting the case where a
6612 incremented register can't be copied directly from
6613 OLDEQUIV since this seems highly unlikely. */
6614 if (reload_secondary_in_reload[j] >= 0)
6617 if (reload_inherited[j])
6618 oldequiv = reloadreg;
6620 old = XEXP (reload_in_reg[j], 0);
6622 if (optimize && GET_CODE (oldequiv) == REG
6623 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6624 && spill_reg_store[REGNO (oldequiv)]
6625 && GET_CODE (old) == REG
6626 && (dead_or_set_p (insn,
6627 spill_reg_stored_to[REGNO (oldequiv)])
6628 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6630 delete_output_reload (insn, j, REGNO (oldequiv));
6632 /* Prevent normal processing of this reload. */
6634 /* Output a special code sequence for this case. */
6635 new_spill_reg_store[REGNO (reloadreg)]
6636 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6640 /* If we are reloading a pseudo-register that was set by the previous
6641 insn, see if we can get rid of that pseudo-register entirely
6642 by redirecting the previous insn into our reload register. */
6644 else if (optimize && GET_CODE (old) == REG
6645 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6646 && dead_or_set_p (insn, old)
6647 /* This is unsafe if some other reload
6648 uses the same reg first. */
6649 && reload_reg_free_for_value_p (REGNO (reloadreg),
6651 reload_when_needed[j],
6655 rtx temp = PREV_INSN (insn);
6656 while (temp && GET_CODE (temp) == NOTE)
6657 temp = PREV_INSN (temp);
6659 && GET_CODE (temp) == INSN
6660 && GET_CODE (PATTERN (temp)) == SET
6661 && SET_DEST (PATTERN (temp)) == old
6662 /* Make sure we can access insn_operand_constraint. */
6663 && asm_noperands (PATTERN (temp)) < 0
6664 /* This is unsafe if prev insn rejects our reload reg. */
6665 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6667 /* This is unsafe if operand occurs more than once in current
6668 insn. Perhaps some occurrences aren't reloaded. */
6669 && count_occurrences (PATTERN (insn), old) == 1
6670 /* Don't risk splitting a matching pair of operands. */
6671 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6673 /* Store into the reload register instead of the pseudo. */
6674 SET_DEST (PATTERN (temp)) = reloadreg;
6676 /* If the previous insn is an output reload, the source is
6677 a reload register, and its spill_reg_store entry will
6678 contain the previous destination. This is now
6680 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6681 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6683 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6684 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6687 /* If these are the only uses of the pseudo reg,
6688 pretend for GDB it lives in the reload reg we used. */
6689 if (REG_N_DEATHS (REGNO (old)) == 1
6690 && REG_N_SETS (REGNO (old)) == 1)
6692 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6693 alter_reg (REGNO (old), -1);
6699 /* We can't do that, so output an insn to load RELOADREG. */
6703 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6704 rtx second_reload_reg = 0;
6705 enum insn_code icode;
6707 /* If we have a secondary reload, pick up the secondary register
6708 and icode, if any. If OLDEQUIV and OLD are different or
6709 if this is an in-out reload, recompute whether or not we
6710 still need a secondary register and what the icode should
6711 be. If we still need a secondary register and the class or
6712 icode is different, go back to reloading from OLD if using
6713 OLDEQUIV means that we got the wrong type of register. We
6714 cannot have different class or icode due to an in-out reload
6715 because we don't make such reloads when both the input and
6716 output need secondary reload registers. */
6718 if (reload_secondary_in_reload[j] >= 0)
6720 int secondary_reload = reload_secondary_in_reload[j];
6721 rtx real_oldequiv = oldequiv;
6724 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6725 and similarly for OLD.
6726 See comments in get_secondary_reload in reload.c. */
6727 /* If it is a pseudo that cannot be replaced with its
6728 equivalent MEM, we must fall back to reload_in, which
6729 will have all the necessary substitutions registered. */
6731 if (GET_CODE (oldequiv) == REG
6732 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6733 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6735 if (reg_equiv_address[REGNO (oldequiv)]
6736 || num_not_at_initial_offset)
6737 real_oldequiv = reload_in[j];
6739 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6742 if (GET_CODE (old) == REG
6743 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6744 && reg_equiv_memory_loc[REGNO (old)] != 0)
6746 if (reg_equiv_address[REGNO (old)]
6747 || num_not_at_initial_offset)
6748 real_old = reload_in[j];
6750 real_old = reg_equiv_mem[REGNO (old)];
6753 second_reload_reg = reload_reg_rtx[secondary_reload];
6754 icode = reload_secondary_in_icode[j];
6756 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6757 || (reload_in[j] != 0 && reload_out[j] != 0))
6759 enum reg_class new_class
6760 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6761 mode, real_oldequiv);
6763 if (new_class == NO_REGS)
6764 second_reload_reg = 0;
6767 enum insn_code new_icode;
6768 enum machine_mode new_mode;
6770 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6771 REGNO (second_reload_reg)))
6772 oldequiv = old, real_oldequiv = real_old;
6775 new_icode = reload_in_optab[(int) mode];
6776 if (new_icode != CODE_FOR_nothing
6777 && ((insn_operand_predicate[(int) new_icode][0]
6778 && ! ((*insn_operand_predicate[(int) new_icode][0])
6780 || (insn_operand_predicate[(int) new_icode][1]
6781 && ! ((*insn_operand_predicate[(int) new_icode][1])
6782 (real_oldequiv, mode)))))
6783 new_icode = CODE_FOR_nothing;
6785 if (new_icode == CODE_FOR_nothing)
6788 new_mode = insn_operand_mode[(int) new_icode][2];
6790 if (GET_MODE (second_reload_reg) != new_mode)
6792 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6794 oldequiv = old, real_oldequiv = real_old;
6797 = gen_rtx_REG (new_mode,
6798 REGNO (second_reload_reg));
6804 /* If we still need a secondary reload register, check
6805 to see if it is being used as a scratch or intermediate
6806 register and generate code appropriately. If we need
6807 a scratch register, use REAL_OLDEQUIV since the form of
6808 the insn may depend on the actual address if it is
6811 if (second_reload_reg)
6813 if (icode != CODE_FOR_nothing)
6815 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6816 second_reload_reg));
6821 /* See if we need a scratch register to load the
6822 intermediate register (a tertiary reload). */
6823 enum insn_code tertiary_icode
6824 = reload_secondary_in_icode[secondary_reload];
6826 if (tertiary_icode != CODE_FOR_nothing)
6828 rtx third_reload_reg
6829 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6831 emit_insn ((GEN_FCN (tertiary_icode)
6832 (second_reload_reg, real_oldequiv,
6833 third_reload_reg)));
6836 gen_reload (second_reload_reg, real_oldequiv,
6838 reload_when_needed[j]);
6840 oldequiv = second_reload_reg;
6846 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6848 rtx real_oldequiv = oldequiv;
6850 if ((GET_CODE (oldequiv) == REG
6851 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6852 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6853 || (GET_CODE (oldequiv) == SUBREG
6854 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6855 && (REGNO (SUBREG_REG (oldequiv))
6856 >= FIRST_PSEUDO_REGISTER)
6857 && (reg_equiv_memory_loc
6858 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6859 real_oldequiv = reload_in[j];
6860 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
6861 reload_when_needed[j]);
6866 this_reload_insn = get_last_insn ();
6867 /* End this sequence. */
6868 *where = get_insns ();
6871 /* Update reload_override_in so that delete_address_reloads_1
6872 can see the actual register usage. */
6874 reload_override_in[j] = oldequiv;
6877 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6878 e.g. inheriting a SImode output reload for
6879 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6880 if (optimize && reload_inherited[j] && reload_in[j]
6881 && GET_CODE (reload_in[j]) == MEM
6882 && GET_CODE (reload_in_reg[j]) == MEM
6883 && reload_spill_index[j] >= 0
6884 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6887 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6889 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6892 /* If we are reloading a register that was recently stored in with an
6893 output-reload, see if we can prove there was
6894 actually no need to store the old value in it. */
6897 && (reload_inherited[j] || reload_override_in[j])
6898 && reload_reg_rtx[j]
6899 && GET_CODE (reload_reg_rtx[j]) == REG
6900 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
6902 /* There doesn't seem to be any reason to restrict this to pseudos
6903 and doing so loses in the case where we are copying from a
6904 register of the wrong class. */
6905 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6906 >= FIRST_PSEUDO_REGISTER
6908 /* The insn might have already some references to stackslots
6909 replaced by MEMs, while reload_out_reg still names the
6911 && (dead_or_set_p (insn,
6912 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6913 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
6914 reload_out_reg[j])))
6915 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
6917 /* Input-reloading is done. Now do output-reloading,
6918 storing the value from the reload-register after the main insn
6919 if reload_out[j] is nonzero.
6921 ??? At some point we need to support handling output reloads of
6922 JUMP_INSNs or insns that set cc0. */
6924 /* If this is an output reload that stores something that is
6925 not loaded in this same reload, see if we can eliminate a previous
6928 rtx pseudo = reload_out_reg[j];
6931 && GET_CODE (pseudo) == REG
6932 && ! rtx_equal_p (reload_in_reg[j], pseudo)
6933 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6934 && reg_last_reload_reg[REGNO (pseudo)])
6936 int pseudo_no = REGNO (pseudo);
6937 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6939 /* We don't need to test full validity of last_regno for
6940 inherit here; we only want to know if the store actually
6941 matches the pseudo. */
6942 if (reg_reloaded_contents[last_regno] == pseudo_no
6943 && spill_reg_store[last_regno]
6944 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6945 delete_output_reload (insn, j, last_regno);
6949 old = reload_out_reg[j];
6951 && reload_reg_rtx[j] != old
6952 && reload_reg_rtx[j] != 0)
6954 register rtx reloadreg = reload_reg_rtx[j];
6955 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6956 register rtx second_reloadreg = 0;
6959 enum machine_mode mode;
6962 /* An output operand that dies right away does need a reload,
6963 but need not be copied from it. Show the new location in the
6965 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6966 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6968 XEXP (note, 0) = reload_reg_rtx[j];
6971 /* Likewise for a SUBREG of an operand that dies. */
6972 else if (GET_CODE (old) == SUBREG
6973 && GET_CODE (SUBREG_REG (old)) == REG
6974 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6977 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6981 else if (GET_CODE (old) == SCRATCH)
6982 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6983 but we don't want to make an output reload. */
6987 /* Strip off of OLD any size-increasing SUBREGs such as
6988 (SUBREG:SI foo:QI 0). */
6990 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6991 && (GET_MODE_SIZE (GET_MODE (old))
6992 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6993 old = SUBREG_REG (old);
6996 /* If is a JUMP_INSN, we can't support output reloads yet. */
6997 if (GET_CODE (insn) == JUMP_INSN)
7000 if (reload_when_needed[j] == RELOAD_OTHER)
7003 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7005 old = reload_out[j];
7007 /* Determine the mode to reload in.
7008 See comments above (for input reloading). */
7010 mode = GET_MODE (old);
7011 if (mode == VOIDmode)
7013 /* VOIDmode should never happen for an output. */
7014 if (asm_noperands (PATTERN (insn)) < 0)
7015 /* It's the compiler's fault. */
7016 fatal_insn ("VOIDmode on an output", insn);
7017 error_for_asm (insn, "output operand is constant in `asm'");
7018 /* Prevent crash--use something we know is valid. */
7020 old = gen_rtx_REG (mode, REGNO (reloadreg));
7023 if (GET_MODE (reloadreg) != mode)
7024 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7026 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7028 /* If we need two reload regs, set RELOADREG to the intermediate
7029 one, since it will be stored into OLD. We might need a secondary
7030 register only for an input reload, so check again here. */
7032 if (reload_secondary_out_reload[j] >= 0)
7036 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7037 && reg_equiv_mem[REGNO (old)] != 0)
7038 real_old = reg_equiv_mem[REGNO (old)];
7040 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7044 second_reloadreg = reloadreg;
7045 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7047 /* See if RELOADREG is to be used as a scratch register
7048 or as an intermediate register. */
7049 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7051 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7052 (real_old, second_reloadreg, reloadreg)));
7057 /* See if we need both a scratch and intermediate reload
7060 int secondary_reload = reload_secondary_out_reload[j];
7061 enum insn_code tertiary_icode
7062 = reload_secondary_out_icode[secondary_reload];
7064 if (GET_MODE (reloadreg) != mode)
7065 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7067 if (tertiary_icode != CODE_FOR_nothing)
7070 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7073 /* Copy primary reload reg to secondary reload reg.
7074 (Note that these have been swapped above, then
7075 secondary reload reg to OLD using our insn. */
7077 /* If REAL_OLD is a paradoxical SUBREG, remove it
7078 and try to put the opposite SUBREG on
7080 if (GET_CODE (real_old) == SUBREG
7081 && (GET_MODE_SIZE (GET_MODE (real_old))
7082 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7083 && 0 != (tem = gen_lowpart_common
7084 (GET_MODE (SUBREG_REG (real_old)),
7086 real_old = SUBREG_REG (real_old), reloadreg = tem;
7088 gen_reload (reloadreg, second_reloadreg,
7089 reload_opnum[j], reload_when_needed[j]);
7090 emit_insn ((GEN_FCN (tertiary_icode)
7091 (real_old, reloadreg, third_reloadreg)));
7096 /* Copy between the reload regs here and then to
7099 gen_reload (reloadreg, second_reloadreg,
7100 reload_opnum[j], reload_when_needed[j]);
7106 /* Output the last reload insn. */
7111 /* Don't output the last reload if OLD is not the dest of
7112 INSN and is in the src and is clobbered by INSN. */
7113 if (! flag_expensive_optimizations
7114 || GET_CODE (old) != REG
7115 || !(set = single_set (insn))
7116 || rtx_equal_p (old, SET_DEST (set))
7117 || !reg_mentioned_p (old, SET_SRC (set))
7118 || !regno_clobbered_p (REGNO (old), insn))
7119 gen_reload (old, reloadreg, reload_opnum[j],
7120 reload_when_needed[j]);
7123 /* Look at all insns we emitted, just to be safe. */
7124 for (p = get_insns (); p; p = NEXT_INSN (p))
7125 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7127 rtx pat = PATTERN (p);
7129 /* If this output reload doesn't come from a spill reg,
7130 clear any memory of reloaded copies of the pseudo reg.
7131 If this output reload comes from a spill reg,
7132 reg_has_output_reload will make this do nothing. */
7133 note_stores (pat, forget_old_reloads_1);
7135 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7137 rtx set = single_set (insn);
7138 if (reload_spill_index[j] < 0
7140 && SET_SRC (set) == reload_reg_rtx[j])
7142 int src = REGNO (SET_SRC (set));
7144 reload_spill_index[j] = src;
7145 SET_HARD_REG_BIT (reg_is_output_reload, src);
7146 if (find_regno_note (insn, REG_DEAD, src))
7147 SET_HARD_REG_BIT (reg_reloaded_died, src);
7149 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7151 int s = reload_secondary_out_reload[j];
7152 set = single_set (p);
7153 /* If this reload copies only to the secondary reload
7154 register, the secondary reload does the actual
7156 if (s >= 0 && set == NULL_RTX)
7157 ; /* We can't tell what function the secondary reload
7158 has and where the actual store to the pseudo is
7159 made; leave new_spill_reg_store alone. */
7161 && SET_SRC (set) == reload_reg_rtx[j]
7162 && SET_DEST (set) == reload_reg_rtx[s])
7164 /* Usually the next instruction will be the
7165 secondary reload insn; if we can confirm
7166 that it is, setting new_spill_reg_store to
7167 that insn will allow an extra optimization. */
7168 rtx s_reg = reload_reg_rtx[s];
7169 rtx next = NEXT_INSN (p);
7170 reload_out[s] = reload_out[j];
7171 reload_out_reg[s] = reload_out_reg[j];
7172 set = single_set (next);
7173 if (set && SET_SRC (set) == s_reg
7174 && ! new_spill_reg_store[REGNO (s_reg)])
7176 SET_HARD_REG_BIT (reg_is_output_reload,
7178 new_spill_reg_store[REGNO (s_reg)] = next;
7182 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7187 if (reload_when_needed[j] == RELOAD_OTHER)
7189 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7190 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7193 output_reload_insns[reload_opnum[j]] = get_insns ();
7199 /* Now write all the insns we made for reloads in the order expected by
7200 the allocation functions. Prior to the insn being reloaded, we write
7201 the following reloads:
7203 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7205 RELOAD_OTHER reloads.
7207 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7208 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7209 RELOAD_FOR_INPUT reload for the operand.
7211 RELOAD_FOR_OPADDR_ADDRS reloads.
7213 RELOAD_FOR_OPERAND_ADDRESS reloads.
7215 After the insn being reloaded, we write the following:
7217 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7218 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7219 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7220 reloads for the operand. The RELOAD_OTHER output reloads are
7221 output in descending order by reload number. */
7223 emit_insns_before (other_input_address_reload_insns, insn);
7224 emit_insns_before (other_input_reload_insns, insn);
7226 for (j = 0; j < reload_n_operands; j++)
7228 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7229 emit_insns_before (input_address_reload_insns[j], insn);
7230 emit_insns_before (input_reload_insns[j], insn);
7233 emit_insns_before (other_operand_reload_insns, insn);
7234 emit_insns_before (operand_reload_insns, insn);
7236 for (j = 0; j < reload_n_operands; j++)
7238 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7239 emit_insns_before (output_address_reload_insns[j], following_insn);
7240 emit_insns_before (output_reload_insns[j], following_insn);
7241 emit_insns_before (other_output_reload_insns[j], following_insn);
7244 /* Keep basic block info up to date. */
7247 if (basic_block_head[chain->block] == insn)
7248 basic_block_head[chain->block] = NEXT_INSN (before_insn);
7249 if (basic_block_end[chain->block] == insn)
7250 basic_block_end[chain->block] = PREV_INSN (following_insn);
7253 /* For all the spill regs newly reloaded in this instruction,
7254 record what they were reloaded from, so subsequent instructions
7255 can inherit the reloads.
7257 Update spill_reg_store for the reloads of this insn.
7258 Copy the elements that were updated in the loop above. */
7260 for (j = 0; j < n_reloads; j++)
7262 register int r = reload_order[j];
7263 register int i = reload_spill_index[r];
7265 /* I is nonneg if this reload used a register.
7266 If reload_reg_rtx[r] is 0, this is an optional reload
7267 that we opted to ignore. */
7269 if (i >= 0 && reload_reg_rtx[r] != 0)
7272 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7274 int part_reaches_end = 0;
7275 int all_reaches_end = 1;
7277 /* For a multi register reload, we need to check if all or part
7278 of the value lives to the end. */
7279 for (k = 0; k < nr; k++)
7281 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7282 reload_when_needed[r]))
7283 part_reaches_end = 1;
7285 all_reaches_end = 0;
7288 /* Ignore reloads that don't reach the end of the insn in
7290 if (all_reaches_end)
7292 /* First, clear out memory of what used to be in this spill reg.
7293 If consecutive registers are used, clear them all. */
7295 for (k = 0; k < nr; k++)
7296 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7298 /* Maybe the spill reg contains a copy of reload_out. */
7299 if (reload_out[r] != 0
7300 && (GET_CODE (reload_out[r]) == REG
7302 || ! reload_out_reg[r]
7304 || GET_CODE (reload_out_reg[r]) == REG))
7306 rtx out = (GET_CODE (reload_out[r]) == REG
7310 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7311 register int nregno = REGNO (out);
7312 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7313 : HARD_REGNO_NREGS (nregno,
7314 GET_MODE (reload_reg_rtx[r])));
7316 spill_reg_store[i] = new_spill_reg_store[i];
7317 spill_reg_stored_to[i] = out;
7318 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7320 /* If NREGNO is a hard register, it may occupy more than
7321 one register. If it does, say what is in the
7322 rest of the registers assuming that both registers
7323 agree on how many words the object takes. If not,
7324 invalidate the subsequent registers. */
7326 if (nregno < FIRST_PSEUDO_REGISTER)
7327 for (k = 1; k < nnr; k++)
7328 reg_last_reload_reg[nregno + k]
7330 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7331 REGNO (reload_reg_rtx[r]) + k)
7334 /* Now do the inverse operation. */
7335 for (k = 0; k < nr; k++)
7337 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7338 reg_reloaded_contents[i + k]
7339 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7342 reg_reloaded_insn[i + k] = insn;
7343 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7347 /* Maybe the spill reg contains a copy of reload_in. Only do
7348 something if there will not be an output reload for
7349 the register being reloaded. */
7350 else if (reload_out_reg[r] == 0
7351 && reload_in[r] != 0
7352 && ((GET_CODE (reload_in[r]) == REG
7353 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7354 && ! reg_has_output_reload[REGNO (reload_in[r])])
7355 || (GET_CODE (reload_in_reg[r]) == REG
7356 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7357 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7359 register int nregno;
7362 if (GET_CODE (reload_in[r]) == REG
7363 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7364 nregno = REGNO (reload_in[r]);
7365 else if (GET_CODE (reload_in_reg[r]) == REG)
7366 nregno = REGNO (reload_in_reg[r]);
7368 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7370 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7371 : HARD_REGNO_NREGS (nregno,
7372 GET_MODE (reload_reg_rtx[r])));
7374 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7376 if (nregno < FIRST_PSEUDO_REGISTER)
7377 for (k = 1; k < nnr; k++)
7378 reg_last_reload_reg[nregno + k]
7380 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7381 REGNO (reload_reg_rtx[r]) + k)
7384 /* Unless we inherited this reload, show we haven't
7385 recently done a store.
7386 Previous stores of inherited auto_inc expressions
7387 also have to be discarded. */
7388 if (! reload_inherited[r]
7389 || (reload_out[r] && ! reload_out_reg[r]))
7390 spill_reg_store[i] = 0;
7392 for (k = 0; k < nr; k++)
7394 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7395 reg_reloaded_contents[i + k]
7396 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7399 reg_reloaded_insn[i + k] = insn;
7400 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7405 /* However, if part of the reload reaches the end, then we must
7406 invalidate the old info for the part that survives to the end. */
7407 else if (part_reaches_end)
7409 for (k = 0; k < nr; k++)
7410 if (reload_reg_reaches_end_p (i + k,
7412 reload_when_needed[r]))
7413 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7417 /* The following if-statement was #if 0'd in 1.34 (or before...).
7418 It's reenabled in 1.35 because supposedly nothing else
7419 deals with this problem. */
7421 /* If a register gets output-reloaded from a non-spill register,
7422 that invalidates any previous reloaded copy of it.
7423 But forget_old_reloads_1 won't get to see it, because
7424 it thinks only about the original insn. So invalidate it here. */
7425 if (i < 0 && reload_out[r] != 0
7426 && (GET_CODE (reload_out[r]) == REG
7427 || (GET_CODE (reload_out[r]) == MEM
7428 && GET_CODE (reload_out_reg[r]) == REG)))
7430 rtx out = (GET_CODE (reload_out[r]) == REG
7431 ? reload_out[r] : reload_out_reg[r]);
7432 register int nregno = REGNO (out);
7433 if (nregno >= FIRST_PSEUDO_REGISTER)
7435 rtx src_reg, store_insn;
7437 reg_last_reload_reg[nregno] = 0;
7439 /* If we can find a hard register that is stored, record
7440 the storing insn so that we may delete this insn with
7441 delete_output_reload. */
7442 src_reg = reload_reg_rtx[r];
7444 /* If this is an optional reload, try to find the source reg
7445 from an input reload. */
7448 rtx set = single_set (insn);
7449 if (SET_DEST (set) == reload_out[r])
7453 src_reg = SET_SRC (set);
7455 for (k = 0; k < n_reloads; k++)
7457 if (reload_in[k] == src_reg)
7459 src_reg = reload_reg_rtx[k];
7466 store_insn = new_spill_reg_store[REGNO (src_reg)];
7467 if (src_reg && GET_CODE (src_reg) == REG
7468 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7470 int src_regno = REGNO (src_reg);
7471 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7472 /* The place where to find a death note varies with
7473 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7474 necessarily checked exactly in the code that moves
7475 notes, so just check both locations. */
7476 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7478 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7481 spill_reg_store[src_regno + nr] = store_insn;
7482 spill_reg_stored_to[src_regno + nr] = out;
7483 reg_reloaded_contents[src_regno + nr] = nregno;
7484 reg_reloaded_insn[src_regno + nr] = store_insn;
7485 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7486 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7487 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7489 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7491 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7493 reg_last_reload_reg[nregno] = src_reg;
7498 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7500 while (num_regs-- > 0)
7501 reg_last_reload_reg[nregno + num_regs] = 0;
7505 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7508 /* Emit code to perform a reload from IN (which may be a reload register) to
7509 OUT (which may also be a reload register). IN or OUT is from operand
7510 OPNUM with reload type TYPE.
7512 Returns first insn emitted. */
7515 gen_reload (out, in, opnum, type)
7519 enum reload_type type;
7521 rtx last = get_last_insn ();
7524 /* If IN is a paradoxical SUBREG, remove it and try to put the
7525 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7526 if (GET_CODE (in) == SUBREG
7527 && (GET_MODE_SIZE (GET_MODE (in))
7528 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7529 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7530 in = SUBREG_REG (in), out = tem;
7531 else if (GET_CODE (out) == SUBREG
7532 && (GET_MODE_SIZE (GET_MODE (out))
7533 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7534 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7535 out = SUBREG_REG (out), in = tem;
7537 /* How to do this reload can get quite tricky. Normally, we are being
7538 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7539 register that didn't get a hard register. In that case we can just
7540 call emit_move_insn.
7542 We can also be asked to reload a PLUS that adds a register or a MEM to
7543 another register, constant or MEM. This can occur during frame pointer
7544 elimination and while reloading addresses. This case is handled by
7545 trying to emit a single insn to perform the add. If it is not valid,
7546 we use a two insn sequence.
7548 Finally, we could be called to handle an 'o' constraint by putting
7549 an address into a register. In that case, we first try to do this
7550 with a named pattern of "reload_load_address". If no such pattern
7551 exists, we just emit a SET insn and hope for the best (it will normally
7552 be valid on machines that use 'o').
7554 This entire process is made complex because reload will never
7555 process the insns we generate here and so we must ensure that
7556 they will fit their constraints and also by the fact that parts of
7557 IN might be being reloaded separately and replaced with spill registers.
7558 Because of this, we are, in some sense, just guessing the right approach
7559 here. The one listed above seems to work.
7561 ??? At some point, this whole thing needs to be rethought. */
7563 if (GET_CODE (in) == PLUS
7564 && (GET_CODE (XEXP (in, 0)) == REG
7565 || GET_CODE (XEXP (in, 0)) == SUBREG
7566 || GET_CODE (XEXP (in, 0)) == MEM)
7567 && (GET_CODE (XEXP (in, 1)) == REG
7568 || GET_CODE (XEXP (in, 1)) == SUBREG
7569 || CONSTANT_P (XEXP (in, 1))
7570 || GET_CODE (XEXP (in, 1)) == MEM))
7572 /* We need to compute the sum of a register or a MEM and another
7573 register, constant, or MEM, and put it into the reload
7574 register. The best possible way of doing this is if the machine
7575 has a three-operand ADD insn that accepts the required operands.
7577 The simplest approach is to try to generate such an insn and see if it
7578 is recognized and matches its constraints. If so, it can be used.
7580 It might be better not to actually emit the insn unless it is valid,
7581 but we need to pass the insn as an operand to `recog' and
7582 `extract_insn' and it is simpler to emit and then delete the insn if
7583 not valid than to dummy things up. */
7585 rtx op0, op1, tem, insn;
7588 op0 = find_replacement (&XEXP (in, 0));
7589 op1 = find_replacement (&XEXP (in, 1));
7591 /* Since constraint checking is strict, commutativity won't be
7592 checked, so we need to do that here to avoid spurious failure
7593 if the add instruction is two-address and the second operand
7594 of the add is the same as the reload reg, which is frequently
7595 the case. If the insn would be A = B + A, rearrange it so
7596 it will be A = A + B as constrain_operands expects. */
7598 if (GET_CODE (XEXP (in, 1)) == REG
7599 && REGNO (out) == REGNO (XEXP (in, 1)))
7600 tem = op0, op0 = op1, op1 = tem;
7602 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7603 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7605 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7606 code = recog_memoized (insn);
7610 extract_insn (insn);
7611 /* We want constrain operands to treat this insn strictly in
7612 its validity determination, i.e., the way it would after reload
7614 if (constrain_operands (1))
7618 delete_insns_since (last);
7620 /* If that failed, we must use a conservative two-insn sequence.
7621 use move to copy constant, MEM, or pseudo register to the reload
7622 register since "move" will be able to handle an arbitrary operand,
7623 unlike add which can't, in general. Then add the registers.
7625 If there is another way to do this for a specific machine, a
7626 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7629 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7630 || (GET_CODE (op1) == REG
7631 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7632 tem = op0, op0 = op1, op1 = tem;
7634 gen_reload (out, op0, opnum, type);
7636 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7637 This fixes a problem on the 32K where the stack pointer cannot
7638 be used as an operand of an add insn. */
7640 if (rtx_equal_p (op0, op1))
7643 insn = emit_insn (gen_add2_insn (out, op1));
7645 /* If that failed, copy the address register to the reload register.
7646 Then add the constant to the reload register. */
7648 code = recog_memoized (insn);
7652 extract_insn (insn);
7653 /* We want constrain operands to treat this insn strictly in
7654 its validity determination, i.e., the way it would after reload
7656 if (constrain_operands (1))
7658 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7660 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7665 delete_insns_since (last);
7667 gen_reload (out, op1, opnum, type);
7668 insn = emit_insn (gen_add2_insn (out, op0));
7669 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7672 #ifdef SECONDARY_MEMORY_NEEDED
7673 /* If we need a memory location to do the move, do it that way. */
7674 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7675 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7676 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7677 REGNO_REG_CLASS (REGNO (out)),
7680 /* Get the memory to use and rewrite both registers to its mode. */
7681 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7683 if (GET_MODE (loc) != GET_MODE (out))
7684 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7686 if (GET_MODE (loc) != GET_MODE (in))
7687 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7689 gen_reload (loc, in, opnum, type);
7690 gen_reload (out, loc, opnum, type);
7694 /* If IN is a simple operand, use gen_move_insn. */
7695 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7696 emit_insn (gen_move_insn (out, in));
7698 #ifdef HAVE_reload_load_address
7699 else if (HAVE_reload_load_address)
7700 emit_insn (gen_reload_load_address (out, in));
7703 /* Otherwise, just write (set OUT IN) and hope for the best. */
7705 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7707 /* Return the first insn emitted.
7708 We can not just return get_last_insn, because there may have
7709 been multiple instructions emitted. Also note that gen_move_insn may
7710 emit more than one insn itself, so we can not assume that there is one
7711 insn emitted per emit_insn_before call. */
7713 return last ? NEXT_INSN (last) : get_insns ();
7716 /* Delete a previously made output-reload
7717 whose result we now believe is not needed.
7718 First we double-check.
7720 INSN is the insn now being processed.
7721 LAST_RELOAD_REG is the hard register number for which we want to delete
7722 the last output reload.
7723 J is the reload-number that originally used REG. The caller has made
7724 certain that reload J doesn't use REG any longer for input. */
7727 delete_output_reload (insn, j, last_reload_reg)
7730 int last_reload_reg;
7732 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7733 rtx reg = spill_reg_stored_to[last_reload_reg];
7736 int n_inherited = 0;
7740 /* Get the raw pseudo-register referred to. */
7742 while (GET_CODE (reg) == SUBREG)
7743 reg = SUBREG_REG (reg);
7744 substed = reg_equiv_memory_loc[REGNO (reg)];
7746 /* This is unsafe if the operand occurs more often in the current
7747 insn than it is inherited. */
7748 for (k = n_reloads - 1; k >= 0; k--)
7750 rtx reg2 = reload_in[k];
7753 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7754 reg2 = reload_in_reg[k];
7756 if (reload_out[k] && ! reload_out_reg[k])
7757 reg2 = XEXP (reload_in_reg[k], 0);
7759 while (GET_CODE (reg2) == SUBREG)
7760 reg2 = SUBREG_REG (reg2);
7761 if (rtx_equal_p (reg2, reg))
7763 if (reload_inherited[k] || reload_override_in[k] || k == j)
7766 reg2 = reload_out_reg[k];
7769 while (GET_CODE (reg2) == SUBREG)
7770 reg2 = XEXP (reg2, 0);
7771 if (rtx_equal_p (reg2, reg))
7778 n_occurrences = count_occurrences (PATTERN (insn), reg);
7780 n_occurrences += count_occurrences (PATTERN (insn), substed);
7781 if (n_occurrences > n_inherited)
7784 /* If the pseudo-reg we are reloading is no longer referenced
7785 anywhere between the store into it and here,
7786 and no jumps or labels intervene, then the value can get
7787 here through the reload reg alone.
7788 Otherwise, give up--return. */
7789 for (i1 = NEXT_INSN (output_reload_insn);
7790 i1 != insn; i1 = NEXT_INSN (i1))
7792 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7794 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7795 && reg_mentioned_p (reg, PATTERN (i1)))
7797 /* If this is USE in front of INSN, we only have to check that
7798 there are no more references than accounted for by inheritance. */
7799 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7801 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7802 i1 = NEXT_INSN (i1);
7804 if (n_occurrences <= n_inherited && i1 == insn)
7810 /* The caller has already checked that REG dies or is set in INSN.
7811 It has also checked that we are optimizing, and thus some inaccurancies
7812 in the debugging information are acceptable.
7813 So we could just delete output_reload_insn.
7814 But in some cases we can improve the debugging information without
7815 sacrificing optimization - maybe even improving the code:
7816 See if the pseudo reg has been completely replaced
7817 with reload regs. If so, delete the store insn
7818 and forget we had a stack slot for the pseudo. */
7819 if (reload_out[j] != reload_in[j]
7820 && REG_N_DEATHS (REGNO (reg)) == 1
7821 && REG_N_SETS (REGNO (reg)) == 1
7822 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7823 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7827 /* We know that it was used only between here
7828 and the beginning of the current basic block.
7829 (We also know that the last use before INSN was
7830 the output reload we are thinking of deleting, but never mind that.)
7831 Search that range; see if any ref remains. */
7832 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7834 rtx set = single_set (i2);
7836 /* Uses which just store in the pseudo don't count,
7837 since if they are the only uses, they are dead. */
7838 if (set != 0 && SET_DEST (set) == reg)
7840 if (GET_CODE (i2) == CODE_LABEL
7841 || GET_CODE (i2) == JUMP_INSN)
7843 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7844 && reg_mentioned_p (reg, PATTERN (i2)))
7846 /* Some other ref remains; just delete the output reload we
7848 delete_address_reloads (output_reload_insn, insn);
7849 PUT_CODE (output_reload_insn, NOTE);
7850 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7851 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7856 /* Delete the now-dead stores into this pseudo. */
7857 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7859 rtx set = single_set (i2);
7861 if (set != 0 && SET_DEST (set) == reg)
7863 delete_address_reloads (i2, insn);
7864 /* This might be a basic block head,
7865 thus don't use delete_insn. */
7866 PUT_CODE (i2, NOTE);
7867 NOTE_SOURCE_FILE (i2) = 0;
7868 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7870 if (GET_CODE (i2) == CODE_LABEL
7871 || GET_CODE (i2) == JUMP_INSN)
7875 /* For the debugging info,
7876 say the pseudo lives in this reload reg. */
7877 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7878 alter_reg (REGNO (reg), -1);
7880 delete_address_reloads (output_reload_insn, insn);
7881 PUT_CODE (output_reload_insn, NOTE);
7882 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7883 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7887 /* We are going to delete DEAD_INSN. Recursively delete loads of
7888 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7889 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7891 delete_address_reloads (dead_insn, current_insn)
7892 rtx dead_insn, current_insn;
7894 rtx set = single_set (dead_insn);
7895 rtx set2, dst, prev, next;
7898 rtx dst = SET_DEST (set);
7899 if (GET_CODE (dst) == MEM)
7900 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7902 /* If we deleted the store from a reloaded post_{in,de}c expression,
7903 we can delete the matching adds. */
7904 prev = PREV_INSN (dead_insn);
7905 next = NEXT_INSN (dead_insn);
7906 if (! prev || ! next)
7908 set = single_set (next);
7909 set2 = single_set (prev);
7911 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7912 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7913 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7915 dst = SET_DEST (set);
7916 if (! rtx_equal_p (dst, SET_DEST (set2))
7917 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7918 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7919 || (INTVAL (XEXP (SET_SRC (set), 1))
7920 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7926 /* Subfunction of delete_address_reloads: process registers found in X. */
7928 delete_address_reloads_1 (dead_insn, x, current_insn)
7929 rtx dead_insn, x, current_insn;
7931 rtx prev, set, dst, i2;
7933 enum rtx_code code = GET_CODE (x);
7937 char *fmt= GET_RTX_FORMAT (code);
7938 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7941 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7942 else if (fmt[i] == 'E')
7944 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7945 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7952 if (spill_reg_order[REGNO (x)] < 0)
7955 /* Scan backwards for the insn that sets x. This might be a way back due
7957 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7959 code = GET_CODE (prev);
7960 if (code == CODE_LABEL || code == JUMP_INSN)
7962 if (GET_RTX_CLASS (code) != 'i')
7964 if (reg_set_p (x, PATTERN (prev)))
7966 if (reg_referenced_p (x, PATTERN (prev)))
7969 if (! prev || INSN_UID (prev) < reload_first_uid)
7971 /* Check that PREV only sets the reload register. */
7972 set = single_set (prev);
7975 dst = SET_DEST (set);
7976 if (GET_CODE (dst) != REG
7977 || ! rtx_equal_p (dst, x))
7979 if (! reg_set_p (dst, PATTERN (dead_insn)))
7981 /* Check if DST was used in a later insn -
7982 it might have been inherited. */
7983 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7985 if (GET_CODE (i2) == CODE_LABEL)
7987 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7989 if (reg_referenced_p (dst, PATTERN (i2)))
7991 /* If there is a reference to the register in the current insn,
7992 it might be loaded in a non-inherited reload. If no other
7993 reload uses it, that means the register is set before
7995 if (i2 == current_insn)
7997 for (j = n_reloads - 1; j >= 0; j--)
7998 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
7999 || reload_override_in[j] == dst)
8001 for (j = n_reloads - 1; j >= 0; j--)
8002 if (reload_in[j] && reload_reg_rtx[j] == dst)
8009 if (GET_CODE (i2) == JUMP_INSN)
8011 if (reg_set_p (dst, PATTERN (i2)))
8013 /* If DST is still live at CURRENT_INSN, check if it is used for
8015 if (i2 == current_insn)
8017 for (j = n_reloads - 1; j >= 0; j--)
8018 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8019 || reload_override_in[j] == dst)
8021 /* ??? We can't finish the loop here, because dst might be
8022 allocated to a pseudo in this block if no reload in this
8023 block needs any of the clsses containing DST - see
8024 spill_hard_reg. There is no easy way to tell this, so we
8025 have to scan till the end of the basic block. */
8029 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8030 reg_reloaded_contents[REGNO (dst)] = -1;
8031 /* Can't use delete_insn here because PREV might be a basic block head. */
8032 PUT_CODE (prev, NOTE);
8033 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8034 NOTE_SOURCE_FILE (prev) = 0;
8037 /* Output reload-insns to reload VALUE into RELOADREG.
8038 VALUE is an autoincrement or autodecrement RTX whose operand
8039 is a register or memory location;
8040 so reloading involves incrementing that location.
8041 IN is either identical to VALUE, or some cheaper place to reload from.
8043 INC_AMOUNT is the number to increment or decrement by (always positive).
8044 This cannot be deduced from VALUE.
8046 Return the instruction that stores into RELOADREG. */
8049 inc_for_reload (reloadreg, in, value, inc_amount)
8054 /* REG or MEM to be copied and incremented. */
8055 rtx incloc = XEXP (value, 0);
8056 /* Nonzero if increment after copying. */
8057 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8063 rtx real_in = in == value ? XEXP (in, 0) : in;
8065 /* No hard register is equivalent to this register after
8066 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8067 we could inc/dec that register as well (maybe even using it for
8068 the source), but I'm not sure it's worth worrying about. */
8069 if (GET_CODE (incloc) == REG)
8070 reg_last_reload_reg[REGNO (incloc)] = 0;
8072 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8073 inc_amount = - inc_amount;
8075 inc = GEN_INT (inc_amount);
8077 /* If this is post-increment, first copy the location to the reload reg. */
8078 if (post && real_in != reloadreg)
8079 emit_insn (gen_move_insn (reloadreg, real_in));
8083 /* See if we can directly increment INCLOC. Use a method similar to
8084 that in gen_reload. */
8086 last = get_last_insn ();
8087 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8088 gen_rtx_PLUS (GET_MODE (incloc),
8091 code = recog_memoized (add_insn);
8094 extract_insn (add_insn);
8095 if (constrain_operands (1))
8097 /* If this is a pre-increment and we have incremented the value
8098 where it lives, copy the incremented value to RELOADREG to
8099 be used as an address. */
8102 emit_insn (gen_move_insn (reloadreg, incloc));
8107 delete_insns_since (last);
8110 /* If couldn't do the increment directly, must increment in RELOADREG.
8111 The way we do this depends on whether this is pre- or post-increment.
8112 For pre-increment, copy INCLOC to the reload register, increment it
8113 there, then save back. */
8117 if (in != reloadreg)
8118 emit_insn (gen_move_insn (reloadreg, real_in));
8119 emit_insn (gen_add2_insn (reloadreg, inc));
8120 store = emit_insn (gen_move_insn (incloc, reloadreg));
8125 Because this might be a jump insn or a compare, and because RELOADREG
8126 may not be available after the insn in an input reload, we must do
8127 the incrementation before the insn being reloaded for.
8129 We have already copied IN to RELOADREG. Increment the copy in
8130 RELOADREG, save that back, then decrement RELOADREG so it has
8131 the original value. */
8133 emit_insn (gen_add2_insn (reloadreg, inc));
8134 store = emit_insn (gen_move_insn (incloc, reloadreg));
8135 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8141 /* Return 1 if we are certain that the constraint-string STRING allows
8142 the hard register REG. Return 0 if we can't be sure of this. */
8145 constraint_accepts_reg_p (string, reg)
8150 int regno = true_regnum (reg);
8153 /* Initialize for first alternative. */
8155 /* Check that each alternative contains `g' or `r'. */
8157 switch (c = *string++)
8160 /* If an alternative lacks `g' or `r', we lose. */
8163 /* If an alternative lacks `g' or `r', we lose. */
8166 /* Initialize for next alternative. */
8171 /* Any general reg wins for this alternative. */
8172 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8176 /* Any reg in specified class wins for this alternative. */
8178 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8180 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8186 /* Return the number of places FIND appears within X, but don't count
8187 an occurrence if some SET_DEST is FIND. */
8190 count_occurrences (x, find)
8191 register rtx x, find;
8194 register enum rtx_code code;
8195 register char *format_ptr;
8203 code = GET_CODE (x);
8218 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8222 if (SET_DEST (x) == find)
8223 return count_occurrences (SET_SRC (x), find);
8230 format_ptr = GET_RTX_FORMAT (code);
8233 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8235 switch (*format_ptr++)
8238 count += count_occurrences (XEXP (x, i), find);
8242 if (XVEC (x, i) != NULL)
8244 for (j = 0; j < XVECLEN (x, i); j++)
8245 count += count_occurrences (XVECEXP (x, i, j), find);
8253 /* This array holds values which are equivalent to a hard register
8254 during reload_cse_regs. Each array element is an EXPR_LIST of
8255 values. Each time a hard register is set, we set the corresponding
8256 array element to the value. Each time a hard register is copied
8257 into memory, we add the memory location to the corresponding array
8258 element. We don't store values or memory addresses with side
8259 effects in this array.
8261 If the value is a CONST_INT, then the mode of the containing
8262 EXPR_LIST is the mode in which that CONST_INT was referenced.
8264 We sometimes clobber a specific entry in a list. In that case, we
8265 just set XEXP (list-entry, 0) to 0. */
8267 static rtx *reg_values;
8269 /* This is a preallocated REG rtx which we use as a temporary in
8270 reload_cse_invalidate_regno, so that we don't need to allocate a
8271 new one each time through a loop in that function. */
8273 static rtx invalidate_regno_rtx;
8275 /* Invalidate any entries in reg_values which depend on REGNO,
8276 including those for REGNO itself. This is called if REGNO is
8277 changing. If CLOBBER is true, then always forget anything we
8278 currently know about REGNO. MODE is the mode of the assignment to
8279 REGNO, which is used to determine how many hard registers are being
8280 changed. If MODE is VOIDmode, then only REGNO is being changed;
8281 this is used when invalidating call clobbered registers across a
8285 reload_cse_invalidate_regno (regno, mode, clobber)
8287 enum machine_mode mode;
8293 /* Our callers don't always go through true_regnum; we may see a
8294 pseudo-register here from a CLOBBER or the like. We probably
8295 won't ever see a pseudo-register that has a real register number,
8296 for we check anyhow for safety. */
8297 if (regno >= FIRST_PSEUDO_REGISTER)
8298 regno = reg_renumber[regno];
8302 if (mode == VOIDmode)
8303 endregno = regno + 1;
8305 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8308 for (i = regno; i < endregno; i++)
8311 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8315 for (x = reg_values[i]; x; x = XEXP (x, 1))
8317 if (XEXP (x, 0) != 0
8318 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8320 /* If this is the only entry on the list, clear
8321 reg_values[i]. Otherwise, just clear this entry on
8323 if (XEXP (x, 1) == 0 && x == reg_values[i])
8333 /* We must look at earlier registers, in case REGNO is part of a
8334 multi word value but is not the first register. If an earlier
8335 register has a value in a mode which overlaps REGNO, then we must
8336 invalidate that earlier register. Note that we do not need to
8337 check REGNO or later registers (we must not check REGNO itself,
8338 because we would incorrectly conclude that there was a conflict). */
8340 for (i = 0; i < regno; i++)
8344 for (x = reg_values[i]; x; x = XEXP (x, 1))
8346 if (XEXP (x, 0) != 0)
8348 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8349 REGNO (invalidate_regno_rtx) = i;
8350 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8353 reload_cse_invalidate_regno (i, VOIDmode, 1);
8361 /* The memory at address MEM_BASE is being changed.
8362 Return whether this change will invalidate VAL. */
8365 reload_cse_mem_conflict_p (mem_base, val)
8373 code = GET_CODE (val);
8376 /* Get rid of a few simple cases quickly. */
8389 if (GET_MODE (mem_base) == BLKmode
8390 || GET_MODE (val) == BLKmode)
8392 if (anti_dependence (val, mem_base))
8394 /* The address may contain nested MEMs. */
8401 fmt = GET_RTX_FORMAT (code);
8403 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8407 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8410 else if (fmt[i] == 'E')
8414 for (j = 0; j < XVECLEN (val, i); j++)
8415 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8423 /* Invalidate any entries in reg_values which are changed because of a
8424 store to MEM_RTX. If this is called because of a non-const call
8425 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8428 reload_cse_invalidate_mem (mem_rtx)
8433 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8437 for (x = reg_values[i]; x; x = XEXP (x, 1))
8439 if (XEXP (x, 0) != 0
8440 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8442 /* If this is the only entry on the list, clear
8443 reg_values[i]. Otherwise, just clear this entry on
8445 if (XEXP (x, 1) == 0 && x == reg_values[i])
8456 /* Invalidate DEST, which is being assigned to or clobbered. The
8457 second parameter exists so that this function can be passed to
8458 note_stores; it is ignored. */
8461 reload_cse_invalidate_rtx (dest, ignore)
8463 rtx ignore ATTRIBUTE_UNUSED;
8465 while (GET_CODE (dest) == STRICT_LOW_PART
8466 || GET_CODE (dest) == SIGN_EXTRACT
8467 || GET_CODE (dest) == ZERO_EXTRACT
8468 || GET_CODE (dest) == SUBREG)
8469 dest = XEXP (dest, 0);
8471 if (GET_CODE (dest) == REG)
8472 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8473 else if (GET_CODE (dest) == MEM)
8474 reload_cse_invalidate_mem (dest);
8477 /* Do a very simple CSE pass over the hard registers.
8479 This function detects no-op moves where we happened to assign two
8480 different pseudo-registers to the same hard register, and then
8481 copied one to the other. Reload will generate a useless
8482 instruction copying a register to itself.
8484 This function also detects cases where we load a value from memory
8485 into two different registers, and (if memory is more expensive than
8486 registers) changes it to simply copy the first register into the
8489 Another optimization is performed that scans the operands of each
8490 instruction to see whether the value is already available in a
8491 hard register. It then replaces the operand with the hard register
8492 if possible, much like an optional reload would. */
8495 reload_cse_regs_1 (first)
8503 init_alias_analysis ();
8505 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8506 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8508 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8509 free them when we are done. */
8510 push_obstacks (&reload_obstack, &reload_obstack);
8511 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8513 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8514 memory for a non-const call instruction. */
8515 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8517 /* This is used in reload_cse_invalidate_regno to avoid consing a
8518 new REG in a loop in that function. */
8519 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8521 for (insn = first; insn; insn = NEXT_INSN (insn))
8525 if (GET_CODE (insn) == CODE_LABEL)
8527 /* Forget all the register values at a code label. We don't
8528 try to do anything clever around jumps. */
8529 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8535 #ifdef NON_SAVING_SETJMP
8536 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8537 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8539 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8546 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8549 /* If this is a call instruction, forget anything stored in a
8550 call clobbered register, or, if this is not a const call, in
8552 if (GET_CODE (insn) == CALL_INSN)
8554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8555 if (call_used_regs[i])
8556 reload_cse_invalidate_regno (i, VOIDmode, 1);
8558 if (! CONST_CALL_P (insn))
8559 reload_cse_invalidate_mem (callmem);
8562 body = PATTERN (insn);
8563 if (GET_CODE (body) == SET)
8566 if (reload_cse_noop_set_p (body, insn))
8568 /* If this sets the return value of the function, we must keep
8569 a USE around, in case this is in a different basic block
8570 than the final USE. Otherwise, we could loose important
8571 register lifeness information on SMALL_REGISTER_CLASSES
8572 machines, where return registers might be used as spills:
8573 subsequent passes assume that spill registers are dead at
8574 the end of a basic block. */
8575 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8578 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8579 INSN_CODE (insn) = -1;
8580 REG_NOTES (insn) = NULL_RTX;
8581 push_obstacks (&reload_obstack, &reload_obstack);
8585 PUT_CODE (insn, NOTE);
8586 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8587 NOTE_SOURCE_FILE (insn) = 0;
8590 /* We're done with this insn. */
8594 /* It's not a no-op, but we can try to simplify it. */
8595 count += reload_cse_simplify_set (body, insn);
8598 apply_change_group ();
8600 reload_cse_simplify_operands (insn);
8602 reload_cse_record_set (body, body);
8604 else if (GET_CODE (body) == PARALLEL)
8607 rtx value = NULL_RTX;
8609 /* If every action in a PARALLEL is a noop, we can delete
8610 the entire PARALLEL. */
8611 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8613 rtx part = XVECEXP (body, 0, i);
8614 if (GET_CODE (part) == SET)
8616 if (! reload_cse_noop_set_p (part, insn))
8618 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8622 value = SET_DEST (part);
8625 else if (GET_CODE (part) != CLOBBER)
8633 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8634 INSN_CODE (insn) = -1;
8635 REG_NOTES (insn) = NULL_RTX;
8636 push_obstacks (&reload_obstack, &reload_obstack);
8640 PUT_CODE (insn, NOTE);
8641 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8642 NOTE_SOURCE_FILE (insn) = 0;
8645 /* We're done with this insn. */
8649 /* It's not a no-op, but we can try to simplify it. */
8650 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8651 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8652 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8655 apply_change_group ();
8657 reload_cse_simplify_operands (insn);
8659 /* Look through the PARALLEL and record the values being
8660 set, if possible. Also handle any CLOBBERs. */
8661 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8663 rtx x = XVECEXP (body, 0, i);
8665 if (GET_CODE (x) == SET)
8666 reload_cse_record_set (x, body);
8668 note_stores (x, reload_cse_invalidate_rtx);
8672 note_stores (body, reload_cse_invalidate_rtx);
8675 /* Clobber any registers which appear in REG_INC notes. We
8676 could keep track of the changes to their values, but it is
8677 unlikely to help. */
8681 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8682 if (REG_NOTE_KIND (x) == REG_INC)
8683 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8687 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8688 after we have processed the insn. */
8689 if (GET_CODE (insn) == CALL_INSN)
8693 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8694 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8695 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8699 /* Free all the temporary structures we created, and go back to the
8700 regular obstacks. */
8701 obstack_free (&reload_obstack, firstobj);
8705 /* Call cse / combine like post-reload optimization phases.
8706 FIRST is the first instruction. */
8708 reload_cse_regs (first)
8711 reload_cse_regs_1 (first);
8713 reload_cse_move2add (first);
8714 if (flag_expensive_optimizations)
8715 reload_cse_regs_1 (first);
8718 /* Return whether the values known for REGNO are equal to VAL. MODE
8719 is the mode of the object that VAL is being copied to; this matters
8720 if VAL is a CONST_INT. */
8723 reload_cse_regno_equal_p (regno, val, mode)
8726 enum machine_mode mode;
8733 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8734 if (XEXP (x, 0) != 0
8735 && rtx_equal_p (XEXP (x, 0), val)
8736 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8737 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8738 && (GET_CODE (val) != CONST_INT
8739 || mode == GET_MODE (x)
8740 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8741 /* On a big endian machine if the value spans more than
8742 one register then this register holds the high part of
8743 it and we can't use it.
8745 ??? We should also compare with the high part of the
8747 && !(WORDS_BIG_ENDIAN
8748 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8749 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8750 GET_MODE_BITSIZE (GET_MODE (x))))))
8756 /* See whether a single set is a noop. SET is the set instruction we
8757 are should check, and INSN is the instruction from which it came. */
8760 reload_cse_noop_set_p (set, insn)
8765 enum machine_mode dest_mode;
8769 src = SET_SRC (set);
8770 dest = SET_DEST (set);
8771 dest_mode = GET_MODE (dest);
8773 if (side_effects_p (src))
8776 dreg = true_regnum (dest);
8777 sreg = true_regnum (src);
8779 /* Check for setting a register to itself. In this case, we don't
8780 have to worry about REG_DEAD notes. */
8781 if (dreg >= 0 && dreg == sreg)
8787 /* Check for setting a register to itself. */
8791 /* Check for setting a register to a value which we already know
8792 is in the register. */
8793 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8796 /* Check for setting a register DREG to another register SREG
8797 where SREG is equal to a value which is already in DREG. */
8802 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8806 if (XEXP (x, 0) == 0)
8809 if (dest_mode == GET_MODE (x))
8811 else if (GET_MODE_BITSIZE (dest_mode)
8812 < GET_MODE_BITSIZE (GET_MODE (x)))
8813 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8818 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8826 else if (GET_CODE (dest) == MEM)
8828 /* Check for storing a register to memory when we know that the
8829 register is equivalent to the memory location. */
8831 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8832 && ! side_effects_p (dest))
8839 /* Try to simplify a single SET instruction. SET is the set pattern.
8840 INSN is the instruction it came from.
8841 This function only handles one case: if we set a register to a value
8842 which is not a register, we try to find that value in some other register
8843 and change the set into a register copy. */
8846 reload_cse_simplify_set (set, insn)
8852 enum machine_mode dest_mode;
8853 enum reg_class dclass;
8856 dreg = true_regnum (SET_DEST (set));
8860 src = SET_SRC (set);
8861 if (side_effects_p (src) || true_regnum (src) >= 0)
8864 dclass = REGNO_REG_CLASS (dreg);
8866 /* If memory loads are cheaper than register copies, don't change them. */
8867 if (GET_CODE (src) == MEM
8868 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8871 /* If the constant is cheaper than a register, don't change it. */
8872 if (CONSTANT_P (src)
8873 && rtx_cost (src, SET) < 2)
8876 dest_mode = GET_MODE (SET_DEST (set));
8877 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8880 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8881 && reload_cse_regno_equal_p (i, src, dest_mode))
8885 /* Pop back to the real obstacks while changing the insn. */
8888 validated = validate_change (insn, &SET_SRC (set),
8889 gen_rtx_REG (dest_mode, i), 1);
8891 /* Go back to the obstack we are using for temporary
8893 push_obstacks (&reload_obstack, &reload_obstack);
8902 /* Try to replace operands in INSN with equivalent values that are already
8903 in registers. This can be viewed as optional reloading.
8905 For each non-register operand in the insn, see if any hard regs are
8906 known to be equivalent to that operand. Record the alternatives which
8907 can accept these hard registers. Among all alternatives, select the
8908 ones which are better or equal to the one currently matching, where
8909 "better" is in terms of '?' and '!' constraints. Among the remaining
8910 alternatives, select the one which replaces most operands with
8914 reload_cse_simplify_operands (insn)
8917 #ifdef REGISTER_CONSTRAINTS
8920 char *constraints[MAX_RECOG_OPERANDS];
8922 /* Vector recording how bad an alternative is. */
8923 int *alternative_reject;
8924 /* Vector recording how many registers can be introduced by choosing
8925 this alternative. */
8926 int *alternative_nregs;
8927 /* Array of vectors recording, for each operand and each alternative,
8928 which hard register to substitute, or -1 if the operand should be
8930 int *op_alt_regno[MAX_RECOG_OPERANDS];
8931 /* Array of alternatives, sorted in order of decreasing desirability. */
8932 int *alternative_order;
8933 rtx reg = gen_rtx_REG (VOIDmode, -1);
8935 extract_insn (insn);
8937 if (recog_n_alternatives == 0 || recog_n_operands == 0)
8940 /* Figure out which alternative currently matches. */
8941 if (! constrain_operands (1))
8942 fatal_insn_not_found (insn);
8944 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
8945 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
8946 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
8947 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
8948 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
8950 for (i = 0; i < recog_n_operands; i++)
8952 enum machine_mode mode;
8956 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
8957 for (j = 0; j < recog_n_alternatives; j++)
8958 op_alt_regno[i][j] = -1;
8960 p = constraints[i] = recog_constraints[i];
8961 mode = recog_operand_mode[i];
8963 /* Add the reject values for each alternative given by the constraints
8964 for this operand. */
8972 alternative_reject[j] += 3;
8974 alternative_reject[j] += 300;
8977 /* We won't change operands which are already registers. We
8978 also don't want to modify output operands. */
8979 regno = true_regnum (recog_operand[i]);
8981 || constraints[i][0] == '='
8982 || constraints[i][0] == '+')
8985 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8987 int class = (int) NO_REGS;
8989 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
8992 REGNO (reg) = regno;
8993 PUT_MODE (reg, mode);
8995 /* We found a register equal to this operand. Now look for all
8996 alternatives that can accept this register and have not been
8997 assigned a register they can use yet. */
9006 case '=': case '+': case '?':
9007 case '#': case '&': case '!':
9009 case '0': case '1': case '2': case '3': case '4':
9010 case 'm': case '<': case '>': case 'V': case 'o':
9011 case 'E': case 'F': case 'G': case 'H':
9012 case 's': case 'i': case 'n':
9013 case 'I': case 'J': case 'K': case 'L':
9014 case 'M': case 'N': case 'O': case 'P':
9015 #ifdef EXTRA_CONSTRAINT
9016 case 'Q': case 'R': case 'S': case 'T': case 'U':
9019 /* These don't say anything we care about. */
9023 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9028 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9031 case ',': case '\0':
9032 /* See if REGNO fits this alternative, and set it up as the
9033 replacement register if we don't have one for this
9034 alternative yet and the operand being replaced is not
9035 a cheap CONST_INT. */
9036 if (op_alt_regno[i][j] == -1
9037 && reg_fits_class_p (reg, class, 0, mode)
9038 && (GET_CODE (recog_operand[i]) != CONST_INT
9039 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9041 alternative_nregs[j]++;
9042 op_alt_regno[i][j] = regno;
9054 /* Record all alternatives which are better or equal to the currently
9055 matching one in the alternative_order array. */
9056 for (i = j = 0; i < recog_n_alternatives; i++)
9057 if (alternative_reject[i] <= alternative_reject[which_alternative])
9058 alternative_order[j++] = i;
9059 recog_n_alternatives = j;
9061 /* Sort it. Given a small number of alternatives, a dumb algorithm
9062 won't hurt too much. */
9063 for (i = 0; i < recog_n_alternatives - 1; i++)
9066 int best_reject = alternative_reject[alternative_order[i]];
9067 int best_nregs = alternative_nregs[alternative_order[i]];
9070 for (j = i + 1; j < recog_n_alternatives; j++)
9072 int this_reject = alternative_reject[alternative_order[j]];
9073 int this_nregs = alternative_nregs[alternative_order[j]];
9075 if (this_reject < best_reject
9076 || (this_reject == best_reject && this_nregs < best_nregs))
9079 best_reject = this_reject;
9080 best_nregs = this_nregs;
9084 tmp = alternative_order[best];
9085 alternative_order[best] = alternative_order[i];
9086 alternative_order[i] = tmp;
9089 /* Substitute the operands as determined by op_alt_regno for the best
9091 j = alternative_order[0];
9093 /* Pop back to the real obstacks while changing the insn. */
9096 for (i = 0; i < recog_n_operands; i++)
9098 enum machine_mode mode = recog_operand_mode[i];
9099 if (op_alt_regno[i][j] == -1)
9102 validate_change (insn, recog_operand_loc[i],
9103 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9106 for (i = recog_n_dups - 1; i >= 0; i--)
9108 int op = recog_dup_num[i];
9109 enum machine_mode mode = recog_operand_mode[op];
9111 if (op_alt_regno[op][j] == -1)
9114 validate_change (insn, recog_dup_loc[i],
9115 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9118 /* Go back to the obstack we are using for temporary
9120 push_obstacks (&reload_obstack, &reload_obstack);
9122 return apply_change_group ();
9128 /* These two variables are used to pass information from
9129 reload_cse_record_set to reload_cse_check_clobber. */
9131 static int reload_cse_check_clobbered;
9132 static rtx reload_cse_check_src;
9134 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9135 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9136 second argument, which is passed by note_stores, is ignored. */
9139 reload_cse_check_clobber (dest, ignore)
9141 rtx ignore ATTRIBUTE_UNUSED;
9143 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9144 reload_cse_check_clobbered = 1;
9147 /* Record the result of a SET instruction. SET is the set pattern.
9148 BODY is the pattern of the insn that it came from. */
9151 reload_cse_record_set (set, body)
9157 enum machine_mode dest_mode;
9159 dest = SET_DEST (set);
9160 src = SET_SRC (set);
9161 dreg = true_regnum (dest);
9162 sreg = true_regnum (src);
9163 dest_mode = GET_MODE (dest);
9165 /* Some machines don't define AUTO_INC_DEC, but they still use push
9166 instructions. We need to catch that case here in order to
9167 invalidate the stack pointer correctly. Note that invalidating
9168 the stack pointer is different from invalidating DEST. */
9170 while (GET_CODE (x) == SUBREG
9171 || GET_CODE (x) == ZERO_EXTRACT
9172 || GET_CODE (x) == SIGN_EXTRACT
9173 || GET_CODE (x) == STRICT_LOW_PART)
9175 if (push_operand (x, GET_MODE (x)))
9177 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9178 reload_cse_invalidate_rtx (dest, NULL_RTX);
9182 /* We can only handle an assignment to a register, or a store of a
9183 register to a memory location. For other cases, we just clobber
9184 the destination. We also have to just clobber if there are side
9185 effects in SRC or DEST. */
9186 if ((dreg < 0 && GET_CODE (dest) != MEM)
9187 || side_effects_p (src)
9188 || side_effects_p (dest))
9190 reload_cse_invalidate_rtx (dest, NULL_RTX);
9195 /* We don't try to handle values involving CC, because it's a pain
9196 to keep track of when they have to be invalidated. */
9197 if (reg_mentioned_p (cc0_rtx, src)
9198 || reg_mentioned_p (cc0_rtx, dest))
9200 reload_cse_invalidate_rtx (dest, NULL_RTX);
9205 /* If BODY is a PARALLEL, then we need to see whether the source of
9206 SET is clobbered by some other instruction in the PARALLEL. */
9207 if (GET_CODE (body) == PARALLEL)
9211 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9215 x = XVECEXP (body, 0, i);
9219 reload_cse_check_clobbered = 0;
9220 reload_cse_check_src = src;
9221 note_stores (x, reload_cse_check_clobber);
9222 if (reload_cse_check_clobbered)
9224 reload_cse_invalidate_rtx (dest, NULL_RTX);
9234 /* This is an assignment to a register. Update the value we
9235 have stored for the register. */
9240 /* This is a copy from one register to another. Any values
9241 which were valid for SREG are now valid for DREG. If the
9242 mode changes, we use gen_lowpart_common to extract only
9243 the part of the value that is copied. */
9244 reg_values[dreg] = 0;
9245 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9249 if (XEXP (x, 0) == 0)
9251 if (dest_mode == GET_MODE (XEXP (x, 0)))
9253 else if (GET_MODE_BITSIZE (dest_mode)
9254 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9257 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9259 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9264 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9266 /* We've changed DREG, so invalidate any values held by other
9267 registers that depend upon it. */
9268 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9270 /* If this assignment changes more than one hard register,
9271 forget anything we know about the others. */
9272 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9273 reg_values[dreg + i] = 0;
9275 else if (GET_CODE (dest) == MEM)
9277 /* Invalidate conflicting memory locations. */
9278 reload_cse_invalidate_mem (dest);
9280 /* If we're storing a register to memory, add DEST to the list
9282 if (sreg >= 0 && ! side_effects_p (dest))
9283 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9288 /* We should have bailed out earlier. */
9293 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9295 This code might also be useful when reload gave up on reg+reg addresssing
9296 because of clashes between the return register and INDEX_REG_CLASS. */
9298 /* The maximum number of uses of a register we can keep track of to
9299 replace them with reg+reg addressing. */
9300 #define RELOAD_COMBINE_MAX_USES 6
9302 /* INSN is the insn where a register has ben used, and USEP points to the
9303 location of the register within the rtl. */
9304 struct reg_use { rtx insn, *usep; };
9306 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9307 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9308 indicates where it becomes live again.
9309 Otherwise, USE_INDEX is the index of the last encountered use of the
9310 register (which is first among these we have seen since we scan backwards),
9311 OFFSET contains the constant offset that is added to the register in
9312 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9313 last, of these uses. */
9316 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9321 } reg_state[FIRST_PSEUDO_REGISTER];
9323 /* Reverse linear uid. This is increased in reload_combine while scanning
9324 the instructions from last to first. It is used to set last_label_ruid
9325 and the store_ruid / use_ruid fields in reg_state. */
9326 static int reload_combine_ruid;
9332 int first_index_reg = 1, last_index_reg = 0;
9334 int last_label_ruid;
9336 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9337 reload has already used it where appropriate, so there is no use in
9338 trying to generate it now. */
9339 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9342 /* To avoid wasting too much time later searching for an index register,
9343 determine the minimum and maximum index register numbers. */
9344 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9346 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9348 if (! last_index_reg)
9350 first_index_reg = i;
9353 /* If no index register is available, we can quit now. */
9354 if (first_index_reg > last_index_reg)
9357 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9358 last_label_ruid = reload_combine_ruid = 0;
9359 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9362 reg_state[i].use_index = -1;
9365 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9366 reg_state[i].store_ruid = reload_combine_ruid;
9370 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9374 /* We cannot do our optimization across labels. Invalidating all the use
9375 information we have would be costly, so we just note where the label
9376 is and then later disable any optimization that would cross it. */
9377 if (GET_CODE (insn) == CODE_LABEL)
9378 last_label_ruid = reload_combine_ruid;
9379 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9381 reload_combine_ruid++;
9383 /* Look for (set (REGX) (CONST_INT))
9384 (set (REGX) (PLUS (REGX) (REGY)))
9386 ... (MEM (REGX)) ...
9388 (set (REGZ) (CONST_INT))
9390 ... (MEM (PLUS (REGZ) (REGY)))... .
9392 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9393 and that we know all uses of REGX before it dies. */
9394 set = single_set (insn);
9396 && GET_CODE (SET_DEST (set)) == REG
9397 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9398 GET_MODE (SET_DEST (set)))
9400 && GET_CODE (SET_SRC (set)) == PLUS
9401 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9402 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9403 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9405 rtx reg = SET_DEST (set);
9406 rtx plus = SET_SRC (set);
9407 rtx base = XEXP (plus, 1);
9408 rtx prev = prev_nonnote_insn (insn);
9409 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9410 int regno = REGNO (reg);
9412 rtx reg_sum = NULL_RTX;
9414 /* Now, we need an index register.
9415 We'll set index_reg to this index register, const_reg to the
9416 register that is to be loaded with the constant
9417 (denoted as REGZ in the substitution illustration above),
9418 and reg_sum to the register-register that we want to use to
9419 substitute uses of REG (typically in MEMs) with.
9420 First check REG and BASE for being index registers;
9421 we can use them even if they are not dead. */
9422 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9423 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9431 /* Otherwise, look for a free index register. Since we have
9432 checked above that neiter REG nor BASE are index registers,
9433 if we find anything at all, it will be different from these
9435 for (i = first_index_reg; i <= last_index_reg; i++)
9437 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9438 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9439 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9440 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9442 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9443 const_reg = index_reg;
9444 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9450 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9451 && rtx_equal_p (SET_DEST (prev_set), reg)
9452 && reg_state[regno].use_index >= 0
9457 /* Change destination register and - if necessary - the
9458 constant value in PREV, the constant loading instruction. */
9459 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9460 if (reg_state[regno].offset != const0_rtx)
9461 validate_change (prev,
9462 &SET_SRC (prev_set),
9463 GEN_INT (INTVAL (SET_SRC (prev_set))
9464 + INTVAL (reg_state[regno].offset)),
9466 /* Now for every use of REG that we have recorded, replace REG
9468 for (i = reg_state[regno].use_index;
9469 i < RELOAD_COMBINE_MAX_USES; i++)
9470 validate_change (reg_state[regno].reg_use[i].insn,
9471 reg_state[regno].reg_use[i].usep,
9474 if (apply_change_group ())
9478 /* Delete the reg-reg addition. */
9479 PUT_CODE (insn, NOTE);
9480 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9481 NOTE_SOURCE_FILE (insn) = 0;
9483 if (reg_state[regno].offset != const0_rtx)
9485 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9487 for (np = ®_NOTES (prev); *np; )
9489 if (REG_NOTE_KIND (*np) == REG_EQUAL
9490 || REG_NOTE_KIND (*np) == REG_EQUIV)
9491 *np = XEXP (*np, 1);
9493 np = &XEXP (*np, 1);
9496 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9497 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9502 note_stores (PATTERN (insn), reload_combine_note_store);
9503 if (GET_CODE (insn) == CALL_INSN)
9507 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9509 if (call_used_regs[i])
9511 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9512 reg_state[i].store_ruid = reload_combine_ruid;
9515 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9516 link = XEXP (link, 1))
9518 rtx use = XEXP (link, 0);
9519 int regno = REGNO (XEXP (use, 0));
9520 if (GET_CODE (use) == CLOBBER)
9522 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9523 reg_state[regno].store_ruid = reload_combine_ruid;
9526 reg_state[regno].use_index = -1;
9529 if (GET_CODE (insn) == JUMP_INSN)
9531 /* Non-spill registers might be used at the call destination in
9532 some unknown fashion, so we have to mark the unknown use. */
9533 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9536 reg_state[i].use_index = -1;
9539 reload_combine_note_use (&PATTERN (insn), insn);
9540 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9542 if (REG_NOTE_KIND (note) == REG_INC
9543 && GET_CODE (XEXP (note, 0)) == REG)
9544 reg_state[REGNO (XEXP (note, 0))].use_index = -1;
9549 /* Check if DST is a register or a subreg of a register; if it is,
9550 update reg_state[regno].store_ruid and reg_state[regno].use_index
9551 accordingly. Called via note_stores from reload_combine.
9552 The second argument, SET, is ignored. */
9554 reload_combine_note_store (dst, set)
9555 rtx dst, set ATTRIBUTE_UNUSED;
9559 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9561 if (GET_CODE (dst) == SUBREG)
9563 regno = SUBREG_WORD (dst);
9564 dst = SUBREG_REG (dst);
9566 if (GET_CODE (dst) != REG)
9568 regno += REGNO (dst);
9569 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9570 careful with registers / register parts that are not full words. */
9571 if (size < (unsigned) UNITS_PER_WORD)
9572 reg_state[regno].use_index = -1;
9575 for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
9577 reg_state[i].store_ruid = reload_combine_ruid;
9578 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9583 /* XP points to a piece of rtl that has to be checked for any uses of
9585 *XP is the pattern of INSN, or a part of it.
9586 Called from reload_combine, and recursively by itself. */
9588 reload_combine_note_use (xp, insn)
9592 enum rtx_code code = x->code;
9595 rtx offset = const0_rtx; /* For the REG case below. */
9600 if (GET_CODE (SET_DEST (x)) == REG)
9602 reload_combine_note_use (&SET_SRC (x), insn);
9608 if (GET_CODE (SET_DEST (x)) == REG)
9613 /* We are interested in (plus (reg) (const_int)) . */
9614 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9616 offset = XEXP (x, 1);
9621 int regno = REGNO (x);
9624 /* Some spurious USEs of pseudo registers might remain.
9625 Just ignore them. */
9626 if (regno >= FIRST_PSEUDO_REGISTER)
9629 /* If this register is already used in some unknown fashion, we
9631 If we decrement the index from zero to -1, we can't store more
9632 uses, so this register becomes used in an unknown fashion. */
9633 use_index = --reg_state[regno].use_index;
9637 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9639 /* We have found another use for a register that is already
9640 used later. Check if the offsets match; if not, mark the
9641 register as used in an unknown fashion. */
9642 if (! rtx_equal_p (offset, reg_state[regno].offset))
9644 reg_state[regno].use_index = -1;
9650 /* This is the first use of this register we have seen since we
9651 marked it as dead. */
9652 reg_state[regno].offset = offset;
9653 reg_state[regno].use_ruid = reload_combine_ruid;
9655 reg_state[regno].reg_use[use_index].insn = insn;
9656 reg_state[regno].reg_use[use_index].usep = xp;
9664 /* Recursively process the components of X. */
9665 fmt = GET_RTX_FORMAT (code);
9666 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9669 reload_combine_note_use (&XEXP (x, i), insn);
9670 else if (fmt[i] == 'E')
9672 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9673 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9678 /* See if we can reduce the cost of a constant by replacing a move with
9680 /* We cannot do our optimization across labels. Invalidating all the
9681 information about register contents we have would be costly, so we
9682 use last_label_luid (local variable of reload_cse_move2add) to note
9683 where the label is and then later disable any optimization that would
9685 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9686 reg_set_luid[n] is larger than last_label_luid[n] . */
9687 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9688 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9689 reg_mode[n] to be valid.
9690 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9691 has been set to reg_offset[n] in mode reg_mode[n] .
9692 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9693 register n has been set to the sum of reg_offset[n] and register
9694 reg_base_reg[n], calculated in mode reg_mode[n] . */
9695 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9696 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9697 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9698 /* move2add_luid is linearily increased while scanning the instructions
9699 from first to last. It is used to set reg_set_luid in
9700 reload_cse_move2add and move2add_note_store. */
9701 static int move2add_luid;
9704 reload_cse_move2add (first)
9709 int last_label_luid;
9711 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9712 reg_set_luid[i] = 0;
9714 last_label_luid = 0;
9716 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9720 if (GET_CODE (insn) == CODE_LABEL)
9721 last_label_luid = move2add_luid;
9722 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9724 pat = PATTERN (insn);
9725 /* For simplicity, we only perform this optimization on
9726 straightforward SETs. */
9727 if (GET_CODE (pat) == SET
9728 && GET_CODE (SET_DEST (pat)) == REG)
9730 rtx reg = SET_DEST (pat);
9731 int regno = REGNO (reg);
9732 rtx src = SET_SRC (pat);
9734 /* Check if we have valid information on the contents of this
9735 register in the mode of REG. */
9736 /* ??? We don't know how zero / sign extension is handled, hence
9737 we can't go from a narrower to a wider mode. */
9738 if (reg_set_luid[regno] > last_label_luid
9739 && (GET_MODE_SIZE (GET_MODE (reg))
9740 <= GET_MODE_SIZE (reg_mode[regno]))
9741 && GET_CODE (reg_offset[regno]) == CONST_INT)
9743 /* Try to transform (set (REGX) (CONST_INT A))
9745 (set (REGX) (CONST_INT B))
9747 (set (REGX) (CONST_INT A))
9749 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9751 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9754 rtx new_src = GEN_INT (INTVAL (src)
9755 - INTVAL (reg_offset[regno]));
9756 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9757 use (set (reg) (reg)) instead.
9758 We don't delete this insn, nor do we convert it into a
9759 note, to avoid losing register notes or the return
9760 value flag. jump2 already knowns how to get rid of
9762 if (new_src == const0_rtx)
9763 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9764 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9765 && have_add2_insn (GET_MODE (reg)))
9766 success = validate_change (insn, &PATTERN (insn),
9767 gen_add2_insn (reg, new_src), 0);
9768 reg_set_luid[regno] = move2add_luid;
9769 reg_mode[regno] = GET_MODE (reg);
9770 reg_offset[regno] = src;
9774 /* Try to transform (set (REGX) (REGY))
9775 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9778 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9781 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9783 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9784 else if (GET_CODE (src) == REG
9785 && reg_base_reg[regno] == REGNO (src)
9786 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9788 rtx next = next_nonnote_insn (insn);
9791 set = single_set (next);
9794 && SET_DEST (set) == reg
9795 && GET_CODE (SET_SRC (set)) == PLUS
9796 && XEXP (SET_SRC (set), 0) == reg
9797 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9799 rtx src3 = XEXP (SET_SRC (set), 1);
9800 rtx new_src = GEN_INT (INTVAL (src3)
9801 - INTVAL (reg_offset[regno]));
9804 if (new_src == const0_rtx)
9805 /* See above why we create (set (reg) (reg)) here. */
9807 = validate_change (next, &SET_SRC (set), reg, 0);
9808 else if ((rtx_cost (new_src, PLUS)
9809 < 2 + rtx_cost (src3, SET))
9810 && have_add2_insn (GET_MODE (reg)))
9812 = validate_change (next, &PATTERN (next),
9813 gen_add2_insn (reg, new_src), 0);
9816 /* INSN might be the first insn in a basic block
9817 if the preceding insn is a conditional jump
9818 or a possible-throwing call. */
9819 PUT_CODE (insn, NOTE);
9820 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9821 NOTE_SOURCE_FILE (insn) = 0;
9824 reg_set_luid[regno] = move2add_luid;
9825 reg_mode[regno] = GET_MODE (reg);
9826 reg_offset[regno] = src3;
9833 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9835 if (REG_NOTE_KIND (note) == REG_INC
9836 && GET_CODE (XEXP (note, 0)) == REG)
9838 /* Indicate that this register has been recently written to,
9839 but the exact contents are not available. */
9840 int regno = REGNO (XEXP (note, 0));
9841 if (regno < FIRST_PSEUDO_REGISTER)
9843 reg_set_luid[regno] = move2add_luid;
9844 reg_offset[regno] = note;
9848 note_stores (PATTERN (insn), move2add_note_store);
9849 /* If this is a CALL_INSN, all call used registers are stored with
9851 if (GET_CODE (insn) == CALL_INSN)
9853 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9855 if (call_used_regs[i])
9857 reg_set_luid[i] = move2add_luid;
9858 reg_offset[i] = insn; /* Invalidate contents. */
9865 /* SET is a SET or CLOBBER that sets DST.
9866 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9867 Called from reload_cse_move2add via note_stores. */
9869 move2add_note_store (dst, set)
9875 enum machine_mode mode = GET_MODE (dst);
9876 if (GET_CODE (dst) == SUBREG)
9878 regno = SUBREG_WORD (dst);
9879 dst = SUBREG_REG (dst);
9881 if (GET_CODE (dst) != REG)
9884 regno += REGNO (dst);
9886 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
9888 rtx src = SET_SRC (set);
9890 reg_mode[regno] = mode;
9891 switch (GET_CODE (src))
9895 rtx src0 = XEXP (src, 0);
9896 if (GET_CODE (src0) == REG)
9898 if (REGNO (src0) != regno
9899 || reg_offset[regno] != const0_rtx)
9901 reg_base_reg[regno] = REGNO (src0);
9902 reg_set_luid[regno] = move2add_luid;
9904 reg_offset[regno] = XEXP (src, 1);
9907 reg_set_luid[regno] = move2add_luid;
9908 reg_offset[regno] = set; /* Invalidate contents. */
9913 reg_base_reg[regno] = REGNO (SET_SRC (set));
9914 reg_offset[regno] = const0_rtx;
9915 reg_set_luid[regno] = move2add_luid;
9919 reg_base_reg[regno] = -1;
9920 reg_offset[regno] = SET_SRC (set);
9921 reg_set_luid[regno] = move2add_luid;
9927 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9929 /* Indicate that this register has been recently written to,
9930 but the exact contents are not available. */
9931 reg_set_luid[i] = move2add_luid;
9932 reg_offset[i] = dst;
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