1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static bool inherit_piecemeal_p (int, int);
438 static void emit_reload_insns (struct insn_chain *);
439 static void delete_output_reload (rtx, int, int);
440 static void delete_address_reloads (rtx, rtx);
441 static void delete_address_reloads_1 (rtx, rtx, rtx);
442 static rtx inc_for_reload (rtx, rtx, rtx, int);
444 static void add_auto_inc_notes (rtx, rtx);
446 static void copy_eh_notes (rtx, rtx);
447 static int reloads_conflict (int, int);
448 static rtx gen_reload (rtx, rtx, int, enum reload_type);
449 static rtx emit_insn_if_valid_for_reload (rtx);
451 /* Initialize the reload pass. This is called at the beginning of compilation
452 and may be called again if the target is reinitialized. */
459 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
460 Set spill_indirect_levels to the number of levels such addressing is
461 permitted, zero if it is not permitted at all. */
464 = gen_rtx_MEM (Pmode,
467 LAST_VIRTUAL_REGISTER + 1),
469 spill_indirect_levels = 0;
471 while (memory_address_p (QImode, tem))
473 spill_indirect_levels++;
474 tem = gen_rtx_MEM (Pmode, tem);
477 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
479 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
480 indirect_symref_ok = memory_address_p (QImode, tem);
482 /* See if reg+reg is a valid (and offsettable) address. */
484 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
486 tem = gen_rtx_PLUS (Pmode,
487 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
488 gen_rtx_REG (Pmode, i));
490 /* This way, we make sure that reg+reg is an offsettable address. */
491 tem = plus_constant (tem, 4);
493 if (memory_address_p (QImode, tem))
495 double_reg_address_ok = 1;
500 /* Initialize obstack for our rtl allocation. */
501 gcc_obstack_init (&reload_obstack);
502 reload_startobj = obstack_alloc (&reload_obstack, 0);
504 INIT_REG_SET (&spilled_pseudos);
505 INIT_REG_SET (&pseudos_counted);
508 /* List of insn chains that are currently unused. */
509 static struct insn_chain *unused_insn_chains = 0;
511 /* Allocate an empty insn_chain structure. */
513 new_insn_chain (void)
515 struct insn_chain *c;
517 if (unused_insn_chains == 0)
519 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
520 INIT_REG_SET (&c->live_throughout);
521 INIT_REG_SET (&c->dead_or_set);
525 c = unused_insn_chains;
526 unused_insn_chains = c->next;
528 c->is_caller_save_insn = 0;
529 c->need_operand_change = 0;
535 /* Small utility function to set all regs in hard reg set TO which are
536 allocated to pseudos in regset FROM. */
539 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
542 reg_set_iterator rsi;
544 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
546 int r = reg_renumber[regno];
550 /* reload_combine uses the information from
551 DF_RA_LIVE_IN (BASIC_BLOCK), which might still
552 contain registers that have not actually been allocated
553 since they have an equivalence. */
554 gcc_assert (reload_completed);
557 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
561 /* Replace all pseudos found in LOC with their corresponding
565 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
578 unsigned int regno = REGNO (x);
580 if (regno < FIRST_PSEUDO_REGISTER)
583 x = eliminate_regs (x, mem_mode, usage);
587 replace_pseudos_in (loc, mem_mode, usage);
591 if (reg_equiv_constant[regno])
592 *loc = reg_equiv_constant[regno];
593 else if (reg_equiv_mem[regno])
594 *loc = reg_equiv_mem[regno];
595 else if (reg_equiv_address[regno])
596 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
599 gcc_assert (!REG_P (regno_reg_rtx[regno])
600 || REGNO (regno_reg_rtx[regno]) != regno);
601 *loc = regno_reg_rtx[regno];
606 else if (code == MEM)
608 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
612 /* Process each of our operands recursively. */
613 fmt = GET_RTX_FORMAT (code);
614 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
616 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
617 else if (*fmt == 'E')
618 for (j = 0; j < XVECLEN (x, i); j++)
619 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
622 /* Determine if the current function has an exception receiver block
623 that reaches the exit block via non-exceptional edges */
626 has_nonexceptional_receiver (void)
630 basic_block *tos, *worklist, bb;
632 /* If we're not optimizing, then just err on the safe side. */
636 /* First determine which blocks can reach exit via normal paths. */
637 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
640 bb->flags &= ~BB_REACHABLE;
642 /* Place the exit block on our worklist. */
643 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
644 *tos++ = EXIT_BLOCK_PTR;
646 /* Iterate: find everything reachable from what we've already seen. */
647 while (tos != worklist)
651 FOR_EACH_EDGE (e, ei, bb->preds)
652 if (!(e->flags & EDGE_ABNORMAL))
654 basic_block src = e->src;
656 if (!(src->flags & BB_REACHABLE))
658 src->flags |= BB_REACHABLE;
665 /* Now see if there's a reachable block with an exceptional incoming
668 if (bb->flags & BB_REACHABLE)
669 FOR_EACH_EDGE (e, ei, bb->preds)
670 if (e->flags & EDGE_ABNORMAL)
673 /* No exceptional block reached exit unexceptionally. */
678 /* Global variables used by reload and its subroutines. */
680 /* Set during calculate_needs if an insn needs register elimination. */
681 static int something_needs_elimination;
682 /* Set during calculate_needs if an insn needs an operand changed. */
683 static int something_needs_operands_changed;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is nonzero if reload failed
699 and we must not do any more for this function. */
702 reload (rtx first, int global)
706 struct elim_table *ep;
709 /* Make sure even insns with volatile mem refs are recognizable. */
714 reload_firstobj = obstack_alloc (&reload_obstack, 0);
716 /* Make sure that the last insn in the chain
717 is not something that needs reloading. */
718 emit_note (NOTE_INSN_DELETED);
720 /* Enable find_equiv_reg to distinguish insns made by reload. */
721 reload_first_uid = get_max_uid ();
723 #ifdef SECONDARY_MEMORY_NEEDED
724 /* Initialize the secondary memory table. */
725 clear_secondary_mem ();
728 /* We don't have a stack slot for any spill reg yet. */
729 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
730 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
732 /* Initialize the save area information for caller-save, in case some
736 /* Compute which hard registers are now in use
737 as homes for pseudo registers.
738 This is done here rather than (eg) in global_alloc
739 because this point is reached even if not optimizing. */
740 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
743 /* A function that has a nonlocal label that can reach the exit
744 block via non-exceptional paths must save all call-saved
746 if (current_function_has_nonlocal_label
747 && has_nonexceptional_receiver ())
748 current_function_saves_all_registers = 1;
750 if (current_function_saves_all_registers)
751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
752 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
753 df_set_regs_ever_live (i, true);
755 /* Find all the pseudo registers that didn't get hard regs
756 but do have known equivalent constants or memory slots.
757 These include parameters (known equivalent to parameter slots)
758 and cse'd or loop-moved constant memory addresses.
760 Record constant equivalents in reg_equiv_constant
761 so they will be substituted by find_reloads.
762 Record memory equivalents in reg_mem_equiv so they can
763 be substituted eventually by altering the REG-rtx's. */
765 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
766 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
767 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
768 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
769 reg_equiv_address = XCNEWVEC (rtx, max_regno);
770 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
771 reg_old_renumber = XCNEWVEC (short, max_regno);
772 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
773 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
774 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
776 CLEAR_HARD_REG_SET (bad_spill_regs_global);
778 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
779 to. Also find all paradoxical subregs and find largest such for
782 num_eliminable_invariants = 0;
783 for (insn = first; insn; insn = NEXT_INSN (insn))
785 rtx set = single_set (insn);
787 /* We may introduce USEs that we want to remove at the end, so
788 we'll mark them with QImode. Make sure there are no
789 previously-marked insns left by say regmove. */
790 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
791 && GET_MODE (insn) != VOIDmode)
792 PUT_MODE (insn, VOIDmode);
795 scan_paradoxical_subregs (PATTERN (insn));
797 if (set != 0 && REG_P (SET_DEST (set)))
799 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
805 i = REGNO (SET_DEST (set));
808 if (i <= LAST_VIRTUAL_REGISTER)
811 if (! function_invariant_p (x)
813 /* A function invariant is often CONSTANT_P but may
814 include a register. We promise to only pass
815 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
817 && LEGITIMATE_PIC_OPERAND_P (x)))
819 /* It can happen that a REG_EQUIV note contains a MEM
820 that is not a legitimate memory operand. As later
821 stages of reload assume that all addresses found
822 in the reg_equiv_* arrays were originally legitimate,
823 we ignore such REG_EQUIV notes. */
824 if (memory_operand (x, VOIDmode))
826 /* Always unshare the equivalence, so we can
827 substitute into this insn without touching the
829 reg_equiv_memory_loc[i] = copy_rtx (x);
831 else if (function_invariant_p (x))
833 if (GET_CODE (x) == PLUS)
835 /* This is PLUS of frame pointer and a constant,
836 and might be shared. Unshare it. */
837 reg_equiv_invariant[i] = copy_rtx (x);
838 num_eliminable_invariants++;
840 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
842 reg_equiv_invariant[i] = x;
843 num_eliminable_invariants++;
845 else if (LEGITIMATE_CONSTANT_P (x))
846 reg_equiv_constant[i] = x;
849 reg_equiv_memory_loc[i]
850 = force_const_mem (GET_MODE (SET_DEST (set)), x);
851 if (! reg_equiv_memory_loc[i])
852 reg_equiv_init[i] = NULL_RTX;
857 reg_equiv_init[i] = NULL_RTX;
862 reg_equiv_init[i] = NULL_RTX;
867 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
868 if (reg_equiv_init[i])
870 fprintf (dump_file, "init_insns for %u: ", i);
871 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
872 fprintf (dump_file, "\n");
877 first_label_num = get_first_label_num ();
878 num_labels = max_label_num () - first_label_num;
880 /* Allocate the tables used to store offset information at labels. */
881 /* We used to use alloca here, but the size of what it would try to
882 allocate would occasionally cause it to exceed the stack limit and
883 cause a core dump. */
884 offsets_known_at = XNEWVEC (char, num_labels);
885 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
887 /* Alter each pseudo-reg rtx to contain its hard reg number.
888 Assign stack slots to the pseudos that lack hard regs or equivalents.
889 Do not touch virtual registers. */
891 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
894 /* If we have some registers we think can be eliminated, scan all insns to
895 see if there is an insn that sets one of these registers to something
896 other than itself plus a constant. If so, the register cannot be
897 eliminated. Doing this scan here eliminates an extra pass through the
898 main reload loop in the most common case where register elimination
900 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
902 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
904 maybe_fix_stack_asms ();
906 insns_need_reload = 0;
907 something_needs_elimination = 0;
909 /* Initialize to -1, which means take the first spill register. */
912 /* Spill any hard regs that we know we can't eliminate. */
913 CLEAR_HARD_REG_SET (used_spill_regs);
914 /* There can be multiple ways to eliminate a register;
915 they should be listed adjacently.
916 Elimination for any register fails only if all possible ways fail. */
917 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
920 int can_eliminate = 0;
923 can_eliminate |= ep->can_eliminate;
926 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
928 spill_hard_reg (from, 1);
931 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
932 if (frame_pointer_needed)
933 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
935 finish_spills (global);
937 /* From now on, we may need to generate moves differently. We may also
938 allow modifications of insns which cause them to not be recognized.
939 Any such modifications will be cleaned up during reload itself. */
940 reload_in_progress = 1;
942 /* This loop scans the entire function each go-round
943 and repeats until one repetition spills no additional hard regs. */
946 int something_changed;
948 HOST_WIDE_INT starting_frame_size;
950 starting_frame_size = get_frame_size ();
952 set_initial_elim_offsets ();
953 set_initial_label_offsets ();
955 /* For each pseudo register that has an equivalent location defined,
956 try to eliminate any eliminable registers (such as the frame pointer)
957 assuming initial offsets for the replacement register, which
960 If the resulting location is directly addressable, substitute
961 the MEM we just got directly for the old REG.
963 If it is not addressable but is a constant or the sum of a hard reg
964 and constant, it is probably not addressable because the constant is
965 out of range, in that case record the address; we will generate
966 hairy code to compute the address in a register each time it is
967 needed. Similarly if it is a hard register, but one that is not
968 valid as an address register.
970 If the location is not addressable, but does not have one of the
971 above forms, assign a stack slot. We have to do this to avoid the
972 potential of producing lots of reloads if, e.g., a location involves
973 a pseudo that didn't get a hard register and has an equivalent memory
974 location that also involves a pseudo that didn't get a hard register.
976 Perhaps at some point we will improve reload_when_needed handling
977 so this problem goes away. But that's very hairy. */
979 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
980 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
982 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
984 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
986 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
987 else if (CONSTANT_P (XEXP (x, 0))
988 || (REG_P (XEXP (x, 0))
989 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
990 || (GET_CODE (XEXP (x, 0)) == PLUS
991 && REG_P (XEXP (XEXP (x, 0), 0))
992 && (REGNO (XEXP (XEXP (x, 0), 0))
993 < FIRST_PSEUDO_REGISTER)
994 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
995 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
998 /* Make a new stack slot. Then indicate that something
999 changed so we go back and recompute offsets for
1000 eliminable registers because the allocation of memory
1001 below might change some offset. reg_equiv_{mem,address}
1002 will be set up for this pseudo on the next pass around
1004 reg_equiv_memory_loc[i] = 0;
1005 reg_equiv_init[i] = 0;
1010 if (caller_save_needed)
1011 setup_save_areas ();
1013 /* If we allocated another stack slot, redo elimination bookkeeping. */
1014 if (starting_frame_size != get_frame_size ())
1016 if (starting_frame_size && cfun->stack_alignment_needed)
1018 /* If we have a stack frame, we must align it now. The
1019 stack size may be a part of the offset computation for
1020 register elimination. So if this changes the stack size,
1021 then repeat the elimination bookkeeping. We don't
1022 realign when there is no stack, as that will cause a
1023 stack frame when none is needed should
1024 STARTING_FRAME_OFFSET not be already aligned to
1026 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
1027 if (starting_frame_size != get_frame_size ())
1031 if (caller_save_needed)
1033 save_call_clobbered_regs ();
1034 /* That might have allocated new insn_chain structures. */
1035 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1038 calculate_needs_all_insns (global);
1040 CLEAR_REG_SET (&spilled_pseudos);
1043 something_changed = 0;
1045 /* If we allocated any new memory locations, make another pass
1046 since it might have changed elimination offsets. */
1047 if (starting_frame_size != get_frame_size ())
1048 something_changed = 1;
1050 /* Even if the frame size remained the same, we might still have
1051 changed elimination offsets, e.g. if find_reloads called
1052 force_const_mem requiring the back end to allocate a constant
1053 pool base register that needs to be saved on the stack. */
1054 else if (!verify_initial_elim_offsets ())
1055 something_changed = 1;
1058 HARD_REG_SET to_spill;
1059 CLEAR_HARD_REG_SET (to_spill);
1060 update_eliminables (&to_spill);
1061 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1063 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1064 if (TEST_HARD_REG_BIT (to_spill, i))
1066 spill_hard_reg (i, 1);
1069 /* Regardless of the state of spills, if we previously had
1070 a register that we thought we could eliminate, but now can
1071 not eliminate, we must run another pass.
1073 Consider pseudos which have an entry in reg_equiv_* which
1074 reference an eliminable register. We must make another pass
1075 to update reg_equiv_* so that we do not substitute in the
1076 old value from when we thought the elimination could be
1078 something_changed = 1;
1082 select_reload_regs ();
1086 if (insns_need_reload != 0 || did_spill)
1087 something_changed |= finish_spills (global);
1089 if (! something_changed)
1092 if (caller_save_needed)
1093 delete_caller_save_insns ();
1095 obstack_free (&reload_obstack, reload_firstobj);
1098 /* If global-alloc was run, notify it of any register eliminations we have
1101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1102 if (ep->can_eliminate)
1103 mark_elimination (ep->from, ep->to);
1105 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1106 If that insn didn't set the register (i.e., it copied the register to
1107 memory), just delete that insn instead of the equivalencing insn plus
1108 anything now dead. If we call delete_dead_insn on that insn, we may
1109 delete the insn that actually sets the register if the register dies
1110 there and that is incorrect. */
1112 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1114 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1117 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1119 rtx equiv_insn = XEXP (list, 0);
1121 /* If we already deleted the insn or if it may trap, we can't
1122 delete it. The latter case shouldn't happen, but can
1123 if an insn has a variable address, gets a REG_EH_REGION
1124 note added to it, and then gets converted into a load
1125 from a constant address. */
1126 if (NOTE_P (equiv_insn)
1127 || can_throw_internal (equiv_insn))
1129 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1130 delete_dead_insn (equiv_insn);
1132 SET_INSN_DELETED (equiv_insn);
1137 /* Use the reload registers where necessary
1138 by generating move instructions to move the must-be-register
1139 values into or out of the reload registers. */
1141 if (insns_need_reload != 0 || something_needs_elimination
1142 || something_needs_operands_changed)
1144 HOST_WIDE_INT old_frame_size = get_frame_size ();
1146 reload_as_needed (global);
1148 gcc_assert (old_frame_size == get_frame_size ());
1150 gcc_assert (verify_initial_elim_offsets ());
1153 /* If we were able to eliminate the frame pointer, show that it is no
1154 longer live at the start of any basic block. If it ls live by
1155 virtue of being in a pseudo, that pseudo will be marked live
1156 and hence the frame pointer will be known to be live via that
1159 if (! frame_pointer_needed)
1162 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1163 bitmap_clear_bit (df_get_live_top (bb), HARD_FRAME_POINTER_REGNUM);
1166 /* Come here (with failure set nonzero) if we can't get enough spill
1170 CLEAR_REG_SET (&spilled_pseudos);
1171 reload_in_progress = 0;
1173 /* Now eliminate all pseudo regs by modifying them into
1174 their equivalent memory references.
1175 The REG-rtx's for the pseudos are modified in place,
1176 so all insns that used to refer to them now refer to memory.
1178 For a reg that has a reg_equiv_address, all those insns
1179 were changed by reloading so that no insns refer to it any longer;
1180 but the DECL_RTL of a variable decl may refer to it,
1181 and if so this causes the debugging info to mention the variable. */
1183 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1187 if (reg_equiv_mem[i])
1188 addr = XEXP (reg_equiv_mem[i], 0);
1190 if (reg_equiv_address[i])
1191 addr = reg_equiv_address[i];
1195 if (reg_renumber[i] < 0)
1197 rtx reg = regno_reg_rtx[i];
1199 REG_USERVAR_P (reg) = 0;
1200 PUT_CODE (reg, MEM);
1201 XEXP (reg, 0) = addr;
1202 if (reg_equiv_memory_loc[i])
1203 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1206 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1207 MEM_ATTRS (reg) = 0;
1209 MEM_NOTRAP_P (reg) = 1;
1211 else if (reg_equiv_mem[i])
1212 XEXP (reg_equiv_mem[i], 0) = addr;
1216 /* We must set reload_completed now since the cleanup_subreg_operands call
1217 below will re-recognize each insn and reload may have generated insns
1218 which are only valid during and after reload. */
1219 reload_completed = 1;
1221 /* Make a pass over all the insns and delete all USEs which we inserted
1222 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1223 notes. Delete all CLOBBER insns, except those that refer to the return
1224 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1225 from misarranging variable-array code, and simplify (subreg (reg))
1226 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1227 are no longer useful or accurate. Strip and regenerate REG_INC notes
1228 that may have been moved around. */
1230 for (insn = first; insn; insn = next)
1232 next = NEXT_INSN (insn);
1238 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1239 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1241 if ((GET_CODE (PATTERN (insn)) == USE
1242 /* We mark with QImode USEs introduced by reload itself. */
1243 && (GET_MODE (insn) == QImode
1244 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1245 || (GET_CODE (PATTERN (insn)) == CLOBBER
1246 && (!MEM_P (XEXP (PATTERN (insn), 0))
1247 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1248 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0))
1250 && XEXP (XEXP (PATTERN (insn), 0), 0)
1251 != stack_pointer_rtx))
1252 && (!REG_P (XEXP (PATTERN (insn), 0))
1253 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1259 /* Some CLOBBERs may survive until here and still reference
1260 unassigned pseudos with const equivalent, which may in turn cause
1261 ICE in later passes if the reference remains in place. */
1262 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1263 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1264 VOIDmode, PATTERN (insn));
1266 /* Discard obvious no-ops, even without -O. This optimization
1267 is fast and doesn't interfere with debugging. */
1268 if (NONJUMP_INSN_P (insn)
1269 && GET_CODE (PATTERN (insn)) == SET
1270 && REG_P (SET_SRC (PATTERN (insn)))
1271 && REG_P (SET_DEST (PATTERN (insn)))
1272 && (REGNO (SET_SRC (PATTERN (insn)))
1273 == REGNO (SET_DEST (PATTERN (insn)))))
1279 pnote = ®_NOTES (insn);
1282 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1283 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1284 || REG_NOTE_KIND (*pnote) == REG_INC
1285 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1286 || REG_NOTE_KIND (*pnote) == REG_LIBCALL_ID
1287 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1288 *pnote = XEXP (*pnote, 1);
1290 pnote = &XEXP (*pnote, 1);
1294 add_auto_inc_notes (insn, PATTERN (insn));
1297 /* Simplify (subreg (reg)) if it appears as an operand. */
1298 cleanup_subreg_operands (insn);
1300 /* Clean up invalid ASMs so that they don't confuse later passes.
1302 if (asm_noperands (PATTERN (insn)) >= 0)
1304 extract_insn (insn);
1305 if (!constrain_operands (1))
1307 error_for_asm (insn,
1308 "%<asm%> operand has impossible constraints");
1316 /* If we are doing stack checking, give a warning if this function's
1317 frame size is larger than we expect. */
1318 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1320 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1321 static int verbose_warned = 0;
1323 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1324 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1325 size += UNITS_PER_WORD;
1327 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1329 warning (0, "frame size too large for reliable stack checking");
1330 if (! verbose_warned)
1332 warning (0, "try reducing the number of local variables");
1338 /* Indicate that we no longer have known memory locations or constants. */
1339 if (reg_equiv_constant)
1340 free (reg_equiv_constant);
1341 if (reg_equiv_invariant)
1342 free (reg_equiv_invariant);
1343 reg_equiv_constant = 0;
1344 reg_equiv_invariant = 0;
1345 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1346 reg_equiv_memory_loc = 0;
1348 if (offsets_known_at)
1349 free (offsets_known_at);
1353 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1354 if (reg_equiv_alt_mem_list[i])
1355 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1356 free (reg_equiv_alt_mem_list);
1358 free (reg_equiv_mem);
1360 free (reg_equiv_address);
1361 free (reg_max_ref_width);
1362 free (reg_old_renumber);
1363 free (pseudo_previous_regs);
1364 free (pseudo_forbidden_regs);
1366 CLEAR_HARD_REG_SET (used_spill_regs);
1367 for (i = 0; i < n_spills; i++)
1368 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1370 /* Free all the insn_chain structures at once. */
1371 obstack_free (&reload_obstack, reload_startobj);
1372 unused_insn_chains = 0;
1373 fixup_abnormal_edges ();
1375 /* Replacing pseudos with their memory equivalents might have
1376 created shared rtx. Subsequent passes would get confused
1377 by this, so unshare everything here. */
1378 unshare_all_rtl_again (first);
1380 #ifdef STACK_BOUNDARY
1381 /* init_emit has set the alignment of the hard frame pointer
1382 to STACK_BOUNDARY. It is very likely no longer valid if
1383 the hard frame pointer was used for register allocation. */
1384 if (!frame_pointer_needed)
1385 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1391 /* Yet another special case. Unfortunately, reg-stack forces people to
1392 write incorrect clobbers in asm statements. These clobbers must not
1393 cause the register to appear in bad_spill_regs, otherwise we'll call
1394 fatal_insn later. We clear the corresponding regnos in the live
1395 register sets to avoid this.
1396 The whole thing is rather sick, I'm afraid. */
1399 maybe_fix_stack_asms (void)
1402 const char *constraints[MAX_RECOG_OPERANDS];
1403 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1404 struct insn_chain *chain;
1406 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1409 HARD_REG_SET clobbered, allowed;
1412 if (! INSN_P (chain->insn)
1413 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1415 pat = PATTERN (chain->insn);
1416 if (GET_CODE (pat) != PARALLEL)
1419 CLEAR_HARD_REG_SET (clobbered);
1420 CLEAR_HARD_REG_SET (allowed);
1422 /* First, make a mask of all stack regs that are clobbered. */
1423 for (i = 0; i < XVECLEN (pat, 0); i++)
1425 rtx t = XVECEXP (pat, 0, i);
1426 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1427 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1430 /* Get the operand values and constraints out of the insn. */
1431 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1432 constraints, operand_mode, NULL);
1434 /* For every operand, see what registers are allowed. */
1435 for (i = 0; i < noperands; i++)
1437 const char *p = constraints[i];
1438 /* For every alternative, we compute the class of registers allowed
1439 for reloading in CLS, and merge its contents into the reg set
1441 int cls = (int) NO_REGS;
1447 if (c == '\0' || c == ',' || c == '#')
1449 /* End of one alternative - mark the regs in the current
1450 class, and reset the class. */
1451 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1457 } while (c != '\0' && c != ',');
1465 case '=': case '+': case '*': case '%': case '?': case '!':
1466 case '0': case '1': case '2': case '3': case '4': case 'm':
1467 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1468 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1469 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1474 cls = (int) reg_class_subunion[cls]
1475 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1480 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1484 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1485 cls = (int) reg_class_subunion[cls]
1486 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1488 cls = (int) reg_class_subunion[cls]
1489 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1491 p += CONSTRAINT_LEN (c, p);
1494 /* Those of the registers which are clobbered, but allowed by the
1495 constraints, must be usable as reload registers. So clear them
1496 out of the life information. */
1497 AND_HARD_REG_SET (allowed, clobbered);
1498 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1499 if (TEST_HARD_REG_BIT (allowed, i))
1501 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1502 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1509 /* Copy the global variables n_reloads and rld into the corresponding elts
1512 copy_reloads (struct insn_chain *chain)
1514 chain->n_reloads = n_reloads;
1515 chain->rld = obstack_alloc (&reload_obstack,
1516 n_reloads * sizeof (struct reload));
1517 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1518 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1521 /* Walk the chain of insns, and determine for each whether it needs reloads
1522 and/or eliminations. Build the corresponding insns_need_reload list, and
1523 set something_needs_elimination as appropriate. */
1525 calculate_needs_all_insns (int global)
1527 struct insn_chain **pprev_reload = &insns_need_reload;
1528 struct insn_chain *chain, *next = 0;
1530 something_needs_elimination = 0;
1532 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1533 for (chain = reload_insn_chain; chain != 0; chain = next)
1535 rtx insn = chain->insn;
1539 /* Clear out the shortcuts. */
1540 chain->n_reloads = 0;
1541 chain->need_elim = 0;
1542 chain->need_reload = 0;
1543 chain->need_operand_change = 0;
1545 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1546 include REG_LABEL), we need to see what effects this has on the
1547 known offsets at labels. */
1549 if (LABEL_P (insn) || JUMP_P (insn)
1550 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1551 set_label_offsets (insn, insn, 0);
1555 rtx old_body = PATTERN (insn);
1556 int old_code = INSN_CODE (insn);
1557 rtx old_notes = REG_NOTES (insn);
1558 int did_elimination = 0;
1559 int operands_changed = 0;
1560 rtx set = single_set (insn);
1562 /* Skip insns that only set an equivalence. */
1563 if (set && REG_P (SET_DEST (set))
1564 && reg_renumber[REGNO (SET_DEST (set))] < 0
1565 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1566 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1567 && reg_equiv_init[REGNO (SET_DEST (set))])
1570 /* If needed, eliminate any eliminable registers. */
1571 if (num_eliminable || num_eliminable_invariants)
1572 did_elimination = eliminate_regs_in_insn (insn, 0);
1574 /* Analyze the instruction. */
1575 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1576 global, spill_reg_order);
1578 /* If a no-op set needs more than one reload, this is likely
1579 to be something that needs input address reloads. We
1580 can't get rid of this cleanly later, and it is of no use
1581 anyway, so discard it now.
1582 We only do this when expensive_optimizations is enabled,
1583 since this complements reload inheritance / output
1584 reload deletion, and it can make debugging harder. */
1585 if (flag_expensive_optimizations && n_reloads > 1)
1587 rtx set = single_set (insn);
1589 && SET_SRC (set) == SET_DEST (set)
1590 && REG_P (SET_SRC (set))
1591 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1594 /* Delete it from the reload chain. */
1596 chain->prev->next = next;
1598 reload_insn_chain = next;
1600 next->prev = chain->prev;
1601 chain->next = unused_insn_chains;
1602 unused_insn_chains = chain;
1607 update_eliminable_offsets ();
1609 /* Remember for later shortcuts which insns had any reloads or
1610 register eliminations. */
1611 chain->need_elim = did_elimination;
1612 chain->need_reload = n_reloads > 0;
1613 chain->need_operand_change = operands_changed;
1615 /* Discard any register replacements done. */
1616 if (did_elimination)
1618 obstack_free (&reload_obstack, reload_insn_firstobj);
1619 PATTERN (insn) = old_body;
1620 INSN_CODE (insn) = old_code;
1621 REG_NOTES (insn) = old_notes;
1622 something_needs_elimination = 1;
1625 something_needs_operands_changed |= operands_changed;
1629 copy_reloads (chain);
1630 *pprev_reload = chain;
1631 pprev_reload = &chain->next_need_reload;
1638 /* Comparison function for qsort to decide which of two reloads
1639 should be handled first. *P1 and *P2 are the reload numbers. */
1642 reload_reg_class_lower (const void *r1p, const void *r2p)
1644 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1647 /* Consider required reloads before optional ones. */
1648 t = rld[r1].optional - rld[r2].optional;
1652 /* Count all solitary classes before non-solitary ones. */
1653 t = ((reg_class_size[(int) rld[r2].class] == 1)
1654 - (reg_class_size[(int) rld[r1].class] == 1));
1658 /* Aside from solitaires, consider all multi-reg groups first. */
1659 t = rld[r2].nregs - rld[r1].nregs;
1663 /* Consider reloads in order of increasing reg-class number. */
1664 t = (int) rld[r1].class - (int) rld[r2].class;
1668 /* If reloads are equally urgent, sort by reload number,
1669 so that the results of qsort leave nothing to chance. */
1673 /* The cost of spilling each hard reg. */
1674 static int spill_cost[FIRST_PSEUDO_REGISTER];
1676 /* When spilling multiple hard registers, we use SPILL_COST for the first
1677 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1678 only the first hard reg for a multi-reg pseudo. */
1679 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1681 /* Update the spill cost arrays, considering that pseudo REG is live. */
1684 count_pseudo (int reg)
1686 int freq = REG_FREQ (reg);
1687 int r = reg_renumber[reg];
1690 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1691 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1694 SET_REGNO_REG_SET (&pseudos_counted, reg);
1696 gcc_assert (r >= 0);
1698 spill_add_cost[r] += freq;
1700 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1702 spill_cost[r + nregs] += freq;
1705 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1706 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1709 order_regs_for_reload (struct insn_chain *chain)
1712 HARD_REG_SET used_by_pseudos;
1713 HARD_REG_SET used_by_pseudos2;
1714 reg_set_iterator rsi;
1716 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1718 memset (spill_cost, 0, sizeof spill_cost);
1719 memset (spill_add_cost, 0, sizeof spill_add_cost);
1721 /* Count number of uses of each hard reg by pseudo regs allocated to it
1722 and then order them by decreasing use. First exclude hard registers
1723 that are live in or across this insn. */
1725 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1726 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1727 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1728 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1730 /* Now find out which pseudos are allocated to it, and update
1732 CLEAR_REG_SET (&pseudos_counted);
1734 EXECUTE_IF_SET_IN_REG_SET
1735 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1739 EXECUTE_IF_SET_IN_REG_SET
1740 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1744 CLEAR_REG_SET (&pseudos_counted);
1747 /* Vector of reload-numbers showing the order in which the reloads should
1749 static short reload_order[MAX_RELOADS];
1751 /* This is used to keep track of the spill regs used in one insn. */
1752 static HARD_REG_SET used_spill_regs_local;
1754 /* We decided to spill hard register SPILLED, which has a size of
1755 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1756 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1757 update SPILL_COST/SPILL_ADD_COST. */
1760 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1762 int r = reg_renumber[reg];
1763 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1765 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1766 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1769 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1771 spill_add_cost[r] -= REG_FREQ (reg);
1773 spill_cost[r + nregs] -= REG_FREQ (reg);
1776 /* Find reload register to use for reload number ORDER. */
1779 find_reg (struct insn_chain *chain, int order)
1781 int rnum = reload_order[order];
1782 struct reload *rl = rld + rnum;
1783 int best_cost = INT_MAX;
1787 HARD_REG_SET not_usable;
1788 HARD_REG_SET used_by_other_reload;
1789 reg_set_iterator rsi;
1791 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1792 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1793 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1795 CLEAR_HARD_REG_SET (used_by_other_reload);
1796 for (k = 0; k < order; k++)
1798 int other = reload_order[k];
1800 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1801 for (j = 0; j < rld[other].nregs; j++)
1802 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1805 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1807 unsigned int regno = i;
1809 if (! TEST_HARD_REG_BIT (not_usable, regno)
1810 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1811 && HARD_REGNO_MODE_OK (regno, rl->mode))
1813 int this_cost = spill_cost[regno];
1815 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1817 for (j = 1; j < this_nregs; j++)
1819 this_cost += spill_add_cost[regno + j];
1820 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1821 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1826 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1828 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1830 if (this_cost < best_cost
1831 /* Among registers with equal cost, prefer caller-saved ones, or
1832 use REG_ALLOC_ORDER if it is defined. */
1833 || (this_cost == best_cost
1834 #ifdef REG_ALLOC_ORDER
1835 && (inv_reg_alloc_order[regno]
1836 < inv_reg_alloc_order[best_reg])
1838 && call_used_regs[regno]
1839 && ! call_used_regs[best_reg]
1844 best_cost = this_cost;
1852 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1854 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1855 rl->regno = best_reg;
1857 EXECUTE_IF_SET_IN_REG_SET
1858 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1860 count_spilled_pseudo (best_reg, rl->nregs, j);
1863 EXECUTE_IF_SET_IN_REG_SET
1864 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1866 count_spilled_pseudo (best_reg, rl->nregs, j);
1869 for (i = 0; i < rl->nregs; i++)
1871 gcc_assert (spill_cost[best_reg + i] == 0);
1872 gcc_assert (spill_add_cost[best_reg + i] == 0);
1873 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1878 /* Find more reload regs to satisfy the remaining need of an insn, which
1880 Do it by ascending class number, since otherwise a reg
1881 might be spilled for a big class and might fail to count
1882 for a smaller class even though it belongs to that class. */
1885 find_reload_regs (struct insn_chain *chain)
1889 /* In order to be certain of getting the registers we need,
1890 we must sort the reloads into order of increasing register class.
1891 Then our grabbing of reload registers will parallel the process
1892 that provided the reload registers. */
1893 for (i = 0; i < chain->n_reloads; i++)
1895 /* Show whether this reload already has a hard reg. */
1896 if (chain->rld[i].reg_rtx)
1898 int regno = REGNO (chain->rld[i].reg_rtx);
1899 chain->rld[i].regno = regno;
1901 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1904 chain->rld[i].regno = -1;
1905 reload_order[i] = i;
1908 n_reloads = chain->n_reloads;
1909 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1911 CLEAR_HARD_REG_SET (used_spill_regs_local);
1914 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1916 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1918 /* Compute the order of preference for hard registers to spill. */
1920 order_regs_for_reload (chain);
1922 for (i = 0; i < n_reloads; i++)
1924 int r = reload_order[i];
1926 /* Ignore reloads that got marked inoperative. */
1927 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1928 && ! rld[r].optional
1929 && rld[r].regno == -1)
1930 if (! find_reg (chain, i))
1933 fprintf (dump_file, "reload failure for reload %d\n", r);
1934 spill_failure (chain->insn, rld[r].class);
1940 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1941 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1943 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1947 select_reload_regs (void)
1949 struct insn_chain *chain;
1951 /* Try to satisfy the needs for each insn. */
1952 for (chain = insns_need_reload; chain != 0;
1953 chain = chain->next_need_reload)
1954 find_reload_regs (chain);
1957 /* Delete all insns that were inserted by emit_caller_save_insns during
1960 delete_caller_save_insns (void)
1962 struct insn_chain *c = reload_insn_chain;
1966 while (c != 0 && c->is_caller_save_insn)
1968 struct insn_chain *next = c->next;
1971 if (c == reload_insn_chain)
1972 reload_insn_chain = next;
1976 next->prev = c->prev;
1978 c->prev->next = next;
1979 c->next = unused_insn_chains;
1980 unused_insn_chains = c;
1988 /* Handle the failure to find a register to spill.
1989 INSN should be one of the insns which needed this particular spill reg. */
1992 spill_failure (rtx insn, enum reg_class class)
1994 if (asm_noperands (PATTERN (insn)) >= 0)
1995 error_for_asm (insn, "can't find a register in class %qs while "
1996 "reloading %<asm%>",
1997 reg_class_names[class]);
2000 error ("unable to find a register to spill in class %qs",
2001 reg_class_names[class]);
2005 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2006 debug_reload_to_stream (dump_file);
2008 fatal_insn ("this is the insn:", insn);
2012 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2013 data that is dead in INSN. */
2016 delete_dead_insn (rtx insn)
2018 rtx prev = prev_real_insn (insn);
2021 /* If the previous insn sets a register that dies in our insn, delete it
2023 if (prev && GET_CODE (PATTERN (prev)) == SET
2024 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2025 && reg_mentioned_p (prev_dest, PATTERN (insn))
2026 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2027 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2028 delete_dead_insn (prev);
2030 SET_INSN_DELETED (insn);
2033 /* Modify the home of pseudo-reg I.
2034 The new home is present in reg_renumber[I].
2036 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2037 or it may be -1, meaning there is none or it is not relevant.
2038 This is used so that all pseudos spilled from a given hard reg
2039 can share one stack slot. */
2042 alter_reg (int i, int from_reg)
2044 /* When outputting an inline function, this can happen
2045 for a reg that isn't actually used. */
2046 if (regno_reg_rtx[i] == 0)
2049 /* If the reg got changed to a MEM at rtl-generation time,
2051 if (!REG_P (regno_reg_rtx[i]))
2054 /* Modify the reg-rtx to contain the new hard reg
2055 number or else to contain its pseudo reg number. */
2056 SET_REGNO (regno_reg_rtx[i],
2057 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2059 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2060 allocate a stack slot for it. */
2062 if (reg_renumber[i] < 0
2063 && REG_N_REFS (i) > 0
2064 && reg_equiv_constant[i] == 0
2065 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2066 && reg_equiv_memory_loc[i] == 0)
2069 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2070 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2071 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2072 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2073 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2076 /* Each pseudo reg has an inherent size which comes from its own mode,
2077 and a total size which provides room for paradoxical subregs
2078 which refer to the pseudo reg in wider modes.
2080 We can use a slot already allocated if it provides both
2081 enough inherent space and enough total space.
2082 Otherwise, we allocate a new slot, making sure that it has no less
2083 inherent space, and no less total space, then the previous slot. */
2086 alias_set_type alias_set = new_alias_set ();
2088 /* No known place to spill from => no slot to reuse. */
2089 x = assign_stack_local (mode, total_size,
2090 min_align > inherent_align
2091 || total_size > inherent_size ? -1 : 0);
2092 if (BYTES_BIG_ENDIAN)
2093 /* Cancel the big-endian correction done in assign_stack_local.
2094 Get the address of the beginning of the slot.
2095 This is so we can do a big-endian correction unconditionally
2097 adjust = inherent_size - total_size;
2099 /* Nothing can alias this slot except this pseudo. */
2100 set_mem_alias_set (x, alias_set);
2101 dse_record_singleton_alias_set (alias_set, mode);
2104 /* Reuse a stack slot if possible. */
2105 else if (spill_stack_slot[from_reg] != 0
2106 && spill_stack_slot_width[from_reg] >= total_size
2107 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2109 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2110 x = spill_stack_slot[from_reg];
2111 /* Allocate a bigger slot. */
2114 /* Compute maximum size needed, both for inherent size
2115 and for total size. */
2118 if (spill_stack_slot[from_reg])
2120 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2122 mode = GET_MODE (spill_stack_slot[from_reg]);
2123 if (spill_stack_slot_width[from_reg] > total_size)
2124 total_size = spill_stack_slot_width[from_reg];
2125 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2126 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2129 /* Make a slot with that size. */
2130 x = assign_stack_local (mode, total_size,
2131 min_align > inherent_align
2132 || total_size > inherent_size ? -1 : 0);
2135 /* All pseudos mapped to this slot can alias each other. */
2136 if (spill_stack_slot[from_reg])
2138 alias_set_type alias_set
2139 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2140 set_mem_alias_set (x, alias_set);
2141 dse_invalidate_singleton_alias_set (alias_set);
2145 alias_set_type alias_set = new_alias_set ();
2146 set_mem_alias_set (x, alias_set);
2147 dse_record_singleton_alias_set (alias_set, mode);
2150 if (BYTES_BIG_ENDIAN)
2152 /* Cancel the big-endian correction done in assign_stack_local.
2153 Get the address of the beginning of the slot.
2154 This is so we can do a big-endian correction unconditionally
2156 adjust = GET_MODE_SIZE (mode) - total_size;
2159 = adjust_address_nv (x, mode_for_size (total_size
2165 spill_stack_slot[from_reg] = stack_slot;
2166 spill_stack_slot_width[from_reg] = total_size;
2169 /* On a big endian machine, the "address" of the slot
2170 is the address of the low part that fits its inherent mode. */
2171 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2172 adjust += (total_size - inherent_size);
2174 /* If we have any adjustment to make, or if the stack slot is the
2175 wrong mode, make a new stack slot. */
2176 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2178 /* If we have a decl for the original register, set it for the
2179 memory. If this is a shared MEM, make a copy. */
2180 if (REG_EXPR (regno_reg_rtx[i])
2181 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2183 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2185 /* We can do this only for the DECLs home pseudo, not for
2186 any copies of it, since otherwise when the stack slot
2187 is reused, nonoverlapping_memrefs_p might think they
2189 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2191 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2194 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2198 /* Save the stack slot for later. */
2199 reg_equiv_memory_loc[i] = x;
2203 /* Mark the slots in regs_ever_live for the hard regs used by
2204 pseudo-reg number REGNO, accessed in MODE. */
2207 mark_home_live_1 (int regno, enum machine_mode mode)
2211 i = reg_renumber[regno];
2214 lim = end_hard_regno (mode, i);
2216 df_set_regs_ever_live(i++, true);
2219 /* Mark the slots in regs_ever_live for the hard regs
2220 used by pseudo-reg number REGNO. */
2223 mark_home_live (int regno)
2225 if (reg_renumber[regno] >= 0)
2226 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2229 /* This function handles the tracking of elimination offsets around branches.
2231 X is a piece of RTL being scanned.
2233 INSN is the insn that it came from, if any.
2235 INITIAL_P is nonzero if we are to set the offset to be the initial
2236 offset and zero if we are setting the offset of the label to be the
2240 set_label_offsets (rtx x, rtx insn, int initial_p)
2242 enum rtx_code code = GET_CODE (x);
2245 struct elim_table *p;
2250 if (LABEL_REF_NONLOCAL_P (x))
2255 /* ... fall through ... */
2258 /* If we know nothing about this label, set the desired offsets. Note
2259 that this sets the offset at a label to be the offset before a label
2260 if we don't know anything about the label. This is not correct for
2261 the label after a BARRIER, but is the best guess we can make. If
2262 we guessed wrong, we will suppress an elimination that might have
2263 been possible had we been able to guess correctly. */
2265 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2267 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2268 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2269 = (initial_p ? reg_eliminate[i].initial_offset
2270 : reg_eliminate[i].offset);
2271 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2274 /* Otherwise, if this is the definition of a label and it is
2275 preceded by a BARRIER, set our offsets to the known offset of
2279 && (tem = prev_nonnote_insn (insn)) != 0
2281 set_offsets_for_label (insn);
2283 /* If neither of the above cases is true, compare each offset
2284 with those previously recorded and suppress any eliminations
2285 where the offsets disagree. */
2287 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2288 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2289 != (initial_p ? reg_eliminate[i].initial_offset
2290 : reg_eliminate[i].offset))
2291 reg_eliminate[i].can_eliminate = 0;
2296 set_label_offsets (PATTERN (insn), insn, initial_p);
2298 /* ... fall through ... */
2302 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2303 and hence must have all eliminations at their initial offsets. */
2304 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2305 if (REG_NOTE_KIND (tem) == REG_LABEL)
2306 set_label_offsets (XEXP (tem, 0), insn, 1);
2312 /* Each of the labels in the parallel or address vector must be
2313 at their initial offsets. We want the first field for PARALLEL
2314 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2316 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2317 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2322 /* We only care about setting PC. If the source is not RETURN,
2323 IF_THEN_ELSE, or a label, disable any eliminations not at
2324 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2325 isn't one of those possibilities. For branches to a label,
2326 call ourselves recursively.
2328 Note that this can disable elimination unnecessarily when we have
2329 a non-local goto since it will look like a non-constant jump to
2330 someplace in the current function. This isn't a significant
2331 problem since such jumps will normally be when all elimination
2332 pairs are back to their initial offsets. */
2334 if (SET_DEST (x) != pc_rtx)
2337 switch (GET_CODE (SET_SRC (x)))
2344 set_label_offsets (SET_SRC (x), insn, initial_p);
2348 tem = XEXP (SET_SRC (x), 1);
2349 if (GET_CODE (tem) == LABEL_REF)
2350 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2351 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2354 tem = XEXP (SET_SRC (x), 2);
2355 if (GET_CODE (tem) == LABEL_REF)
2356 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2357 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2365 /* If we reach here, all eliminations must be at their initial
2366 offset because we are doing a jump to a variable address. */
2367 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2368 if (p->offset != p->initial_offset)
2369 p->can_eliminate = 0;
2377 /* Scan X and replace any eliminable registers (such as fp) with a
2378 replacement (such as sp), plus an offset.
2380 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2381 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2382 MEM, we are allowed to replace a sum of a register and the constant zero
2383 with the register, which we cannot do outside a MEM. In addition, we need
2384 to record the fact that a register is referenced outside a MEM.
2386 If INSN is an insn, it is the insn containing X. If we replace a REG
2387 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2388 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2389 the REG is being modified.
2391 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2392 That's used when we eliminate in expressions stored in notes.
2393 This means, do not set ref_outside_mem even if the reference
2396 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2397 replacements done assuming all offsets are at their initial values. If
2398 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2399 encounter, return the actual location so that find_reloads will do
2400 the proper thing. */
2403 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2404 bool may_use_invariant)
2406 enum rtx_code code = GET_CODE (x);
2407 struct elim_table *ep;
2414 if (! current_function_decl)
2437 /* First handle the case where we encounter a bare register that
2438 is eliminable. Replace it with a PLUS. */
2439 if (regno < FIRST_PSEUDO_REGISTER)
2441 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2443 if (ep->from_rtx == x && ep->can_eliminate)
2444 return plus_constant (ep->to_rtx, ep->previous_offset);
2447 else if (reg_renumber && reg_renumber[regno] < 0
2448 && reg_equiv_invariant && reg_equiv_invariant[regno])
2450 if (may_use_invariant)
2451 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2452 mem_mode, insn, true);
2453 /* There exists at least one use of REGNO that cannot be
2454 eliminated. Prevent the defining insn from being deleted. */
2455 reg_equiv_init[regno] = NULL_RTX;
2456 alter_reg (regno, -1);
2460 /* You might think handling MINUS in a manner similar to PLUS is a
2461 good idea. It is not. It has been tried multiple times and every
2462 time the change has had to have been reverted.
2464 Other parts of reload know a PLUS is special (gen_reload for example)
2465 and require special code to handle code a reloaded PLUS operand.
2467 Also consider backends where the flags register is clobbered by a
2468 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2469 lea instruction comes to mind). If we try to reload a MINUS, we
2470 may kill the flags register that was holding a useful value.
2472 So, please before trying to handle MINUS, consider reload as a
2473 whole instead of this little section as well as the backend issues. */
2475 /* If this is the sum of an eliminable register and a constant, rework
2477 if (REG_P (XEXP (x, 0))
2478 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2479 && CONSTANT_P (XEXP (x, 1)))
2481 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2483 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2485 /* The only time we want to replace a PLUS with a REG (this
2486 occurs when the constant operand of the PLUS is the negative
2487 of the offset) is when we are inside a MEM. We won't want
2488 to do so at other times because that would change the
2489 structure of the insn in a way that reload can't handle.
2490 We special-case the commonest situation in
2491 eliminate_regs_in_insn, so just replace a PLUS with a
2492 PLUS here, unless inside a MEM. */
2493 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2494 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2497 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2498 plus_constant (XEXP (x, 1),
2499 ep->previous_offset));
2502 /* If the register is not eliminable, we are done since the other
2503 operand is a constant. */
2507 /* If this is part of an address, we want to bring any constant to the
2508 outermost PLUS. We will do this by doing register replacement in
2509 our operands and seeing if a constant shows up in one of them.
2511 Note that there is no risk of modifying the structure of the insn,
2512 since we only get called for its operands, thus we are either
2513 modifying the address inside a MEM, or something like an address
2514 operand of a load-address insn. */
2517 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2518 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2520 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2522 /* If one side is a PLUS and the other side is a pseudo that
2523 didn't get a hard register but has a reg_equiv_constant,
2524 we must replace the constant here since it may no longer
2525 be in the position of any operand. */
2526 if (GET_CODE (new0) == PLUS && REG_P (new1)
2527 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2528 && reg_renumber[REGNO (new1)] < 0
2529 && reg_equiv_constant != 0
2530 && reg_equiv_constant[REGNO (new1)] != 0)
2531 new1 = reg_equiv_constant[REGNO (new1)];
2532 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2533 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2534 && reg_renumber[REGNO (new0)] < 0
2535 && reg_equiv_constant[REGNO (new0)] != 0)
2536 new0 = reg_equiv_constant[REGNO (new0)];
2538 new = form_sum (new0, new1);
2540 /* As above, if we are not inside a MEM we do not want to
2541 turn a PLUS into something else. We might try to do so here
2542 for an addition of 0 if we aren't optimizing. */
2543 if (! mem_mode && GET_CODE (new) != PLUS)
2544 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2552 /* If this is the product of an eliminable register and a
2553 constant, apply the distribute law and move the constant out
2554 so that we have (plus (mult ..) ..). This is needed in order
2555 to keep load-address insns valid. This case is pathological.
2556 We ignore the possibility of overflow here. */
2557 if (REG_P (XEXP (x, 0))
2558 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2559 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2560 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2562 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2565 /* Refs inside notes don't count for this purpose. */
2566 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2567 || GET_CODE (insn) == INSN_LIST)))
2568 ep->ref_outside_mem = 1;
2571 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2572 ep->previous_offset * INTVAL (XEXP (x, 1)));
2575 /* ... fall through ... */
2579 /* See comments before PLUS about handling MINUS. */
2581 case DIV: case UDIV:
2582 case MOD: case UMOD:
2583 case AND: case IOR: case XOR:
2584 case ROTATERT: case ROTATE:
2585 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2587 case GE: case GT: case GEU: case GTU:
2588 case LE: case LT: case LEU: case LTU:
2590 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2591 rtx new1 = XEXP (x, 1)
2592 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2594 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2595 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2600 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2603 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2604 if (new != XEXP (x, 0))
2606 /* If this is a REG_DEAD note, it is not valid anymore.
2607 Using the eliminated version could result in creating a
2608 REG_DEAD note for the stack or frame pointer. */
2609 if (GET_MODE (x) == REG_DEAD)
2611 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2614 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2618 /* ... fall through ... */
2621 /* Now do eliminations in the rest of the chain. If this was
2622 an EXPR_LIST, this might result in allocating more memory than is
2623 strictly needed, but it simplifies the code. */
2626 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2627 if (new != XEXP (x, 1))
2629 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2637 /* We do not support elimination of a register that is modified.
2638 elimination_effects has already make sure that this does not
2644 /* We do not support elimination of a register that is modified.
2645 elimination_effects has already make sure that this does not
2646 happen. The only remaining case we need to consider here is
2647 that the increment value may be an eliminable register. */
2648 if (GET_CODE (XEXP (x, 1)) == PLUS
2649 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2651 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2654 if (new != XEXP (XEXP (x, 1), 1))
2655 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2656 gen_rtx_PLUS (GET_MODE (x),
2661 case STRICT_LOW_PART:
2663 case SIGN_EXTEND: case ZERO_EXTEND:
2664 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2665 case FLOAT: case FIX:
2666 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2675 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2676 if (new != XEXP (x, 0))
2677 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2681 /* Similar to above processing, but preserve SUBREG_BYTE.
2682 Convert (subreg (mem)) to (mem) if not paradoxical.
2683 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2684 pseudo didn't get a hard reg, we must replace this with the
2685 eliminated version of the memory location because push_reload
2686 may do the replacement in certain circumstances. */
2687 if (REG_P (SUBREG_REG (x))
2688 && (GET_MODE_SIZE (GET_MODE (x))
2689 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2690 && reg_equiv_memory_loc != 0
2691 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2693 new = SUBREG_REG (x);
2696 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2698 if (new != SUBREG_REG (x))
2700 int x_size = GET_MODE_SIZE (GET_MODE (x));
2701 int new_size = GET_MODE_SIZE (GET_MODE (new));
2704 && ((x_size < new_size
2705 #ifdef WORD_REGISTER_OPERATIONS
2706 /* On these machines, combine can create rtl of the form
2707 (set (subreg:m1 (reg:m2 R) 0) ...)
2708 where m1 < m2, and expects something interesting to
2709 happen to the entire word. Moreover, it will use the
2710 (reg:m2 R) later, expecting all bits to be preserved.
2711 So if the number of words is the same, preserve the
2712 subreg so that push_reload can see it. */
2713 && ! ((x_size - 1) / UNITS_PER_WORD
2714 == (new_size -1 ) / UNITS_PER_WORD)
2717 || x_size == new_size)
2719 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2721 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2727 /* Our only special processing is to pass the mode of the MEM to our
2728 recursive call and copy the flags. While we are here, handle this
2729 case more efficiently. */
2731 replace_equiv_address_nv (x,
2732 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2736 /* Handle insn_list USE that a call to a pure function may generate. */
2737 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2738 if (new != XEXP (x, 0))
2739 return gen_rtx_USE (GET_MODE (x), new);
2751 /* Process each of our operands recursively. If any have changed, make a
2753 fmt = GET_RTX_FORMAT (code);
2754 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2758 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2759 if (new != XEXP (x, i) && ! copied)
2761 x = shallow_copy_rtx (x);
2766 else if (*fmt == 'E')
2769 for (j = 0; j < XVECLEN (x, i); j++)
2771 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2772 if (new != XVECEXP (x, i, j) && ! copied_vec)
2774 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2778 x = shallow_copy_rtx (x);
2781 XVEC (x, i) = new_v;
2784 XVECEXP (x, i, j) = new;
2793 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2795 return eliminate_regs_1 (x, mem_mode, insn, false);
2798 /* Scan rtx X for modifications of elimination target registers. Update
2799 the table of eliminables to reflect the changed state. MEM_MODE is
2800 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2803 elimination_effects (rtx x, enum machine_mode mem_mode)
2805 enum rtx_code code = GET_CODE (x);
2806 struct elim_table *ep;
2831 /* First handle the case where we encounter a bare register that
2832 is eliminable. Replace it with a PLUS. */
2833 if (regno < FIRST_PSEUDO_REGISTER)
2835 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2837 if (ep->from_rtx == x && ep->can_eliminate)
2840 ep->ref_outside_mem = 1;
2845 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2846 && reg_equiv_constant[regno]
2847 && ! function_invariant_p (reg_equiv_constant[regno]))
2848 elimination_effects (reg_equiv_constant[regno], mem_mode);
2857 /* If we modify the source of an elimination rule, disable it. */
2858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2859 if (ep->from_rtx == XEXP (x, 0))
2860 ep->can_eliminate = 0;
2862 /* If we modify the target of an elimination rule by adding a constant,
2863 update its offset. If we modify the target in any other way, we'll
2864 have to disable the rule as well. */
2865 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2866 if (ep->to_rtx == XEXP (x, 0))
2868 int size = GET_MODE_SIZE (mem_mode);
2870 /* If more bytes than MEM_MODE are pushed, account for them. */
2871 #ifdef PUSH_ROUNDING
2872 if (ep->to_rtx == stack_pointer_rtx)
2873 size = PUSH_ROUNDING (size);
2875 if (code == PRE_DEC || code == POST_DEC)
2877 else if (code == PRE_INC || code == POST_INC)
2879 else if (code == PRE_MODIFY || code == POST_MODIFY)
2881 if (GET_CODE (XEXP (x, 1)) == PLUS
2882 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2883 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2884 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2886 ep->can_eliminate = 0;
2890 /* These two aren't unary operators. */
2891 if (code == POST_MODIFY || code == PRE_MODIFY)
2894 /* Fall through to generic unary operation case. */
2895 case STRICT_LOW_PART:
2897 case SIGN_EXTEND: case ZERO_EXTEND:
2898 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2899 case FLOAT: case FIX:
2900 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2909 elimination_effects (XEXP (x, 0), mem_mode);
2913 if (REG_P (SUBREG_REG (x))
2914 && (GET_MODE_SIZE (GET_MODE (x))
2915 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2916 && reg_equiv_memory_loc != 0
2917 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2920 elimination_effects (SUBREG_REG (x), mem_mode);
2924 /* If using a register that is the source of an eliminate we still
2925 think can be performed, note it cannot be performed since we don't
2926 know how this register is used. */
2927 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2928 if (ep->from_rtx == XEXP (x, 0))
2929 ep->can_eliminate = 0;
2931 elimination_effects (XEXP (x, 0), mem_mode);
2935 /* If clobbering a register that is the replacement register for an
2936 elimination we still think can be performed, note that it cannot
2937 be performed. Otherwise, we need not be concerned about it. */
2938 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2939 if (ep->to_rtx == XEXP (x, 0))
2940 ep->can_eliminate = 0;
2942 elimination_effects (XEXP (x, 0), mem_mode);
2946 /* Check for setting a register that we know about. */
2947 if (REG_P (SET_DEST (x)))
2949 /* See if this is setting the replacement register for an
2952 If DEST is the hard frame pointer, we do nothing because we
2953 assume that all assignments to the frame pointer are for
2954 non-local gotos and are being done at a time when they are valid
2955 and do not disturb anything else. Some machines want to
2956 eliminate a fake argument pointer (or even a fake frame pointer)
2957 with either the real frame or the stack pointer. Assignments to
2958 the hard frame pointer must not prevent this elimination. */
2960 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2962 if (ep->to_rtx == SET_DEST (x)
2963 && SET_DEST (x) != hard_frame_pointer_rtx)
2965 /* If it is being incremented, adjust the offset. Otherwise,
2966 this elimination can't be done. */
2967 rtx src = SET_SRC (x);
2969 if (GET_CODE (src) == PLUS
2970 && XEXP (src, 0) == SET_DEST (x)
2971 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2972 ep->offset -= INTVAL (XEXP (src, 1));
2974 ep->can_eliminate = 0;
2978 elimination_effects (SET_DEST (x), 0);
2979 elimination_effects (SET_SRC (x), 0);
2983 /* Our only special processing is to pass the mode of the MEM to our
2985 elimination_effects (XEXP (x, 0), GET_MODE (x));
2992 fmt = GET_RTX_FORMAT (code);
2993 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2996 elimination_effects (XEXP (x, i), mem_mode);
2997 else if (*fmt == 'E')
2998 for (j = 0; j < XVECLEN (x, i); j++)
2999 elimination_effects (XVECEXP (x, i, j), mem_mode);
3003 /* Descend through rtx X and verify that no references to eliminable registers
3004 remain. If any do remain, mark the involved register as not
3008 check_eliminable_occurrences (rtx x)
3017 code = GET_CODE (x);
3019 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3021 struct elim_table *ep;
3023 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3024 if (ep->from_rtx == x)
3025 ep->can_eliminate = 0;
3029 fmt = GET_RTX_FORMAT (code);
3030 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3033 check_eliminable_occurrences (XEXP (x, i));
3034 else if (*fmt == 'E')
3037 for (j = 0; j < XVECLEN (x, i); j++)
3038 check_eliminable_occurrences (XVECEXP (x, i, j));
3043 /* Scan INSN and eliminate all eliminable registers in it.
3045 If REPLACE is nonzero, do the replacement destructively. Also
3046 delete the insn as dead it if it is setting an eliminable register.
3048 If REPLACE is zero, do all our allocations in reload_obstack.
3050 If no eliminations were done and this insn doesn't require any elimination
3051 processing (these are not identical conditions: it might be updating sp,
3052 but not referencing fp; this needs to be seen during reload_as_needed so
3053 that the offset between fp and sp can be taken into consideration), zero
3054 is returned. Otherwise, 1 is returned. */
3057 eliminate_regs_in_insn (rtx insn, int replace)
3059 int icode = recog_memoized (insn);
3060 rtx old_body = PATTERN (insn);
3061 int insn_is_asm = asm_noperands (old_body) >= 0;
3062 rtx old_set = single_set (insn);
3066 rtx substed_operand[MAX_RECOG_OPERANDS];
3067 rtx orig_operand[MAX_RECOG_OPERANDS];
3068 struct elim_table *ep;
3069 rtx plus_src, plus_cst_src;
3071 if (! insn_is_asm && icode < 0)
3073 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3074 || GET_CODE (PATTERN (insn)) == CLOBBER
3075 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3076 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3077 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3081 if (old_set != 0 && REG_P (SET_DEST (old_set))
3082 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3084 /* Check for setting an eliminable register. */
3085 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3086 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3088 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3089 /* If this is setting the frame pointer register to the
3090 hardware frame pointer register and this is an elimination
3091 that will be done (tested above), this insn is really
3092 adjusting the frame pointer downward to compensate for
3093 the adjustment done before a nonlocal goto. */
3094 if (ep->from == FRAME_POINTER_REGNUM
3095 && ep->to == HARD_FRAME_POINTER_REGNUM)
3097 rtx base = SET_SRC (old_set);
3098 rtx base_insn = insn;
3099 HOST_WIDE_INT offset = 0;
3101 while (base != ep->to_rtx)
3103 rtx prev_insn, prev_set;
3105 if (GET_CODE (base) == PLUS
3106 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3108 offset += INTVAL (XEXP (base, 1));
3109 base = XEXP (base, 0);
3111 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3112 && (prev_set = single_set (prev_insn)) != 0
3113 && rtx_equal_p (SET_DEST (prev_set), base))
3115 base = SET_SRC (prev_set);
3116 base_insn = prev_insn;
3122 if (base == ep->to_rtx)
3125 = plus_constant (ep->to_rtx, offset - ep->offset);
3127 new_body = old_body;
3130 new_body = copy_insn (old_body);
3131 if (REG_NOTES (insn))
3132 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3134 PATTERN (insn) = new_body;
3135 old_set = single_set (insn);
3137 /* First see if this insn remains valid when we
3138 make the change. If not, keep the INSN_CODE
3139 the same and let reload fit it up. */
3140 validate_change (insn, &SET_SRC (old_set), src, 1);
3141 validate_change (insn, &SET_DEST (old_set),
3143 if (! apply_change_group ())
3145 SET_SRC (old_set) = src;
3146 SET_DEST (old_set) = ep->to_rtx;
3155 /* In this case this insn isn't serving a useful purpose. We
3156 will delete it in reload_as_needed once we know that this
3157 elimination is, in fact, being done.
3159 If REPLACE isn't set, we can't delete this insn, but needn't
3160 process it since it won't be used unless something changes. */
3163 delete_dead_insn (insn);
3171 /* We allow one special case which happens to work on all machines we
3172 currently support: a single set with the source or a REG_EQUAL
3173 note being a PLUS of an eliminable register and a constant. */
3174 plus_src = plus_cst_src = 0;
3175 if (old_set && REG_P (SET_DEST (old_set)))
3177 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3178 plus_src = SET_SRC (old_set);
3179 /* First see if the source is of the form (plus (...) CST). */
3181 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3182 plus_cst_src = plus_src;
3183 else if (REG_P (SET_SRC (old_set))
3186 /* Otherwise, see if we have a REG_EQUAL note of the form
3187 (plus (...) CST). */
3189 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3191 if ((REG_NOTE_KIND (links) == REG_EQUAL
3192 || REG_NOTE_KIND (links) == REG_EQUIV)
3193 && GET_CODE (XEXP (links, 0)) == PLUS
3194 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3196 plus_cst_src = XEXP (links, 0);
3202 /* Check that the first operand of the PLUS is a hard reg or
3203 the lowpart subreg of one. */
3206 rtx reg = XEXP (plus_cst_src, 0);
3207 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3208 reg = SUBREG_REG (reg);
3210 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3216 rtx reg = XEXP (plus_cst_src, 0);
3217 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3219 if (GET_CODE (reg) == SUBREG)
3220 reg = SUBREG_REG (reg);
3222 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3223 if (ep->from_rtx == reg && ep->can_eliminate)
3225 rtx to_rtx = ep->to_rtx;
3226 offset += ep->offset;
3227 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3229 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3230 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3232 /* If we have a nonzero offset, and the source is already
3233 a simple REG, the following transformation would
3234 increase the cost of the insn by replacing a simple REG
3235 with (plus (reg sp) CST). So try only when we already
3236 had a PLUS before. */
3237 if (offset == 0 || plus_src)
3239 rtx new_src = plus_constant (to_rtx, offset);
3241 new_body = old_body;
3244 new_body = copy_insn (old_body);
3245 if (REG_NOTES (insn))
3246 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3248 PATTERN (insn) = new_body;
3249 old_set = single_set (insn);
3251 /* First see if this insn remains valid when we make the
3252 change. If not, try to replace the whole pattern with
3253 a simple set (this may help if the original insn was a
3254 PARALLEL that was only recognized as single_set due to
3255 REG_UNUSED notes). If this isn't valid either, keep
3256 the INSN_CODE the same and let reload fix it up. */
3257 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3259 rtx new_pat = gen_rtx_SET (VOIDmode,
3260 SET_DEST (old_set), new_src);
3262 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3263 SET_SRC (old_set) = new_src;
3270 /* This can't have an effect on elimination offsets, so skip right
3276 /* Determine the effects of this insn on elimination offsets. */
3277 elimination_effects (old_body, 0);
3279 /* Eliminate all eliminable registers occurring in operands that
3280 can be handled by reload. */
3281 extract_insn (insn);
3282 for (i = 0; i < recog_data.n_operands; i++)
3284 orig_operand[i] = recog_data.operand[i];
3285 substed_operand[i] = recog_data.operand[i];
3287 /* For an asm statement, every operand is eliminable. */
3288 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3290 bool is_set_src, in_plus;
3292 /* Check for setting a register that we know about. */
3293 if (recog_data.operand_type[i] != OP_IN
3294 && REG_P (orig_operand[i]))
3296 /* If we are assigning to a register that can be eliminated, it
3297 must be as part of a PARALLEL, since the code above handles
3298 single SETs. We must indicate that we can no longer
3299 eliminate this reg. */
3300 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3302 if (ep->from_rtx == orig_operand[i])
3303 ep->can_eliminate = 0;
3306 /* Companion to the above plus substitution, we can allow
3307 invariants as the source of a plain move. */
3309 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3313 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3314 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3318 = eliminate_regs_1 (recog_data.operand[i], 0,
3319 replace ? insn : NULL_RTX,
3320 is_set_src || in_plus);
3321 if (substed_operand[i] != orig_operand[i])
3323 /* Terminate the search in check_eliminable_occurrences at
3325 *recog_data.operand_loc[i] = 0;
3327 /* If an output operand changed from a REG to a MEM and INSN is an
3328 insn, write a CLOBBER insn. */
3329 if (recog_data.operand_type[i] != OP_IN
3330 && REG_P (orig_operand[i])
3331 && MEM_P (substed_operand[i])
3333 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3338 for (i = 0; i < recog_data.n_dups; i++)
3339 *recog_data.dup_loc[i]
3340 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3342 /* If any eliminable remain, they aren't eliminable anymore. */
3343 check_eliminable_occurrences (old_body);
3345 /* Substitute the operands; the new values are in the substed_operand
3347 for (i = 0; i < recog_data.n_operands; i++)
3348 *recog_data.operand_loc[i] = substed_operand[i];
3349 for (i = 0; i < recog_data.n_dups; i++)
3350 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3352 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3353 re-recognize the insn. We do this in case we had a simple addition
3354 but now can do this as a load-address. This saves an insn in this
3356 If re-recognition fails, the old insn code number will still be used,
3357 and some register operands may have changed into PLUS expressions.
3358 These will be handled by find_reloads by loading them into a register
3363 /* If we aren't replacing things permanently and we changed something,
3364 make another copy to ensure that all the RTL is new. Otherwise
3365 things can go wrong if find_reload swaps commutative operands
3366 and one is inside RTL that has been copied while the other is not. */
3367 new_body = old_body;
3370 new_body = copy_insn (old_body);
3371 if (REG_NOTES (insn))
3372 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3374 PATTERN (insn) = new_body;
3376 /* If we had a move insn but now we don't, rerecognize it. This will
3377 cause spurious re-recognition if the old move had a PARALLEL since
3378 the new one still will, but we can't call single_set without
3379 having put NEW_BODY into the insn and the re-recognition won't
3380 hurt in this rare case. */
3381 /* ??? Why this huge if statement - why don't we just rerecognize the
3385 && ((REG_P (SET_SRC (old_set))
3386 && (GET_CODE (new_body) != SET
3387 || !REG_P (SET_SRC (new_body))))
3388 /* If this was a load from or store to memory, compare
3389 the MEM in recog_data.operand to the one in the insn.
3390 If they are not equal, then rerecognize the insn. */
3392 && ((MEM_P (SET_SRC (old_set))
3393 && SET_SRC (old_set) != recog_data.operand[1])
3394 || (MEM_P (SET_DEST (old_set))
3395 && SET_DEST (old_set) != recog_data.operand[0])))
3396 /* If this was an add insn before, rerecognize. */
3397 || GET_CODE (SET_SRC (old_set)) == PLUS))
3399 int new_icode = recog (PATTERN (insn), insn, 0);
3401 INSN_CODE (insn) = new_icode;
3405 /* Restore the old body. If there were any changes to it, we made a copy
3406 of it while the changes were still in place, so we'll correctly return
3407 a modified insn below. */
3410 /* Restore the old body. */
3411 for (i = 0; i < recog_data.n_operands; i++)
3412 *recog_data.operand_loc[i] = orig_operand[i];
3413 for (i = 0; i < recog_data.n_dups; i++)
3414 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3417 /* Update all elimination pairs to reflect the status after the current
3418 insn. The changes we make were determined by the earlier call to
3419 elimination_effects.
3421 We also detect cases where register elimination cannot be done,
3422 namely, if a register would be both changed and referenced outside a MEM
3423 in the resulting insn since such an insn is often undefined and, even if
3424 not, we cannot know what meaning will be given to it. Note that it is
3425 valid to have a register used in an address in an insn that changes it
3426 (presumably with a pre- or post-increment or decrement).
3428 If anything changes, return nonzero. */
3430 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3432 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3433 ep->can_eliminate = 0;
3435 ep->ref_outside_mem = 0;
3437 if (ep->previous_offset != ep->offset)
3442 /* If we changed something, perform elimination in REG_NOTES. This is
3443 needed even when REPLACE is zero because a REG_DEAD note might refer
3444 to a register that we eliminate and could cause a different number
3445 of spill registers to be needed in the final reload pass than in
3447 if (val && REG_NOTES (insn) != 0)
3449 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3454 /* Loop through all elimination pairs.
3455 Recalculate the number not at initial offset.
3457 Compute the maximum offset (minimum offset if the stack does not
3458 grow downward) for each elimination pair. */
3461 update_eliminable_offsets (void)
3463 struct elim_table *ep;
3465 num_not_at_initial_offset = 0;
3466 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3468 ep->previous_offset = ep->offset;
3469 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3470 num_not_at_initial_offset++;
3474 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3475 replacement we currently believe is valid, mark it as not eliminable if X
3476 modifies DEST in any way other than by adding a constant integer to it.
3478 If DEST is the frame pointer, we do nothing because we assume that
3479 all assignments to the hard frame pointer are nonlocal gotos and are being
3480 done at a time when they are valid and do not disturb anything else.
3481 Some machines want to eliminate a fake argument pointer with either the
3482 frame or stack pointer. Assignments to the hard frame pointer must not
3483 prevent this elimination.
3485 Called via note_stores from reload before starting its passes to scan
3486 the insns of the function. */
3489 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3493 /* A SUBREG of a hard register here is just changing its mode. We should
3494 not see a SUBREG of an eliminable hard register, but check just in
3496 if (GET_CODE (dest) == SUBREG)
3497 dest = SUBREG_REG (dest);
3499 if (dest == hard_frame_pointer_rtx)
3502 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3503 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3504 && (GET_CODE (x) != SET
3505 || GET_CODE (SET_SRC (x)) != PLUS
3506 || XEXP (SET_SRC (x), 0) != dest
3507 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3509 reg_eliminate[i].can_eliminate_previous
3510 = reg_eliminate[i].can_eliminate = 0;
3515 /* Verify that the initial elimination offsets did not change since the
3516 last call to set_initial_elim_offsets. This is used to catch cases
3517 where something illegal happened during reload_as_needed that could
3518 cause incorrect code to be generated if we did not check for it. */
3521 verify_initial_elim_offsets (void)
3525 if (!num_eliminable)
3528 #ifdef ELIMINABLE_REGS
3530 struct elim_table *ep;
3532 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3534 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3535 if (t != ep->initial_offset)
3540 INITIAL_FRAME_POINTER_OFFSET (t);
3541 if (t != reg_eliminate[0].initial_offset)
3548 /* Reset all offsets on eliminable registers to their initial values. */
3551 set_initial_elim_offsets (void)
3553 struct elim_table *ep = reg_eliminate;
3555 #ifdef ELIMINABLE_REGS
3556 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3558 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3559 ep->previous_offset = ep->offset = ep->initial_offset;
3562 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3563 ep->previous_offset = ep->offset = ep->initial_offset;
3566 num_not_at_initial_offset = 0;
3569 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3572 set_initial_eh_label_offset (rtx label)
3574 set_label_offsets (label, NULL_RTX, 1);
3577 /* Initialize the known label offsets.
3578 Set a known offset for each forced label to be at the initial offset
3579 of each elimination. We do this because we assume that all
3580 computed jumps occur from a location where each elimination is
3581 at its initial offset.
3582 For all other labels, show that we don't know the offsets. */
3585 set_initial_label_offsets (void)
3588 memset (offsets_known_at, 0, num_labels);
3590 for (x = forced_labels; x; x = XEXP (x, 1))
3592 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3594 for_each_eh_label (set_initial_eh_label_offset);
3597 /* Set all elimination offsets to the known values for the code label given
3601 set_offsets_for_label (rtx insn)
3604 int label_nr = CODE_LABEL_NUMBER (insn);
3605 struct elim_table *ep;
3607 num_not_at_initial_offset = 0;
3608 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3610 ep->offset = ep->previous_offset
3611 = offsets_at[label_nr - first_label_num][i];
3612 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3613 num_not_at_initial_offset++;
3617 /* See if anything that happened changes which eliminations are valid.
3618 For example, on the SPARC, whether or not the frame pointer can
3619 be eliminated can depend on what registers have been used. We need
3620 not check some conditions again (such as flag_omit_frame_pointer)
3621 since they can't have changed. */
3624 update_eliminables (HARD_REG_SET *pset)
3626 int previous_frame_pointer_needed = frame_pointer_needed;
3627 struct elim_table *ep;
3629 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3630 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3631 #ifdef ELIMINABLE_REGS
3632 || ! CAN_ELIMINATE (ep->from, ep->to)
3635 ep->can_eliminate = 0;
3637 /* Look for the case where we have discovered that we can't replace
3638 register A with register B and that means that we will now be
3639 trying to replace register A with register C. This means we can
3640 no longer replace register C with register B and we need to disable
3641 such an elimination, if it exists. This occurs often with A == ap,
3642 B == sp, and C == fp. */
3644 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3646 struct elim_table *op;
3649 if (! ep->can_eliminate && ep->can_eliminate_previous)
3651 /* Find the current elimination for ep->from, if there is a
3653 for (op = reg_eliminate;
3654 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3655 if (op->from == ep->from && op->can_eliminate)
3661 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3663 for (op = reg_eliminate;
3664 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3665 if (op->from == new_to && op->to == ep->to)
3666 op->can_eliminate = 0;
3670 /* See if any registers that we thought we could eliminate the previous
3671 time are no longer eliminable. If so, something has changed and we
3672 must spill the register. Also, recompute the number of eliminable
3673 registers and see if the frame pointer is needed; it is if there is
3674 no elimination of the frame pointer that we can perform. */
3676 frame_pointer_needed = 1;
3677 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3679 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3680 && ep->to != HARD_FRAME_POINTER_REGNUM)
3681 frame_pointer_needed = 0;
3683 if (! ep->can_eliminate && ep->can_eliminate_previous)
3685 ep->can_eliminate_previous = 0;
3686 SET_HARD_REG_BIT (*pset, ep->from);
3691 /* If we didn't need a frame pointer last time, but we do now, spill
3692 the hard frame pointer. */
3693 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3694 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3697 /* Return true if X is used as the target register of an elimination. */
3700 elimination_target_reg_p (rtx x)
3702 struct elim_table *ep;
3704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3705 if (ep->to_rtx == x && ep->can_eliminate)
3711 /* Initialize the table of registers to eliminate. */
3714 init_elim_table (void)
3716 struct elim_table *ep;
3717 #ifdef ELIMINABLE_REGS
3718 const struct elim_table_1 *ep1;
3722 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3724 /* Does this function require a frame pointer? */
3726 frame_pointer_needed = (! flag_omit_frame_pointer
3727 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3728 and restore sp for alloca. So we can't eliminate
3729 the frame pointer in that case. At some point,
3730 we should improve this by emitting the
3731 sp-adjusting insns for this case. */
3732 || (current_function_calls_alloca
3733 && EXIT_IGNORE_STACK)
3734 || current_function_accesses_prior_frames
3735 || FRAME_POINTER_REQUIRED);
3739 #ifdef ELIMINABLE_REGS
3740 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3741 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3743 ep->from = ep1->from;
3745 ep->can_eliminate = ep->can_eliminate_previous
3746 = (CAN_ELIMINATE (ep->from, ep->to)
3747 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3750 reg_eliminate[0].from = reg_eliminate_1[0].from;
3751 reg_eliminate[0].to = reg_eliminate_1[0].to;
3752 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3753 = ! frame_pointer_needed;
3756 /* Count the number of eliminable registers and build the FROM and TO
3757 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3758 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3759 We depend on this. */
3760 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3762 num_eliminable += ep->can_eliminate;
3763 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3764 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3768 /* Kick all pseudos out of hard register REGNO.
3770 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3771 because we found we can't eliminate some register. In the case, no pseudos
3772 are allowed to be in the register, even if they are only in a block that
3773 doesn't require spill registers, unlike the case when we are spilling this
3774 hard reg to produce another spill register.
3776 Return nonzero if any pseudos needed to be kicked out. */
3779 spill_hard_reg (unsigned int regno, int cant_eliminate)
3785 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3786 df_set_regs_ever_live (regno, true);
3789 /* Spill every pseudo reg that was allocated to this reg
3790 or to something that overlaps this reg. */
3792 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3793 if (reg_renumber[i] >= 0
3794 && (unsigned int) reg_renumber[i] <= regno
3795 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3796 SET_REGNO_REG_SET (&spilled_pseudos, i);
3799 /* After find_reload_regs has been run for all insn that need reloads,
3800 and/or spill_hard_regs was called, this function is used to actually
3801 spill pseudo registers and try to reallocate them. It also sets up the
3802 spill_regs array for use by choose_reload_regs. */
3805 finish_spills (int global)
3807 struct insn_chain *chain;
3808 int something_changed = 0;
3810 reg_set_iterator rsi;
3812 /* Build the spill_regs array for the function. */
3813 /* If there are some registers still to eliminate and one of the spill regs
3814 wasn't ever used before, additional stack space may have to be
3815 allocated to store this register. Thus, we may have changed the offset
3816 between the stack and frame pointers, so mark that something has changed.
3818 One might think that we need only set VAL to 1 if this is a call-used
3819 register. However, the set of registers that must be saved by the
3820 prologue is not identical to the call-used set. For example, the
3821 register used by the call insn for the return PC is a call-used register,
3822 but must be saved by the prologue. */
3825 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3826 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3828 spill_reg_order[i] = n_spills;
3829 spill_regs[n_spills++] = i;
3830 if (num_eliminable && ! df_regs_ever_live_p (i))
3831 something_changed = 1;
3832 df_set_regs_ever_live (i, true);
3835 spill_reg_order[i] = -1;
3837 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3839 /* Record the current hard register the pseudo is allocated to in
3840 pseudo_previous_regs so we avoid reallocating it to the same
3841 hard reg in a later pass. */
3842 gcc_assert (reg_renumber[i] >= 0);
3844 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3845 /* Mark it as no longer having a hard register home. */
3846 reg_renumber[i] = -1;
3847 /* We will need to scan everything again. */
3848 something_changed = 1;
3851 /* Retry global register allocation if possible. */
3854 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3855 /* For every insn that needs reloads, set the registers used as spill
3856 regs in pseudo_forbidden_regs for every pseudo live across the
3858 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3860 EXECUTE_IF_SET_IN_REG_SET
3861 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3863 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3864 chain->used_spill_regs);
3866 EXECUTE_IF_SET_IN_REG_SET
3867 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3869 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3870 chain->used_spill_regs);
3874 /* Retry allocating the spilled pseudos. For each reg, merge the
3875 various reg sets that indicate which hard regs can't be used,
3876 and call retry_global_alloc.
3877 We change spill_pseudos here to only contain pseudos that did not
3878 get a new hard register. */
3879 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3880 if (reg_old_renumber[i] != reg_renumber[i])
3882 HARD_REG_SET forbidden;
3883 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3884 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3885 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3886 retry_global_alloc (i, forbidden);
3887 if (reg_renumber[i] >= 0)
3888 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3892 /* Fix up the register information in the insn chain.
3893 This involves deleting those of the spilled pseudos which did not get
3894 a new hard register home from the live_{before,after} sets. */
3895 for (chain = reload_insn_chain; chain; chain = chain->next)
3897 HARD_REG_SET used_by_pseudos;
3898 HARD_REG_SET used_by_pseudos2;
3900 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3901 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3903 /* Mark any unallocated hard regs as available for spills. That
3904 makes inheritance work somewhat better. */
3905 if (chain->need_reload)
3907 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3908 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3909 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3911 /* Save the old value for the sanity test below. */
3912 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3914 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3915 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3916 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3917 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3919 /* Make sure we only enlarge the set. */
3920 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3921 chain->used_spill_regs));
3925 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3926 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3928 int regno = reg_renumber[i];
3929 if (reg_old_renumber[i] == regno)
3932 alter_reg (i, reg_old_renumber[i]);
3933 reg_old_renumber[i] = regno;
3937 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3939 fprintf (dump_file, " Register %d now in %d.\n\n",
3940 i, reg_renumber[i]);
3944 return something_changed;
3947 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3950 scan_paradoxical_subregs (rtx x)
3954 enum rtx_code code = GET_CODE (x);
3965 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3973 if (REG_P (SUBREG_REG (x))
3974 && (GET_MODE_SIZE (GET_MODE (x))
3975 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3977 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3978 = GET_MODE_SIZE (GET_MODE (x));
3979 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3987 fmt = GET_RTX_FORMAT (code);
3988 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3991 scan_paradoxical_subregs (XEXP (x, i));
3992 else if (fmt[i] == 'E')
3995 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3996 scan_paradoxical_subregs (XVECEXP (x, i, j));
4001 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4002 examine all of the reload insns between PREV and NEXT exclusive, and
4003 annotate all that may trap. */
4006 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4008 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4009 unsigned int trap_count;
4015 if (may_trap_p (PATTERN (insn)))
4019 remove_note (insn, note);
4023 for (i = NEXT_INSN (prev); i && (i != next); i = NEXT_INSN (i))
4024 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4028 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4032 /* Reload pseudo-registers into hard regs around each insn as needed.
4033 Additional register load insns are output before the insn that needs it
4034 and perhaps store insns after insns that modify the reloaded pseudo reg.
4036 reg_last_reload_reg and reg_reloaded_contents keep track of
4037 which registers are already available in reload registers.
4038 We update these for the reloads that we perform,
4039 as the insns are scanned. */
4042 reload_as_needed (int live_known)
4044 struct insn_chain *chain;
4045 #if defined (AUTO_INC_DEC)
4050 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4051 memset (spill_reg_store, 0, sizeof spill_reg_store);
4052 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4053 INIT_REG_SET (®_has_output_reload);
4054 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4055 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4057 set_initial_elim_offsets ();
4059 for (chain = reload_insn_chain; chain; chain = chain->next)
4062 rtx insn = chain->insn;
4063 rtx old_next = NEXT_INSN (insn);
4065 /* If we pass a label, copy the offsets from the label information
4066 into the current offsets of each elimination. */
4068 set_offsets_for_label (insn);
4070 else if (INSN_P (insn))
4072 regset_head regs_to_forget;
4073 INIT_REG_SET (®s_to_forget);
4074 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4076 /* If this is a USE and CLOBBER of a MEM, ensure that any
4077 references to eliminable registers have been removed. */
4079 if ((GET_CODE (PATTERN (insn)) == USE
4080 || GET_CODE (PATTERN (insn)) == CLOBBER)
4081 && MEM_P (XEXP (PATTERN (insn), 0)))
4082 XEXP (XEXP (PATTERN (insn), 0), 0)
4083 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4084 GET_MODE (XEXP (PATTERN (insn), 0)),
4087 /* If we need to do register elimination processing, do so.
4088 This might delete the insn, in which case we are done. */
4089 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4091 eliminate_regs_in_insn (insn, 1);
4094 update_eliminable_offsets ();
4095 CLEAR_REG_SET (®s_to_forget);
4100 /* If need_elim is nonzero but need_reload is zero, one might think
4101 that we could simply set n_reloads to 0. However, find_reloads
4102 could have done some manipulation of the insn (such as swapping
4103 commutative operands), and these manipulations are lost during
4104 the first pass for every insn that needs register elimination.
4105 So the actions of find_reloads must be redone here. */
4107 if (! chain->need_elim && ! chain->need_reload
4108 && ! chain->need_operand_change)
4110 /* First find the pseudo regs that must be reloaded for this insn.
4111 This info is returned in the tables reload_... (see reload.h).
4112 Also modify the body of INSN by substituting RELOAD
4113 rtx's for those pseudo regs. */
4116 CLEAR_REG_SET (®_has_output_reload);
4117 CLEAR_HARD_REG_SET (reg_is_output_reload);
4119 find_reloads (insn, 1, spill_indirect_levels, live_known,
4125 rtx next = NEXT_INSN (insn);
4128 prev = PREV_INSN (insn);
4130 /* Now compute which reload regs to reload them into. Perhaps
4131 reusing reload regs from previous insns, or else output
4132 load insns to reload them. Maybe output store insns too.
4133 Record the choices of reload reg in reload_reg_rtx. */
4134 choose_reload_regs (chain);
4136 /* Merge any reloads that we didn't combine for fear of
4137 increasing the number of spill registers needed but now
4138 discover can be safely merged. */
4139 if (SMALL_REGISTER_CLASSES)
4140 merge_assigned_reloads (insn);
4142 /* Generate the insns to reload operands into or out of
4143 their reload regs. */
4144 emit_reload_insns (chain);
4146 /* Substitute the chosen reload regs from reload_reg_rtx
4147 into the insn's body (or perhaps into the bodies of other
4148 load and store insn that we just made for reloading
4149 and that we moved the structure into). */
4150 subst_reloads (insn);
4152 /* Adjust the exception region notes for loads and stores. */
4153 if (flag_non_call_exceptions && !CALL_P (insn))
4154 fixup_eh_region_note (insn, prev, next);
4156 /* If this was an ASM, make sure that all the reload insns
4157 we have generated are valid. If not, give an error
4159 if (asm_noperands (PATTERN (insn)) >= 0)
4160 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4161 if (p != insn && INSN_P (p)
4162 && GET_CODE (PATTERN (p)) != USE
4163 && (recog_memoized (p) < 0
4164 || (extract_insn (p), ! constrain_operands (1))))
4166 error_for_asm (insn,
4167 "%<asm%> operand requires "
4168 "impossible reload");
4173 if (num_eliminable && chain->need_elim)
4174 update_eliminable_offsets ();
4176 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4177 is no longer validly lying around to save a future reload.
4178 Note that this does not detect pseudos that were reloaded
4179 for this insn in order to be stored in
4180 (obeying register constraints). That is correct; such reload
4181 registers ARE still valid. */
4182 forget_marked_reloads (®s_to_forget);
4183 CLEAR_REG_SET (®s_to_forget);
4185 /* There may have been CLOBBER insns placed after INSN. So scan
4186 between INSN and NEXT and use them to forget old reloads. */
4187 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4188 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4189 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4192 /* Likewise for regs altered by auto-increment in this insn.
4193 REG_INC notes have been changed by reloading:
4194 find_reloads_address_1 records substitutions for them,
4195 which have been performed by subst_reloads above. */
4196 for (i = n_reloads - 1; i >= 0; i--)
4198 rtx in_reg = rld[i].in_reg;
4201 enum rtx_code code = GET_CODE (in_reg);
4202 /* PRE_INC / PRE_DEC will have the reload register ending up
4203 with the same value as the stack slot, but that doesn't
4204 hold true for POST_INC / POST_DEC. Either we have to
4205 convert the memory access to a true POST_INC / POST_DEC,
4206 or we can't use the reload register for inheritance. */
4207 if ((code == POST_INC || code == POST_DEC)
4208 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4209 REGNO (rld[i].reg_rtx))
4210 /* Make sure it is the inc/dec pseudo, and not
4211 some other (e.g. output operand) pseudo. */
4212 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4213 == REGNO (XEXP (in_reg, 0))))
4216 rtx reload_reg = rld[i].reg_rtx;
4217 enum machine_mode mode = GET_MODE (reload_reg);
4221 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4223 /* We really want to ignore REG_INC notes here, so
4224 use PATTERN (p) as argument to reg_set_p . */
4225 if (reg_set_p (reload_reg, PATTERN (p)))
4227 n = count_occurrences (PATTERN (p), reload_reg, 0);
4232 n = validate_replace_rtx (reload_reg,
4233 gen_rtx_fmt_e (code,
4238 /* We must also verify that the constraints
4239 are met after the replacement. */
4242 n = constrain_operands (1);
4246 /* If the constraints were not met, then
4247 undo the replacement. */
4250 validate_replace_rtx (gen_rtx_fmt_e (code,
4263 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4265 /* Mark this as having an output reload so that the
4266 REG_INC processing code below won't invalidate
4267 the reload for inheritance. */
4268 SET_HARD_REG_BIT (reg_is_output_reload,
4269 REGNO (reload_reg));
4270 SET_REGNO_REG_SET (®_has_output_reload,
4271 REGNO (XEXP (in_reg, 0)));
4274 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4277 else if ((code == PRE_INC || code == PRE_DEC)
4278 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4279 REGNO (rld[i].reg_rtx))
4280 /* Make sure it is the inc/dec pseudo, and not
4281 some other (e.g. output operand) pseudo. */
4282 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4283 == REGNO (XEXP (in_reg, 0))))
4285 SET_HARD_REG_BIT (reg_is_output_reload,
4286 REGNO (rld[i].reg_rtx));
4287 SET_REGNO_REG_SET (®_has_output_reload,
4288 REGNO (XEXP (in_reg, 0)));
4292 /* If a pseudo that got a hard register is auto-incremented,
4293 we must purge records of copying it into pseudos without
4295 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4296 if (REG_NOTE_KIND (x) == REG_INC)
4298 /* See if this pseudo reg was reloaded in this insn.
4299 If so, its last-reload info is still valid
4300 because it is based on this insn's reload. */
4301 for (i = 0; i < n_reloads; i++)
4302 if (rld[i].out == XEXP (x, 0))
4306 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4310 /* A reload reg's contents are unknown after a label. */
4312 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4314 /* Don't assume a reload reg is still good after a call insn
4315 if it is a call-used reg, or if it contains a value that will
4316 be partially clobbered by the call. */
4317 else if (CALL_P (insn))
4319 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4320 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4325 free (reg_last_reload_reg);
4326 CLEAR_REG_SET (®_has_output_reload);
4329 /* Discard all record of any value reloaded from X,
4330 or reloaded in X from someplace else;
4331 unless X is an output reload reg of the current insn.
4333 X may be a hard reg (the reload reg)
4334 or it may be a pseudo reg that was reloaded from.
4336 When DATA is non-NULL just mark the registers in regset
4337 to be forgotten later. */
4340 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4345 regset regs = (regset) data;
4347 /* note_stores does give us subregs of hard regs,
4348 subreg_regno_offset requires a hard reg. */
4349 while (GET_CODE (x) == SUBREG)
4351 /* We ignore the subreg offset when calculating the regno,
4352 because we are using the entire underlying hard register
4362 if (regno >= FIRST_PSEUDO_REGISTER)
4368 nr = hard_regno_nregs[regno][GET_MODE (x)];
4369 /* Storing into a spilled-reg invalidates its contents.
4370 This can happen if a block-local pseudo is allocated to that reg
4371 and it wasn't spilled because this block's total need is 0.
4372 Then some insn might have an optional reload and use this reg. */
4374 for (i = 0; i < nr; i++)
4375 /* But don't do this if the reg actually serves as an output
4376 reload reg in the current instruction. */
4378 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4380 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4381 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4382 spill_reg_store[regno + i] = 0;
4388 SET_REGNO_REG_SET (regs, regno + nr);
4391 /* Since value of X has changed,
4392 forget any value previously copied from it. */
4395 /* But don't forget a copy if this is the output reload
4396 that establishes the copy's validity. */
4398 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4399 reg_last_reload_reg[regno + nr] = 0;
4403 /* Forget the reloads marked in regset by previous function. */
4405 forget_marked_reloads (regset regs)
4408 reg_set_iterator rsi;
4409 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4411 if (reg < FIRST_PSEUDO_REGISTER
4412 /* But don't do this if the reg actually serves as an output
4413 reload reg in the current instruction. */
4415 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4417 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4418 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4419 spill_reg_store[reg] = 0;
4422 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4423 reg_last_reload_reg[reg] = 0;
4427 /* The following HARD_REG_SETs indicate when each hard register is
4428 used for a reload of various parts of the current insn. */
4430 /* If reg is unavailable for all reloads. */
4431 static HARD_REG_SET reload_reg_unavailable;
4432 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4433 static HARD_REG_SET reload_reg_used;
4434 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4435 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4436 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4437 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4438 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4439 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4440 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4441 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4442 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4443 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4444 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4445 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4446 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4447 static HARD_REG_SET reload_reg_used_in_op_addr;
4448 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4449 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4450 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4451 static HARD_REG_SET reload_reg_used_in_insn;
4452 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4453 static HARD_REG_SET reload_reg_used_in_other_addr;
4455 /* If reg is in use as a reload reg for any sort of reload. */
4456 static HARD_REG_SET reload_reg_used_at_all;
4458 /* If reg is use as an inherited reload. We just mark the first register
4460 static HARD_REG_SET reload_reg_used_for_inherit;
4462 /* Records which hard regs are used in any way, either as explicit use or
4463 by being allocated to a pseudo during any point of the current insn. */
4464 static HARD_REG_SET reg_used_in_insn;
4466 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4467 TYPE. MODE is used to indicate how many consecutive regs are
4471 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4472 enum machine_mode mode)
4474 unsigned int nregs = hard_regno_nregs[regno][mode];
4477 for (i = regno; i < nregs + regno; i++)
4482 SET_HARD_REG_BIT (reload_reg_used, i);
4485 case RELOAD_FOR_INPUT_ADDRESS:
4486 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4489 case RELOAD_FOR_INPADDR_ADDRESS:
4490 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4493 case RELOAD_FOR_OUTPUT_ADDRESS:
4494 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4497 case RELOAD_FOR_OUTADDR_ADDRESS:
4498 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4501 case RELOAD_FOR_OPERAND_ADDRESS:
4502 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4505 case RELOAD_FOR_OPADDR_ADDR:
4506 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4509 case RELOAD_FOR_OTHER_ADDRESS:
4510 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4513 case RELOAD_FOR_INPUT:
4514 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4517 case RELOAD_FOR_OUTPUT:
4518 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4521 case RELOAD_FOR_INSN:
4522 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4526 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4530 /* Similarly, but show REGNO is no longer in use for a reload. */
4533 clear_reload_reg_in_use (unsigned int regno, int opnum,
4534 enum reload_type type, enum machine_mode mode)
4536 unsigned int nregs = hard_regno_nregs[regno][mode];
4537 unsigned int start_regno, end_regno, r;
4539 /* A complication is that for some reload types, inheritance might
4540 allow multiple reloads of the same types to share a reload register.
4541 We set check_opnum if we have to check only reloads with the same
4542 operand number, and check_any if we have to check all reloads. */
4543 int check_opnum = 0;
4545 HARD_REG_SET *used_in_set;
4550 used_in_set = &reload_reg_used;
4553 case RELOAD_FOR_INPUT_ADDRESS:
4554 used_in_set = &reload_reg_used_in_input_addr[opnum];
4557 case RELOAD_FOR_INPADDR_ADDRESS:
4559 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4562 case RELOAD_FOR_OUTPUT_ADDRESS:
4563 used_in_set = &reload_reg_used_in_output_addr[opnum];
4566 case RELOAD_FOR_OUTADDR_ADDRESS:
4568 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4571 case RELOAD_FOR_OPERAND_ADDRESS:
4572 used_in_set = &reload_reg_used_in_op_addr;
4575 case RELOAD_FOR_OPADDR_ADDR:
4577 used_in_set = &reload_reg_used_in_op_addr_reload;
4580 case RELOAD_FOR_OTHER_ADDRESS:
4581 used_in_set = &reload_reg_used_in_other_addr;
4585 case RELOAD_FOR_INPUT:
4586 used_in_set = &reload_reg_used_in_input[opnum];
4589 case RELOAD_FOR_OUTPUT:
4590 used_in_set = &reload_reg_used_in_output[opnum];
4593 case RELOAD_FOR_INSN:
4594 used_in_set = &reload_reg_used_in_insn;
4599 /* We resolve conflicts with remaining reloads of the same type by
4600 excluding the intervals of reload registers by them from the
4601 interval of freed reload registers. Since we only keep track of
4602 one set of interval bounds, we might have to exclude somewhat
4603 more than what would be necessary if we used a HARD_REG_SET here.
4604 But this should only happen very infrequently, so there should
4605 be no reason to worry about it. */
4607 start_regno = regno;
4608 end_regno = regno + nregs;
4609 if (check_opnum || check_any)
4611 for (i = n_reloads - 1; i >= 0; i--)
4613 if (rld[i].when_needed == type
4614 && (check_any || rld[i].opnum == opnum)
4617 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4618 unsigned int conflict_end
4619 = end_hard_regno (rld[i].mode, conflict_start);
4621 /* If there is an overlap with the first to-be-freed register,
4622 adjust the interval start. */
4623 if (conflict_start <= start_regno && conflict_end > start_regno)
4624 start_regno = conflict_end;
4625 /* Otherwise, if there is a conflict with one of the other
4626 to-be-freed registers, adjust the interval end. */
4627 if (conflict_start > start_regno && conflict_start < end_regno)
4628 end_regno = conflict_start;
4633 for (r = start_regno; r < end_regno; r++)
4634 CLEAR_HARD_REG_BIT (*used_in_set, r);
4637 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4638 specified by OPNUM and TYPE. */
4641 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4645 /* In use for a RELOAD_OTHER means it's not available for anything. */
4646 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4647 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4653 /* In use for anything means we can't use it for RELOAD_OTHER. */
4654 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4655 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4656 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4657 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4660 for (i = 0; i < reload_n_operands; i++)
4661 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4663 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4664 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4665 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4666 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4671 case RELOAD_FOR_INPUT:
4672 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4673 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4676 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4679 /* If it is used for some other input, can't use it. */
4680 for (i = 0; i < reload_n_operands; i++)
4681 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4684 /* If it is used in a later operand's address, can't use it. */
4685 for (i = opnum + 1; i < reload_n_operands; i++)
4686 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4692 case RELOAD_FOR_INPUT_ADDRESS:
4693 /* Can't use a register if it is used for an input address for this
4694 operand or used as an input in an earlier one. */
4695 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4696 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4699 for (i = 0; i < opnum; i++)
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4705 case RELOAD_FOR_INPADDR_ADDRESS:
4706 /* Can't use a register if it is used for an input address
4707 for this operand or used as an input in an earlier
4709 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4712 for (i = 0; i < opnum; i++)
4713 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4718 case RELOAD_FOR_OUTPUT_ADDRESS:
4719 /* Can't use a register if it is used for an output address for this
4720 operand or used as an output in this or a later operand. Note
4721 that multiple output operands are emitted in reverse order, so
4722 the conflicting ones are those with lower indices. */
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4726 for (i = 0; i <= opnum; i++)
4727 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4732 case RELOAD_FOR_OUTADDR_ADDRESS:
4733 /* Can't use a register if it is used for an output address
4734 for this operand or used as an output in this or a
4735 later operand. Note that multiple output operands are
4736 emitted in reverse order, so the conflicting ones are
4737 those with lower indices. */
4738 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4741 for (i = 0; i <= opnum; i++)
4742 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4747 case RELOAD_FOR_OPERAND_ADDRESS:
4748 for (i = 0; i < reload_n_operands; i++)
4749 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4752 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4753 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4755 case RELOAD_FOR_OPADDR_ADDR:
4756 for (i = 0; i < reload_n_operands; i++)
4757 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4760 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4762 case RELOAD_FOR_OUTPUT:
4763 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4764 outputs, or an operand address for this or an earlier output.
4765 Note that multiple output operands are emitted in reverse order,
4766 so the conflicting ones are those with higher indices. */
4767 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4770 for (i = 0; i < reload_n_operands; i++)
4771 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4774 for (i = opnum; i < reload_n_operands; i++)
4775 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4776 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4781 case RELOAD_FOR_INSN:
4782 for (i = 0; i < reload_n_operands; i++)
4783 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4784 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4787 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4788 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4790 case RELOAD_FOR_OTHER_ADDRESS:
4791 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4798 /* Return 1 if the value in reload reg REGNO, as used by a reload
4799 needed for the part of the insn specified by OPNUM and TYPE,
4800 is still available in REGNO at the end of the insn.
4802 We can assume that the reload reg was already tested for availability
4803 at the time it is needed, and we should not check this again,
4804 in case the reg has already been marked in use. */
4807 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4814 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4815 its value must reach the end. */
4818 /* If this use is for part of the insn,
4819 its value reaches if no subsequent part uses the same register.
4820 Just like the above function, don't try to do this with lots
4823 case RELOAD_FOR_OTHER_ADDRESS:
4824 /* Here we check for everything else, since these don't conflict
4825 with anything else and everything comes later. */
4827 for (i = 0; i < reload_n_operands; i++)
4828 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4829 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4830 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4831 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4833 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4836 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4837 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4838 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4839 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4841 case RELOAD_FOR_INPUT_ADDRESS:
4842 case RELOAD_FOR_INPADDR_ADDRESS:
4843 /* Similar, except that we check only for this and subsequent inputs
4844 and the address of only subsequent inputs and we do not need
4845 to check for RELOAD_OTHER objects since they are known not to
4848 for (i = opnum; i < reload_n_operands; i++)
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4852 for (i = opnum + 1; i < reload_n_operands; i++)
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4854 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4857 for (i = 0; i < reload_n_operands; i++)
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4859 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4860 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4863 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4866 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4867 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4868 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4870 case RELOAD_FOR_INPUT:
4871 /* Similar to input address, except we start at the next operand for
4872 both input and input address and we do not check for
4873 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4876 for (i = opnum + 1; i < reload_n_operands; i++)
4877 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4878 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4879 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4882 /* ... fall through ... */
4884 case RELOAD_FOR_OPERAND_ADDRESS:
4885 /* Check outputs and their addresses. */
4887 for (i = 0; i < reload_n_operands; i++)
4888 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4890 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4893 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4895 case RELOAD_FOR_OPADDR_ADDR:
4896 for (i = 0; i < reload_n_operands; i++)
4897 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4898 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4899 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4902 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4903 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4904 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4906 case RELOAD_FOR_INSN:
4907 /* These conflict with other outputs with RELOAD_OTHER. So
4908 we need only check for output addresses. */
4910 opnum = reload_n_operands;
4912 /* ... fall through ... */
4914 case RELOAD_FOR_OUTPUT:
4915 case RELOAD_FOR_OUTPUT_ADDRESS:
4916 case RELOAD_FOR_OUTADDR_ADDRESS:
4917 /* We already know these can't conflict with a later output. So the
4918 only thing to check are later output addresses.
4919 Note that multiple output operands are emitted in reverse order,
4920 so the conflicting ones are those with lower indices. */
4921 for (i = 0; i < opnum; i++)
4922 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4923 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4934 /* Returns whether R1 and R2 are uniquely chained: the value of one
4935 is used by the other, and that value is not used by any other
4936 reload for this insn. This is used to partially undo the decision
4937 made in find_reloads when in the case of multiple
4938 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4939 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4940 reloads. This code tries to avoid the conflict created by that
4941 change. It might be cleaner to explicitly keep track of which
4942 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4943 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4944 this after the fact. */
4946 reloads_unique_chain_p (int r1, int r2)
4950 /* We only check input reloads. */
4951 if (! rld[r1].in || ! rld[r2].in)
4954 /* Avoid anything with output reloads. */
4955 if (rld[r1].out || rld[r2].out)
4958 /* "chained" means one reload is a component of the other reload,
4959 not the same as the other reload. */
4960 if (rld[r1].opnum != rld[r2].opnum
4961 || rtx_equal_p (rld[r1].in, rld[r2].in)
4962 || rld[r1].optional || rld[r2].optional
4963 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4964 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4967 for (i = 0; i < n_reloads; i ++)
4968 /* Look for input reloads that aren't our two */
4969 if (i != r1 && i != r2 && rld[i].in)
4971 /* If our reload is mentioned at all, it isn't a simple chain. */
4972 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4978 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4981 This function uses the same algorithm as reload_reg_free_p above. */
4984 reloads_conflict (int r1, int r2)
4986 enum reload_type r1_type = rld[r1].when_needed;
4987 enum reload_type r2_type = rld[r2].when_needed;
4988 int r1_opnum = rld[r1].opnum;
4989 int r2_opnum = rld[r2].opnum;
4991 /* RELOAD_OTHER conflicts with everything. */
4992 if (r2_type == RELOAD_OTHER)
4995 /* Otherwise, check conflicts differently for each type. */
4999 case RELOAD_FOR_INPUT:
5000 return (r2_type == RELOAD_FOR_INSN
5001 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5002 || r2_type == RELOAD_FOR_OPADDR_ADDR
5003 || r2_type == RELOAD_FOR_INPUT
5004 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5005 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5006 && r2_opnum > r1_opnum));
5008 case RELOAD_FOR_INPUT_ADDRESS:
5009 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5010 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5012 case RELOAD_FOR_INPADDR_ADDRESS:
5013 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5014 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5016 case RELOAD_FOR_OUTPUT_ADDRESS:
5017 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5018 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5020 case RELOAD_FOR_OUTADDR_ADDRESS:
5021 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5022 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5024 case RELOAD_FOR_OPERAND_ADDRESS:
5025 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5026 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5027 && !reloads_unique_chain_p (r1, r2)));
5029 case RELOAD_FOR_OPADDR_ADDR:
5030 return (r2_type == RELOAD_FOR_INPUT
5031 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5033 case RELOAD_FOR_OUTPUT:
5034 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5035 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5036 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5037 && r2_opnum >= r1_opnum));
5039 case RELOAD_FOR_INSN:
5040 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5041 || r2_type == RELOAD_FOR_INSN
5042 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5044 case RELOAD_FOR_OTHER_ADDRESS:
5045 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5055 /* Indexed by reload number, 1 if incoming value
5056 inherited from previous insns. */
5057 static char reload_inherited[MAX_RELOADS];
5059 /* For an inherited reload, this is the insn the reload was inherited from,
5060 if we know it. Otherwise, this is 0. */
5061 static rtx reload_inheritance_insn[MAX_RELOADS];
5063 /* If nonzero, this is a place to get the value of the reload,
5064 rather than using reload_in. */
5065 static rtx reload_override_in[MAX_RELOADS];
5067 /* For each reload, the hard register number of the register used,
5068 or -1 if we did not need a register for this reload. */
5069 static int reload_spill_index[MAX_RELOADS];
5071 /* Subroutine of free_for_value_p, used to check a single register.
5072 START_REGNO is the starting regno of the full reload register
5073 (possibly comprising multiple hard registers) that we are considering. */
5076 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5077 enum reload_type type, rtx value, rtx out,
5078 int reloadnum, int ignore_address_reloads)
5081 /* Set if we see an input reload that must not share its reload register
5082 with any new earlyclobber, but might otherwise share the reload
5083 register with an output or input-output reload. */
5084 int check_earlyclobber = 0;
5088 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5091 if (out == const0_rtx)
5097 /* We use some pseudo 'time' value to check if the lifetimes of the
5098 new register use would overlap with the one of a previous reload
5099 that is not read-only or uses a different value.
5100 The 'time' used doesn't have to be linear in any shape or form, just
5102 Some reload types use different 'buckets' for each operand.
5103 So there are MAX_RECOG_OPERANDS different time values for each
5105 We compute TIME1 as the time when the register for the prospective
5106 new reload ceases to be live, and TIME2 for each existing
5107 reload as the time when that the reload register of that reload
5109 Where there is little to be gained by exact lifetime calculations,
5110 we just make conservative assumptions, i.e. a longer lifetime;
5111 this is done in the 'default:' cases. */
5114 case RELOAD_FOR_OTHER_ADDRESS:
5115 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5116 time1 = copy ? 0 : 1;
5119 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5121 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5122 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5123 respectively, to the time values for these, we get distinct time
5124 values. To get distinct time values for each operand, we have to
5125 multiply opnum by at least three. We round that up to four because
5126 multiply by four is often cheaper. */
5127 case RELOAD_FOR_INPADDR_ADDRESS:
5128 time1 = opnum * 4 + 2;
5130 case RELOAD_FOR_INPUT_ADDRESS:
5131 time1 = opnum * 4 + 3;
5133 case RELOAD_FOR_INPUT:
5134 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5135 executes (inclusive). */
5136 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5138 case RELOAD_FOR_OPADDR_ADDR:
5140 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5141 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5143 case RELOAD_FOR_OPERAND_ADDRESS:
5144 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5146 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5148 case RELOAD_FOR_OUTADDR_ADDRESS:
5149 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5151 case RELOAD_FOR_OUTPUT_ADDRESS:
5152 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5155 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5158 for (i = 0; i < n_reloads; i++)
5160 rtx reg = rld[i].reg_rtx;
5161 if (reg && REG_P (reg)
5162 && ((unsigned) regno - true_regnum (reg)
5163 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5166 rtx other_input = rld[i].in;
5168 /* If the other reload loads the same input value, that
5169 will not cause a conflict only if it's loading it into
5170 the same register. */
5171 if (true_regnum (reg) != start_regno)
5172 other_input = NULL_RTX;
5173 if (! other_input || ! rtx_equal_p (other_input, value)
5174 || rld[i].out || out)
5177 switch (rld[i].when_needed)
5179 case RELOAD_FOR_OTHER_ADDRESS:
5182 case RELOAD_FOR_INPADDR_ADDRESS:
5183 /* find_reloads makes sure that a
5184 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5185 by at most one - the first -
5186 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5187 address reload is inherited, the address address reload
5188 goes away, so we can ignore this conflict. */
5189 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5190 && ignore_address_reloads
5191 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5192 Then the address address is still needed to store
5193 back the new address. */
5194 && ! rld[reloadnum].out)
5196 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5197 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5199 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5200 && ignore_address_reloads
5201 /* Unless we are reloading an auto_inc expression. */
5202 && ! rld[reloadnum].out)
5204 time2 = rld[i].opnum * 4 + 2;
5206 case RELOAD_FOR_INPUT_ADDRESS:
5207 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5208 && ignore_address_reloads
5209 && ! rld[reloadnum].out)
5211 time2 = rld[i].opnum * 4 + 3;
5213 case RELOAD_FOR_INPUT:
5214 time2 = rld[i].opnum * 4 + 4;
5215 check_earlyclobber = 1;
5217 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5218 == MAX_RECOG_OPERAND * 4 */
5219 case RELOAD_FOR_OPADDR_ADDR:
5220 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5221 && ignore_address_reloads
5222 && ! rld[reloadnum].out)
5224 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5226 case RELOAD_FOR_OPERAND_ADDRESS:
5227 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5228 check_earlyclobber = 1;
5230 case RELOAD_FOR_INSN:
5231 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5233 case RELOAD_FOR_OUTPUT:
5234 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5235 instruction is executed. */
5236 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5238 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5239 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5241 case RELOAD_FOR_OUTADDR_ADDRESS:
5242 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5243 && ignore_address_reloads
5244 && ! rld[reloadnum].out)
5246 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5248 case RELOAD_FOR_OUTPUT_ADDRESS:
5249 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5252 /* If there is no conflict in the input part, handle this
5253 like an output reload. */
5254 if (! rld[i].in || rtx_equal_p (other_input, value))
5256 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5257 /* Earlyclobbered outputs must conflict with inputs. */
5258 if (earlyclobber_operand_p (rld[i].out))
5259 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5264 /* RELOAD_OTHER might be live beyond instruction execution,
5265 but this is not obvious when we set time2 = 1. So check
5266 here if there might be a problem with the new reload
5267 clobbering the register used by the RELOAD_OTHER. */
5275 && (! rld[i].in || rld[i].out
5276 || ! rtx_equal_p (other_input, value)))
5277 || (out && rld[reloadnum].out_reg
5278 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5284 /* Earlyclobbered outputs must conflict with inputs. */
5285 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5291 /* Return 1 if the value in reload reg REGNO, as used by a reload
5292 needed for the part of the insn specified by OPNUM and TYPE,
5293 may be used to load VALUE into it.
5295 MODE is the mode in which the register is used, this is needed to
5296 determine how many hard regs to test.
5298 Other read-only reloads with the same value do not conflict
5299 unless OUT is nonzero and these other reloads have to live while
5300 output reloads live.
5301 If OUT is CONST0_RTX, this is a special case: it means that the
5302 test should not be for using register REGNO as reload register, but
5303 for copying from register REGNO into the reload register.
5305 RELOADNUM is the number of the reload we want to load this value for;
5306 a reload does not conflict with itself.
5308 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5309 reloads that load an address for the very reload we are considering.
5311 The caller has to make sure that there is no conflict with the return
5315 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5316 enum reload_type type, rtx value, rtx out, int reloadnum,
5317 int ignore_address_reloads)
5319 int nregs = hard_regno_nregs[regno][mode];
5321 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5322 value, out, reloadnum,
5323 ignore_address_reloads))
5328 /* Return nonzero if the rtx X is invariant over the current function. */
5329 /* ??? Actually, the places where we use this expect exactly what is
5330 tested here, and not everything that is function invariant. In
5331 particular, the frame pointer and arg pointer are special cased;
5332 pic_offset_table_rtx is not, and we must not spill these things to
5336 function_invariant_p (const_rtx x)
5340 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5342 if (GET_CODE (x) == PLUS
5343 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5344 && CONSTANT_P (XEXP (x, 1)))
5349 /* Determine whether the reload reg X overlaps any rtx'es used for
5350 overriding inheritance. Return nonzero if so. */
5353 conflicts_with_override (rtx x)
5356 for (i = 0; i < n_reloads; i++)
5357 if (reload_override_in[i]
5358 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5363 /* Give an error message saying we failed to find a reload for INSN,
5364 and clear out reload R. */
5366 failed_reload (rtx insn, int r)
5368 if (asm_noperands (PATTERN (insn)) < 0)
5369 /* It's the compiler's fault. */
5370 fatal_insn ("could not find a spill register", insn);
5372 /* It's the user's fault; the operand's mode and constraint
5373 don't match. Disable this reload so we don't crash in final. */
5374 error_for_asm (insn,
5375 "%<asm%> operand constraint incompatible with operand size");
5379 rld[r].optional = 1;
5380 rld[r].secondary_p = 1;
5383 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5384 for reload R. If it's valid, get an rtx for it. Return nonzero if
5387 set_reload_reg (int i, int r)
5390 rtx reg = spill_reg_rtx[i];
5392 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5393 spill_reg_rtx[i] = reg
5394 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5396 regno = true_regnum (reg);
5398 /* Detect when the reload reg can't hold the reload mode.
5399 This used to be one `if', but Sequent compiler can't handle that. */
5400 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5402 enum machine_mode test_mode = VOIDmode;
5404 test_mode = GET_MODE (rld[r].in);
5405 /* If rld[r].in has VOIDmode, it means we will load it
5406 in whatever mode the reload reg has: to wit, rld[r].mode.
5407 We have already tested that for validity. */
5408 /* Aside from that, we need to test that the expressions
5409 to reload from or into have modes which are valid for this
5410 reload register. Otherwise the reload insns would be invalid. */
5411 if (! (rld[r].in != 0 && test_mode != VOIDmode
5412 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5413 if (! (rld[r].out != 0
5414 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5416 /* The reg is OK. */
5419 /* Mark as in use for this insn the reload regs we use
5421 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5422 rld[r].when_needed, rld[r].mode);
5424 rld[r].reg_rtx = reg;
5425 reload_spill_index[r] = spill_regs[i];
5432 /* Find a spill register to use as a reload register for reload R.
5433 LAST_RELOAD is nonzero if this is the last reload for the insn being
5436 Set rld[R].reg_rtx to the register allocated.
5438 We return 1 if successful, or 0 if we couldn't find a spill reg and
5439 we didn't change anything. */
5442 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5447 /* If we put this reload ahead, thinking it is a group,
5448 then insist on finding a group. Otherwise we can grab a
5449 reg that some other reload needs.
5450 (That can happen when we have a 68000 DATA_OR_FP_REG
5451 which is a group of data regs or one fp reg.)
5452 We need not be so restrictive if there are no more reloads
5455 ??? Really it would be nicer to have smarter handling
5456 for that kind of reg class, where a problem like this is normal.
5457 Perhaps those classes should be avoided for reloading
5458 by use of more alternatives. */
5460 int force_group = rld[r].nregs > 1 && ! last_reload;
5462 /* If we want a single register and haven't yet found one,
5463 take any reg in the right class and not in use.
5464 If we want a consecutive group, here is where we look for it.
5466 We use two passes so we can first look for reload regs to
5467 reuse, which are already in use for other reloads in this insn,
5468 and only then use additional registers.
5469 I think that maximizing reuse is needed to make sure we don't
5470 run out of reload regs. Suppose we have three reloads, and
5471 reloads A and B can share regs. These need two regs.
5472 Suppose A and B are given different regs.
5473 That leaves none for C. */
5474 for (pass = 0; pass < 2; pass++)
5476 /* I is the index in spill_regs.
5477 We advance it round-robin between insns to use all spill regs
5478 equally, so that inherited reloads have a chance
5479 of leapfrogging each other. */
5483 for (count = 0; count < n_spills; count++)
5485 int class = (int) rld[r].class;
5491 regnum = spill_regs[i];
5493 if ((reload_reg_free_p (regnum, rld[r].opnum,
5496 /* We check reload_reg_used to make sure we
5497 don't clobber the return register. */
5498 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5499 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5500 rld[r].when_needed, rld[r].in,
5502 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5503 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5504 /* Look first for regs to share, then for unshared. But
5505 don't share regs used for inherited reloads; they are
5506 the ones we want to preserve. */
5508 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5510 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5513 int nr = hard_regno_nregs[regnum][rld[r].mode];
5514 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5515 (on 68000) got us two FP regs. If NR is 1,
5516 we would reject both of them. */
5519 /* If we need only one reg, we have already won. */
5522 /* But reject a single reg if we demand a group. */
5527 /* Otherwise check that as many consecutive regs as we need
5528 are available here. */
5531 int regno = regnum + nr - 1;
5532 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5533 && spill_reg_order[regno] >= 0
5534 && reload_reg_free_p (regno, rld[r].opnum,
5535 rld[r].when_needed)))
5544 /* If we found something on pass 1, omit pass 2. */
5545 if (count < n_spills)
5549 /* We should have found a spill register by now. */
5550 if (count >= n_spills)
5553 /* I is the index in SPILL_REG_RTX of the reload register we are to
5554 allocate. Get an rtx for it and find its register number. */
5556 return set_reload_reg (i, r);
5559 /* Initialize all the tables needed to allocate reload registers.
5560 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5561 is the array we use to restore the reg_rtx field for every reload. */
5564 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5568 for (i = 0; i < n_reloads; i++)
5569 rld[i].reg_rtx = save_reload_reg_rtx[i];
5571 memset (reload_inherited, 0, MAX_RELOADS);
5572 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5573 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5575 CLEAR_HARD_REG_SET (reload_reg_used);
5576 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5577 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5578 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5579 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5580 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5582 CLEAR_HARD_REG_SET (reg_used_in_insn);
5585 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5586 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5587 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5588 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5589 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5590 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5593 for (i = 0; i < reload_n_operands; i++)
5595 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5596 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5597 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5598 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5599 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5600 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5603 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5605 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5607 for (i = 0; i < n_reloads; i++)
5608 /* If we have already decided to use a certain register,
5609 don't use it in another way. */
5611 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5612 rld[i].when_needed, rld[i].mode);
5615 /* Assign hard reg targets for the pseudo-registers we must reload
5616 into hard regs for this insn.
5617 Also output the instructions to copy them in and out of the hard regs.
5619 For machines with register classes, we are responsible for
5620 finding a reload reg in the proper class. */
5623 choose_reload_regs (struct insn_chain *chain)
5625 rtx insn = chain->insn;
5627 unsigned int max_group_size = 1;
5628 enum reg_class group_class = NO_REGS;
5629 int pass, win, inheritance;
5631 rtx save_reload_reg_rtx[MAX_RELOADS];
5633 /* In order to be certain of getting the registers we need,
5634 we must sort the reloads into order of increasing register class.
5635 Then our grabbing of reload registers will parallel the process
5636 that provided the reload registers.
5638 Also note whether any of the reloads wants a consecutive group of regs.
5639 If so, record the maximum size of the group desired and what
5640 register class contains all the groups needed by this insn. */
5642 for (j = 0; j < n_reloads; j++)
5644 reload_order[j] = j;
5645 if (rld[j].reg_rtx != NULL_RTX)
5647 gcc_assert (REG_P (rld[j].reg_rtx)
5648 && HARD_REGISTER_P (rld[j].reg_rtx));
5649 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5652 reload_spill_index[j] = -1;
5654 if (rld[j].nregs > 1)
5656 max_group_size = MAX (rld[j].nregs, max_group_size);
5658 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5661 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5665 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5667 /* If -O, try first with inheritance, then turning it off.
5668 If not -O, don't do inheritance.
5669 Using inheritance when not optimizing leads to paradoxes
5670 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5671 because one side of the comparison might be inherited. */
5673 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5675 choose_reload_regs_init (chain, save_reload_reg_rtx);
5677 /* Process the reloads in order of preference just found.
5678 Beyond this point, subregs can be found in reload_reg_rtx.
5680 This used to look for an existing reloaded home for all of the
5681 reloads, and only then perform any new reloads. But that could lose
5682 if the reloads were done out of reg-class order because a later
5683 reload with a looser constraint might have an old home in a register
5684 needed by an earlier reload with a tighter constraint.
5686 To solve this, we make two passes over the reloads, in the order
5687 described above. In the first pass we try to inherit a reload
5688 from a previous insn. If there is a later reload that needs a
5689 class that is a proper subset of the class being processed, we must
5690 also allocate a spill register during the first pass.
5692 Then make a second pass over the reloads to allocate any reloads
5693 that haven't been given registers yet. */
5695 for (j = 0; j < n_reloads; j++)
5697 int r = reload_order[j];
5698 rtx search_equiv = NULL_RTX;
5700 /* Ignore reloads that got marked inoperative. */
5701 if (rld[r].out == 0 && rld[r].in == 0
5702 && ! rld[r].secondary_p)
5705 /* If find_reloads chose to use reload_in or reload_out as a reload
5706 register, we don't need to chose one. Otherwise, try even if it
5707 found one since we might save an insn if we find the value lying
5709 Try also when reload_in is a pseudo without a hard reg. */
5710 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5711 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5712 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5713 && !MEM_P (rld[r].in)
5714 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5717 #if 0 /* No longer needed for correct operation.
5718 It might give better code, or might not; worth an experiment? */
5719 /* If this is an optional reload, we can't inherit from earlier insns
5720 until we are sure that any non-optional reloads have been allocated.
5721 The following code takes advantage of the fact that optional reloads
5722 are at the end of reload_order. */
5723 if (rld[r].optional != 0)
5724 for (i = 0; i < j; i++)
5725 if ((rld[reload_order[i]].out != 0
5726 || rld[reload_order[i]].in != 0
5727 || rld[reload_order[i]].secondary_p)
5728 && ! rld[reload_order[i]].optional
5729 && rld[reload_order[i]].reg_rtx == 0)
5730 allocate_reload_reg (chain, reload_order[i], 0);
5733 /* First see if this pseudo is already available as reloaded
5734 for a previous insn. We cannot try to inherit for reloads
5735 that are smaller than the maximum number of registers needed
5736 for groups unless the register we would allocate cannot be used
5739 We could check here to see if this is a secondary reload for
5740 an object that is already in a register of the desired class.
5741 This would avoid the need for the secondary reload register.
5742 But this is complex because we can't easily determine what
5743 objects might want to be loaded via this reload. So let a
5744 register be allocated here. In `emit_reload_insns' we suppress
5745 one of the loads in the case described above. */
5751 enum machine_mode mode = VOIDmode;
5755 else if (REG_P (rld[r].in))
5757 regno = REGNO (rld[r].in);
5758 mode = GET_MODE (rld[r].in);
5760 else if (REG_P (rld[r].in_reg))
5762 regno = REGNO (rld[r].in_reg);
5763 mode = GET_MODE (rld[r].in_reg);
5765 else if (GET_CODE (rld[r].in_reg) == SUBREG
5766 && REG_P (SUBREG_REG (rld[r].in_reg)))
5768 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5769 if (regno < FIRST_PSEUDO_REGISTER)
5770 regno = subreg_regno (rld[r].in_reg);
5772 byte = SUBREG_BYTE (rld[r].in_reg);
5773 mode = GET_MODE (rld[r].in_reg);
5776 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5777 && REG_P (XEXP (rld[r].in_reg, 0)))
5779 regno = REGNO (XEXP (rld[r].in_reg, 0));
5780 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5781 rld[r].out = rld[r].in;
5785 /* This won't work, since REGNO can be a pseudo reg number.
5786 Also, it takes much more hair to keep track of all the things
5787 that can invalidate an inherited reload of part of a pseudoreg. */
5788 else if (GET_CODE (rld[r].in) == SUBREG
5789 && REG_P (SUBREG_REG (rld[r].in)))
5790 regno = subreg_regno (rld[r].in);
5794 && reg_last_reload_reg[regno] != 0
5795 #ifdef CANNOT_CHANGE_MODE_CLASS
5796 /* Verify that the register it's in can be used in
5798 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5799 GET_MODE (reg_last_reload_reg[regno]),
5804 enum reg_class class = rld[r].class, last_class;
5805 rtx last_reg = reg_last_reload_reg[regno];
5806 enum machine_mode need_mode;
5808 i = REGNO (last_reg);
5809 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5810 last_class = REGNO_REG_CLASS (i);
5816 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5817 + byte * BITS_PER_UNIT,
5818 GET_MODE_CLASS (mode));
5820 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5821 >= GET_MODE_SIZE (need_mode))
5822 && reg_reloaded_contents[i] == regno
5823 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5824 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5825 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5826 /* Even if we can't use this register as a reload
5827 register, we might use it for reload_override_in,
5828 if copying it to the desired class is cheap
5830 || ((REGISTER_MOVE_COST (mode, last_class, class)
5831 < MEMORY_MOVE_COST (mode, class, 1))
5832 && (secondary_reload_class (1, class, mode,
5835 #ifdef SECONDARY_MEMORY_NEEDED
5836 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5841 && (rld[r].nregs == max_group_size
5842 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5844 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5845 rld[r].when_needed, rld[r].in,
5848 /* If a group is needed, verify that all the subsequent
5849 registers still have their values intact. */
5850 int nr = hard_regno_nregs[i][rld[r].mode];
5853 for (k = 1; k < nr; k++)
5854 if (reg_reloaded_contents[i + k] != regno
5855 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5863 last_reg = (GET_MODE (last_reg) == mode
5864 ? last_reg : gen_rtx_REG (mode, i));
5867 for (k = 0; k < nr; k++)
5868 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5871 /* We found a register that contains the
5872 value we need. If this register is the
5873 same as an `earlyclobber' operand of the
5874 current insn, just mark it as a place to
5875 reload from since we can't use it as the
5876 reload register itself. */
5878 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5879 if (reg_overlap_mentioned_for_reload_p
5880 (reg_last_reload_reg[regno],
5881 reload_earlyclobbers[i1]))
5884 if (i1 != n_earlyclobbers
5885 || ! (free_for_value_p (i, rld[r].mode,
5887 rld[r].when_needed, rld[r].in,
5889 /* Don't use it if we'd clobber a pseudo reg. */
5890 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5892 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5893 /* Don't clobber the frame pointer. */
5894 || (i == HARD_FRAME_POINTER_REGNUM
5895 && frame_pointer_needed
5897 /* Don't really use the inherited spill reg
5898 if we need it wider than we've got it. */
5899 || (GET_MODE_SIZE (rld[r].mode)
5900 > GET_MODE_SIZE (mode))
5903 /* If find_reloads chose reload_out as reload
5904 register, stay with it - that leaves the
5905 inherited register for subsequent reloads. */
5906 || (rld[r].out && rld[r].reg_rtx
5907 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5909 if (! rld[r].optional)
5911 reload_override_in[r] = last_reg;
5912 reload_inheritance_insn[r]
5913 = reg_reloaded_insn[i];
5919 /* We can use this as a reload reg. */
5920 /* Mark the register as in use for this part of
5922 mark_reload_reg_in_use (i,
5926 rld[r].reg_rtx = last_reg;
5927 reload_inherited[r] = 1;
5928 reload_inheritance_insn[r]
5929 = reg_reloaded_insn[i];
5930 reload_spill_index[r] = i;
5931 for (k = 0; k < nr; k++)
5932 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5940 /* Here's another way to see if the value is already lying around. */
5943 && ! reload_inherited[r]
5945 && (CONSTANT_P (rld[r].in)
5946 || GET_CODE (rld[r].in) == PLUS
5947 || REG_P (rld[r].in)
5948 || MEM_P (rld[r].in))
5949 && (rld[r].nregs == max_group_size
5950 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5951 search_equiv = rld[r].in;
5952 /* If this is an output reload from a simple move insn, look
5953 if an equivalence for the input is available. */
5954 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5956 rtx set = single_set (insn);
5959 && rtx_equal_p (rld[r].out, SET_DEST (set))
5960 && CONSTANT_P (SET_SRC (set)))
5961 search_equiv = SET_SRC (set);
5967 = find_equiv_reg (search_equiv, insn, rld[r].class,
5968 -1, NULL, 0, rld[r].mode);
5974 regno = REGNO (equiv);
5977 /* This must be a SUBREG of a hard register.
5978 Make a new REG since this might be used in an
5979 address and not all machines support SUBREGs
5981 gcc_assert (GET_CODE (equiv) == SUBREG);
5982 regno = subreg_regno (equiv);
5983 equiv = gen_rtx_REG (rld[r].mode, regno);
5984 /* If we choose EQUIV as the reload register, but the
5985 loop below decides to cancel the inheritance, we'll
5986 end up reloading EQUIV in rld[r].mode, not the mode
5987 it had originally. That isn't safe when EQUIV isn't
5988 available as a spill register since its value might
5989 still be live at this point. */
5990 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5991 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5996 /* If we found a spill reg, reject it unless it is free
5997 and of the desired class. */
6001 int bad_for_class = 0;
6002 int max_regno = regno + rld[r].nregs;
6004 for (i = regno; i < max_regno; i++)
6006 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6008 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6013 && ! free_for_value_p (regno, rld[r].mode,
6014 rld[r].opnum, rld[r].when_needed,
6015 rld[r].in, rld[r].out, r, 1))
6020 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6023 /* We found a register that contains the value we need.
6024 If this register is the same as an `earlyclobber' operand
6025 of the current insn, just mark it as a place to reload from
6026 since we can't use it as the reload register itself. */
6029 for (i = 0; i < n_earlyclobbers; i++)
6030 if (reg_overlap_mentioned_for_reload_p (equiv,
6031 reload_earlyclobbers[i]))
6033 if (! rld[r].optional)
6034 reload_override_in[r] = equiv;
6039 /* If the equiv register we have found is explicitly clobbered
6040 in the current insn, it depends on the reload type if we
6041 can use it, use it for reload_override_in, or not at all.
6042 In particular, we then can't use EQUIV for a
6043 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6047 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6048 switch (rld[r].when_needed)
6050 case RELOAD_FOR_OTHER_ADDRESS:
6051 case RELOAD_FOR_INPADDR_ADDRESS:
6052 case RELOAD_FOR_INPUT_ADDRESS:
6053 case RELOAD_FOR_OPADDR_ADDR:
6056 case RELOAD_FOR_INPUT:
6057 case RELOAD_FOR_OPERAND_ADDRESS:
6058 if (! rld[r].optional)
6059 reload_override_in[r] = equiv;
6065 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6066 switch (rld[r].when_needed)
6068 case RELOAD_FOR_OTHER_ADDRESS:
6069 case RELOAD_FOR_INPADDR_ADDRESS:
6070 case RELOAD_FOR_INPUT_ADDRESS:
6071 case RELOAD_FOR_OPADDR_ADDR:
6072 case RELOAD_FOR_OPERAND_ADDRESS:
6073 case RELOAD_FOR_INPUT:
6076 if (! rld[r].optional)
6077 reload_override_in[r] = equiv;
6085 /* If we found an equivalent reg, say no code need be generated
6086 to load it, and use it as our reload reg. */
6088 && (regno != HARD_FRAME_POINTER_REGNUM
6089 || !frame_pointer_needed))
6091 int nr = hard_regno_nregs[regno][rld[r].mode];
6093 rld[r].reg_rtx = equiv;
6094 reload_inherited[r] = 1;
6096 /* If reg_reloaded_valid is not set for this register,
6097 there might be a stale spill_reg_store lying around.
6098 We must clear it, since otherwise emit_reload_insns
6099 might delete the store. */
6100 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6101 spill_reg_store[regno] = NULL_RTX;
6102 /* If any of the hard registers in EQUIV are spill
6103 registers, mark them as in use for this insn. */
6104 for (k = 0; k < nr; k++)
6106 i = spill_reg_order[regno + k];
6109 mark_reload_reg_in_use (regno, rld[r].opnum,
6112 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6119 /* If we found a register to use already, or if this is an optional
6120 reload, we are done. */
6121 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6125 /* No longer needed for correct operation. Might or might
6126 not give better code on the average. Want to experiment? */
6128 /* See if there is a later reload that has a class different from our
6129 class that intersects our class or that requires less register
6130 than our reload. If so, we must allocate a register to this
6131 reload now, since that reload might inherit a previous reload
6132 and take the only available register in our class. Don't do this
6133 for optional reloads since they will force all previous reloads
6134 to be allocated. Also don't do this for reloads that have been
6137 for (i = j + 1; i < n_reloads; i++)
6139 int s = reload_order[i];
6141 if ((rld[s].in == 0 && rld[s].out == 0
6142 && ! rld[s].secondary_p)
6146 if ((rld[s].class != rld[r].class
6147 && reg_classes_intersect_p (rld[r].class,
6149 || rld[s].nregs < rld[r].nregs)
6156 allocate_reload_reg (chain, r, j == n_reloads - 1);
6160 /* Now allocate reload registers for anything non-optional that
6161 didn't get one yet. */
6162 for (j = 0; j < n_reloads; j++)
6164 int r = reload_order[j];
6166 /* Ignore reloads that got marked inoperative. */
6167 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6170 /* Skip reloads that already have a register allocated or are
6172 if (rld[r].reg_rtx != 0 || rld[r].optional)
6175 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6179 /* If that loop got all the way, we have won. */
6186 /* Loop around and try without any inheritance. */
6191 /* First undo everything done by the failed attempt
6192 to allocate with inheritance. */
6193 choose_reload_regs_init (chain, save_reload_reg_rtx);
6195 /* Some sanity tests to verify that the reloads found in the first
6196 pass are identical to the ones we have now. */
6197 gcc_assert (chain->n_reloads == n_reloads);
6199 for (i = 0; i < n_reloads; i++)
6201 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6203 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6204 for (j = 0; j < n_spills; j++)
6205 if (spill_regs[j] == chain->rld[i].regno)
6206 if (! set_reload_reg (j, i))
6207 failed_reload (chain->insn, i);
6211 /* If we thought we could inherit a reload, because it seemed that
6212 nothing else wanted the same reload register earlier in the insn,
6213 verify that assumption, now that all reloads have been assigned.
6214 Likewise for reloads where reload_override_in has been set. */
6216 /* If doing expensive optimizations, do one preliminary pass that doesn't
6217 cancel any inheritance, but removes reloads that have been needed only
6218 for reloads that we know can be inherited. */
6219 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6221 for (j = 0; j < n_reloads; j++)
6223 int r = reload_order[j];
6225 if (reload_inherited[r] && rld[r].reg_rtx)
6226 check_reg = rld[r].reg_rtx;
6227 else if (reload_override_in[r]
6228 && (REG_P (reload_override_in[r])
6229 || GET_CODE (reload_override_in[r]) == SUBREG))
6230 check_reg = reload_override_in[r];
6233 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6234 rld[r].opnum, rld[r].when_needed, rld[r].in,
6235 (reload_inherited[r]
6236 ? rld[r].out : const0_rtx),
6241 reload_inherited[r] = 0;
6242 reload_override_in[r] = 0;
6244 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6245 reload_override_in, then we do not need its related
6246 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6247 likewise for other reload types.
6248 We handle this by removing a reload when its only replacement
6249 is mentioned in reload_in of the reload we are going to inherit.
6250 A special case are auto_inc expressions; even if the input is
6251 inherited, we still need the address for the output. We can
6252 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6253 If we succeeded removing some reload and we are doing a preliminary
6254 pass just to remove such reloads, make another pass, since the
6255 removal of one reload might allow us to inherit another one. */
6257 && rld[r].out != rld[r].in
6258 && remove_address_replacements (rld[r].in) && pass)
6263 /* Now that reload_override_in is known valid,
6264 actually override reload_in. */
6265 for (j = 0; j < n_reloads; j++)
6266 if (reload_override_in[j])
6267 rld[j].in = reload_override_in[j];
6269 /* If this reload won't be done because it has been canceled or is
6270 optional and not inherited, clear reload_reg_rtx so other
6271 routines (such as subst_reloads) don't get confused. */
6272 for (j = 0; j < n_reloads; j++)
6273 if (rld[j].reg_rtx != 0
6274 && ((rld[j].optional && ! reload_inherited[j])
6275 || (rld[j].in == 0 && rld[j].out == 0
6276 && ! rld[j].secondary_p)))
6278 int regno = true_regnum (rld[j].reg_rtx);
6280 if (spill_reg_order[regno] >= 0)
6281 clear_reload_reg_in_use (regno, rld[j].opnum,
6282 rld[j].when_needed, rld[j].mode);
6284 reload_spill_index[j] = -1;
6287 /* Record which pseudos and which spill regs have output reloads. */
6288 for (j = 0; j < n_reloads; j++)
6290 int r = reload_order[j];
6292 i = reload_spill_index[r];
6294 /* I is nonneg if this reload uses a register.
6295 If rld[r].reg_rtx is 0, this is an optional reload
6296 that we opted to ignore. */
6297 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6298 && rld[r].reg_rtx != 0)
6300 int nregno = REGNO (rld[r].out_reg);
6303 if (nregno < FIRST_PSEUDO_REGISTER)
6304 nr = hard_regno_nregs[nregno][rld[r].mode];
6307 SET_REGNO_REG_SET (®_has_output_reload,
6312 nr = hard_regno_nregs[i][rld[r].mode];
6314 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6317 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6318 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6319 || rld[r].when_needed == RELOAD_FOR_INSN);
6324 /* Deallocate the reload register for reload R. This is called from
6325 remove_address_replacements. */
6328 deallocate_reload_reg (int r)
6332 if (! rld[r].reg_rtx)
6334 regno = true_regnum (rld[r].reg_rtx);
6336 if (spill_reg_order[regno] >= 0)
6337 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6339 reload_spill_index[r] = -1;
6342 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6343 reloads of the same item for fear that we might not have enough reload
6344 registers. However, normally they will get the same reload register
6345 and hence actually need not be loaded twice.
6347 Here we check for the most common case of this phenomenon: when we have
6348 a number of reloads for the same object, each of which were allocated
6349 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6350 reload, and is not modified in the insn itself. If we find such,
6351 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6352 This will not increase the number of spill registers needed and will
6353 prevent redundant code. */
6356 merge_assigned_reloads (rtx insn)
6360 /* Scan all the reloads looking for ones that only load values and
6361 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6362 assigned and not modified by INSN. */
6364 for (i = 0; i < n_reloads; i++)
6366 int conflicting_input = 0;
6367 int max_input_address_opnum = -1;
6368 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6370 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6371 || rld[i].out != 0 || rld[i].reg_rtx == 0
6372 || reg_set_p (rld[i].reg_rtx, insn))
6375 /* Look at all other reloads. Ensure that the only use of this
6376 reload_reg_rtx is in a reload that just loads the same value
6377 as we do. Note that any secondary reloads must be of the identical
6378 class since the values, modes, and result registers are the
6379 same, so we need not do anything with any secondary reloads. */
6381 for (j = 0; j < n_reloads; j++)
6383 if (i == j || rld[j].reg_rtx == 0
6384 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6388 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6389 && rld[j].opnum > max_input_address_opnum)
6390 max_input_address_opnum = rld[j].opnum;
6392 /* If the reload regs aren't exactly the same (e.g, different modes)
6393 or if the values are different, we can't merge this reload.
6394 But if it is an input reload, we might still merge
6395 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6397 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6398 || rld[j].out != 0 || rld[j].in == 0
6399 || ! rtx_equal_p (rld[i].in, rld[j].in))
6401 if (rld[j].when_needed != RELOAD_FOR_INPUT
6402 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6403 || rld[i].opnum > rld[j].opnum)
6404 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6406 conflicting_input = 1;
6407 if (min_conflicting_input_opnum > rld[j].opnum)
6408 min_conflicting_input_opnum = rld[j].opnum;
6412 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6413 we, in fact, found any matching reloads. */
6416 && max_input_address_opnum <= min_conflicting_input_opnum)
6418 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6420 for (j = 0; j < n_reloads; j++)
6421 if (i != j && rld[j].reg_rtx != 0
6422 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6423 && (! conflicting_input
6424 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6425 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6427 rld[i].when_needed = RELOAD_OTHER;
6429 reload_spill_index[j] = -1;
6430 transfer_replacements (i, j);
6433 /* If this is now RELOAD_OTHER, look for any reloads that
6434 load parts of this operand and set them to
6435 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6436 RELOAD_OTHER for outputs. Note that this test is
6437 equivalent to looking for reloads for this operand
6440 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6441 it may share registers with a RELOAD_FOR_INPUT, so we can
6442 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6443 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6445 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6446 instruction is assigned the same register as the earlier
6447 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6448 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6449 instruction to be deleted later on. */
6451 if (rld[i].when_needed == RELOAD_OTHER)
6452 for (j = 0; j < n_reloads; j++)
6454 && rld[j].when_needed != RELOAD_OTHER
6455 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6456 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6457 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6458 && (! conflicting_input
6459 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6460 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6461 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6467 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6468 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6469 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6471 /* Check to see if we accidentally converted two
6472 reloads that use the same reload register with
6473 different inputs to the same type. If so, the
6474 resulting code won't work. */
6476 for (k = 0; k < j; k++)
6477 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6478 || rld[k].when_needed != rld[j].when_needed
6479 || !rtx_equal_p (rld[k].reg_rtx,
6481 || rtx_equal_p (rld[k].in,
6488 /* These arrays are filled by emit_reload_insns and its subroutines. */
6489 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6490 static rtx other_input_address_reload_insns = 0;
6491 static rtx other_input_reload_insns = 0;
6492 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6493 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6494 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6495 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6496 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6497 static rtx operand_reload_insns = 0;
6498 static rtx other_operand_reload_insns = 0;
6499 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6501 /* Values to be put in spill_reg_store are put here first. */
6502 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6503 static HARD_REG_SET reg_reloaded_died;
6505 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6506 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6507 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6508 adjusted register, and return true. Otherwise, return false. */
6510 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6511 enum reg_class new_class,
6512 enum machine_mode new_mode)
6517 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6519 unsigned regno = REGNO (reg);
6521 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6523 if (GET_MODE (reg) != new_mode)
6525 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6527 if (hard_regno_nregs[regno][new_mode]
6528 > hard_regno_nregs[regno][GET_MODE (reg)])
6530 reg = reload_adjust_reg_for_mode (reg, new_mode);
6538 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6539 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6540 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6541 adjusted register, and return true. Otherwise, return false. */
6543 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6544 enum insn_code icode)
6547 enum reg_class new_class = scratch_reload_class (icode);
6548 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6550 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6551 new_class, new_mode);
6554 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6555 has the number J. OLD contains the value to be used as input. */
6558 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6561 rtx insn = chain->insn;
6562 rtx reloadreg = rl->reg_rtx;
6563 rtx oldequiv_reg = 0;
6566 enum machine_mode mode;
6569 /* Determine the mode to reload in.
6570 This is very tricky because we have three to choose from.
6571 There is the mode the insn operand wants (rl->inmode).
6572 There is the mode of the reload register RELOADREG.
6573 There is the intrinsic mode of the operand, which we could find
6574 by stripping some SUBREGs.
6575 It turns out that RELOADREG's mode is irrelevant:
6576 we can change that arbitrarily.
6578 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6579 then the reload reg may not support QImode moves, so use SImode.
6580 If foo is in memory due to spilling a pseudo reg, this is safe,
6581 because the QImode value is in the least significant part of a
6582 slot big enough for a SImode. If foo is some other sort of
6583 memory reference, then it is impossible to reload this case,
6584 so previous passes had better make sure this never happens.
6586 Then consider a one-word union which has SImode and one of its
6587 members is a float, being fetched as (SUBREG:SF union:SI).
6588 We must fetch that as SFmode because we could be loading into
6589 a float-only register. In this case OLD's mode is correct.
6591 Consider an immediate integer: it has VOIDmode. Here we need
6592 to get a mode from something else.
6594 In some cases, there is a fourth mode, the operand's
6595 containing mode. If the insn specifies a containing mode for
6596 this operand, it overrides all others.
6598 I am not sure whether the algorithm here is always right,
6599 but it does the right things in those cases. */
6601 mode = GET_MODE (old);
6602 if (mode == VOIDmode)
6605 /* delete_output_reload is only invoked properly if old contains
6606 the original pseudo register. Since this is replaced with a
6607 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6608 find the pseudo in RELOAD_IN_REG. */
6609 if (reload_override_in[j]
6610 && REG_P (rl->in_reg))
6617 else if (REG_P (oldequiv))
6618 oldequiv_reg = oldequiv;
6619 else if (GET_CODE (oldequiv) == SUBREG)
6620 oldequiv_reg = SUBREG_REG (oldequiv);
6622 /* If we are reloading from a register that was recently stored in
6623 with an output-reload, see if we can prove there was
6624 actually no need to store the old value in it. */
6626 if (optimize && REG_P (oldequiv)
6627 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6628 && spill_reg_store[REGNO (oldequiv)]
6630 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6631 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6633 delete_output_reload (insn, j, REGNO (oldequiv));
6635 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6636 then load RELOADREG from OLDEQUIV. Note that we cannot use
6637 gen_lowpart_common since it can do the wrong thing when
6638 RELOADREG has a multi-word mode. Note that RELOADREG
6639 must always be a REG here. */
6641 if (GET_MODE (reloadreg) != mode)
6642 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6643 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6644 oldequiv = SUBREG_REG (oldequiv);
6645 if (GET_MODE (oldequiv) != VOIDmode
6646 && mode != GET_MODE (oldequiv))
6647 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6649 /* Switch to the right place to emit the reload insns. */
6650 switch (rl->when_needed)
6653 where = &other_input_reload_insns;
6655 case RELOAD_FOR_INPUT:
6656 where = &input_reload_insns[rl->opnum];
6658 case RELOAD_FOR_INPUT_ADDRESS:
6659 where = &input_address_reload_insns[rl->opnum];
6661 case RELOAD_FOR_INPADDR_ADDRESS:
6662 where = &inpaddr_address_reload_insns[rl->opnum];
6664 case RELOAD_FOR_OUTPUT_ADDRESS:
6665 where = &output_address_reload_insns[rl->opnum];
6667 case RELOAD_FOR_OUTADDR_ADDRESS:
6668 where = &outaddr_address_reload_insns[rl->opnum];
6670 case RELOAD_FOR_OPERAND_ADDRESS:
6671 where = &operand_reload_insns;
6673 case RELOAD_FOR_OPADDR_ADDR:
6674 where = &other_operand_reload_insns;
6676 case RELOAD_FOR_OTHER_ADDRESS:
6677 where = &other_input_address_reload_insns;
6683 push_to_sequence (*where);
6685 /* Auto-increment addresses must be reloaded in a special way. */
6686 if (rl->out && ! rl->out_reg)
6688 /* We are not going to bother supporting the case where a
6689 incremented register can't be copied directly from
6690 OLDEQUIV since this seems highly unlikely. */
6691 gcc_assert (rl->secondary_in_reload < 0);
6693 if (reload_inherited[j])
6694 oldequiv = reloadreg;
6696 old = XEXP (rl->in_reg, 0);
6698 if (optimize && REG_P (oldequiv)
6699 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6700 && spill_reg_store[REGNO (oldequiv)]
6702 && (dead_or_set_p (insn,
6703 spill_reg_stored_to[REGNO (oldequiv)])
6704 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6706 delete_output_reload (insn, j, REGNO (oldequiv));
6708 /* Prevent normal processing of this reload. */
6710 /* Output a special code sequence for this case. */
6711 new_spill_reg_store[REGNO (reloadreg)]
6712 = inc_for_reload (reloadreg, oldequiv, rl->out,
6716 /* If we are reloading a pseudo-register that was set by the previous
6717 insn, see if we can get rid of that pseudo-register entirely
6718 by redirecting the previous insn into our reload register. */
6720 else if (optimize && REG_P (old)
6721 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6722 && dead_or_set_p (insn, old)
6723 /* This is unsafe if some other reload
6724 uses the same reg first. */
6725 && ! conflicts_with_override (reloadreg)
6726 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6727 rl->when_needed, old, rl->out, j, 0))
6729 rtx temp = PREV_INSN (insn);
6730 while (temp && NOTE_P (temp))
6731 temp = PREV_INSN (temp);
6733 && NONJUMP_INSN_P (temp)
6734 && GET_CODE (PATTERN (temp)) == SET
6735 && SET_DEST (PATTERN (temp)) == old
6736 /* Make sure we can access insn_operand_constraint. */
6737 && asm_noperands (PATTERN (temp)) < 0
6738 /* This is unsafe if operand occurs more than once in current
6739 insn. Perhaps some occurrences aren't reloaded. */
6740 && count_occurrences (PATTERN (insn), old, 0) == 1)
6742 rtx old = SET_DEST (PATTERN (temp));
6743 /* Store into the reload register instead of the pseudo. */
6744 SET_DEST (PATTERN (temp)) = reloadreg;
6746 /* Verify that resulting insn is valid. */
6747 extract_insn (temp);
6748 if (constrain_operands (1))
6750 /* If the previous insn is an output reload, the source is
6751 a reload register, and its spill_reg_store entry will
6752 contain the previous destination. This is now
6754 if (REG_P (SET_SRC (PATTERN (temp)))
6755 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6757 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6758 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6761 /* If these are the only uses of the pseudo reg,
6762 pretend for GDB it lives in the reload reg we used. */
6763 if (REG_N_DEATHS (REGNO (old)) == 1
6764 && REG_N_SETS (REGNO (old)) == 1)
6766 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6767 alter_reg (REGNO (old), -1);
6773 SET_DEST (PATTERN (temp)) = old;
6778 /* We can't do that, so output an insn to load RELOADREG. */
6780 /* If we have a secondary reload, pick up the secondary register
6781 and icode, if any. If OLDEQUIV and OLD are different or
6782 if this is an in-out reload, recompute whether or not we
6783 still need a secondary register and what the icode should
6784 be. If we still need a secondary register and the class or
6785 icode is different, go back to reloading from OLD if using
6786 OLDEQUIV means that we got the wrong type of register. We
6787 cannot have different class or icode due to an in-out reload
6788 because we don't make such reloads when both the input and
6789 output need secondary reload registers. */
6791 if (! special && rl->secondary_in_reload >= 0)
6793 rtx second_reload_reg = 0;
6794 rtx third_reload_reg = 0;
6795 int secondary_reload = rl->secondary_in_reload;
6796 rtx real_oldequiv = oldequiv;
6799 enum insn_code icode;
6800 enum insn_code tertiary_icode = CODE_FOR_nothing;
6802 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6803 and similarly for OLD.
6804 See comments in get_secondary_reload in reload.c. */
6805 /* If it is a pseudo that cannot be replaced with its
6806 equivalent MEM, we must fall back to reload_in, which
6807 will have all the necessary substitutions registered.
6808 Likewise for a pseudo that can't be replaced with its
6809 equivalent constant.
6811 Take extra care for subregs of such pseudos. Note that
6812 we cannot use reg_equiv_mem in this case because it is
6813 not in the right mode. */
6816 if (GET_CODE (tmp) == SUBREG)
6817 tmp = SUBREG_REG (tmp);
6819 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6820 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6821 || reg_equiv_constant[REGNO (tmp)] != 0))
6823 if (! reg_equiv_mem[REGNO (tmp)]
6824 || num_not_at_initial_offset
6825 || GET_CODE (oldequiv) == SUBREG)
6826 real_oldequiv = rl->in;
6828 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6832 if (GET_CODE (tmp) == SUBREG)
6833 tmp = SUBREG_REG (tmp);
6835 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6836 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6837 || reg_equiv_constant[REGNO (tmp)] != 0))
6839 if (! reg_equiv_mem[REGNO (tmp)]
6840 || num_not_at_initial_offset
6841 || GET_CODE (old) == SUBREG)
6844 real_old = reg_equiv_mem[REGNO (tmp)];
6847 second_reload_reg = rld[secondary_reload].reg_rtx;
6848 if (rld[secondary_reload].secondary_in_reload >= 0)
6850 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6852 third_reload_reg = rld[tertiary_reload].reg_rtx;
6853 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6854 /* We'd have to add more code for quartary reloads. */
6855 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6857 icode = rl->secondary_in_icode;
6859 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6860 || (rl->in != 0 && rl->out != 0))
6862 secondary_reload_info sri, sri2;
6863 enum reg_class new_class, new_t_class;
6865 sri.icode = CODE_FOR_nothing;
6866 sri.prev_sri = NULL;
6867 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6870 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6871 second_reload_reg = 0;
6872 else if (new_class == NO_REGS)
6874 if (reload_adjust_reg_for_icode (&second_reload_reg,
6875 third_reload_reg, sri.icode))
6876 icode = sri.icode, third_reload_reg = 0;
6878 oldequiv = old, real_oldequiv = real_old;
6880 else if (sri.icode != CODE_FOR_nothing)
6881 /* We currently lack a way to express this in reloads. */
6885 sri2.icode = CODE_FOR_nothing;
6886 sri2.prev_sri = &sri;
6887 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6888 new_class, mode, &sri);
6889 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6891 if (reload_adjust_reg_for_temp (&second_reload_reg,
6894 third_reload_reg = 0, tertiary_icode = sri2.icode;
6896 oldequiv = old, real_oldequiv = real_old;
6898 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6900 rtx intermediate = second_reload_reg;
6902 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6904 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6907 second_reload_reg = intermediate;
6908 tertiary_icode = sri2.icode;
6911 oldequiv = old, real_oldequiv = real_old;
6913 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6915 rtx intermediate = second_reload_reg;
6917 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6919 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6922 second_reload_reg = intermediate;
6923 tertiary_icode = sri2.icode;
6926 oldequiv = old, real_oldequiv = real_old;
6929 /* This could be handled more intelligently too. */
6930 oldequiv = old, real_oldequiv = real_old;
6934 /* If we still need a secondary reload register, check
6935 to see if it is being used as a scratch or intermediate
6936 register and generate code appropriately. If we need
6937 a scratch register, use REAL_OLDEQUIV since the form of
6938 the insn may depend on the actual address if it is
6941 if (second_reload_reg)
6943 if (icode != CODE_FOR_nothing)
6945 /* We'd have to add extra code to handle this case. */
6946 gcc_assert (!third_reload_reg);
6948 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6949 second_reload_reg));
6954 /* See if we need a scratch register to load the
6955 intermediate register (a tertiary reload). */
6956 if (tertiary_icode != CODE_FOR_nothing)
6958 emit_insn ((GEN_FCN (tertiary_icode)
6959 (second_reload_reg, real_oldequiv,
6960 third_reload_reg)));
6962 else if (third_reload_reg)
6964 gen_reload (third_reload_reg, real_oldequiv,
6967 gen_reload (second_reload_reg, third_reload_reg,
6972 gen_reload (second_reload_reg, real_oldequiv,
6976 oldequiv = second_reload_reg;
6981 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6983 rtx real_oldequiv = oldequiv;
6985 if ((REG_P (oldequiv)
6986 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6987 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6988 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6989 || (GET_CODE (oldequiv) == SUBREG
6990 && REG_P (SUBREG_REG (oldequiv))
6991 && (REGNO (SUBREG_REG (oldequiv))
6992 >= FIRST_PSEUDO_REGISTER)
6993 && ((reg_equiv_memory_loc
6994 [REGNO (SUBREG_REG (oldequiv))] != 0)
6995 || (reg_equiv_constant
6996 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6997 || (CONSTANT_P (oldequiv)
6998 && (PREFERRED_RELOAD_CLASS (oldequiv,
6999 REGNO_REG_CLASS (REGNO (reloadreg)))
7001 real_oldequiv = rl->in;
7002 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7006 if (flag_non_call_exceptions)
7007 copy_eh_notes (insn, get_insns ());
7009 /* End this sequence. */
7010 *where = get_insns ();
7013 /* Update reload_override_in so that delete_address_reloads_1
7014 can see the actual register usage. */
7016 reload_override_in[j] = oldequiv;
7019 /* Generate insns to for the output reload RL, which is for the insn described
7020 by CHAIN and has the number J. */
7022 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7025 rtx reloadreg = rl->reg_rtx;
7026 rtx insn = chain->insn;
7029 enum machine_mode mode = GET_MODE (old);
7032 if (rl->when_needed == RELOAD_OTHER)
7035 push_to_sequence (output_reload_insns[rl->opnum]);
7037 /* Determine the mode to reload in.
7038 See comments above (for input reloading). */
7040 if (mode == VOIDmode)
7042 /* VOIDmode should never happen for an output. */
7043 if (asm_noperands (PATTERN (insn)) < 0)
7044 /* It's the compiler's fault. */
7045 fatal_insn ("VOIDmode on an output", insn);
7046 error_for_asm (insn, "output operand is constant in %<asm%>");
7047 /* Prevent crash--use something we know is valid. */
7049 old = gen_rtx_REG (mode, REGNO (reloadreg));
7052 if (GET_MODE (reloadreg) != mode)
7053 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7055 /* If we need two reload regs, set RELOADREG to the intermediate
7056 one, since it will be stored into OLD. We might need a secondary
7057 register only for an input reload, so check again here. */
7059 if (rl->secondary_out_reload >= 0)
7062 int secondary_reload = rl->secondary_out_reload;
7063 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7065 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7066 && reg_equiv_mem[REGNO (old)] != 0)
7067 real_old = reg_equiv_mem[REGNO (old)];
7069 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7071 rtx second_reloadreg = reloadreg;
7072 reloadreg = rld[secondary_reload].reg_rtx;
7074 /* See if RELOADREG is to be used as a scratch register
7075 or as an intermediate register. */
7076 if (rl->secondary_out_icode != CODE_FOR_nothing)
7078 /* We'd have to add extra code to handle this case. */
7079 gcc_assert (tertiary_reload < 0);
7081 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7082 (real_old, second_reloadreg, reloadreg)));
7087 /* See if we need both a scratch and intermediate reload
7090 enum insn_code tertiary_icode
7091 = rld[secondary_reload].secondary_out_icode;
7093 /* We'd have to add more code for quartary reloads. */
7094 gcc_assert (tertiary_reload < 0
7095 || rld[tertiary_reload].secondary_out_reload < 0);
7097 if (GET_MODE (reloadreg) != mode)
7098 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7100 if (tertiary_icode != CODE_FOR_nothing)
7102 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7105 /* Copy primary reload reg to secondary reload reg.
7106 (Note that these have been swapped above, then
7107 secondary reload reg to OLD using our insn.) */
7109 /* If REAL_OLD is a paradoxical SUBREG, remove it
7110 and try to put the opposite SUBREG on
7112 if (GET_CODE (real_old) == SUBREG
7113 && (GET_MODE_SIZE (GET_MODE (real_old))
7114 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7115 && 0 != (tem = gen_lowpart_common
7116 (GET_MODE (SUBREG_REG (real_old)),
7118 real_old = SUBREG_REG (real_old), reloadreg = tem;
7120 gen_reload (reloadreg, second_reloadreg,
7121 rl->opnum, rl->when_needed);
7122 emit_insn ((GEN_FCN (tertiary_icode)
7123 (real_old, reloadreg, third_reloadreg)));
7129 /* Copy between the reload regs here and then to
7132 gen_reload (reloadreg, second_reloadreg,
7133 rl->opnum, rl->when_needed);
7134 if (tertiary_reload >= 0)
7136 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7138 gen_reload (third_reloadreg, reloadreg,
7139 rl->opnum, rl->when_needed);
7140 reloadreg = third_reloadreg;
7147 /* Output the last reload insn. */
7152 /* Don't output the last reload if OLD is not the dest of
7153 INSN and is in the src and is clobbered by INSN. */
7154 if (! flag_expensive_optimizations
7156 || !(set = single_set (insn))
7157 || rtx_equal_p (old, SET_DEST (set))
7158 || !reg_mentioned_p (old, SET_SRC (set))
7159 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7160 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7161 gen_reload (old, reloadreg, rl->opnum,
7165 /* Look at all insns we emitted, just to be safe. */
7166 for (p = get_insns (); p; p = NEXT_INSN (p))
7169 rtx pat = PATTERN (p);
7171 /* If this output reload doesn't come from a spill reg,
7172 clear any memory of reloaded copies of the pseudo reg.
7173 If this output reload comes from a spill reg,
7174 reg_has_output_reload will make this do nothing. */
7175 note_stores (pat, forget_old_reloads_1, NULL);
7177 if (reg_mentioned_p (rl->reg_rtx, pat))
7179 rtx set = single_set (insn);
7180 if (reload_spill_index[j] < 0
7182 && SET_SRC (set) == rl->reg_rtx)
7184 int src = REGNO (SET_SRC (set));
7186 reload_spill_index[j] = src;
7187 SET_HARD_REG_BIT (reg_is_output_reload, src);
7188 if (find_regno_note (insn, REG_DEAD, src))
7189 SET_HARD_REG_BIT (reg_reloaded_died, src);
7191 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7193 int s = rl->secondary_out_reload;
7194 set = single_set (p);
7195 /* If this reload copies only to the secondary reload
7196 register, the secondary reload does the actual
7198 if (s >= 0 && set == NULL_RTX)
7199 /* We can't tell what function the secondary reload
7200 has and where the actual store to the pseudo is
7201 made; leave new_spill_reg_store alone. */
7204 && SET_SRC (set) == rl->reg_rtx
7205 && SET_DEST (set) == rld[s].reg_rtx)
7207 /* Usually the next instruction will be the
7208 secondary reload insn; if we can confirm
7209 that it is, setting new_spill_reg_store to
7210 that insn will allow an extra optimization. */
7211 rtx s_reg = rld[s].reg_rtx;
7212 rtx next = NEXT_INSN (p);
7213 rld[s].out = rl->out;
7214 rld[s].out_reg = rl->out_reg;
7215 set = single_set (next);
7216 if (set && SET_SRC (set) == s_reg
7217 && ! new_spill_reg_store[REGNO (s_reg)])
7219 SET_HARD_REG_BIT (reg_is_output_reload,
7221 new_spill_reg_store[REGNO (s_reg)] = next;
7225 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7230 if (rl->when_needed == RELOAD_OTHER)
7232 emit_insn (other_output_reload_insns[rl->opnum]);
7233 other_output_reload_insns[rl->opnum] = get_insns ();
7236 output_reload_insns[rl->opnum] = get_insns ();
7238 if (flag_non_call_exceptions)
7239 copy_eh_notes (insn, get_insns ());
7244 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7245 and has the number J. */
7247 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7249 rtx insn = chain->insn;
7250 rtx old = (rl->in && MEM_P (rl->in)
7251 ? rl->in_reg : rl->in);
7254 /* AUTO_INC reloads need to be handled even if inherited. We got an
7255 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7256 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7257 && ! rtx_equal_p (rl->reg_rtx, old)
7258 && rl->reg_rtx != 0)
7259 emit_input_reload_insns (chain, rld + j, old, j);
7261 /* When inheriting a wider reload, we have a MEM in rl->in,
7262 e.g. inheriting a SImode output reload for
7263 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7264 if (optimize && reload_inherited[j] && rl->in
7266 && MEM_P (rl->in_reg)
7267 && reload_spill_index[j] >= 0
7268 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7269 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7271 /* If we are reloading a register that was recently stored in with an
7272 output-reload, see if we can prove there was
7273 actually no need to store the old value in it. */
7276 && (reload_inherited[j] || reload_override_in[j])
7278 && REG_P (rl->reg_rtx)
7279 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7281 /* There doesn't seem to be any reason to restrict this to pseudos
7282 and doing so loses in the case where we are copying from a
7283 register of the wrong class. */
7284 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7285 >= FIRST_PSEUDO_REGISTER)
7287 /* The insn might have already some references to stackslots
7288 replaced by MEMs, while reload_out_reg still names the
7290 && (dead_or_set_p (insn,
7291 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7292 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7294 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7297 /* Do output reloading for reload RL, which is for the insn described by
7298 CHAIN and has the number J.
7299 ??? At some point we need to support handling output reloads of
7300 JUMP_INSNs or insns that set cc0. */
7302 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7305 rtx insn = chain->insn;
7306 /* If this is an output reload that stores something that is
7307 not loaded in this same reload, see if we can eliminate a previous
7309 rtx pseudo = rl->out_reg;
7314 && ! rtx_equal_p (rl->in_reg, pseudo)
7315 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7316 && reg_last_reload_reg[REGNO (pseudo)])
7318 int pseudo_no = REGNO (pseudo);
7319 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7321 /* We don't need to test full validity of last_regno for
7322 inherit here; we only want to know if the store actually
7323 matches the pseudo. */
7324 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7325 && reg_reloaded_contents[last_regno] == pseudo_no
7326 && spill_reg_store[last_regno]
7327 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7328 delete_output_reload (insn, j, last_regno);
7333 || rl->reg_rtx == old
7334 || rl->reg_rtx == 0)
7337 /* An output operand that dies right away does need a reload,
7338 but need not be copied from it. Show the new location in the
7340 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7341 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7343 XEXP (note, 0) = rl->reg_rtx;
7346 /* Likewise for a SUBREG of an operand that dies. */
7347 else if (GET_CODE (old) == SUBREG
7348 && REG_P (SUBREG_REG (old))
7349 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7352 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7356 else if (GET_CODE (old) == SCRATCH)
7357 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7358 but we don't want to make an output reload. */
7361 /* If is a JUMP_INSN, we can't support output reloads yet. */
7362 gcc_assert (NONJUMP_INSN_P (insn));
7364 emit_output_reload_insns (chain, rld + j, j);
7367 /* Reload number R reloads from or to a group of hard registers starting at
7368 register REGNO. Return true if it can be treated for inheritance purposes
7369 like a group of reloads, each one reloading a single hard register.
7370 The caller has already checked that the spill register and REGNO use
7371 the same number of registers to store the reload value. */
7374 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7376 #ifdef CANNOT_CHANGE_MODE_CLASS
7377 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7378 GET_MODE (rld[r].reg_rtx),
7379 reg_raw_mode[reload_spill_index[r]])
7380 && !REG_CANNOT_CHANGE_MODE_P (regno,
7381 GET_MODE (rld[r].reg_rtx),
7382 reg_raw_mode[regno]));
7388 /* Output insns to reload values in and out of the chosen reload regs. */
7391 emit_reload_insns (struct insn_chain *chain)
7393 rtx insn = chain->insn;
7397 CLEAR_HARD_REG_SET (reg_reloaded_died);
7399 for (j = 0; j < reload_n_operands; j++)
7400 input_reload_insns[j] = input_address_reload_insns[j]
7401 = inpaddr_address_reload_insns[j]
7402 = output_reload_insns[j] = output_address_reload_insns[j]
7403 = outaddr_address_reload_insns[j]
7404 = other_output_reload_insns[j] = 0;
7405 other_input_address_reload_insns = 0;
7406 other_input_reload_insns = 0;
7407 operand_reload_insns = 0;
7408 other_operand_reload_insns = 0;
7410 /* Dump reloads into the dump file. */
7413 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7414 debug_reload_to_stream (dump_file);
7417 /* Now output the instructions to copy the data into and out of the
7418 reload registers. Do these in the order that the reloads were reported,
7419 since reloads of base and index registers precede reloads of operands
7420 and the operands may need the base and index registers reloaded. */
7422 for (j = 0; j < n_reloads; j++)
7425 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7426 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7428 do_input_reload (chain, rld + j, j);
7429 do_output_reload (chain, rld + j, j);
7432 /* Now write all the insns we made for reloads in the order expected by
7433 the allocation functions. Prior to the insn being reloaded, we write
7434 the following reloads:
7436 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7438 RELOAD_OTHER reloads.
7440 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7441 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7442 RELOAD_FOR_INPUT reload for the operand.
7444 RELOAD_FOR_OPADDR_ADDRS reloads.
7446 RELOAD_FOR_OPERAND_ADDRESS reloads.
7448 After the insn being reloaded, we write the following:
7450 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7451 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7452 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7453 reloads for the operand. The RELOAD_OTHER output reloads are
7454 output in descending order by reload number. */
7456 emit_insn_before (other_input_address_reload_insns, insn);
7457 emit_insn_before (other_input_reload_insns, insn);
7459 for (j = 0; j < reload_n_operands; j++)
7461 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7462 emit_insn_before (input_address_reload_insns[j], insn);
7463 emit_insn_before (input_reload_insns[j], insn);
7466 emit_insn_before (other_operand_reload_insns, insn);
7467 emit_insn_before (operand_reload_insns, insn);
7469 for (j = 0; j < reload_n_operands; j++)
7471 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7472 x = emit_insn_after (output_address_reload_insns[j], x);
7473 x = emit_insn_after (output_reload_insns[j], x);
7474 emit_insn_after (other_output_reload_insns[j], x);
7477 /* For all the spill regs newly reloaded in this instruction,
7478 record what they were reloaded from, so subsequent instructions
7479 can inherit the reloads.
7481 Update spill_reg_store for the reloads of this insn.
7482 Copy the elements that were updated in the loop above. */
7484 for (j = 0; j < n_reloads; j++)
7486 int r = reload_order[j];
7487 int i = reload_spill_index[r];
7489 /* If this is a non-inherited input reload from a pseudo, we must
7490 clear any memory of a previous store to the same pseudo. Only do
7491 something if there will not be an output reload for the pseudo
7493 if (rld[r].in_reg != 0
7494 && ! (reload_inherited[r] || reload_override_in[r]))
7496 rtx reg = rld[r].in_reg;
7498 if (GET_CODE (reg) == SUBREG)
7499 reg = SUBREG_REG (reg);
7502 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7503 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7505 int nregno = REGNO (reg);
7507 if (reg_last_reload_reg[nregno])
7509 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7511 if (reg_reloaded_contents[last_regno] == nregno)
7512 spill_reg_store[last_regno] = 0;
7517 /* I is nonneg if this reload used a register.
7518 If rld[r].reg_rtx is 0, this is an optional reload
7519 that we opted to ignore. */
7521 if (i >= 0 && rld[r].reg_rtx != 0)
7523 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7525 int part_reaches_end = 0;
7526 int all_reaches_end = 1;
7528 /* For a multi register reload, we need to check if all or part
7529 of the value lives to the end. */
7530 for (k = 0; k < nr; k++)
7532 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7533 rld[r].when_needed))
7534 part_reaches_end = 1;
7536 all_reaches_end = 0;
7539 /* Ignore reloads that don't reach the end of the insn in
7541 if (all_reaches_end)
7543 /* First, clear out memory of what used to be in this spill reg.
7544 If consecutive registers are used, clear them all. */
7546 for (k = 0; k < nr; k++)
7548 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7549 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7552 /* Maybe the spill reg contains a copy of reload_out. */
7554 && (REG_P (rld[r].out)
7558 || REG_P (rld[r].out_reg)))
7560 rtx out = (REG_P (rld[r].out)
7564 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7565 int nregno = REGNO (out);
7566 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7567 : hard_regno_nregs[nregno]
7568 [GET_MODE (rld[r].reg_rtx)]);
7571 spill_reg_store[i] = new_spill_reg_store[i];
7572 spill_reg_stored_to[i] = out;
7573 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7575 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7577 && inherit_piecemeal_p (r, nregno));
7579 /* If NREGNO is a hard register, it may occupy more than
7580 one register. If it does, say what is in the
7581 rest of the registers assuming that both registers
7582 agree on how many words the object takes. If not,
7583 invalidate the subsequent registers. */
7585 if (nregno < FIRST_PSEUDO_REGISTER)
7586 for (k = 1; k < nnr; k++)
7587 reg_last_reload_reg[nregno + k]
7589 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7592 /* Now do the inverse operation. */
7593 for (k = 0; k < nr; k++)
7595 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7596 reg_reloaded_contents[i + k]
7597 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7600 reg_reloaded_insn[i + k] = insn;
7601 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7602 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7603 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7607 /* Maybe the spill reg contains a copy of reload_in. Only do
7608 something if there will not be an output reload for
7609 the register being reloaded. */
7610 else if (rld[r].out_reg == 0
7612 && ((REG_P (rld[r].in)
7613 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7614 && !REGNO_REG_SET_P (®_has_output_reload,
7616 || (REG_P (rld[r].in_reg)
7617 && !REGNO_REG_SET_P (®_has_output_reload,
7618 REGNO (rld[r].in_reg))))
7619 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7626 if (REG_P (rld[r].in)
7627 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7629 else if (REG_P (rld[r].in_reg))
7632 in = XEXP (rld[r].in_reg, 0);
7633 nregno = REGNO (in);
7635 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7636 : hard_regno_nregs[nregno]
7637 [GET_MODE (rld[r].reg_rtx)]);
7639 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7641 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7643 && inherit_piecemeal_p (r, nregno));
7645 if (nregno < FIRST_PSEUDO_REGISTER)
7646 for (k = 1; k < nnr; k++)
7647 reg_last_reload_reg[nregno + k]
7649 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7652 /* Unless we inherited this reload, show we haven't
7653 recently done a store.
7654 Previous stores of inherited auto_inc expressions
7655 also have to be discarded. */
7656 if (! reload_inherited[r]
7657 || (rld[r].out && ! rld[r].out_reg))
7658 spill_reg_store[i] = 0;
7660 for (k = 0; k < nr; k++)
7662 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7663 reg_reloaded_contents[i + k]
7664 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7667 reg_reloaded_insn[i + k] = insn;
7668 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7669 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7670 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7675 /* However, if part of the reload reaches the end, then we must
7676 invalidate the old info for the part that survives to the end. */
7677 else if (part_reaches_end)
7679 for (k = 0; k < nr; k++)
7680 if (reload_reg_reaches_end_p (i + k,
7682 rld[r].when_needed))
7683 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7687 /* The following if-statement was #if 0'd in 1.34 (or before...).
7688 It's reenabled in 1.35 because supposedly nothing else
7689 deals with this problem. */
7691 /* If a register gets output-reloaded from a non-spill register,
7692 that invalidates any previous reloaded copy of it.
7693 But forget_old_reloads_1 won't get to see it, because
7694 it thinks only about the original insn. So invalidate it here.
7695 Also do the same thing for RELOAD_OTHER constraints where the
7696 output is discarded. */
7698 && ((rld[r].out != 0
7699 && (REG_P (rld[r].out)
7700 || (MEM_P (rld[r].out)
7701 && REG_P (rld[r].out_reg))))
7702 || (rld[r].out == 0 && rld[r].out_reg
7703 && REG_P (rld[r].out_reg))))
7705 rtx out = ((rld[r].out && REG_P (rld[r].out))
7706 ? rld[r].out : rld[r].out_reg);
7707 int nregno = REGNO (out);
7709 /* REG_RTX is now set or clobbered by the main instruction.
7710 As the comment above explains, forget_old_reloads_1 only
7711 sees the original instruction, and there is no guarantee
7712 that the original instruction also clobbered REG_RTX.
7713 For example, if find_reloads sees that the input side of
7714 a matched operand pair dies in this instruction, it may
7715 use the input register as the reload register.
7717 Calling forget_old_reloads_1 is a waste of effort if
7718 REG_RTX is also the output register.
7720 If we know that REG_RTX holds the value of a pseudo
7721 register, the code after the call will record that fact. */
7722 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7723 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7725 if (nregno >= FIRST_PSEUDO_REGISTER)
7727 rtx src_reg, store_insn = NULL_RTX;
7729 reg_last_reload_reg[nregno] = 0;
7731 /* If we can find a hard register that is stored, record
7732 the storing insn so that we may delete this insn with
7733 delete_output_reload. */
7734 src_reg = rld[r].reg_rtx;
7736 /* If this is an optional reload, try to find the source reg
7737 from an input reload. */
7740 rtx set = single_set (insn);
7741 if (set && SET_DEST (set) == rld[r].out)
7745 src_reg = SET_SRC (set);
7747 for (k = 0; k < n_reloads; k++)
7749 if (rld[k].in == src_reg)
7751 src_reg = rld[k].reg_rtx;
7758 store_insn = new_spill_reg_store[REGNO (src_reg)];
7759 if (src_reg && REG_P (src_reg)
7760 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7762 int src_regno = REGNO (src_reg);
7763 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7764 /* The place where to find a death note varies with
7765 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7766 necessarily checked exactly in the code that moves
7767 notes, so just check both locations. */
7768 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7769 if (! note && store_insn)
7770 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7773 spill_reg_store[src_regno + nr] = store_insn;
7774 spill_reg_stored_to[src_regno + nr] = out;
7775 reg_reloaded_contents[src_regno + nr] = nregno;
7776 reg_reloaded_insn[src_regno + nr] = store_insn;
7777 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7778 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7779 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7780 GET_MODE (src_reg)))
7781 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7783 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7785 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7787 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7789 reg_last_reload_reg[nregno] = src_reg;
7790 /* We have to set reg_has_output_reload here, or else
7791 forget_old_reloads_1 will clear reg_last_reload_reg
7793 SET_REGNO_REG_SET (®_has_output_reload,
7799 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7801 while (num_regs-- > 0)
7802 reg_last_reload_reg[nregno + num_regs] = 0;
7806 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7809 /* Go through the motions to emit INSN and test if it is strictly valid.
7810 Return the emitted insn if valid, else return NULL. */
7813 emit_insn_if_valid_for_reload (rtx insn)
7815 rtx last = get_last_insn ();
7818 insn = emit_insn (insn);
7819 code = recog_memoized (insn);
7823 extract_insn (insn);
7824 /* We want constrain operands to treat this insn strictly in its
7825 validity determination, i.e., the way it would after reload has
7827 if (constrain_operands (1))
7831 delete_insns_since (last);
7835 /* Emit code to perform a reload from IN (which may be a reload register) to
7836 OUT (which may also be a reload register). IN or OUT is from operand
7837 OPNUM with reload type TYPE.
7839 Returns first insn emitted. */
7842 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7844 rtx last = get_last_insn ();
7847 /* If IN is a paradoxical SUBREG, remove it and try to put the
7848 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7849 if (GET_CODE (in) == SUBREG
7850 && (GET_MODE_SIZE (GET_MODE (in))
7851 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7852 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7853 in = SUBREG_REG (in), out = tem;
7854 else if (GET_CODE (out) == SUBREG
7855 && (GET_MODE_SIZE (GET_MODE (out))
7856 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7857 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7858 out = SUBREG_REG (out), in = tem;
7860 /* How to do this reload can get quite tricky. Normally, we are being
7861 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7862 register that didn't get a hard register. In that case we can just
7863 call emit_move_insn.
7865 We can also be asked to reload a PLUS that adds a register or a MEM to
7866 another register, constant or MEM. This can occur during frame pointer
7867 elimination and while reloading addresses. This case is handled by
7868 trying to emit a single insn to perform the add. If it is not valid,
7869 we use a two insn sequence.
7871 Or we can be asked to reload an unary operand that was a fragment of
7872 an addressing mode, into a register. If it isn't recognized as-is,
7873 we try making the unop operand and the reload-register the same:
7874 (set reg:X (unop:X expr:Y))
7875 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7877 Finally, we could be called to handle an 'o' constraint by putting
7878 an address into a register. In that case, we first try to do this
7879 with a named pattern of "reload_load_address". If no such pattern
7880 exists, we just emit a SET insn and hope for the best (it will normally
7881 be valid on machines that use 'o').
7883 This entire process is made complex because reload will never
7884 process the insns we generate here and so we must ensure that
7885 they will fit their constraints and also by the fact that parts of
7886 IN might be being reloaded separately and replaced with spill registers.
7887 Because of this, we are, in some sense, just guessing the right approach
7888 here. The one listed above seems to work.
7890 ??? At some point, this whole thing needs to be rethought. */
7892 if (GET_CODE (in) == PLUS
7893 && (REG_P (XEXP (in, 0))
7894 || GET_CODE (XEXP (in, 0)) == SUBREG
7895 || MEM_P (XEXP (in, 0)))
7896 && (REG_P (XEXP (in, 1))
7897 || GET_CODE (XEXP (in, 1)) == SUBREG
7898 || CONSTANT_P (XEXP (in, 1))
7899 || MEM_P (XEXP (in, 1))))
7901 /* We need to compute the sum of a register or a MEM and another
7902 register, constant, or MEM, and put it into the reload
7903 register. The best possible way of doing this is if the machine
7904 has a three-operand ADD insn that accepts the required operands.
7906 The simplest approach is to try to generate such an insn and see if it
7907 is recognized and matches its constraints. If so, it can be used.
7909 It might be better not to actually emit the insn unless it is valid,
7910 but we need to pass the insn as an operand to `recog' and
7911 `extract_insn' and it is simpler to emit and then delete the insn if
7912 not valid than to dummy things up. */
7914 rtx op0, op1, tem, insn;
7917 op0 = find_replacement (&XEXP (in, 0));
7918 op1 = find_replacement (&XEXP (in, 1));
7920 /* Since constraint checking is strict, commutativity won't be
7921 checked, so we need to do that here to avoid spurious failure
7922 if the add instruction is two-address and the second operand
7923 of the add is the same as the reload reg, which is frequently
7924 the case. If the insn would be A = B + A, rearrange it so
7925 it will be A = A + B as constrain_operands expects. */
7927 if (REG_P (XEXP (in, 1))
7928 && REGNO (out) == REGNO (XEXP (in, 1)))
7929 tem = op0, op0 = op1, op1 = tem;
7931 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7932 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7934 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7938 /* If that failed, we must use a conservative two-insn sequence.
7940 Use a move to copy one operand into the reload register. Prefer
7941 to reload a constant, MEM or pseudo since the move patterns can
7942 handle an arbitrary operand. If OP1 is not a constant, MEM or
7943 pseudo and OP1 is not a valid operand for an add instruction, then
7946 After reloading one of the operands into the reload register, add
7947 the reload register to the output register.
7949 If there is another way to do this for a specific machine, a
7950 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7953 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7955 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7957 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7958 || (code != CODE_FOR_nothing
7959 && ! ((*insn_data[code].operand[2].predicate)
7960 (op1, insn_data[code].operand[2].mode))))
7961 tem = op0, op0 = op1, op1 = tem;
7963 gen_reload (out, op0, opnum, type);
7965 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7966 This fixes a problem on the 32K where the stack pointer cannot
7967 be used as an operand of an add insn. */
7969 if (rtx_equal_p (op0, op1))
7972 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7975 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7976 set_unique_reg_note (insn, REG_EQUIV, in);
7980 /* If that failed, copy the address register to the reload register.
7981 Then add the constant to the reload register. */
7983 gcc_assert (!reg_overlap_mentioned_p (out, op0));
7984 gen_reload (out, op1, opnum, type);
7985 insn = emit_insn (gen_add2_insn (out, op0));
7986 set_unique_reg_note (insn, REG_EQUIV, in);
7989 #ifdef SECONDARY_MEMORY_NEEDED
7990 /* If we need a memory location to do the move, do it that way. */
7991 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7992 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7993 && (REG_P (out) || GET_CODE (out) == SUBREG)
7994 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7995 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7996 REGNO_REG_CLASS (reg_or_subregno (out)),
7999 /* Get the memory to use and rewrite both registers to its mode. */
8000 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8002 if (GET_MODE (loc) != GET_MODE (out))
8003 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8005 if (GET_MODE (loc) != GET_MODE (in))
8006 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8008 gen_reload (loc, in, opnum, type);
8009 gen_reload (out, loc, opnum, type);
8012 else if (REG_P (out) && UNARY_P (in))
8019 op1 = find_replacement (&XEXP (in, 0));
8020 if (op1 != XEXP (in, 0))
8021 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8023 /* First, try a plain SET. */
8024 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8028 /* If that failed, move the inner operand to the reload
8029 register, and try the same unop with the inner expression
8030 replaced with the reload register. */
8032 if (GET_MODE (op1) != GET_MODE (out))
8033 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8037 gen_reload (out_moded, op1, opnum, type);
8040 = gen_rtx_SET (VOIDmode, out,
8041 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8043 insn = emit_insn_if_valid_for_reload (insn);
8046 set_unique_reg_note (insn, REG_EQUIV, in);
8050 fatal_insn ("Failure trying to reload:", set);
8052 /* If IN is a simple operand, use gen_move_insn. */
8053 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8055 tem = emit_insn (gen_move_insn (out, in));
8056 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
8057 mark_jump_label (in, tem, 0);
8060 #ifdef HAVE_reload_load_address
8061 else if (HAVE_reload_load_address)
8062 emit_insn (gen_reload_load_address (out, in));
8065 /* Otherwise, just write (set OUT IN) and hope for the best. */
8067 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8069 /* Return the first insn emitted.
8070 We can not just return get_last_insn, because there may have
8071 been multiple instructions emitted. Also note that gen_move_insn may
8072 emit more than one insn itself, so we can not assume that there is one
8073 insn emitted per emit_insn_before call. */
8075 return last ? NEXT_INSN (last) : get_insns ();
8078 /* Delete a previously made output-reload whose result we now believe
8079 is not needed. First we double-check.
8081 INSN is the insn now being processed.
8082 LAST_RELOAD_REG is the hard register number for which we want to delete
8083 the last output reload.
8084 J is the reload-number that originally used REG. The caller has made
8085 certain that reload J doesn't use REG any longer for input. */
8088 delete_output_reload (rtx insn, int j, int last_reload_reg)
8090 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8091 rtx reg = spill_reg_stored_to[last_reload_reg];
8094 int n_inherited = 0;
8098 /* It is possible that this reload has been only used to set another reload
8099 we eliminated earlier and thus deleted this instruction too. */
8100 if (INSN_DELETED_P (output_reload_insn))
8103 /* Get the raw pseudo-register referred to. */
8105 while (GET_CODE (reg) == SUBREG)
8106 reg = SUBREG_REG (reg);
8107 substed = reg_equiv_memory_loc[REGNO (reg)];
8109 /* This is unsafe if the operand occurs more often in the current
8110 insn than it is inherited. */
8111 for (k = n_reloads - 1; k >= 0; k--)
8113 rtx reg2 = rld[k].in;
8116 if (MEM_P (reg2) || reload_override_in[k])
8117 reg2 = rld[k].in_reg;
8119 if (rld[k].out && ! rld[k].out_reg)
8120 reg2 = XEXP (rld[k].in_reg, 0);
8122 while (GET_CODE (reg2) == SUBREG)
8123 reg2 = SUBREG_REG (reg2);
8124 if (rtx_equal_p (reg2, reg))
8126 if (reload_inherited[k] || reload_override_in[k] || k == j)
8132 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8133 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8134 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8137 n_occurrences += count_occurrences (PATTERN (insn),
8138 eliminate_regs (substed, 0,
8140 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8142 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8143 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8145 if (n_occurrences > n_inherited)
8148 /* If the pseudo-reg we are reloading is no longer referenced
8149 anywhere between the store into it and here,
8150 and we're within the same basic block, then the value can only
8151 pass through the reload reg and end up here.
8152 Otherwise, give up--return. */
8153 for (i1 = NEXT_INSN (output_reload_insn);
8154 i1 != insn; i1 = NEXT_INSN (i1))
8156 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8158 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8159 && reg_mentioned_p (reg, PATTERN (i1)))
8161 /* If this is USE in front of INSN, we only have to check that
8162 there are no more references than accounted for by inheritance. */
8163 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8165 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8166 i1 = NEXT_INSN (i1);
8168 if (n_occurrences <= n_inherited && i1 == insn)
8174 /* We will be deleting the insn. Remove the spill reg information. */
8175 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8177 spill_reg_store[last_reload_reg + k] = 0;
8178 spill_reg_stored_to[last_reload_reg + k] = 0;
8181 /* The caller has already checked that REG dies or is set in INSN.
8182 It has also checked that we are optimizing, and thus some
8183 inaccuracies in the debugging information are acceptable.
8184 So we could just delete output_reload_insn. But in some cases
8185 we can improve the debugging information without sacrificing
8186 optimization - maybe even improving the code: See if the pseudo
8187 reg has been completely replaced with reload regs. If so, delete
8188 the store insn and forget we had a stack slot for the pseudo. */
8189 if (rld[j].out != rld[j].in
8190 && REG_N_DEATHS (REGNO (reg)) == 1
8191 && REG_N_SETS (REGNO (reg)) == 1
8192 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8193 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8197 /* We know that it was used only between here and the beginning of
8198 the current basic block. (We also know that the last use before
8199 INSN was the output reload we are thinking of deleting, but never
8200 mind that.) Search that range; see if any ref remains. */
8201 for (i2 = PREV_INSN (insn); i2; i2 = prev)
8205 prev = PREV_INSN (i2);
8206 set = single_set (i2);
8208 /* Uses which just store in the pseudo don't count,
8209 since if they are the only uses, they are dead. */
8210 if (set != 0 && SET_DEST (set) == reg)
8215 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8216 && reg_mentioned_p (reg, PATTERN (i2)))
8218 /* Some other ref remains; just delete the output reload we
8220 delete_address_reloads (output_reload_insn, insn);
8221 delete_insn (output_reload_insn);
8226 /* Delete the now-dead stores into this pseudo. Note that this
8227 loop also takes care of deleting output_reload_insn. */
8228 for (i2 = PREV_INSN (insn); i2; i2 = prev)
8231 prev = PREV_INSN (i2);
8232 set = single_set (i2);
8234 if (set != 0 && SET_DEST (set) == reg)
8236 delete_address_reloads (i2, insn);
8244 /* For the debugging info, say the pseudo lives in this reload reg. */
8245 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8246 alter_reg (REGNO (reg), -1);
8250 delete_address_reloads (output_reload_insn, insn);
8251 delete_insn (output_reload_insn);
8255 /* We are going to delete DEAD_INSN. Recursively delete loads of
8256 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8257 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8259 delete_address_reloads (rtx dead_insn, rtx current_insn)
8261 rtx set = single_set (dead_insn);
8262 rtx set2, dst, prev, next;
8265 rtx dst = SET_DEST (set);
8267 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8269 /* If we deleted the store from a reloaded post_{in,de}c expression,
8270 we can delete the matching adds. */
8271 prev = PREV_INSN (dead_insn);
8272 next = NEXT_INSN (dead_insn);
8273 if (! prev || ! next)
8275 set = single_set (next);
8276 set2 = single_set (prev);
8278 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8279 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8280 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8282 dst = SET_DEST (set);
8283 if (! rtx_equal_p (dst, SET_DEST (set2))
8284 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8285 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8286 || (INTVAL (XEXP (SET_SRC (set), 1))
8287 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8289 delete_related_insns (prev);
8290 delete_related_insns (next);
8293 /* Subfunction of delete_address_reloads: process registers found in X. */
8295 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8297 rtx prev, set, dst, i2;
8299 enum rtx_code code = GET_CODE (x);
8303 const char *fmt = GET_RTX_FORMAT (code);
8304 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8307 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8308 else if (fmt[i] == 'E')
8310 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8311 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8318 if (spill_reg_order[REGNO (x)] < 0)
8321 /* Scan backwards for the insn that sets x. This might be a way back due
8323 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8325 code = GET_CODE (prev);
8326 if (code == CODE_LABEL || code == JUMP_INSN)
8330 if (reg_set_p (x, PATTERN (prev)))
8332 if (reg_referenced_p (x, PATTERN (prev)))
8335 if (! prev || INSN_UID (prev) < reload_first_uid)
8337 /* Check that PREV only sets the reload register. */
8338 set = single_set (prev);
8341 dst = SET_DEST (set);
8343 || ! rtx_equal_p (dst, x))
8345 if (! reg_set_p (dst, PATTERN (dead_insn)))
8347 /* Check if DST was used in a later insn -
8348 it might have been inherited. */
8349 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8355 if (reg_referenced_p (dst, PATTERN (i2)))
8357 /* If there is a reference to the register in the current insn,
8358 it might be loaded in a non-inherited reload. If no other
8359 reload uses it, that means the register is set before
8361 if (i2 == current_insn)
8363 for (j = n_reloads - 1; j >= 0; j--)
8364 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8365 || reload_override_in[j] == dst)
8367 for (j = n_reloads - 1; j >= 0; j--)
8368 if (rld[j].in && rld[j].reg_rtx == dst)
8377 /* If DST is still live at CURRENT_INSN, check if it is used for
8378 any reload. Note that even if CURRENT_INSN sets DST, we still
8379 have to check the reloads. */
8380 if (i2 == current_insn)
8382 for (j = n_reloads - 1; j >= 0; j--)
8383 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8384 || reload_override_in[j] == dst)
8386 /* ??? We can't finish the loop here, because dst might be
8387 allocated to a pseudo in this block if no reload in this
8388 block needs any of the classes containing DST - see
8389 spill_hard_reg. There is no easy way to tell this, so we
8390 have to scan till the end of the basic block. */
8392 if (reg_set_p (dst, PATTERN (i2)))
8396 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8397 reg_reloaded_contents[REGNO (dst)] = -1;
8401 /* Output reload-insns to reload VALUE into RELOADREG.
8402 VALUE is an autoincrement or autodecrement RTX whose operand
8403 is a register or memory location;
8404 so reloading involves incrementing that location.
8405 IN is either identical to VALUE, or some cheaper place to reload from.
8407 INC_AMOUNT is the number to increment or decrement by (always positive).
8408 This cannot be deduced from VALUE.
8410 Return the instruction that stores into RELOADREG. */
8413 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8415 /* REG or MEM to be copied and incremented. */
8416 rtx incloc = find_replacement (&XEXP (value, 0));
8417 /* Nonzero if increment after copying. */
8418 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8419 || GET_CODE (value) == POST_MODIFY);
8425 rtx real_in = in == value ? incloc : in;
8427 /* No hard register is equivalent to this register after
8428 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8429 we could inc/dec that register as well (maybe even using it for
8430 the source), but I'm not sure it's worth worrying about. */
8432 reg_last_reload_reg[REGNO (incloc)] = 0;
8434 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8436 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8437 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8441 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8442 inc_amount = -inc_amount;
8444 inc = GEN_INT (inc_amount);
8447 /* If this is post-increment, first copy the location to the reload reg. */
8448 if (post && real_in != reloadreg)
8449 emit_insn (gen_move_insn (reloadreg, real_in));
8453 /* See if we can directly increment INCLOC. Use a method similar to
8454 that in gen_reload. */
8456 last = get_last_insn ();
8457 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8458 gen_rtx_PLUS (GET_MODE (incloc),
8461 code = recog_memoized (add_insn);
8464 extract_insn (add_insn);
8465 if (constrain_operands (1))
8467 /* If this is a pre-increment and we have incremented the value
8468 where it lives, copy the incremented value to RELOADREG to
8469 be used as an address. */
8472 emit_insn (gen_move_insn (reloadreg, incloc));
8477 delete_insns_since (last);
8480 /* If couldn't do the increment directly, must increment in RELOADREG.
8481 The way we do this depends on whether this is pre- or post-increment.
8482 For pre-increment, copy INCLOC to the reload register, increment it
8483 there, then save back. */
8487 if (in != reloadreg)
8488 emit_insn (gen_move_insn (reloadreg, real_in));
8489 emit_insn (gen_add2_insn (reloadreg, inc));
8490 store = emit_insn (gen_move_insn (incloc, reloadreg));
8495 Because this might be a jump insn or a compare, and because RELOADREG
8496 may not be available after the insn in an input reload, we must do
8497 the incrementation before the insn being reloaded for.
8499 We have already copied IN to RELOADREG. Increment the copy in
8500 RELOADREG, save that back, then decrement RELOADREG so it has
8501 the original value. */
8503 emit_insn (gen_add2_insn (reloadreg, inc));
8504 store = emit_insn (gen_move_insn (incloc, reloadreg));
8505 if (GET_CODE (inc) == CONST_INT)
8506 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8508 emit_insn (gen_sub2_insn (reloadreg, inc));
8516 add_auto_inc_notes (rtx insn, rtx x)
8518 enum rtx_code code = GET_CODE (x);
8522 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8525 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8529 /* Scan all the operand sub-expressions. */
8530 fmt = GET_RTX_FORMAT (code);
8531 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8534 add_auto_inc_notes (insn, XEXP (x, i));
8535 else if (fmt[i] == 'E')
8536 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8537 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8542 /* Copy EH notes from an insn to its reloads. */
8544 copy_eh_notes (rtx insn, rtx x)
8546 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8549 for (; x != 0; x = NEXT_INSN (x))
8551 if (may_trap_p (PATTERN (x)))
8553 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8559 /* This is used by reload pass, that does emit some instructions after
8560 abnormal calls moving basic block end, but in fact it wants to emit
8561 them on the edge. Looks for abnormal call edges, find backward the
8562 proper call and fix the damage.
8564 Similar handle instructions throwing exceptions internally. */
8566 fixup_abnormal_edges (void)
8568 bool inserted = false;
8576 /* Look for cases we are interested in - calls or instructions causing
8578 FOR_EACH_EDGE (e, ei, bb->succs)
8580 if (e->flags & EDGE_ABNORMAL_CALL)
8582 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8583 == (EDGE_ABNORMAL | EDGE_EH))
8586 if (e && !CALL_P (BB_END (bb))
8587 && !can_throw_internal (BB_END (bb)))
8591 /* Get past the new insns generated. Allow notes, as the insns
8592 may be already deleted. */
8594 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8595 && !can_throw_internal (insn)
8596 && insn != BB_HEAD (bb))
8597 insn = PREV_INSN (insn);
8599 if (CALL_P (insn) || can_throw_internal (insn))
8603 stop = NEXT_INSN (BB_END (bb));
8605 insn = NEXT_INSN (insn);
8607 FOR_EACH_EDGE (e, ei, bb->succs)
8608 if (e->flags & EDGE_FALLTHRU)
8611 while (insn && insn != stop)
8613 next = NEXT_INSN (insn);
8618 /* Sometimes there's still the return value USE.
8619 If it's placed after a trapping call (i.e. that
8620 call is the last insn anyway), we have no fallthru
8621 edge. Simply delete this use and don't try to insert
8622 on the non-existent edge. */
8623 if (GET_CODE (PATTERN (insn)) != USE)
8625 /* We're not deleting it, we're moving it. */
8626 INSN_DELETED_P (insn) = 0;
8627 PREV_INSN (insn) = NULL_RTX;
8628 NEXT_INSN (insn) = NULL_RTX;
8630 insert_insn_on_edge (insn, e);
8634 else if (!BARRIER_P (insn))
8635 set_block_for_insn (insn, NULL);
8640 /* It may be that we don't find any such trapping insn. In this
8641 case we discovered quite late that the insn that had been
8642 marked as can_throw_internal in fact couldn't trap at all.
8643 So we should in fact delete the EH edges out of the block. */
8645 purge_dead_edges (bb);
8649 /* We've possibly turned single trapping insn into multiple ones. */
8650 if (flag_non_call_exceptions)
8653 blocks = sbitmap_alloc (last_basic_block);
8654 sbitmap_ones (blocks);
8655 find_many_sub_basic_blocks (blocks);
8656 sbitmap_free (blocks);
8660 commit_edge_insertions ();
8662 #ifdef ENABLE_CHECKING
8663 /* Verify that we didn't turn one trapping insn into many, and that
8664 we found and corrected all of the problems wrt fixups on the
8666 verify_flow_info ();
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