1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
415 rtx, rtx, int, int));
416 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
418 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
420 static int conflicts_with_override PARAMS ((rtx));
421 static void failed_reload PARAMS ((rtx, int));
422 static int set_reload_reg PARAMS ((int, int));
423 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
424 static void choose_reload_regs PARAMS ((struct insn_chain *));
425 static void merge_assigned_reloads PARAMS ((rtx));
426 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
427 struct reload *, rtx, int));
428 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
429 struct reload *, int));
430 static void do_input_reload PARAMS ((struct insn_chain *,
431 struct reload *, int));
432 static void do_output_reload PARAMS ((struct insn_chain *,
433 struct reload *, int));
434 static void emit_reload_insns PARAMS ((struct insn_chain *));
435 static void delete_output_reload PARAMS ((rtx, int, int));
436 static void delete_address_reloads PARAMS ((rtx, rtx));
437 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
438 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
439 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
440 static void reload_cse_regs_1 PARAMS ((rtx));
441 static int reload_cse_noop_set_p PARAMS ((rtx));
442 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
443 static int reload_cse_simplify_operands PARAMS ((rtx));
444 static void reload_combine PARAMS ((void));
445 static void reload_combine_note_use PARAMS ((rtx *, rtx));
446 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
447 static void reload_cse_move2add PARAMS ((rtx));
448 static void move2add_note_store PARAMS ((rtx, rtx, void *));
450 static void add_auto_inc_notes PARAMS ((rtx, rtx));
452 static rtx gen_mode_int PARAMS ((enum machine_mode,
454 static void failed_reload PARAMS ((rtx, int));
455 static int set_reload_reg PARAMS ((int, int));
456 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
457 static void reload_cse_simplify PARAMS ((rtx));
458 extern void dump_needs PARAMS ((struct insn_chain *));
460 /* Initialize the reload pass once per compilation. */
467 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
468 Set spill_indirect_levels to the number of levels such addressing is
469 permitted, zero if it is not permitted at all. */
472 = gen_rtx_MEM (Pmode,
475 LAST_VIRTUAL_REGISTER + 1),
477 spill_indirect_levels = 0;
479 while (memory_address_p (QImode, tem))
481 spill_indirect_levels++;
482 tem = gen_rtx_MEM (Pmode, tem);
485 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
487 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
488 indirect_symref_ok = memory_address_p (QImode, tem);
490 /* See if reg+reg is a valid (and offsettable) address. */
492 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
494 tem = gen_rtx_PLUS (Pmode,
495 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
496 gen_rtx_REG (Pmode, i));
498 /* This way, we make sure that reg+reg is an offsettable address. */
499 tem = plus_constant (tem, 4);
501 if (memory_address_p (QImode, tem))
503 double_reg_address_ok = 1;
508 /* Initialize obstack for our rtl allocation. */
509 gcc_obstack_init (&reload_obstack);
510 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
512 INIT_REG_SET (&spilled_pseudos);
513 INIT_REG_SET (&pseudos_counted);
516 /* List of insn chains that are currently unused. */
517 static struct insn_chain *unused_insn_chains = 0;
519 /* Allocate an empty insn_chain structure. */
523 struct insn_chain *c;
525 if (unused_insn_chains == 0)
527 c = (struct insn_chain *)
528 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
529 INIT_REG_SET (&c->live_throughout);
530 INIT_REG_SET (&c->dead_or_set);
534 c = unused_insn_chains;
535 unused_insn_chains = c->next;
537 c->is_caller_save_insn = 0;
538 c->need_operand_change = 0;
544 /* Small utility function to set all regs in hard reg set TO which are
545 allocated to pseudos in regset FROM. */
548 compute_use_by_pseudos (to, from)
554 EXECUTE_IF_SET_IN_REG_SET
555 (from, FIRST_PSEUDO_REGISTER, regno,
557 int r = reg_renumber[regno];
562 /* reload_combine uses the information from
563 BASIC_BLOCK->global_live_at_start, which might still
564 contain registers that have not actually been allocated
565 since they have an equivalence. */
566 if (! reload_completed)
571 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
573 SET_HARD_REG_BIT (*to, r + nregs);
578 /* Global variables used by reload and its subroutines. */
580 /* Set during calculate_needs if an insn needs register elimination. */
581 static int something_needs_elimination;
582 /* Set during calculate_needs if an insn needs an operand changed. */
583 int something_needs_operands_changed;
585 /* Nonzero means we couldn't get enough spill regs. */
588 /* Main entry point for the reload pass.
590 FIRST is the first insn of the function being compiled.
592 GLOBAL nonzero means we were called from global_alloc
593 and should attempt to reallocate any pseudoregs that we
594 displace from hard regs we will use for reloads.
595 If GLOBAL is zero, we do not have enough information to do that,
596 so any pseudo reg that is spilled must go to the stack.
598 Return value is nonzero if reload failed
599 and we must not do any more for this function. */
602 reload (first, global)
608 register struct elim_table *ep;
610 /* The two pointers used to track the true location of the memory used
611 for label offsets. */
612 char *real_known_ptr = NULL_PTR;
613 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
615 /* Make sure even insns with volatile mem refs are recognizable. */
620 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
622 /* Make sure that the last insn in the chain
623 is not something that needs reloading. */
624 emit_note (NULL_PTR, NOTE_INSN_DELETED);
626 /* Enable find_equiv_reg to distinguish insns made by reload. */
627 reload_first_uid = get_max_uid ();
629 #ifdef SECONDARY_MEMORY_NEEDED
630 /* Initialize the secondary memory table. */
631 clear_secondary_mem ();
634 /* We don't have a stack slot for any spill reg yet. */
635 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
636 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
638 /* Initialize the save area information for caller-save, in case some
642 /* Compute which hard registers are now in use
643 as homes for pseudo registers.
644 This is done here rather than (eg) in global_alloc
645 because this point is reached even if not optimizing. */
646 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
649 /* A function that receives a nonlocal goto must save all call-saved
651 if (current_function_has_nonlocal_label)
652 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
653 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
654 regs_ever_live[i] = 1;
656 /* Find all the pseudo registers that didn't get hard regs
657 but do have known equivalent constants or memory slots.
658 These include parameters (known equivalent to parameter slots)
659 and cse'd or loop-moved constant memory addresses.
661 Record constant equivalents in reg_equiv_constant
662 so they will be substituted by find_reloads.
663 Record memory equivalents in reg_mem_equiv so they can
664 be substituted eventually by altering the REG-rtx's. */
666 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
667 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
672 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
673 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
674 pseudo_forbidden_regs
675 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
677 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
679 CLEAR_HARD_REG_SET (bad_spill_regs_global);
681 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
682 Also find all paradoxical subregs and find largest such for each pseudo.
683 On machines with small register classes, record hard registers that
684 are used for user variables. These can never be used for spills.
685 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
686 caller-saved registers must be marked live. */
688 num_eliminable_invariants = 0;
689 for (insn = first; insn; insn = NEXT_INSN (insn))
691 rtx set = single_set (insn);
693 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
694 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
695 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
696 if (! call_used_regs[i])
697 regs_ever_live[i] = 1;
699 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
701 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
703 #ifdef LEGITIMATE_PIC_OPERAND_P
704 && (! function_invariant_p (XEXP (note, 0))
706 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
710 rtx x = XEXP (note, 0);
711 i = REGNO (SET_DEST (set));
712 if (i > LAST_VIRTUAL_REGISTER)
714 if (GET_CODE (x) == MEM)
716 /* If the operand is a PLUS, the MEM may be shared,
717 so make sure we have an unshared copy here. */
718 if (GET_CODE (XEXP (x, 0)) == PLUS)
721 reg_equiv_memory_loc[i] = x;
723 else if (function_invariant_p (x))
725 if (GET_CODE (x) == PLUS)
727 /* This is PLUS of frame pointer and a constant,
728 and might be shared. Unshare it. */
729 reg_equiv_constant[i] = copy_rtx (x);
730 num_eliminable_invariants++;
732 else if (x == frame_pointer_rtx
733 || x == arg_pointer_rtx)
735 reg_equiv_constant[i] = x;
736 num_eliminable_invariants++;
738 else if (LEGITIMATE_CONSTANT_P (x))
739 reg_equiv_constant[i] = x;
741 reg_equiv_memory_loc[i]
742 = force_const_mem (GET_MODE (SET_DEST (set)), x);
747 /* If this register is being made equivalent to a MEM
748 and the MEM is not SET_SRC, the equivalencing insn
749 is one with the MEM as a SET_DEST and it occurs later.
750 So don't mark this insn now. */
751 if (GET_CODE (x) != MEM
752 || rtx_equal_p (SET_SRC (set), x))
754 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
759 /* If this insn is setting a MEM from a register equivalent to it,
760 this is the equivalencing insn. */
761 else if (set && GET_CODE (SET_DEST (set)) == MEM
762 && GET_CODE (SET_SRC (set)) == REG
763 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
764 && rtx_equal_p (SET_DEST (set),
765 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
766 reg_equiv_init[REGNO (SET_SRC (set))]
767 = gen_rtx_INSN_LIST (VOIDmode, insn,
768 reg_equiv_init[REGNO (SET_SRC (set))]);
771 scan_paradoxical_subregs (PATTERN (insn));
776 num_labels = max_label_num () - get_first_label_num ();
778 /* Allocate the tables used to store offset information at labels. */
779 /* We used to use alloca here, but the size of what it would try to
780 allocate would occasionally cause it to exceed the stack limit and
781 cause a core dump. */
782 real_known_ptr = xmalloc (num_labels);
784 = (int (*)[NUM_ELIMINABLE_REGS])
785 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
787 offsets_known_at = real_known_ptr - get_first_label_num ();
789 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
791 /* Alter each pseudo-reg rtx to contain its hard reg number.
792 Assign stack slots to the pseudos that lack hard regs or equivalents.
793 Do not touch virtual registers. */
795 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
798 /* If we have some registers we think can be eliminated, scan all insns to
799 see if there is an insn that sets one of these registers to something
800 other than itself plus a constant. If so, the register cannot be
801 eliminated. Doing this scan here eliminates an extra pass through the
802 main reload loop in the most common case where register elimination
804 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
805 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
806 || GET_CODE (insn) == CALL_INSN)
807 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
809 maybe_fix_stack_asms ();
811 insns_need_reload = 0;
812 something_needs_elimination = 0;
814 /* Initialize to -1, which means take the first spill register. */
817 /* Spill any hard regs that we know we can't eliminate. */
818 CLEAR_HARD_REG_SET (used_spill_regs);
819 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
820 if (! ep->can_eliminate)
821 spill_hard_reg (ep->from, 1);
823 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
824 if (frame_pointer_needed)
825 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
827 finish_spills (global);
829 /* From now on, we may need to generate moves differently. We may also
830 allow modifications of insns which cause them to not be recognized.
831 Any such modifications will be cleaned up during reload itself. */
832 reload_in_progress = 1;
834 /* This loop scans the entire function each go-round
835 and repeats until one repetition spills no additional hard regs. */
838 int something_changed;
841 HOST_WIDE_INT starting_frame_size;
843 /* Round size of stack frame to stack_alignment_needed. This must be done
844 here because the stack size may be a part of the offset computation
845 for register elimination, and there might have been new stack slots
846 created in the last iteration of this loop. */
847 if (cfun->stack_alignment_needed)
848 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
850 starting_frame_size = get_frame_size ();
852 set_initial_elim_offsets ();
853 set_initial_label_offsets ();
855 /* For each pseudo register that has an equivalent location defined,
856 try to eliminate any eliminable registers (such as the frame pointer)
857 assuming initial offsets for the replacement register, which
860 If the resulting location is directly addressable, substitute
861 the MEM we just got directly for the old REG.
863 If it is not addressable but is a constant or the sum of a hard reg
864 and constant, it is probably not addressable because the constant is
865 out of range, in that case record the address; we will generate
866 hairy code to compute the address in a register each time it is
867 needed. Similarly if it is a hard register, but one that is not
868 valid as an address register.
870 If the location is not addressable, but does not have one of the
871 above forms, assign a stack slot. We have to do this to avoid the
872 potential of producing lots of reloads if, e.g., a location involves
873 a pseudo that didn't get a hard register and has an equivalent memory
874 location that also involves a pseudo that didn't get a hard register.
876 Perhaps at some point we will improve reload_when_needed handling
877 so this problem goes away. But that's very hairy. */
879 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
880 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
882 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
884 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
886 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
887 else if (CONSTANT_P (XEXP (x, 0))
888 || (GET_CODE (XEXP (x, 0)) == REG
889 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
890 || (GET_CODE (XEXP (x, 0)) == PLUS
891 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
892 && (REGNO (XEXP (XEXP (x, 0), 0))
893 < FIRST_PSEUDO_REGISTER)
894 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
895 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
898 /* Make a new stack slot. Then indicate that something
899 changed so we go back and recompute offsets for
900 eliminable registers because the allocation of memory
901 below might change some offset. reg_equiv_{mem,address}
902 will be set up for this pseudo on the next pass around
904 reg_equiv_memory_loc[i] = 0;
905 reg_equiv_init[i] = 0;
910 if (caller_save_needed)
913 /* If we allocated another stack slot, redo elimination bookkeeping. */
914 if (starting_frame_size != get_frame_size ())
917 if (caller_save_needed)
919 save_call_clobbered_regs ();
920 /* That might have allocated new insn_chain structures. */
921 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
924 calculate_needs_all_insns (global);
926 CLEAR_REG_SET (&spilled_pseudos);
929 something_changed = 0;
931 /* If we allocated any new memory locations, make another pass
932 since it might have changed elimination offsets. */
933 if (starting_frame_size != get_frame_size ())
934 something_changed = 1;
937 HARD_REG_SET to_spill;
938 CLEAR_HARD_REG_SET (to_spill);
939 update_eliminables (&to_spill);
940 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
941 if (TEST_HARD_REG_BIT (to_spill, i))
943 spill_hard_reg (i, 1);
946 /* Regardless of the state of spills, if we previously had
947 a register that we thought we could eliminate, but no can
948 not eliminate, we must run another pass.
950 Consider pseudos which have an entry in reg_equiv_* which
951 reference an eliminable register. We must make another pass
952 to update reg_equiv_* so that we do not substitute in the
953 old value from when we thought the elimination could be
955 something_changed = 1;
959 select_reload_regs ();
963 if (insns_need_reload != 0 || did_spill)
964 something_changed |= finish_spills (global);
966 if (! something_changed)
969 if (caller_save_needed)
970 delete_caller_save_insns ();
972 obstack_free (&reload_obstack, reload_firstobj);
975 /* If global-alloc was run, notify it of any register eliminations we have
978 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
979 if (ep->can_eliminate)
980 mark_elimination (ep->from, ep->to);
982 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
983 If that insn didn't set the register (i.e., it copied the register to
984 memory), just delete that insn instead of the equivalencing insn plus
985 anything now dead. If we call delete_dead_insn on that insn, we may
986 delete the insn that actually sets the register if the register dies
987 there and that is incorrect. */
989 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
991 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
994 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
996 rtx equiv_insn = XEXP (list, 0);
997 if (GET_CODE (equiv_insn) == NOTE)
999 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1000 delete_dead_insn (equiv_insn);
1003 PUT_CODE (equiv_insn, NOTE);
1004 NOTE_SOURCE_FILE (equiv_insn) = 0;
1005 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1011 /* Use the reload registers where necessary
1012 by generating move instructions to move the must-be-register
1013 values into or out of the reload registers. */
1015 if (insns_need_reload != 0 || something_needs_elimination
1016 || something_needs_operands_changed)
1018 int old_frame_size = get_frame_size ();
1020 reload_as_needed (global);
1022 if (old_frame_size != get_frame_size ())
1026 verify_initial_elim_offsets ();
1029 /* If we were able to eliminate the frame pointer, show that it is no
1030 longer live at the start of any basic block. If it ls live by
1031 virtue of being in a pseudo, that pseudo will be marked live
1032 and hence the frame pointer will be known to be live via that
1035 if (! frame_pointer_needed)
1036 for (i = 0; i < n_basic_blocks; i++)
1037 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1038 HARD_FRAME_POINTER_REGNUM);
1040 /* Come here (with failure set nonzero) if we can't get enough spill regs
1041 and we decide not to abort about it. */
1044 CLEAR_REG_SET (&spilled_pseudos);
1045 reload_in_progress = 0;
1047 /* Now eliminate all pseudo regs by modifying them into
1048 their equivalent memory references.
1049 The REG-rtx's for the pseudos are modified in place,
1050 so all insns that used to refer to them now refer to memory.
1052 For a reg that has a reg_equiv_address, all those insns
1053 were changed by reloading so that no insns refer to it any longer;
1054 but the DECL_RTL of a variable decl may refer to it,
1055 and if so this causes the debugging info to mention the variable. */
1057 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1062 int is_readonly = 0;
1064 if (reg_equiv_memory_loc[i])
1066 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1067 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1068 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1071 if (reg_equiv_mem[i])
1072 addr = XEXP (reg_equiv_mem[i], 0);
1074 if (reg_equiv_address[i])
1075 addr = reg_equiv_address[i];
1079 if (reg_renumber[i] < 0)
1081 rtx reg = regno_reg_rtx[i];
1082 PUT_CODE (reg, MEM);
1083 XEXP (reg, 0) = addr;
1084 REG_USERVAR_P (reg) = 0;
1085 RTX_UNCHANGING_P (reg) = is_readonly;
1086 MEM_IN_STRUCT_P (reg) = in_struct;
1087 MEM_SCALAR_P (reg) = is_scalar;
1088 /* We have no alias information about this newly created
1090 MEM_ALIAS_SET (reg) = 0;
1092 else if (reg_equiv_mem[i])
1093 XEXP (reg_equiv_mem[i], 0) = addr;
1097 /* We must set reload_completed now since the cleanup_subreg_operands call
1098 below will re-recognize each insn and reload may have generated insns
1099 which are only valid during and after reload. */
1100 reload_completed = 1;
1102 /* Make a pass over all the insns and delete all USEs which we inserted
1103 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1104 notes. Delete all CLOBBER insns that don't refer to the return value
1105 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1106 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1107 and regenerate REG_INC notes that may have been moved around. */
1109 for (insn = first; insn; insn = NEXT_INSN (insn))
1114 if ((GET_CODE (PATTERN (insn)) == USE
1115 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1116 || (GET_CODE (PATTERN (insn)) == CLOBBER
1117 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1118 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1120 PUT_CODE (insn, NOTE);
1121 NOTE_SOURCE_FILE (insn) = 0;
1122 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1126 pnote = ®_NOTES (insn);
1129 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1130 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1131 || REG_NOTE_KIND (*pnote) == REG_INC
1132 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1133 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1134 *pnote = XEXP (*pnote, 1);
1136 pnote = &XEXP (*pnote, 1);
1140 add_auto_inc_notes (insn, PATTERN (insn));
1143 /* And simplify (subreg (reg)) if it appears as an operand. */
1144 cleanup_subreg_operands (insn);
1147 /* If we are doing stack checking, give a warning if this function's
1148 frame size is larger than we expect. */
1149 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1151 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1152 static int verbose_warned = 0;
1154 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1155 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1156 size += UNITS_PER_WORD;
1158 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1160 warning ("frame size too large for reliable stack checking");
1161 if (! verbose_warned)
1163 warning ("try reducing the number of local variables");
1169 /* Indicate that we no longer have known memory locations or constants. */
1170 if (reg_equiv_constant)
1171 free (reg_equiv_constant);
1172 reg_equiv_constant = 0;
1173 if (reg_equiv_memory_loc)
1174 free (reg_equiv_memory_loc);
1175 reg_equiv_memory_loc = 0;
1178 free (real_known_ptr);
1182 free (reg_equiv_mem);
1183 free (reg_equiv_init);
1184 free (reg_equiv_address);
1185 free (reg_max_ref_width);
1186 free (reg_old_renumber);
1187 free (pseudo_previous_regs);
1188 free (pseudo_forbidden_regs);
1190 CLEAR_HARD_REG_SET (used_spill_regs);
1191 for (i = 0; i < n_spills; i++)
1192 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1194 /* Free all the insn_chain structures at once. */
1195 obstack_free (&reload_obstack, reload_startobj);
1196 unused_insn_chains = 0;
1201 /* Yet another special case. Unfortunately, reg-stack forces people to
1202 write incorrect clobbers in asm statements. These clobbers must not
1203 cause the register to appear in bad_spill_regs, otherwise we'll call
1204 fatal_insn later. We clear the corresponding regnos in the live
1205 register sets to avoid this.
1206 The whole thing is rather sick, I'm afraid. */
1209 maybe_fix_stack_asms ()
1212 const char *constraints[MAX_RECOG_OPERANDS];
1213 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1214 struct insn_chain *chain;
1216 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1219 HARD_REG_SET clobbered, allowed;
1222 if (! INSN_P (chain->insn)
1223 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1225 pat = PATTERN (chain->insn);
1226 if (GET_CODE (pat) != PARALLEL)
1229 CLEAR_HARD_REG_SET (clobbered);
1230 CLEAR_HARD_REG_SET (allowed);
1232 /* First, make a mask of all stack regs that are clobbered. */
1233 for (i = 0; i < XVECLEN (pat, 0); i++)
1235 rtx t = XVECEXP (pat, 0, i);
1236 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1237 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1240 /* Get the operand values and constraints out of the insn. */
1241 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1242 constraints, operand_mode);
1244 /* For every operand, see what registers are allowed. */
1245 for (i = 0; i < noperands; i++)
1247 const char *p = constraints[i];
1248 /* For every alternative, we compute the class of registers allowed
1249 for reloading in CLS, and merge its contents into the reg set
1251 int cls = (int) NO_REGS;
1257 if (c == '\0' || c == ',' || c == '#')
1259 /* End of one alternative - mark the regs in the current
1260 class, and reset the class. */
1261 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1266 } while (c != '\0' && c != ',');
1274 case '=': case '+': case '*': case '%': case '?': case '!':
1275 case '0': case '1': case '2': case '3': case '4': case 'm':
1276 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1277 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1278 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1283 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1288 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1292 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1297 /* Those of the registers which are clobbered, but allowed by the
1298 constraints, must be usable as reload registers. So clear them
1299 out of the life information. */
1300 AND_HARD_REG_SET (allowed, clobbered);
1301 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1302 if (TEST_HARD_REG_BIT (allowed, i))
1304 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1305 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1312 /* Copy the global variables n_reloads and rld into the corresponding elts
1315 copy_reloads (chain)
1316 struct insn_chain *chain;
1318 chain->n_reloads = n_reloads;
1320 = (struct reload *) obstack_alloc (&reload_obstack,
1321 n_reloads * sizeof (struct reload));
1322 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1323 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1326 /* Walk the chain of insns, and determine for each whether it needs reloads
1327 and/or eliminations. Build the corresponding insns_need_reload list, and
1328 set something_needs_elimination as appropriate. */
1330 calculate_needs_all_insns (global)
1333 struct insn_chain **pprev_reload = &insns_need_reload;
1334 struct insn_chain *chain, *next = 0;
1336 something_needs_elimination = 0;
1338 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1339 for (chain = reload_insn_chain; chain != 0; chain = next)
1341 rtx insn = chain->insn;
1345 /* Clear out the shortcuts. */
1346 chain->n_reloads = 0;
1347 chain->need_elim = 0;
1348 chain->need_reload = 0;
1349 chain->need_operand_change = 0;
1351 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1352 include REG_LABEL), we need to see what effects this has on the
1353 known offsets at labels. */
1355 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1356 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1357 set_label_offsets (insn, insn, 0);
1361 rtx old_body = PATTERN (insn);
1362 int old_code = INSN_CODE (insn);
1363 rtx old_notes = REG_NOTES (insn);
1364 int did_elimination = 0;
1365 int operands_changed = 0;
1366 rtx set = single_set (insn);
1368 /* Skip insns that only set an equivalence. */
1369 if (set && GET_CODE (SET_DEST (set)) == REG
1370 && reg_renumber[REGNO (SET_DEST (set))] < 0
1371 && reg_equiv_constant[REGNO (SET_DEST (set))])
1374 /* If needed, eliminate any eliminable registers. */
1375 if (num_eliminable || num_eliminable_invariants)
1376 did_elimination = eliminate_regs_in_insn (insn, 0);
1378 /* Analyze the instruction. */
1379 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1380 global, spill_reg_order);
1382 /* If a no-op set needs more than one reload, this is likely
1383 to be something that needs input address reloads. We
1384 can't get rid of this cleanly later, and it is of no use
1385 anyway, so discard it now.
1386 We only do this when expensive_optimizations is enabled,
1387 since this complements reload inheritance / output
1388 reload deletion, and it can make debugging harder. */
1389 if (flag_expensive_optimizations && n_reloads > 1)
1391 rtx set = single_set (insn);
1393 && SET_SRC (set) == SET_DEST (set)
1394 && GET_CODE (SET_SRC (set)) == REG
1395 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1397 PUT_CODE (insn, NOTE);
1398 NOTE_SOURCE_FILE (insn) = 0;
1399 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1400 /* Delete it from the reload chain */
1402 chain->prev->next = next;
1404 reload_insn_chain = next;
1406 next->prev = chain->prev;
1407 chain->next = unused_insn_chains;
1408 unused_insn_chains = chain;
1413 update_eliminable_offsets ();
1415 /* Remember for later shortcuts which insns had any reloads or
1416 register eliminations. */
1417 chain->need_elim = did_elimination;
1418 chain->need_reload = n_reloads > 0;
1419 chain->need_operand_change = operands_changed;
1421 /* Discard any register replacements done. */
1422 if (did_elimination)
1424 obstack_free (&reload_obstack, reload_insn_firstobj);
1425 PATTERN (insn) = old_body;
1426 INSN_CODE (insn) = old_code;
1427 REG_NOTES (insn) = old_notes;
1428 something_needs_elimination = 1;
1431 something_needs_operands_changed |= operands_changed;
1435 copy_reloads (chain);
1436 *pprev_reload = chain;
1437 pprev_reload = &chain->next_need_reload;
1444 /* Comparison function for qsort to decide which of two reloads
1445 should be handled first. *P1 and *P2 are the reload numbers. */
1448 reload_reg_class_lower (r1p, r2p)
1452 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1455 /* Consider required reloads before optional ones. */
1456 t = rld[r1].optional - rld[r2].optional;
1460 /* Count all solitary classes before non-solitary ones. */
1461 t = ((reg_class_size[(int) rld[r2].class] == 1)
1462 - (reg_class_size[(int) rld[r1].class] == 1));
1466 /* Aside from solitaires, consider all multi-reg groups first. */
1467 t = rld[r2].nregs - rld[r1].nregs;
1471 /* Consider reloads in order of increasing reg-class number. */
1472 t = (int) rld[r1].class - (int) rld[r2].class;
1476 /* If reloads are equally urgent, sort by reload number,
1477 so that the results of qsort leave nothing to chance. */
1481 /* The cost of spilling each hard reg. */
1482 static int spill_cost[FIRST_PSEUDO_REGISTER];
1484 /* When spilling multiple hard registers, we use SPILL_COST for the first
1485 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1486 only the first hard reg for a multi-reg pseudo. */
1487 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1489 /* Update the spill cost arrays, considering that pseudo REG is live. */
1495 int n_refs = REG_N_REFS (reg);
1496 int r = reg_renumber[reg];
1499 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1500 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1503 SET_REGNO_REG_SET (&pseudos_counted, reg);
1508 spill_add_cost[r] += n_refs;
1510 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1512 spill_cost[r + nregs] += n_refs;
1515 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1516 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1519 order_regs_for_reload (chain)
1520 struct insn_chain *chain;
1523 HARD_REG_SET used_by_pseudos;
1524 HARD_REG_SET used_by_pseudos2;
1526 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1528 memset (spill_cost, 0, sizeof spill_cost);
1529 memset (spill_add_cost, 0, sizeof spill_add_cost);
1531 /* Count number of uses of each hard reg by pseudo regs allocated to it
1532 and then order them by decreasing use. First exclude hard registers
1533 that are live in or across this insn. */
1535 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1536 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1537 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1538 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1540 /* Now find out which pseudos are allocated to it, and update
1542 CLEAR_REG_SET (&pseudos_counted);
1544 EXECUTE_IF_SET_IN_REG_SET
1545 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1549 EXECUTE_IF_SET_IN_REG_SET
1550 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1554 CLEAR_REG_SET (&pseudos_counted);
1557 /* Vector of reload-numbers showing the order in which the reloads should
1559 static short reload_order[MAX_RELOADS];
1561 /* This is used to keep track of the spill regs used in one insn. */
1562 static HARD_REG_SET used_spill_regs_local;
1564 /* We decided to spill hard register SPILLED, which has a size of
1565 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1566 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1567 update SPILL_COST/SPILL_ADD_COST. */
1570 count_spilled_pseudo (spilled, spilled_nregs, reg)
1571 int spilled, spilled_nregs, reg;
1573 int r = reg_renumber[reg];
1574 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1576 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1577 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1580 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1582 spill_add_cost[r] -= REG_N_REFS (reg);
1584 spill_cost[r + nregs] -= REG_N_REFS (reg);
1587 /* Find reload register to use for reload number ORDER. */
1590 find_reg (chain, order)
1591 struct insn_chain *chain;
1594 int rnum = reload_order[order];
1595 struct reload *rl = rld + rnum;
1596 int best_cost = INT_MAX;
1600 HARD_REG_SET not_usable;
1601 HARD_REG_SET used_by_other_reload;
1603 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1604 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1605 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1607 CLEAR_HARD_REG_SET (used_by_other_reload);
1608 for (k = 0; k < order; k++)
1610 int other = reload_order[k];
1612 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1613 for (j = 0; j < rld[other].nregs; j++)
1614 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1617 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1619 unsigned int regno = i;
1621 if (! TEST_HARD_REG_BIT (not_usable, regno)
1622 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1623 && HARD_REGNO_MODE_OK (regno, rl->mode))
1625 int this_cost = spill_cost[regno];
1627 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1629 for (j = 1; j < this_nregs; j++)
1631 this_cost += spill_add_cost[regno + j];
1632 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1633 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1638 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1640 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1642 if (this_cost < best_cost
1643 /* Among registers with equal cost, prefer caller-saved ones, or
1644 use REG_ALLOC_ORDER if it is defined. */
1645 || (this_cost == best_cost
1646 #ifdef REG_ALLOC_ORDER
1647 && (inv_reg_alloc_order[regno]
1648 < inv_reg_alloc_order[best_reg])
1650 && call_used_regs[regno]
1651 && ! call_used_regs[best_reg]
1656 best_cost = this_cost;
1664 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1666 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1667 rl->regno = best_reg;
1669 EXECUTE_IF_SET_IN_REG_SET
1670 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1672 count_spilled_pseudo (best_reg, rl->nregs, j);
1675 EXECUTE_IF_SET_IN_REG_SET
1676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1678 count_spilled_pseudo (best_reg, rl->nregs, j);
1681 for (i = 0; i < rl->nregs; i++)
1683 if (spill_cost[best_reg + i] != 0
1684 || spill_add_cost[best_reg + i] != 0)
1686 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1691 /* Find more reload regs to satisfy the remaining need of an insn, which
1693 Do it by ascending class number, since otherwise a reg
1694 might be spilled for a big class and might fail to count
1695 for a smaller class even though it belongs to that class. */
1698 find_reload_regs (chain)
1699 struct insn_chain *chain;
1703 /* In order to be certain of getting the registers we need,
1704 we must sort the reloads into order of increasing register class.
1705 Then our grabbing of reload registers will parallel the process
1706 that provided the reload registers. */
1707 for (i = 0; i < chain->n_reloads; i++)
1709 /* Show whether this reload already has a hard reg. */
1710 if (chain->rld[i].reg_rtx)
1712 int regno = REGNO (chain->rld[i].reg_rtx);
1713 chain->rld[i].regno = regno;
1715 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1718 chain->rld[i].regno = -1;
1719 reload_order[i] = i;
1722 n_reloads = chain->n_reloads;
1723 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1725 CLEAR_HARD_REG_SET (used_spill_regs_local);
1728 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1730 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1732 /* Compute the order of preference for hard registers to spill. */
1734 order_regs_for_reload (chain);
1736 for (i = 0; i < n_reloads; i++)
1738 int r = reload_order[i];
1740 /* Ignore reloads that got marked inoperative. */
1741 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1742 && ! rld[r].optional
1743 && rld[r].regno == -1)
1744 if (! find_reg (chain, i))
1746 spill_failure (chain->insn, rld[r].class);
1752 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1753 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1755 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1759 select_reload_regs ()
1761 struct insn_chain *chain;
1763 /* Try to satisfy the needs for each insn. */
1764 for (chain = insns_need_reload; chain != 0;
1765 chain = chain->next_need_reload)
1766 find_reload_regs (chain);
1769 /* Delete all insns that were inserted by emit_caller_save_insns during
1772 delete_caller_save_insns ()
1774 struct insn_chain *c = reload_insn_chain;
1778 while (c != 0 && c->is_caller_save_insn)
1780 struct insn_chain *next = c->next;
1783 if (insn == BLOCK_HEAD (c->block))
1784 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1785 if (insn == BLOCK_END (c->block))
1786 BLOCK_END (c->block) = PREV_INSN (insn);
1787 if (c == reload_insn_chain)
1788 reload_insn_chain = next;
1790 if (NEXT_INSN (insn) != 0)
1791 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1792 if (PREV_INSN (insn) != 0)
1793 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1796 next->prev = c->prev;
1798 c->prev->next = next;
1799 c->next = unused_insn_chains;
1800 unused_insn_chains = c;
1808 /* Handle the failure to find a register to spill.
1809 INSN should be one of the insns which needed this particular spill reg. */
1812 spill_failure (insn, class)
1814 enum reg_class class;
1816 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1817 if (asm_noperands (PATTERN (insn)) >= 0)
1818 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1819 reg_class_names[class]);
1822 error ("Unable to find a register to spill in class `%s'.",
1823 reg_class_names[class]);
1824 fatal_insn ("This is the insn:", insn);
1828 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1829 data that is dead in INSN. */
1832 delete_dead_insn (insn)
1835 rtx prev = prev_real_insn (insn);
1838 /* If the previous insn sets a register that dies in our insn, delete it
1840 if (prev && GET_CODE (PATTERN (prev)) == SET
1841 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1842 && reg_mentioned_p (prev_dest, PATTERN (insn))
1843 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1844 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1845 delete_dead_insn (prev);
1847 PUT_CODE (insn, NOTE);
1848 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1849 NOTE_SOURCE_FILE (insn) = 0;
1852 /* Modify the home of pseudo-reg I.
1853 The new home is present in reg_renumber[I].
1855 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1856 or it may be -1, meaning there is none or it is not relevant.
1857 This is used so that all pseudos spilled from a given hard reg
1858 can share one stack slot. */
1861 alter_reg (i, from_reg)
1865 /* When outputting an inline function, this can happen
1866 for a reg that isn't actually used. */
1867 if (regno_reg_rtx[i] == 0)
1870 /* If the reg got changed to a MEM at rtl-generation time,
1872 if (GET_CODE (regno_reg_rtx[i]) != REG)
1875 /* Modify the reg-rtx to contain the new hard reg
1876 number or else to contain its pseudo reg number. */
1877 REGNO (regno_reg_rtx[i])
1878 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1880 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1881 allocate a stack slot for it. */
1883 if (reg_renumber[i] < 0
1884 && REG_N_REFS (i) > 0
1885 && reg_equiv_constant[i] == 0
1886 && reg_equiv_memory_loc[i] == 0)
1889 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1890 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1893 /* Each pseudo reg has an inherent size which comes from its own mode,
1894 and a total size which provides room for paradoxical subregs
1895 which refer to the pseudo reg in wider modes.
1897 We can use a slot already allocated if it provides both
1898 enough inherent space and enough total space.
1899 Otherwise, we allocate a new slot, making sure that it has no less
1900 inherent space, and no less total space, then the previous slot. */
1903 /* No known place to spill from => no slot to reuse. */
1904 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1905 inherent_size == total_size ? 0 : -1);
1906 if (BYTES_BIG_ENDIAN)
1907 /* Cancel the big-endian correction done in assign_stack_local.
1908 Get the address of the beginning of the slot.
1909 This is so we can do a big-endian correction unconditionally
1911 adjust = inherent_size - total_size;
1913 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1915 /* Nothing can alias this slot except this pseudo. */
1916 MEM_ALIAS_SET (x) = new_alias_set ();
1919 /* Reuse a stack slot if possible. */
1920 else if (spill_stack_slot[from_reg] != 0
1921 && spill_stack_slot_width[from_reg] >= total_size
1922 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1924 x = spill_stack_slot[from_reg];
1926 /* Allocate a bigger slot. */
1929 /* Compute maximum size needed, both for inherent size
1930 and for total size. */
1931 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1934 if (spill_stack_slot[from_reg])
1936 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1938 mode = GET_MODE (spill_stack_slot[from_reg]);
1939 if (spill_stack_slot_width[from_reg] > total_size)
1940 total_size = spill_stack_slot_width[from_reg];
1943 /* Make a slot with that size. */
1944 x = assign_stack_local (mode, total_size,
1945 inherent_size == total_size ? 0 : -1);
1948 /* All pseudos mapped to this slot can alias each other. */
1949 if (spill_stack_slot[from_reg])
1950 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1952 MEM_ALIAS_SET (x) = new_alias_set ();
1954 if (BYTES_BIG_ENDIAN)
1956 /* Cancel the big-endian correction done in assign_stack_local.
1957 Get the address of the beginning of the slot.
1958 This is so we can do a big-endian correction unconditionally
1960 adjust = GET_MODE_SIZE (mode) - total_size;
1962 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1965 plus_constant (XEXP (x, 0), adjust));
1968 spill_stack_slot[from_reg] = stack_slot;
1969 spill_stack_slot_width[from_reg] = total_size;
1972 /* On a big endian machine, the "address" of the slot
1973 is the address of the low part that fits its inherent mode. */
1974 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1975 adjust += (total_size - inherent_size);
1977 /* If we have any adjustment to make, or if the stack slot is the
1978 wrong mode, make a new stack slot. */
1979 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1981 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1982 plus_constant (XEXP (x, 0), adjust));
1984 MEM_COPY_ATTRIBUTES (new, x);
1988 /* Save the stack slot for later. */
1989 reg_equiv_memory_loc[i] = x;
1993 /* Mark the slots in regs_ever_live for the hard regs
1994 used by pseudo-reg number REGNO. */
1997 mark_home_live (regno)
2000 register int i, lim;
2002 i = reg_renumber[regno];
2005 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2007 regs_ever_live[i++] = 1;
2010 /* This function handles the tracking of elimination offsets around branches.
2012 X is a piece of RTL being scanned.
2014 INSN is the insn that it came from, if any.
2016 INITIAL_P is non-zero if we are to set the offset to be the initial
2017 offset and zero if we are setting the offset of the label to be the
2021 set_label_offsets (x, insn, initial_p)
2026 enum rtx_code code = GET_CODE (x);
2029 struct elim_table *p;
2034 if (LABEL_REF_NONLOCAL_P (x))
2039 /* ... fall through ... */
2042 /* If we know nothing about this label, set the desired offsets. Note
2043 that this sets the offset at a label to be the offset before a label
2044 if we don't know anything about the label. This is not correct for
2045 the label after a BARRIER, but is the best guess we can make. If
2046 we guessed wrong, we will suppress an elimination that might have
2047 been possible had we been able to guess correctly. */
2049 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2051 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2052 offsets_at[CODE_LABEL_NUMBER (x)][i]
2053 = (initial_p ? reg_eliminate[i].initial_offset
2054 : reg_eliminate[i].offset);
2055 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2058 /* Otherwise, if this is the definition of a label and it is
2059 preceded by a BARRIER, set our offsets to the known offset of
2063 && (tem = prev_nonnote_insn (insn)) != 0
2064 && GET_CODE (tem) == BARRIER)
2065 set_offsets_for_label (insn);
2067 /* If neither of the above cases is true, compare each offset
2068 with those previously recorded and suppress any eliminations
2069 where the offsets disagree. */
2071 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2072 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2073 != (initial_p ? reg_eliminate[i].initial_offset
2074 : reg_eliminate[i].offset))
2075 reg_eliminate[i].can_eliminate = 0;
2080 set_label_offsets (PATTERN (insn), insn, initial_p);
2082 /* ... fall through ... */
2086 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2087 and hence must have all eliminations at their initial offsets. */
2088 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2089 if (REG_NOTE_KIND (tem) == REG_LABEL)
2090 set_label_offsets (XEXP (tem, 0), insn, 1);
2096 /* Each of the labels in the parallel or address vector must be
2097 at their initial offsets. We want the first field for PARALLEL
2098 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2100 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2101 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2106 /* We only care about setting PC. If the source is not RETURN,
2107 IF_THEN_ELSE, or a label, disable any eliminations not at
2108 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2109 isn't one of those possibilities. For branches to a label,
2110 call ourselves recursively.
2112 Note that this can disable elimination unnecessarily when we have
2113 a non-local goto since it will look like a non-constant jump to
2114 someplace in the current function. This isn't a significant
2115 problem since such jumps will normally be when all elimination
2116 pairs are back to their initial offsets. */
2118 if (SET_DEST (x) != pc_rtx)
2121 switch (GET_CODE (SET_SRC (x)))
2128 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2132 tem = XEXP (SET_SRC (x), 1);
2133 if (GET_CODE (tem) == LABEL_REF)
2134 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2135 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2138 tem = XEXP (SET_SRC (x), 2);
2139 if (GET_CODE (tem) == LABEL_REF)
2140 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2141 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2149 /* If we reach here, all eliminations must be at their initial
2150 offset because we are doing a jump to a variable address. */
2151 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2152 if (p->offset != p->initial_offset)
2153 p->can_eliminate = 0;
2161 /* Scan X and replace any eliminable registers (such as fp) with a
2162 replacement (such as sp), plus an offset.
2164 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2165 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2166 MEM, we are allowed to replace a sum of a register and the constant zero
2167 with the register, which we cannot do outside a MEM. In addition, we need
2168 to record the fact that a register is referenced outside a MEM.
2170 If INSN is an insn, it is the insn containing X. If we replace a REG
2171 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2172 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2173 the REG is being modified.
2175 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2176 That's used when we eliminate in expressions stored in notes.
2177 This means, do not set ref_outside_mem even if the reference
2180 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2181 replacements done assuming all offsets are at their initial values. If
2182 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2183 encounter, return the actual location so that find_reloads will do
2184 the proper thing. */
2187 eliminate_regs (x, mem_mode, insn)
2189 enum machine_mode mem_mode;
2192 enum rtx_code code = GET_CODE (x);
2193 struct elim_table *ep;
2200 if (! current_function_decl)
2219 /* This is only for the benefit of the debugging backends, which call
2220 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2221 removed after CSE. */
2222 new = eliminate_regs (XEXP (x, 0), 0, insn);
2223 if (GET_CODE (new) == MEM)
2224 return XEXP (new, 0);
2230 /* First handle the case where we encounter a bare register that
2231 is eliminable. Replace it with a PLUS. */
2232 if (regno < FIRST_PSEUDO_REGISTER)
2234 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2236 if (ep->from_rtx == x && ep->can_eliminate)
2237 return plus_constant (ep->to_rtx, ep->previous_offset);
2240 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2241 && reg_equiv_constant[regno]
2242 && ! CONSTANT_P (reg_equiv_constant[regno]))
2243 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2247 /* You might think handling MINUS in a manner similar to PLUS is a
2248 good idea. It is not. It has been tried multiple times and every
2249 time the change has had to have been reverted.
2251 Other parts of reload know a PLUS is special (gen_reload for example)
2252 and require special code to handle code a reloaded PLUS operand.
2254 Also consider backends where the flags register is clobbered by a
2255 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2256 lea instruction comes to mind). If we try to reload a MINUS, we
2257 may kill the flags register that was holding a useful value.
2259 So, please before trying to handle MINUS, consider reload as a
2260 whole instead of this little section as well as the backend issues. */
2262 /* If this is the sum of an eliminable register and a constant, rework
2264 if (GET_CODE (XEXP (x, 0)) == REG
2265 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2266 && CONSTANT_P (XEXP (x, 1)))
2268 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2270 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2272 /* The only time we want to replace a PLUS with a REG (this
2273 occurs when the constant operand of the PLUS is the negative
2274 of the offset) is when we are inside a MEM. We won't want
2275 to do so at other times because that would change the
2276 structure of the insn in a way that reload can't handle.
2277 We special-case the commonest situation in
2278 eliminate_regs_in_insn, so just replace a PLUS with a
2279 PLUS here, unless inside a MEM. */
2280 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2281 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2284 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2285 plus_constant (XEXP (x, 1),
2286 ep->previous_offset));
2289 /* If the register is not eliminable, we are done since the other
2290 operand is a constant. */
2294 /* If this is part of an address, we want to bring any constant to the
2295 outermost PLUS. We will do this by doing register replacement in
2296 our operands and seeing if a constant shows up in one of them.
2298 Note that there is no risk of modifying the structure of the insn,
2299 since we only get called for its operands, thus we are either
2300 modifying the address inside a MEM, or something like an address
2301 operand of a load-address insn. */
2304 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2305 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2307 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2309 /* If one side is a PLUS and the other side is a pseudo that
2310 didn't get a hard register but has a reg_equiv_constant,
2311 we must replace the constant here since it may no longer
2312 be in the position of any operand. */
2313 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2314 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2315 && reg_renumber[REGNO (new1)] < 0
2316 && reg_equiv_constant != 0
2317 && reg_equiv_constant[REGNO (new1)] != 0)
2318 new1 = reg_equiv_constant[REGNO (new1)];
2319 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2320 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2321 && reg_renumber[REGNO (new0)] < 0
2322 && reg_equiv_constant[REGNO (new0)] != 0)
2323 new0 = reg_equiv_constant[REGNO (new0)];
2325 new = form_sum (new0, new1);
2327 /* As above, if we are not inside a MEM we do not want to
2328 turn a PLUS into something else. We might try to do so here
2329 for an addition of 0 if we aren't optimizing. */
2330 if (! mem_mode && GET_CODE (new) != PLUS)
2331 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2339 /* If this is the product of an eliminable register and a
2340 constant, apply the distribute law and move the constant out
2341 so that we have (plus (mult ..) ..). This is needed in order
2342 to keep load-address insns valid. This case is pathological.
2343 We ignore the possibility of overflow here. */
2344 if (GET_CODE (XEXP (x, 0)) == REG
2345 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2346 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2347 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2349 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2352 /* Refs inside notes don't count for this purpose. */
2353 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2354 || GET_CODE (insn) == INSN_LIST)))
2355 ep->ref_outside_mem = 1;
2358 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2359 ep->previous_offset * INTVAL (XEXP (x, 1)));
2362 /* ... fall through ... */
2366 /* See comments before PLUS about handling MINUS. */
2368 case DIV: case UDIV:
2369 case MOD: case UMOD:
2370 case AND: case IOR: case XOR:
2371 case ROTATERT: case ROTATE:
2372 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2374 case GE: case GT: case GEU: case GTU:
2375 case LE: case LT: case LEU: case LTU:
2377 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2379 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2381 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2382 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2387 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2390 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2391 if (new != XEXP (x, 0))
2393 /* If this is a REG_DEAD note, it is not valid anymore.
2394 Using the eliminated version could result in creating a
2395 REG_DEAD note for the stack or frame pointer. */
2396 if (GET_MODE (x) == REG_DEAD)
2398 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2401 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2405 /* ... fall through ... */
2408 /* Now do eliminations in the rest of the chain. If this was
2409 an EXPR_LIST, this might result in allocating more memory than is
2410 strictly needed, but it simplifies the code. */
2413 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2414 if (new != XEXP (x, 1))
2415 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2423 case STRICT_LOW_PART:
2425 case SIGN_EXTEND: case ZERO_EXTEND:
2426 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2427 case FLOAT: case FIX:
2428 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2432 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2433 if (new != XEXP (x, 0))
2434 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2438 /* Similar to above processing, but preserve SUBREG_WORD.
2439 Convert (subreg (mem)) to (mem) if not paradoxical.
2440 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2441 pseudo didn't get a hard reg, we must replace this with the
2442 eliminated version of the memory location because push_reloads
2443 may do the replacement in certain circumstances. */
2444 if (GET_CODE (SUBREG_REG (x)) == REG
2445 && (GET_MODE_SIZE (GET_MODE (x))
2446 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2447 && reg_equiv_memory_loc != 0
2448 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2450 new = SUBREG_REG (x);
2453 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2455 if (new != XEXP (x, 0))
2457 int x_size = GET_MODE_SIZE (GET_MODE (x));
2458 int new_size = GET_MODE_SIZE (GET_MODE (new));
2460 if (GET_CODE (new) == MEM
2461 && ((x_size < new_size
2462 #ifdef WORD_REGISTER_OPERATIONS
2463 /* On these machines, combine can create rtl of the form
2464 (set (subreg:m1 (reg:m2 R) 0) ...)
2465 where m1 < m2, and expects something interesting to
2466 happen to the entire word. Moreover, it will use the
2467 (reg:m2 R) later, expecting all bits to be preserved.
2468 So if the number of words is the same, preserve the
2469 subreg so that push_reloads can see it. */
2470 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2473 || (x_size == new_size))
2476 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2477 enum machine_mode mode = GET_MODE (x);
2479 if (BYTES_BIG_ENDIAN)
2480 offset += (MIN (UNITS_PER_WORD,
2481 GET_MODE_SIZE (GET_MODE (new)))
2482 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2484 PUT_MODE (new, mode);
2485 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2489 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2495 /* This is only for the benefit of the debugging backends, which call
2496 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2497 removed after CSE. */
2498 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2499 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2501 /* Our only special processing is to pass the mode of the MEM to our
2502 recursive call and copy the flags. While we are here, handle this
2503 case more efficiently. */
2504 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2505 if (new != XEXP (x, 0))
2507 new = gen_rtx_MEM (GET_MODE (x), new);
2508 MEM_COPY_ATTRIBUTES (new, x);
2524 /* Process each of our operands recursively. If any have changed, make a
2526 fmt = GET_RTX_FORMAT (code);
2527 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2531 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2532 if (new != XEXP (x, i) && ! copied)
2534 rtx new_x = rtx_alloc (code);
2536 (sizeof (*new_x) - sizeof (new_x->fld)
2537 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2543 else if (*fmt == 'E')
2546 for (j = 0; j < XVECLEN (x, i); j++)
2548 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2549 if (new != XVECEXP (x, i, j) && ! copied_vec)
2551 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2555 rtx new_x = rtx_alloc (code);
2557 (sizeof (*new_x) - sizeof (new_x->fld)
2558 + (sizeof (new_x->fld[0])
2559 * GET_RTX_LENGTH (code))));
2563 XVEC (x, i) = new_v;
2566 XVECEXP (x, i, j) = new;
2574 /* Scan rtx X for modifications of elimination target registers. Update
2575 the table of eliminables to reflect the changed state. MEM_MODE is
2576 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2579 elimination_effects (x, mem_mode)
2581 enum machine_mode mem_mode;
2584 enum rtx_code code = GET_CODE (x);
2585 struct elim_table *ep;
2611 /* First handle the case where we encounter a bare register that
2612 is eliminable. Replace it with a PLUS. */
2613 if (regno < FIRST_PSEUDO_REGISTER)
2615 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2617 if (ep->from_rtx == x && ep->can_eliminate)
2620 ep->ref_outside_mem = 1;
2625 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2626 && reg_equiv_constant[regno]
2627 && ! CONSTANT_P (reg_equiv_constant[regno]))
2628 elimination_effects (reg_equiv_constant[regno], mem_mode);
2637 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2638 if (ep->to_rtx == XEXP (x, 0))
2640 int size = GET_MODE_SIZE (mem_mode);
2642 /* If more bytes than MEM_MODE are pushed, account for them. */
2643 #ifdef PUSH_ROUNDING
2644 if (ep->to_rtx == stack_pointer_rtx)
2645 size = PUSH_ROUNDING (size);
2647 if (code == PRE_DEC || code == POST_DEC)
2649 else if (code == PRE_INC || code == POST_INC)
2651 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2652 && GET_CODE (XEXP (x, 1)) == PLUS
2653 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2654 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2655 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2658 /* These two aren't unary operators. */
2659 if (code == POST_MODIFY || code == PRE_MODIFY)
2662 /* Fall through to generic unary operation case. */
2663 case STRICT_LOW_PART:
2665 case SIGN_EXTEND: case ZERO_EXTEND:
2666 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2667 case FLOAT: case FIX:
2668 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2672 elimination_effects (XEXP (x, 0), mem_mode);
2676 if (GET_CODE (SUBREG_REG (x)) == REG
2677 && (GET_MODE_SIZE (GET_MODE (x))
2678 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2679 && reg_equiv_memory_loc != 0
2680 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2683 elimination_effects (SUBREG_REG (x), mem_mode);
2687 /* If using a register that is the source of an eliminate we still
2688 think can be performed, note it cannot be performed since we don't
2689 know how this register is used. */
2690 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2691 if (ep->from_rtx == XEXP (x, 0))
2692 ep->can_eliminate = 0;
2694 elimination_effects (XEXP (x, 0), mem_mode);
2698 /* If clobbering a register that is the replacement register for an
2699 elimination we still think can be performed, note that it cannot
2700 be performed. Otherwise, we need not be concerned about it. */
2701 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2702 if (ep->to_rtx == XEXP (x, 0))
2703 ep->can_eliminate = 0;
2705 elimination_effects (XEXP (x, 0), mem_mode);
2709 /* Check for setting a register that we know about. */
2710 if (GET_CODE (SET_DEST (x)) == REG)
2712 /* See if this is setting the replacement register for an
2715 If DEST is the hard frame pointer, we do nothing because we
2716 assume that all assignments to the frame pointer are for
2717 non-local gotos and are being done at a time when they are valid
2718 and do not disturb anything else. Some machines want to
2719 eliminate a fake argument pointer (or even a fake frame pointer)
2720 with either the real frame or the stack pointer. Assignments to
2721 the hard frame pointer must not prevent this elimination. */
2723 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2725 if (ep->to_rtx == SET_DEST (x)
2726 && SET_DEST (x) != hard_frame_pointer_rtx)
2728 /* If it is being incremented, adjust the offset. Otherwise,
2729 this elimination can't be done. */
2730 rtx src = SET_SRC (x);
2732 if (GET_CODE (src) == PLUS
2733 && XEXP (src, 0) == SET_DEST (x)
2734 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2735 ep->offset -= INTVAL (XEXP (src, 1));
2737 ep->can_eliminate = 0;
2741 elimination_effects (SET_DEST (x), 0);
2742 elimination_effects (SET_SRC (x), 0);
2746 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2749 /* Our only special processing is to pass the mode of the MEM to our
2751 elimination_effects (XEXP (x, 0), GET_MODE (x));
2758 fmt = GET_RTX_FORMAT (code);
2759 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2762 elimination_effects (XEXP (x, i), mem_mode);
2763 else if (*fmt == 'E')
2764 for (j = 0; j < XVECLEN (x, i); j++)
2765 elimination_effects (XVECEXP (x, i, j), mem_mode);
2769 /* Descend through rtx X and verify that no references to eliminable registers
2770 remain. If any do remain, mark the involved register as not
2774 check_eliminable_occurrences (x)
2784 code = GET_CODE (x);
2786 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2788 struct elim_table *ep;
2790 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2791 if (ep->from_rtx == x && ep->can_eliminate)
2792 ep->can_eliminate = 0;
2796 fmt = GET_RTX_FORMAT (code);
2797 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2800 check_eliminable_occurrences (XEXP (x, i));
2801 else if (*fmt == 'E')
2804 for (j = 0; j < XVECLEN (x, i); j++)
2805 check_eliminable_occurrences (XVECEXP (x, i, j));
2810 /* Scan INSN and eliminate all eliminable registers in it.
2812 If REPLACE is nonzero, do the replacement destructively. Also
2813 delete the insn as dead it if it is setting an eliminable register.
2815 If REPLACE is zero, do all our allocations in reload_obstack.
2817 If no eliminations were done and this insn doesn't require any elimination
2818 processing (these are not identical conditions: it might be updating sp,
2819 but not referencing fp; this needs to be seen during reload_as_needed so
2820 that the offset between fp and sp can be taken into consideration), zero
2821 is returned. Otherwise, 1 is returned. */
2824 eliminate_regs_in_insn (insn, replace)
2828 int icode = recog_memoized (insn);
2829 rtx old_body = PATTERN (insn);
2830 int insn_is_asm = asm_noperands (old_body) >= 0;
2831 rtx old_set = single_set (insn);
2835 rtx substed_operand[MAX_RECOG_OPERANDS];
2836 rtx orig_operand[MAX_RECOG_OPERANDS];
2837 struct elim_table *ep;
2839 if (! insn_is_asm && icode < 0)
2841 if (GET_CODE (PATTERN (insn)) == USE
2842 || GET_CODE (PATTERN (insn)) == CLOBBER
2843 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2844 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2845 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2850 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2851 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2853 /* Check for setting an eliminable register. */
2854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2855 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2857 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2858 /* If this is setting the frame pointer register to the
2859 hardware frame pointer register and this is an elimination
2860 that will be done (tested above), this insn is really
2861 adjusting the frame pointer downward to compensate for
2862 the adjustment done before a nonlocal goto. */
2863 if (ep->from == FRAME_POINTER_REGNUM
2864 && ep->to == HARD_FRAME_POINTER_REGNUM)
2866 rtx src = SET_SRC (old_set);
2867 int offset = 0, ok = 0;
2868 rtx prev_insn, prev_set;
2870 if (src == ep->to_rtx)
2872 else if (GET_CODE (src) == PLUS
2873 && GET_CODE (XEXP (src, 0)) == CONST_INT
2874 && XEXP (src, 1) == ep->to_rtx)
2875 offset = INTVAL (XEXP (src, 0)), ok = 1;
2876 else if (GET_CODE (src) == PLUS
2877 && GET_CODE (XEXP (src, 1)) == CONST_INT
2878 && XEXP (src, 0) == ep->to_rtx)
2879 offset = INTVAL (XEXP (src, 1)), ok = 1;
2880 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2881 && (prev_set = single_set (prev_insn)) != 0
2882 && rtx_equal_p (SET_DEST (prev_set), src))
2884 src = SET_SRC (prev_set);
2885 if (src == ep->to_rtx)
2887 else if (GET_CODE (src) == PLUS
2888 && GET_CODE (XEXP (src, 0)) == CONST_INT
2889 && XEXP (src, 1) == ep->to_rtx)
2890 offset = INTVAL (XEXP (src, 0)), ok = 1;
2891 else if (GET_CODE (src) == PLUS
2892 && GET_CODE (XEXP (src, 1)) == CONST_INT
2893 && XEXP (src, 0) == ep->to_rtx)
2894 offset = INTVAL (XEXP (src, 1)), ok = 1;
2902 = plus_constant (ep->to_rtx, offset - ep->offset);
2904 /* First see if this insn remains valid when we
2905 make the change. If not, keep the INSN_CODE
2906 the same and let reload fit it up. */
2907 validate_change (insn, &SET_SRC (old_set), src, 1);
2908 validate_change (insn, &SET_DEST (old_set),
2910 if (! apply_change_group ())
2912 SET_SRC (old_set) = src;
2913 SET_DEST (old_set) = ep->to_rtx;
2923 /* In this case this insn isn't serving a useful purpose. We
2924 will delete it in reload_as_needed once we know that this
2925 elimination is, in fact, being done.
2927 If REPLACE isn't set, we can't delete this insn, but needn't
2928 process it since it won't be used unless something changes. */
2931 delete_dead_insn (insn);
2939 /* We allow one special case which happens to work on all machines we
2940 currently support: a single set with the source being a PLUS of an
2941 eliminable register and a constant. */
2943 && GET_CODE (SET_SRC (old_set)) == PLUS
2944 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2945 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2946 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2948 rtx reg = XEXP (SET_SRC (old_set), 0);
2949 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2951 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2952 if (ep->from_rtx == reg && ep->can_eliminate)
2954 offset += ep->offset;
2959 /* We assume here that if we need a PARALLEL with
2960 CLOBBERs for this assignment, we can do with the
2961 MATCH_SCRATCHes that add_clobbers allocates.
2962 There's not much we can do if that doesn't work. */
2963 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2967 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
2970 rtvec vec = rtvec_alloc (num_clobbers + 1);
2972 vec->elem[0] = PATTERN (insn);
2973 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
2974 add_clobbers (PATTERN (insn), INSN_CODE (insn));
2976 if (INSN_CODE (insn) < 0)
2981 new_body = old_body;
2984 new_body = copy_insn (old_body);
2985 if (REG_NOTES (insn))
2986 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2988 PATTERN (insn) = new_body;
2989 old_set = single_set (insn);
2991 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2992 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2995 /* This can't have an effect on elimination offsets, so skip right
3001 /* Determine the effects of this insn on elimination offsets. */
3002 elimination_effects (old_body, 0);
3004 /* Eliminate all eliminable registers occurring in operands that
3005 can be handled by reload. */
3006 extract_insn (insn);
3008 for (i = 0; i < recog_data.n_operands; i++)
3010 orig_operand[i] = recog_data.operand[i];
3011 substed_operand[i] = recog_data.operand[i];
3013 /* For an asm statement, every operand is eliminable. */
3014 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3016 /* Check for setting a register that we know about. */
3017 if (recog_data.operand_type[i] != OP_IN
3018 && GET_CODE (orig_operand[i]) == REG)
3020 /* If we are assigning to a register that can be eliminated, it
3021 must be as part of a PARALLEL, since the code above handles
3022 single SETs. We must indicate that we can no longer
3023 eliminate this reg. */
3024 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3026 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3027 ep->can_eliminate = 0;
3030 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3031 replace ? insn : NULL_RTX);
3032 if (substed_operand[i] != orig_operand[i])
3033 val = any_changes = 1;
3034 /* Terminate the search in check_eliminable_occurrences at
3036 *recog_data.operand_loc[i] = 0;
3038 /* If an output operand changed from a REG to a MEM and INSN is an
3039 insn, write a CLOBBER insn. */
3040 if (recog_data.operand_type[i] != OP_IN
3041 && GET_CODE (orig_operand[i]) == REG
3042 && GET_CODE (substed_operand[i]) == MEM
3044 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3049 for (i = 0; i < recog_data.n_dups; i++)
3050 *recog_data.dup_loc[i]
3051 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3053 /* If any eliminable remain, they aren't eliminable anymore. */
3054 check_eliminable_occurrences (old_body);
3056 /* Substitute the operands; the new values are in the substed_operand
3058 for (i = 0; i < recog_data.n_operands; i++)
3059 *recog_data.operand_loc[i] = substed_operand[i];
3060 for (i = 0; i < recog_data.n_dups; i++)
3061 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3063 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3064 re-recognize the insn. We do this in case we had a simple addition
3065 but now can do this as a load-address. This saves an insn in this
3067 If re-recognition fails, the old insn code number will still be used,
3068 and some register operands may have changed into PLUS expressions.
3069 These will be handled by find_reloads by loading them into a register
3074 /* If we aren't replacing things permanently and we changed something,
3075 make another copy to ensure that all the RTL is new. Otherwise
3076 things can go wrong if find_reload swaps commutative operands
3077 and one is inside RTL that has been copied while the other is not. */
3078 new_body = old_body;
3081 new_body = copy_insn (old_body);
3082 if (REG_NOTES (insn))
3083 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3085 PATTERN (insn) = new_body;
3087 /* If we had a move insn but now we don't, rerecognize it. This will
3088 cause spurious re-recognition if the old move had a PARALLEL since
3089 the new one still will, but we can't call single_set without
3090 having put NEW_BODY into the insn and the re-recognition won't
3091 hurt in this rare case. */
3092 /* ??? Why this huge if statement - why don't we just rerecognize the
3096 && ((GET_CODE (SET_SRC (old_set)) == REG
3097 && (GET_CODE (new_body) != SET
3098 || GET_CODE (SET_SRC (new_body)) != REG))
3099 /* If this was a load from or store to memory, compare
3100 the MEM in recog_data.operand to the one in the insn.
3101 If they are not equal, then rerecognize the insn. */
3103 && ((GET_CODE (SET_SRC (old_set)) == MEM
3104 && SET_SRC (old_set) != recog_data.operand[1])
3105 || (GET_CODE (SET_DEST (old_set)) == MEM
3106 && SET_DEST (old_set) != recog_data.operand[0])))
3107 /* If this was an add insn before, rerecognize. */
3108 || GET_CODE (SET_SRC (old_set)) == PLUS))
3110 int new_icode = recog (PATTERN (insn), insn, 0);
3112 INSN_CODE (insn) = icode;
3116 /* Restore the old body. If there were any changes to it, we made a copy
3117 of it while the changes were still in place, so we'll correctly return
3118 a modified insn below. */
3121 /* Restore the old body. */
3122 for (i = 0; i < recog_data.n_operands; i++)
3123 *recog_data.operand_loc[i] = orig_operand[i];
3124 for (i = 0; i < recog_data.n_dups; i++)
3125 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3128 /* Update all elimination pairs to reflect the status after the current
3129 insn. The changes we make were determined by the earlier call to
3130 elimination_effects.
3132 We also detect a cases where register elimination cannot be done,
3133 namely, if a register would be both changed and referenced outside a MEM
3134 in the resulting insn since such an insn is often undefined and, even if
3135 not, we cannot know what meaning will be given to it. Note that it is
3136 valid to have a register used in an address in an insn that changes it
3137 (presumably with a pre- or post-increment or decrement).
3139 If anything changes, return nonzero. */
3141 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3143 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3144 ep->can_eliminate = 0;
3146 ep->ref_outside_mem = 0;
3148 if (ep->previous_offset != ep->offset)
3153 /* If we changed something, perform elimination in REG_NOTES. This is
3154 needed even when REPLACE is zero because a REG_DEAD note might refer
3155 to a register that we eliminate and could cause a different number
3156 of spill registers to be needed in the final reload pass than in
3158 if (val && REG_NOTES (insn) != 0)
3159 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3164 /* Loop through all elimination pairs.
3165 Recalculate the number not at initial offset.
3167 Compute the maximum offset (minimum offset if the stack does not
3168 grow downward) for each elimination pair. */
3171 update_eliminable_offsets ()
3173 struct elim_table *ep;
3175 num_not_at_initial_offset = 0;
3176 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3178 ep->previous_offset = ep->offset;
3179 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3180 num_not_at_initial_offset++;
3184 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3185 replacement we currently believe is valid, mark it as not eliminable if X
3186 modifies DEST in any way other than by adding a constant integer to it.
3188 If DEST is the frame pointer, we do nothing because we assume that
3189 all assignments to the hard frame pointer are nonlocal gotos and are being
3190 done at a time when they are valid and do not disturb anything else.
3191 Some machines want to eliminate a fake argument pointer with either the
3192 frame or stack pointer. Assignments to the hard frame pointer must not
3193 prevent this elimination.
3195 Called via note_stores from reload before starting its passes to scan
3196 the insns of the function. */
3199 mark_not_eliminable (dest, x, data)
3202 void *data ATTRIBUTE_UNUSED;
3204 register unsigned int i;
3206 /* A SUBREG of a hard register here is just changing its mode. We should
3207 not see a SUBREG of an eliminable hard register, but check just in
3209 if (GET_CODE (dest) == SUBREG)
3210 dest = SUBREG_REG (dest);
3212 if (dest == hard_frame_pointer_rtx)
3215 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3216 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3217 && (GET_CODE (x) != SET
3218 || GET_CODE (SET_SRC (x)) != PLUS
3219 || XEXP (SET_SRC (x), 0) != dest
3220 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3222 reg_eliminate[i].can_eliminate_previous
3223 = reg_eliminate[i].can_eliminate = 0;
3228 /* Verify that the initial elimination offsets did not change since the
3229 last call to set_initial_elim_offsets. This is used to catch cases
3230 where something illegal happened during reload_as_needed that could
3231 cause incorrect code to be generated if we did not check for it. */
3234 verify_initial_elim_offsets ()
3238 #ifdef ELIMINABLE_REGS
3239 struct elim_table *ep;
3241 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3243 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3244 if (t != ep->initial_offset)
3248 INITIAL_FRAME_POINTER_OFFSET (t);
3249 if (t != reg_eliminate[0].initial_offset)
3254 /* Reset all offsets on eliminable registers to their initial values. */
3257 set_initial_elim_offsets ()
3259 struct elim_table *ep = reg_eliminate;
3261 #ifdef ELIMINABLE_REGS
3262 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3264 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3265 ep->previous_offset = ep->offset = ep->initial_offset;
3268 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3269 ep->previous_offset = ep->offset = ep->initial_offset;
3272 num_not_at_initial_offset = 0;
3275 /* Initialize the known label offsets.
3276 Set a known offset for each forced label to be at the initial offset
3277 of each elimination. We do this because we assume that all
3278 computed jumps occur from a location where each elimination is
3279 at its initial offset.
3280 For all other labels, show that we don't know the offsets. */
3283 set_initial_label_offsets ()
3286 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3288 for (x = forced_labels; x; x = XEXP (x, 1))
3290 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3293 /* Set all elimination offsets to the known values for the code label given
3297 set_offsets_for_label (insn)
3301 int label_nr = CODE_LABEL_NUMBER (insn);
3302 struct elim_table *ep;
3304 num_not_at_initial_offset = 0;
3305 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3307 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3308 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3309 num_not_at_initial_offset++;
3313 /* See if anything that happened changes which eliminations are valid.
3314 For example, on the Sparc, whether or not the frame pointer can
3315 be eliminated can depend on what registers have been used. We need
3316 not check some conditions again (such as flag_omit_frame_pointer)
3317 since they can't have changed. */
3320 update_eliminables (pset)
3323 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3324 int previous_frame_pointer_needed = frame_pointer_needed;
3326 struct elim_table *ep;
3328 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3329 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3330 #ifdef ELIMINABLE_REGS
3331 || ! CAN_ELIMINATE (ep->from, ep->to)
3334 ep->can_eliminate = 0;
3336 /* Look for the case where we have discovered that we can't replace
3337 register A with register B and that means that we will now be
3338 trying to replace register A with register C. This means we can
3339 no longer replace register C with register B and we need to disable
3340 such an elimination, if it exists. This occurs often with A == ap,
3341 B == sp, and C == fp. */
3343 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3345 struct elim_table *op;
3346 register int new_to = -1;
3348 if (! ep->can_eliminate && ep->can_eliminate_previous)
3350 /* Find the current elimination for ep->from, if there is a
3352 for (op = reg_eliminate;
3353 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3354 if (op->from == ep->from && op->can_eliminate)
3360 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3362 for (op = reg_eliminate;
3363 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3364 if (op->from == new_to && op->to == ep->to)
3365 op->can_eliminate = 0;
3369 /* See if any registers that we thought we could eliminate the previous
3370 time are no longer eliminable. If so, something has changed and we
3371 must spill the register. Also, recompute the number of eliminable
3372 registers and see if the frame pointer is needed; it is if there is
3373 no elimination of the frame pointer that we can perform. */
3375 frame_pointer_needed = 1;
3376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3378 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3379 && ep->to != HARD_FRAME_POINTER_REGNUM)
3380 frame_pointer_needed = 0;
3382 if (! ep->can_eliminate && ep->can_eliminate_previous)
3384 ep->can_eliminate_previous = 0;
3385 SET_HARD_REG_BIT (*pset, ep->from);
3390 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3391 /* If we didn't need a frame pointer last time, but we do now, spill
3392 the hard frame pointer. */
3393 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3394 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3398 /* Initialize the table of registers to eliminate. */
3403 struct elim_table *ep;
3404 #ifdef ELIMINABLE_REGS
3405 struct elim_table_1 *ep1;
3409 reg_eliminate = (struct elim_table *)
3410 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3412 /* Does this function require a frame pointer? */
3414 frame_pointer_needed = (! flag_omit_frame_pointer
3415 #ifdef EXIT_IGNORE_STACK
3416 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3417 and restore sp for alloca. So we can't eliminate
3418 the frame pointer in that case. At some point,
3419 we should improve this by emitting the
3420 sp-adjusting insns for this case. */
3421 || (current_function_calls_alloca
3422 && EXIT_IGNORE_STACK)
3424 || FRAME_POINTER_REQUIRED);
3428 #ifdef ELIMINABLE_REGS
3429 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3430 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3432 ep->from = ep1->from;
3434 ep->can_eliminate = ep->can_eliminate_previous
3435 = (CAN_ELIMINATE (ep->from, ep->to)
3436 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3439 reg_eliminate[0].from = reg_eliminate_1[0].from;
3440 reg_eliminate[0].to = reg_eliminate_1[0].to;
3441 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3442 = ! frame_pointer_needed;
3445 /* Count the number of eliminable registers and build the FROM and TO
3446 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3447 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3448 We depend on this. */
3449 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3451 num_eliminable += ep->can_eliminate;
3452 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3453 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3457 /* Kick all pseudos out of hard register REGNO.
3459 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3460 because we found we can't eliminate some register. In the case, no pseudos
3461 are allowed to be in the register, even if they are only in a block that
3462 doesn't require spill registers, unlike the case when we are spilling this
3463 hard reg to produce another spill register.
3465 Return nonzero if any pseudos needed to be kicked out. */
3468 spill_hard_reg (regno, cant_eliminate)
3476 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3477 regs_ever_live[regno] = 1;
3480 /* Spill every pseudo reg that was allocated to this reg
3481 or to something that overlaps this reg. */
3483 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3484 if (reg_renumber[i] >= 0
3485 && (unsigned int) reg_renumber[i] <= regno
3486 && ((unsigned int) reg_renumber[i]
3487 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3488 PSEUDO_REGNO_MODE (i))
3490 SET_REGNO_REG_SET (&spilled_pseudos, i);
3493 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3494 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3497 ior_hard_reg_set (set1, set2)
3498 HARD_REG_SET *set1, *set2;
3500 IOR_HARD_REG_SET (*set1, *set2);
3503 /* After find_reload_regs has been run for all insn that need reloads,
3504 and/or spill_hard_regs was called, this function is used to actually
3505 spill pseudo registers and try to reallocate them. It also sets up the
3506 spill_regs array for use by choose_reload_regs. */
3509 finish_spills (global)
3512 struct insn_chain *chain;
3513 int something_changed = 0;
3516 /* Build the spill_regs array for the function. */
3517 /* If there are some registers still to eliminate and one of the spill regs
3518 wasn't ever used before, additional stack space may have to be
3519 allocated to store this register. Thus, we may have changed the offset
3520 between the stack and frame pointers, so mark that something has changed.
3522 One might think that we need only set VAL to 1 if this is a call-used
3523 register. However, the set of registers that must be saved by the
3524 prologue is not identical to the call-used set. For example, the
3525 register used by the call insn for the return PC is a call-used register,
3526 but must be saved by the prologue. */
3529 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3530 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3532 spill_reg_order[i] = n_spills;
3533 spill_regs[n_spills++] = i;
3534 if (num_eliminable && ! regs_ever_live[i])
3535 something_changed = 1;
3536 regs_ever_live[i] = 1;
3539 spill_reg_order[i] = -1;
3541 EXECUTE_IF_SET_IN_REG_SET
3542 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3544 /* Record the current hard register the pseudo is allocated to in
3545 pseudo_previous_regs so we avoid reallocating it to the same
3546 hard reg in a later pass. */
3547 if (reg_renumber[i] < 0)
3550 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3551 /* Mark it as no longer having a hard register home. */
3552 reg_renumber[i] = -1;
3553 /* We will need to scan everything again. */
3554 something_changed = 1;
3557 /* Retry global register allocation if possible. */
3560 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3561 /* For every insn that needs reloads, set the registers used as spill
3562 regs in pseudo_forbidden_regs for every pseudo live across the
3564 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3566 EXECUTE_IF_SET_IN_REG_SET
3567 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3569 ior_hard_reg_set (pseudo_forbidden_regs + i,
3570 &chain->used_spill_regs);
3572 EXECUTE_IF_SET_IN_REG_SET
3573 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3575 ior_hard_reg_set (pseudo_forbidden_regs + i,
3576 &chain->used_spill_regs);
3580 /* Retry allocating the spilled pseudos. For each reg, merge the
3581 various reg sets that indicate which hard regs can't be used,
3582 and call retry_global_alloc.
3583 We change spill_pseudos here to only contain pseudos that did not
3584 get a new hard register. */
3585 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3586 if (reg_old_renumber[i] != reg_renumber[i])
3588 HARD_REG_SET forbidden;
3589 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3590 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3591 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3592 retry_global_alloc (i, forbidden);
3593 if (reg_renumber[i] >= 0)
3594 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3598 /* Fix up the register information in the insn chain.
3599 This involves deleting those of the spilled pseudos which did not get
3600 a new hard register home from the live_{before,after} sets. */
3601 for (chain = reload_insn_chain; chain; chain = chain->next)
3603 HARD_REG_SET used_by_pseudos;
3604 HARD_REG_SET used_by_pseudos2;
3606 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3607 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3609 /* Mark any unallocated hard regs as available for spills. That
3610 makes inheritance work somewhat better. */
3611 if (chain->need_reload)
3613 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3614 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3615 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3617 /* Save the old value for the sanity test below. */
3618 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3620 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3621 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3622 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3623 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3625 /* Make sure we only enlarge the set. */
3626 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3632 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3633 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3635 int regno = reg_renumber[i];
3636 if (reg_old_renumber[i] == regno)
3639 alter_reg (i, reg_old_renumber[i]);
3640 reg_old_renumber[i] = regno;
3644 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3646 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3647 i, reg_renumber[i]);
3651 return something_changed;
3654 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3655 Also mark any hard registers used to store user variables as
3656 forbidden from being used for spill registers. */
3659 scan_paradoxical_subregs (x)
3663 register const char *fmt;
3664 register enum rtx_code code = GET_CODE (x);
3670 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3671 && REG_USERVAR_P (x))
3672 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3688 if (GET_CODE (SUBREG_REG (x)) == REG
3689 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3690 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3691 = GET_MODE_SIZE (GET_MODE (x));
3698 fmt = GET_RTX_FORMAT (code);
3699 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3702 scan_paradoxical_subregs (XEXP (x, i));
3703 else if (fmt[i] == 'E')
3706 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3707 scan_paradoxical_subregs (XVECEXP (x, i, j));
3712 /* Reload pseudo-registers into hard regs around each insn as needed.
3713 Additional register load insns are output before the insn that needs it
3714 and perhaps store insns after insns that modify the reloaded pseudo reg.
3716 reg_last_reload_reg and reg_reloaded_contents keep track of
3717 which registers are already available in reload registers.
3718 We update these for the reloads that we perform,
3719 as the insns are scanned. */
3722 reload_as_needed (live_known)
3725 struct insn_chain *chain;
3726 #if defined (AUTO_INC_DEC)
3731 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3732 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3733 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3734 reg_has_output_reload = (char *) xmalloc (max_regno);
3735 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3737 set_initial_elim_offsets ();
3739 for (chain = reload_insn_chain; chain; chain = chain->next)
3742 rtx insn = chain->insn;
3743 rtx old_next = NEXT_INSN (insn);
3745 /* If we pass a label, copy the offsets from the label information
3746 into the current offsets of each elimination. */
3747 if (GET_CODE (insn) == CODE_LABEL)
3748 set_offsets_for_label (insn);
3750 else if (INSN_P (insn))
3752 rtx oldpat = PATTERN (insn);
3754 /* If this is a USE and CLOBBER of a MEM, ensure that any
3755 references to eliminable registers have been removed. */
3757 if ((GET_CODE (PATTERN (insn)) == USE
3758 || GET_CODE (PATTERN (insn)) == CLOBBER)
3759 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3760 XEXP (XEXP (PATTERN (insn), 0), 0)
3761 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3762 GET_MODE (XEXP (PATTERN (insn), 0)),
3765 /* If we need to do register elimination processing, do so.
3766 This might delete the insn, in which case we are done. */
3767 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3769 eliminate_regs_in_insn (insn, 1);
3770 if (GET_CODE (insn) == NOTE)
3772 update_eliminable_offsets ();
3777 /* If need_elim is nonzero but need_reload is zero, one might think
3778 that we could simply set n_reloads to 0. However, find_reloads
3779 could have done some manipulation of the insn (such as swapping
3780 commutative operands), and these manipulations are lost during
3781 the first pass for every insn that needs register elimination.
3782 So the actions of find_reloads must be redone here. */
3784 if (! chain->need_elim && ! chain->need_reload
3785 && ! chain->need_operand_change)
3787 /* First find the pseudo regs that must be reloaded for this insn.
3788 This info is returned in the tables reload_... (see reload.h).
3789 Also modify the body of INSN by substituting RELOAD
3790 rtx's for those pseudo regs. */
3793 memset (reg_has_output_reload, 0, max_regno);
3794 CLEAR_HARD_REG_SET (reg_is_output_reload);
3796 find_reloads (insn, 1, spill_indirect_levels, live_known,
3800 if (num_eliminable && chain->need_elim)
3801 update_eliminable_offsets ();
3805 rtx next = NEXT_INSN (insn);
3808 prev = PREV_INSN (insn);
3810 /* Now compute which reload regs to reload them into. Perhaps
3811 reusing reload regs from previous insns, or else output
3812 load insns to reload them. Maybe output store insns too.
3813 Record the choices of reload reg in reload_reg_rtx. */
3814 choose_reload_regs (chain);
3816 /* Merge any reloads that we didn't combine for fear of
3817 increasing the number of spill registers needed but now
3818 discover can be safely merged. */
3819 if (SMALL_REGISTER_CLASSES)
3820 merge_assigned_reloads (insn);
3822 /* Generate the insns to reload operands into or out of
3823 their reload regs. */
3824 emit_reload_insns (chain);
3826 /* Substitute the chosen reload regs from reload_reg_rtx
3827 into the insn's body (or perhaps into the bodies of other
3828 load and store insn that we just made for reloading
3829 and that we moved the structure into). */
3832 /* If this was an ASM, make sure that all the reload insns
3833 we have generated are valid. If not, give an error
3836 if (asm_noperands (PATTERN (insn)) >= 0)
3837 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3838 if (p != insn && INSN_P (p)
3839 && (recog_memoized (p) < 0
3840 || (extract_insn (p), ! constrain_operands (1))))
3842 error_for_asm (insn,
3843 "`asm' operand requires impossible reload");
3845 NOTE_SOURCE_FILE (p) = 0;
3846 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3849 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3850 is no longer validly lying around to save a future reload.
3851 Note that this does not detect pseudos that were reloaded
3852 for this insn in order to be stored in
3853 (obeying register constraints). That is correct; such reload
3854 registers ARE still valid. */
3855 note_stores (oldpat, forget_old_reloads_1, NULL);
3857 /* There may have been CLOBBER insns placed after INSN. So scan
3858 between INSN and NEXT and use them to forget old reloads. */
3859 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3860 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3861 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3864 /* Likewise for regs altered by auto-increment in this insn.
3865 REG_INC notes have been changed by reloading:
3866 find_reloads_address_1 records substitutions for them,
3867 which have been performed by subst_reloads above. */
3868 for (i = n_reloads - 1; i >= 0; i--)
3870 rtx in_reg = rld[i].in_reg;
3873 enum rtx_code code = GET_CODE (in_reg);
3874 /* PRE_INC / PRE_DEC will have the reload register ending up
3875 with the same value as the stack slot, but that doesn't
3876 hold true for POST_INC / POST_DEC. Either we have to
3877 convert the memory access to a true POST_INC / POST_DEC,
3878 or we can't use the reload register for inheritance. */
3879 if ((code == POST_INC || code == POST_DEC)
3880 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3881 REGNO (rld[i].reg_rtx))
3882 /* Make sure it is the inc/dec pseudo, and not
3883 some other (e.g. output operand) pseudo. */
3884 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3885 == REGNO (XEXP (in_reg, 0))))
3888 rtx reload_reg = rld[i].reg_rtx;
3889 enum machine_mode mode = GET_MODE (reload_reg);
3893 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3895 /* We really want to ignore REG_INC notes here, so
3896 use PATTERN (p) as argument to reg_set_p . */
3897 if (reg_set_p (reload_reg, PATTERN (p)))
3899 n = count_occurrences (PATTERN (p), reload_reg, 0);
3904 n = validate_replace_rtx (reload_reg,
3905 gen_rtx (code, mode,
3909 /* We must also verify that the constraints
3910 are met after the replacement. */
3913 n = constrain_operands (1);
3917 /* If the constraints were not met, then
3918 undo the replacement. */
3921 validate_replace_rtx (gen_rtx (code, mode,
3933 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3935 /* Mark this as having an output reload so that the
3936 REG_INC processing code below won't invalidate
3937 the reload for inheritance. */
3938 SET_HARD_REG_BIT (reg_is_output_reload,
3939 REGNO (reload_reg));
3940 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3943 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3946 else if ((code == PRE_INC || code == PRE_DEC)
3947 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3948 REGNO (rld[i].reg_rtx))
3949 /* Make sure it is the inc/dec pseudo, and not
3950 some other (e.g. output operand) pseudo. */
3951 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3952 == REGNO (XEXP (in_reg, 0))))
3954 SET_HARD_REG_BIT (reg_is_output_reload,
3955 REGNO (rld[i].reg_rtx));
3956 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3960 /* If a pseudo that got a hard register is auto-incremented,
3961 we must purge records of copying it into pseudos without
3963 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3964 if (REG_NOTE_KIND (x) == REG_INC)
3966 /* See if this pseudo reg was reloaded in this insn.
3967 If so, its last-reload info is still valid
3968 because it is based on this insn's reload. */
3969 for (i = 0; i < n_reloads; i++)
3970 if (rld[i].out == XEXP (x, 0))
3974 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3978 /* A reload reg's contents are unknown after a label. */
3979 if (GET_CODE (insn) == CODE_LABEL)
3980 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3982 /* Don't assume a reload reg is still good after a call insn
3983 if it is a call-used reg. */
3984 else if (GET_CODE (insn) == CALL_INSN)
3985 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3989 free (reg_last_reload_reg);
3990 free (reg_has_output_reload);
3993 /* Discard all record of any value reloaded from X,
3994 or reloaded in X from someplace else;
3995 unless X is an output reload reg of the current insn.
3997 X may be a hard reg (the reload reg)
3998 or it may be a pseudo reg that was reloaded from. */
4001 forget_old_reloads_1 (x, ignored, data)
4003 rtx ignored ATTRIBUTE_UNUSED;
4004 void *data ATTRIBUTE_UNUSED;
4010 /* note_stores does give us subregs of hard regs. */
4011 while (GET_CODE (x) == SUBREG)
4013 offset += SUBREG_WORD (x);
4017 if (GET_CODE (x) != REG)
4020 regno = REGNO (x) + offset;
4022 if (regno >= FIRST_PSEUDO_REGISTER)
4028 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4029 /* Storing into a spilled-reg invalidates its contents.
4030 This can happen if a block-local pseudo is allocated to that reg
4031 and it wasn't spilled because this block's total need is 0.
4032 Then some insn might have an optional reload and use this reg. */
4033 for (i = 0; i < nr; i++)
4034 /* But don't do this if the reg actually serves as an output
4035 reload reg in the current instruction. */
4037 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4039 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4040 spill_reg_store[regno + i] = 0;
4044 /* Since value of X has changed,
4045 forget any value previously copied from it. */
4048 /* But don't forget a copy if this is the output reload
4049 that establishes the copy's validity. */
4050 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4051 reg_last_reload_reg[regno + nr] = 0;
4054 /* The following HARD_REG_SETs indicate when each hard register is
4055 used for a reload of various parts of the current insn. */
4057 /* If reg is unavailable for all reloads. */
4058 static HARD_REG_SET reload_reg_unavailable;
4059 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4060 static HARD_REG_SET reload_reg_used;
4061 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4062 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4063 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4064 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4065 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4066 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4067 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4068 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4069 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4070 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4071 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4072 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4073 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4074 static HARD_REG_SET reload_reg_used_in_op_addr;
4075 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4076 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4077 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4078 static HARD_REG_SET reload_reg_used_in_insn;
4079 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4080 static HARD_REG_SET reload_reg_used_in_other_addr;
4082 /* If reg is in use as a reload reg for any sort of reload. */
4083 static HARD_REG_SET reload_reg_used_at_all;
4085 /* If reg is use as an inherited reload. We just mark the first register
4087 static HARD_REG_SET reload_reg_used_for_inherit;
4089 /* Records which hard regs are used in any way, either as explicit use or
4090 by being allocated to a pseudo during any point of the current insn. */
4091 static HARD_REG_SET reg_used_in_insn;
4093 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4094 TYPE. MODE is used to indicate how many consecutive regs are
4098 mark_reload_reg_in_use (regno, opnum, type, mode)
4101 enum reload_type type;
4102 enum machine_mode mode;
4104 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4107 for (i = regno; i < nregs + regno; i++)
4112 SET_HARD_REG_BIT (reload_reg_used, i);
4115 case RELOAD_FOR_INPUT_ADDRESS:
4116 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4119 case RELOAD_FOR_INPADDR_ADDRESS:
4120 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4123 case RELOAD_FOR_OUTPUT_ADDRESS:
4124 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4127 case RELOAD_FOR_OUTADDR_ADDRESS:
4128 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4131 case RELOAD_FOR_OPERAND_ADDRESS:
4132 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4135 case RELOAD_FOR_OPADDR_ADDR:
4136 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4139 case RELOAD_FOR_OTHER_ADDRESS:
4140 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4143 case RELOAD_FOR_INPUT:
4144 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4147 case RELOAD_FOR_OUTPUT:
4148 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4151 case RELOAD_FOR_INSN:
4152 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4156 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4160 /* Similarly, but show REGNO is no longer in use for a reload. */
4163 clear_reload_reg_in_use (regno, opnum, type, mode)
4166 enum reload_type type;
4167 enum machine_mode mode;
4169 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4170 unsigned int start_regno, end_regno, r;
4172 /* A complication is that for some reload types, inheritance might
4173 allow multiple reloads of the same types to share a reload register.
4174 We set check_opnum if we have to check only reloads with the same
4175 operand number, and check_any if we have to check all reloads. */
4176 int check_opnum = 0;
4178 HARD_REG_SET *used_in_set;
4183 used_in_set = &reload_reg_used;
4186 case RELOAD_FOR_INPUT_ADDRESS:
4187 used_in_set = &reload_reg_used_in_input_addr[opnum];
4190 case RELOAD_FOR_INPADDR_ADDRESS:
4192 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4195 case RELOAD_FOR_OUTPUT_ADDRESS:
4196 used_in_set = &reload_reg_used_in_output_addr[opnum];
4199 case RELOAD_FOR_OUTADDR_ADDRESS:
4201 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4204 case RELOAD_FOR_OPERAND_ADDRESS:
4205 used_in_set = &reload_reg_used_in_op_addr;
4208 case RELOAD_FOR_OPADDR_ADDR:
4210 used_in_set = &reload_reg_used_in_op_addr_reload;
4213 case RELOAD_FOR_OTHER_ADDRESS:
4214 used_in_set = &reload_reg_used_in_other_addr;
4218 case RELOAD_FOR_INPUT:
4219 used_in_set = &reload_reg_used_in_input[opnum];
4222 case RELOAD_FOR_OUTPUT:
4223 used_in_set = &reload_reg_used_in_output[opnum];
4226 case RELOAD_FOR_INSN:
4227 used_in_set = &reload_reg_used_in_insn;
4232 /* We resolve conflicts with remaining reloads of the same type by
4233 excluding the intervals of of reload registers by them from the
4234 interval of freed reload registers. Since we only keep track of
4235 one set of interval bounds, we might have to exclude somewhat
4236 more then what would be necessary if we used a HARD_REG_SET here.
4237 But this should only happen very infrequently, so there should
4238 be no reason to worry about it. */
4240 start_regno = regno;
4241 end_regno = regno + nregs;
4242 if (check_opnum || check_any)
4244 for (i = n_reloads - 1; i >= 0; i--)
4246 if (rld[i].when_needed == type
4247 && (check_any || rld[i].opnum == opnum)
4250 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4251 unsigned int conflict_end
4253 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4255 /* If there is an overlap with the first to-be-freed register,
4256 adjust the interval start. */
4257 if (conflict_start <= start_regno && conflict_end > start_regno)
4258 start_regno = conflict_end;
4259 /* Otherwise, if there is a conflict with one of the other
4260 to-be-freed registers, adjust the interval end. */
4261 if (conflict_start > start_regno && conflict_start < end_regno)
4262 end_regno = conflict_start;
4267 for (r = start_regno; r < end_regno; r++)
4268 CLEAR_HARD_REG_BIT (*used_in_set, r);
4271 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4272 specified by OPNUM and TYPE. */
4275 reload_reg_free_p (regno, opnum, type)
4278 enum reload_type type;
4282 /* In use for a RELOAD_OTHER means it's not available for anything. */
4283 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4284 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4290 /* In use for anything means we can't use it for RELOAD_OTHER. */
4291 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4292 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4293 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4296 for (i = 0; i < reload_n_operands; i++)
4297 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4298 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4299 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4300 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4301 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4302 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4307 case RELOAD_FOR_INPUT:
4308 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4309 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4312 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4315 /* If it is used for some other input, can't use it. */
4316 for (i = 0; i < reload_n_operands; i++)
4317 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4320 /* If it is used in a later operand's address, can't use it. */
4321 for (i = opnum + 1; i < reload_n_operands; i++)
4322 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4323 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4328 case RELOAD_FOR_INPUT_ADDRESS:
4329 /* Can't use a register if it is used for an input address for this
4330 operand or used as an input in an earlier one. */
4331 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4332 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4335 for (i = 0; i < opnum; i++)
4336 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4341 case RELOAD_FOR_INPADDR_ADDRESS:
4342 /* Can't use a register if it is used for an input address
4343 for this operand or used as an input in an earlier
4345 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4348 for (i = 0; i < opnum; i++)
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4354 case RELOAD_FOR_OUTPUT_ADDRESS:
4355 /* Can't use a register if it is used for an output address for this
4356 operand or used as an output in this or a later operand. */
4357 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4360 for (i = opnum; i < reload_n_operands; i++)
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4366 case RELOAD_FOR_OUTADDR_ADDRESS:
4367 /* Can't use a register if it is used for an output address
4368 for this operand or used as an output in this or a
4370 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4373 for (i = opnum; i < reload_n_operands; i++)
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4379 case RELOAD_FOR_OPERAND_ADDRESS:
4380 for (i = 0; i < reload_n_operands; i++)
4381 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4384 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4385 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4387 case RELOAD_FOR_OPADDR_ADDR:
4388 for (i = 0; i < reload_n_operands; i++)
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4392 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4394 case RELOAD_FOR_OUTPUT:
4395 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4396 outputs, or an operand address for this or an earlier output. */
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4400 for (i = 0; i < reload_n_operands; i++)
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4404 for (i = 0; i <= opnum; i++)
4405 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4406 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4411 case RELOAD_FOR_INSN:
4412 for (i = 0; i < reload_n_operands; i++)
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4414 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4417 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4418 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4420 case RELOAD_FOR_OTHER_ADDRESS:
4421 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4426 /* Return 1 if the value in reload reg REGNO, as used by a reload
4427 needed for the part of the insn specified by OPNUM and TYPE,
4428 is still available in REGNO at the end of the insn.
4430 We can assume that the reload reg was already tested for availability
4431 at the time it is needed, and we should not check this again,
4432 in case the reg has already been marked in use. */
4435 reload_reg_reaches_end_p (regno, opnum, type)
4438 enum reload_type type;
4445 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4446 its value must reach the end. */
4449 /* If this use is for part of the insn,
4450 its value reaches if no subsequent part uses the same register.
4451 Just like the above function, don't try to do this with lots
4454 case RELOAD_FOR_OTHER_ADDRESS:
4455 /* Here we check for everything else, since these don't conflict
4456 with anything else and everything comes later. */
4458 for (i = 0; i < reload_n_operands; i++)
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4460 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4462 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4464 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4467 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4468 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4469 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4471 case RELOAD_FOR_INPUT_ADDRESS:
4472 case RELOAD_FOR_INPADDR_ADDRESS:
4473 /* Similar, except that we check only for this and subsequent inputs
4474 and the address of only subsequent inputs and we do not need
4475 to check for RELOAD_OTHER objects since they are known not to
4478 for (i = opnum; i < reload_n_operands; i++)
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4482 for (i = opnum + 1; i < reload_n_operands; i++)
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4484 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4487 for (i = 0; i < reload_n_operands; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4489 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4490 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4493 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4496 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4497 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4498 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4500 case RELOAD_FOR_INPUT:
4501 /* Similar to input address, except we start at the next operand for
4502 both input and input address and we do not check for
4503 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4506 for (i = opnum + 1; i < reload_n_operands; i++)
4507 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4508 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4512 /* ... fall through ... */
4514 case RELOAD_FOR_OPERAND_ADDRESS:
4515 /* Check outputs and their addresses. */
4517 for (i = 0; i < reload_n_operands; i++)
4518 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4519 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4520 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4523 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4525 case RELOAD_FOR_OPADDR_ADDR:
4526 for (i = 0; i < reload_n_operands; i++)
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4532 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4533 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4534 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4536 case RELOAD_FOR_INSN:
4537 /* These conflict with other outputs with RELOAD_OTHER. So
4538 we need only check for output addresses. */
4542 /* ... fall through ... */
4544 case RELOAD_FOR_OUTPUT:
4545 case RELOAD_FOR_OUTPUT_ADDRESS:
4546 case RELOAD_FOR_OUTADDR_ADDRESS:
4547 /* We already know these can't conflict with a later output. So the
4548 only thing to check are later output addresses. */
4549 for (i = opnum + 1; i < reload_n_operands; i++)
4550 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4551 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4560 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4563 This function uses the same algorithm as reload_reg_free_p above. */
4566 reloads_conflict (r1, r2)
4569 enum reload_type r1_type = rld[r1].when_needed;
4570 enum reload_type r2_type = rld[r2].when_needed;
4571 int r1_opnum = rld[r1].opnum;
4572 int r2_opnum = rld[r2].opnum;
4574 /* RELOAD_OTHER conflicts with everything. */
4575 if (r2_type == RELOAD_OTHER)
4578 /* Otherwise, check conflicts differently for each type. */
4582 case RELOAD_FOR_INPUT:
4583 return (r2_type == RELOAD_FOR_INSN
4584 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4585 || r2_type == RELOAD_FOR_OPADDR_ADDR
4586 || r2_type == RELOAD_FOR_INPUT
4587 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4588 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4589 && r2_opnum > r1_opnum));
4591 case RELOAD_FOR_INPUT_ADDRESS:
4592 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4593 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4595 case RELOAD_FOR_INPADDR_ADDRESS:
4596 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4597 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4599 case RELOAD_FOR_OUTPUT_ADDRESS:
4600 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4601 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4603 case RELOAD_FOR_OUTADDR_ADDRESS:
4604 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4605 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4607 case RELOAD_FOR_OPERAND_ADDRESS:
4608 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4609 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4611 case RELOAD_FOR_OPADDR_ADDR:
4612 return (r2_type == RELOAD_FOR_INPUT
4613 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4615 case RELOAD_FOR_OUTPUT:
4616 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4617 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4618 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4619 && r2_opnum <= r1_opnum));
4621 case RELOAD_FOR_INSN:
4622 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4623 || r2_type == RELOAD_FOR_INSN
4624 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4626 case RELOAD_FOR_OTHER_ADDRESS:
4627 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4637 /* Indexed by reload number, 1 if incoming value
4638 inherited from previous insns. */
4639 char reload_inherited[MAX_RELOADS];
4641 /* For an inherited reload, this is the insn the reload was inherited from,
4642 if we know it. Otherwise, this is 0. */
4643 rtx reload_inheritance_insn[MAX_RELOADS];
4645 /* If non-zero, this is a place to get the value of the reload,
4646 rather than using reload_in. */
4647 rtx reload_override_in[MAX_RELOADS];
4649 /* For each reload, the hard register number of the register used,
4650 or -1 if we did not need a register for this reload. */
4651 int reload_spill_index[MAX_RELOADS];
4653 /* Return 1 if the value in reload reg REGNO, as used by a reload
4654 needed for the part of the insn specified by OPNUM and TYPE,
4655 may be used to load VALUE into it.
4657 Other read-only reloads with the same value do not conflict
4658 unless OUT is non-zero and these other reloads have to live while
4659 output reloads live.
4660 If OUT is CONST0_RTX, this is a special case: it means that the
4661 test should not be for using register REGNO as reload register, but
4662 for copying from register REGNO into the reload register.
4664 RELOADNUM is the number of the reload we want to load this value for;
4665 a reload does not conflict with itself.
4667 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4668 reloads that load an address for the very reload we are considering.
4670 The caller has to make sure that there is no conflict with the return
4673 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4674 ignore_address_reloads)
4677 enum reload_type type;
4680 int ignore_address_reloads;
4683 /* Set if we see an input reload that must not share its reload register
4684 with any new earlyclobber, but might otherwise share the reload
4685 register with an output or input-output reload. */
4686 int check_earlyclobber = 0;
4690 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4693 if (out == const0_rtx)
4699 /* We use some pseudo 'time' value to check if the lifetimes of the
4700 new register use would overlap with the one of a previous reload
4701 that is not read-only or uses a different value.
4702 The 'time' used doesn't have to be linear in any shape or form, just
4704 Some reload types use different 'buckets' for each operand.
4705 So there are MAX_RECOG_OPERANDS different time values for each
4707 We compute TIME1 as the time when the register for the prospective
4708 new reload ceases to be live, and TIME2 for each existing
4709 reload as the time when that the reload register of that reload
4711 Where there is little to be gained by exact lifetime calculations,
4712 we just make conservative assumptions, i.e. a longer lifetime;
4713 this is done in the 'default:' cases. */
4716 case RELOAD_FOR_OTHER_ADDRESS:
4717 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4718 time1 = copy ? 0 : 1;
4721 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4723 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4724 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4725 respectively, to the time values for these, we get distinct time
4726 values. To get distinct time values for each operand, we have to
4727 multiply opnum by at least three. We round that up to four because
4728 multiply by four is often cheaper. */
4729 case RELOAD_FOR_INPADDR_ADDRESS:
4730 time1 = opnum * 4 + 2;
4732 case RELOAD_FOR_INPUT_ADDRESS:
4733 time1 = opnum * 4 + 3;
4735 case RELOAD_FOR_INPUT:
4736 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4737 executes (inclusive). */
4738 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4740 case RELOAD_FOR_OPADDR_ADDR:
4742 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4743 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4745 case RELOAD_FOR_OPERAND_ADDRESS:
4746 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4748 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4750 case RELOAD_FOR_OUTADDR_ADDRESS:
4751 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4753 case RELOAD_FOR_OUTPUT_ADDRESS:
4754 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4757 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4760 for (i = 0; i < n_reloads; i++)
4762 rtx reg = rld[i].reg_rtx;
4763 if (reg && GET_CODE (reg) == REG
4764 && ((unsigned) regno - true_regnum (reg)
4765 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4768 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4769 || rld[i].out || out)
4772 switch (rld[i].when_needed)
4774 case RELOAD_FOR_OTHER_ADDRESS:
4777 case RELOAD_FOR_INPADDR_ADDRESS:
4778 /* find_reloads makes sure that a
4779 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4780 by at most one - the first -
4781 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4782 address reload is inherited, the address address reload
4783 goes away, so we can ignore this conflict. */
4784 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4785 && ignore_address_reloads
4786 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4787 Then the address address is still needed to store
4788 back the new address. */
4789 && ! rld[reloadnum].out)
4791 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4792 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4794 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4795 && ignore_address_reloads
4796 /* Unless we are reloading an auto_inc expression. */
4797 && ! rld[reloadnum].out)
4799 time2 = rld[i].opnum * 4 + 2;
4801 case RELOAD_FOR_INPUT_ADDRESS:
4802 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4803 && ignore_address_reloads
4804 && ! rld[reloadnum].out)
4806 time2 = rld[i].opnum * 4 + 3;
4808 case RELOAD_FOR_INPUT:
4809 time2 = rld[i].opnum * 4 + 4;
4810 check_earlyclobber = 1;
4812 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4813 == MAX_RECOG_OPERAND * 4 */
4814 case RELOAD_FOR_OPADDR_ADDR:
4815 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4816 && ignore_address_reloads
4817 && ! rld[reloadnum].out)
4819 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4821 case RELOAD_FOR_OPERAND_ADDRESS:
4822 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4823 check_earlyclobber = 1;
4825 case RELOAD_FOR_INSN:
4826 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4828 case RELOAD_FOR_OUTPUT:
4829 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4830 instruction is executed. */
4831 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4833 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4834 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4836 case RELOAD_FOR_OUTADDR_ADDRESS:
4837 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4838 && ignore_address_reloads
4839 && ! rld[reloadnum].out)
4841 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4843 case RELOAD_FOR_OUTPUT_ADDRESS:
4844 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4847 /* If there is no conflict in the input part, handle this
4848 like an output reload. */
4849 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4851 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4852 /* Earlyclobbered outputs must conflict with inputs. */
4853 if (earlyclobber_operand_p (rld[i].out))
4854 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4859 /* RELOAD_OTHER might be live beyond instruction execution,
4860 but this is not obvious when we set time2 = 1. So check
4861 here if there might be a problem with the new reload
4862 clobbering the register used by the RELOAD_OTHER. */
4870 && (! rld[i].in || rld[i].out
4871 || ! rtx_equal_p (rld[i].in, value)))
4872 || (out && rld[reloadnum].out_reg
4873 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4879 /* Earlyclobbered outputs must conflict with inputs. */
4880 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4886 /* Determine whether the reload reg X overlaps any rtx'es used for
4887 overriding inheritance. Return nonzero if so. */
4890 conflicts_with_override (x)
4894 for (i = 0; i < n_reloads; i++)
4895 if (reload_override_in[i]
4896 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4901 /* Give an error message saying we failed to find a reload for INSN,
4902 and clear out reload R. */
4904 failed_reload (insn, r)
4908 if (asm_noperands (PATTERN (insn)) < 0)
4909 /* It's the compiler's fault. */
4910 fatal_insn ("Could not find a spill register", insn);
4912 /* It's the user's fault; the operand's mode and constraint
4913 don't match. Disable this reload so we don't crash in final. */
4914 error_for_asm (insn,
4915 "`asm' operand constraint incompatible with operand size");
4919 rld[r].optional = 1;
4920 rld[r].secondary_p = 1;
4923 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4924 for reload R. If it's valid, get an rtx for it. Return nonzero if
4927 set_reload_reg (i, r)
4931 rtx reg = spill_reg_rtx[i];
4933 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4934 spill_reg_rtx[i] = reg
4935 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4937 regno = true_regnum (reg);
4939 /* Detect when the reload reg can't hold the reload mode.
4940 This used to be one `if', but Sequent compiler can't handle that. */
4941 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4943 enum machine_mode test_mode = VOIDmode;
4945 test_mode = GET_MODE (rld[r].in);
4946 /* If rld[r].in has VOIDmode, it means we will load it
4947 in whatever mode the reload reg has: to wit, rld[r].mode.
4948 We have already tested that for validity. */
4949 /* Aside from that, we need to test that the expressions
4950 to reload from or into have modes which are valid for this
4951 reload register. Otherwise the reload insns would be invalid. */
4952 if (! (rld[r].in != 0 && test_mode != VOIDmode
4953 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4954 if (! (rld[r].out != 0
4955 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4957 /* The reg is OK. */
4960 /* Mark as in use for this insn the reload regs we use
4962 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4963 rld[r].when_needed, rld[r].mode);
4965 rld[r].reg_rtx = reg;
4966 reload_spill_index[r] = spill_regs[i];
4973 /* Find a spill register to use as a reload register for reload R.
4974 LAST_RELOAD is non-zero if this is the last reload for the insn being
4977 Set rld[R].reg_rtx to the register allocated.
4979 We return 1 if successful, or 0 if we couldn't find a spill reg and
4980 we didn't change anything. */
4983 allocate_reload_reg (chain, r, last_reload)
4984 struct insn_chain *chain ATTRIBUTE_UNUSED;
4990 /* If we put this reload ahead, thinking it is a group,
4991 then insist on finding a group. Otherwise we can grab a
4992 reg that some other reload needs.
4993 (That can happen when we have a 68000 DATA_OR_FP_REG
4994 which is a group of data regs or one fp reg.)
4995 We need not be so restrictive if there are no more reloads
4998 ??? Really it would be nicer to have smarter handling
4999 for that kind of reg class, where a problem like this is normal.
5000 Perhaps those classes should be avoided for reloading
5001 by use of more alternatives. */
5003 int force_group = rld[r].nregs > 1 && ! last_reload;
5005 /* If we want a single register and haven't yet found one,
5006 take any reg in the right class and not in use.
5007 If we want a consecutive group, here is where we look for it.
5009 We use two passes so we can first look for reload regs to
5010 reuse, which are already in use for other reloads in this insn,
5011 and only then use additional registers.
5012 I think that maximizing reuse is needed to make sure we don't
5013 run out of reload regs. Suppose we have three reloads, and
5014 reloads A and B can share regs. These need two regs.
5015 Suppose A and B are given different regs.
5016 That leaves none for C. */
5017 for (pass = 0; pass < 2; pass++)
5019 /* I is the index in spill_regs.
5020 We advance it round-robin between insns to use all spill regs
5021 equally, so that inherited reloads have a chance
5022 of leapfrogging each other. */
5026 for (count = 0; count < n_spills; count++)
5028 int class = (int) rld[r].class;
5034 regnum = spill_regs[i];
5036 if ((reload_reg_free_p (regnum, rld[r].opnum,
5039 /* We check reload_reg_used to make sure we
5040 don't clobber the return register. */
5041 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5042 && reload_reg_free_for_value_p (regnum,
5047 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5048 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5049 /* Look first for regs to share, then for unshared. But
5050 don't share regs used for inherited reloads; they are
5051 the ones we want to preserve. */
5053 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5055 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5058 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5059 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5060 (on 68000) got us two FP regs. If NR is 1,
5061 we would reject both of them. */
5064 /* If we need only one reg, we have already won. */
5067 /* But reject a single reg if we demand a group. */
5072 /* Otherwise check that as many consecutive regs as we need
5073 are available here. */
5076 int regno = regnum + nr - 1;
5077 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5078 && spill_reg_order[regno] >= 0
5079 && reload_reg_free_p (regno, rld[r].opnum,
5080 rld[r].when_needed)))
5089 /* If we found something on pass 1, omit pass 2. */
5090 if (count < n_spills)
5094 /* We should have found a spill register by now. */
5095 if (count >= n_spills)
5098 /* I is the index in SPILL_REG_RTX of the reload register we are to
5099 allocate. Get an rtx for it and find its register number. */
5101 return set_reload_reg (i, r);
5104 /* Initialize all the tables needed to allocate reload registers.
5105 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5106 is the array we use to restore the reg_rtx field for every reload. */
5109 choose_reload_regs_init (chain, save_reload_reg_rtx)
5110 struct insn_chain *chain;
5111 rtx *save_reload_reg_rtx;
5115 for (i = 0; i < n_reloads; i++)
5116 rld[i].reg_rtx = save_reload_reg_rtx[i];
5118 memset (reload_inherited, 0, MAX_RELOADS);
5119 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5120 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5122 CLEAR_HARD_REG_SET (reload_reg_used);
5123 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5124 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5125 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5126 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5127 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5129 CLEAR_HARD_REG_SET (reg_used_in_insn);
5132 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5133 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5134 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5135 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5136 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5137 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5140 for (i = 0; i < reload_n_operands; i++)
5142 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5143 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5144 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5145 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5146 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5147 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5150 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5152 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5154 for (i = 0; i < n_reloads; i++)
5155 /* If we have already decided to use a certain register,
5156 don't use it in another way. */
5158 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5159 rld[i].when_needed, rld[i].mode);
5162 /* Assign hard reg targets for the pseudo-registers we must reload
5163 into hard regs for this insn.
5164 Also output the instructions to copy them in and out of the hard regs.
5166 For machines with register classes, we are responsible for
5167 finding a reload reg in the proper class. */
5170 choose_reload_regs (chain)
5171 struct insn_chain *chain;
5173 rtx insn = chain->insn;
5175 unsigned int max_group_size = 1;
5176 enum reg_class group_class = NO_REGS;
5177 int pass, win, inheritance;
5179 rtx save_reload_reg_rtx[MAX_RELOADS];
5181 /* In order to be certain of getting the registers we need,
5182 we must sort the reloads into order of increasing register class.
5183 Then our grabbing of reload registers will parallel the process
5184 that provided the reload registers.
5186 Also note whether any of the reloads wants a consecutive group of regs.
5187 If so, record the maximum size of the group desired and what
5188 register class contains all the groups needed by this insn. */
5190 for (j = 0; j < n_reloads; j++)
5192 reload_order[j] = j;
5193 reload_spill_index[j] = -1;
5195 if (rld[j].nregs > 1)
5197 max_group_size = MAX (rld[j].nregs, max_group_size);
5199 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5202 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5206 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5208 /* If -O, try first with inheritance, then turning it off.
5209 If not -O, don't do inheritance.
5210 Using inheritance when not optimizing leads to paradoxes
5211 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5212 because one side of the comparison might be inherited. */
5214 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5216 choose_reload_regs_init (chain, save_reload_reg_rtx);
5218 /* Process the reloads in order of preference just found.
5219 Beyond this point, subregs can be found in reload_reg_rtx.
5221 This used to look for an existing reloaded home for all of the
5222 reloads, and only then perform any new reloads. But that could lose
5223 if the reloads were done out of reg-class order because a later
5224 reload with a looser constraint might have an old home in a register
5225 needed by an earlier reload with a tighter constraint.
5227 To solve this, we make two passes over the reloads, in the order
5228 described above. In the first pass we try to inherit a reload
5229 from a previous insn. If there is a later reload that needs a
5230 class that is a proper subset of the class being processed, we must
5231 also allocate a spill register during the first pass.
5233 Then make a second pass over the reloads to allocate any reloads
5234 that haven't been given registers yet. */
5236 for (j = 0; j < n_reloads; j++)
5238 register int r = reload_order[j];
5239 rtx search_equiv = NULL_RTX;
5241 /* Ignore reloads that got marked inoperative. */
5242 if (rld[r].out == 0 && rld[r].in == 0
5243 && ! rld[r].secondary_p)
5246 /* If find_reloads chose to use reload_in or reload_out as a reload
5247 register, we don't need to chose one. Otherwise, try even if it
5248 found one since we might save an insn if we find the value lying
5250 Try also when reload_in is a pseudo without a hard reg. */
5251 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5252 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5253 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5254 && GET_CODE (rld[r].in) != MEM
5255 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5258 #if 0 /* No longer needed for correct operation.
5259 It might give better code, or might not; worth an experiment? */
5260 /* If this is an optional reload, we can't inherit from earlier insns
5261 until we are sure that any non-optional reloads have been allocated.
5262 The following code takes advantage of the fact that optional reloads
5263 are at the end of reload_order. */
5264 if (rld[r].optional != 0)
5265 for (i = 0; i < j; i++)
5266 if ((rld[reload_order[i]].out != 0
5267 || rld[reload_order[i]].in != 0
5268 || rld[reload_order[i]].secondary_p)
5269 && ! rld[reload_order[i]].optional
5270 && rld[reload_order[i]].reg_rtx == 0)
5271 allocate_reload_reg (chain, reload_order[i], 0);
5274 /* First see if this pseudo is already available as reloaded
5275 for a previous insn. We cannot try to inherit for reloads
5276 that are smaller than the maximum number of registers needed
5277 for groups unless the register we would allocate cannot be used
5280 We could check here to see if this is a secondary reload for
5281 an object that is already in a register of the desired class.
5282 This would avoid the need for the secondary reload register.
5283 But this is complex because we can't easily determine what
5284 objects might want to be loaded via this reload. So let a
5285 register be allocated here. In `emit_reload_insns' we suppress
5286 one of the loads in the case described above. */
5291 register int regno = -1;
5292 enum machine_mode mode = VOIDmode;
5296 else if (GET_CODE (rld[r].in) == REG)
5298 regno = REGNO (rld[r].in);
5299 mode = GET_MODE (rld[r].in);
5301 else if (GET_CODE (rld[r].in_reg) == REG)
5303 regno = REGNO (rld[r].in_reg);
5304 mode = GET_MODE (rld[r].in_reg);
5306 else if (GET_CODE (rld[r].in_reg) == SUBREG
5307 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5309 word = SUBREG_WORD (rld[r].in_reg);
5310 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5311 if (regno < FIRST_PSEUDO_REGISTER)
5313 mode = GET_MODE (rld[r].in_reg);
5316 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5317 || GET_CODE (rld[r].in_reg) == PRE_DEC
5318 || GET_CODE (rld[r].in_reg) == POST_INC
5319 || GET_CODE (rld[r].in_reg) == POST_DEC)
5320 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5322 regno = REGNO (XEXP (rld[r].in_reg, 0));
5323 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5324 rld[r].out = rld[r].in;
5328 /* This won't work, since REGNO can be a pseudo reg number.
5329 Also, it takes much more hair to keep track of all the things
5330 that can invalidate an inherited reload of part of a pseudoreg. */
5331 else if (GET_CODE (rld[r].in) == SUBREG
5332 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5333 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5336 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5338 enum reg_class class = rld[r].class, last_class;
5339 rtx last_reg = reg_last_reload_reg[regno];
5340 enum machine_mode need_mode;
5342 i = REGNO (last_reg) + word;
5343 last_class = REGNO_REG_CLASS (i);
5349 = smallest_mode_for_size (GET_MODE_SIZE (mode)
5350 + word * UNITS_PER_WORD,
5351 GET_MODE_CLASS (mode));
5354 #ifdef CLASS_CANNOT_CHANGE_MODE
5356 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5357 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5359 : (GET_MODE_SIZE (GET_MODE (last_reg))
5360 >= GET_MODE_SIZE (need_mode)))
5362 (GET_MODE_SIZE (GET_MODE (last_reg))
5363 >= GET_MODE_SIZE (need_mode))
5365 && reg_reloaded_contents[i] == regno
5366 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5367 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5368 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5369 /* Even if we can't use this register as a reload
5370 register, we might use it for reload_override_in,
5371 if copying it to the desired class is cheap
5373 || ((REGISTER_MOVE_COST (last_class, class)
5374 < MEMORY_MOVE_COST (mode, class, 1))
5375 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5376 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5380 #ifdef SECONDARY_MEMORY_NEEDED
5381 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5386 && (rld[r].nregs == max_group_size
5387 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5389 && reload_reg_free_for_value_p (i, rld[r].opnum,
5394 /* If a group is needed, verify that all the subsequent
5395 registers still have their values intact. */
5396 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5399 for (k = 1; k < nr; k++)
5400 if (reg_reloaded_contents[i + k] != regno
5401 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5408 last_reg = (GET_MODE (last_reg) == mode
5409 ? last_reg : gen_rtx_REG (mode, i));
5411 /* We found a register that contains the
5412 value we need. If this register is the
5413 same as an `earlyclobber' operand of the
5414 current insn, just mark it as a place to
5415 reload from since we can't use it as the
5416 reload register itself. */
5418 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5419 if (reg_overlap_mentioned_for_reload_p
5420 (reg_last_reload_reg[regno],
5421 reload_earlyclobbers[i1]))
5424 if (i1 != n_earlyclobbers
5425 || ! (reload_reg_free_for_value_p
5426 (i, rld[r].opnum, rld[r].when_needed,
5427 rld[r].in, rld[r].out, r, 1))
5428 /* Don't use it if we'd clobber a pseudo reg. */
5429 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5431 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5432 /* Don't clobber the frame pointer. */
5433 || (i == HARD_FRAME_POINTER_REGNUM
5435 /* Don't really use the inherited spill reg
5436 if we need it wider than we've got it. */
5437 || (GET_MODE_SIZE (rld[r].mode)
5438 > GET_MODE_SIZE (mode))
5439 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5442 /* If find_reloads chose reload_out as reload
5443 register, stay with it - that leaves the
5444 inherited register for subsequent reloads. */
5445 || (rld[r].out && rld[r].reg_rtx
5446 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5448 if (! rld[r].optional)
5450 reload_override_in[r] = last_reg;
5451 reload_inheritance_insn[r]
5452 = reg_reloaded_insn[i];
5458 /* We can use this as a reload reg. */
5459 /* Mark the register as in use for this part of
5461 mark_reload_reg_in_use (i,
5465 rld[r].reg_rtx = last_reg;
5466 reload_inherited[r] = 1;
5467 reload_inheritance_insn[r]
5468 = reg_reloaded_insn[i];
5469 reload_spill_index[r] = i;
5470 for (k = 0; k < nr; k++)
5471 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5479 /* Here's another way to see if the value is already lying around. */
5482 && ! reload_inherited[r]
5484 && (CONSTANT_P (rld[r].in)
5485 || GET_CODE (rld[r].in) == PLUS
5486 || GET_CODE (rld[r].in) == REG
5487 || GET_CODE (rld[r].in) == MEM)
5488 && (rld[r].nregs == max_group_size
5489 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5490 search_equiv = rld[r].in;
5491 /* If this is an output reload from a simple move insn, look
5492 if an equivalence for the input is available. */
5493 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5495 rtx set = single_set (insn);
5498 && rtx_equal_p (rld[r].out, SET_DEST (set))
5499 && CONSTANT_P (SET_SRC (set)))
5500 search_equiv = SET_SRC (set);
5506 = find_equiv_reg (search_equiv, insn, rld[r].class,
5507 -1, NULL_PTR, 0, rld[r].mode);
5512 if (GET_CODE (equiv) == REG)
5513 regno = REGNO (equiv);
5514 else if (GET_CODE (equiv) == SUBREG)
5516 /* This must be a SUBREG of a hard register.
5517 Make a new REG since this might be used in an
5518 address and not all machines support SUBREGs
5520 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5521 equiv = gen_rtx_REG (rld[r].mode, regno);
5527 /* If we found a spill reg, reject it unless it is free
5528 and of the desired class. */
5530 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5531 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5535 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5539 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5542 /* We found a register that contains the value we need.
5543 If this register is the same as an `earlyclobber' operand
5544 of the current insn, just mark it as a place to reload from
5545 since we can't use it as the reload register itself. */
5548 for (i = 0; i < n_earlyclobbers; i++)
5549 if (reg_overlap_mentioned_for_reload_p (equiv,
5550 reload_earlyclobbers[i]))
5552 if (! rld[r].optional)
5553 reload_override_in[r] = equiv;
5558 /* If the equiv register we have found is explicitly clobbered
5559 in the current insn, it depends on the reload type if we
5560 can use it, use it for reload_override_in, or not at all.
5561 In particular, we then can't use EQUIV for a
5562 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5566 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5567 switch (rld[r].when_needed)
5569 case RELOAD_FOR_OTHER_ADDRESS:
5570 case RELOAD_FOR_INPADDR_ADDRESS:
5571 case RELOAD_FOR_INPUT_ADDRESS:
5572 case RELOAD_FOR_OPADDR_ADDR:
5575 case RELOAD_FOR_INPUT:
5576 case RELOAD_FOR_OPERAND_ADDRESS:
5577 if (! rld[r].optional)
5578 reload_override_in[r] = equiv;
5584 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5585 switch (rld[r].when_needed)
5587 case RELOAD_FOR_OTHER_ADDRESS:
5588 case RELOAD_FOR_INPADDR_ADDRESS:
5589 case RELOAD_FOR_INPUT_ADDRESS:
5590 case RELOAD_FOR_OPADDR_ADDR:
5591 case RELOAD_FOR_OPERAND_ADDRESS:
5592 case RELOAD_FOR_INPUT:
5595 if (! rld[r].optional)
5596 reload_override_in[r] = equiv;
5604 /* If we found an equivalent reg, say no code need be generated
5605 to load it, and use it as our reload reg. */
5606 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5608 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5610 rld[r].reg_rtx = equiv;
5611 reload_inherited[r] = 1;
5613 /* If reg_reloaded_valid is not set for this register,
5614 there might be a stale spill_reg_store lying around.
5615 We must clear it, since otherwise emit_reload_insns
5616 might delete the store. */
5617 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5618 spill_reg_store[regno] = NULL_RTX;
5619 /* If any of the hard registers in EQUIV are spill
5620 registers, mark them as in use for this insn. */
5621 for (k = 0; k < nr; k++)
5623 i = spill_reg_order[regno + k];
5626 mark_reload_reg_in_use (regno, rld[r].opnum,
5629 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5636 /* If we found a register to use already, or if this is an optional
5637 reload, we are done. */
5638 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5642 /* No longer needed for correct operation. Might or might
5643 not give better code on the average. Want to experiment? */
5645 /* See if there is a later reload that has a class different from our
5646 class that intersects our class or that requires less register
5647 than our reload. If so, we must allocate a register to this
5648 reload now, since that reload might inherit a previous reload
5649 and take the only available register in our class. Don't do this
5650 for optional reloads since they will force all previous reloads
5651 to be allocated. Also don't do this for reloads that have been
5654 for (i = j + 1; i < n_reloads; i++)
5656 int s = reload_order[i];
5658 if ((rld[s].in == 0 && rld[s].out == 0
5659 && ! rld[s].secondary_p)
5663 if ((rld[s].class != rld[r].class
5664 && reg_classes_intersect_p (rld[r].class,
5666 || rld[s].nregs < rld[r].nregs)
5673 allocate_reload_reg (chain, r, j == n_reloads - 1);
5677 /* Now allocate reload registers for anything non-optional that
5678 didn't get one yet. */
5679 for (j = 0; j < n_reloads; j++)
5681 register int r = reload_order[j];
5683 /* Ignore reloads that got marked inoperative. */
5684 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5687 /* Skip reloads that already have a register allocated or are
5689 if (rld[r].reg_rtx != 0 || rld[r].optional)
5692 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5696 /* If that loop got all the way, we have won. */
5703 /* Loop around and try without any inheritance. */
5708 /* First undo everything done by the failed attempt
5709 to allocate with inheritance. */
5710 choose_reload_regs_init (chain, save_reload_reg_rtx);
5712 /* Some sanity tests to verify that the reloads found in the first
5713 pass are identical to the ones we have now. */
5714 if (chain->n_reloads != n_reloads)
5717 for (i = 0; i < n_reloads; i++)
5719 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5721 if (chain->rld[i].when_needed != rld[i].when_needed)
5723 for (j = 0; j < n_spills; j++)
5724 if (spill_regs[j] == chain->rld[i].regno)
5725 if (! set_reload_reg (j, i))
5726 failed_reload (chain->insn, i);
5730 /* If we thought we could inherit a reload, because it seemed that
5731 nothing else wanted the same reload register earlier in the insn,
5732 verify that assumption, now that all reloads have been assigned.
5733 Likewise for reloads where reload_override_in has been set. */
5735 /* If doing expensive optimizations, do one preliminary pass that doesn't
5736 cancel any inheritance, but removes reloads that have been needed only
5737 for reloads that we know can be inherited. */
5738 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5740 for (j = 0; j < n_reloads; j++)
5742 register int r = reload_order[j];
5744 if (reload_inherited[r] && rld[r].reg_rtx)
5745 check_reg = rld[r].reg_rtx;
5746 else if (reload_override_in[r]
5747 && (GET_CODE (reload_override_in[r]) == REG
5748 || GET_CODE (reload_override_in[r]) == SUBREG))
5749 check_reg = reload_override_in[r];
5752 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5756 (reload_inherited[r]
5757 ? rld[r].out : const0_rtx),
5762 reload_inherited[r] = 0;
5763 reload_override_in[r] = 0;
5765 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5766 reload_override_in, then we do not need its related
5767 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5768 likewise for other reload types.
5769 We handle this by removing a reload when its only replacement
5770 is mentioned in reload_in of the reload we are going to inherit.
5771 A special case are auto_inc expressions; even if the input is
5772 inherited, we still need the address for the output. We can
5773 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5774 If we suceeded removing some reload and we are doing a preliminary
5775 pass just to remove such reloads, make another pass, since the
5776 removal of one reload might allow us to inherit another one. */
5778 && rld[r].out != rld[r].in
5779 && remove_address_replacements (rld[r].in) && pass)
5784 /* Now that reload_override_in is known valid,
5785 actually override reload_in. */
5786 for (j = 0; j < n_reloads; j++)
5787 if (reload_override_in[j])
5788 rld[j].in = reload_override_in[j];
5790 /* If this reload won't be done because it has been cancelled or is
5791 optional and not inherited, clear reload_reg_rtx so other
5792 routines (such as subst_reloads) don't get confused. */
5793 for (j = 0; j < n_reloads; j++)
5794 if (rld[j].reg_rtx != 0
5795 && ((rld[j].optional && ! reload_inherited[j])
5796 || (rld[j].in == 0 && rld[j].out == 0
5797 && ! rld[j].secondary_p)))
5799 int regno = true_regnum (rld[j].reg_rtx);
5801 if (spill_reg_order[regno] >= 0)
5802 clear_reload_reg_in_use (regno, rld[j].opnum,
5803 rld[j].when_needed, rld[j].mode);
5805 reload_spill_index[j] = -1;
5808 /* Record which pseudos and which spill regs have output reloads. */
5809 for (j = 0; j < n_reloads; j++)
5811 register int r = reload_order[j];
5813 i = reload_spill_index[r];
5815 /* I is nonneg if this reload uses a register.
5816 If rld[r].reg_rtx is 0, this is an optional reload
5817 that we opted to ignore. */
5818 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5819 && rld[r].reg_rtx != 0)
5821 register int nregno = REGNO (rld[r].out_reg);
5824 if (nregno < FIRST_PSEUDO_REGISTER)
5825 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5828 reg_has_output_reload[nregno + nr] = 1;
5832 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5834 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5837 if (rld[r].when_needed != RELOAD_OTHER
5838 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5839 && rld[r].when_needed != RELOAD_FOR_INSN)
5845 /* Deallocate the reload register for reload R. This is called from
5846 remove_address_replacements. */
5849 deallocate_reload_reg (r)
5854 if (! rld[r].reg_rtx)
5856 regno = true_regnum (rld[r].reg_rtx);
5858 if (spill_reg_order[regno] >= 0)
5859 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5861 reload_spill_index[r] = -1;
5864 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5865 reloads of the same item for fear that we might not have enough reload
5866 registers. However, normally they will get the same reload register
5867 and hence actually need not be loaded twice.
5869 Here we check for the most common case of this phenomenon: when we have
5870 a number of reloads for the same object, each of which were allocated
5871 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5872 reload, and is not modified in the insn itself. If we find such,
5873 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5874 This will not increase the number of spill registers needed and will
5875 prevent redundant code. */
5878 merge_assigned_reloads (insn)
5883 /* Scan all the reloads looking for ones that only load values and
5884 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5885 assigned and not modified by INSN. */
5887 for (i = 0; i < n_reloads; i++)
5889 int conflicting_input = 0;
5890 int max_input_address_opnum = -1;
5891 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5893 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5894 || rld[i].out != 0 || rld[i].reg_rtx == 0
5895 || reg_set_p (rld[i].reg_rtx, insn))
5898 /* Look at all other reloads. Ensure that the only use of this
5899 reload_reg_rtx is in a reload that just loads the same value
5900 as we do. Note that any secondary reloads must be of the identical
5901 class since the values, modes, and result registers are the
5902 same, so we need not do anything with any secondary reloads. */
5904 for (j = 0; j < n_reloads; j++)
5906 if (i == j || rld[j].reg_rtx == 0
5907 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5911 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5912 && rld[j].opnum > max_input_address_opnum)
5913 max_input_address_opnum = rld[j].opnum;
5915 /* If the reload regs aren't exactly the same (e.g, different modes)
5916 or if the values are different, we can't merge this reload.
5917 But if it is an input reload, we might still merge
5918 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5920 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5921 || rld[j].out != 0 || rld[j].in == 0
5922 || ! rtx_equal_p (rld[i].in, rld[j].in))
5924 if (rld[j].when_needed != RELOAD_FOR_INPUT
5925 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5926 || rld[i].opnum > rld[j].opnum)
5927 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5929 conflicting_input = 1;
5930 if (min_conflicting_input_opnum > rld[j].opnum)
5931 min_conflicting_input_opnum = rld[j].opnum;
5935 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5936 we, in fact, found any matching reloads. */
5939 && max_input_address_opnum <= min_conflicting_input_opnum)
5941 for (j = 0; j < n_reloads; j++)
5942 if (i != j && rld[j].reg_rtx != 0
5943 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5944 && (! conflicting_input
5945 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5946 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5948 rld[i].when_needed = RELOAD_OTHER;
5950 reload_spill_index[j] = -1;
5951 transfer_replacements (i, j);
5954 /* If this is now RELOAD_OTHER, look for any reloads that load
5955 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5956 if they were for inputs, RELOAD_OTHER for outputs. Note that
5957 this test is equivalent to looking for reloads for this operand
5960 if (rld[i].when_needed == RELOAD_OTHER)
5961 for (j = 0; j < n_reloads; j++)
5963 && rld[i].when_needed != RELOAD_OTHER
5964 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5967 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5968 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5969 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5974 /* These arrays are filled by emit_reload_insns and its subroutines. */
5975 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5976 static rtx other_input_address_reload_insns = 0;
5977 static rtx other_input_reload_insns = 0;
5978 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5979 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5980 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5981 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5982 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5983 static rtx operand_reload_insns = 0;
5984 static rtx other_operand_reload_insns = 0;
5985 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5987 /* Values to be put in spill_reg_store are put here first. */
5988 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5989 static HARD_REG_SET reg_reloaded_died;
5991 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5992 has the number J. OLD contains the value to be used as input. */
5995 emit_input_reload_insns (chain, rl, old, j)
5996 struct insn_chain *chain;
6001 rtx insn = chain->insn;
6002 register rtx reloadreg = rl->reg_rtx;
6003 rtx oldequiv_reg = 0;
6006 enum machine_mode mode;
6009 /* Determine the mode to reload in.
6010 This is very tricky because we have three to choose from.
6011 There is the mode the insn operand wants (rl->inmode).
6012 There is the mode of the reload register RELOADREG.
6013 There is the intrinsic mode of the operand, which we could find
6014 by stripping some SUBREGs.
6015 It turns out that RELOADREG's mode is irrelevant:
6016 we can change that arbitrarily.
6018 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6019 then the reload reg may not support QImode moves, so use SImode.
6020 If foo is in memory due to spilling a pseudo reg, this is safe,
6021 because the QImode value is in the least significant part of a
6022 slot big enough for a SImode. If foo is some other sort of
6023 memory reference, then it is impossible to reload this case,
6024 so previous passes had better make sure this never happens.
6026 Then consider a one-word union which has SImode and one of its
6027 members is a float, being fetched as (SUBREG:SF union:SI).
6028 We must fetch that as SFmode because we could be loading into
6029 a float-only register. In this case OLD's mode is correct.
6031 Consider an immediate integer: it has VOIDmode. Here we need
6032 to get a mode from something else.
6034 In some cases, there is a fourth mode, the operand's
6035 containing mode. If the insn specifies a containing mode for
6036 this operand, it overrides all others.
6038 I am not sure whether the algorithm here is always right,
6039 but it does the right things in those cases. */
6041 mode = GET_MODE (old);
6042 if (mode == VOIDmode)
6045 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6046 /* If we need a secondary register for this operation, see if
6047 the value is already in a register in that class. Don't
6048 do this if the secondary register will be used as a scratch
6051 if (rl->secondary_in_reload >= 0
6052 && rl->secondary_in_icode == CODE_FOR_nothing
6055 = find_equiv_reg (old, insn,
6056 rld[rl->secondary_in_reload].class,
6057 -1, NULL_PTR, 0, mode);
6060 /* If reloading from memory, see if there is a register
6061 that already holds the same value. If so, reload from there.
6062 We can pass 0 as the reload_reg_p argument because
6063 any other reload has either already been emitted,
6064 in which case find_equiv_reg will see the reload-insn,
6065 or has yet to be emitted, in which case it doesn't matter
6066 because we will use this equiv reg right away. */
6068 if (oldequiv == 0 && optimize
6069 && (GET_CODE (old) == MEM
6070 || (GET_CODE (old) == REG
6071 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6072 && reg_renumber[REGNO (old)] < 0)))
6073 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6074 -1, NULL_PTR, 0, mode);
6078 unsigned int regno = true_regnum (oldequiv);
6080 /* Don't use OLDEQUIV if any other reload changes it at an
6081 earlier stage of this insn or at this stage. */
6082 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6084 rl->in, const0_rtx, j,
6088 /* If it is no cheaper to copy from OLDEQUIV into the
6089 reload register than it would be to move from memory,
6090 don't use it. Likewise, if we need a secondary register
6094 && ((REGNO_REG_CLASS (regno) != rl->class
6095 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6097 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6098 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6099 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6103 #ifdef SECONDARY_MEMORY_NEEDED
6104 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6112 /* delete_output_reload is only invoked properly if old contains
6113 the original pseudo register. Since this is replaced with a
6114 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6115 find the pseudo in RELOAD_IN_REG. */
6117 && reload_override_in[j]
6118 && GET_CODE (rl->in_reg) == REG)
6125 else if (GET_CODE (oldequiv) == REG)
6126 oldequiv_reg = oldequiv;
6127 else if (GET_CODE (oldequiv) == SUBREG)
6128 oldequiv_reg = SUBREG_REG (oldequiv);
6130 /* If we are reloading from a register that was recently stored in
6131 with an output-reload, see if we can prove there was
6132 actually no need to store the old value in it. */
6134 if (optimize && GET_CODE (oldequiv) == REG
6135 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6136 && spill_reg_store[REGNO (oldequiv)]
6137 && GET_CODE (old) == REG
6138 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6139 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6141 delete_output_reload (insn, j, REGNO (oldequiv));
6143 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6144 then load RELOADREG from OLDEQUIV. Note that we cannot use
6145 gen_lowpart_common since it can do the wrong thing when
6146 RELOADREG has a multi-word mode. Note that RELOADREG
6147 must always be a REG here. */
6149 if (GET_MODE (reloadreg) != mode)
6150 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6151 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6152 oldequiv = SUBREG_REG (oldequiv);
6153 if (GET_MODE (oldequiv) != VOIDmode
6154 && mode != GET_MODE (oldequiv))
6155 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6157 /* Switch to the right place to emit the reload insns. */
6158 switch (rl->when_needed)
6161 where = &other_input_reload_insns;
6163 case RELOAD_FOR_INPUT:
6164 where = &input_reload_insns[rl->opnum];
6166 case RELOAD_FOR_INPUT_ADDRESS:
6167 where = &input_address_reload_insns[rl->opnum];
6169 case RELOAD_FOR_INPADDR_ADDRESS:
6170 where = &inpaddr_address_reload_insns[rl->opnum];
6172 case RELOAD_FOR_OUTPUT_ADDRESS:
6173 where = &output_address_reload_insns[rl->opnum];
6175 case RELOAD_FOR_OUTADDR_ADDRESS:
6176 where = &outaddr_address_reload_insns[rl->opnum];
6178 case RELOAD_FOR_OPERAND_ADDRESS:
6179 where = &operand_reload_insns;
6181 case RELOAD_FOR_OPADDR_ADDR:
6182 where = &other_operand_reload_insns;
6184 case RELOAD_FOR_OTHER_ADDRESS:
6185 where = &other_input_address_reload_insns;
6191 push_to_sequence (*where);
6193 /* Auto-increment addresses must be reloaded in a special way. */
6194 if (rl->out && ! rl->out_reg)
6196 /* We are not going to bother supporting the case where a
6197 incremented register can't be copied directly from
6198 OLDEQUIV since this seems highly unlikely. */
6199 if (rl->secondary_in_reload >= 0)
6202 if (reload_inherited[j])
6203 oldequiv = reloadreg;
6205 old = XEXP (rl->in_reg, 0);
6207 if (optimize && GET_CODE (oldequiv) == REG
6208 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6209 && spill_reg_store[REGNO (oldequiv)]
6210 && GET_CODE (old) == REG
6211 && (dead_or_set_p (insn,
6212 spill_reg_stored_to[REGNO (oldequiv)])
6213 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6215 delete_output_reload (insn, j, REGNO (oldequiv));
6217 /* Prevent normal processing of this reload. */
6219 /* Output a special code sequence for this case. */
6220 new_spill_reg_store[REGNO (reloadreg)]
6221 = inc_for_reload (reloadreg, oldequiv, rl->out,
6225 /* If we are reloading a pseudo-register that was set by the previous
6226 insn, see if we can get rid of that pseudo-register entirely
6227 by redirecting the previous insn into our reload register. */
6229 else if (optimize && GET_CODE (old) == REG
6230 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6231 && dead_or_set_p (insn, old)
6232 /* This is unsafe if some other reload
6233 uses the same reg first. */
6234 && ! conflicts_with_override (reloadreg)
6235 && reload_reg_free_for_value_p (REGNO (reloadreg),
6241 rtx temp = PREV_INSN (insn);
6242 while (temp && GET_CODE (temp) == NOTE)
6243 temp = PREV_INSN (temp);
6245 && GET_CODE (temp) == INSN
6246 && GET_CODE (PATTERN (temp)) == SET
6247 && SET_DEST (PATTERN (temp)) == old
6248 /* Make sure we can access insn_operand_constraint. */
6249 && asm_noperands (PATTERN (temp)) < 0
6250 /* This is unsafe if prev insn rejects our reload reg. */
6251 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6253 /* This is unsafe if operand occurs more than once in current
6254 insn. Perhaps some occurrences aren't reloaded. */
6255 && count_occurrences (PATTERN (insn), old, 0) == 1
6256 /* Don't risk splitting a matching pair of operands. */
6257 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6259 /* Store into the reload register instead of the pseudo. */
6260 SET_DEST (PATTERN (temp)) = reloadreg;
6262 /* If the previous insn is an output reload, the source is
6263 a reload register, and its spill_reg_store entry will
6264 contain the previous destination. This is now
6266 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6267 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6269 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6270 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6273 /* If these are the only uses of the pseudo reg,
6274 pretend for GDB it lives in the reload reg we used. */
6275 if (REG_N_DEATHS (REGNO (old)) == 1
6276 && REG_N_SETS (REGNO (old)) == 1)
6278 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6279 alter_reg (REGNO (old), -1);
6285 /* We can't do that, so output an insn to load RELOADREG. */
6287 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6288 /* If we have a secondary reload, pick up the secondary register
6289 and icode, if any. If OLDEQUIV and OLD are different or
6290 if this is an in-out reload, recompute whether or not we
6291 still need a secondary register and what the icode should
6292 be. If we still need a secondary register and the class or
6293 icode is different, go back to reloading from OLD if using
6294 OLDEQUIV means that we got the wrong type of register. We
6295 cannot have different class or icode due to an in-out reload
6296 because we don't make such reloads when both the input and
6297 output need secondary reload registers. */
6299 if (! special && rl->secondary_in_reload >= 0)
6301 rtx second_reload_reg = 0;
6302 int secondary_reload = rl->secondary_in_reload;
6303 rtx real_oldequiv = oldequiv;
6306 enum insn_code icode;
6308 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6309 and similarly for OLD.
6310 See comments in get_secondary_reload in reload.c. */
6311 /* If it is a pseudo that cannot be replaced with its
6312 equivalent MEM, we must fall back to reload_in, which
6313 will have all the necessary substitutions registered.
6314 Likewise for a pseudo that can't be replaced with its
6315 equivalent constant.
6317 Take extra care for subregs of such pseudos. Note that
6318 we cannot use reg_equiv_mem in this case because it is
6319 not in the right mode. */
6322 if (GET_CODE (tmp) == SUBREG)
6323 tmp = SUBREG_REG (tmp);
6324 if (GET_CODE (tmp) == REG
6325 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6326 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6327 || reg_equiv_constant[REGNO (tmp)] != 0))
6329 if (! reg_equiv_mem[REGNO (tmp)]
6330 || num_not_at_initial_offset
6331 || GET_CODE (oldequiv) == SUBREG)
6332 real_oldequiv = rl->in;
6334 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6338 if (GET_CODE (tmp) == SUBREG)
6339 tmp = SUBREG_REG (tmp);
6340 if (GET_CODE (tmp) == REG
6341 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6342 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6343 || reg_equiv_constant[REGNO (tmp)] != 0))
6345 if (! reg_equiv_mem[REGNO (tmp)]
6346 || num_not_at_initial_offset
6347 || GET_CODE (old) == SUBREG)
6350 real_old = reg_equiv_mem[REGNO (tmp)];
6353 second_reload_reg = rld[secondary_reload].reg_rtx;
6354 icode = rl->secondary_in_icode;
6356 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6357 || (rl->in != 0 && rl->out != 0))
6359 enum reg_class new_class
6360 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6361 mode, real_oldequiv);
6363 if (new_class == NO_REGS)
6364 second_reload_reg = 0;
6367 enum insn_code new_icode;
6368 enum machine_mode new_mode;
6370 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6371 REGNO (second_reload_reg)))
6372 oldequiv = old, real_oldequiv = real_old;
6375 new_icode = reload_in_optab[(int) mode];
6376 if (new_icode != CODE_FOR_nothing
6377 && ((insn_data[(int) new_icode].operand[0].predicate
6378 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6380 || (insn_data[(int) new_icode].operand[1].predicate
6381 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6382 (real_oldequiv, mode)))))
6383 new_icode = CODE_FOR_nothing;
6385 if (new_icode == CODE_FOR_nothing)
6388 new_mode = insn_data[(int) new_icode].operand[2].mode;
6390 if (GET_MODE (second_reload_reg) != new_mode)
6392 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6394 oldequiv = old, real_oldequiv = real_old;
6397 = gen_rtx_REG (new_mode,
6398 REGNO (second_reload_reg));
6404 /* If we still need a secondary reload register, check
6405 to see if it is being used as a scratch or intermediate
6406 register and generate code appropriately. If we need
6407 a scratch register, use REAL_OLDEQUIV since the form of
6408 the insn may depend on the actual address if it is
6411 if (second_reload_reg)
6413 if (icode != CODE_FOR_nothing)
6415 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6416 second_reload_reg));
6421 /* See if we need a scratch register to load the
6422 intermediate register (a tertiary reload). */
6423 enum insn_code tertiary_icode
6424 = rld[secondary_reload].secondary_in_icode;
6426 if (tertiary_icode != CODE_FOR_nothing)
6428 rtx third_reload_reg
6429 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6431 emit_insn ((GEN_FCN (tertiary_icode)
6432 (second_reload_reg, real_oldequiv,
6433 third_reload_reg)));
6436 gen_reload (second_reload_reg, real_oldequiv,
6440 oldequiv = second_reload_reg;
6446 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6448 rtx real_oldequiv = oldequiv;
6450 if ((GET_CODE (oldequiv) == REG
6451 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6452 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6453 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6454 || (GET_CODE (oldequiv) == SUBREG
6455 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6456 && (REGNO (SUBREG_REG (oldequiv))
6457 >= FIRST_PSEUDO_REGISTER)
6458 && ((reg_equiv_memory_loc
6459 [REGNO (SUBREG_REG (oldequiv))] != 0)
6460 || (reg_equiv_constant
6461 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6462 || (CONSTANT_P (oldequiv)
6463 && PREFERRED_RELOAD_CLASS (oldequiv,
6464 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6465 real_oldequiv = rl->in;
6466 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6470 /* End this sequence. */
6471 *where = get_insns ();
6474 /* Update reload_override_in so that delete_address_reloads_1
6475 can see the actual register usage. */
6477 reload_override_in[j] = oldequiv;
6480 /* Generate insns to for the output reload RL, which is for the insn described
6481 by CHAIN and has the number J. */
6483 emit_output_reload_insns (chain, rl, j)
6484 struct insn_chain *chain;
6488 rtx reloadreg = rl->reg_rtx;
6489 rtx insn = chain->insn;
6492 enum machine_mode mode = GET_MODE (old);
6495 if (rl->when_needed == RELOAD_OTHER)
6498 push_to_sequence (output_reload_insns[rl->opnum]);
6500 /* Determine the mode to reload in.
6501 See comments above (for input reloading). */
6503 if (mode == VOIDmode)
6505 /* VOIDmode should never happen for an output. */
6506 if (asm_noperands (PATTERN (insn)) < 0)
6507 /* It's the compiler's fault. */
6508 fatal_insn ("VOIDmode on an output", insn);
6509 error_for_asm (insn, "output operand is constant in `asm'");
6510 /* Prevent crash--use something we know is valid. */
6512 old = gen_rtx_REG (mode, REGNO (reloadreg));
6515 if (GET_MODE (reloadreg) != mode)
6516 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6518 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6520 /* If we need two reload regs, set RELOADREG to the intermediate
6521 one, since it will be stored into OLD. We might need a secondary
6522 register only for an input reload, so check again here. */
6524 if (rl->secondary_out_reload >= 0)
6528 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6529 && reg_equiv_mem[REGNO (old)] != 0)
6530 real_old = reg_equiv_mem[REGNO (old)];
6532 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6536 rtx second_reloadreg = reloadreg;
6537 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6539 /* See if RELOADREG is to be used as a scratch register
6540 or as an intermediate register. */
6541 if (rl->secondary_out_icode != CODE_FOR_nothing)
6543 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6544 (real_old, second_reloadreg, reloadreg)));
6549 /* See if we need both a scratch and intermediate reload
6552 int secondary_reload = rl->secondary_out_reload;
6553 enum insn_code tertiary_icode
6554 = rld[secondary_reload].secondary_out_icode;
6556 if (GET_MODE (reloadreg) != mode)
6557 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6559 if (tertiary_icode != CODE_FOR_nothing)
6562 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6565 /* Copy primary reload reg to secondary reload reg.
6566 (Note that these have been swapped above, then
6567 secondary reload reg to OLD using our insn. */
6569 /* If REAL_OLD is a paradoxical SUBREG, remove it
6570 and try to put the opposite SUBREG on
6572 if (GET_CODE (real_old) == SUBREG
6573 && (GET_MODE_SIZE (GET_MODE (real_old))
6574 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6575 && 0 != (tem = gen_lowpart_common
6576 (GET_MODE (SUBREG_REG (real_old)),
6578 real_old = SUBREG_REG (real_old), reloadreg = tem;
6580 gen_reload (reloadreg, second_reloadreg,
6581 rl->opnum, rl->when_needed);
6582 emit_insn ((GEN_FCN (tertiary_icode)
6583 (real_old, reloadreg, third_reloadreg)));
6588 /* Copy between the reload regs here and then to
6591 gen_reload (reloadreg, second_reloadreg,
6592 rl->opnum, rl->when_needed);
6598 /* Output the last reload insn. */
6603 /* Don't output the last reload if OLD is not the dest of
6604 INSN and is in the src and is clobbered by INSN. */
6605 if (! flag_expensive_optimizations
6606 || GET_CODE (old) != REG
6607 || !(set = single_set (insn))
6608 || rtx_equal_p (old, SET_DEST (set))
6609 || !reg_mentioned_p (old, SET_SRC (set))
6610 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6611 gen_reload (old, reloadreg, rl->opnum,
6615 /* Look at all insns we emitted, just to be safe. */
6616 for (p = get_insns (); p; p = NEXT_INSN (p))
6619 rtx pat = PATTERN (p);
6621 /* If this output reload doesn't come from a spill reg,
6622 clear any memory of reloaded copies of the pseudo reg.
6623 If this output reload comes from a spill reg,
6624 reg_has_output_reload will make this do nothing. */
6625 note_stores (pat, forget_old_reloads_1, NULL);
6627 if (reg_mentioned_p (rl->reg_rtx, pat))
6629 rtx set = single_set (insn);
6630 if (reload_spill_index[j] < 0
6632 && SET_SRC (set) == rl->reg_rtx)
6634 int src = REGNO (SET_SRC (set));
6636 reload_spill_index[j] = src;
6637 SET_HARD_REG_BIT (reg_is_output_reload, src);
6638 if (find_regno_note (insn, REG_DEAD, src))
6639 SET_HARD_REG_BIT (reg_reloaded_died, src);
6641 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6643 int s = rl->secondary_out_reload;
6644 set = single_set (p);
6645 /* If this reload copies only to the secondary reload
6646 register, the secondary reload does the actual
6648 if (s >= 0 && set == NULL_RTX)
6649 /* We can't tell what function the secondary reload
6650 has and where the actual store to the pseudo is
6651 made; leave new_spill_reg_store alone. */
6654 && SET_SRC (set) == rl->reg_rtx
6655 && SET_DEST (set) == rld[s].reg_rtx)
6657 /* Usually the next instruction will be the
6658 secondary reload insn; if we can confirm
6659 that it is, setting new_spill_reg_store to
6660 that insn will allow an extra optimization. */
6661 rtx s_reg = rld[s].reg_rtx;
6662 rtx next = NEXT_INSN (p);
6663 rld[s].out = rl->out;
6664 rld[s].out_reg = rl->out_reg;
6665 set = single_set (next);
6666 if (set && SET_SRC (set) == s_reg
6667 && ! new_spill_reg_store[REGNO (s_reg)])
6669 SET_HARD_REG_BIT (reg_is_output_reload,
6671 new_spill_reg_store[REGNO (s_reg)] = next;
6675 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6680 if (rl->when_needed == RELOAD_OTHER)
6682 emit_insns (other_output_reload_insns[rl->opnum]);
6683 other_output_reload_insns[rl->opnum] = get_insns ();
6686 output_reload_insns[rl->opnum] = get_insns ();
6691 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6692 and has the number J. */
6694 do_input_reload (chain, rl, j)
6695 struct insn_chain *chain;
6699 int expect_occurrences = 1;
6700 rtx insn = chain->insn;
6701 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6702 ? rl->in_reg : rl->in);
6705 /* AUTO_INC reloads need to be handled even if inherited. We got an
6706 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6707 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6708 && ! rtx_equal_p (rl->reg_rtx, old)
6709 && rl->reg_rtx != 0)
6710 emit_input_reload_insns (chain, rld + j, old, j);
6712 /* When inheriting a wider reload, we have a MEM in rl->in,
6713 e.g. inheriting a SImode output reload for
6714 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6715 if (optimize && reload_inherited[j] && rl->in
6716 && GET_CODE (rl->in) == MEM
6717 && GET_CODE (rl->in_reg) == MEM
6718 && reload_spill_index[j] >= 0
6719 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6722 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6723 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6726 /* If we are reloading a register that was recently stored in with an
6727 output-reload, see if we can prove there was
6728 actually no need to store the old value in it. */
6731 && (reload_inherited[j] || reload_override_in[j])
6733 && GET_CODE (rl->reg_rtx) == REG
6734 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6736 /* There doesn't seem to be any reason to restrict this to pseudos
6737 and doing so loses in the case where we are copying from a
6738 register of the wrong class. */
6739 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6740 >= FIRST_PSEUDO_REGISTER)
6742 /* The insn might have already some references to stackslots
6743 replaced by MEMs, while reload_out_reg still names the
6745 && (dead_or_set_p (insn,
6746 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6747 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6749 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6752 /* Do output reloading for reload RL, which is for the insn described by
6753 CHAIN and has the number J.
6754 ??? At some point we need to support handling output reloads of
6755 JUMP_INSNs or insns that set cc0. */
6757 do_output_reload (chain, rl, j)
6758 struct insn_chain *chain;
6763 rtx insn = chain->insn;
6764 /* If this is an output reload that stores something that is
6765 not loaded in this same reload, see if we can eliminate a previous
6767 rtx pseudo = rl->out_reg;
6770 && GET_CODE (pseudo) == REG
6771 && ! rtx_equal_p (rl->in_reg, pseudo)
6772 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6773 && reg_last_reload_reg[REGNO (pseudo)])
6775 int pseudo_no = REGNO (pseudo);
6776 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6778 /* We don't need to test full validity of last_regno for
6779 inherit here; we only want to know if the store actually
6780 matches the pseudo. */
6781 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6782 && reg_reloaded_contents[last_regno] == pseudo_no
6783 && spill_reg_store[last_regno]
6784 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6785 delete_output_reload (insn, j, last_regno);
6790 || rl->reg_rtx == old
6791 || rl->reg_rtx == 0)
6794 /* An output operand that dies right away does need a reload,
6795 but need not be copied from it. Show the new location in the
6797 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6798 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6800 XEXP (note, 0) = rl->reg_rtx;
6803 /* Likewise for a SUBREG of an operand that dies. */
6804 else if (GET_CODE (old) == SUBREG
6805 && GET_CODE (SUBREG_REG (old)) == REG
6806 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6809 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6813 else if (GET_CODE (old) == SCRATCH)
6814 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6815 but we don't want to make an output reload. */
6818 /* If is a JUMP_INSN, we can't support output reloads yet. */
6819 if (GET_CODE (insn) == JUMP_INSN)
6822 emit_output_reload_insns (chain, rld + j, j);
6825 /* Output insns to reload values in and out of the chosen reload regs. */
6828 emit_reload_insns (chain)
6829 struct insn_chain *chain;
6831 rtx insn = chain->insn;
6834 rtx following_insn = NEXT_INSN (insn);
6835 rtx before_insn = PREV_INSN (insn);
6837 CLEAR_HARD_REG_SET (reg_reloaded_died);
6839 for (j = 0; j < reload_n_operands; j++)
6840 input_reload_insns[j] = input_address_reload_insns[j]
6841 = inpaddr_address_reload_insns[j]
6842 = output_reload_insns[j] = output_address_reload_insns[j]
6843 = outaddr_address_reload_insns[j]
6844 = other_output_reload_insns[j] = 0;
6845 other_input_address_reload_insns = 0;
6846 other_input_reload_insns = 0;
6847 operand_reload_insns = 0;
6848 other_operand_reload_insns = 0;
6850 /* Dump reloads into the dump file. */
6853 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6854 debug_reload_to_stream (rtl_dump_file);
6857 /* Now output the instructions to copy the data into and out of the
6858 reload registers. Do these in the order that the reloads were reported,
6859 since reloads of base and index registers precede reloads of operands
6860 and the operands may need the base and index registers reloaded. */
6862 for (j = 0; j < n_reloads; j++)
6865 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6866 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6868 do_input_reload (chain, rld + j, j);
6869 do_output_reload (chain, rld + j, j);
6872 /* Now write all the insns we made for reloads in the order expected by
6873 the allocation functions. Prior to the insn being reloaded, we write
6874 the following reloads:
6876 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6878 RELOAD_OTHER reloads.
6880 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6881 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6882 RELOAD_FOR_INPUT reload for the operand.
6884 RELOAD_FOR_OPADDR_ADDRS reloads.
6886 RELOAD_FOR_OPERAND_ADDRESS reloads.
6888 After the insn being reloaded, we write the following:
6890 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6891 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6892 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6893 reloads for the operand. The RELOAD_OTHER output reloads are
6894 output in descending order by reload number. */
6896 emit_insns_before (other_input_address_reload_insns, insn);
6897 emit_insns_before (other_input_reload_insns, insn);
6899 for (j = 0; j < reload_n_operands; j++)
6901 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6902 emit_insns_before (input_address_reload_insns[j], insn);
6903 emit_insns_before (input_reload_insns[j], insn);
6906 emit_insns_before (other_operand_reload_insns, insn);
6907 emit_insns_before (operand_reload_insns, insn);
6909 for (j = 0; j < reload_n_operands; j++)
6911 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6912 emit_insns_before (output_address_reload_insns[j], following_insn);
6913 emit_insns_before (output_reload_insns[j], following_insn);
6914 emit_insns_before (other_output_reload_insns[j], following_insn);
6917 /* Keep basic block info up to date. */
6920 if (BLOCK_HEAD (chain->block) == insn)
6921 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6922 if (BLOCK_END (chain->block) == insn)
6923 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6926 /* For all the spill regs newly reloaded in this instruction,
6927 record what they were reloaded from, so subsequent instructions
6928 can inherit the reloads.
6930 Update spill_reg_store for the reloads of this insn.
6931 Copy the elements that were updated in the loop above. */
6933 for (j = 0; j < n_reloads; j++)
6935 register int r = reload_order[j];
6936 register int i = reload_spill_index[r];
6938 /* If this is a non-inherited input reload from a pseudo, we must
6939 clear any memory of a previous store to the same pseudo. Only do
6940 something if there will not be an output reload for the pseudo
6942 if (rld[r].in_reg != 0
6943 && ! (reload_inherited[r] || reload_override_in[r]))
6945 rtx reg = rld[r].in_reg;
6947 if (GET_CODE (reg) == SUBREG)
6948 reg = SUBREG_REG (reg);
6950 if (GET_CODE (reg) == REG
6951 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6952 && ! reg_has_output_reload[REGNO (reg)])
6954 int nregno = REGNO (reg);
6956 if (reg_last_reload_reg[nregno])
6958 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6960 if (reg_reloaded_contents[last_regno] == nregno)
6961 spill_reg_store[last_regno] = 0;
6966 /* I is nonneg if this reload used a register.
6967 If rld[r].reg_rtx is 0, this is an optional reload
6968 that we opted to ignore. */
6970 if (i >= 0 && rld[r].reg_rtx != 0)
6972 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6974 int part_reaches_end = 0;
6975 int all_reaches_end = 1;
6977 /* For a multi register reload, we need to check if all or part
6978 of the value lives to the end. */
6979 for (k = 0; k < nr; k++)
6981 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6982 rld[r].when_needed))
6983 part_reaches_end = 1;
6985 all_reaches_end = 0;
6988 /* Ignore reloads that don't reach the end of the insn in
6990 if (all_reaches_end)
6992 /* First, clear out memory of what used to be in this spill reg.
6993 If consecutive registers are used, clear them all. */
6995 for (k = 0; k < nr; k++)
6996 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6998 /* Maybe the spill reg contains a copy of reload_out. */
7000 && (GET_CODE (rld[r].out) == REG
7004 || GET_CODE (rld[r].out_reg) == REG))
7006 rtx out = (GET_CODE (rld[r].out) == REG
7010 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7011 register int nregno = REGNO (out);
7012 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7013 : HARD_REGNO_NREGS (nregno,
7014 GET_MODE (rld[r].reg_rtx)));
7016 spill_reg_store[i] = new_spill_reg_store[i];
7017 spill_reg_stored_to[i] = out;
7018 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7020 /* If NREGNO is a hard register, it may occupy more than
7021 one register. If it does, say what is in the
7022 rest of the registers assuming that both registers
7023 agree on how many words the object takes. If not,
7024 invalidate the subsequent registers. */
7026 if (nregno < FIRST_PSEUDO_REGISTER)
7027 for (k = 1; k < nnr; k++)
7028 reg_last_reload_reg[nregno + k]
7030 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7031 REGNO (rld[r].reg_rtx) + k)
7034 /* Now do the inverse operation. */
7035 for (k = 0; k < nr; k++)
7037 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7038 reg_reloaded_contents[i + k]
7039 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7042 reg_reloaded_insn[i + k] = insn;
7043 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7047 /* Maybe the spill reg contains a copy of reload_in. Only do
7048 something if there will not be an output reload for
7049 the register being reloaded. */
7050 else if (rld[r].out_reg == 0
7052 && ((GET_CODE (rld[r].in) == REG
7053 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7054 && ! reg_has_output_reload[REGNO (rld[r].in)])
7055 || (GET_CODE (rld[r].in_reg) == REG
7056 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7057 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7059 register int nregno;
7062 if (GET_CODE (rld[r].in) == REG
7063 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7064 nregno = REGNO (rld[r].in);
7065 else if (GET_CODE (rld[r].in_reg) == REG)
7066 nregno = REGNO (rld[r].in_reg);
7068 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7070 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7071 : HARD_REGNO_NREGS (nregno,
7072 GET_MODE (rld[r].reg_rtx)));
7074 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7076 if (nregno < FIRST_PSEUDO_REGISTER)
7077 for (k = 1; k < nnr; k++)
7078 reg_last_reload_reg[nregno + k]
7080 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7081 REGNO (rld[r].reg_rtx) + k)
7084 /* Unless we inherited this reload, show we haven't
7085 recently done a store.
7086 Previous stores of inherited auto_inc expressions
7087 also have to be discarded. */
7088 if (! reload_inherited[r]
7089 || (rld[r].out && ! rld[r].out_reg))
7090 spill_reg_store[i] = 0;
7092 for (k = 0; k < nr; k++)
7094 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7095 reg_reloaded_contents[i + k]
7096 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7099 reg_reloaded_insn[i + k] = insn;
7100 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7105 /* However, if part of the reload reaches the end, then we must
7106 invalidate the old info for the part that survives to the end. */
7107 else if (part_reaches_end)
7109 for (k = 0; k < nr; k++)
7110 if (reload_reg_reaches_end_p (i + k,
7112 rld[r].when_needed))
7113 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7117 /* The following if-statement was #if 0'd in 1.34 (or before...).
7118 It's reenabled in 1.35 because supposedly nothing else
7119 deals with this problem. */
7121 /* If a register gets output-reloaded from a non-spill register,
7122 that invalidates any previous reloaded copy of it.
7123 But forget_old_reloads_1 won't get to see it, because
7124 it thinks only about the original insn. So invalidate it here. */
7125 if (i < 0 && rld[r].out != 0
7126 && (GET_CODE (rld[r].out) == REG
7127 || (GET_CODE (rld[r].out) == MEM
7128 && GET_CODE (rld[r].out_reg) == REG)))
7130 rtx out = (GET_CODE (rld[r].out) == REG
7131 ? rld[r].out : rld[r].out_reg);
7132 register int nregno = REGNO (out);
7133 if (nregno >= FIRST_PSEUDO_REGISTER)
7135 rtx src_reg, store_insn = NULL_RTX;
7137 reg_last_reload_reg[nregno] = 0;
7139 /* If we can find a hard register that is stored, record
7140 the storing insn so that we may delete this insn with
7141 delete_output_reload. */
7142 src_reg = rld[r].reg_rtx;
7144 /* If this is an optional reload, try to find the source reg
7145 from an input reload. */
7148 rtx set = single_set (insn);
7149 if (set && SET_DEST (set) == rld[r].out)
7153 src_reg = SET_SRC (set);
7155 for (k = 0; k < n_reloads; k++)
7157 if (rld[k].in == src_reg)
7159 src_reg = rld[k].reg_rtx;
7166 store_insn = new_spill_reg_store[REGNO (src_reg)];
7167 if (src_reg && GET_CODE (src_reg) == REG
7168 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7170 int src_regno = REGNO (src_reg);
7171 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7172 /* The place where to find a death note varies with
7173 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7174 necessarily checked exactly in the code that moves
7175 notes, so just check both locations. */
7176 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7178 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7181 spill_reg_store[src_regno + nr] = store_insn;
7182 spill_reg_stored_to[src_regno + nr] = out;
7183 reg_reloaded_contents[src_regno + nr] = nregno;
7184 reg_reloaded_insn[src_regno + nr] = store_insn;
7185 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7186 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7187 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7189 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7191 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7193 reg_last_reload_reg[nregno] = src_reg;
7198 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7200 while (num_regs-- > 0)
7201 reg_last_reload_reg[nregno + num_regs] = 0;
7205 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7208 /* Emit code to perform a reload from IN (which may be a reload register) to
7209 OUT (which may also be a reload register). IN or OUT is from operand
7210 OPNUM with reload type TYPE.
7212 Returns first insn emitted. */
7215 gen_reload (out, in, opnum, type)
7219 enum reload_type type;
7221 rtx last = get_last_insn ();
7224 /* If IN is a paradoxical SUBREG, remove it and try to put the
7225 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7226 if (GET_CODE (in) == SUBREG
7227 && (GET_MODE_SIZE (GET_MODE (in))
7228 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7229 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7230 in = SUBREG_REG (in), out = tem;
7231 else if (GET_CODE (out) == SUBREG
7232 && (GET_MODE_SIZE (GET_MODE (out))
7233 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7234 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7235 out = SUBREG_REG (out), in = tem;
7237 /* How to do this reload can get quite tricky. Normally, we are being
7238 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7239 register that didn't get a hard register. In that case we can just
7240 call emit_move_insn.
7242 We can also be asked to reload a PLUS that adds a register or a MEM to
7243 another register, constant or MEM. This can occur during frame pointer
7244 elimination and while reloading addresses. This case is handled by
7245 trying to emit a single insn to perform the add. If it is not valid,
7246 we use a two insn sequence.
7248 Finally, we could be called to handle an 'o' constraint by putting
7249 an address into a register. In that case, we first try to do this
7250 with a named pattern of "reload_load_address". If no such pattern
7251 exists, we just emit a SET insn and hope for the best (it will normally
7252 be valid on machines that use 'o').
7254 This entire process is made complex because reload will never
7255 process the insns we generate here and so we must ensure that
7256 they will fit their constraints and also by the fact that parts of
7257 IN might be being reloaded separately and replaced with spill registers.
7258 Because of this, we are, in some sense, just guessing the right approach
7259 here. The one listed above seems to work.
7261 ??? At some point, this whole thing needs to be rethought. */
7263 if (GET_CODE (in) == PLUS
7264 && (GET_CODE (XEXP (in, 0)) == REG
7265 || GET_CODE (XEXP (in, 0)) == SUBREG
7266 || GET_CODE (XEXP (in, 0)) == MEM)
7267 && (GET_CODE (XEXP (in, 1)) == REG
7268 || GET_CODE (XEXP (in, 1)) == SUBREG
7269 || CONSTANT_P (XEXP (in, 1))
7270 || GET_CODE (XEXP (in, 1)) == MEM))
7272 /* We need to compute the sum of a register or a MEM and another
7273 register, constant, or MEM, and put it into the reload
7274 register. The best possible way of doing this is if the machine
7275 has a three-operand ADD insn that accepts the required operands.
7277 The simplest approach is to try to generate such an insn and see if it
7278 is recognized and matches its constraints. If so, it can be used.
7280 It might be better not to actually emit the insn unless it is valid,
7281 but we need to pass the insn as an operand to `recog' and
7282 `extract_insn' and it is simpler to emit and then delete the insn if
7283 not valid than to dummy things up. */
7285 rtx op0, op1, tem, insn;
7288 op0 = find_replacement (&XEXP (in, 0));
7289 op1 = find_replacement (&XEXP (in, 1));
7291 /* Since constraint checking is strict, commutativity won't be
7292 checked, so we need to do that here to avoid spurious failure
7293 if the add instruction is two-address and the second operand
7294 of the add is the same as the reload reg, which is frequently
7295 the case. If the insn would be A = B + A, rearrange it so
7296 it will be A = A + B as constrain_operands expects. */
7298 if (GET_CODE (XEXP (in, 1)) == REG
7299 && REGNO (out) == REGNO (XEXP (in, 1)))
7300 tem = op0, op0 = op1, op1 = tem;
7302 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7303 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7305 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7306 code = recog_memoized (insn);
7310 extract_insn (insn);
7311 /* We want constrain operands to treat this insn strictly in
7312 its validity determination, i.e., the way it would after reload
7314 if (constrain_operands (1))
7318 delete_insns_since (last);
7320 /* If that failed, we must use a conservative two-insn sequence.
7322 Use a move to copy one operand into the reload register. Prefer
7323 to reload a constant, MEM or pseudo since the move patterns can
7324 handle an arbitrary operand. If OP1 is not a constant, MEM or
7325 pseudo and OP1 is not a valid operand for an add instruction, then
7328 After reloading one of the operands into the reload register, add
7329 the reload register to the output register.
7331 If there is another way to do this for a specific machine, a
7332 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7335 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7337 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7338 || (GET_CODE (op1) == REG
7339 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7340 || (code != CODE_FOR_nothing
7341 && ! ((*insn_data[code].operand[2].predicate)
7342 (op1, insn_data[code].operand[2].mode))))
7343 tem = op0, op0 = op1, op1 = tem;
7345 gen_reload (out, op0, opnum, type);
7347 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7348 This fixes a problem on the 32K where the stack pointer cannot
7349 be used as an operand of an add insn. */
7351 if (rtx_equal_p (op0, op1))
7354 insn = emit_insn (gen_add2_insn (out, op1));
7356 /* If that failed, copy the address register to the reload register.
7357 Then add the constant to the reload register. */
7359 code = recog_memoized (insn);
7363 extract_insn (insn);
7364 /* We want constrain operands to treat this insn strictly in
7365 its validity determination, i.e., the way it would after reload
7367 if (constrain_operands (1))
7369 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7371 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7376 delete_insns_since (last);
7378 gen_reload (out, op1, opnum, type);
7379 insn = emit_insn (gen_add2_insn (out, op0));
7380 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7383 #ifdef SECONDARY_MEMORY_NEEDED
7384 /* If we need a memory location to do the move, do it that way. */
7385 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7386 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7387 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7388 REGNO_REG_CLASS (REGNO (out)),
7391 /* Get the memory to use and rewrite both registers to its mode. */
7392 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7394 if (GET_MODE (loc) != GET_MODE (out))
7395 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7397 if (GET_MODE (loc) != GET_MODE (in))
7398 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7400 gen_reload (loc, in, opnum, type);
7401 gen_reload (out, loc, opnum, type);
7405 /* If IN is a simple operand, use gen_move_insn. */
7406 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7407 emit_insn (gen_move_insn (out, in));
7409 #ifdef HAVE_reload_load_address
7410 else if (HAVE_reload_load_address)
7411 emit_insn (gen_reload_load_address (out, in));
7414 /* Otherwise, just write (set OUT IN) and hope for the best. */
7416 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7418 /* Return the first insn emitted.
7419 We can not just return get_last_insn, because there may have
7420 been multiple instructions emitted. Also note that gen_move_insn may
7421 emit more than one insn itself, so we can not assume that there is one
7422 insn emitted per emit_insn_before call. */
7424 return last ? NEXT_INSN (last) : get_insns ();
7427 /* Delete a previously made output-reload
7428 whose result we now believe is not needed.
7429 First we double-check.
7431 INSN is the insn now being processed.
7432 LAST_RELOAD_REG is the hard register number for which we want to delete
7433 the last output reload.
7434 J is the reload-number that originally used REG. The caller has made
7435 certain that reload J doesn't use REG any longer for input. */
7438 delete_output_reload (insn, j, last_reload_reg)
7441 int last_reload_reg;
7443 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7444 rtx reg = spill_reg_stored_to[last_reload_reg];
7447 int n_inherited = 0;
7451 /* Get the raw pseudo-register referred to. */
7453 while (GET_CODE (reg) == SUBREG)
7454 reg = SUBREG_REG (reg);
7455 substed = reg_equiv_memory_loc[REGNO (reg)];
7457 /* This is unsafe if the operand occurs more often in the current
7458 insn than it is inherited. */
7459 for (k = n_reloads - 1; k >= 0; k--)
7461 rtx reg2 = rld[k].in;
7464 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7465 reg2 = rld[k].in_reg;
7467 if (rld[k].out && ! rld[k].out_reg)
7468 reg2 = XEXP (rld[k].in_reg, 0);
7470 while (GET_CODE (reg2) == SUBREG)
7471 reg2 = SUBREG_REG (reg2);
7472 if (rtx_equal_p (reg2, reg))
7474 if (reload_inherited[k] || reload_override_in[k] || k == j)
7477 reg2 = rld[k].out_reg;
7480 while (GET_CODE (reg2) == SUBREG)
7481 reg2 = XEXP (reg2, 0);
7482 if (rtx_equal_p (reg2, reg))
7489 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7491 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7492 if (n_occurrences > n_inherited)
7495 /* If the pseudo-reg we are reloading is no longer referenced
7496 anywhere between the store into it and here,
7497 and no jumps or labels intervene, then the value can get
7498 here through the reload reg alone.
7499 Otherwise, give up--return. */
7500 for (i1 = NEXT_INSN (output_reload_insn);
7501 i1 != insn; i1 = NEXT_INSN (i1))
7503 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7505 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7506 && reg_mentioned_p (reg, PATTERN (i1)))
7508 /* If this is USE in front of INSN, we only have to check that
7509 there are no more references than accounted for by inheritance. */
7510 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7512 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7513 i1 = NEXT_INSN (i1);
7515 if (n_occurrences <= n_inherited && i1 == insn)
7521 /* The caller has already checked that REG dies or is set in INSN.
7522 It has also checked that we are optimizing, and thus some inaccurancies
7523 in the debugging information are acceptable.
7524 So we could just delete output_reload_insn.
7525 But in some cases we can improve the debugging information without
7526 sacrificing optimization - maybe even improving the code:
7527 See if the pseudo reg has been completely replaced
7528 with reload regs. If so, delete the store insn
7529 and forget we had a stack slot for the pseudo. */
7530 if (rld[j].out != rld[j].in
7531 && REG_N_DEATHS (REGNO (reg)) == 1
7532 && REG_N_SETS (REGNO (reg)) == 1
7533 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7534 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7538 /* We know that it was used only between here
7539 and the beginning of the current basic block.
7540 (We also know that the last use before INSN was
7541 the output reload we are thinking of deleting, but never mind that.)
7542 Search that range; see if any ref remains. */
7543 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7545 rtx set = single_set (i2);
7547 /* Uses which just store in the pseudo don't count,
7548 since if they are the only uses, they are dead. */
7549 if (set != 0 && SET_DEST (set) == reg)
7551 if (GET_CODE (i2) == CODE_LABEL
7552 || GET_CODE (i2) == JUMP_INSN)
7554 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7555 && reg_mentioned_p (reg, PATTERN (i2)))
7557 /* Some other ref remains; just delete the output reload we
7559 delete_address_reloads (output_reload_insn, insn);
7560 PUT_CODE (output_reload_insn, NOTE);
7561 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7562 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7567 /* Delete the now-dead stores into this pseudo. */
7568 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7570 rtx set = single_set (i2);
7572 if (set != 0 && SET_DEST (set) == reg)
7574 delete_address_reloads (i2, insn);
7575 /* This might be a basic block head,
7576 thus don't use delete_insn. */
7577 PUT_CODE (i2, NOTE);
7578 NOTE_SOURCE_FILE (i2) = 0;
7579 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7581 if (GET_CODE (i2) == CODE_LABEL
7582 || GET_CODE (i2) == JUMP_INSN)
7586 /* For the debugging info,
7587 say the pseudo lives in this reload reg. */
7588 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7589 alter_reg (REGNO (reg), -1);
7591 delete_address_reloads (output_reload_insn, insn);
7592 PUT_CODE (output_reload_insn, NOTE);
7593 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7594 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7598 /* We are going to delete DEAD_INSN. Recursively delete loads of
7599 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7600 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7602 delete_address_reloads (dead_insn, current_insn)
7603 rtx dead_insn, current_insn;
7605 rtx set = single_set (dead_insn);
7606 rtx set2, dst, prev, next;
7609 rtx dst = SET_DEST (set);
7610 if (GET_CODE (dst) == MEM)
7611 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7613 /* If we deleted the store from a reloaded post_{in,de}c expression,
7614 we can delete the matching adds. */
7615 prev = PREV_INSN (dead_insn);
7616 next = NEXT_INSN (dead_insn);
7617 if (! prev || ! next)
7619 set = single_set (next);
7620 set2 = single_set (prev);
7622 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7623 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7624 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7626 dst = SET_DEST (set);
7627 if (! rtx_equal_p (dst, SET_DEST (set2))
7628 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7629 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7630 || (INTVAL (XEXP (SET_SRC (set), 1))
7631 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7637 /* Subfunction of delete_address_reloads: process registers found in X. */
7639 delete_address_reloads_1 (dead_insn, x, current_insn)
7640 rtx dead_insn, x, current_insn;
7642 rtx prev, set, dst, i2;
7644 enum rtx_code code = GET_CODE (x);
7648 const char *fmt = GET_RTX_FORMAT (code);
7649 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7652 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7653 else if (fmt[i] == 'E')
7655 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7656 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7663 if (spill_reg_order[REGNO (x)] < 0)
7666 /* Scan backwards for the insn that sets x. This might be a way back due
7668 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7670 code = GET_CODE (prev);
7671 if (code == CODE_LABEL || code == JUMP_INSN)
7673 if (GET_RTX_CLASS (code) != 'i')
7675 if (reg_set_p (x, PATTERN (prev)))
7677 if (reg_referenced_p (x, PATTERN (prev)))
7680 if (! prev || INSN_UID (prev) < reload_first_uid)
7682 /* Check that PREV only sets the reload register. */
7683 set = single_set (prev);
7686 dst = SET_DEST (set);
7687 if (GET_CODE (dst) != REG
7688 || ! rtx_equal_p (dst, x))
7690 if (! reg_set_p (dst, PATTERN (dead_insn)))
7692 /* Check if DST was used in a later insn -
7693 it might have been inherited. */
7694 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7696 if (GET_CODE (i2) == CODE_LABEL)
7700 if (reg_referenced_p (dst, PATTERN (i2)))
7702 /* If there is a reference to the register in the current insn,
7703 it might be loaded in a non-inherited reload. If no other
7704 reload uses it, that means the register is set before
7706 if (i2 == current_insn)
7708 for (j = n_reloads - 1; j >= 0; j--)
7709 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7710 || reload_override_in[j] == dst)
7712 for (j = n_reloads - 1; j >= 0; j--)
7713 if (rld[j].in && rld[j].reg_rtx == dst)
7720 if (GET_CODE (i2) == JUMP_INSN)
7722 /* If DST is still live at CURRENT_INSN, check if it is used for
7723 any reload. Note that even if CURRENT_INSN sets DST, we still
7724 have to check the reloads. */
7725 if (i2 == current_insn)
7727 for (j = n_reloads - 1; j >= 0; j--)
7728 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7729 || reload_override_in[j] == dst)
7731 /* ??? We can't finish the loop here, because dst might be
7732 allocated to a pseudo in this block if no reload in this
7733 block needs any of the clsses containing DST - see
7734 spill_hard_reg. There is no easy way to tell this, so we
7735 have to scan till the end of the basic block. */
7737 if (reg_set_p (dst, PATTERN (i2)))
7741 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7742 reg_reloaded_contents[REGNO (dst)] = -1;
7743 /* Can't use delete_insn here because PREV might be a basic block head. */
7744 PUT_CODE (prev, NOTE);
7745 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7746 NOTE_SOURCE_FILE (prev) = 0;
7749 /* Output reload-insns to reload VALUE into RELOADREG.
7750 VALUE is an autoincrement or autodecrement RTX whose operand
7751 is a register or memory location;
7752 so reloading involves incrementing that location.
7753 IN is either identical to VALUE, or some cheaper place to reload from.
7755 INC_AMOUNT is the number to increment or decrement by (always positive).
7756 This cannot be deduced from VALUE.
7758 Return the instruction that stores into RELOADREG. */
7761 inc_for_reload (reloadreg, in, value, inc_amount)
7766 /* REG or MEM to be copied and incremented. */
7767 rtx incloc = XEXP (value, 0);
7768 /* Nonzero if increment after copying. */
7769 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7775 rtx real_in = in == value ? XEXP (in, 0) : in;
7777 /* No hard register is equivalent to this register after
7778 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7779 we could inc/dec that register as well (maybe even using it for
7780 the source), but I'm not sure it's worth worrying about. */
7781 if (GET_CODE (incloc) == REG)
7782 reg_last_reload_reg[REGNO (incloc)] = 0;
7784 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7785 inc_amount = -inc_amount;
7787 inc = GEN_INT (inc_amount);
7789 /* If this is post-increment, first copy the location to the reload reg. */
7790 if (post && real_in != reloadreg)
7791 emit_insn (gen_move_insn (reloadreg, real_in));
7795 /* See if we can directly increment INCLOC. Use a method similar to
7796 that in gen_reload. */
7798 last = get_last_insn ();
7799 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7800 gen_rtx_PLUS (GET_MODE (incloc),
7803 code = recog_memoized (add_insn);
7806 extract_insn (add_insn);
7807 if (constrain_operands (1))
7809 /* If this is a pre-increment and we have incremented the value
7810 where it lives, copy the incremented value to RELOADREG to
7811 be used as an address. */
7814 emit_insn (gen_move_insn (reloadreg, incloc));
7819 delete_insns_since (last);
7822 /* If couldn't do the increment directly, must increment in RELOADREG.
7823 The way we do this depends on whether this is pre- or post-increment.
7824 For pre-increment, copy INCLOC to the reload register, increment it
7825 there, then save back. */
7829 if (in != reloadreg)
7830 emit_insn (gen_move_insn (reloadreg, real_in));
7831 emit_insn (gen_add2_insn (reloadreg, inc));
7832 store = emit_insn (gen_move_insn (incloc, reloadreg));
7837 Because this might be a jump insn or a compare, and because RELOADREG
7838 may not be available after the insn in an input reload, we must do
7839 the incrementation before the insn being reloaded for.
7841 We have already copied IN to RELOADREG. Increment the copy in
7842 RELOADREG, save that back, then decrement RELOADREG so it has
7843 the original value. */
7845 emit_insn (gen_add2_insn (reloadreg, inc));
7846 store = emit_insn (gen_move_insn (incloc, reloadreg));
7847 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7853 /* Return 1 if we are certain that the constraint-string STRING allows
7854 the hard register REG. Return 0 if we can't be sure of this. */
7857 constraint_accepts_reg_p (string, reg)
7862 int regno = true_regnum (reg);
7865 /* Initialize for first alternative. */
7867 /* Check that each alternative contains `g' or `r'. */
7869 switch (c = *string++)
7872 /* If an alternative lacks `g' or `r', we lose. */
7875 /* If an alternative lacks `g' or `r', we lose. */
7878 /* Initialize for next alternative. */
7883 /* Any general reg wins for this alternative. */
7884 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7888 /* Any reg in specified class wins for this alternative. */
7890 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7892 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7898 /* INSN is a no-op; delete it.
7899 If this sets the return value of the function, we must keep a USE around,
7900 in case this is in a different basic block than the final USE. Otherwise,
7901 we could loose important register lifeness information on
7902 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7903 spills: subsequent passes assume that spill registers are dead at the end
7905 VALUE must be the return value in such a case, NULL otherwise. */
7907 reload_cse_delete_noop_set (insn, value)
7912 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7913 INSN_CODE (insn) = -1;
7914 REG_NOTES (insn) = NULL_RTX;
7918 PUT_CODE (insn, NOTE);
7919 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7920 NOTE_SOURCE_FILE (insn) = 0;
7924 /* See whether a single set SET is a noop. */
7926 reload_cse_noop_set_p (set)
7929 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7932 /* Try to simplify INSN. */
7934 reload_cse_simplify (insn)
7937 rtx body = PATTERN (insn);
7939 if (GET_CODE (body) == SET)
7942 if (reload_cse_noop_set_p (body))
7944 rtx value = SET_DEST (body);
7945 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7947 reload_cse_delete_noop_set (insn, value);
7951 /* It's not a no-op, but we can try to simplify it. */
7952 count += reload_cse_simplify_set (body, insn);
7955 apply_change_group ();
7957 reload_cse_simplify_operands (insn);
7959 else if (GET_CODE (body) == PARALLEL)
7963 rtx value = NULL_RTX;
7965 /* If every action in a PARALLEL is a noop, we can delete
7966 the entire PARALLEL. */
7967 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7969 rtx part = XVECEXP (body, 0, i);
7970 if (GET_CODE (part) == SET)
7972 if (! reload_cse_noop_set_p (part))
7974 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7978 value = SET_DEST (part);
7981 else if (GET_CODE (part) != CLOBBER)
7987 reload_cse_delete_noop_set (insn, value);
7988 /* We're done with this insn. */
7992 /* It's not a no-op, but we can try to simplify it. */
7993 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7994 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7995 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7998 apply_change_group ();
8000 reload_cse_simplify_operands (insn);
8004 /* Do a very simple CSE pass over the hard registers.
8006 This function detects no-op moves where we happened to assign two
8007 different pseudo-registers to the same hard register, and then
8008 copied one to the other. Reload will generate a useless
8009 instruction copying a register to itself.
8011 This function also detects cases where we load a value from memory
8012 into two different registers, and (if memory is more expensive than
8013 registers) changes it to simply copy the first register into the
8016 Another optimization is performed that scans the operands of each
8017 instruction to see whether the value is already available in a
8018 hard register. It then replaces the operand with the hard register
8019 if possible, much like an optional reload would. */
8022 reload_cse_regs_1 (first)
8028 init_alias_analysis ();
8030 for (insn = first; insn; insn = NEXT_INSN (insn))
8033 reload_cse_simplify (insn);
8035 cselib_process_insn (insn);
8039 end_alias_analysis ();
8043 /* Call cse / combine like post-reload optimization phases.
8044 FIRST is the first instruction. */
8046 reload_cse_regs (first)
8049 reload_cse_regs_1 (first);
8051 reload_cse_move2add (first);
8052 if (flag_expensive_optimizations)
8053 reload_cse_regs_1 (first);
8056 /* Try to simplify a single SET instruction. SET is the set pattern.
8057 INSN is the instruction it came from.
8058 This function only handles one case: if we set a register to a value
8059 which is not a register, we try to find that value in some other register
8060 and change the set into a register copy. */
8063 reload_cse_simplify_set (set, insn)
8070 enum reg_class dclass;
8073 struct elt_loc_list *l;
8075 dreg = true_regnum (SET_DEST (set));
8079 src = SET_SRC (set);
8080 if (side_effects_p (src) || true_regnum (src) >= 0)
8083 dclass = REGNO_REG_CLASS (dreg);
8085 /* If memory loads are cheaper than register copies, don't change them. */
8086 if (GET_CODE (src) == MEM)
8087 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8088 else if (CONSTANT_P (src))
8089 old_cost = rtx_cost (src, SET);
8090 else if (GET_CODE (src) == REG)
8091 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8094 old_cost = rtx_cost (src, SET);
8096 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8099 for (l = val->locs; l; l = l->next)
8102 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8103 this_cost = rtx_cost (l->loc, SET);
8104 else if (GET_CODE (l->loc) == REG)
8105 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8109 /* If equal costs, prefer registers over anything else. That tends to
8110 lead to smaller instructions on some machines. */
8111 if ((this_cost < old_cost
8112 || (this_cost == old_cost
8113 && GET_CODE (l->loc) == REG
8114 && GET_CODE (SET_SRC (set)) != REG))
8115 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8116 old_cost = this_cost, did_change = 1;
8122 /* Try to replace operands in INSN with equivalent values that are already
8123 in registers. This can be viewed as optional reloading.
8125 For each non-register operand in the insn, see if any hard regs are
8126 known to be equivalent to that operand. Record the alternatives which
8127 can accept these hard registers. Among all alternatives, select the
8128 ones which are better or equal to the one currently matching, where
8129 "better" is in terms of '?' and '!' constraints. Among the remaining
8130 alternatives, select the one which replaces most operands with
8134 reload_cse_simplify_operands (insn)
8139 /* For each operand, all registers that are equivalent to it. */
8140 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8142 const char *constraints[MAX_RECOG_OPERANDS];
8144 /* Vector recording how bad an alternative is. */
8145 int *alternative_reject;
8146 /* Vector recording how many registers can be introduced by choosing
8147 this alternative. */
8148 int *alternative_nregs;
8149 /* Array of vectors recording, for each operand and each alternative,
8150 which hard register to substitute, or -1 if the operand should be
8152 int *op_alt_regno[MAX_RECOG_OPERANDS];
8153 /* Array of alternatives, sorted in order of decreasing desirability. */
8154 int *alternative_order;
8155 rtx reg = gen_rtx_REG (VOIDmode, -1);
8157 extract_insn (insn);
8159 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8162 /* Figure out which alternative currently matches. */
8163 if (! constrain_operands (1))
8164 fatal_insn_not_found (insn);
8166 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8167 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8168 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8169 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8170 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8172 /* For each operand, find out which regs are equivalent. */
8173 for (i = 0; i < recog_data.n_operands; i++)
8176 struct elt_loc_list *l;
8178 CLEAR_HARD_REG_SET (equiv_regs[i]);
8180 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8181 right, so avoid the problem here. Likewise if we have a constant
8182 and the insn pattern doesn't tell us the mode we need. */
8183 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8184 || (CONSTANT_P (recog_data.operand[i])
8185 && recog_data.operand_mode[i] == VOIDmode))
8188 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8192 for (l = v->locs; l; l = l->next)
8193 if (GET_CODE (l->loc) == REG)
8194 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8197 for (i = 0; i < recog_data.n_operands; i++)
8199 enum machine_mode mode;
8203 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8204 for (j = 0; j < recog_data.n_alternatives; j++)
8205 op_alt_regno[i][j] = -1;
8207 p = constraints[i] = recog_data.constraints[i];
8208 mode = recog_data.operand_mode[i];
8210 /* Add the reject values for each alternative given by the constraints
8211 for this operand. */
8219 alternative_reject[j] += 3;
8221 alternative_reject[j] += 300;
8224 /* We won't change operands which are already registers. We
8225 also don't want to modify output operands. */
8226 regno = true_regnum (recog_data.operand[i]);
8228 || constraints[i][0] == '='
8229 || constraints[i][0] == '+')
8232 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8234 int class = (int) NO_REGS;
8236 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8239 REGNO (reg) = regno;
8240 PUT_MODE (reg, mode);
8242 /* We found a register equal to this operand. Now look for all
8243 alternatives that can accept this register and have not been
8244 assigned a register they can use yet. */
8253 case '=': case '+': case '?':
8254 case '#': case '&': case '!':
8256 case '0': case '1': case '2': case '3': case '4':
8257 case '5': case '6': case '7': case '8': case '9':
8258 case 'm': case '<': case '>': case 'V': case 'o':
8259 case 'E': case 'F': case 'G': case 'H':
8260 case 's': case 'i': case 'n':
8261 case 'I': case 'J': case 'K': case 'L':
8262 case 'M': case 'N': case 'O': case 'P':
8264 /* These don't say anything we care about. */
8268 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8273 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8276 case ',': case '\0':
8277 /* See if REGNO fits this alternative, and set it up as the
8278 replacement register if we don't have one for this
8279 alternative yet and the operand being replaced is not
8280 a cheap CONST_INT. */
8281 if (op_alt_regno[i][j] == -1
8282 && reg_fits_class_p (reg, class, 0, mode)
8283 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8284 || (rtx_cost (recog_data.operand[i], SET)
8285 > rtx_cost (reg, SET))))
8287 alternative_nregs[j]++;
8288 op_alt_regno[i][j] = regno;
8300 /* Record all alternatives which are better or equal to the currently
8301 matching one in the alternative_order array. */
8302 for (i = j = 0; i < recog_data.n_alternatives; i++)
8303 if (alternative_reject[i] <= alternative_reject[which_alternative])
8304 alternative_order[j++] = i;
8305 recog_data.n_alternatives = j;
8307 /* Sort it. Given a small number of alternatives, a dumb algorithm
8308 won't hurt too much. */
8309 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8312 int best_reject = alternative_reject[alternative_order[i]];
8313 int best_nregs = alternative_nregs[alternative_order[i]];
8316 for (j = i + 1; j < recog_data.n_alternatives; j++)
8318 int this_reject = alternative_reject[alternative_order[j]];
8319 int this_nregs = alternative_nregs[alternative_order[j]];
8321 if (this_reject < best_reject
8322 || (this_reject == best_reject && this_nregs < best_nregs))
8325 best_reject = this_reject;
8326 best_nregs = this_nregs;
8330 tmp = alternative_order[best];
8331 alternative_order[best] = alternative_order[i];
8332 alternative_order[i] = tmp;
8335 /* Substitute the operands as determined by op_alt_regno for the best
8337 j = alternative_order[0];
8339 for (i = 0; i < recog_data.n_operands; i++)
8341 enum machine_mode mode = recog_data.operand_mode[i];
8342 if (op_alt_regno[i][j] == -1)
8345 validate_change (insn, recog_data.operand_loc[i],
8346 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8349 for (i = recog_data.n_dups - 1; i >= 0; i--)
8351 int op = recog_data.dup_num[i];
8352 enum machine_mode mode = recog_data.operand_mode[op];
8354 if (op_alt_regno[op][j] == -1)
8357 validate_change (insn, recog_data.dup_loc[i],
8358 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8361 return apply_change_group ();
8364 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8366 This code might also be useful when reload gave up on reg+reg addresssing
8367 because of clashes between the return register and INDEX_REG_CLASS. */
8369 /* The maximum number of uses of a register we can keep track of to
8370 replace them with reg+reg addressing. */
8371 #define RELOAD_COMBINE_MAX_USES 6
8373 /* INSN is the insn where a register has ben used, and USEP points to the
8374 location of the register within the rtl. */
8375 struct reg_use { rtx insn, *usep; };
8377 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8378 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8379 indicates where it becomes live again.
8380 Otherwise, USE_INDEX is the index of the last encountered use of the
8381 register (which is first among these we have seen since we scan backwards),
8382 OFFSET contains the constant offset that is added to the register in
8383 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8384 last, of these uses.
8385 STORE_RUID is always meaningful if we only want to use a value in a
8386 register in a different place: it denotes the next insn in the insn
8387 stream (i.e. the last ecountered) that sets or clobbers the register. */
8390 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8395 } reg_state[FIRST_PSEUDO_REGISTER];
8397 /* Reverse linear uid. This is increased in reload_combine while scanning
8398 the instructions from last to first. It is used to set last_label_ruid
8399 and the store_ruid / use_ruid fields in reg_state. */
8400 static int reload_combine_ruid;
8402 #define LABEL_LIVE(LABEL) \
8403 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8409 int first_index_reg = -1, last_index_reg;
8412 int last_label_ruid;
8413 int min_labelno, n_labels;
8414 HARD_REG_SET ever_live_at_start, *label_live;
8416 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8417 reload has already used it where appropriate, so there is no use in
8418 trying to generate it now. */
8419 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8422 /* To avoid wasting too much time later searching for an index register,
8423 determine the minimum and maximum index register numbers. */
8424 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8425 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8427 if (first_index_reg == -1)
8428 first_index_reg = r;
8433 /* If no index register is available, we can quit now. */
8434 if (first_index_reg == -1)
8437 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8438 information is a bit fuzzy immediately after reload, but it's
8439 still good enough to determine which registers are live at a jump
8441 min_labelno = get_first_label_num ();
8442 n_labels = max_label_num () - min_labelno;
8443 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8444 CLEAR_HARD_REG_SET (ever_live_at_start);
8446 for (i = n_basic_blocks - 1; i >= 0; i--)
8448 insn = BLOCK_HEAD (i);
8449 if (GET_CODE (insn) == CODE_LABEL)
8453 REG_SET_TO_HARD_REG_SET (live,
8454 BASIC_BLOCK (i)->global_live_at_start);
8455 compute_use_by_pseudos (&live,
8456 BASIC_BLOCK (i)->global_live_at_start);
8457 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8458 IOR_HARD_REG_SET (ever_live_at_start, live);
8462 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8463 last_label_ruid = reload_combine_ruid = 0;
8464 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8466 reg_state[r].store_ruid = reload_combine_ruid;
8468 reg_state[r].use_index = -1;
8470 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8473 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8477 /* We cannot do our optimization across labels. Invalidating all the use
8478 information we have would be costly, so we just note where the label
8479 is and then later disable any optimization that would cross it. */
8480 if (GET_CODE (insn) == CODE_LABEL)
8481 last_label_ruid = reload_combine_ruid;
8482 else if (GET_CODE (insn) == BARRIER)
8483 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8484 if (! fixed_regs[r])
8485 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8487 if (! INSN_P (insn))
8490 reload_combine_ruid++;
8492 /* Look for (set (REGX) (CONST_INT))
8493 (set (REGX) (PLUS (REGX) (REGY)))
8495 ... (MEM (REGX)) ...
8497 (set (REGZ) (CONST_INT))
8499 ... (MEM (PLUS (REGZ) (REGY)))... .
8501 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8502 and that we know all uses of REGX before it dies. */
8503 set = single_set (insn);
8505 && GET_CODE (SET_DEST (set)) == REG
8506 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8507 GET_MODE (SET_DEST (set)))
8509 && GET_CODE (SET_SRC (set)) == PLUS
8510 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8511 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8512 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8514 rtx reg = SET_DEST (set);
8515 rtx plus = SET_SRC (set);
8516 rtx base = XEXP (plus, 1);
8517 rtx prev = prev_nonnote_insn (insn);
8518 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8519 unsigned int regno = REGNO (reg);
8520 rtx const_reg = NULL_RTX;
8521 rtx reg_sum = NULL_RTX;
8523 /* Now, we need an index register.
8524 We'll set index_reg to this index register, const_reg to the
8525 register that is to be loaded with the constant
8526 (denoted as REGZ in the substitution illustration above),
8527 and reg_sum to the register-register that we want to use to
8528 substitute uses of REG (typically in MEMs) with.
8529 First check REG and BASE for being index registers;
8530 we can use them even if they are not dead. */
8531 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8532 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8540 /* Otherwise, look for a free index register. Since we have
8541 checked above that neiter REG nor BASE are index registers,
8542 if we find anything at all, it will be different from these
8544 for (i = first_index_reg; i <= last_index_reg; i++)
8546 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8548 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8549 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8550 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8552 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8554 const_reg = index_reg;
8555 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8561 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8562 (REGY), i.e. BASE, is not clobbered before the last use we'll
8565 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8566 && rtx_equal_p (SET_DEST (prev_set), reg)
8567 && reg_state[regno].use_index >= 0
8568 && (reg_state[REGNO (base)].store_ruid
8569 <= reg_state[regno].use_ruid)
8574 /* Change destination register and, if necessary, the
8575 constant value in PREV, the constant loading instruction. */
8576 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8577 if (reg_state[regno].offset != const0_rtx)
8578 validate_change (prev,
8579 &SET_SRC (prev_set),
8580 GEN_INT (INTVAL (SET_SRC (prev_set))
8581 + INTVAL (reg_state[regno].offset)),
8584 /* Now for every use of REG that we have recorded, replace REG
8586 for (i = reg_state[regno].use_index;
8587 i < RELOAD_COMBINE_MAX_USES; i++)
8588 validate_change (reg_state[regno].reg_use[i].insn,
8589 reg_state[regno].reg_use[i].usep,
8592 if (apply_change_group ())
8596 /* Delete the reg-reg addition. */
8597 PUT_CODE (insn, NOTE);
8598 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8599 NOTE_SOURCE_FILE (insn) = 0;
8601 if (reg_state[regno].offset != const0_rtx)
8602 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8604 for (np = ®_NOTES (prev); *np;)
8606 if (REG_NOTE_KIND (*np) == REG_EQUAL
8607 || REG_NOTE_KIND (*np) == REG_EQUIV)
8608 *np = XEXP (*np, 1);
8610 np = &XEXP (*np, 1);
8613 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8614 reg_state[REGNO (const_reg)].store_ruid
8615 = reload_combine_ruid;
8621 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8623 if (GET_CODE (insn) == CALL_INSN)
8627 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8628 if (call_used_regs[r])
8630 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8631 reg_state[r].store_ruid = reload_combine_ruid;
8634 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8635 link = XEXP (link, 1))
8636 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8638 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8640 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8642 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8643 reg_state[regno].store_ruid = reload_combine_ruid;
8646 reg_state[regno].use_index = -1;
8650 else if (GET_CODE (insn) == JUMP_INSN
8651 && GET_CODE (PATTERN (insn)) != RETURN)
8653 /* Non-spill registers might be used at the call destination in
8654 some unknown fashion, so we have to mark the unknown use. */
8657 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8658 && JUMP_LABEL (insn))
8659 live = &LABEL_LIVE (JUMP_LABEL (insn));
8661 live = &ever_live_at_start;
8663 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8664 if (TEST_HARD_REG_BIT (*live, i))
8665 reg_state[i].use_index = -1;
8668 reload_combine_note_use (&PATTERN (insn), insn);
8669 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8671 if (REG_NOTE_KIND (note) == REG_INC
8672 && GET_CODE (XEXP (note, 0)) == REG)
8674 int regno = REGNO (XEXP (note, 0));
8676 reg_state[regno].store_ruid = reload_combine_ruid;
8677 reg_state[regno].use_index = -1;
8685 /* Check if DST is a register or a subreg of a register; if it is,
8686 update reg_state[regno].store_ruid and reg_state[regno].use_index
8687 accordingly. Called via note_stores from reload_combine. */
8690 reload_combine_note_store (dst, set, data)
8692 void *data ATTRIBUTE_UNUSED;
8696 enum machine_mode mode = GET_MODE (dst);
8698 if (GET_CODE (dst) == SUBREG)
8700 regno = SUBREG_WORD (dst);
8701 dst = SUBREG_REG (dst);
8703 if (GET_CODE (dst) != REG)
8705 regno += REGNO (dst);
8707 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8708 careful with registers / register parts that are not full words.
8710 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8711 if (GET_CODE (set) != SET
8712 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8713 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8714 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8716 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8718 reg_state[i].use_index = -1;
8719 reg_state[i].store_ruid = reload_combine_ruid;
8724 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8726 reg_state[i].store_ruid = reload_combine_ruid;
8727 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8732 /* XP points to a piece of rtl that has to be checked for any uses of
8734 *XP is the pattern of INSN, or a part of it.
8735 Called from reload_combine, and recursively by itself. */
8737 reload_combine_note_use (xp, insn)
8741 enum rtx_code code = x->code;
8744 rtx offset = const0_rtx; /* For the REG case below. */
8749 if (GET_CODE (SET_DEST (x)) == REG)
8751 reload_combine_note_use (&SET_SRC (x), insn);
8757 /* If this is the USE of a return value, we can't change it. */
8758 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8760 /* Mark the return register as used in an unknown fashion. */
8761 rtx reg = XEXP (x, 0);
8762 int regno = REGNO (reg);
8763 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8765 while (--nregs >= 0)
8766 reg_state[regno + nregs].use_index = -1;
8772 if (GET_CODE (SET_DEST (x)) == REG)
8777 /* We are interested in (plus (reg) (const_int)) . */
8778 if (GET_CODE (XEXP (x, 0)) != REG
8779 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8781 offset = XEXP (x, 1);
8786 int regno = REGNO (x);
8790 /* Some spurious USEs of pseudo registers might remain.
8791 Just ignore them. */
8792 if (regno >= FIRST_PSEUDO_REGISTER)
8795 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8797 /* We can't substitute into multi-hard-reg uses. */
8800 while (--nregs >= 0)
8801 reg_state[regno + nregs].use_index = -1;
8805 /* If this register is already used in some unknown fashion, we
8807 If we decrement the index from zero to -1, we can't store more
8808 uses, so this register becomes used in an unknown fashion. */
8809 use_index = --reg_state[regno].use_index;
8813 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8815 /* We have found another use for a register that is already
8816 used later. Check if the offsets match; if not, mark the
8817 register as used in an unknown fashion. */
8818 if (! rtx_equal_p (offset, reg_state[regno].offset))
8820 reg_state[regno].use_index = -1;
8826 /* This is the first use of this register we have seen since we
8827 marked it as dead. */
8828 reg_state[regno].offset = offset;
8829 reg_state[regno].use_ruid = reload_combine_ruid;
8831 reg_state[regno].reg_use[use_index].insn = insn;
8832 reg_state[regno].reg_use[use_index].usep = xp;
8840 /* Recursively process the components of X. */
8841 fmt = GET_RTX_FORMAT (code);
8842 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8845 reload_combine_note_use (&XEXP (x, i), insn);
8846 else if (fmt[i] == 'E')
8848 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8849 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8854 /* See if we can reduce the cost of a constant by replacing a move with
8856 /* We cannot do our optimization across labels. Invalidating all the
8857 information about register contents we have would be costly, so we
8858 use last_label_luid (local variable of reload_cse_move2add) to note
8859 where the label is and then later disable any optimization that would
8861 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8862 reg_set_luid[n] is larger than last_label_luid[n] . */
8863 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8865 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8866 reg_mode[n] to be valid.
8867 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8868 has been set to reg_offset[n] in mode reg_mode[n] .
8869 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8870 register n has been set to the sum of reg_offset[n] and register
8871 reg_base_reg[n], calculated in mode reg_mode[n] . */
8872 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8873 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8874 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8876 /* move2add_luid is linearily increased while scanning the instructions
8877 from first to last. It is used to set reg_set_luid in
8878 reload_cse_move2add and move2add_note_store. */
8879 static int move2add_luid;
8881 /* Generate a CONST_INT and force it in the range of MODE. */
8884 gen_mode_int (mode, value)
8885 enum machine_mode mode;
8886 HOST_WIDE_INT value;
8888 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8889 int width = GET_MODE_BITSIZE (mode);
8891 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8893 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8894 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8895 cval |= (HOST_WIDE_INT) -1 << width;
8897 return GEN_INT (cval);
8901 reload_cse_move2add (first)
8906 int last_label_luid;
8908 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8909 reg_set_luid[i] = 0;
8911 last_label_luid = 0;
8913 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8917 if (GET_CODE (insn) == CODE_LABEL)
8918 last_label_luid = move2add_luid;
8919 if (! INSN_P (insn))
8921 pat = PATTERN (insn);
8922 /* For simplicity, we only perform this optimization on
8923 straightforward SETs. */
8924 if (GET_CODE (pat) == SET
8925 && GET_CODE (SET_DEST (pat)) == REG)
8927 rtx reg = SET_DEST (pat);
8928 int regno = REGNO (reg);
8929 rtx src = SET_SRC (pat);
8931 /* Check if we have valid information on the contents of this
8932 register in the mode of REG. */
8933 /* ??? We don't know how zero / sign extension is handled, hence
8934 we can't go from a narrower to a wider mode. */
8935 if (reg_set_luid[regno] > last_label_luid
8936 && ((GET_MODE_SIZE (GET_MODE (reg))
8937 == GET_MODE_SIZE (reg_mode[regno]))
8938 || ((GET_MODE_SIZE (GET_MODE (reg))
8939 <= GET_MODE_SIZE (reg_mode[regno]))
8940 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8941 GET_MODE_BITSIZE (reg_mode[regno]))))
8942 && GET_CODE (reg_offset[regno]) == CONST_INT)
8944 /* Try to transform (set (REGX) (CONST_INT A))
8946 (set (REGX) (CONST_INT B))
8948 (set (REGX) (CONST_INT A))
8950 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8952 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8956 = gen_mode_int (GET_MODE (reg),
8957 INTVAL (src) - INTVAL (reg_offset[regno]));
8958 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8959 use (set (reg) (reg)) instead.
8960 We don't delete this insn, nor do we convert it into a
8961 note, to avoid losing register notes or the return
8962 value flag. jump2 already knowns how to get rid of
8964 if (new_src == const0_rtx)
8965 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8966 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8967 && have_add2_insn (GET_MODE (reg)))
8968 success = validate_change (insn, &PATTERN (insn),
8969 gen_add2_insn (reg, new_src), 0);
8970 reg_set_luid[regno] = move2add_luid;
8971 reg_mode[regno] = GET_MODE (reg);
8972 reg_offset[regno] = src;
8976 /* Try to transform (set (REGX) (REGY))
8977 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8980 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8983 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8985 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8986 else if (GET_CODE (src) == REG
8987 && reg_base_reg[regno] == (int) REGNO (src)
8988 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8990 rtx next = next_nonnote_insn (insn);
8993 set = single_set (next);
8996 && SET_DEST (set) == reg
8997 && GET_CODE (SET_SRC (set)) == PLUS
8998 && XEXP (SET_SRC (set), 0) == reg
8999 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9001 rtx src3 = XEXP (SET_SRC (set), 1);
9003 = gen_mode_int (GET_MODE (reg),
9005 - INTVAL (reg_offset[regno]));
9008 if (new_src == const0_rtx)
9009 /* See above why we create (set (reg) (reg)) here. */
9011 = validate_change (next, &SET_SRC (set), reg, 0);
9012 else if ((rtx_cost (new_src, PLUS)
9013 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9014 && have_add2_insn (GET_MODE (reg)))
9016 = validate_change (next, &PATTERN (next),
9017 gen_add2_insn (reg, new_src), 0);
9020 /* INSN might be the first insn in a basic block
9021 if the preceding insn is a conditional jump
9022 or a possible-throwing call. */
9023 PUT_CODE (insn, NOTE);
9024 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9025 NOTE_SOURCE_FILE (insn) = 0;
9028 reg_set_luid[regno] = move2add_luid;
9029 reg_mode[regno] = GET_MODE (reg);
9030 reg_offset[regno] = src3;
9037 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9039 if (REG_NOTE_KIND (note) == REG_INC
9040 && GET_CODE (XEXP (note, 0)) == REG)
9042 /* Indicate that this register has been recently written to,
9043 but the exact contents are not available. */
9044 int regno = REGNO (XEXP (note, 0));
9045 if (regno < FIRST_PSEUDO_REGISTER)
9047 reg_set_luid[regno] = move2add_luid;
9048 reg_offset[regno] = note;
9052 note_stores (PATTERN (insn), move2add_note_store, NULL);
9053 /* If this is a CALL_INSN, all call used registers are stored with
9055 if (GET_CODE (insn) == CALL_INSN)
9057 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9059 if (call_used_regs[i])
9061 reg_set_luid[i] = move2add_luid;
9062 reg_offset[i] = insn; /* Invalidate contents. */
9069 /* SET is a SET or CLOBBER that sets DST.
9070 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9071 Called from reload_cse_move2add via note_stores. */
9074 move2add_note_store (dst, set, data)
9076 void *data ATTRIBUTE_UNUSED;
9078 unsigned int regno = 0;
9080 enum machine_mode mode = GET_MODE (dst);
9082 if (GET_CODE (dst) == SUBREG)
9084 regno = SUBREG_WORD (dst);
9085 dst = SUBREG_REG (dst);
9088 /* Some targets do argument pushes without adding REG_INC notes. */
9090 if (GET_CODE (dst) == MEM)
9092 dst = XEXP (dst, 0);
9093 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9094 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9096 regno = REGNO (XEXP (dst, 0));
9097 reg_set_luid[regno] = move2add_luid;
9098 reg_offset[regno] = dst;
9102 if (GET_CODE (dst) != REG)
9105 regno += REGNO (dst);
9107 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9108 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9109 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9110 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9112 rtx src = SET_SRC (set);
9114 reg_mode[regno] = mode;
9115 switch (GET_CODE (src))
9119 rtx src0 = XEXP (src, 0);
9121 if (GET_CODE (src0) == REG)
9123 if (REGNO (src0) != regno
9124 || reg_offset[regno] != const0_rtx)
9126 reg_base_reg[regno] = REGNO (src0);
9127 reg_set_luid[regno] = move2add_luid;
9130 reg_offset[regno] = XEXP (src, 1);
9134 reg_set_luid[regno] = move2add_luid;
9135 reg_offset[regno] = set; /* Invalidate contents. */
9140 reg_base_reg[regno] = REGNO (SET_SRC (set));
9141 reg_offset[regno] = const0_rtx;
9142 reg_set_luid[regno] = move2add_luid;
9146 reg_base_reg[regno] = -1;
9147 reg_offset[regno] = SET_SRC (set);
9148 reg_set_luid[regno] = move2add_luid;
9154 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9156 for (i = regno; i < endregno; i++)
9158 /* Indicate that this register has been recently written to,
9159 but the exact contents are not available. */
9160 reg_set_luid[i] = move2add_luid;
9161 reg_offset[i] = dst;
9168 add_auto_inc_notes (insn, x)
9172 enum rtx_code code = GET_CODE (x);
9176 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9179 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9183 /* Scan all the operand sub-expressions. */
9184 fmt = GET_RTX_FORMAT (code);
9185 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9188 add_auto_inc_notes (insn, XEXP (x, i));
9189 else if (fmt[i] == 'E')
9190 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9191 add_auto_inc_notes (insn, XVECEXP (x, i, j));
OSDN Git Service
