1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
415 rtx, rtx, int, int));
416 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
418 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
420 static void failed_reload PARAMS ((rtx, int));
421 static int set_reload_reg PARAMS ((int, int));
422 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
423 static void choose_reload_regs PARAMS ((struct insn_chain *));
424 static void merge_assigned_reloads PARAMS ((rtx));
425 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
426 struct reload *, rtx, int));
427 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
428 struct reload *, int));
429 static void do_input_reload PARAMS ((struct insn_chain *,
430 struct reload *, int));
431 static void do_output_reload PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void emit_reload_insns PARAMS ((struct insn_chain *));
434 static void delete_output_reload PARAMS ((rtx, int, int));
435 static void delete_address_reloads PARAMS ((rtx, rtx));
436 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
437 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
438 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
439 static void reload_cse_regs_1 PARAMS ((rtx));
440 static int reload_cse_noop_set_p PARAMS ((rtx));
441 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
442 static int reload_cse_simplify_operands PARAMS ((rtx));
443 static void reload_combine PARAMS ((void));
444 static void reload_combine_note_use PARAMS ((rtx *, rtx));
445 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
446 static void reload_cse_move2add PARAMS ((rtx));
447 static void move2add_note_store PARAMS ((rtx, rtx, void *));
449 static void add_auto_inc_notes PARAMS ((rtx, rtx));
451 static rtx gen_mode_int PARAMS ((enum machine_mode,
453 static void failed_reload PARAMS ((rtx, int));
454 static int set_reload_reg PARAMS ((int, int));
455 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
456 static void reload_cse_simplify PARAMS ((rtx));
457 extern void dump_needs PARAMS ((struct insn_chain *));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
511 INIT_REG_SET (&spilled_pseudos);
512 INIT_REG_SET (&pseudos_counted);
515 /* List of insn chains that are currently unused. */
516 static struct insn_chain *unused_insn_chains = 0;
518 /* Allocate an empty insn_chain structure. */
522 struct insn_chain *c;
524 if (unused_insn_chains == 0)
526 c = (struct insn_chain *)
527 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
528 INIT_REG_SET (&c->live_throughout);
529 INIT_REG_SET (&c->dead_or_set);
533 c = unused_insn_chains;
534 unused_insn_chains = c->next;
536 c->is_caller_save_insn = 0;
537 c->need_operand_change = 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (to, from)
553 EXECUTE_IF_SET_IN_REG_SET
554 (from, FIRST_PSEUDO_REGISTER, regno,
556 int r = reg_renumber[regno];
561 /* reload_combine uses the information from
562 BASIC_BLOCK->global_live_at_start, which might still
563 contain registers that have not actually been allocated
564 since they have an equivalence. */
565 if (! reload_completed)
570 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
572 SET_HARD_REG_BIT (*to, r + nregs);
577 /* Global variables used by reload and its subroutines. */
579 /* Set during calculate_needs if an insn needs register elimination. */
580 static int something_needs_elimination;
581 /* Set during calculate_needs if an insn needs an operand changed. */
582 int something_needs_operands_changed;
584 /* Nonzero means we couldn't get enough spill regs. */
587 /* Main entry point for the reload pass.
589 FIRST is the first insn of the function being compiled.
591 GLOBAL nonzero means we were called from global_alloc
592 and should attempt to reallocate any pseudoregs that we
593 displace from hard regs we will use for reloads.
594 If GLOBAL is zero, we do not have enough information to do that,
595 so any pseudo reg that is spilled must go to the stack.
597 Return value is nonzero if reload failed
598 and we must not do any more for this function. */
601 reload (first, global)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
635 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
652 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
653 regs_ever_live[i] = 1;
655 /* Find all the pseudo registers that didn't get hard regs
656 but do have known equivalent constants or memory slots.
657 These include parameters (known equivalent to parameter slots)
658 and cse'd or loop-moved constant memory addresses.
660 Record constant equivalents in reg_equiv_constant
661 so they will be substituted by find_reloads.
662 Record memory equivalents in reg_mem_equiv so they can
663 be substituted eventually by altering the REG-rtx's. */
665 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
666 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
667 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
671 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
672 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
673 pseudo_forbidden_regs
674 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
676 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
678 CLEAR_HARD_REG_SET (bad_spill_regs_global);
680 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
681 Also find all paradoxical subregs and find largest such for each pseudo.
682 On machines with small register classes, record hard registers that
683 are used for user variables. These can never be used for spills.
684 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
685 caller-saved registers must be marked live. */
687 num_eliminable_invariants = 0;
688 for (insn = first; insn; insn = NEXT_INSN (insn))
690 rtx set = single_set (insn);
692 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
693 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i])
696 regs_ever_live[i] = 1;
698 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
700 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
702 #ifdef LEGITIMATE_PIC_OPERAND_P
703 && (! function_invariant_p (XEXP (note, 0))
705 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
709 rtx x = XEXP (note, 0);
710 i = REGNO (SET_DEST (set));
711 if (i > LAST_VIRTUAL_REGISTER)
713 if (GET_CODE (x) == MEM)
715 /* If the operand is a PLUS, the MEM may be shared,
716 so make sure we have an unshared copy here. */
717 if (GET_CODE (XEXP (x, 0)) == PLUS)
720 reg_equiv_memory_loc[i] = x;
722 else if (function_invariant_p (x))
724 if (GET_CODE (x) == PLUS)
726 /* This is PLUS of frame pointer and a constant,
727 and might be shared. Unshare it. */
728 reg_equiv_constant[i] = copy_rtx (x);
729 num_eliminable_invariants++;
731 else if (x == frame_pointer_rtx
732 || x == arg_pointer_rtx)
734 reg_equiv_constant[i] = x;
735 num_eliminable_invariants++;
737 else if (LEGITIMATE_CONSTANT_P (x))
738 reg_equiv_constant[i] = x;
740 reg_equiv_memory_loc[i]
741 = force_const_mem (GET_MODE (SET_DEST (set)), x);
746 /* If this register is being made equivalent to a MEM
747 and the MEM is not SET_SRC, the equivalencing insn
748 is one with the MEM as a SET_DEST and it occurs later.
749 So don't mark this insn now. */
750 if (GET_CODE (x) != MEM
751 || rtx_equal_p (SET_SRC (set), x))
753 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
758 /* If this insn is setting a MEM from a register equivalent to it,
759 this is the equivalencing insn. */
760 else if (set && GET_CODE (SET_DEST (set)) == MEM
761 && GET_CODE (SET_SRC (set)) == REG
762 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
763 && rtx_equal_p (SET_DEST (set),
764 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
765 reg_equiv_init[REGNO (SET_SRC (set))]
766 = gen_rtx_INSN_LIST (VOIDmode, insn,
767 reg_equiv_init[REGNO (SET_SRC (set))]);
770 scan_paradoxical_subregs (PATTERN (insn));
775 num_labels = max_label_num () - get_first_label_num ();
777 /* Allocate the tables used to store offset information at labels. */
778 /* We used to use alloca here, but the size of what it would try to
779 allocate would occasionally cause it to exceed the stack limit and
780 cause a core dump. */
781 real_known_ptr = xmalloc (num_labels);
783 = (int (*)[NUM_ELIMINABLE_REGS])
784 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
786 offsets_known_at = real_known_ptr - get_first_label_num ();
788 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
790 /* Alter each pseudo-reg rtx to contain its hard reg number.
791 Assign stack slots to the pseudos that lack hard regs or equivalents.
792 Do not touch virtual registers. */
794 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
804 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
805 || GET_CODE (insn) == CALL_INSN)
806 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
808 maybe_fix_stack_asms ();
810 insns_need_reload = 0;
811 something_needs_elimination = 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs);
818 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
819 if (! ep->can_eliminate)
820 spill_hard_reg (ep->from, 1);
822 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
823 if (frame_pointer_needed)
824 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
826 finish_spills (global);
828 /* From now on, we may need to generate moves differently. We may also
829 allow modifications of insns which cause them to not be recognized.
830 Any such modifications will be cleaned up during reload itself. */
831 reload_in_progress = 1;
833 /* This loop scans the entire function each go-round
834 and repeats until one repetition spills no additional hard regs. */
837 int something_changed;
840 HOST_WIDE_INT starting_frame_size;
842 /* Round size of stack frame to stack_alignment_needed. This must be done
843 here because the stack size may be a part of the offset computation
844 for register elimination, and there might have been new stack slots
845 created in the last iteration of this loop. */
846 if (cfun->stack_alignment_needed)
847 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
849 starting_frame_size = get_frame_size ();
851 set_initial_elim_offsets ();
852 set_initial_label_offsets ();
854 /* For each pseudo register that has an equivalent location defined,
855 try to eliminate any eliminable registers (such as the frame pointer)
856 assuming initial offsets for the replacement register, which
859 If the resulting location is directly addressable, substitute
860 the MEM we just got directly for the old REG.
862 If it is not addressable but is a constant or the sum of a hard reg
863 and constant, it is probably not addressable because the constant is
864 out of range, in that case record the address; we will generate
865 hairy code to compute the address in a register each time it is
866 needed. Similarly if it is a hard register, but one that is not
867 valid as an address register.
869 If the location is not addressable, but does not have one of the
870 above forms, assign a stack slot. We have to do this to avoid the
871 potential of producing lots of reloads if, e.g., a location involves
872 a pseudo that didn't get a hard register and has an equivalent memory
873 location that also involves a pseudo that didn't get a hard register.
875 Perhaps at some point we will improve reload_when_needed handling
876 so this problem goes away. But that's very hairy. */
878 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
879 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
881 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
883 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
885 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
886 else if (CONSTANT_P (XEXP (x, 0))
887 || (GET_CODE (XEXP (x, 0)) == REG
888 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
889 || (GET_CODE (XEXP (x, 0)) == PLUS
890 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
891 && (REGNO (XEXP (XEXP (x, 0), 0))
892 < FIRST_PSEUDO_REGISTER)
893 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
894 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
897 /* Make a new stack slot. Then indicate that something
898 changed so we go back and recompute offsets for
899 eliminable registers because the allocation of memory
900 below might change some offset. reg_equiv_{mem,address}
901 will be set up for this pseudo on the next pass around
903 reg_equiv_memory_loc[i] = 0;
904 reg_equiv_init[i] = 0;
909 if (caller_save_needed)
912 /* If we allocated another stack slot, redo elimination bookkeeping. */
913 if (starting_frame_size != get_frame_size ())
916 if (caller_save_needed)
918 save_call_clobbered_regs ();
919 /* That might have allocated new insn_chain structures. */
920 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
923 calculate_needs_all_insns (global);
925 CLEAR_REG_SET (&spilled_pseudos);
928 something_changed = 0;
930 /* If we allocated any new memory locations, make another pass
931 since it might have changed elimination offsets. */
932 if (starting_frame_size != get_frame_size ())
933 something_changed = 1;
936 HARD_REG_SET to_spill;
937 CLEAR_HARD_REG_SET (to_spill);
938 update_eliminables (&to_spill);
939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
940 if (TEST_HARD_REG_BIT (to_spill, i))
942 spill_hard_reg (i, 1);
945 /* Regardless of the state of spills, if we previously had
946 a register that we thought we could eliminate, but no can
947 not eliminate, we must run another pass.
949 Consider pseudos which have an entry in reg_equiv_* which
950 reference an eliminable register. We must make another pass
951 to update reg_equiv_* so that we do not substitute in the
952 old value from when we thought the elimination could be
954 something_changed = 1;
958 select_reload_regs ();
962 if (insns_need_reload != 0 || did_spill)
963 something_changed |= finish_spills (global);
965 if (! something_changed)
968 if (caller_save_needed)
969 delete_caller_save_insns ();
971 obstack_free (&reload_obstack, reload_firstobj);
974 /* If global-alloc was run, notify it of any register eliminations we have
977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
978 if (ep->can_eliminate)
979 mark_elimination (ep->from, ep->to);
981 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
982 If that insn didn't set the register (i.e., it copied the register to
983 memory), just delete that insn instead of the equivalencing insn plus
984 anything now dead. If we call delete_dead_insn on that insn, we may
985 delete the insn that actually sets the register if the register dies
986 there and that is incorrect. */
988 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
990 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
993 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
995 rtx equiv_insn = XEXP (list, 0);
996 if (GET_CODE (equiv_insn) == NOTE)
998 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
999 delete_dead_insn (equiv_insn);
1002 PUT_CODE (equiv_insn, NOTE);
1003 NOTE_SOURCE_FILE (equiv_insn) = 0;
1004 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1010 /* Use the reload registers where necessary
1011 by generating move instructions to move the must-be-register
1012 values into or out of the reload registers. */
1014 if (insns_need_reload != 0 || something_needs_elimination
1015 || something_needs_operands_changed)
1017 int old_frame_size = get_frame_size ();
1019 reload_as_needed (global);
1021 if (old_frame_size != get_frame_size ())
1025 verify_initial_elim_offsets ();
1028 /* If we were able to eliminate the frame pointer, show that it is no
1029 longer live at the start of any basic block. If it ls live by
1030 virtue of being in a pseudo, that pseudo will be marked live
1031 and hence the frame pointer will be known to be live via that
1034 if (! frame_pointer_needed)
1035 for (i = 0; i < n_basic_blocks; i++)
1036 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1037 HARD_FRAME_POINTER_REGNUM);
1039 /* Come here (with failure set nonzero) if we can't get enough spill regs
1040 and we decide not to abort about it. */
1043 CLEAR_REG_SET (&spilled_pseudos);
1044 reload_in_progress = 0;
1046 /* Now eliminate all pseudo regs by modifying them into
1047 their equivalent memory references.
1048 The REG-rtx's for the pseudos are modified in place,
1049 so all insns that used to refer to them now refer to memory.
1051 For a reg that has a reg_equiv_address, all those insns
1052 were changed by reloading so that no insns refer to it any longer;
1053 but the DECL_RTL of a variable decl may refer to it,
1054 and if so this causes the debugging info to mention the variable. */
1056 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1061 int is_readonly = 0;
1063 if (reg_equiv_memory_loc[i])
1065 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1066 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1067 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1070 if (reg_equiv_mem[i])
1071 addr = XEXP (reg_equiv_mem[i], 0);
1073 if (reg_equiv_address[i])
1074 addr = reg_equiv_address[i];
1078 if (reg_renumber[i] < 0)
1080 rtx reg = regno_reg_rtx[i];
1081 PUT_CODE (reg, MEM);
1082 XEXP (reg, 0) = addr;
1083 REG_USERVAR_P (reg) = 0;
1084 RTX_UNCHANGING_P (reg) = is_readonly;
1085 MEM_IN_STRUCT_P (reg) = in_struct;
1086 MEM_SCALAR_P (reg) = is_scalar;
1087 /* We have no alias information about this newly created
1089 MEM_ALIAS_SET (reg) = 0;
1091 else if (reg_equiv_mem[i])
1092 XEXP (reg_equiv_mem[i], 0) = addr;
1096 /* We must set reload_completed now since the cleanup_subreg_operands call
1097 below will re-recognize each insn and reload may have generated insns
1098 which are only valid during and after reload. */
1099 reload_completed = 1;
1101 /* Make a pass over all the insns and delete all USEs which we inserted
1102 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1103 notes. Delete all CLOBBER insns that don't refer to the return value
1104 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1105 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1106 and regenerate REG_INC notes that may have been moved around. */
1108 for (insn = first; insn; insn = NEXT_INSN (insn))
1113 if ((GET_CODE (PATTERN (insn)) == USE
1114 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1115 || (GET_CODE (PATTERN (insn)) == CLOBBER
1116 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1117 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1119 PUT_CODE (insn, NOTE);
1120 NOTE_SOURCE_FILE (insn) = 0;
1121 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1125 pnote = ®_NOTES (insn);
1128 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1129 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1130 || REG_NOTE_KIND (*pnote) == REG_INC
1131 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1132 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1133 *pnote = XEXP (*pnote, 1);
1135 pnote = &XEXP (*pnote, 1);
1139 add_auto_inc_notes (insn, PATTERN (insn));
1142 /* And simplify (subreg (reg)) if it appears as an operand. */
1143 cleanup_subreg_operands (insn);
1146 /* If we are doing stack checking, give a warning if this function's
1147 frame size is larger than we expect. */
1148 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1150 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1151 static int verbose_warned = 0;
1153 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1154 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1155 size += UNITS_PER_WORD;
1157 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1159 warning ("frame size too large for reliable stack checking");
1160 if (! verbose_warned)
1162 warning ("try reducing the number of local variables");
1168 /* Indicate that we no longer have known memory locations or constants. */
1169 if (reg_equiv_constant)
1170 free (reg_equiv_constant);
1171 reg_equiv_constant = 0;
1172 if (reg_equiv_memory_loc)
1173 free (reg_equiv_memory_loc);
1174 reg_equiv_memory_loc = 0;
1177 free (real_known_ptr);
1181 free (reg_equiv_mem);
1182 free (reg_equiv_init);
1183 free (reg_equiv_address);
1184 free (reg_max_ref_width);
1185 free (reg_old_renumber);
1186 free (pseudo_previous_regs);
1187 free (pseudo_forbidden_regs);
1189 CLEAR_HARD_REG_SET (used_spill_regs);
1190 for (i = 0; i < n_spills; i++)
1191 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1193 /* Free all the insn_chain structures at once. */
1194 obstack_free (&reload_obstack, reload_startobj);
1195 unused_insn_chains = 0;
1200 /* Yet another special case. Unfortunately, reg-stack forces people to
1201 write incorrect clobbers in asm statements. These clobbers must not
1202 cause the register to appear in bad_spill_regs, otherwise we'll call
1203 fatal_insn later. We clear the corresponding regnos in the live
1204 register sets to avoid this.
1205 The whole thing is rather sick, I'm afraid. */
1208 maybe_fix_stack_asms ()
1211 const char *constraints[MAX_RECOG_OPERANDS];
1212 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1213 struct insn_chain *chain;
1215 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1218 HARD_REG_SET clobbered, allowed;
1221 if (! INSN_P (chain->insn)
1222 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1224 pat = PATTERN (chain->insn);
1225 if (GET_CODE (pat) != PARALLEL)
1228 CLEAR_HARD_REG_SET (clobbered);
1229 CLEAR_HARD_REG_SET (allowed);
1231 /* First, make a mask of all stack regs that are clobbered. */
1232 for (i = 0; i < XVECLEN (pat, 0); i++)
1234 rtx t = XVECEXP (pat, 0, i);
1235 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1236 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1239 /* Get the operand values and constraints out of the insn. */
1240 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1241 constraints, operand_mode);
1243 /* For every operand, see what registers are allowed. */
1244 for (i = 0; i < noperands; i++)
1246 const char *p = constraints[i];
1247 /* For every alternative, we compute the class of registers allowed
1248 for reloading in CLS, and merge its contents into the reg set
1250 int cls = (int) NO_REGS;
1256 if (c == '\0' || c == ',' || c == '#')
1258 /* End of one alternative - mark the regs in the current
1259 class, and reset the class. */
1260 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1265 } while (c != '\0' && c != ',');
1273 case '=': case '+': case '*': case '%': case '?': case '!':
1274 case '0': case '1': case '2': case '3': case '4': case 'm':
1275 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1276 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1277 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1282 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1287 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1291 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1296 /* Those of the registers which are clobbered, but allowed by the
1297 constraints, must be usable as reload registers. So clear them
1298 out of the life information. */
1299 AND_HARD_REG_SET (allowed, clobbered);
1300 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1301 if (TEST_HARD_REG_BIT (allowed, i))
1303 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1304 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1311 /* Copy the global variables n_reloads and rld into the corresponding elts
1314 copy_reloads (chain)
1315 struct insn_chain *chain;
1317 chain->n_reloads = n_reloads;
1319 = (struct reload *) obstack_alloc (&reload_obstack,
1320 n_reloads * sizeof (struct reload));
1321 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1322 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1325 /* Walk the chain of insns, and determine for each whether it needs reloads
1326 and/or eliminations. Build the corresponding insns_need_reload list, and
1327 set something_needs_elimination as appropriate. */
1329 calculate_needs_all_insns (global)
1332 struct insn_chain **pprev_reload = &insns_need_reload;
1333 struct insn_chain *chain, *next = 0;
1335 something_needs_elimination = 0;
1337 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1338 for (chain = reload_insn_chain; chain != 0; chain = next)
1340 rtx insn = chain->insn;
1344 /* Clear out the shortcuts. */
1345 chain->n_reloads = 0;
1346 chain->need_elim = 0;
1347 chain->need_reload = 0;
1348 chain->need_operand_change = 0;
1350 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1351 include REG_LABEL), we need to see what effects this has on the
1352 known offsets at labels. */
1354 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1355 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1356 set_label_offsets (insn, insn, 0);
1360 rtx old_body = PATTERN (insn);
1361 int old_code = INSN_CODE (insn);
1362 rtx old_notes = REG_NOTES (insn);
1363 int did_elimination = 0;
1364 int operands_changed = 0;
1365 rtx set = single_set (insn);
1367 /* Skip insns that only set an equivalence. */
1368 if (set && GET_CODE (SET_DEST (set)) == REG
1369 && reg_renumber[REGNO (SET_DEST (set))] < 0
1370 && reg_equiv_constant[REGNO (SET_DEST (set))])
1373 /* If needed, eliminate any eliminable registers. */
1374 if (num_eliminable || num_eliminable_invariants)
1375 did_elimination = eliminate_regs_in_insn (insn, 0);
1377 /* Analyze the instruction. */
1378 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1379 global, spill_reg_order);
1381 /* If a no-op set needs more than one reload, this is likely
1382 to be something that needs input address reloads. We
1383 can't get rid of this cleanly later, and it is of no use
1384 anyway, so discard it now.
1385 We only do this when expensive_optimizations is enabled,
1386 since this complements reload inheritance / output
1387 reload deletion, and it can make debugging harder. */
1388 if (flag_expensive_optimizations && n_reloads > 1)
1390 rtx set = single_set (insn);
1392 && SET_SRC (set) == SET_DEST (set)
1393 && GET_CODE (SET_SRC (set)) == REG
1394 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1396 PUT_CODE (insn, NOTE);
1397 NOTE_SOURCE_FILE (insn) = 0;
1398 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1399 /* Delete it from the reload chain */
1401 chain->prev->next = next;
1403 reload_insn_chain = next;
1405 next->prev = chain->prev;
1406 chain->next = unused_insn_chains;
1407 unused_insn_chains = chain;
1412 update_eliminable_offsets ();
1414 /* Remember for later shortcuts which insns had any reloads or
1415 register eliminations. */
1416 chain->need_elim = did_elimination;
1417 chain->need_reload = n_reloads > 0;
1418 chain->need_operand_change = operands_changed;
1420 /* Discard any register replacements done. */
1421 if (did_elimination)
1423 obstack_free (&reload_obstack, reload_insn_firstobj);
1424 PATTERN (insn) = old_body;
1425 INSN_CODE (insn) = old_code;
1426 REG_NOTES (insn) = old_notes;
1427 something_needs_elimination = 1;
1430 something_needs_operands_changed |= operands_changed;
1434 copy_reloads (chain);
1435 *pprev_reload = chain;
1436 pprev_reload = &chain->next_need_reload;
1443 /* Comparison function for qsort to decide which of two reloads
1444 should be handled first. *P1 and *P2 are the reload numbers. */
1447 reload_reg_class_lower (r1p, r2p)
1451 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1454 /* Consider required reloads before optional ones. */
1455 t = rld[r1].optional - rld[r2].optional;
1459 /* Count all solitary classes before non-solitary ones. */
1460 t = ((reg_class_size[(int) rld[r2].class] == 1)
1461 - (reg_class_size[(int) rld[r1].class] == 1));
1465 /* Aside from solitaires, consider all multi-reg groups first. */
1466 t = rld[r2].nregs - rld[r1].nregs;
1470 /* Consider reloads in order of increasing reg-class number. */
1471 t = (int) rld[r1].class - (int) rld[r2].class;
1475 /* If reloads are equally urgent, sort by reload number,
1476 so that the results of qsort leave nothing to chance. */
1480 /* The cost of spilling each hard reg. */
1481 static int spill_cost[FIRST_PSEUDO_REGISTER];
1483 /* When spilling multiple hard registers, we use SPILL_COST for the first
1484 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1485 only the first hard reg for a multi-reg pseudo. */
1486 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1488 /* Update the spill cost arrays, considering that pseudo REG is live. */
1494 int n_refs = REG_N_REFS (reg);
1495 int r = reg_renumber[reg];
1498 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1499 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1502 SET_REGNO_REG_SET (&pseudos_counted, reg);
1507 spill_add_cost[r] += n_refs;
1509 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1511 spill_cost[r + nregs] += n_refs;
1514 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1515 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1518 order_regs_for_reload (chain)
1519 struct insn_chain *chain;
1522 HARD_REG_SET used_by_pseudos;
1523 HARD_REG_SET used_by_pseudos2;
1525 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1527 memset (spill_cost, 0, sizeof spill_cost);
1528 memset (spill_add_cost, 0, sizeof spill_add_cost);
1530 /* Count number of uses of each hard reg by pseudo regs allocated to it
1531 and then order them by decreasing use. First exclude hard registers
1532 that are live in or across this insn. */
1534 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1535 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1536 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1537 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1539 /* Now find out which pseudos are allocated to it, and update
1541 CLEAR_REG_SET (&pseudos_counted);
1543 EXECUTE_IF_SET_IN_REG_SET
1544 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1548 EXECUTE_IF_SET_IN_REG_SET
1549 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1553 CLEAR_REG_SET (&pseudos_counted);
1556 /* Vector of reload-numbers showing the order in which the reloads should
1558 static short reload_order[MAX_RELOADS];
1560 /* This is used to keep track of the spill regs used in one insn. */
1561 static HARD_REG_SET used_spill_regs_local;
1563 /* We decided to spill hard register SPILLED, which has a size of
1564 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1565 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1566 update SPILL_COST/SPILL_ADD_COST. */
1569 count_spilled_pseudo (spilled, spilled_nregs, reg)
1570 int spilled, spilled_nregs, reg;
1572 int r = reg_renumber[reg];
1573 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1575 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1576 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1579 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1581 spill_add_cost[r] -= REG_N_REFS (reg);
1583 spill_cost[r + nregs] -= REG_N_REFS (reg);
1586 /* Find reload register to use for reload number ORDER. */
1589 find_reg (chain, order)
1590 struct insn_chain *chain;
1593 int rnum = reload_order[order];
1594 struct reload *rl = rld + rnum;
1595 int best_cost = INT_MAX;
1599 HARD_REG_SET not_usable;
1600 HARD_REG_SET used_by_other_reload;
1602 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1603 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1604 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1606 CLEAR_HARD_REG_SET (used_by_other_reload);
1607 for (k = 0; k < order; k++)
1609 int other = reload_order[k];
1611 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1612 for (j = 0; j < rld[other].nregs; j++)
1613 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1616 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1618 unsigned int regno = i;
1620 if (! TEST_HARD_REG_BIT (not_usable, regno)
1621 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1622 && HARD_REGNO_MODE_OK (regno, rl->mode))
1624 int this_cost = spill_cost[regno];
1626 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1628 for (j = 1; j < this_nregs; j++)
1630 this_cost += spill_add_cost[regno + j];
1631 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1632 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1637 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1639 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1641 if (this_cost < best_cost
1642 /* Among registers with equal cost, prefer caller-saved ones, or
1643 use REG_ALLOC_ORDER if it is defined. */
1644 || (this_cost == best_cost
1645 #ifdef REG_ALLOC_ORDER
1646 && (inv_reg_alloc_order[regno]
1647 < inv_reg_alloc_order[best_reg])
1649 && call_used_regs[regno]
1650 && ! call_used_regs[best_reg]
1655 best_cost = this_cost;
1663 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1665 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1666 rl->regno = best_reg;
1668 EXECUTE_IF_SET_IN_REG_SET
1669 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1671 count_spilled_pseudo (best_reg, rl->nregs, j);
1674 EXECUTE_IF_SET_IN_REG_SET
1675 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1677 count_spilled_pseudo (best_reg, rl->nregs, j);
1680 for (i = 0; i < rl->nregs; i++)
1682 if (spill_cost[best_reg + i] != 0
1683 || spill_add_cost[best_reg + i] != 0)
1685 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1690 /* Find more reload regs to satisfy the remaining need of an insn, which
1692 Do it by ascending class number, since otherwise a reg
1693 might be spilled for a big class and might fail to count
1694 for a smaller class even though it belongs to that class. */
1697 find_reload_regs (chain)
1698 struct insn_chain *chain;
1702 /* In order to be certain of getting the registers we need,
1703 we must sort the reloads into order of increasing register class.
1704 Then our grabbing of reload registers will parallel the process
1705 that provided the reload registers. */
1706 for (i = 0; i < chain->n_reloads; i++)
1708 /* Show whether this reload already has a hard reg. */
1709 if (chain->rld[i].reg_rtx)
1711 int regno = REGNO (chain->rld[i].reg_rtx);
1712 chain->rld[i].regno = regno;
1714 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1717 chain->rld[i].regno = -1;
1718 reload_order[i] = i;
1721 n_reloads = chain->n_reloads;
1722 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1724 CLEAR_HARD_REG_SET (used_spill_regs_local);
1727 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1729 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1731 /* Compute the order of preference for hard registers to spill. */
1733 order_regs_for_reload (chain);
1735 for (i = 0; i < n_reloads; i++)
1737 int r = reload_order[i];
1739 /* Ignore reloads that got marked inoperative. */
1740 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1741 && ! rld[r].optional
1742 && rld[r].regno == -1)
1743 if (! find_reg (chain, i))
1745 spill_failure (chain->insn, rld[r].class);
1751 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1752 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1754 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1758 select_reload_regs ()
1760 struct insn_chain *chain;
1762 /* Try to satisfy the needs for each insn. */
1763 for (chain = insns_need_reload; chain != 0;
1764 chain = chain->next_need_reload)
1765 find_reload_regs (chain);
1768 /* Delete all insns that were inserted by emit_caller_save_insns during
1771 delete_caller_save_insns ()
1773 struct insn_chain *c = reload_insn_chain;
1777 while (c != 0 && c->is_caller_save_insn)
1779 struct insn_chain *next = c->next;
1782 if (insn == BLOCK_HEAD (c->block))
1783 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1784 if (insn == BLOCK_END (c->block))
1785 BLOCK_END (c->block) = PREV_INSN (insn);
1786 if (c == reload_insn_chain)
1787 reload_insn_chain = next;
1789 if (NEXT_INSN (insn) != 0)
1790 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1791 if (PREV_INSN (insn) != 0)
1792 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1795 next->prev = c->prev;
1797 c->prev->next = next;
1798 c->next = unused_insn_chains;
1799 unused_insn_chains = c;
1807 /* Handle the failure to find a register to spill.
1808 INSN should be one of the insns which needed this particular spill reg. */
1811 spill_failure (insn, class)
1813 enum reg_class class;
1815 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1816 if (asm_noperands (PATTERN (insn)) >= 0)
1817 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1818 reg_class_names[class]);
1821 error ("Unable to find a register to spill in class `%s'.",
1822 reg_class_names[class]);
1823 fatal_insn ("This is the insn:", insn);
1827 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1828 data that is dead in INSN. */
1831 delete_dead_insn (insn)
1834 rtx prev = prev_real_insn (insn);
1837 /* If the previous insn sets a register that dies in our insn, delete it
1839 if (prev && GET_CODE (PATTERN (prev)) == SET
1840 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1841 && reg_mentioned_p (prev_dest, PATTERN (insn))
1842 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1843 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1844 delete_dead_insn (prev);
1846 PUT_CODE (insn, NOTE);
1847 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1848 NOTE_SOURCE_FILE (insn) = 0;
1851 /* Modify the home of pseudo-reg I.
1852 The new home is present in reg_renumber[I].
1854 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1855 or it may be -1, meaning there is none or it is not relevant.
1856 This is used so that all pseudos spilled from a given hard reg
1857 can share one stack slot. */
1860 alter_reg (i, from_reg)
1864 /* When outputting an inline function, this can happen
1865 for a reg that isn't actually used. */
1866 if (regno_reg_rtx[i] == 0)
1869 /* If the reg got changed to a MEM at rtl-generation time,
1871 if (GET_CODE (regno_reg_rtx[i]) != REG)
1874 /* Modify the reg-rtx to contain the new hard reg
1875 number or else to contain its pseudo reg number. */
1876 REGNO (regno_reg_rtx[i])
1877 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1879 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1880 allocate a stack slot for it. */
1882 if (reg_renumber[i] < 0
1883 && REG_N_REFS (i) > 0
1884 && reg_equiv_constant[i] == 0
1885 && reg_equiv_memory_loc[i] == 0)
1888 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1889 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1892 /* Each pseudo reg has an inherent size which comes from its own mode,
1893 and a total size which provides room for paradoxical subregs
1894 which refer to the pseudo reg in wider modes.
1896 We can use a slot already allocated if it provides both
1897 enough inherent space and enough total space.
1898 Otherwise, we allocate a new slot, making sure that it has no less
1899 inherent space, and no less total space, then the previous slot. */
1902 /* No known place to spill from => no slot to reuse. */
1903 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1904 inherent_size == total_size ? 0 : -1);
1905 if (BYTES_BIG_ENDIAN)
1906 /* Cancel the big-endian correction done in assign_stack_local.
1907 Get the address of the beginning of the slot.
1908 This is so we can do a big-endian correction unconditionally
1910 adjust = inherent_size - total_size;
1912 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1914 /* Nothing can alias this slot except this pseudo. */
1915 MEM_ALIAS_SET (x) = new_alias_set ();
1918 /* Reuse a stack slot if possible. */
1919 else if (spill_stack_slot[from_reg] != 0
1920 && spill_stack_slot_width[from_reg] >= total_size
1921 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1923 x = spill_stack_slot[from_reg];
1925 /* Allocate a bigger slot. */
1928 /* Compute maximum size needed, both for inherent size
1929 and for total size. */
1930 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1933 if (spill_stack_slot[from_reg])
1935 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1937 mode = GET_MODE (spill_stack_slot[from_reg]);
1938 if (spill_stack_slot_width[from_reg] > total_size)
1939 total_size = spill_stack_slot_width[from_reg];
1942 /* Make a slot with that size. */
1943 x = assign_stack_local (mode, total_size,
1944 inherent_size == total_size ? 0 : -1);
1947 /* All pseudos mapped to this slot can alias each other. */
1948 if (spill_stack_slot[from_reg])
1949 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1951 MEM_ALIAS_SET (x) = new_alias_set ();
1953 if (BYTES_BIG_ENDIAN)
1955 /* Cancel the big-endian correction done in assign_stack_local.
1956 Get the address of the beginning of the slot.
1957 This is so we can do a big-endian correction unconditionally
1959 adjust = GET_MODE_SIZE (mode) - total_size;
1961 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1964 plus_constant (XEXP (x, 0), adjust));
1967 spill_stack_slot[from_reg] = stack_slot;
1968 spill_stack_slot_width[from_reg] = total_size;
1971 /* On a big endian machine, the "address" of the slot
1972 is the address of the low part that fits its inherent mode. */
1973 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1974 adjust += (total_size - inherent_size);
1976 /* If we have any adjustment to make, or if the stack slot is the
1977 wrong mode, make a new stack slot. */
1978 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1980 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1981 plus_constant (XEXP (x, 0), adjust));
1983 MEM_COPY_ATTRIBUTES (new, x);
1987 /* Save the stack slot for later. */
1988 reg_equiv_memory_loc[i] = x;
1992 /* Mark the slots in regs_ever_live for the hard regs
1993 used by pseudo-reg number REGNO. */
1996 mark_home_live (regno)
1999 register int i, lim;
2001 i = reg_renumber[regno];
2004 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2006 regs_ever_live[i++] = 1;
2009 /* This function handles the tracking of elimination offsets around branches.
2011 X is a piece of RTL being scanned.
2013 INSN is the insn that it came from, if any.
2015 INITIAL_P is non-zero if we are to set the offset to be the initial
2016 offset and zero if we are setting the offset of the label to be the
2020 set_label_offsets (x, insn, initial_p)
2025 enum rtx_code code = GET_CODE (x);
2028 struct elim_table *p;
2033 if (LABEL_REF_NONLOCAL_P (x))
2038 /* ... fall through ... */
2041 /* If we know nothing about this label, set the desired offsets. Note
2042 that this sets the offset at a label to be the offset before a label
2043 if we don't know anything about the label. This is not correct for
2044 the label after a BARRIER, but is the best guess we can make. If
2045 we guessed wrong, we will suppress an elimination that might have
2046 been possible had we been able to guess correctly. */
2048 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2050 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2051 offsets_at[CODE_LABEL_NUMBER (x)][i]
2052 = (initial_p ? reg_eliminate[i].initial_offset
2053 : reg_eliminate[i].offset);
2054 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2057 /* Otherwise, if this is the definition of a label and it is
2058 preceded by a BARRIER, set our offsets to the known offset of
2062 && (tem = prev_nonnote_insn (insn)) != 0
2063 && GET_CODE (tem) == BARRIER)
2064 set_offsets_for_label (insn);
2066 /* If neither of the above cases is true, compare each offset
2067 with those previously recorded and suppress any eliminations
2068 where the offsets disagree. */
2070 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2071 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2072 != (initial_p ? reg_eliminate[i].initial_offset
2073 : reg_eliminate[i].offset))
2074 reg_eliminate[i].can_eliminate = 0;
2079 set_label_offsets (PATTERN (insn), insn, initial_p);
2081 /* ... fall through ... */
2085 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2086 and hence must have all eliminations at their initial offsets. */
2087 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2088 if (REG_NOTE_KIND (tem) == REG_LABEL)
2089 set_label_offsets (XEXP (tem, 0), insn, 1);
2094 /* Each of the labels in the address vector must be at their initial
2095 offsets. We want the first field for ADDR_VEC and the second
2096 field for ADDR_DIFF_VEC. */
2098 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2099 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2104 /* We only care about setting PC. If the source is not RETURN,
2105 IF_THEN_ELSE, or a label, disable any eliminations not at
2106 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2107 isn't one of those possibilities. For branches to a label,
2108 call ourselves recursively.
2110 Note that this can disable elimination unnecessarily when we have
2111 a non-local goto since it will look like a non-constant jump to
2112 someplace in the current function. This isn't a significant
2113 problem since such jumps will normally be when all elimination
2114 pairs are back to their initial offsets. */
2116 if (SET_DEST (x) != pc_rtx)
2119 switch (GET_CODE (SET_SRC (x)))
2126 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2130 tem = XEXP (SET_SRC (x), 1);
2131 if (GET_CODE (tem) == LABEL_REF)
2132 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2133 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2136 tem = XEXP (SET_SRC (x), 2);
2137 if (GET_CODE (tem) == LABEL_REF)
2138 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2139 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2147 /* If we reach here, all eliminations must be at their initial
2148 offset because we are doing a jump to a variable address. */
2149 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2150 if (p->offset != p->initial_offset)
2151 p->can_eliminate = 0;
2159 /* Scan X and replace any eliminable registers (such as fp) with a
2160 replacement (such as sp), plus an offset.
2162 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2163 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2164 MEM, we are allowed to replace a sum of a register and the constant zero
2165 with the register, which we cannot do outside a MEM. In addition, we need
2166 to record the fact that a register is referenced outside a MEM.
2168 If INSN is an insn, it is the insn containing X. If we replace a REG
2169 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2170 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2171 the REG is being modified.
2173 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2174 That's used when we eliminate in expressions stored in notes.
2175 This means, do not set ref_outside_mem even if the reference
2178 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2179 replacements done assuming all offsets are at their initial values. If
2180 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2181 encounter, return the actual location so that find_reloads will do
2182 the proper thing. */
2185 eliminate_regs (x, mem_mode, insn)
2187 enum machine_mode mem_mode;
2190 enum rtx_code code = GET_CODE (x);
2191 struct elim_table *ep;
2198 if (! current_function_decl)
2217 /* This is only for the benefit of the debugging backends, which call
2218 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2219 removed after CSE. */
2220 new = eliminate_regs (XEXP (x, 0), 0, insn);
2221 if (GET_CODE (new) == MEM)
2222 return XEXP (new, 0);
2228 /* First handle the case where we encounter a bare register that
2229 is eliminable. Replace it with a PLUS. */
2230 if (regno < FIRST_PSEUDO_REGISTER)
2232 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2234 if (ep->from_rtx == x && ep->can_eliminate)
2235 return plus_constant (ep->to_rtx, ep->previous_offset);
2238 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2239 && reg_equiv_constant[regno]
2240 && ! CONSTANT_P (reg_equiv_constant[regno]))
2241 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2245 /* You might think handling MINUS in a manner similar to PLUS is a
2246 good idea. It is not. It has been tried multiple times and every
2247 time the change has had to have been reverted.
2249 Other parts of reload know a PLUS is special (gen_reload for example)
2250 and require special code to handle code a reloaded PLUS operand.
2252 Also consider backends where the flags register is clobbered by a
2253 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2254 lea instruction comes to mind). If we try to reload a MINUS, we
2255 may kill the flags register that was holding a useful value.
2257 So, please before trying to handle MINUS, consider reload as a
2258 whole instead of this little section as well as the backend issues. */
2260 /* If this is the sum of an eliminable register and a constant, rework
2262 if (GET_CODE (XEXP (x, 0)) == REG
2263 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2264 && CONSTANT_P (XEXP (x, 1)))
2266 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2268 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2270 /* The only time we want to replace a PLUS with a REG (this
2271 occurs when the constant operand of the PLUS is the negative
2272 of the offset) is when we are inside a MEM. We won't want
2273 to do so at other times because that would change the
2274 structure of the insn in a way that reload can't handle.
2275 We special-case the commonest situation in
2276 eliminate_regs_in_insn, so just replace a PLUS with a
2277 PLUS here, unless inside a MEM. */
2278 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2279 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2282 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2283 plus_constant (XEXP (x, 1),
2284 ep->previous_offset));
2287 /* If the register is not eliminable, we are done since the other
2288 operand is a constant. */
2292 /* If this is part of an address, we want to bring any constant to the
2293 outermost PLUS. We will do this by doing register replacement in
2294 our operands and seeing if a constant shows up in one of them.
2296 Note that there is no risk of modifying the structure of the insn,
2297 since we only get called for its operands, thus we are either
2298 modifying the address inside a MEM, or something like an address
2299 operand of a load-address insn. */
2302 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2303 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2305 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2307 /* If one side is a PLUS and the other side is a pseudo that
2308 didn't get a hard register but has a reg_equiv_constant,
2309 we must replace the constant here since it may no longer
2310 be in the position of any operand. */
2311 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2312 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2313 && reg_renumber[REGNO (new1)] < 0
2314 && reg_equiv_constant != 0
2315 && reg_equiv_constant[REGNO (new1)] != 0)
2316 new1 = reg_equiv_constant[REGNO (new1)];
2317 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2318 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2319 && reg_renumber[REGNO (new0)] < 0
2320 && reg_equiv_constant[REGNO (new0)] != 0)
2321 new0 = reg_equiv_constant[REGNO (new0)];
2323 new = form_sum (new0, new1);
2325 /* As above, if we are not inside a MEM we do not want to
2326 turn a PLUS into something else. We might try to do so here
2327 for an addition of 0 if we aren't optimizing. */
2328 if (! mem_mode && GET_CODE (new) != PLUS)
2329 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2337 /* If this is the product of an eliminable register and a
2338 constant, apply the distribute law and move the constant out
2339 so that we have (plus (mult ..) ..). This is needed in order
2340 to keep load-address insns valid. This case is pathological.
2341 We ignore the possibility of overflow here. */
2342 if (GET_CODE (XEXP (x, 0)) == REG
2343 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2344 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2345 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2347 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2350 /* Refs inside notes don't count for this purpose. */
2351 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2352 || GET_CODE (insn) == INSN_LIST)))
2353 ep->ref_outside_mem = 1;
2356 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2357 ep->previous_offset * INTVAL (XEXP (x, 1)));
2360 /* ... fall through ... */
2364 /* See comments before PLUS about handling MINUS. */
2366 case DIV: case UDIV:
2367 case MOD: case UMOD:
2368 case AND: case IOR: case XOR:
2369 case ROTATERT: case ROTATE:
2370 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2372 case GE: case GT: case GEU: case GTU:
2373 case LE: case LT: case LEU: case LTU:
2375 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2377 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2379 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2380 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2385 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2388 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2389 if (new != XEXP (x, 0))
2391 /* If this is a REG_DEAD note, it is not valid anymore.
2392 Using the eliminated version could result in creating a
2393 REG_DEAD note for the stack or frame pointer. */
2394 if (GET_MODE (x) == REG_DEAD)
2396 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2399 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2403 /* ... fall through ... */
2406 /* Now do eliminations in the rest of the chain. If this was
2407 an EXPR_LIST, this might result in allocating more memory than is
2408 strictly needed, but it simplifies the code. */
2411 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2412 if (new != XEXP (x, 1))
2413 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2421 case STRICT_LOW_PART:
2423 case SIGN_EXTEND: case ZERO_EXTEND:
2424 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2425 case FLOAT: case FIX:
2426 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2430 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2431 if (new != XEXP (x, 0))
2432 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2436 /* Similar to above processing, but preserve SUBREG_WORD.
2437 Convert (subreg (mem)) to (mem) if not paradoxical.
2438 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2439 pseudo didn't get a hard reg, we must replace this with the
2440 eliminated version of the memory location because push_reloads
2441 may do the replacement in certain circumstances. */
2442 if (GET_CODE (SUBREG_REG (x)) == REG
2443 && (GET_MODE_SIZE (GET_MODE (x))
2444 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2445 && reg_equiv_memory_loc != 0
2446 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2448 new = SUBREG_REG (x);
2451 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2453 if (new != XEXP (x, 0))
2455 int x_size = GET_MODE_SIZE (GET_MODE (x));
2456 int new_size = GET_MODE_SIZE (GET_MODE (new));
2458 if (GET_CODE (new) == MEM
2459 && ((x_size < new_size
2460 #ifdef WORD_REGISTER_OPERATIONS
2461 /* On these machines, combine can create rtl of the form
2462 (set (subreg:m1 (reg:m2 R) 0) ...)
2463 where m1 < m2, and expects something interesting to
2464 happen to the entire word. Moreover, it will use the
2465 (reg:m2 R) later, expecting all bits to be preserved.
2466 So if the number of words is the same, preserve the
2467 subreg so that push_reloads can see it. */
2468 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2471 || (x_size == new_size))
2474 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2475 enum machine_mode mode = GET_MODE (x);
2477 if (BYTES_BIG_ENDIAN)
2478 offset += (MIN (UNITS_PER_WORD,
2479 GET_MODE_SIZE (GET_MODE (new)))
2480 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2482 PUT_MODE (new, mode);
2483 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2487 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2493 /* This is only for the benefit of the debugging backends, which call
2494 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2495 removed after CSE. */
2496 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2497 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2499 /* Our only special processing is to pass the mode of the MEM to our
2500 recursive call and copy the flags. While we are here, handle this
2501 case more efficiently. */
2502 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2503 if (new != XEXP (x, 0))
2505 new = gen_rtx_MEM (GET_MODE (x), new);
2506 MEM_COPY_ATTRIBUTES (new, x);
2522 /* Process each of our operands recursively. If any have changed, make a
2524 fmt = GET_RTX_FORMAT (code);
2525 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2529 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2530 if (new != XEXP (x, i) && ! copied)
2532 rtx new_x = rtx_alloc (code);
2533 bcopy ((char *) x, (char *) new_x,
2534 (sizeof (*new_x) - sizeof (new_x->fld)
2535 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2541 else if (*fmt == 'E')
2544 for (j = 0; j < XVECLEN (x, i); j++)
2546 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2547 if (new != XVECEXP (x, i, j) && ! copied_vec)
2549 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2553 rtx new_x = rtx_alloc (code);
2554 bcopy ((char *) x, (char *) new_x,
2555 (sizeof (*new_x) - sizeof (new_x->fld)
2556 + (sizeof (new_x->fld[0])
2557 * GET_RTX_LENGTH (code))));
2561 XVEC (x, i) = new_v;
2564 XVECEXP (x, i, j) = new;
2572 /* Scan rtx X for modifications of elimination target registers. Update
2573 the table of eliminables to reflect the changed state. MEM_MODE is
2574 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2577 elimination_effects (x, mem_mode)
2579 enum machine_mode mem_mode;
2582 enum rtx_code code = GET_CODE (x);
2583 struct elim_table *ep;
2609 /* First handle the case where we encounter a bare register that
2610 is eliminable. Replace it with a PLUS. */
2611 if (regno < FIRST_PSEUDO_REGISTER)
2613 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2615 if (ep->from_rtx == x && ep->can_eliminate)
2618 ep->ref_outside_mem = 1;
2623 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2624 && reg_equiv_constant[regno]
2625 && ! CONSTANT_P (reg_equiv_constant[regno]))
2626 elimination_effects (reg_equiv_constant[regno], mem_mode);
2635 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2636 if (ep->to_rtx == XEXP (x, 0))
2638 int size = GET_MODE_SIZE (mem_mode);
2640 /* If more bytes than MEM_MODE are pushed, account for them. */
2641 #ifdef PUSH_ROUNDING
2642 if (ep->to_rtx == stack_pointer_rtx)
2643 size = PUSH_ROUNDING (size);
2645 if (code == PRE_DEC || code == POST_DEC)
2647 else if (code == PRE_INC || code == POST_INC)
2649 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2650 && GET_CODE (XEXP (x, 1)) == PLUS
2651 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2652 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2653 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2656 /* These two aren't unary operators. */
2657 if (code == POST_MODIFY || code == PRE_MODIFY)
2660 /* Fall through to generic unary operation case. */
2661 case STRICT_LOW_PART:
2663 case SIGN_EXTEND: case ZERO_EXTEND:
2664 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2665 case FLOAT: case FIX:
2666 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2670 elimination_effects (XEXP (x, 0), mem_mode);
2674 if (GET_CODE (SUBREG_REG (x)) == REG
2675 && (GET_MODE_SIZE (GET_MODE (x))
2676 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2677 && reg_equiv_memory_loc != 0
2678 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2681 elimination_effects (SUBREG_REG (x), mem_mode);
2685 /* If using a register that is the source of an eliminate we still
2686 think can be performed, note it cannot be performed since we don't
2687 know how this register is used. */
2688 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2689 if (ep->from_rtx == XEXP (x, 0))
2690 ep->can_eliminate = 0;
2692 elimination_effects (XEXP (x, 0), mem_mode);
2696 /* If clobbering a register that is the replacement register for an
2697 elimination we still think can be performed, note that it cannot
2698 be performed. Otherwise, we need not be concerned about it. */
2699 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2700 if (ep->to_rtx == XEXP (x, 0))
2701 ep->can_eliminate = 0;
2703 elimination_effects (XEXP (x, 0), mem_mode);
2707 /* Check for setting a register that we know about. */
2708 if (GET_CODE (SET_DEST (x)) == REG)
2710 /* See if this is setting the replacement register for an
2713 If DEST is the hard frame pointer, we do nothing because we
2714 assume that all assignments to the frame pointer are for
2715 non-local gotos and are being done at a time when they are valid
2716 and do not disturb anything else. Some machines want to
2717 eliminate a fake argument pointer (or even a fake frame pointer)
2718 with either the real frame or the stack pointer. Assignments to
2719 the hard frame pointer must not prevent this elimination. */
2721 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2723 if (ep->to_rtx == SET_DEST (x)
2724 && SET_DEST (x) != hard_frame_pointer_rtx)
2726 /* If it is being incremented, adjust the offset. Otherwise,
2727 this elimination can't be done. */
2728 rtx src = SET_SRC (x);
2730 if (GET_CODE (src) == PLUS
2731 && XEXP (src, 0) == SET_DEST (x)
2732 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2733 ep->offset -= INTVAL (XEXP (src, 1));
2735 ep->can_eliminate = 0;
2739 elimination_effects (SET_DEST (x), 0);
2740 elimination_effects (SET_SRC (x), 0);
2744 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2747 /* Our only special processing is to pass the mode of the MEM to our
2749 elimination_effects (XEXP (x, 0), GET_MODE (x));
2756 fmt = GET_RTX_FORMAT (code);
2757 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2760 elimination_effects (XEXP (x, i), mem_mode);
2761 else if (*fmt == 'E')
2762 for (j = 0; j < XVECLEN (x, i); j++)
2763 elimination_effects (XVECEXP (x, i, j), mem_mode);
2767 /* Descend through rtx X and verify that no references to eliminable registers
2768 remain. If any do remain, mark the involved register as not
2772 check_eliminable_occurrences (x)
2782 code = GET_CODE (x);
2784 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2786 struct elim_table *ep;
2788 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2789 if (ep->from_rtx == x && ep->can_eliminate)
2790 ep->can_eliminate = 0;
2794 fmt = GET_RTX_FORMAT (code);
2795 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2798 check_eliminable_occurrences (XEXP (x, i));
2799 else if (*fmt == 'E')
2802 for (j = 0; j < XVECLEN (x, i); j++)
2803 check_eliminable_occurrences (XVECEXP (x, i, j));
2808 /* Scan INSN and eliminate all eliminable registers in it.
2810 If REPLACE is nonzero, do the replacement destructively. Also
2811 delete the insn as dead it if it is setting an eliminable register.
2813 If REPLACE is zero, do all our allocations in reload_obstack.
2815 If no eliminations were done and this insn doesn't require any elimination
2816 processing (these are not identical conditions: it might be updating sp,
2817 but not referencing fp; this needs to be seen during reload_as_needed so
2818 that the offset between fp and sp can be taken into consideration), zero
2819 is returned. Otherwise, 1 is returned. */
2822 eliminate_regs_in_insn (insn, replace)
2826 int icode = recog_memoized (insn);
2827 rtx old_body = PATTERN (insn);
2828 int insn_is_asm = asm_noperands (old_body) >= 0;
2829 rtx old_set = single_set (insn);
2833 rtx substed_operand[MAX_RECOG_OPERANDS];
2834 rtx orig_operand[MAX_RECOG_OPERANDS];
2835 struct elim_table *ep;
2837 if (! insn_is_asm && icode < 0)
2839 if (GET_CODE (PATTERN (insn)) == USE
2840 || GET_CODE (PATTERN (insn)) == CLOBBER
2841 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2842 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2843 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2848 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2849 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2851 /* Check for setting an eliminable register. */
2852 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2853 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2855 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2856 /* If this is setting the frame pointer register to the
2857 hardware frame pointer register and this is an elimination
2858 that will be done (tested above), this insn is really
2859 adjusting the frame pointer downward to compensate for
2860 the adjustment done before a nonlocal goto. */
2861 if (ep->from == FRAME_POINTER_REGNUM
2862 && ep->to == HARD_FRAME_POINTER_REGNUM)
2864 rtx src = SET_SRC (old_set);
2865 int offset = 0, ok = 0;
2866 rtx prev_insn, prev_set;
2868 if (src == ep->to_rtx)
2870 else if (GET_CODE (src) == PLUS
2871 && GET_CODE (XEXP (src, 0)) == CONST_INT
2872 && XEXP (src, 1) == ep->to_rtx)
2873 offset = INTVAL (XEXP (src, 0)), ok = 1;
2874 else if (GET_CODE (src) == PLUS
2875 && GET_CODE (XEXP (src, 1)) == CONST_INT
2876 && XEXP (src, 0) == ep->to_rtx)
2877 offset = INTVAL (XEXP (src, 1)), ok = 1;
2878 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2879 && (prev_set = single_set (prev_insn)) != 0
2880 && rtx_equal_p (SET_DEST (prev_set), src))
2882 src = SET_SRC (prev_set);
2883 if (src == ep->to_rtx)
2885 else if (GET_CODE (src) == PLUS
2886 && GET_CODE (XEXP (src, 0)) == CONST_INT
2887 && XEXP (src, 1) == ep->to_rtx)
2888 offset = INTVAL (XEXP (src, 0)), ok = 1;
2889 else if (GET_CODE (src) == PLUS
2890 && GET_CODE (XEXP (src, 1)) == CONST_INT
2891 && XEXP (src, 0) == ep->to_rtx)
2892 offset = INTVAL (XEXP (src, 1)), ok = 1;
2900 = plus_constant (ep->to_rtx, offset - ep->offset);
2902 /* First see if this insn remains valid when we
2903 make the change. If not, keep the INSN_CODE
2904 the same and let reload fit it up. */
2905 validate_change (insn, &SET_SRC (old_set), src, 1);
2906 validate_change (insn, &SET_DEST (old_set),
2908 if (! apply_change_group ())
2910 SET_SRC (old_set) = src;
2911 SET_DEST (old_set) = ep->to_rtx;
2921 /* In this case this insn isn't serving a useful purpose. We
2922 will delete it in reload_as_needed once we know that this
2923 elimination is, in fact, being done.
2925 If REPLACE isn't set, we can't delete this insn, but needn't
2926 process it since it won't be used unless something changes. */
2929 delete_dead_insn (insn);
2937 /* We allow one special case which happens to work on all machines we
2938 currently support: a single set with the source being a PLUS of an
2939 eliminable register and a constant. */
2941 && GET_CODE (SET_SRC (old_set)) == PLUS
2942 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2943 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2944 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2946 rtx reg = XEXP (SET_SRC (old_set), 0);
2947 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2949 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2950 if (ep->from_rtx == reg && ep->can_eliminate)
2952 offset += ep->offset;
2956 /* We assume here that we don't need a PARALLEL of
2957 any CLOBBERs for this assignment. There's not
2958 much we can do if we do need it. */
2959 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2962 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
2963 if (INSN_CODE (insn) < 0)
2968 new_body = old_body;
2971 new_body = copy_insn (old_body);
2972 if (REG_NOTES (insn))
2973 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2975 PATTERN (insn) = new_body;
2976 old_set = single_set (insn);
2978 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2979 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2982 /* This can't have an effect on elimination offsets, so skip right
2988 /* Determine the effects of this insn on elimination offsets. */
2989 elimination_effects (old_body, 0);
2991 /* Eliminate all eliminable registers occurring in operands that
2992 can be handled by reload. */
2993 extract_insn (insn);
2995 for (i = 0; i < recog_data.n_operands; i++)
2997 orig_operand[i] = recog_data.operand[i];
2998 substed_operand[i] = recog_data.operand[i];
3000 /* For an asm statement, every operand is eliminable. */
3001 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3003 /* Check for setting a register that we know about. */
3004 if (recog_data.operand_type[i] != OP_IN
3005 && GET_CODE (orig_operand[i]) == REG)
3007 /* If we are assigning to a register that can be eliminated, it
3008 must be as part of a PARALLEL, since the code above handles
3009 single SETs. We must indicate that we can no longer
3010 eliminate this reg. */
3011 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3013 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3014 ep->can_eliminate = 0;
3017 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3018 replace ? insn : NULL_RTX);
3019 if (substed_operand[i] != orig_operand[i])
3020 val = any_changes = 1;
3021 /* Terminate the search in check_eliminable_occurrences at
3023 *recog_data.operand_loc[i] = 0;
3025 /* If an output operand changed from a REG to a MEM and INSN is an
3026 insn, write a CLOBBER insn. */
3027 if (recog_data.operand_type[i] != OP_IN
3028 && GET_CODE (orig_operand[i]) == REG
3029 && GET_CODE (substed_operand[i]) == MEM
3031 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3036 for (i = 0; i < recog_data.n_dups; i++)
3037 *recog_data.dup_loc[i]
3038 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3040 /* If any eliminable remain, they aren't eliminable anymore. */
3041 check_eliminable_occurrences (old_body);
3043 /* Substitute the operands; the new values are in the substed_operand
3045 for (i = 0; i < recog_data.n_operands; i++)
3046 *recog_data.operand_loc[i] = substed_operand[i];
3047 for (i = 0; i < recog_data.n_dups; i++)
3048 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3050 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3051 re-recognize the insn. We do this in case we had a simple addition
3052 but now can do this as a load-address. This saves an insn in this
3054 If re-recognition fails, the old insn code number will still be used,
3055 and some register operands may have changed into PLUS expressions.
3056 These will be handled by find_reloads by loading them into a register
3061 /* If we aren't replacing things permanently and we changed something,
3062 make another copy to ensure that all the RTL is new. Otherwise
3063 things can go wrong if find_reload swaps commutative operands
3064 and one is inside RTL that has been copied while the other is not. */
3065 new_body = old_body;
3068 new_body = copy_insn (old_body);
3069 if (REG_NOTES (insn))
3070 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3072 PATTERN (insn) = new_body;
3074 /* If we had a move insn but now we don't, rerecognize it. This will
3075 cause spurious re-recognition if the old move had a PARALLEL since
3076 the new one still will, but we can't call single_set without
3077 having put NEW_BODY into the insn and the re-recognition won't
3078 hurt in this rare case. */
3079 /* ??? Why this huge if statement - why don't we just rerecognize the
3083 && ((GET_CODE (SET_SRC (old_set)) == REG
3084 && (GET_CODE (new_body) != SET
3085 || GET_CODE (SET_SRC (new_body)) != REG))
3086 /* If this was a load from or store to memory, compare
3087 the MEM in recog_data.operand to the one in the insn.
3088 If they are not equal, then rerecognize the insn. */
3090 && ((GET_CODE (SET_SRC (old_set)) == MEM
3091 && SET_SRC (old_set) != recog_data.operand[1])
3092 || (GET_CODE (SET_DEST (old_set)) == MEM
3093 && SET_DEST (old_set) != recog_data.operand[0])))
3094 /* If this was an add insn before, rerecognize. */
3095 || GET_CODE (SET_SRC (old_set)) == PLUS))
3097 int new_icode = recog (PATTERN (insn), insn, 0);
3099 INSN_CODE (insn) = icode;
3103 /* Restore the old body. If there were any changes to it, we made a copy
3104 of it while the changes were still in place, so we'll correctly return
3105 a modified insn below. */
3108 /* Restore the old body. */
3109 for (i = 0; i < recog_data.n_operands; i++)
3110 *recog_data.operand_loc[i] = orig_operand[i];
3111 for (i = 0; i < recog_data.n_dups; i++)
3112 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3115 /* Update all elimination pairs to reflect the status after the current
3116 insn. The changes we make were determined by the earlier call to
3117 elimination_effects.
3119 We also detect a cases where register elimination cannot be done,
3120 namely, if a register would be both changed and referenced outside a MEM
3121 in the resulting insn since such an insn is often undefined and, even if
3122 not, we cannot know what meaning will be given to it. Note that it is
3123 valid to have a register used in an address in an insn that changes it
3124 (presumably with a pre- or post-increment or decrement).
3126 If anything changes, return nonzero. */
3128 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3130 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3131 ep->can_eliminate = 0;
3133 ep->ref_outside_mem = 0;
3135 if (ep->previous_offset != ep->offset)
3140 /* If we changed something, perform elimination in REG_NOTES. This is
3141 needed even when REPLACE is zero because a REG_DEAD note might refer
3142 to a register that we eliminate and could cause a different number
3143 of spill registers to be needed in the final reload pass than in
3145 if (val && REG_NOTES (insn) != 0)
3146 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3151 /* Loop through all elimination pairs.
3152 Recalculate the number not at initial offset.
3154 Compute the maximum offset (minimum offset if the stack does not
3155 grow downward) for each elimination pair. */
3158 update_eliminable_offsets ()
3160 struct elim_table *ep;
3162 num_not_at_initial_offset = 0;
3163 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3165 ep->previous_offset = ep->offset;
3166 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3167 num_not_at_initial_offset++;
3171 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3172 replacement we currently believe is valid, mark it as not eliminable if X
3173 modifies DEST in any way other than by adding a constant integer to it.
3175 If DEST is the frame pointer, we do nothing because we assume that
3176 all assignments to the hard frame pointer are nonlocal gotos and are being
3177 done at a time when they are valid and do not disturb anything else.
3178 Some machines want to eliminate a fake argument pointer with either the
3179 frame or stack pointer. Assignments to the hard frame pointer must not
3180 prevent this elimination.
3182 Called via note_stores from reload before starting its passes to scan
3183 the insns of the function. */
3186 mark_not_eliminable (dest, x, data)
3189 void *data ATTRIBUTE_UNUSED;
3191 register unsigned int i;
3193 /* A SUBREG of a hard register here is just changing its mode. We should
3194 not see a SUBREG of an eliminable hard register, but check just in
3196 if (GET_CODE (dest) == SUBREG)
3197 dest = SUBREG_REG (dest);
3199 if (dest == hard_frame_pointer_rtx)
3202 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3203 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3204 && (GET_CODE (x) != SET
3205 || GET_CODE (SET_SRC (x)) != PLUS
3206 || XEXP (SET_SRC (x), 0) != dest
3207 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3209 reg_eliminate[i].can_eliminate_previous
3210 = reg_eliminate[i].can_eliminate = 0;
3215 /* Verify that the initial elimination offsets did not change since the
3216 last call to set_initial_elim_offsets. This is used to catch cases
3217 where something illegal happened during reload_as_needed that could
3218 cause incorrect code to be generated if we did not check for it. */
3221 verify_initial_elim_offsets ()
3225 #ifdef ELIMINABLE_REGS
3226 struct elim_table *ep;
3228 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3230 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3231 if (t != ep->initial_offset)
3235 INITIAL_FRAME_POINTER_OFFSET (t);
3236 if (t != reg_eliminate[0].initial_offset)
3241 /* Reset all offsets on eliminable registers to their initial values. */
3244 set_initial_elim_offsets ()
3246 struct elim_table *ep = reg_eliminate;
3248 #ifdef ELIMINABLE_REGS
3249 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3251 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3252 ep->previous_offset = ep->offset = ep->initial_offset;
3255 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3256 ep->previous_offset = ep->offset = ep->initial_offset;
3259 num_not_at_initial_offset = 0;
3262 /* Initialize the known label offsets.
3263 Set a known offset for each forced label to be at the initial offset
3264 of each elimination. We do this because we assume that all
3265 computed jumps occur from a location where each elimination is
3266 at its initial offset.
3267 For all other labels, show that we don't know the offsets. */
3270 set_initial_label_offsets ()
3273 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3275 for (x = forced_labels; x; x = XEXP (x, 1))
3277 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3280 /* Set all elimination offsets to the known values for the code label given
3284 set_offsets_for_label (insn)
3288 int label_nr = CODE_LABEL_NUMBER (insn);
3289 struct elim_table *ep;
3291 num_not_at_initial_offset = 0;
3292 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3294 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3295 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3296 num_not_at_initial_offset++;
3300 /* See if anything that happened changes which eliminations are valid.
3301 For example, on the Sparc, whether or not the frame pointer can
3302 be eliminated can depend on what registers have been used. We need
3303 not check some conditions again (such as flag_omit_frame_pointer)
3304 since they can't have changed. */
3307 update_eliminables (pset)
3310 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3311 int previous_frame_pointer_needed = frame_pointer_needed;
3313 struct elim_table *ep;
3315 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3316 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3317 #ifdef ELIMINABLE_REGS
3318 || ! CAN_ELIMINATE (ep->from, ep->to)
3321 ep->can_eliminate = 0;
3323 /* Look for the case where we have discovered that we can't replace
3324 register A with register B and that means that we will now be
3325 trying to replace register A with register C. This means we can
3326 no longer replace register C with register B and we need to disable
3327 such an elimination, if it exists. This occurs often with A == ap,
3328 B == sp, and C == fp. */
3330 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3332 struct elim_table *op;
3333 register int new_to = -1;
3335 if (! ep->can_eliminate && ep->can_eliminate_previous)
3337 /* Find the current elimination for ep->from, if there is a
3339 for (op = reg_eliminate;
3340 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3341 if (op->from == ep->from && op->can_eliminate)
3347 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3349 for (op = reg_eliminate;
3350 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3351 if (op->from == new_to && op->to == ep->to)
3352 op->can_eliminate = 0;
3356 /* See if any registers that we thought we could eliminate the previous
3357 time are no longer eliminable. If so, something has changed and we
3358 must spill the register. Also, recompute the number of eliminable
3359 registers and see if the frame pointer is needed; it is if there is
3360 no elimination of the frame pointer that we can perform. */
3362 frame_pointer_needed = 1;
3363 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3365 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3366 && ep->to != HARD_FRAME_POINTER_REGNUM)
3367 frame_pointer_needed = 0;
3369 if (! ep->can_eliminate && ep->can_eliminate_previous)
3371 ep->can_eliminate_previous = 0;
3372 SET_HARD_REG_BIT (*pset, ep->from);
3377 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3378 /* If we didn't need a frame pointer last time, but we do now, spill
3379 the hard frame pointer. */
3380 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3381 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3385 /* Initialize the table of registers to eliminate. */
3390 struct elim_table *ep;
3391 #ifdef ELIMINABLE_REGS
3392 struct elim_table_1 *ep1;
3396 reg_eliminate = (struct elim_table *)
3397 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3399 /* Does this function require a frame pointer? */
3401 frame_pointer_needed = (! flag_omit_frame_pointer
3402 #ifdef EXIT_IGNORE_STACK
3403 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3404 and restore sp for alloca. So we can't eliminate
3405 the frame pointer in that case. At some point,
3406 we should improve this by emitting the
3407 sp-adjusting insns for this case. */
3408 || (current_function_calls_alloca
3409 && EXIT_IGNORE_STACK)
3411 || FRAME_POINTER_REQUIRED);
3415 #ifdef ELIMINABLE_REGS
3416 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3417 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3419 ep->from = ep1->from;
3421 ep->can_eliminate = ep->can_eliminate_previous
3422 = (CAN_ELIMINATE (ep->from, ep->to)
3423 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3426 reg_eliminate[0].from = reg_eliminate_1[0].from;
3427 reg_eliminate[0].to = reg_eliminate_1[0].to;
3428 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3429 = ! frame_pointer_needed;
3432 /* Count the number of eliminable registers and build the FROM and TO
3433 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3434 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3435 We depend on this. */
3436 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3438 num_eliminable += ep->can_eliminate;
3439 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3440 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3444 /* Kick all pseudos out of hard register REGNO.
3446 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3447 because we found we can't eliminate some register. In the case, no pseudos
3448 are allowed to be in the register, even if they are only in a block that
3449 doesn't require spill registers, unlike the case when we are spilling this
3450 hard reg to produce another spill register.
3452 Return nonzero if any pseudos needed to be kicked out. */
3455 spill_hard_reg (regno, cant_eliminate)
3463 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3464 regs_ever_live[regno] = 1;
3467 /* Spill every pseudo reg that was allocated to this reg
3468 or to something that overlaps this reg. */
3470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3471 if (reg_renumber[i] >= 0
3472 && (unsigned int) reg_renumber[i] <= regno
3473 && ((unsigned int) reg_renumber[i]
3474 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3475 PSEUDO_REGNO_MODE (i))
3477 SET_REGNO_REG_SET (&spilled_pseudos, i);
3480 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3481 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3484 ior_hard_reg_set (set1, set2)
3485 HARD_REG_SET *set1, *set2;
3487 IOR_HARD_REG_SET (*set1, *set2);
3490 /* After find_reload_regs has been run for all insn that need reloads,
3491 and/or spill_hard_regs was called, this function is used to actually
3492 spill pseudo registers and try to reallocate them. It also sets up the
3493 spill_regs array for use by choose_reload_regs. */
3496 finish_spills (global)
3499 struct insn_chain *chain;
3500 int something_changed = 0;
3503 /* Build the spill_regs array for the function. */
3504 /* If there are some registers still to eliminate and one of the spill regs
3505 wasn't ever used before, additional stack space may have to be
3506 allocated to store this register. Thus, we may have changed the offset
3507 between the stack and frame pointers, so mark that something has changed.
3509 One might think that we need only set VAL to 1 if this is a call-used
3510 register. However, the set of registers that must be saved by the
3511 prologue is not identical to the call-used set. For example, the
3512 register used by the call insn for the return PC is a call-used register,
3513 but must be saved by the prologue. */
3516 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3517 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3519 spill_reg_order[i] = n_spills;
3520 spill_regs[n_spills++] = i;
3521 if (num_eliminable && ! regs_ever_live[i])
3522 something_changed = 1;
3523 regs_ever_live[i] = 1;
3526 spill_reg_order[i] = -1;
3528 EXECUTE_IF_SET_IN_REG_SET
3529 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3531 /* Record the current hard register the pseudo is allocated to in
3532 pseudo_previous_regs so we avoid reallocating it to the same
3533 hard reg in a later pass. */
3534 if (reg_renumber[i] < 0)
3537 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3538 /* Mark it as no longer having a hard register home. */
3539 reg_renumber[i] = -1;
3540 /* We will need to scan everything again. */
3541 something_changed = 1;
3544 /* Retry global register allocation if possible. */
3547 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3548 /* For every insn that needs reloads, set the registers used as spill
3549 regs in pseudo_forbidden_regs for every pseudo live across the
3551 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3553 EXECUTE_IF_SET_IN_REG_SET
3554 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3556 ior_hard_reg_set (pseudo_forbidden_regs + i,
3557 &chain->used_spill_regs);
3559 EXECUTE_IF_SET_IN_REG_SET
3560 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3562 ior_hard_reg_set (pseudo_forbidden_regs + i,
3563 &chain->used_spill_regs);
3567 /* Retry allocating the spilled pseudos. For each reg, merge the
3568 various reg sets that indicate which hard regs can't be used,
3569 and call retry_global_alloc.
3570 We change spill_pseudos here to only contain pseudos that did not
3571 get a new hard register. */
3572 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3573 if (reg_old_renumber[i] != reg_renumber[i])
3575 HARD_REG_SET forbidden;
3576 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3577 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3578 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3579 retry_global_alloc (i, forbidden);
3580 if (reg_renumber[i] >= 0)
3581 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3585 /* Fix up the register information in the insn chain.
3586 This involves deleting those of the spilled pseudos which did not get
3587 a new hard register home from the live_{before,after} sets. */
3588 for (chain = reload_insn_chain; chain; chain = chain->next)
3590 HARD_REG_SET used_by_pseudos;
3591 HARD_REG_SET used_by_pseudos2;
3593 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3594 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3596 /* Mark any unallocated hard regs as available for spills. That
3597 makes inheritance work somewhat better. */
3598 if (chain->need_reload)
3600 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3601 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3602 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3604 /* Save the old value for the sanity test below. */
3605 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3607 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3608 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3609 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3610 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3612 /* Make sure we only enlarge the set. */
3613 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3619 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3620 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3622 int regno = reg_renumber[i];
3623 if (reg_old_renumber[i] == regno)
3626 alter_reg (i, reg_old_renumber[i]);
3627 reg_old_renumber[i] = regno;
3631 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3633 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3634 i, reg_renumber[i]);
3638 return something_changed;
3641 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3642 Also mark any hard registers used to store user variables as
3643 forbidden from being used for spill registers. */
3646 scan_paradoxical_subregs (x)
3650 register const char *fmt;
3651 register enum rtx_code code = GET_CODE (x);
3657 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3658 && REG_USERVAR_P (x))
3659 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3675 if (GET_CODE (SUBREG_REG (x)) == REG
3676 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3677 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3678 = GET_MODE_SIZE (GET_MODE (x));
3685 fmt = GET_RTX_FORMAT (code);
3686 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3689 scan_paradoxical_subregs (XEXP (x, i));
3690 else if (fmt[i] == 'E')
3693 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3694 scan_paradoxical_subregs (XVECEXP (x, i, j));
3699 /* Reload pseudo-registers into hard regs around each insn as needed.
3700 Additional register load insns are output before the insn that needs it
3701 and perhaps store insns after insns that modify the reloaded pseudo reg.
3703 reg_last_reload_reg and reg_reloaded_contents keep track of
3704 which registers are already available in reload registers.
3705 We update these for the reloads that we perform,
3706 as the insns are scanned. */
3709 reload_as_needed (live_known)
3712 struct insn_chain *chain;
3713 #if defined (AUTO_INC_DEC)
3718 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3719 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3720 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3721 reg_has_output_reload = (char *) xmalloc (max_regno);
3722 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3724 set_initial_elim_offsets ();
3726 for (chain = reload_insn_chain; chain; chain = chain->next)
3729 rtx insn = chain->insn;
3730 rtx old_next = NEXT_INSN (insn);
3732 /* If we pass a label, copy the offsets from the label information
3733 into the current offsets of each elimination. */
3734 if (GET_CODE (insn) == CODE_LABEL)
3735 set_offsets_for_label (insn);
3737 else if (INSN_P (insn))
3739 rtx oldpat = PATTERN (insn);
3741 /* If this is a USE and CLOBBER of a MEM, ensure that any
3742 references to eliminable registers have been removed. */
3744 if ((GET_CODE (PATTERN (insn)) == USE
3745 || GET_CODE (PATTERN (insn)) == CLOBBER)
3746 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3747 XEXP (XEXP (PATTERN (insn), 0), 0)
3748 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3749 GET_MODE (XEXP (PATTERN (insn), 0)),
3752 /* If we need to do register elimination processing, do so.
3753 This might delete the insn, in which case we are done. */
3754 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3756 eliminate_regs_in_insn (insn, 1);
3757 if (GET_CODE (insn) == NOTE)
3759 update_eliminable_offsets ();
3764 /* If need_elim is nonzero but need_reload is zero, one might think
3765 that we could simply set n_reloads to 0. However, find_reloads
3766 could have done some manipulation of the insn (such as swapping
3767 commutative operands), and these manipulations are lost during
3768 the first pass for every insn that needs register elimination.
3769 So the actions of find_reloads must be redone here. */
3771 if (! chain->need_elim && ! chain->need_reload
3772 && ! chain->need_operand_change)
3774 /* First find the pseudo regs that must be reloaded for this insn.
3775 This info is returned in the tables reload_... (see reload.h).
3776 Also modify the body of INSN by substituting RELOAD
3777 rtx's for those pseudo regs. */
3780 bzero (reg_has_output_reload, max_regno);
3781 CLEAR_HARD_REG_SET (reg_is_output_reload);
3783 find_reloads (insn, 1, spill_indirect_levels, live_known,
3787 if (num_eliminable && chain->need_elim)
3788 update_eliminable_offsets ();
3792 rtx next = NEXT_INSN (insn);
3795 prev = PREV_INSN (insn);
3797 /* Now compute which reload regs to reload them into. Perhaps
3798 reusing reload regs from previous insns, or else output
3799 load insns to reload them. Maybe output store insns too.
3800 Record the choices of reload reg in reload_reg_rtx. */
3801 choose_reload_regs (chain);
3803 /* Merge any reloads that we didn't combine for fear of
3804 increasing the number of spill registers needed but now
3805 discover can be safely merged. */
3806 if (SMALL_REGISTER_CLASSES)
3807 merge_assigned_reloads (insn);
3809 /* Generate the insns to reload operands into or out of
3810 their reload regs. */
3811 emit_reload_insns (chain);
3813 /* Substitute the chosen reload regs from reload_reg_rtx
3814 into the insn's body (or perhaps into the bodies of other
3815 load and store insn that we just made for reloading
3816 and that we moved the structure into). */
3819 /* If this was an ASM, make sure that all the reload insns
3820 we have generated are valid. If not, give an error
3823 if (asm_noperands (PATTERN (insn)) >= 0)
3824 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3825 if (p != insn && INSN_P (p)
3826 && (recog_memoized (p) < 0
3827 || (extract_insn (p), ! constrain_operands (1))))
3829 error_for_asm (insn,
3830 "`asm' operand requires impossible reload");
3832 NOTE_SOURCE_FILE (p) = 0;
3833 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3836 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3837 is no longer validly lying around to save a future reload.
3838 Note that this does not detect pseudos that were reloaded
3839 for this insn in order to be stored in
3840 (obeying register constraints). That is correct; such reload
3841 registers ARE still valid. */
3842 note_stores (oldpat, forget_old_reloads_1, NULL);
3844 /* There may have been CLOBBER insns placed after INSN. So scan
3845 between INSN and NEXT and use them to forget old reloads. */
3846 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3847 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3848 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3851 /* Likewise for regs altered by auto-increment in this insn.
3852 REG_INC notes have been changed by reloading:
3853 find_reloads_address_1 records substitutions for them,
3854 which have been performed by subst_reloads above. */
3855 for (i = n_reloads - 1; i >= 0; i--)
3857 rtx in_reg = rld[i].in_reg;
3860 enum rtx_code code = GET_CODE (in_reg);
3861 /* PRE_INC / PRE_DEC will have the reload register ending up
3862 with the same value as the stack slot, but that doesn't
3863 hold true for POST_INC / POST_DEC. Either we have to
3864 convert the memory access to a true POST_INC / POST_DEC,
3865 or we can't use the reload register for inheritance. */
3866 if ((code == POST_INC || code == POST_DEC)
3867 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3868 REGNO (rld[i].reg_rtx))
3869 /* Make sure it is the inc/dec pseudo, and not
3870 some other (e.g. output operand) pseudo. */
3871 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3872 == REGNO (XEXP (in_reg, 0))))
3875 rtx reload_reg = rld[i].reg_rtx;
3876 enum machine_mode mode = GET_MODE (reload_reg);
3880 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3882 /* We really want to ignore REG_INC notes here, so
3883 use PATTERN (p) as argument to reg_set_p . */
3884 if (reg_set_p (reload_reg, PATTERN (p)))
3886 n = count_occurrences (PATTERN (p), reload_reg, 0);
3891 n = validate_replace_rtx (reload_reg,
3892 gen_rtx (code, mode,
3896 /* We must also verify that the constraints
3897 are met after the replacement. */
3900 n = constrain_operands (1);
3904 /* If the constraints were not met, then
3905 undo the replacement. */
3908 validate_replace_rtx (gen_rtx (code, mode,
3920 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3922 /* Mark this as having an output reload so that the
3923 REG_INC processing code below won't invalidate
3924 the reload for inheritance. */
3925 SET_HARD_REG_BIT (reg_is_output_reload,
3926 REGNO (reload_reg));
3927 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3930 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3933 else if ((code == PRE_INC || code == PRE_DEC)
3934 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3935 REGNO (rld[i].reg_rtx))
3936 /* Make sure it is the inc/dec pseudo, and not
3937 some other (e.g. output operand) pseudo. */
3938 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3939 == REGNO (XEXP (in_reg, 0))))
3941 SET_HARD_REG_BIT (reg_is_output_reload,
3942 REGNO (rld[i].reg_rtx));
3943 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3947 /* If a pseudo that got a hard register is auto-incremented,
3948 we must purge records of copying it into pseudos without
3950 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3951 if (REG_NOTE_KIND (x) == REG_INC)
3953 /* See if this pseudo reg was reloaded in this insn.
3954 If so, its last-reload info is still valid
3955 because it is based on this insn's reload. */
3956 for (i = 0; i < n_reloads; i++)
3957 if (rld[i].out == XEXP (x, 0))
3961 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3965 /* A reload reg's contents are unknown after a label. */
3966 if (GET_CODE (insn) == CODE_LABEL)
3967 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3969 /* Don't assume a reload reg is still good after a call insn
3970 if it is a call-used reg. */
3971 else if (GET_CODE (insn) == CALL_INSN)
3972 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3976 free (reg_last_reload_reg);
3977 free (reg_has_output_reload);
3980 /* Discard all record of any value reloaded from X,
3981 or reloaded in X from someplace else;
3982 unless X is an output reload reg of the current insn.
3984 X may be a hard reg (the reload reg)
3985 or it may be a pseudo reg that was reloaded from. */
3988 forget_old_reloads_1 (x, ignored, data)
3990 rtx ignored ATTRIBUTE_UNUSED;
3991 void *data ATTRIBUTE_UNUSED;
3997 /* note_stores does give us subregs of hard regs. */
3998 while (GET_CODE (x) == SUBREG)
4000 offset += SUBREG_WORD (x);
4004 if (GET_CODE (x) != REG)
4007 regno = REGNO (x) + offset;
4009 if (regno >= FIRST_PSEUDO_REGISTER)
4015 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4016 /* Storing into a spilled-reg invalidates its contents.
4017 This can happen if a block-local pseudo is allocated to that reg
4018 and it wasn't spilled because this block's total need is 0.
4019 Then some insn might have an optional reload and use this reg. */
4020 for (i = 0; i < nr; i++)
4021 /* But don't do this if the reg actually serves as an output
4022 reload reg in the current instruction. */
4024 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4026 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4027 spill_reg_store[regno + i] = 0;
4031 /* Since value of X has changed,
4032 forget any value previously copied from it. */
4035 /* But don't forget a copy if this is the output reload
4036 that establishes the copy's validity. */
4037 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4038 reg_last_reload_reg[regno + nr] = 0;
4041 /* The following HARD_REG_SETs indicate when each hard register is
4042 used for a reload of various parts of the current insn. */
4044 /* If reg is unavailable for all reloads. */
4045 static HARD_REG_SET reload_reg_unavailable;
4046 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4047 static HARD_REG_SET reload_reg_used;
4048 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4049 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4050 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4051 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4052 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4053 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4054 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4055 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4056 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4057 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4058 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4059 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4060 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4061 static HARD_REG_SET reload_reg_used_in_op_addr;
4062 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4063 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4064 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4065 static HARD_REG_SET reload_reg_used_in_insn;
4066 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4067 static HARD_REG_SET reload_reg_used_in_other_addr;
4069 /* If reg is in use as a reload reg for any sort of reload. */
4070 static HARD_REG_SET reload_reg_used_at_all;
4072 /* If reg is use as an inherited reload. We just mark the first register
4074 static HARD_REG_SET reload_reg_used_for_inherit;
4076 /* Records which hard regs are used in any way, either as explicit use or
4077 by being allocated to a pseudo during any point of the current insn. */
4078 static HARD_REG_SET reg_used_in_insn;
4080 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4081 TYPE. MODE is used to indicate how many consecutive regs are
4085 mark_reload_reg_in_use (regno, opnum, type, mode)
4088 enum reload_type type;
4089 enum machine_mode mode;
4091 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4094 for (i = regno; i < nregs + regno; i++)
4099 SET_HARD_REG_BIT (reload_reg_used, i);
4102 case RELOAD_FOR_INPUT_ADDRESS:
4103 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4106 case RELOAD_FOR_INPADDR_ADDRESS:
4107 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4110 case RELOAD_FOR_OUTPUT_ADDRESS:
4111 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4114 case RELOAD_FOR_OUTADDR_ADDRESS:
4115 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4118 case RELOAD_FOR_OPERAND_ADDRESS:
4119 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4122 case RELOAD_FOR_OPADDR_ADDR:
4123 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4126 case RELOAD_FOR_OTHER_ADDRESS:
4127 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4130 case RELOAD_FOR_INPUT:
4131 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4134 case RELOAD_FOR_OUTPUT:
4135 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4138 case RELOAD_FOR_INSN:
4139 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4143 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4147 /* Similarly, but show REGNO is no longer in use for a reload. */
4150 clear_reload_reg_in_use (regno, opnum, type, mode)
4153 enum reload_type type;
4154 enum machine_mode mode;
4156 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4157 unsigned int start_regno, end_regno, r;
4159 /* A complication is that for some reload types, inheritance might
4160 allow multiple reloads of the same types to share a reload register.
4161 We set check_opnum if we have to check only reloads with the same
4162 operand number, and check_any if we have to check all reloads. */
4163 int check_opnum = 0;
4165 HARD_REG_SET *used_in_set;
4170 used_in_set = &reload_reg_used;
4173 case RELOAD_FOR_INPUT_ADDRESS:
4174 used_in_set = &reload_reg_used_in_input_addr[opnum];
4177 case RELOAD_FOR_INPADDR_ADDRESS:
4179 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4182 case RELOAD_FOR_OUTPUT_ADDRESS:
4183 used_in_set = &reload_reg_used_in_output_addr[opnum];
4186 case RELOAD_FOR_OUTADDR_ADDRESS:
4188 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4191 case RELOAD_FOR_OPERAND_ADDRESS:
4192 used_in_set = &reload_reg_used_in_op_addr;
4195 case RELOAD_FOR_OPADDR_ADDR:
4197 used_in_set = &reload_reg_used_in_op_addr_reload;
4200 case RELOAD_FOR_OTHER_ADDRESS:
4201 used_in_set = &reload_reg_used_in_other_addr;
4205 case RELOAD_FOR_INPUT:
4206 used_in_set = &reload_reg_used_in_input[opnum];
4209 case RELOAD_FOR_OUTPUT:
4210 used_in_set = &reload_reg_used_in_output[opnum];
4213 case RELOAD_FOR_INSN:
4214 used_in_set = &reload_reg_used_in_insn;
4219 /* We resolve conflicts with remaining reloads of the same type by
4220 excluding the intervals of of reload registers by them from the
4221 interval of freed reload registers. Since we only keep track of
4222 one set of interval bounds, we might have to exclude somewhat
4223 more then what would be necessary if we used a HARD_REG_SET here.
4224 But this should only happen very infrequently, so there should
4225 be no reason to worry about it. */
4227 start_regno = regno;
4228 end_regno = regno + nregs;
4229 if (check_opnum || check_any)
4231 for (i = n_reloads - 1; i >= 0; i--)
4233 if (rld[i].when_needed == type
4234 && (check_any || rld[i].opnum == opnum)
4237 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4238 unsigned int conflict_end
4240 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4242 /* If there is an overlap with the first to-be-freed register,
4243 adjust the interval start. */
4244 if (conflict_start <= start_regno && conflict_end > start_regno)
4245 start_regno = conflict_end;
4246 /* Otherwise, if there is a conflict with one of the other
4247 to-be-freed registers, adjust the interval end. */
4248 if (conflict_start > start_regno && conflict_start < end_regno)
4249 end_regno = conflict_start;
4254 for (r = start_regno; r < end_regno; r++)
4255 CLEAR_HARD_REG_BIT (*used_in_set, r);
4258 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4259 specified by OPNUM and TYPE. */
4262 reload_reg_free_p (regno, opnum, type)
4265 enum reload_type type;
4269 /* In use for a RELOAD_OTHER means it's not available for anything. */
4270 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4271 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4277 /* In use for anything means we can't use it for RELOAD_OTHER. */
4278 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4279 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4280 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4283 for (i = 0; i < reload_n_operands; i++)
4284 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4285 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4286 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4287 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4288 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4289 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4294 case RELOAD_FOR_INPUT:
4295 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4296 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4299 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4302 /* If it is used for some other input, can't use it. */
4303 for (i = 0; i < reload_n_operands; i++)
4304 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4307 /* If it is used in a later operand's address, can't use it. */
4308 for (i = opnum + 1; i < reload_n_operands; i++)
4309 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4310 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4315 case RELOAD_FOR_INPUT_ADDRESS:
4316 /* Can't use a register if it is used for an input address for this
4317 operand or used as an input in an earlier one. */
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4319 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4322 for (i = 0; i < opnum; i++)
4323 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4328 case RELOAD_FOR_INPADDR_ADDRESS:
4329 /* Can't use a register if it is used for an input address
4330 for this operand or used as an input in an earlier
4332 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4335 for (i = 0; i < opnum; i++)
4336 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4341 case RELOAD_FOR_OUTPUT_ADDRESS:
4342 /* Can't use a register if it is used for an output address for this
4343 operand or used as an output in this or a later operand. */
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4347 for (i = opnum; i < reload_n_operands; i++)
4348 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4353 case RELOAD_FOR_OUTADDR_ADDRESS:
4354 /* Can't use a register if it is used for an output address
4355 for this operand or used as an output in this or a
4357 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4360 for (i = opnum; i < reload_n_operands; i++)
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4366 case RELOAD_FOR_OPERAND_ADDRESS:
4367 for (i = 0; i < reload_n_operands; i++)
4368 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4371 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4372 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4374 case RELOAD_FOR_OPADDR_ADDR:
4375 for (i = 0; i < reload_n_operands; i++)
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4379 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4381 case RELOAD_FOR_OUTPUT:
4382 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4383 outputs, or an operand address for this or an earlier output. */
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4387 for (i = 0; i < reload_n_operands; i++)
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4391 for (i = 0; i <= opnum; i++)
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4398 case RELOAD_FOR_INSN:
4399 for (i = 0; i < reload_n_operands; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4401 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4404 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4405 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4407 case RELOAD_FOR_OTHER_ADDRESS:
4408 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4413 /* Return 1 if the value in reload reg REGNO, as used by a reload
4414 needed for the part of the insn specified by OPNUM and TYPE,
4415 is still available in REGNO at the end of the insn.
4417 We can assume that the reload reg was already tested for availability
4418 at the time it is needed, and we should not check this again,
4419 in case the reg has already been marked in use. */
4422 reload_reg_reaches_end_p (regno, opnum, type)
4425 enum reload_type type;
4432 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4433 its value must reach the end. */
4436 /* If this use is for part of the insn,
4437 its value reaches if no subsequent part uses the same register.
4438 Just like the above function, don't try to do this with lots
4441 case RELOAD_FOR_OTHER_ADDRESS:
4442 /* Here we check for everything else, since these don't conflict
4443 with anything else and everything comes later. */
4445 for (i = 0; i < reload_n_operands; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4447 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4448 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4449 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4450 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4454 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4455 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4456 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4458 case RELOAD_FOR_INPUT_ADDRESS:
4459 case RELOAD_FOR_INPADDR_ADDRESS:
4460 /* Similar, except that we check only for this and subsequent inputs
4461 and the address of only subsequent inputs and we do not need
4462 to check for RELOAD_OTHER objects since they are known not to
4465 for (i = opnum; i < reload_n_operands; i++)
4466 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4469 for (i = opnum + 1; i < reload_n_operands; i++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4471 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4474 for (i = 0; i < reload_n_operands; i++)
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4476 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4477 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4483 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4484 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4486 case RELOAD_FOR_INPUT:
4487 /* Similar to input address, except we start at the next operand for
4488 both input and input address and we do not check for
4489 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4492 for (i = opnum + 1; i < reload_n_operands; i++)
4493 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4494 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4498 /* ... fall through ... */
4500 case RELOAD_FOR_OPERAND_ADDRESS:
4501 /* Check outputs and their addresses. */
4503 for (i = 0; i < reload_n_operands; i++)
4504 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4505 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4506 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4511 case RELOAD_FOR_OPADDR_ADDR:
4512 for (i = 0; i < reload_n_operands; i++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4518 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4519 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4521 case RELOAD_FOR_INSN:
4522 /* These conflict with other outputs with RELOAD_OTHER. So
4523 we need only check for output addresses. */
4527 /* ... fall through ... */
4529 case RELOAD_FOR_OUTPUT:
4530 case RELOAD_FOR_OUTPUT_ADDRESS:
4531 case RELOAD_FOR_OUTADDR_ADDRESS:
4532 /* We already know these can't conflict with a later output. So the
4533 only thing to check are later output addresses. */
4534 for (i = opnum + 1; i < reload_n_operands; i++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4545 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4548 This function uses the same algorithm as reload_reg_free_p above. */
4551 reloads_conflict (r1, r2)
4554 enum reload_type r1_type = rld[r1].when_needed;
4555 enum reload_type r2_type = rld[r2].when_needed;
4556 int r1_opnum = rld[r1].opnum;
4557 int r2_opnum = rld[r2].opnum;
4559 /* RELOAD_OTHER conflicts with everything. */
4560 if (r2_type == RELOAD_OTHER)
4563 /* Otherwise, check conflicts differently for each type. */
4567 case RELOAD_FOR_INPUT:
4568 return (r2_type == RELOAD_FOR_INSN
4569 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4570 || r2_type == RELOAD_FOR_OPADDR_ADDR
4571 || r2_type == RELOAD_FOR_INPUT
4572 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4573 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4574 && r2_opnum > r1_opnum));
4576 case RELOAD_FOR_INPUT_ADDRESS:
4577 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4578 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4580 case RELOAD_FOR_INPADDR_ADDRESS:
4581 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4582 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4584 case RELOAD_FOR_OUTPUT_ADDRESS:
4585 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4586 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4588 case RELOAD_FOR_OUTADDR_ADDRESS:
4589 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4590 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4592 case RELOAD_FOR_OPERAND_ADDRESS:
4593 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4594 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4596 case RELOAD_FOR_OPADDR_ADDR:
4597 return (r2_type == RELOAD_FOR_INPUT
4598 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4600 case RELOAD_FOR_OUTPUT:
4601 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4602 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4603 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4604 && r2_opnum <= r1_opnum));
4606 case RELOAD_FOR_INSN:
4607 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4608 || r2_type == RELOAD_FOR_INSN
4609 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4611 case RELOAD_FOR_OTHER_ADDRESS:
4612 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4622 /* Indexed by reload number, 1 if incoming value
4623 inherited from previous insns. */
4624 char reload_inherited[MAX_RELOADS];
4626 /* For an inherited reload, this is the insn the reload was inherited from,
4627 if we know it. Otherwise, this is 0. */
4628 rtx reload_inheritance_insn[MAX_RELOADS];
4630 /* If non-zero, this is a place to get the value of the reload,
4631 rather than using reload_in. */
4632 rtx reload_override_in[MAX_RELOADS];
4634 /* For each reload, the hard register number of the register used,
4635 or -1 if we did not need a register for this reload. */
4636 int reload_spill_index[MAX_RELOADS];
4638 /* Return 1 if the value in reload reg REGNO, as used by a reload
4639 needed for the part of the insn specified by OPNUM and TYPE,
4640 may be used to load VALUE into it.
4642 Other read-only reloads with the same value do not conflict
4643 unless OUT is non-zero and these other reloads have to live while
4644 output reloads live.
4645 If OUT is CONST0_RTX, this is a special case: it means that the
4646 test should not be for using register REGNO as reload register, but
4647 for copying from register REGNO into the reload register.
4649 RELOADNUM is the number of the reload we want to load this value for;
4650 a reload does not conflict with itself.
4652 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4653 reloads that load an address for the very reload we are considering.
4655 The caller has to make sure that there is no conflict with the return
4658 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4659 ignore_address_reloads)
4662 enum reload_type type;
4665 int ignore_address_reloads;
4668 /* Set if we see an input reload that must not share its reload register
4669 with any new earlyclobber, but might otherwise share the reload
4670 register with an output or input-output reload. */
4671 int check_earlyclobber = 0;
4675 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4678 if (out == const0_rtx)
4684 /* We use some pseudo 'time' value to check if the lifetimes of the
4685 new register use would overlap with the one of a previous reload
4686 that is not read-only or uses a different value.
4687 The 'time' used doesn't have to be linear in any shape or form, just
4689 Some reload types use different 'buckets' for each operand.
4690 So there are MAX_RECOG_OPERANDS different time values for each
4692 We compute TIME1 as the time when the register for the prospective
4693 new reload ceases to be live, and TIME2 for each existing
4694 reload as the time when that the reload register of that reload
4696 Where there is little to be gained by exact lifetime calculations,
4697 we just make conservative assumptions, i.e. a longer lifetime;
4698 this is done in the 'default:' cases. */
4701 case RELOAD_FOR_OTHER_ADDRESS:
4702 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4703 time1 = copy ? 0 : 1;
4706 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4708 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4709 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4710 respectively, to the time values for these, we get distinct time
4711 values. To get distinct time values for each operand, we have to
4712 multiply opnum by at least three. We round that up to four because
4713 multiply by four is often cheaper. */
4714 case RELOAD_FOR_INPADDR_ADDRESS:
4715 time1 = opnum * 4 + 2;
4717 case RELOAD_FOR_INPUT_ADDRESS:
4718 time1 = opnum * 4 + 3;
4720 case RELOAD_FOR_INPUT:
4721 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4722 executes (inclusive). */
4723 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4725 case RELOAD_FOR_OPADDR_ADDR:
4727 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4728 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4730 case RELOAD_FOR_OPERAND_ADDRESS:
4731 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4733 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4735 case RELOAD_FOR_OUTADDR_ADDRESS:
4736 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4738 case RELOAD_FOR_OUTPUT_ADDRESS:
4739 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4742 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4745 for (i = 0; i < n_reloads; i++)
4747 rtx reg = rld[i].reg_rtx;
4748 if (reg && GET_CODE (reg) == REG
4749 && ((unsigned) regno - true_regnum (reg)
4750 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4753 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4754 || rld[i].out || out)
4757 switch (rld[i].when_needed)
4759 case RELOAD_FOR_OTHER_ADDRESS:
4762 case RELOAD_FOR_INPADDR_ADDRESS:
4763 /* find_reloads makes sure that a
4764 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4765 by at most one - the first -
4766 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4767 address reload is inherited, the address address reload
4768 goes away, so we can ignore this conflict. */
4769 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4770 && ignore_address_reloads
4771 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4772 Then the address address is still needed to store
4773 back the new address. */
4774 && ! rld[reloadnum].out)
4776 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4777 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4779 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4780 && ignore_address_reloads
4781 /* Unless we are reloading an auto_inc expression. */
4782 && ! rld[reloadnum].out)
4784 time2 = rld[i].opnum * 4 + 2;
4786 case RELOAD_FOR_INPUT_ADDRESS:
4787 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4788 && ignore_address_reloads
4789 && ! rld[reloadnum].out)
4791 time2 = rld[i].opnum * 4 + 3;
4793 case RELOAD_FOR_INPUT:
4794 time2 = rld[i].opnum * 4 + 4;
4795 check_earlyclobber = 1;
4797 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4798 == MAX_RECOG_OPERAND * 4 */
4799 case RELOAD_FOR_OPADDR_ADDR:
4800 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4801 && ignore_address_reloads
4802 && ! rld[reloadnum].out)
4804 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4806 case RELOAD_FOR_OPERAND_ADDRESS:
4807 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4808 check_earlyclobber = 1;
4810 case RELOAD_FOR_INSN:
4811 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4813 case RELOAD_FOR_OUTPUT:
4814 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4815 instruction is executed. */
4816 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4818 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4819 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4821 case RELOAD_FOR_OUTADDR_ADDRESS:
4822 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4823 && ignore_address_reloads
4824 && ! rld[reloadnum].out)
4826 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4828 case RELOAD_FOR_OUTPUT_ADDRESS:
4829 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4832 /* If there is no conflict in the input part, handle this
4833 like an output reload. */
4834 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4836 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4837 /* Earlyclobbered outputs must conflict with inputs. */
4838 if (earlyclobber_operand_p (rld[i].out))
4839 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4844 /* RELOAD_OTHER might be live beyond instruction execution,
4845 but this is not obvious when we set time2 = 1. So check
4846 here if there might be a problem with the new reload
4847 clobbering the register used by the RELOAD_OTHER. */
4855 && (! rld[i].in || rld[i].out
4856 || ! rtx_equal_p (rld[i].in, value)))
4857 || (out && rld[reloadnum].out_reg
4858 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4864 /* Earlyclobbered outputs must conflict with inputs. */
4865 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4871 /* Give an error message saying we failed to find a reload for INSN,
4872 and clear out reload R. */
4874 failed_reload (insn, r)
4878 if (asm_noperands (PATTERN (insn)) < 0)
4879 /* It's the compiler's fault. */
4880 fatal_insn ("Could not find a spill register", insn);
4882 /* It's the user's fault; the operand's mode and constraint
4883 don't match. Disable this reload so we don't crash in final. */
4884 error_for_asm (insn,
4885 "`asm' operand constraint incompatible with operand size");
4889 rld[r].optional = 1;
4890 rld[r].secondary_p = 1;
4893 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4894 for reload R. If it's valid, get an rtx for it. Return nonzero if
4897 set_reload_reg (i, r)
4901 rtx reg = spill_reg_rtx[i];
4903 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4904 spill_reg_rtx[i] = reg
4905 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4907 regno = true_regnum (reg);
4909 /* Detect when the reload reg can't hold the reload mode.
4910 This used to be one `if', but Sequent compiler can't handle that. */
4911 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4913 enum machine_mode test_mode = VOIDmode;
4915 test_mode = GET_MODE (rld[r].in);
4916 /* If rld[r].in has VOIDmode, it means we will load it
4917 in whatever mode the reload reg has: to wit, rld[r].mode.
4918 We have already tested that for validity. */
4919 /* Aside from that, we need to test that the expressions
4920 to reload from or into have modes which are valid for this
4921 reload register. Otherwise the reload insns would be invalid. */
4922 if (! (rld[r].in != 0 && test_mode != VOIDmode
4923 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4924 if (! (rld[r].out != 0
4925 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4927 /* The reg is OK. */
4930 /* Mark as in use for this insn the reload regs we use
4932 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4933 rld[r].when_needed, rld[r].mode);
4935 rld[r].reg_rtx = reg;
4936 reload_spill_index[r] = spill_regs[i];
4943 /* Find a spill register to use as a reload register for reload R.
4944 LAST_RELOAD is non-zero if this is the last reload for the insn being
4947 Set rld[R].reg_rtx to the register allocated.
4949 We return 1 if successful, or 0 if we couldn't find a spill reg and
4950 we didn't change anything. */
4953 allocate_reload_reg (chain, r, last_reload)
4954 struct insn_chain *chain ATTRIBUTE_UNUSED;
4960 /* If we put this reload ahead, thinking it is a group,
4961 then insist on finding a group. Otherwise we can grab a
4962 reg that some other reload needs.
4963 (That can happen when we have a 68000 DATA_OR_FP_REG
4964 which is a group of data regs or one fp reg.)
4965 We need not be so restrictive if there are no more reloads
4968 ??? Really it would be nicer to have smarter handling
4969 for that kind of reg class, where a problem like this is normal.
4970 Perhaps those classes should be avoided for reloading
4971 by use of more alternatives. */
4973 int force_group = rld[r].nregs > 1 && ! last_reload;
4975 /* If we want a single register and haven't yet found one,
4976 take any reg in the right class and not in use.
4977 If we want a consecutive group, here is where we look for it.
4979 We use two passes so we can first look for reload regs to
4980 reuse, which are already in use for other reloads in this insn,
4981 and only then use additional registers.
4982 I think that maximizing reuse is needed to make sure we don't
4983 run out of reload regs. Suppose we have three reloads, and
4984 reloads A and B can share regs. These need two regs.
4985 Suppose A and B are given different regs.
4986 That leaves none for C. */
4987 for (pass = 0; pass < 2; pass++)
4989 /* I is the index in spill_regs.
4990 We advance it round-robin between insns to use all spill regs
4991 equally, so that inherited reloads have a chance
4992 of leapfrogging each other. */
4996 for (count = 0; count < n_spills; count++)
4998 int class = (int) rld[r].class;
5004 regnum = spill_regs[i];
5006 if ((reload_reg_free_p (regnum, rld[r].opnum,
5009 /* We check reload_reg_used to make sure we
5010 don't clobber the return register. */
5011 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5012 && reload_reg_free_for_value_p (regnum,
5017 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5018 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5019 /* Look first for regs to share, then for unshared. But
5020 don't share regs used for inherited reloads; they are
5021 the ones we want to preserve. */
5023 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5025 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5028 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5029 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5030 (on 68000) got us two FP regs. If NR is 1,
5031 we would reject both of them. */
5034 /* If we need only one reg, we have already won. */
5037 /* But reject a single reg if we demand a group. */
5042 /* Otherwise check that as many consecutive regs as we need
5043 are available here. */
5046 int regno = regnum + nr - 1;
5047 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5048 && spill_reg_order[regno] >= 0
5049 && reload_reg_free_p (regno, rld[r].opnum,
5050 rld[r].when_needed)))
5059 /* If we found something on pass 1, omit pass 2. */
5060 if (count < n_spills)
5064 /* We should have found a spill register by now. */
5065 if (count >= n_spills)
5068 /* I is the index in SPILL_REG_RTX of the reload register we are to
5069 allocate. Get an rtx for it and find its register number. */
5071 return set_reload_reg (i, r);
5074 /* Initialize all the tables needed to allocate reload registers.
5075 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5076 is the array we use to restore the reg_rtx field for every reload. */
5079 choose_reload_regs_init (chain, save_reload_reg_rtx)
5080 struct insn_chain *chain;
5081 rtx *save_reload_reg_rtx;
5085 for (i = 0; i < n_reloads; i++)
5086 rld[i].reg_rtx = save_reload_reg_rtx[i];
5088 bzero (reload_inherited, MAX_RELOADS);
5089 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5090 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5092 CLEAR_HARD_REG_SET (reload_reg_used);
5093 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5094 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5095 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5096 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5097 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5099 CLEAR_HARD_REG_SET (reg_used_in_insn);
5102 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5103 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5104 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5105 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5106 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5107 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5110 for (i = 0; i < reload_n_operands; i++)
5112 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5113 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5114 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5115 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5116 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5117 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5120 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5122 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5124 for (i = 0; i < n_reloads; i++)
5125 /* If we have already decided to use a certain register,
5126 don't use it in another way. */
5128 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5129 rld[i].when_needed, rld[i].mode);
5132 /* Assign hard reg targets for the pseudo-registers we must reload
5133 into hard regs for this insn.
5134 Also output the instructions to copy them in and out of the hard regs.
5136 For machines with register classes, we are responsible for
5137 finding a reload reg in the proper class. */
5140 choose_reload_regs (chain)
5141 struct insn_chain *chain;
5143 rtx insn = chain->insn;
5145 unsigned int max_group_size = 1;
5146 enum reg_class group_class = NO_REGS;
5147 int pass, win, inheritance;
5149 rtx save_reload_reg_rtx[MAX_RELOADS];
5151 /* In order to be certain of getting the registers we need,
5152 we must sort the reloads into order of increasing register class.
5153 Then our grabbing of reload registers will parallel the process
5154 that provided the reload registers.
5156 Also note whether any of the reloads wants a consecutive group of regs.
5157 If so, record the maximum size of the group desired and what
5158 register class contains all the groups needed by this insn. */
5160 for (j = 0; j < n_reloads; j++)
5162 reload_order[j] = j;
5163 reload_spill_index[j] = -1;
5165 if (rld[j].nregs > 1)
5167 max_group_size = MAX (rld[j].nregs, max_group_size);
5169 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5172 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5176 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5178 /* If -O, try first with inheritance, then turning it off.
5179 If not -O, don't do inheritance.
5180 Using inheritance when not optimizing leads to paradoxes
5181 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5182 because one side of the comparison might be inherited. */
5184 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5186 choose_reload_regs_init (chain, save_reload_reg_rtx);
5188 /* Process the reloads in order of preference just found.
5189 Beyond this point, subregs can be found in reload_reg_rtx.
5191 This used to look for an existing reloaded home for all of the
5192 reloads, and only then perform any new reloads. But that could lose
5193 if the reloads were done out of reg-class order because a later
5194 reload with a looser constraint might have an old home in a register
5195 needed by an earlier reload with a tighter constraint.
5197 To solve this, we make two passes over the reloads, in the order
5198 described above. In the first pass we try to inherit a reload
5199 from a previous insn. If there is a later reload that needs a
5200 class that is a proper subset of the class being processed, we must
5201 also allocate a spill register during the first pass.
5203 Then make a second pass over the reloads to allocate any reloads
5204 that haven't been given registers yet. */
5206 for (j = 0; j < n_reloads; j++)
5208 register int r = reload_order[j];
5209 rtx search_equiv = NULL_RTX;
5211 /* Ignore reloads that got marked inoperative. */
5212 if (rld[r].out == 0 && rld[r].in == 0
5213 && ! rld[r].secondary_p)
5216 /* If find_reloads chose to use reload_in or reload_out as a reload
5217 register, we don't need to chose one. Otherwise, try even if it
5218 found one since we might save an insn if we find the value lying
5220 Try also when reload_in is a pseudo without a hard reg. */
5221 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5222 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5223 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5224 && GET_CODE (rld[r].in) != MEM
5225 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5228 #if 0 /* No longer needed for correct operation.
5229 It might give better code, or might not; worth an experiment? */
5230 /* If this is an optional reload, we can't inherit from earlier insns
5231 until we are sure that any non-optional reloads have been allocated.
5232 The following code takes advantage of the fact that optional reloads
5233 are at the end of reload_order. */
5234 if (rld[r].optional != 0)
5235 for (i = 0; i < j; i++)
5236 if ((rld[reload_order[i]].out != 0
5237 || rld[reload_order[i]].in != 0
5238 || rld[reload_order[i]].secondary_p)
5239 && ! rld[reload_order[i]].optional
5240 && rld[reload_order[i]].reg_rtx == 0)
5241 allocate_reload_reg (chain, reload_order[i], 0);
5244 /* First see if this pseudo is already available as reloaded
5245 for a previous insn. We cannot try to inherit for reloads
5246 that are smaller than the maximum number of registers needed
5247 for groups unless the register we would allocate cannot be used
5250 We could check here to see if this is a secondary reload for
5251 an object that is already in a register of the desired class.
5252 This would avoid the need for the secondary reload register.
5253 But this is complex because we can't easily determine what
5254 objects might want to be loaded via this reload. So let a
5255 register be allocated here. In `emit_reload_insns' we suppress
5256 one of the loads in the case described above. */
5261 register int regno = -1;
5262 enum machine_mode mode = VOIDmode;
5266 else if (GET_CODE (rld[r].in) == REG)
5268 regno = REGNO (rld[r].in);
5269 mode = GET_MODE (rld[r].in);
5271 else if (GET_CODE (rld[r].in_reg) == REG)
5273 regno = REGNO (rld[r].in_reg);
5274 mode = GET_MODE (rld[r].in_reg);
5276 else if (GET_CODE (rld[r].in_reg) == SUBREG
5277 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5279 word = SUBREG_WORD (rld[r].in_reg);
5280 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5281 if (regno < FIRST_PSEUDO_REGISTER)
5283 mode = GET_MODE (rld[r].in_reg);
5286 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5287 || GET_CODE (rld[r].in_reg) == PRE_DEC
5288 || GET_CODE (rld[r].in_reg) == POST_INC
5289 || GET_CODE (rld[r].in_reg) == POST_DEC)
5290 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5292 regno = REGNO (XEXP (rld[r].in_reg, 0));
5293 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5294 rld[r].out = rld[r].in;
5298 /* This won't work, since REGNO can be a pseudo reg number.
5299 Also, it takes much more hair to keep track of all the things
5300 that can invalidate an inherited reload of part of a pseudoreg. */
5301 else if (GET_CODE (rld[r].in) == SUBREG
5302 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5303 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5306 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5308 enum reg_class class = rld[r].class, last_class;
5309 rtx last_reg = reg_last_reload_reg[regno];
5310 enum machine_mode need_mode;
5312 i = REGNO (last_reg) + word;
5313 last_class = REGNO_REG_CLASS (i);
5319 = smallest_mode_for_size (GET_MODE_SIZE (mode)
5320 + word * UNITS_PER_WORD,
5321 GET_MODE_CLASS (mode));
5324 #ifdef CLASS_CANNOT_CHANGE_MODE
5326 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5327 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5329 : (GET_MODE_SIZE (GET_MODE (last_reg))
5330 >= GET_MODE_SIZE (need_mode)))
5332 (GET_MODE_SIZE (GET_MODE (last_reg))
5333 >= GET_MODE_SIZE (need_mode))
5335 && reg_reloaded_contents[i] == regno
5336 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5337 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5338 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5339 /* Even if we can't use this register as a reload
5340 register, we might use it for reload_override_in,
5341 if copying it to the desired class is cheap
5343 || ((REGISTER_MOVE_COST (last_class, class)
5344 < MEMORY_MOVE_COST (mode, class, 1))
5345 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5346 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5350 #ifdef SECONDARY_MEMORY_NEEDED
5351 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5356 && (rld[r].nregs == max_group_size
5357 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5359 && reload_reg_free_for_value_p (i, rld[r].opnum,
5364 /* If a group is needed, verify that all the subsequent
5365 registers still have their values intact. */
5366 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5369 for (k = 1; k < nr; k++)
5370 if (reg_reloaded_contents[i + k] != regno
5371 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5378 last_reg = (GET_MODE (last_reg) == mode
5379 ? last_reg : gen_rtx_REG (mode, i));
5381 /* We found a register that contains the
5382 value we need. If this register is the
5383 same as an `earlyclobber' operand of the
5384 current insn, just mark it as a place to
5385 reload from since we can't use it as the
5386 reload register itself. */
5388 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5389 if (reg_overlap_mentioned_for_reload_p
5390 (reg_last_reload_reg[regno],
5391 reload_earlyclobbers[i1]))
5394 if (i1 != n_earlyclobbers
5395 || ! (reload_reg_free_for_value_p
5396 (i, rld[r].opnum, rld[r].when_needed,
5397 rld[r].in, rld[r].out, r, 1))
5398 /* Don't use it if we'd clobber a pseudo reg. */
5399 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5401 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5402 /* Don't clobber the frame pointer. */
5403 || (i == HARD_FRAME_POINTER_REGNUM
5405 /* Don't really use the inherited spill reg
5406 if we need it wider than we've got it. */
5407 || (GET_MODE_SIZE (rld[r].mode)
5408 > GET_MODE_SIZE (mode))
5409 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5412 /* If find_reloads chose reload_out as reload
5413 register, stay with it - that leaves the
5414 inherited register for subsequent reloads. */
5415 || (rld[r].out && rld[r].reg_rtx
5416 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5418 reload_override_in[r] = last_reg;
5419 reload_inheritance_insn[r]
5420 = reg_reloaded_insn[i];
5425 /* We can use this as a reload reg. */
5426 /* Mark the register as in use for this part of
5428 mark_reload_reg_in_use (i,
5432 rld[r].reg_rtx = last_reg;
5433 reload_inherited[r] = 1;
5434 reload_inheritance_insn[r]
5435 = reg_reloaded_insn[i];
5436 reload_spill_index[r] = i;
5437 for (k = 0; k < nr; k++)
5438 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5446 /* Here's another way to see if the value is already lying around. */
5449 && ! reload_inherited[r]
5451 && (CONSTANT_P (rld[r].in)
5452 || GET_CODE (rld[r].in) == PLUS
5453 || GET_CODE (rld[r].in) == REG
5454 || GET_CODE (rld[r].in) == MEM)
5455 && (rld[r].nregs == max_group_size
5456 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5457 search_equiv = rld[r].in;
5458 /* If this is an output reload from a simple move insn, look
5459 if an equivalence for the input is available. */
5460 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5462 rtx set = single_set (insn);
5465 && rtx_equal_p (rld[r].out, SET_DEST (set))
5466 && CONSTANT_P (SET_SRC (set)))
5467 search_equiv = SET_SRC (set);
5473 = find_equiv_reg (search_equiv, insn, rld[r].class,
5474 -1, NULL_PTR, 0, rld[r].mode);
5479 if (GET_CODE (equiv) == REG)
5480 regno = REGNO (equiv);
5481 else if (GET_CODE (equiv) == SUBREG)
5483 /* This must be a SUBREG of a hard register.
5484 Make a new REG since this might be used in an
5485 address and not all machines support SUBREGs
5487 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5488 equiv = gen_rtx_REG (rld[r].mode, regno);
5494 /* If we found a spill reg, reject it unless it is free
5495 and of the desired class. */
5497 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5498 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5502 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5506 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5509 /* We found a register that contains the value we need.
5510 If this register is the same as an `earlyclobber' operand
5511 of the current insn, just mark it as a place to reload from
5512 since we can't use it as the reload register itself. */
5515 for (i = 0; i < n_earlyclobbers; i++)
5516 if (reg_overlap_mentioned_for_reload_p (equiv,
5517 reload_earlyclobbers[i]))
5519 reload_override_in[r] = equiv;
5524 /* If the equiv register we have found is explicitly clobbered
5525 in the current insn, it depends on the reload type if we
5526 can use it, use it for reload_override_in, or not at all.
5527 In particular, we then can't use EQUIV for a
5528 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5530 if (equiv != 0 && regno_clobbered_p (regno, insn, rld[r].mode))
5532 switch (rld[r].when_needed)
5534 case RELOAD_FOR_OTHER_ADDRESS:
5535 case RELOAD_FOR_INPADDR_ADDRESS:
5536 case RELOAD_FOR_INPUT_ADDRESS:
5537 case RELOAD_FOR_OPADDR_ADDR:
5540 case RELOAD_FOR_INPUT:
5541 case RELOAD_FOR_OPERAND_ADDRESS:
5542 reload_override_in[r] = equiv;
5550 /* If we found an equivalent reg, say no code need be generated
5551 to load it, and use it as our reload reg. */
5552 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5554 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5556 rld[r].reg_rtx = equiv;
5557 reload_inherited[r] = 1;
5559 /* If reg_reloaded_valid is not set for this register,
5560 there might be a stale spill_reg_store lying around.
5561 We must clear it, since otherwise emit_reload_insns
5562 might delete the store. */
5563 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5564 spill_reg_store[regno] = NULL_RTX;
5565 /* If any of the hard registers in EQUIV are spill
5566 registers, mark them as in use for this insn. */
5567 for (k = 0; k < nr; k++)
5569 i = spill_reg_order[regno + k];
5572 mark_reload_reg_in_use (regno, rld[r].opnum,
5575 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5582 /* If we found a register to use already, or if this is an optional
5583 reload, we are done. */
5584 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5588 /* No longer needed for correct operation. Might or might
5589 not give better code on the average. Want to experiment? */
5591 /* See if there is a later reload that has a class different from our
5592 class that intersects our class or that requires less register
5593 than our reload. If so, we must allocate a register to this
5594 reload now, since that reload might inherit a previous reload
5595 and take the only available register in our class. Don't do this
5596 for optional reloads since they will force all previous reloads
5597 to be allocated. Also don't do this for reloads that have been
5600 for (i = j + 1; i < n_reloads; i++)
5602 int s = reload_order[i];
5604 if ((rld[s].in == 0 && rld[s].out == 0
5605 && ! rld[s].secondary_p)
5609 if ((rld[s].class != rld[r].class
5610 && reg_classes_intersect_p (rld[r].class,
5612 || rld[s].nregs < rld[r].nregs)
5619 allocate_reload_reg (chain, r, j == n_reloads - 1);
5623 /* Now allocate reload registers for anything non-optional that
5624 didn't get one yet. */
5625 for (j = 0; j < n_reloads; j++)
5627 register int r = reload_order[j];
5629 /* Ignore reloads that got marked inoperative. */
5630 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5633 /* Skip reloads that already have a register allocated or are
5635 if (rld[r].reg_rtx != 0 || rld[r].optional)
5638 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5642 /* If that loop got all the way, we have won. */
5649 /* Loop around and try without any inheritance. */
5654 /* First undo everything done by the failed attempt
5655 to allocate with inheritance. */
5656 choose_reload_regs_init (chain, save_reload_reg_rtx);
5658 /* Some sanity tests to verify that the reloads found in the first
5659 pass are identical to the ones we have now. */
5660 if (chain->n_reloads != n_reloads)
5663 for (i = 0; i < n_reloads; i++)
5665 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5667 if (chain->rld[i].when_needed != rld[i].when_needed)
5669 for (j = 0; j < n_spills; j++)
5670 if (spill_regs[j] == chain->rld[i].regno)
5671 if (! set_reload_reg (j, i))
5672 failed_reload (chain->insn, i);
5676 /* If we thought we could inherit a reload, because it seemed that
5677 nothing else wanted the same reload register earlier in the insn,
5678 verify that assumption, now that all reloads have been assigned.
5679 Likewise for reloads where reload_override_in has been set. */
5681 /* If doing expensive optimizations, do one preliminary pass that doesn't
5682 cancel any inheritance, but removes reloads that have been needed only
5683 for reloads that we know can be inherited. */
5684 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5686 for (j = 0; j < n_reloads; j++)
5688 register int r = reload_order[j];
5690 if (reload_inherited[r] && rld[r].reg_rtx)
5691 check_reg = rld[r].reg_rtx;
5692 else if (reload_override_in[r]
5693 && (GET_CODE (reload_override_in[r]) == REG
5694 || GET_CODE (reload_override_in[r]) == SUBREG))
5695 check_reg = reload_override_in[r];
5698 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5702 (reload_inherited[r]
5703 ? rld[r].out : const0_rtx),
5708 reload_inherited[r] = 0;
5709 reload_override_in[r] = 0;
5711 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5712 reload_override_in, then we do not need its related
5713 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5714 likewise for other reload types.
5715 We handle this by removing a reload when its only replacement
5716 is mentioned in reload_in of the reload we are going to inherit.
5717 A special case are auto_inc expressions; even if the input is
5718 inherited, we still need the address for the output. We can
5719 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5720 If we suceeded removing some reload and we are doing a preliminary
5721 pass just to remove such reloads, make another pass, since the
5722 removal of one reload might allow us to inherit another one. */
5724 && rld[r].out != rld[r].in
5725 && remove_address_replacements (rld[r].in) && pass)
5730 /* Now that reload_override_in is known valid,
5731 actually override reload_in. */
5732 for (j = 0; j < n_reloads; j++)
5733 if (reload_override_in[j])
5734 rld[j].in = reload_override_in[j];
5736 /* If this reload won't be done because it has been cancelled or is
5737 optional and not inherited, clear reload_reg_rtx so other
5738 routines (such as subst_reloads) don't get confused. */
5739 for (j = 0; j < n_reloads; j++)
5740 if (rld[j].reg_rtx != 0
5741 && ((rld[j].optional && ! reload_inherited[j])
5742 || (rld[j].in == 0 && rld[j].out == 0
5743 && ! rld[j].secondary_p)))
5745 int regno = true_regnum (rld[j].reg_rtx);
5747 if (spill_reg_order[regno] >= 0)
5748 clear_reload_reg_in_use (regno, rld[j].opnum,
5749 rld[j].when_needed, rld[j].mode);
5751 reload_spill_index[j] = -1;
5754 /* Record which pseudos and which spill regs have output reloads. */
5755 for (j = 0; j < n_reloads; j++)
5757 register int r = reload_order[j];
5759 i = reload_spill_index[r];
5761 /* I is nonneg if this reload uses a register.
5762 If rld[r].reg_rtx is 0, this is an optional reload
5763 that we opted to ignore. */
5764 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5765 && rld[r].reg_rtx != 0)
5767 register int nregno = REGNO (rld[r].out_reg);
5770 if (nregno < FIRST_PSEUDO_REGISTER)
5771 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5774 reg_has_output_reload[nregno + nr] = 1;
5778 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5780 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5783 if (rld[r].when_needed != RELOAD_OTHER
5784 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5785 && rld[r].when_needed != RELOAD_FOR_INSN)
5791 /* Deallocate the reload register for reload R. This is called from
5792 remove_address_replacements. */
5795 deallocate_reload_reg (r)
5800 if (! rld[r].reg_rtx)
5802 regno = true_regnum (rld[r].reg_rtx);
5804 if (spill_reg_order[regno] >= 0)
5805 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5807 reload_spill_index[r] = -1;
5810 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5811 reloads of the same item for fear that we might not have enough reload
5812 registers. However, normally they will get the same reload register
5813 and hence actually need not be loaded twice.
5815 Here we check for the most common case of this phenomenon: when we have
5816 a number of reloads for the same object, each of which were allocated
5817 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5818 reload, and is not modified in the insn itself. If we find such,
5819 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5820 This will not increase the number of spill registers needed and will
5821 prevent redundant code. */
5824 merge_assigned_reloads (insn)
5829 /* Scan all the reloads looking for ones that only load values and
5830 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5831 assigned and not modified by INSN. */
5833 for (i = 0; i < n_reloads; i++)
5835 int conflicting_input = 0;
5836 int max_input_address_opnum = -1;
5837 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5839 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5840 || rld[i].out != 0 || rld[i].reg_rtx == 0
5841 || reg_set_p (rld[i].reg_rtx, insn))
5844 /* Look at all other reloads. Ensure that the only use of this
5845 reload_reg_rtx is in a reload that just loads the same value
5846 as we do. Note that any secondary reloads must be of the identical
5847 class since the values, modes, and result registers are the
5848 same, so we need not do anything with any secondary reloads. */
5850 for (j = 0; j < n_reloads; j++)
5852 if (i == j || rld[j].reg_rtx == 0
5853 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5857 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5858 && rld[j].opnum > max_input_address_opnum)
5859 max_input_address_opnum = rld[j].opnum;
5861 /* If the reload regs aren't exactly the same (e.g, different modes)
5862 or if the values are different, we can't merge this reload.
5863 But if it is an input reload, we might still merge
5864 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5866 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5867 || rld[j].out != 0 || rld[j].in == 0
5868 || ! rtx_equal_p (rld[i].in, rld[j].in))
5870 if (rld[j].when_needed != RELOAD_FOR_INPUT
5871 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5872 || rld[i].opnum > rld[j].opnum)
5873 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5875 conflicting_input = 1;
5876 if (min_conflicting_input_opnum > rld[j].opnum)
5877 min_conflicting_input_opnum = rld[j].opnum;
5881 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5882 we, in fact, found any matching reloads. */
5885 && max_input_address_opnum <= min_conflicting_input_opnum)
5887 for (j = 0; j < n_reloads; j++)
5888 if (i != j && rld[j].reg_rtx != 0
5889 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5890 && (! conflicting_input
5891 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5892 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5894 rld[i].when_needed = RELOAD_OTHER;
5896 reload_spill_index[j] = -1;
5897 transfer_replacements (i, j);
5900 /* If this is now RELOAD_OTHER, look for any reloads that load
5901 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5902 if they were for inputs, RELOAD_OTHER for outputs. Note that
5903 this test is equivalent to looking for reloads for this operand
5906 if (rld[i].when_needed == RELOAD_OTHER)
5907 for (j = 0; j < n_reloads; j++)
5909 && rld[i].when_needed != RELOAD_OTHER
5910 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5913 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5914 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5915 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5920 /* These arrays are filled by emit_reload_insns and its subroutines. */
5921 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5922 static rtx other_input_address_reload_insns = 0;
5923 static rtx other_input_reload_insns = 0;
5924 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5925 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5926 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5927 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5928 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5929 static rtx operand_reload_insns = 0;
5930 static rtx other_operand_reload_insns = 0;
5931 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5933 /* Values to be put in spill_reg_store are put here first. */
5934 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5935 static HARD_REG_SET reg_reloaded_died;
5937 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5938 has the number J. OLD contains the value to be used as input. */
5941 emit_input_reload_insns (chain, rl, old, j)
5942 struct insn_chain *chain;
5947 rtx insn = chain->insn;
5948 register rtx reloadreg = rl->reg_rtx;
5949 rtx oldequiv_reg = 0;
5952 enum machine_mode mode;
5955 /* Determine the mode to reload in.
5956 This is very tricky because we have three to choose from.
5957 There is the mode the insn operand wants (rl->inmode).
5958 There is the mode of the reload register RELOADREG.
5959 There is the intrinsic mode of the operand, which we could find
5960 by stripping some SUBREGs.
5961 It turns out that RELOADREG's mode is irrelevant:
5962 we can change that arbitrarily.
5964 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5965 then the reload reg may not support QImode moves, so use SImode.
5966 If foo is in memory due to spilling a pseudo reg, this is safe,
5967 because the QImode value is in the least significant part of a
5968 slot big enough for a SImode. If foo is some other sort of
5969 memory reference, then it is impossible to reload this case,
5970 so previous passes had better make sure this never happens.
5972 Then consider a one-word union which has SImode and one of its
5973 members is a float, being fetched as (SUBREG:SF union:SI).
5974 We must fetch that as SFmode because we could be loading into
5975 a float-only register. In this case OLD's mode is correct.
5977 Consider an immediate integer: it has VOIDmode. Here we need
5978 to get a mode from something else.
5980 In some cases, there is a fourth mode, the operand's
5981 containing mode. If the insn specifies a containing mode for
5982 this operand, it overrides all others.
5984 I am not sure whether the algorithm here is always right,
5985 but it does the right things in those cases. */
5987 mode = GET_MODE (old);
5988 if (mode == VOIDmode)
5991 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5992 /* If we need a secondary register for this operation, see if
5993 the value is already in a register in that class. Don't
5994 do this if the secondary register will be used as a scratch
5997 if (rl->secondary_in_reload >= 0
5998 && rl->secondary_in_icode == CODE_FOR_nothing
6001 = find_equiv_reg (old, insn,
6002 rld[rl->secondary_in_reload].class,
6003 -1, NULL_PTR, 0, mode);
6006 /* If reloading from memory, see if there is a register
6007 that already holds the same value. If so, reload from there.
6008 We can pass 0 as the reload_reg_p argument because
6009 any other reload has either already been emitted,
6010 in which case find_equiv_reg will see the reload-insn,
6011 or has yet to be emitted, in which case it doesn't matter
6012 because we will use this equiv reg right away. */
6014 if (oldequiv == 0 && optimize
6015 && (GET_CODE (old) == MEM
6016 || (GET_CODE (old) == REG
6017 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6018 && reg_renumber[REGNO (old)] < 0)))
6019 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6020 -1, NULL_PTR, 0, mode);
6024 unsigned int regno = true_regnum (oldequiv);
6026 /* Don't use OLDEQUIV if any other reload changes it at an
6027 earlier stage of this insn or at this stage. */
6028 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6030 rl->in, const0_rtx, j,
6034 /* If it is no cheaper to copy from OLDEQUIV into the
6035 reload register than it would be to move from memory,
6036 don't use it. Likewise, if we need a secondary register
6040 && ((REGNO_REG_CLASS (regno) != rl->class
6041 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6043 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6044 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6045 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6049 #ifdef SECONDARY_MEMORY_NEEDED
6050 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6058 /* delete_output_reload is only invoked properly if old contains
6059 the original pseudo register. Since this is replaced with a
6060 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6061 find the pseudo in RELOAD_IN_REG. */
6063 && reload_override_in[j]
6064 && GET_CODE (rl->in_reg) == REG)
6071 else if (GET_CODE (oldequiv) == REG)
6072 oldequiv_reg = oldequiv;
6073 else if (GET_CODE (oldequiv) == SUBREG)
6074 oldequiv_reg = SUBREG_REG (oldequiv);
6076 /* If we are reloading from a register that was recently stored in
6077 with an output-reload, see if we can prove there was
6078 actually no need to store the old value in it. */
6080 if (optimize && GET_CODE (oldequiv) == REG
6081 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6082 && spill_reg_store[REGNO (oldequiv)]
6083 && GET_CODE (old) == REG
6084 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6085 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6087 delete_output_reload (insn, j, REGNO (oldequiv));
6089 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6090 then load RELOADREG from OLDEQUIV. Note that we cannot use
6091 gen_lowpart_common since it can do the wrong thing when
6092 RELOADREG has a multi-word mode. Note that RELOADREG
6093 must always be a REG here. */
6095 if (GET_MODE (reloadreg) != mode)
6096 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6097 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6098 oldequiv = SUBREG_REG (oldequiv);
6099 if (GET_MODE (oldequiv) != VOIDmode
6100 && mode != GET_MODE (oldequiv))
6101 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6103 /* Switch to the right place to emit the reload insns. */
6104 switch (rl->when_needed)
6107 where = &other_input_reload_insns;
6109 case RELOAD_FOR_INPUT:
6110 where = &input_reload_insns[rl->opnum];
6112 case RELOAD_FOR_INPUT_ADDRESS:
6113 where = &input_address_reload_insns[rl->opnum];
6115 case RELOAD_FOR_INPADDR_ADDRESS:
6116 where = &inpaddr_address_reload_insns[rl->opnum];
6118 case RELOAD_FOR_OUTPUT_ADDRESS:
6119 where = &output_address_reload_insns[rl->opnum];
6121 case RELOAD_FOR_OUTADDR_ADDRESS:
6122 where = &outaddr_address_reload_insns[rl->opnum];
6124 case RELOAD_FOR_OPERAND_ADDRESS:
6125 where = &operand_reload_insns;
6127 case RELOAD_FOR_OPADDR_ADDR:
6128 where = &other_operand_reload_insns;
6130 case RELOAD_FOR_OTHER_ADDRESS:
6131 where = &other_input_address_reload_insns;
6137 push_to_sequence (*where);
6139 /* Auto-increment addresses must be reloaded in a special way. */
6140 if (rl->out && ! rl->out_reg)
6142 /* We are not going to bother supporting the case where a
6143 incremented register can't be copied directly from
6144 OLDEQUIV since this seems highly unlikely. */
6145 if (rl->secondary_in_reload >= 0)
6148 if (reload_inherited[j])
6149 oldequiv = reloadreg;
6151 old = XEXP (rl->in_reg, 0);
6153 if (optimize && GET_CODE (oldequiv) == REG
6154 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6155 && spill_reg_store[REGNO (oldequiv)]
6156 && GET_CODE (old) == REG
6157 && (dead_or_set_p (insn,
6158 spill_reg_stored_to[REGNO (oldequiv)])
6159 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6161 delete_output_reload (insn, j, REGNO (oldequiv));
6163 /* Prevent normal processing of this reload. */
6165 /* Output a special code sequence for this case. */
6166 new_spill_reg_store[REGNO (reloadreg)]
6167 = inc_for_reload (reloadreg, oldequiv, rl->out,
6171 /* If we are reloading a pseudo-register that was set by the previous
6172 insn, see if we can get rid of that pseudo-register entirely
6173 by redirecting the previous insn into our reload register. */
6175 else if (optimize && GET_CODE (old) == REG
6176 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6177 && dead_or_set_p (insn, old)
6178 /* This is unsafe if some other reload
6179 uses the same reg first. */
6180 && reload_reg_free_for_value_p (REGNO (reloadreg),
6186 rtx temp = PREV_INSN (insn);
6187 while (temp && GET_CODE (temp) == NOTE)
6188 temp = PREV_INSN (temp);
6190 && GET_CODE (temp) == INSN
6191 && GET_CODE (PATTERN (temp)) == SET
6192 && SET_DEST (PATTERN (temp)) == old
6193 /* Make sure we can access insn_operand_constraint. */
6194 && asm_noperands (PATTERN (temp)) < 0
6195 /* This is unsafe if prev insn rejects our reload reg. */
6196 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6198 /* This is unsafe if operand occurs more than once in current
6199 insn. Perhaps some occurrences aren't reloaded. */
6200 && count_occurrences (PATTERN (insn), old, 0) == 1
6201 /* Don't risk splitting a matching pair of operands. */
6202 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6204 /* Store into the reload register instead of the pseudo. */
6205 SET_DEST (PATTERN (temp)) = reloadreg;
6207 /* If the previous insn is an output reload, the source is
6208 a reload register, and its spill_reg_store entry will
6209 contain the previous destination. This is now
6211 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6212 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6214 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6215 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6218 /* If these are the only uses of the pseudo reg,
6219 pretend for GDB it lives in the reload reg we used. */
6220 if (REG_N_DEATHS (REGNO (old)) == 1
6221 && REG_N_SETS (REGNO (old)) == 1)
6223 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6224 alter_reg (REGNO (old), -1);
6230 /* We can't do that, so output an insn to load RELOADREG. */
6232 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6233 /* If we have a secondary reload, pick up the secondary register
6234 and icode, if any. If OLDEQUIV and OLD are different or
6235 if this is an in-out reload, recompute whether or not we
6236 still need a secondary register and what the icode should
6237 be. If we still need a secondary register and the class or
6238 icode is different, go back to reloading from OLD if using
6239 OLDEQUIV means that we got the wrong type of register. We
6240 cannot have different class or icode due to an in-out reload
6241 because we don't make such reloads when both the input and
6242 output need secondary reload registers. */
6244 if (! special && rl->secondary_in_reload >= 0)
6246 rtx second_reload_reg = 0;
6247 int secondary_reload = rl->secondary_in_reload;
6248 rtx real_oldequiv = oldequiv;
6251 enum insn_code icode;
6253 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6254 and similarly for OLD.
6255 See comments in get_secondary_reload in reload.c. */
6256 /* If it is a pseudo that cannot be replaced with its
6257 equivalent MEM, we must fall back to reload_in, which
6258 will have all the necessary substitutions registered.
6259 Likewise for a pseudo that can't be replaced with its
6260 equivalent constant.
6262 Take extra care for subregs of such pseudos. Note that
6263 we cannot use reg_equiv_mem in this case because it is
6264 not in the right mode. */
6267 if (GET_CODE (tmp) == SUBREG)
6268 tmp = SUBREG_REG (tmp);
6269 if (GET_CODE (tmp) == REG
6270 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6271 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6272 || reg_equiv_constant[REGNO (tmp)] != 0))
6274 if (! reg_equiv_mem[REGNO (tmp)]
6275 || num_not_at_initial_offset
6276 || GET_CODE (oldequiv) == SUBREG)
6277 real_oldequiv = rl->in;
6279 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6283 if (GET_CODE (tmp) == SUBREG)
6284 tmp = SUBREG_REG (tmp);
6285 if (GET_CODE (tmp) == REG
6286 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6287 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6288 || reg_equiv_constant[REGNO (tmp)] != 0))
6290 if (! reg_equiv_mem[REGNO (tmp)]
6291 || num_not_at_initial_offset
6292 || GET_CODE (old) == SUBREG)
6295 real_old = reg_equiv_mem[REGNO (tmp)];
6298 second_reload_reg = rld[secondary_reload].reg_rtx;
6299 icode = rl->secondary_in_icode;
6301 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6302 || (rl->in != 0 && rl->out != 0))
6304 enum reg_class new_class
6305 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6306 mode, real_oldequiv);
6308 if (new_class == NO_REGS)
6309 second_reload_reg = 0;
6312 enum insn_code new_icode;
6313 enum machine_mode new_mode;
6315 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6316 REGNO (second_reload_reg)))
6317 oldequiv = old, real_oldequiv = real_old;
6320 new_icode = reload_in_optab[(int) mode];
6321 if (new_icode != CODE_FOR_nothing
6322 && ((insn_data[(int) new_icode].operand[0].predicate
6323 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6325 || (insn_data[(int) new_icode].operand[1].predicate
6326 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6327 (real_oldequiv, mode)))))
6328 new_icode = CODE_FOR_nothing;
6330 if (new_icode == CODE_FOR_nothing)
6333 new_mode = insn_data[(int) new_icode].operand[2].mode;
6335 if (GET_MODE (second_reload_reg) != new_mode)
6337 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6339 oldequiv = old, real_oldequiv = real_old;
6342 = gen_rtx_REG (new_mode,
6343 REGNO (second_reload_reg));
6349 /* If we still need a secondary reload register, check
6350 to see if it is being used as a scratch or intermediate
6351 register and generate code appropriately. If we need
6352 a scratch register, use REAL_OLDEQUIV since the form of
6353 the insn may depend on the actual address if it is
6356 if (second_reload_reg)
6358 if (icode != CODE_FOR_nothing)
6360 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6361 second_reload_reg));
6366 /* See if we need a scratch register to load the
6367 intermediate register (a tertiary reload). */
6368 enum insn_code tertiary_icode
6369 = rld[secondary_reload].secondary_in_icode;
6371 if (tertiary_icode != CODE_FOR_nothing)
6373 rtx third_reload_reg
6374 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6376 emit_insn ((GEN_FCN (tertiary_icode)
6377 (second_reload_reg, real_oldequiv,
6378 third_reload_reg)));
6381 gen_reload (second_reload_reg, real_oldequiv,
6385 oldequiv = second_reload_reg;
6391 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6393 rtx real_oldequiv = oldequiv;
6395 if ((GET_CODE (oldequiv) == REG
6396 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6397 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6398 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6399 || (GET_CODE (oldequiv) == SUBREG
6400 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6401 && (REGNO (SUBREG_REG (oldequiv))
6402 >= FIRST_PSEUDO_REGISTER)
6403 && ((reg_equiv_memory_loc
6404 [REGNO (SUBREG_REG (oldequiv))] != 0)
6405 || (reg_equiv_constant
6406 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6407 real_oldequiv = rl->in;
6408 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6412 /* End this sequence. */
6413 *where = get_insns ();
6416 /* Update reload_override_in so that delete_address_reloads_1
6417 can see the actual register usage. */
6419 reload_override_in[j] = oldequiv;
6422 /* Generate insns to for the output reload RL, which is for the insn described
6423 by CHAIN and has the number J. */
6425 emit_output_reload_insns (chain, rl, j)
6426 struct insn_chain *chain;
6430 rtx reloadreg = rl->reg_rtx;
6431 rtx insn = chain->insn;
6434 enum machine_mode mode = GET_MODE (old);
6437 if (rl->when_needed == RELOAD_OTHER)
6440 push_to_sequence (output_reload_insns[rl->opnum]);
6442 /* Determine the mode to reload in.
6443 See comments above (for input reloading). */
6445 if (mode == VOIDmode)
6447 /* VOIDmode should never happen for an output. */
6448 if (asm_noperands (PATTERN (insn)) < 0)
6449 /* It's the compiler's fault. */
6450 fatal_insn ("VOIDmode on an output", insn);
6451 error_for_asm (insn, "output operand is constant in `asm'");
6452 /* Prevent crash--use something we know is valid. */
6454 old = gen_rtx_REG (mode, REGNO (reloadreg));
6457 if (GET_MODE (reloadreg) != mode)
6458 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6460 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6462 /* If we need two reload regs, set RELOADREG to the intermediate
6463 one, since it will be stored into OLD. We might need a secondary
6464 register only for an input reload, so check again here. */
6466 if (rl->secondary_out_reload >= 0)
6470 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6471 && reg_equiv_mem[REGNO (old)] != 0)
6472 real_old = reg_equiv_mem[REGNO (old)];
6474 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6478 rtx second_reloadreg = reloadreg;
6479 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6481 /* See if RELOADREG is to be used as a scratch register
6482 or as an intermediate register. */
6483 if (rl->secondary_out_icode != CODE_FOR_nothing)
6485 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6486 (real_old, second_reloadreg, reloadreg)));
6491 /* See if we need both a scratch and intermediate reload
6494 int secondary_reload = rl->secondary_out_reload;
6495 enum insn_code tertiary_icode
6496 = rld[secondary_reload].secondary_out_icode;
6498 if (GET_MODE (reloadreg) != mode)
6499 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6501 if (tertiary_icode != CODE_FOR_nothing)
6504 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6507 /* Copy primary reload reg to secondary reload reg.
6508 (Note that these have been swapped above, then
6509 secondary reload reg to OLD using our insn. */
6511 /* If REAL_OLD is a paradoxical SUBREG, remove it
6512 and try to put the opposite SUBREG on
6514 if (GET_CODE (real_old) == SUBREG
6515 && (GET_MODE_SIZE (GET_MODE (real_old))
6516 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6517 && 0 != (tem = gen_lowpart_common
6518 (GET_MODE (SUBREG_REG (real_old)),
6520 real_old = SUBREG_REG (real_old), reloadreg = tem;
6522 gen_reload (reloadreg, second_reloadreg,
6523 rl->opnum, rl->when_needed);
6524 emit_insn ((GEN_FCN (tertiary_icode)
6525 (real_old, reloadreg, third_reloadreg)));
6530 /* Copy between the reload regs here and then to
6533 gen_reload (reloadreg, second_reloadreg,
6534 rl->opnum, rl->when_needed);
6540 /* Output the last reload insn. */
6545 /* Don't output the last reload if OLD is not the dest of
6546 INSN and is in the src and is clobbered by INSN. */
6547 if (! flag_expensive_optimizations
6548 || GET_CODE (old) != REG
6549 || !(set = single_set (insn))
6550 || rtx_equal_p (old, SET_DEST (set))
6551 || !reg_mentioned_p (old, SET_SRC (set))
6552 || !regno_clobbered_p (REGNO (old), insn, rl->mode))
6553 gen_reload (old, reloadreg, rl->opnum,
6557 /* Look at all insns we emitted, just to be safe. */
6558 for (p = get_insns (); p; p = NEXT_INSN (p))
6561 rtx pat = PATTERN (p);
6563 /* If this output reload doesn't come from a spill reg,
6564 clear any memory of reloaded copies of the pseudo reg.
6565 If this output reload comes from a spill reg,
6566 reg_has_output_reload will make this do nothing. */
6567 note_stores (pat, forget_old_reloads_1, NULL);
6569 if (reg_mentioned_p (rl->reg_rtx, pat))
6571 rtx set = single_set (insn);
6572 if (reload_spill_index[j] < 0
6574 && SET_SRC (set) == rl->reg_rtx)
6576 int src = REGNO (SET_SRC (set));
6578 reload_spill_index[j] = src;
6579 SET_HARD_REG_BIT (reg_is_output_reload, src);
6580 if (find_regno_note (insn, REG_DEAD, src))
6581 SET_HARD_REG_BIT (reg_reloaded_died, src);
6583 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6585 int s = rl->secondary_out_reload;
6586 set = single_set (p);
6587 /* If this reload copies only to the secondary reload
6588 register, the secondary reload does the actual
6590 if (s >= 0 && set == NULL_RTX)
6591 /* We can't tell what function the secondary reload
6592 has and where the actual store to the pseudo is
6593 made; leave new_spill_reg_store alone. */
6596 && SET_SRC (set) == rl->reg_rtx
6597 && SET_DEST (set) == rld[s].reg_rtx)
6599 /* Usually the next instruction will be the
6600 secondary reload insn; if we can confirm
6601 that it is, setting new_spill_reg_store to
6602 that insn will allow an extra optimization. */
6603 rtx s_reg = rld[s].reg_rtx;
6604 rtx next = NEXT_INSN (p);
6605 rld[s].out = rl->out;
6606 rld[s].out_reg = rl->out_reg;
6607 set = single_set (next);
6608 if (set && SET_SRC (set) == s_reg
6609 && ! new_spill_reg_store[REGNO (s_reg)])
6611 SET_HARD_REG_BIT (reg_is_output_reload,
6613 new_spill_reg_store[REGNO (s_reg)] = next;
6617 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6622 if (rl->when_needed == RELOAD_OTHER)
6624 emit_insns (other_output_reload_insns[rl->opnum]);
6625 other_output_reload_insns[rl->opnum] = get_insns ();
6628 output_reload_insns[rl->opnum] = get_insns ();
6633 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6634 and has the number J. */
6636 do_input_reload (chain, rl, j)
6637 struct insn_chain *chain;
6641 int expect_occurrences = 1;
6642 rtx insn = chain->insn;
6643 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6644 ? rl->in_reg : rl->in);
6647 /* AUTO_INC reloads need to be handled even if inherited. We got an
6648 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6649 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6650 && ! rtx_equal_p (rl->reg_rtx, old)
6651 && rl->reg_rtx != 0)
6652 emit_input_reload_insns (chain, rld + j, old, j);
6654 /* When inheriting a wider reload, we have a MEM in rl->in,
6655 e.g. inheriting a SImode output reload for
6656 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6657 if (optimize && reload_inherited[j] && rl->in
6658 && GET_CODE (rl->in) == MEM
6659 && GET_CODE (rl->in_reg) == MEM
6660 && reload_spill_index[j] >= 0
6661 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6664 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6665 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6668 /* If we are reloading a register that was recently stored in with an
6669 output-reload, see if we can prove there was
6670 actually no need to store the old value in it. */
6673 && (reload_inherited[j] || reload_override_in[j])
6675 && GET_CODE (rl->reg_rtx) == REG
6676 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6678 /* There doesn't seem to be any reason to restrict this to pseudos
6679 and doing so loses in the case where we are copying from a
6680 register of the wrong class. */
6681 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6682 >= FIRST_PSEUDO_REGISTER)
6684 /* The insn might have already some references to stackslots
6685 replaced by MEMs, while reload_out_reg still names the
6687 && (dead_or_set_p (insn,
6688 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6689 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6691 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6694 /* Do output reloading for reload RL, which is for the insn described by
6695 CHAIN and has the number J.
6696 ??? At some point we need to support handling output reloads of
6697 JUMP_INSNs or insns that set cc0. */
6699 do_output_reload (chain, rl, j)
6700 struct insn_chain *chain;
6705 rtx insn = chain->insn;
6706 /* If this is an output reload that stores something that is
6707 not loaded in this same reload, see if we can eliminate a previous
6709 rtx pseudo = rl->out_reg;
6712 && GET_CODE (pseudo) == REG
6713 && ! rtx_equal_p (rl->in_reg, pseudo)
6714 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6715 && reg_last_reload_reg[REGNO (pseudo)])
6717 int pseudo_no = REGNO (pseudo);
6718 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6720 /* We don't need to test full validity of last_regno for
6721 inherit here; we only want to know if the store actually
6722 matches the pseudo. */
6723 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6724 && reg_reloaded_contents[last_regno] == pseudo_no
6725 && spill_reg_store[last_regno]
6726 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6727 delete_output_reload (insn, j, last_regno);
6732 || rl->reg_rtx == old
6733 || rl->reg_rtx == 0)
6736 /* An output operand that dies right away does need a reload,
6737 but need not be copied from it. Show the new location in the
6739 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6740 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6742 XEXP (note, 0) = rl->reg_rtx;
6745 /* Likewise for a SUBREG of an operand that dies. */
6746 else if (GET_CODE (old) == SUBREG
6747 && GET_CODE (SUBREG_REG (old)) == REG
6748 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6751 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6755 else if (GET_CODE (old) == SCRATCH)
6756 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6757 but we don't want to make an output reload. */
6760 /* If is a JUMP_INSN, we can't support output reloads yet. */
6761 if (GET_CODE (insn) == JUMP_INSN)
6764 emit_output_reload_insns (chain, rld + j, j);
6767 /* Output insns to reload values in and out of the chosen reload regs. */
6770 emit_reload_insns (chain)
6771 struct insn_chain *chain;
6773 rtx insn = chain->insn;
6776 rtx following_insn = NEXT_INSN (insn);
6777 rtx before_insn = PREV_INSN (insn);
6779 CLEAR_HARD_REG_SET (reg_reloaded_died);
6781 for (j = 0; j < reload_n_operands; j++)
6782 input_reload_insns[j] = input_address_reload_insns[j]
6783 = inpaddr_address_reload_insns[j]
6784 = output_reload_insns[j] = output_address_reload_insns[j]
6785 = outaddr_address_reload_insns[j]
6786 = other_output_reload_insns[j] = 0;
6787 other_input_address_reload_insns = 0;
6788 other_input_reload_insns = 0;
6789 operand_reload_insns = 0;
6790 other_operand_reload_insns = 0;
6792 /* Dump reloads into the dump file. */
6795 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6796 debug_reload_to_stream (rtl_dump_file);
6799 /* Now output the instructions to copy the data into and out of the
6800 reload registers. Do these in the order that the reloads were reported,
6801 since reloads of base and index registers precede reloads of operands
6802 and the operands may need the base and index registers reloaded. */
6804 for (j = 0; j < n_reloads; j++)
6807 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6808 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6810 do_input_reload (chain, rld + j, j);
6811 do_output_reload (chain, rld + j, j);
6814 /* Now write all the insns we made for reloads in the order expected by
6815 the allocation functions. Prior to the insn being reloaded, we write
6816 the following reloads:
6818 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6820 RELOAD_OTHER reloads.
6822 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6823 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6824 RELOAD_FOR_INPUT reload for the operand.
6826 RELOAD_FOR_OPADDR_ADDRS reloads.
6828 RELOAD_FOR_OPERAND_ADDRESS reloads.
6830 After the insn being reloaded, we write the following:
6832 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6833 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6834 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6835 reloads for the operand. The RELOAD_OTHER output reloads are
6836 output in descending order by reload number. */
6838 emit_insns_before (other_input_address_reload_insns, insn);
6839 emit_insns_before (other_input_reload_insns, insn);
6841 for (j = 0; j < reload_n_operands; j++)
6843 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6844 emit_insns_before (input_address_reload_insns[j], insn);
6845 emit_insns_before (input_reload_insns[j], insn);
6848 emit_insns_before (other_operand_reload_insns, insn);
6849 emit_insns_before (operand_reload_insns, insn);
6851 for (j = 0; j < reload_n_operands; j++)
6853 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6854 emit_insns_before (output_address_reload_insns[j], following_insn);
6855 emit_insns_before (output_reload_insns[j], following_insn);
6856 emit_insns_before (other_output_reload_insns[j], following_insn);
6859 /* Keep basic block info up to date. */
6862 if (BLOCK_HEAD (chain->block) == insn)
6863 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6864 if (BLOCK_END (chain->block) == insn)
6865 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6868 /* For all the spill regs newly reloaded in this instruction,
6869 record what they were reloaded from, so subsequent instructions
6870 can inherit the reloads.
6872 Update spill_reg_store for the reloads of this insn.
6873 Copy the elements that were updated in the loop above. */
6875 for (j = 0; j < n_reloads; j++)
6877 register int r = reload_order[j];
6878 register int i = reload_spill_index[r];
6880 /* If this is a non-inherited input reload from a pseudo, we must
6881 clear any memory of a previous store to the same pseudo. Only do
6882 something if there will not be an output reload for the pseudo
6884 if (rld[r].in_reg != 0
6885 && ! (reload_inherited[r] || reload_override_in[r]))
6887 rtx reg = rld[r].in_reg;
6889 if (GET_CODE (reg) == SUBREG)
6890 reg = SUBREG_REG (reg);
6892 if (GET_CODE (reg) == REG
6893 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6894 && ! reg_has_output_reload[REGNO (reg)])
6896 int nregno = REGNO (reg);
6898 if (reg_last_reload_reg[nregno])
6900 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6902 if (reg_reloaded_contents[last_regno] == nregno)
6903 spill_reg_store[last_regno] = 0;
6908 /* I is nonneg if this reload used a register.
6909 If rld[r].reg_rtx is 0, this is an optional reload
6910 that we opted to ignore. */
6912 if (i >= 0 && rld[r].reg_rtx != 0)
6914 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6916 int part_reaches_end = 0;
6917 int all_reaches_end = 1;
6919 /* For a multi register reload, we need to check if all or part
6920 of the value lives to the end. */
6921 for (k = 0; k < nr; k++)
6923 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6924 rld[r].when_needed))
6925 part_reaches_end = 1;
6927 all_reaches_end = 0;
6930 /* Ignore reloads that don't reach the end of the insn in
6932 if (all_reaches_end)
6934 /* First, clear out memory of what used to be in this spill reg.
6935 If consecutive registers are used, clear them all. */
6937 for (k = 0; k < nr; k++)
6938 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6940 /* Maybe the spill reg contains a copy of reload_out. */
6942 && (GET_CODE (rld[r].out) == REG
6946 || GET_CODE (rld[r].out_reg) == REG))
6948 rtx out = (GET_CODE (rld[r].out) == REG
6952 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6953 register int nregno = REGNO (out);
6954 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6955 : HARD_REGNO_NREGS (nregno,
6956 GET_MODE (rld[r].reg_rtx)));
6958 spill_reg_store[i] = new_spill_reg_store[i];
6959 spill_reg_stored_to[i] = out;
6960 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6962 /* If NREGNO is a hard register, it may occupy more than
6963 one register. If it does, say what is in the
6964 rest of the registers assuming that both registers
6965 agree on how many words the object takes. If not,
6966 invalidate the subsequent registers. */
6968 if (nregno < FIRST_PSEUDO_REGISTER)
6969 for (k = 1; k < nnr; k++)
6970 reg_last_reload_reg[nregno + k]
6972 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6973 REGNO (rld[r].reg_rtx) + k)
6976 /* Now do the inverse operation. */
6977 for (k = 0; k < nr; k++)
6979 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6980 reg_reloaded_contents[i + k]
6981 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6984 reg_reloaded_insn[i + k] = insn;
6985 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6989 /* Maybe the spill reg contains a copy of reload_in. Only do
6990 something if there will not be an output reload for
6991 the register being reloaded. */
6992 else if (rld[r].out_reg == 0
6994 && ((GET_CODE (rld[r].in) == REG
6995 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6996 && ! reg_has_output_reload[REGNO (rld[r].in)])
6997 || (GET_CODE (rld[r].in_reg) == REG
6998 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6999 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7001 register int nregno;
7004 if (GET_CODE (rld[r].in) == REG
7005 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7006 nregno = REGNO (rld[r].in);
7007 else if (GET_CODE (rld[r].in_reg) == REG)
7008 nregno = REGNO (rld[r].in_reg);
7010 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7012 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7013 : HARD_REGNO_NREGS (nregno,
7014 GET_MODE (rld[r].reg_rtx)));
7016 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7018 if (nregno < FIRST_PSEUDO_REGISTER)
7019 for (k = 1; k < nnr; k++)
7020 reg_last_reload_reg[nregno + k]
7022 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7023 REGNO (rld[r].reg_rtx) + k)
7026 /* Unless we inherited this reload, show we haven't
7027 recently done a store.
7028 Previous stores of inherited auto_inc expressions
7029 also have to be discarded. */
7030 if (! reload_inherited[r]
7031 || (rld[r].out && ! rld[r].out_reg))
7032 spill_reg_store[i] = 0;
7034 for (k = 0; k < nr; k++)
7036 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7037 reg_reloaded_contents[i + k]
7038 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7041 reg_reloaded_insn[i + k] = insn;
7042 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7047 /* However, if part of the reload reaches the end, then we must
7048 invalidate the old info for the part that survives to the end. */
7049 else if (part_reaches_end)
7051 for (k = 0; k < nr; k++)
7052 if (reload_reg_reaches_end_p (i + k,
7054 rld[r].when_needed))
7055 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7059 /* The following if-statement was #if 0'd in 1.34 (or before...).
7060 It's reenabled in 1.35 because supposedly nothing else
7061 deals with this problem. */
7063 /* If a register gets output-reloaded from a non-spill register,
7064 that invalidates any previous reloaded copy of it.
7065 But forget_old_reloads_1 won't get to see it, because
7066 it thinks only about the original insn. So invalidate it here. */
7067 if (i < 0 && rld[r].out != 0
7068 && (GET_CODE (rld[r].out) == REG
7069 || (GET_CODE (rld[r].out) == MEM
7070 && GET_CODE (rld[r].out_reg) == REG)))
7072 rtx out = (GET_CODE (rld[r].out) == REG
7073 ? rld[r].out : rld[r].out_reg);
7074 register int nregno = REGNO (out);
7075 if (nregno >= FIRST_PSEUDO_REGISTER)
7077 rtx src_reg, store_insn = NULL_RTX;
7079 reg_last_reload_reg[nregno] = 0;
7081 /* If we can find a hard register that is stored, record
7082 the storing insn so that we may delete this insn with
7083 delete_output_reload. */
7084 src_reg = rld[r].reg_rtx;
7086 /* If this is an optional reload, try to find the source reg
7087 from an input reload. */
7090 rtx set = single_set (insn);
7091 if (set && SET_DEST (set) == rld[r].out)
7095 src_reg = SET_SRC (set);
7097 for (k = 0; k < n_reloads; k++)
7099 if (rld[k].in == src_reg)
7101 src_reg = rld[k].reg_rtx;
7108 store_insn = new_spill_reg_store[REGNO (src_reg)];
7109 if (src_reg && GET_CODE (src_reg) == REG
7110 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7112 int src_regno = REGNO (src_reg);
7113 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7114 /* The place where to find a death note varies with
7115 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7116 necessarily checked exactly in the code that moves
7117 notes, so just check both locations. */
7118 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7120 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7123 spill_reg_store[src_regno + nr] = store_insn;
7124 spill_reg_stored_to[src_regno + nr] = out;
7125 reg_reloaded_contents[src_regno + nr] = nregno;
7126 reg_reloaded_insn[src_regno + nr] = store_insn;
7127 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7128 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7129 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7131 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7133 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7135 reg_last_reload_reg[nregno] = src_reg;
7140 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7142 while (num_regs-- > 0)
7143 reg_last_reload_reg[nregno + num_regs] = 0;
7147 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7150 /* Emit code to perform a reload from IN (which may be a reload register) to
7151 OUT (which may also be a reload register). IN or OUT is from operand
7152 OPNUM with reload type TYPE.
7154 Returns first insn emitted. */
7157 gen_reload (out, in, opnum, type)
7161 enum reload_type type;
7163 rtx last = get_last_insn ();
7166 /* If IN is a paradoxical SUBREG, remove it and try to put the
7167 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7168 if (GET_CODE (in) == SUBREG
7169 && (GET_MODE_SIZE (GET_MODE (in))
7170 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7171 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7172 in = SUBREG_REG (in), out = tem;
7173 else if (GET_CODE (out) == SUBREG
7174 && (GET_MODE_SIZE (GET_MODE (out))
7175 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7176 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7177 out = SUBREG_REG (out), in = tem;
7179 /* How to do this reload can get quite tricky. Normally, we are being
7180 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7181 register that didn't get a hard register. In that case we can just
7182 call emit_move_insn.
7184 We can also be asked to reload a PLUS that adds a register or a MEM to
7185 another register, constant or MEM. This can occur during frame pointer
7186 elimination and while reloading addresses. This case is handled by
7187 trying to emit a single insn to perform the add. If it is not valid,
7188 we use a two insn sequence.
7190 Finally, we could be called to handle an 'o' constraint by putting
7191 an address into a register. In that case, we first try to do this
7192 with a named pattern of "reload_load_address". If no such pattern
7193 exists, we just emit a SET insn and hope for the best (it will normally
7194 be valid on machines that use 'o').
7196 This entire process is made complex because reload will never
7197 process the insns we generate here and so we must ensure that
7198 they will fit their constraints and also by the fact that parts of
7199 IN might be being reloaded separately and replaced with spill registers.
7200 Because of this, we are, in some sense, just guessing the right approach
7201 here. The one listed above seems to work.
7203 ??? At some point, this whole thing needs to be rethought. */
7205 if (GET_CODE (in) == PLUS
7206 && (GET_CODE (XEXP (in, 0)) == REG
7207 || GET_CODE (XEXP (in, 0)) == SUBREG
7208 || GET_CODE (XEXP (in, 0)) == MEM)
7209 && (GET_CODE (XEXP (in, 1)) == REG
7210 || GET_CODE (XEXP (in, 1)) == SUBREG
7211 || CONSTANT_P (XEXP (in, 1))
7212 || GET_CODE (XEXP (in, 1)) == MEM))
7214 /* We need to compute the sum of a register or a MEM and another
7215 register, constant, or MEM, and put it into the reload
7216 register. The best possible way of doing this is if the machine
7217 has a three-operand ADD insn that accepts the required operands.
7219 The simplest approach is to try to generate such an insn and see if it
7220 is recognized and matches its constraints. If so, it can be used.
7222 It might be better not to actually emit the insn unless it is valid,
7223 but we need to pass the insn as an operand to `recog' and
7224 `extract_insn' and it is simpler to emit and then delete the insn if
7225 not valid than to dummy things up. */
7227 rtx op0, op1, tem, insn;
7230 op0 = find_replacement (&XEXP (in, 0));
7231 op1 = find_replacement (&XEXP (in, 1));
7233 /* Since constraint checking is strict, commutativity won't be
7234 checked, so we need to do that here to avoid spurious failure
7235 if the add instruction is two-address and the second operand
7236 of the add is the same as the reload reg, which is frequently
7237 the case. If the insn would be A = B + A, rearrange it so
7238 it will be A = A + B as constrain_operands expects. */
7240 if (GET_CODE (XEXP (in, 1)) == REG
7241 && REGNO (out) == REGNO (XEXP (in, 1)))
7242 tem = op0, op0 = op1, op1 = tem;
7244 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7245 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7247 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7248 code = recog_memoized (insn);
7252 extract_insn (insn);
7253 /* We want constrain operands to treat this insn strictly in
7254 its validity determination, i.e., the way it would after reload
7256 if (constrain_operands (1))
7260 delete_insns_since (last);
7262 /* If that failed, we must use a conservative two-insn sequence.
7264 Use a move to copy one operand into the reload register. Prefer
7265 to reload a constant, MEM or pseudo since the move patterns can
7266 handle an arbitrary operand. If OP1 is not a constant, MEM or
7267 pseudo and OP1 is not a valid operand for an add instruction, then
7270 After reloading one of the operands into the reload register, add
7271 the reload register to the output register.
7273 If there is another way to do this for a specific machine, a
7274 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7277 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7279 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7280 || (GET_CODE (op1) == REG
7281 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7282 || (code != CODE_FOR_nothing
7283 && ! ((*insn_data[code].operand[2].predicate)
7284 (op1, insn_data[code].operand[2].mode))))
7285 tem = op0, op0 = op1, op1 = tem;
7287 gen_reload (out, op0, opnum, type);
7289 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7290 This fixes a problem on the 32K where the stack pointer cannot
7291 be used as an operand of an add insn. */
7293 if (rtx_equal_p (op0, op1))
7296 insn = emit_insn (gen_add2_insn (out, op1));
7298 /* If that failed, copy the address register to the reload register.
7299 Then add the constant to the reload register. */
7301 code = recog_memoized (insn);
7305 extract_insn (insn);
7306 /* We want constrain operands to treat this insn strictly in
7307 its validity determination, i.e., the way it would after reload
7309 if (constrain_operands (1))
7311 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7313 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7318 delete_insns_since (last);
7320 gen_reload (out, op1, opnum, type);
7321 insn = emit_insn (gen_add2_insn (out, op0));
7322 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7325 #ifdef SECONDARY_MEMORY_NEEDED
7326 /* If we need a memory location to do the move, do it that way. */
7327 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7328 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7329 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7330 REGNO_REG_CLASS (REGNO (out)),
7333 /* Get the memory to use and rewrite both registers to its mode. */
7334 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7336 if (GET_MODE (loc) != GET_MODE (out))
7337 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7339 if (GET_MODE (loc) != GET_MODE (in))
7340 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7342 gen_reload (loc, in, opnum, type);
7343 gen_reload (out, loc, opnum, type);
7347 /* If IN is a simple operand, use gen_move_insn. */
7348 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7349 emit_insn (gen_move_insn (out, in));
7351 #ifdef HAVE_reload_load_address
7352 else if (HAVE_reload_load_address)
7353 emit_insn (gen_reload_load_address (out, in));
7356 /* Otherwise, just write (set OUT IN) and hope for the best. */
7358 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7360 /* Return the first insn emitted.
7361 We can not just return get_last_insn, because there may have
7362 been multiple instructions emitted. Also note that gen_move_insn may
7363 emit more than one insn itself, so we can not assume that there is one
7364 insn emitted per emit_insn_before call. */
7366 return last ? NEXT_INSN (last) : get_insns ();
7369 /* Delete a previously made output-reload
7370 whose result we now believe is not needed.
7371 First we double-check.
7373 INSN is the insn now being processed.
7374 LAST_RELOAD_REG is the hard register number for which we want to delete
7375 the last output reload.
7376 J is the reload-number that originally used REG. The caller has made
7377 certain that reload J doesn't use REG any longer for input. */
7380 delete_output_reload (insn, j, last_reload_reg)
7383 int last_reload_reg;
7385 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7386 rtx reg = spill_reg_stored_to[last_reload_reg];
7389 int n_inherited = 0;
7393 /* Get the raw pseudo-register referred to. */
7395 while (GET_CODE (reg) == SUBREG)
7396 reg = SUBREG_REG (reg);
7397 substed = reg_equiv_memory_loc[REGNO (reg)];
7399 /* This is unsafe if the operand occurs more often in the current
7400 insn than it is inherited. */
7401 for (k = n_reloads - 1; k >= 0; k--)
7403 rtx reg2 = rld[k].in;
7406 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7407 reg2 = rld[k].in_reg;
7409 if (rld[k].out && ! rld[k].out_reg)
7410 reg2 = XEXP (rld[k].in_reg, 0);
7412 while (GET_CODE (reg2) == SUBREG)
7413 reg2 = SUBREG_REG (reg2);
7414 if (rtx_equal_p (reg2, reg))
7416 if (reload_inherited[k] || reload_override_in[k] || k == j)
7419 reg2 = rld[k].out_reg;
7422 while (GET_CODE (reg2) == SUBREG)
7423 reg2 = XEXP (reg2, 0);
7424 if (rtx_equal_p (reg2, reg))
7431 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7433 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7434 if (n_occurrences > n_inherited)
7437 /* If the pseudo-reg we are reloading is no longer referenced
7438 anywhere between the store into it and here,
7439 and no jumps or labels intervene, then the value can get
7440 here through the reload reg alone.
7441 Otherwise, give up--return. */
7442 for (i1 = NEXT_INSN (output_reload_insn);
7443 i1 != insn; i1 = NEXT_INSN (i1))
7445 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7447 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7448 && reg_mentioned_p (reg, PATTERN (i1)))
7450 /* If this is USE in front of INSN, we only have to check that
7451 there are no more references than accounted for by inheritance. */
7452 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7454 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7455 i1 = NEXT_INSN (i1);
7457 if (n_occurrences <= n_inherited && i1 == insn)
7463 /* The caller has already checked that REG dies or is set in INSN.
7464 It has also checked that we are optimizing, and thus some inaccurancies
7465 in the debugging information are acceptable.
7466 So we could just delete output_reload_insn.
7467 But in some cases we can improve the debugging information without
7468 sacrificing optimization - maybe even improving the code:
7469 See if the pseudo reg has been completely replaced
7470 with reload regs. If so, delete the store insn
7471 and forget we had a stack slot for the pseudo. */
7472 if (rld[j].out != rld[j].in
7473 && REG_N_DEATHS (REGNO (reg)) == 1
7474 && REG_N_SETS (REGNO (reg)) == 1
7475 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7476 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7480 /* We know that it was used only between here
7481 and the beginning of the current basic block.
7482 (We also know that the last use before INSN was
7483 the output reload we are thinking of deleting, but never mind that.)
7484 Search that range; see if any ref remains. */
7485 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7487 rtx set = single_set (i2);
7489 /* Uses which just store in the pseudo don't count,
7490 since if they are the only uses, they are dead. */
7491 if (set != 0 && SET_DEST (set) == reg)
7493 if (GET_CODE (i2) == CODE_LABEL
7494 || GET_CODE (i2) == JUMP_INSN)
7496 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7497 && reg_mentioned_p (reg, PATTERN (i2)))
7499 /* Some other ref remains; just delete the output reload we
7501 delete_address_reloads (output_reload_insn, insn);
7502 PUT_CODE (output_reload_insn, NOTE);
7503 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7504 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7509 /* Delete the now-dead stores into this pseudo. */
7510 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7512 rtx set = single_set (i2);
7514 if (set != 0 && SET_DEST (set) == reg)
7516 delete_address_reloads (i2, insn);
7517 /* This might be a basic block head,
7518 thus don't use delete_insn. */
7519 PUT_CODE (i2, NOTE);
7520 NOTE_SOURCE_FILE (i2) = 0;
7521 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7523 if (GET_CODE (i2) == CODE_LABEL
7524 || GET_CODE (i2) == JUMP_INSN)
7528 /* For the debugging info,
7529 say the pseudo lives in this reload reg. */
7530 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7531 alter_reg (REGNO (reg), -1);
7533 delete_address_reloads (output_reload_insn, insn);
7534 PUT_CODE (output_reload_insn, NOTE);
7535 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7536 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7540 /* We are going to delete DEAD_INSN. Recursively delete loads of
7541 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7542 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7544 delete_address_reloads (dead_insn, current_insn)
7545 rtx dead_insn, current_insn;
7547 rtx set = single_set (dead_insn);
7548 rtx set2, dst, prev, next;
7551 rtx dst = SET_DEST (set);
7552 if (GET_CODE (dst) == MEM)
7553 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7555 /* If we deleted the store from a reloaded post_{in,de}c expression,
7556 we can delete the matching adds. */
7557 prev = PREV_INSN (dead_insn);
7558 next = NEXT_INSN (dead_insn);
7559 if (! prev || ! next)
7561 set = single_set (next);
7562 set2 = single_set (prev);
7564 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7565 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7566 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7568 dst = SET_DEST (set);
7569 if (! rtx_equal_p (dst, SET_DEST (set2))
7570 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7571 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7572 || (INTVAL (XEXP (SET_SRC (set), 1))
7573 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7579 /* Subfunction of delete_address_reloads: process registers found in X. */
7581 delete_address_reloads_1 (dead_insn, x, current_insn)
7582 rtx dead_insn, x, current_insn;
7584 rtx prev, set, dst, i2;
7586 enum rtx_code code = GET_CODE (x);
7590 const char *fmt = GET_RTX_FORMAT (code);
7591 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7594 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7595 else if (fmt[i] == 'E')
7597 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7598 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7605 if (spill_reg_order[REGNO (x)] < 0)
7608 /* Scan backwards for the insn that sets x. This might be a way back due
7610 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7612 code = GET_CODE (prev);
7613 if (code == CODE_LABEL || code == JUMP_INSN)
7615 if (GET_RTX_CLASS (code) != 'i')
7617 if (reg_set_p (x, PATTERN (prev)))
7619 if (reg_referenced_p (x, PATTERN (prev)))
7622 if (! prev || INSN_UID (prev) < reload_first_uid)
7624 /* Check that PREV only sets the reload register. */
7625 set = single_set (prev);
7628 dst = SET_DEST (set);
7629 if (GET_CODE (dst) != REG
7630 || ! rtx_equal_p (dst, x))
7632 if (! reg_set_p (dst, PATTERN (dead_insn)))
7634 /* Check if DST was used in a later insn -
7635 it might have been inherited. */
7636 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7638 if (GET_CODE (i2) == CODE_LABEL)
7642 if (reg_referenced_p (dst, PATTERN (i2)))
7644 /* If there is a reference to the register in the current insn,
7645 it might be loaded in a non-inherited reload. If no other
7646 reload uses it, that means the register is set before
7648 if (i2 == current_insn)
7650 for (j = n_reloads - 1; j >= 0; j--)
7651 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7652 || reload_override_in[j] == dst)
7654 for (j = n_reloads - 1; j >= 0; j--)
7655 if (rld[j].in && rld[j].reg_rtx == dst)
7662 if (GET_CODE (i2) == JUMP_INSN)
7664 /* If DST is still live at CURRENT_INSN, check if it is used for
7665 any reload. Note that even if CURRENT_INSN sets DST, we still
7666 have to check the reloads. */
7667 if (i2 == current_insn)
7669 for (j = n_reloads - 1; j >= 0; j--)
7670 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7671 || reload_override_in[j] == dst)
7673 /* ??? We can't finish the loop here, because dst might be
7674 allocated to a pseudo in this block if no reload in this
7675 block needs any of the clsses containing DST - see
7676 spill_hard_reg. There is no easy way to tell this, so we
7677 have to scan till the end of the basic block. */
7679 if (reg_set_p (dst, PATTERN (i2)))
7683 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7684 reg_reloaded_contents[REGNO (dst)] = -1;
7685 /* Can't use delete_insn here because PREV might be a basic block head. */
7686 PUT_CODE (prev, NOTE);
7687 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7688 NOTE_SOURCE_FILE (prev) = 0;
7691 /* Output reload-insns to reload VALUE into RELOADREG.
7692 VALUE is an autoincrement or autodecrement RTX whose operand
7693 is a register or memory location;
7694 so reloading involves incrementing that location.
7695 IN is either identical to VALUE, or some cheaper place to reload from.
7697 INC_AMOUNT is the number to increment or decrement by (always positive).
7698 This cannot be deduced from VALUE.
7700 Return the instruction that stores into RELOADREG. */
7703 inc_for_reload (reloadreg, in, value, inc_amount)
7708 /* REG or MEM to be copied and incremented. */
7709 rtx incloc = XEXP (value, 0);
7710 /* Nonzero if increment after copying. */
7711 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7717 rtx real_in = in == value ? XEXP (in, 0) : in;
7719 /* No hard register is equivalent to this register after
7720 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7721 we could inc/dec that register as well (maybe even using it for
7722 the source), but I'm not sure it's worth worrying about. */
7723 if (GET_CODE (incloc) == REG)
7724 reg_last_reload_reg[REGNO (incloc)] = 0;
7726 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7727 inc_amount = -inc_amount;
7729 inc = GEN_INT (inc_amount);
7731 /* If this is post-increment, first copy the location to the reload reg. */
7732 if (post && real_in != reloadreg)
7733 emit_insn (gen_move_insn (reloadreg, real_in));
7737 /* See if we can directly increment INCLOC. Use a method similar to
7738 that in gen_reload. */
7740 last = get_last_insn ();
7741 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7742 gen_rtx_PLUS (GET_MODE (incloc),
7745 code = recog_memoized (add_insn);
7748 extract_insn (add_insn);
7749 if (constrain_operands (1))
7751 /* If this is a pre-increment and we have incremented the value
7752 where it lives, copy the incremented value to RELOADREG to
7753 be used as an address. */
7756 emit_insn (gen_move_insn (reloadreg, incloc));
7761 delete_insns_since (last);
7764 /* If couldn't do the increment directly, must increment in RELOADREG.
7765 The way we do this depends on whether this is pre- or post-increment.
7766 For pre-increment, copy INCLOC to the reload register, increment it
7767 there, then save back. */
7771 if (in != reloadreg)
7772 emit_insn (gen_move_insn (reloadreg, real_in));
7773 emit_insn (gen_add2_insn (reloadreg, inc));
7774 store = emit_insn (gen_move_insn (incloc, reloadreg));
7779 Because this might be a jump insn or a compare, and because RELOADREG
7780 may not be available after the insn in an input reload, we must do
7781 the incrementation before the insn being reloaded for.
7783 We have already copied IN to RELOADREG. Increment the copy in
7784 RELOADREG, save that back, then decrement RELOADREG so it has
7785 the original value. */
7787 emit_insn (gen_add2_insn (reloadreg, inc));
7788 store = emit_insn (gen_move_insn (incloc, reloadreg));
7789 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7795 /* Return 1 if we are certain that the constraint-string STRING allows
7796 the hard register REG. Return 0 if we can't be sure of this. */
7799 constraint_accepts_reg_p (string, reg)
7804 int regno = true_regnum (reg);
7807 /* Initialize for first alternative. */
7809 /* Check that each alternative contains `g' or `r'. */
7811 switch (c = *string++)
7814 /* If an alternative lacks `g' or `r', we lose. */
7817 /* If an alternative lacks `g' or `r', we lose. */
7820 /* Initialize for next alternative. */
7825 /* Any general reg wins for this alternative. */
7826 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7830 /* Any reg in specified class wins for this alternative. */
7832 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7834 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7840 /* INSN is a no-op; delete it.
7841 If this sets the return value of the function, we must keep a USE around,
7842 in case this is in a different basic block than the final USE. Otherwise,
7843 we could loose important register lifeness information on
7844 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7845 spills: subsequent passes assume that spill registers are dead at the end
7847 VALUE must be the return value in such a case, NULL otherwise. */
7849 reload_cse_delete_noop_set (insn, value)
7854 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7855 INSN_CODE (insn) = -1;
7856 REG_NOTES (insn) = NULL_RTX;
7860 PUT_CODE (insn, NOTE);
7861 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7862 NOTE_SOURCE_FILE (insn) = 0;
7866 /* See whether a single set SET is a noop. */
7868 reload_cse_noop_set_p (set)
7871 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7874 /* Try to simplify INSN. */
7876 reload_cse_simplify (insn)
7879 rtx body = PATTERN (insn);
7881 if (GET_CODE (body) == SET)
7884 if (reload_cse_noop_set_p (body))
7886 rtx value = SET_DEST (body);
7887 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7889 reload_cse_delete_noop_set (insn, value);
7893 /* It's not a no-op, but we can try to simplify it. */
7894 count += reload_cse_simplify_set (body, insn);
7897 apply_change_group ();
7899 reload_cse_simplify_operands (insn);
7901 else if (GET_CODE (body) == PARALLEL)
7905 rtx value = NULL_RTX;
7907 /* If every action in a PARALLEL is a noop, we can delete
7908 the entire PARALLEL. */
7909 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7911 rtx part = XVECEXP (body, 0, i);
7912 if (GET_CODE (part) == SET)
7914 if (! reload_cse_noop_set_p (part))
7916 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7920 value = SET_DEST (part);
7923 else if (GET_CODE (part) != CLOBBER)
7929 reload_cse_delete_noop_set (insn, value);
7930 /* We're done with this insn. */
7934 /* It's not a no-op, but we can try to simplify it. */
7935 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7936 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7937 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7940 apply_change_group ();
7942 reload_cse_simplify_operands (insn);
7946 /* Do a very simple CSE pass over the hard registers.
7948 This function detects no-op moves where we happened to assign two
7949 different pseudo-registers to the same hard register, and then
7950 copied one to the other. Reload will generate a useless
7951 instruction copying a register to itself.
7953 This function also detects cases where we load a value from memory
7954 into two different registers, and (if memory is more expensive than
7955 registers) changes it to simply copy the first register into the
7958 Another optimization is performed that scans the operands of each
7959 instruction to see whether the value is already available in a
7960 hard register. It then replaces the operand with the hard register
7961 if possible, much like an optional reload would. */
7964 reload_cse_regs_1 (first)
7970 init_alias_analysis ();
7972 for (insn = first; insn; insn = NEXT_INSN (insn))
7975 reload_cse_simplify (insn);
7977 cselib_process_insn (insn);
7981 end_alias_analysis ();
7985 /* Call cse / combine like post-reload optimization phases.
7986 FIRST is the first instruction. */
7988 reload_cse_regs (first)
7991 reload_cse_regs_1 (first);
7993 reload_cse_move2add (first);
7994 if (flag_expensive_optimizations)
7995 reload_cse_regs_1 (first);
7998 /* Try to simplify a single SET instruction. SET is the set pattern.
7999 INSN is the instruction it came from.
8000 This function only handles one case: if we set a register to a value
8001 which is not a register, we try to find that value in some other register
8002 and change the set into a register copy. */
8005 reload_cse_simplify_set (set, insn)
8012 enum reg_class dclass;
8015 struct elt_loc_list *l;
8017 dreg = true_regnum (SET_DEST (set));
8021 src = SET_SRC (set);
8022 if (side_effects_p (src) || true_regnum (src) >= 0)
8025 dclass = REGNO_REG_CLASS (dreg);
8027 /* If memory loads are cheaper than register copies, don't change them. */
8028 if (GET_CODE (src) == MEM)
8029 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8030 else if (CONSTANT_P (src))
8031 old_cost = rtx_cost (src, SET);
8032 else if (GET_CODE (src) == REG)
8033 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8036 old_cost = rtx_cost (src, SET);
8038 val = cselib_lookup (src, VOIDmode, 0);
8041 for (l = val->locs; l; l = l->next)
8044 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8045 this_cost = rtx_cost (l->loc, SET);
8046 else if (GET_CODE (l->loc) == REG)
8047 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8051 /* If equal costs, prefer registers over anything else. That tends to
8052 lead to smaller instructions on some machines. */
8053 if ((this_cost < old_cost
8054 || (this_cost == old_cost
8055 && GET_CODE (l->loc) == REG
8056 && GET_CODE (SET_SRC (set)) != REG))
8057 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8058 old_cost = this_cost, did_change = 1;
8064 /* Try to replace operands in INSN with equivalent values that are already
8065 in registers. This can be viewed as optional reloading.
8067 For each non-register operand in the insn, see if any hard regs are
8068 known to be equivalent to that operand. Record the alternatives which
8069 can accept these hard registers. Among all alternatives, select the
8070 ones which are better or equal to the one currently matching, where
8071 "better" is in terms of '?' and '!' constraints. Among the remaining
8072 alternatives, select the one which replaces most operands with
8076 reload_cse_simplify_operands (insn)
8081 /* For each operand, all registers that are equivalent to it. */
8082 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8084 const char *constraints[MAX_RECOG_OPERANDS];
8086 /* Vector recording how bad an alternative is. */
8087 int *alternative_reject;
8088 /* Vector recording how many registers can be introduced by choosing
8089 this alternative. */
8090 int *alternative_nregs;
8091 /* Array of vectors recording, for each operand and each alternative,
8092 which hard register to substitute, or -1 if the operand should be
8094 int *op_alt_regno[MAX_RECOG_OPERANDS];
8095 /* Array of alternatives, sorted in order of decreasing desirability. */
8096 int *alternative_order;
8097 rtx reg = gen_rtx_REG (VOIDmode, -1);
8099 extract_insn (insn);
8101 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8104 /* Figure out which alternative currently matches. */
8105 if (! constrain_operands (1))
8106 fatal_insn_not_found (insn);
8108 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8109 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8110 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8111 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8112 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8114 /* For each operand, find out which regs are equivalent. */
8115 for (i = 0; i < recog_data.n_operands; i++)
8118 struct elt_loc_list *l;
8120 CLEAR_HARD_REG_SET (equiv_regs[i]);
8122 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8123 right, so avoid the problem here. */
8124 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8127 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8131 for (l = v->locs; l; l = l->next)
8132 if (GET_CODE (l->loc) == REG)
8133 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8136 for (i = 0; i < recog_data.n_operands; i++)
8138 enum machine_mode mode;
8142 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8143 for (j = 0; j < recog_data.n_alternatives; j++)
8144 op_alt_regno[i][j] = -1;
8146 p = constraints[i] = recog_data.constraints[i];
8147 mode = recog_data.operand_mode[i];
8149 /* Add the reject values for each alternative given by the constraints
8150 for this operand. */
8158 alternative_reject[j] += 3;
8160 alternative_reject[j] += 300;
8163 /* We won't change operands which are already registers. We
8164 also don't want to modify output operands. */
8165 regno = true_regnum (recog_data.operand[i]);
8167 || constraints[i][0] == '='
8168 || constraints[i][0] == '+')
8171 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8173 int class = (int) NO_REGS;
8175 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8178 REGNO (reg) = regno;
8179 PUT_MODE (reg, mode);
8181 /* We found a register equal to this operand. Now look for all
8182 alternatives that can accept this register and have not been
8183 assigned a register they can use yet. */
8192 case '=': case '+': case '?':
8193 case '#': case '&': case '!':
8195 case '0': case '1': case '2': case '3': case '4':
8196 case '5': case '6': case '7': case '8': case '9':
8197 case 'm': case '<': case '>': case 'V': case 'o':
8198 case 'E': case 'F': case 'G': case 'H':
8199 case 's': case 'i': case 'n':
8200 case 'I': case 'J': case 'K': case 'L':
8201 case 'M': case 'N': case 'O': case 'P':
8203 /* These don't say anything we care about. */
8207 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8212 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8215 case ',': case '\0':
8216 /* See if REGNO fits this alternative, and set it up as the
8217 replacement register if we don't have one for this
8218 alternative yet and the operand being replaced is not
8219 a cheap CONST_INT. */
8220 if (op_alt_regno[i][j] == -1
8221 && reg_fits_class_p (reg, class, 0, mode)
8222 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8223 || (rtx_cost (recog_data.operand[i], SET)
8224 > rtx_cost (reg, SET))))
8226 alternative_nregs[j]++;
8227 op_alt_regno[i][j] = regno;
8239 /* Record all alternatives which are better or equal to the currently
8240 matching one in the alternative_order array. */
8241 for (i = j = 0; i < recog_data.n_alternatives; i++)
8242 if (alternative_reject[i] <= alternative_reject[which_alternative])
8243 alternative_order[j++] = i;
8244 recog_data.n_alternatives = j;
8246 /* Sort it. Given a small number of alternatives, a dumb algorithm
8247 won't hurt too much. */
8248 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8251 int best_reject = alternative_reject[alternative_order[i]];
8252 int best_nregs = alternative_nregs[alternative_order[i]];
8255 for (j = i + 1; j < recog_data.n_alternatives; j++)
8257 int this_reject = alternative_reject[alternative_order[j]];
8258 int this_nregs = alternative_nregs[alternative_order[j]];
8260 if (this_reject < best_reject
8261 || (this_reject == best_reject && this_nregs < best_nregs))
8264 best_reject = this_reject;
8265 best_nregs = this_nregs;
8269 tmp = alternative_order[best];
8270 alternative_order[best] = alternative_order[i];
8271 alternative_order[i] = tmp;
8274 /* Substitute the operands as determined by op_alt_regno for the best
8276 j = alternative_order[0];
8278 for (i = 0; i < recog_data.n_operands; i++)
8280 enum machine_mode mode = recog_data.operand_mode[i];
8281 if (op_alt_regno[i][j] == -1)
8284 validate_change (insn, recog_data.operand_loc[i],
8285 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8288 for (i = recog_data.n_dups - 1; i >= 0; i--)
8290 int op = recog_data.dup_num[i];
8291 enum machine_mode mode = recog_data.operand_mode[op];
8293 if (op_alt_regno[op][j] == -1)
8296 validate_change (insn, recog_data.dup_loc[i],
8297 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8300 return apply_change_group ();
8303 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8305 This code might also be useful when reload gave up on reg+reg addresssing
8306 because of clashes between the return register and INDEX_REG_CLASS. */
8308 /* The maximum number of uses of a register we can keep track of to
8309 replace them with reg+reg addressing. */
8310 #define RELOAD_COMBINE_MAX_USES 6
8312 /* INSN is the insn where a register has ben used, and USEP points to the
8313 location of the register within the rtl. */
8314 struct reg_use { rtx insn, *usep; };
8316 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8317 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8318 indicates where it becomes live again.
8319 Otherwise, USE_INDEX is the index of the last encountered use of the
8320 register (which is first among these we have seen since we scan backwards),
8321 OFFSET contains the constant offset that is added to the register in
8322 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8323 last, of these uses.
8324 STORE_RUID is always meaningful if we only want to use a value in a
8325 register in a different place: it denotes the next insn in the insn
8326 stream (i.e. the last ecountered) that sets or clobbers the register. */
8329 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8334 } reg_state[FIRST_PSEUDO_REGISTER];
8336 /* Reverse linear uid. This is increased in reload_combine while scanning
8337 the instructions from last to first. It is used to set last_label_ruid
8338 and the store_ruid / use_ruid fields in reg_state. */
8339 static int reload_combine_ruid;
8341 #define LABEL_LIVE(LABEL) \
8342 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8348 int first_index_reg = 1, last_index_reg = 0;
8351 int last_label_ruid;
8352 int min_labelno, n_labels;
8353 HARD_REG_SET ever_live_at_start, *label_live;
8355 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8356 reload has already used it where appropriate, so there is no use in
8357 trying to generate it now. */
8358 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8361 /* To avoid wasting too much time later searching for an index register,
8362 determine the minimum and maximum index register numbers. */
8363 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8364 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8366 if (! first_index_reg)
8367 first_index_reg = r;
8372 /* If no index register is available, we can quit now. */
8373 if (first_index_reg > last_index_reg)
8376 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8377 information is a bit fuzzy immediately after reload, but it's
8378 still good enough to determine which registers are live at a jump
8380 min_labelno = get_first_label_num ();
8381 n_labels = max_label_num () - min_labelno;
8382 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8383 CLEAR_HARD_REG_SET (ever_live_at_start);
8385 for (i = n_basic_blocks - 1; i >= 0; i--)
8387 insn = BLOCK_HEAD (i);
8388 if (GET_CODE (insn) == CODE_LABEL)
8392 REG_SET_TO_HARD_REG_SET (live,
8393 BASIC_BLOCK (i)->global_live_at_start);
8394 compute_use_by_pseudos (&live,
8395 BASIC_BLOCK (i)->global_live_at_start);
8396 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8397 IOR_HARD_REG_SET (ever_live_at_start, live);
8401 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8402 last_label_ruid = reload_combine_ruid = 0;
8403 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8405 reg_state[r].store_ruid = reload_combine_ruid;
8407 reg_state[r].use_index = -1;
8409 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8412 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8416 /* We cannot do our optimization across labels. Invalidating all the use
8417 information we have would be costly, so we just note where the label
8418 is and then later disable any optimization that would cross it. */
8419 if (GET_CODE (insn) == CODE_LABEL)
8420 last_label_ruid = reload_combine_ruid;
8421 else if (GET_CODE (insn) == BARRIER)
8422 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8423 if (! fixed_regs[r])
8424 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8426 if (! INSN_P (insn))
8429 reload_combine_ruid++;
8431 /* Look for (set (REGX) (CONST_INT))
8432 (set (REGX) (PLUS (REGX) (REGY)))
8434 ... (MEM (REGX)) ...
8436 (set (REGZ) (CONST_INT))
8438 ... (MEM (PLUS (REGZ) (REGY)))... .
8440 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8441 and that we know all uses of REGX before it dies. */
8442 set = single_set (insn);
8444 && GET_CODE (SET_DEST (set)) == REG
8445 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8446 GET_MODE (SET_DEST (set)))
8448 && GET_CODE (SET_SRC (set)) == PLUS
8449 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8450 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8451 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8453 rtx reg = SET_DEST (set);
8454 rtx plus = SET_SRC (set);
8455 rtx base = XEXP (plus, 1);
8456 rtx prev = prev_nonnote_insn (insn);
8457 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8458 unsigned int regno = REGNO (reg);
8459 rtx const_reg = NULL_RTX;
8460 rtx reg_sum = NULL_RTX;
8462 /* Now, we need an index register.
8463 We'll set index_reg to this index register, const_reg to the
8464 register that is to be loaded with the constant
8465 (denoted as REGZ in the substitution illustration above),
8466 and reg_sum to the register-register that we want to use to
8467 substitute uses of REG (typically in MEMs) with.
8468 First check REG and BASE for being index registers;
8469 we can use them even if they are not dead. */
8470 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8471 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8479 /* Otherwise, look for a free index register. Since we have
8480 checked above that neiter REG nor BASE are index registers,
8481 if we find anything at all, it will be different from these
8483 for (i = first_index_reg; i <= last_index_reg; i++)
8485 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8487 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8488 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8489 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8491 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8493 const_reg = index_reg;
8494 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8500 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8501 (REGY), i.e. BASE, is not clobbered before the last use we'll
8504 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8505 && rtx_equal_p (SET_DEST (prev_set), reg)
8506 && reg_state[regno].use_index >= 0
8507 && (reg_state[REGNO (base)].store_ruid
8508 <= reg_state[regno].use_ruid)
8513 /* Change destination register and, if necessary, the
8514 constant value in PREV, the constant loading instruction. */
8515 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8516 if (reg_state[regno].offset != const0_rtx)
8517 validate_change (prev,
8518 &SET_SRC (prev_set),
8519 GEN_INT (INTVAL (SET_SRC (prev_set))
8520 + INTVAL (reg_state[regno].offset)),
8523 /* Now for every use of REG that we have recorded, replace REG
8525 for (i = reg_state[regno].use_index;
8526 i < RELOAD_COMBINE_MAX_USES; i++)
8527 validate_change (reg_state[regno].reg_use[i].insn,
8528 reg_state[regno].reg_use[i].usep,
8531 if (apply_change_group ())
8535 /* Delete the reg-reg addition. */
8536 PUT_CODE (insn, NOTE);
8537 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8538 NOTE_SOURCE_FILE (insn) = 0;
8540 if (reg_state[regno].offset != const0_rtx)
8541 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8543 for (np = ®_NOTES (prev); *np;)
8545 if (REG_NOTE_KIND (*np) == REG_EQUAL
8546 || REG_NOTE_KIND (*np) == REG_EQUIV)
8547 *np = XEXP (*np, 1);
8549 np = &XEXP (*np, 1);
8552 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8553 reg_state[REGNO (const_reg)].store_ruid
8554 = reload_combine_ruid;
8560 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8562 if (GET_CODE (insn) == CALL_INSN)
8566 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8567 if (call_used_regs[r])
8569 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8570 reg_state[r].store_ruid = reload_combine_ruid;
8573 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8574 link = XEXP (link, 1))
8575 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8577 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8579 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8581 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8582 reg_state[regno].store_ruid = reload_combine_ruid;
8585 reg_state[regno].use_index = -1;
8589 else if (GET_CODE (insn) == JUMP_INSN
8590 && GET_CODE (PATTERN (insn)) != RETURN)
8592 /* Non-spill registers might be used at the call destination in
8593 some unknown fashion, so we have to mark the unknown use. */
8596 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8597 && JUMP_LABEL (insn))
8598 live = &LABEL_LIVE (JUMP_LABEL (insn));
8600 live = &ever_live_at_start;
8602 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8603 if (TEST_HARD_REG_BIT (*live, i))
8604 reg_state[i].use_index = -1;
8607 reload_combine_note_use (&PATTERN (insn), insn);
8608 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8610 if (REG_NOTE_KIND (note) == REG_INC
8611 && GET_CODE (XEXP (note, 0)) == REG)
8613 int regno = REGNO (XEXP (note, 0));
8615 reg_state[regno].store_ruid = reload_combine_ruid;
8616 reg_state[regno].use_index = -1;
8624 /* Check if DST is a register or a subreg of a register; if it is,
8625 update reg_state[regno].store_ruid and reg_state[regno].use_index
8626 accordingly. Called via note_stores from reload_combine. */
8629 reload_combine_note_store (dst, set, data)
8631 void *data ATTRIBUTE_UNUSED;
8635 enum machine_mode mode = GET_MODE (dst);
8637 if (GET_CODE (dst) == SUBREG)
8639 regno = SUBREG_WORD (dst);
8640 dst = SUBREG_REG (dst);
8642 if (GET_CODE (dst) != REG)
8644 regno += REGNO (dst);
8646 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8647 careful with registers / register parts that are not full words.
8649 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8650 if (GET_CODE (set) != SET
8651 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8652 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8653 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8655 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8657 reg_state[i].use_index = -1;
8658 reg_state[i].store_ruid = reload_combine_ruid;
8663 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8665 reg_state[i].store_ruid = reload_combine_ruid;
8666 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8671 /* XP points to a piece of rtl that has to be checked for any uses of
8673 *XP is the pattern of INSN, or a part of it.
8674 Called from reload_combine, and recursively by itself. */
8676 reload_combine_note_use (xp, insn)
8680 enum rtx_code code = x->code;
8683 rtx offset = const0_rtx; /* For the REG case below. */
8688 if (GET_CODE (SET_DEST (x)) == REG)
8690 reload_combine_note_use (&SET_SRC (x), insn);
8696 /* If this is the USE of a return value, we can't change it. */
8697 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8699 /* Mark the return register as used in an unknown fashion. */
8700 rtx reg = XEXP (x, 0);
8701 int regno = REGNO (reg);
8702 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8704 while (--nregs >= 0)
8705 reg_state[regno + nregs].use_index = -1;
8711 if (GET_CODE (SET_DEST (x)) == REG)
8716 /* We are interested in (plus (reg) (const_int)) . */
8717 if (GET_CODE (XEXP (x, 0)) != REG
8718 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8720 offset = XEXP (x, 1);
8725 int regno = REGNO (x);
8729 /* Some spurious USEs of pseudo registers might remain.
8730 Just ignore them. */
8731 if (regno >= FIRST_PSEUDO_REGISTER)
8734 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8736 /* We can't substitute into multi-hard-reg uses. */
8739 while (--nregs >= 0)
8740 reg_state[regno + nregs].use_index = -1;
8744 /* If this register is already used in some unknown fashion, we
8746 If we decrement the index from zero to -1, we can't store more
8747 uses, so this register becomes used in an unknown fashion. */
8748 use_index = --reg_state[regno].use_index;
8752 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8754 /* We have found another use for a register that is already
8755 used later. Check if the offsets match; if not, mark the
8756 register as used in an unknown fashion. */
8757 if (! rtx_equal_p (offset, reg_state[regno].offset))
8759 reg_state[regno].use_index = -1;
8765 /* This is the first use of this register we have seen since we
8766 marked it as dead. */
8767 reg_state[regno].offset = offset;
8768 reg_state[regno].use_ruid = reload_combine_ruid;
8770 reg_state[regno].reg_use[use_index].insn = insn;
8771 reg_state[regno].reg_use[use_index].usep = xp;
8779 /* Recursively process the components of X. */
8780 fmt = GET_RTX_FORMAT (code);
8781 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8784 reload_combine_note_use (&XEXP (x, i), insn);
8785 else if (fmt[i] == 'E')
8787 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8788 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8793 /* See if we can reduce the cost of a constant by replacing a move with
8795 /* We cannot do our optimization across labels. Invalidating all the
8796 information about register contents we have would be costly, so we
8797 use last_label_luid (local variable of reload_cse_move2add) to note
8798 where the label is and then later disable any optimization that would
8800 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8801 reg_set_luid[n] is larger than last_label_luid[n] . */
8802 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8804 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8805 reg_mode[n] to be valid.
8806 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8807 has been set to reg_offset[n] in mode reg_mode[n] .
8808 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8809 register n has been set to the sum of reg_offset[n] and register
8810 reg_base_reg[n], calculated in mode reg_mode[n] . */
8811 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8812 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8813 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8815 /* move2add_luid is linearily increased while scanning the instructions
8816 from first to last. It is used to set reg_set_luid in
8817 reload_cse_move2add and move2add_note_store. */
8818 static int move2add_luid;
8820 /* Generate a CONST_INT and force it in the range of MODE. */
8823 gen_mode_int (mode, value)
8824 enum machine_mode mode;
8825 HOST_WIDE_INT value;
8827 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8828 int width = GET_MODE_BITSIZE (mode);
8830 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8832 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8833 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8834 cval |= (HOST_WIDE_INT) -1 << width;
8836 return GEN_INT (cval);
8840 reload_cse_move2add (first)
8845 int last_label_luid;
8847 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8848 reg_set_luid[i] = 0;
8850 last_label_luid = 0;
8852 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8856 if (GET_CODE (insn) == CODE_LABEL)
8857 last_label_luid = move2add_luid;
8858 if (! INSN_P (insn))
8860 pat = PATTERN (insn);
8861 /* For simplicity, we only perform this optimization on
8862 straightforward SETs. */
8863 if (GET_CODE (pat) == SET
8864 && GET_CODE (SET_DEST (pat)) == REG)
8866 rtx reg = SET_DEST (pat);
8867 int regno = REGNO (reg);
8868 rtx src = SET_SRC (pat);
8870 /* Check if we have valid information on the contents of this
8871 register in the mode of REG. */
8872 /* ??? We don't know how zero / sign extension is handled, hence
8873 we can't go from a narrower to a wider mode. */
8874 if (reg_set_luid[regno] > last_label_luid
8875 && ((GET_MODE_SIZE (GET_MODE (reg))
8876 == GET_MODE_SIZE (reg_mode[regno]))
8877 || ((GET_MODE_SIZE (GET_MODE (reg))
8878 <= GET_MODE_SIZE (reg_mode[regno]))
8879 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8880 GET_MODE_BITSIZE (reg_mode[regno]))))
8881 && GET_CODE (reg_offset[regno]) == CONST_INT)
8883 /* Try to transform (set (REGX) (CONST_INT A))
8885 (set (REGX) (CONST_INT B))
8887 (set (REGX) (CONST_INT A))
8889 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8891 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8895 = gen_mode_int (GET_MODE (reg),
8896 INTVAL (src) - INTVAL (reg_offset[regno]));
8897 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8898 use (set (reg) (reg)) instead.
8899 We don't delete this insn, nor do we convert it into a
8900 note, to avoid losing register notes or the return
8901 value flag. jump2 already knowns how to get rid of
8903 if (new_src == const0_rtx)
8904 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8905 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8906 && have_add2_insn (GET_MODE (reg)))
8907 success = validate_change (insn, &PATTERN (insn),
8908 gen_add2_insn (reg, new_src), 0);
8909 reg_set_luid[regno] = move2add_luid;
8910 reg_mode[regno] = GET_MODE (reg);
8911 reg_offset[regno] = src;
8915 /* Try to transform (set (REGX) (REGY))
8916 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8919 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8922 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8924 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8925 else if (GET_CODE (src) == REG
8926 && reg_base_reg[regno] == (int) REGNO (src)
8927 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8929 rtx next = next_nonnote_insn (insn);
8932 set = single_set (next);
8935 && SET_DEST (set) == reg
8936 && GET_CODE (SET_SRC (set)) == PLUS
8937 && XEXP (SET_SRC (set), 0) == reg
8938 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8940 rtx src3 = XEXP (SET_SRC (set), 1);
8942 = gen_mode_int (GET_MODE (reg),
8944 - INTVAL (reg_offset[regno]));
8947 if (new_src == const0_rtx)
8948 /* See above why we create (set (reg) (reg)) here. */
8950 = validate_change (next, &SET_SRC (set), reg, 0);
8951 else if ((rtx_cost (new_src, PLUS)
8952 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
8953 && have_add2_insn (GET_MODE (reg)))
8955 = validate_change (next, &PATTERN (next),
8956 gen_add2_insn (reg, new_src), 0);
8959 /* INSN might be the first insn in a basic block
8960 if the preceding insn is a conditional jump
8961 or a possible-throwing call. */
8962 PUT_CODE (insn, NOTE);
8963 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8964 NOTE_SOURCE_FILE (insn) = 0;
8967 reg_set_luid[regno] = move2add_luid;
8968 reg_mode[regno] = GET_MODE (reg);
8969 reg_offset[regno] = src3;
8976 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8978 if (REG_NOTE_KIND (note) == REG_INC
8979 && GET_CODE (XEXP (note, 0)) == REG)
8981 /* Indicate that this register has been recently written to,
8982 but the exact contents are not available. */
8983 int regno = REGNO (XEXP (note, 0));
8984 if (regno < FIRST_PSEUDO_REGISTER)
8986 reg_set_luid[regno] = move2add_luid;
8987 reg_offset[regno] = note;
8991 note_stores (PATTERN (insn), move2add_note_store, NULL);
8992 /* If this is a CALL_INSN, all call used registers are stored with
8994 if (GET_CODE (insn) == CALL_INSN)
8996 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8998 if (call_used_regs[i])
9000 reg_set_luid[i] = move2add_luid;
9001 reg_offset[i] = insn; /* Invalidate contents. */
9008 /* SET is a SET or CLOBBER that sets DST.
9009 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9010 Called from reload_cse_move2add via note_stores. */
9013 move2add_note_store (dst, set, data)
9015 void *data ATTRIBUTE_UNUSED;
9017 unsigned int regno = 0;
9019 enum machine_mode mode = GET_MODE (dst);
9021 if (GET_CODE (dst) == SUBREG)
9023 regno = SUBREG_WORD (dst);
9024 dst = SUBREG_REG (dst);
9027 /* Some targets do argument pushes without adding REG_INC notes. */
9029 if (GET_CODE (dst) == MEM)
9031 dst = XEXP (dst, 0);
9032 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9033 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9035 regno = REGNO (XEXP (dst, 0));
9036 reg_set_luid[regno] = move2add_luid;
9037 reg_offset[regno] = dst;
9041 if (GET_CODE (dst) != REG)
9044 regno += REGNO (dst);
9046 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9047 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9048 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9049 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9051 rtx src = SET_SRC (set);
9053 reg_mode[regno] = mode;
9054 switch (GET_CODE (src))
9058 rtx src0 = XEXP (src, 0);
9060 if (GET_CODE (src0) == REG)
9062 if (REGNO (src0) != regno
9063 || reg_offset[regno] != const0_rtx)
9065 reg_base_reg[regno] = REGNO (src0);
9066 reg_set_luid[regno] = move2add_luid;
9069 reg_offset[regno] = XEXP (src, 1);
9073 reg_set_luid[regno] = move2add_luid;
9074 reg_offset[regno] = set; /* Invalidate contents. */
9079 reg_base_reg[regno] = REGNO (SET_SRC (set));
9080 reg_offset[regno] = const0_rtx;
9081 reg_set_luid[regno] = move2add_luid;
9085 reg_base_reg[regno] = -1;
9086 reg_offset[regno] = SET_SRC (set);
9087 reg_set_luid[regno] = move2add_luid;
9093 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9095 for (i = regno; i < endregno; i++)
9097 /* Indicate that this register has been recently written to,
9098 but the exact contents are not available. */
9099 reg_set_luid[i] = move2add_luid;
9100 reg_offset[i] = dst;
9107 add_auto_inc_notes (insn, x)
9111 enum rtx_code code = GET_CODE (x);
9115 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9118 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9122 /* Scan all the operand sub-expressions. */
9123 fmt = GET_RTX_FORMAT (code);
9124 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9127 add_auto_inc_notes (insn, XEXP (x, i));
9128 else if (fmt[i] == 'E')
9129 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9130 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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