1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload;
87 struct target_reload *this_target_reload = &default_target_reload;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx *reg_last_reload_reg;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs[FIRST_PSEUDO_REGISTER];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET *pseudo_previous_regs;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET *pseudo_forbidden_regs;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain *reload_insn_chain;
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254 run DCE immediately after reload, FALSE otherwise. */
255 static bool need_dce;
257 /* List of all insns needing reloads. */
258 static struct insn_chain *insns_need_reload;
260 /* This structure is used to record information about register eliminations.
261 Each array entry describes one possible way of eliminating a register
262 in favor of another. If there is more than one way of eliminating a
263 particular register, the most preferred should be specified first. */
267 int from; /* Register number to be eliminated. */
268 int to; /* Register number used as replacement. */
269 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
270 int can_eliminate; /* Nonzero if this elimination can be done. */
271 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
272 target hook in previous scan over insns
274 HOST_WIDE_INT offset; /* Current offset between the two regs. */
275 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
276 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
277 rtx from_rtx; /* REG rtx for the register to be eliminated.
278 We cannot simply compare the number since
279 we might then spuriously replace a hard
280 register corresponding to a pseudo
281 assigned to the reg to be eliminated. */
282 rtx to_rtx; /* REG rtx for the replacement. */
285 static struct elim_table *reg_eliminate = 0;
287 /* This is an intermediate structure to initialize the table. It has
288 exactly the members provided by ELIMINABLE_REGS. */
289 static const struct elim_table_1
293 } reg_eliminate_1[] =
295 /* If a set of eliminable registers was specified, define the table from it.
296 Otherwise, default to the normal case of the frame pointer being
297 replaced by the stack pointer. */
299 #ifdef ELIMINABLE_REGS
302 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
307 /* Record the number of pending eliminations that have an offset not equal
308 to their initial offset. If nonzero, we use a new copy of each
309 replacement result in any insns encountered. */
310 int num_not_at_initial_offset;
312 /* Count the number of registers that we may be able to eliminate. */
313 static int num_eliminable;
314 /* And the number of registers that are equivalent to a constant that
315 can be eliminated to frame_pointer / arg_pointer + constant. */
316 static int num_eliminable_invariants;
318 /* For each label, we record the offset of each elimination. If we reach
319 a label by more than one path and an offset differs, we cannot do the
320 elimination. This information is indexed by the difference of the
321 number of the label and the first label number. We can't offset the
322 pointer itself as this can cause problems on machines with segmented
323 memory. The first table is an array of flags that records whether we
324 have yet encountered a label and the second table is an array of arrays,
325 one entry in the latter array for each elimination. */
327 static int first_label_num;
328 static char *offsets_known_at;
329 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
331 VEC(reg_equivs_t,gc) *reg_equivs;
333 /* Stack of addresses where an rtx has been changed. We can undo the
334 changes by popping items off the stack and restoring the original
335 value at each location.
337 We use this simplistic undo capability rather than copy_rtx as copy_rtx
338 will not make a deep copy of a normally sharable rtx, such as
339 (const (plus (symbol_ref) (const_int))). If such an expression appears
340 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341 rtx expression would be changed. See PR 42431. */
345 DEF_VEC_ALLOC_P(rtx_p,heap);
346 static VEC(rtx_p,heap) *substitute_stack;
348 /* Number of labels in the current function. */
350 static int num_labels;
352 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain *);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain *, int);
357 static void find_reload_regs (struct insn_chain *);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
361 static void spill_failure (rtx, enum reg_class);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx, rtx, int);
366 static void check_eliminable_occurrences (rtx);
367 static void elimination_effects (rtx, enum machine_mode);
368 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
369 static int eliminate_regs_in_insn (rtx, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx, const_rtx, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx);
376 static void init_eliminable_invariants (rtx, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET *);
380 static void elimination_costs_in_insn (rtx);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain *);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx, const_rtx, void *);
388 static void forget_marked_reloads (regset);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
394 static int reload_reg_free_p (unsigned int, int, enum reload_type);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
397 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
399 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
400 static int allocate_reload_reg (struct insn_chain *, int, int);
401 static int conflicts_with_override (rtx);
402 static void failed_reload (rtx, int);
403 static int set_reload_reg (int, int);
404 static void choose_reload_regs_init (struct insn_chain *, rtx *);
405 static void choose_reload_regs (struct insn_chain *);
406 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
408 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
410 static void do_input_reload (struct insn_chain *, struct reload *, int);
411 static void do_output_reload (struct insn_chain *, struct reload *, int);
412 static void emit_reload_insns (struct insn_chain *);
413 static void delete_output_reload (rtx, int, int, rtx);
414 static void delete_address_reloads (rtx, rtx);
415 static void delete_address_reloads_1 (rtx, rtx, rtx);
416 static void inc_for_reload (rtx, rtx, rtx, int);
418 static void add_auto_inc_notes (rtx, rtx);
420 static void substitute (rtx *, const_rtx, rtx);
421 static bool gen_reload_chain_without_interm_reg_p (int, int);
422 static int reloads_conflict (int, int);
423 static rtx gen_reload (rtx, rtx, int, enum reload_type);
424 static rtx emit_insn_if_valid_for_reload (rtx);
426 /* Initialize the reload pass. This is called at the beginning of compilation
427 and may be called again if the target is reinitialized. */
434 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
435 Set spill_indirect_levels to the number of levels such addressing is
436 permitted, zero if it is not permitted at all. */
439 = gen_rtx_MEM (Pmode,
442 LAST_VIRTUAL_REGISTER + 1),
444 spill_indirect_levels = 0;
446 while (memory_address_p (QImode, tem))
448 spill_indirect_levels++;
449 tem = gen_rtx_MEM (Pmode, tem);
452 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
454 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
455 indirect_symref_ok = memory_address_p (QImode, tem);
457 /* See if reg+reg is a valid (and offsettable) address. */
459 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
461 tem = gen_rtx_PLUS (Pmode,
462 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
463 gen_rtx_REG (Pmode, i));
465 /* This way, we make sure that reg+reg is an offsettable address. */
466 tem = plus_constant (tem, 4);
468 if (memory_address_p (QImode, tem))
470 double_reg_address_ok = 1;
475 /* Initialize obstack for our rtl allocation. */
476 gcc_obstack_init (&reload_obstack);
477 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
479 INIT_REG_SET (&spilled_pseudos);
480 INIT_REG_SET (&changed_allocation_pseudos);
481 INIT_REG_SET (&pseudos_counted);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain *unused_insn_chains = 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain *c;
493 if (unused_insn_chains == 0)
495 c = XOBNEW (&reload_obstack, struct insn_chain);
496 INIT_REG_SET (&c->live_throughout);
497 INIT_REG_SET (&c->dead_or_set);
501 c = unused_insn_chains;
502 unused_insn_chains = c->next;
504 c->is_caller_save_insn = 0;
505 c->need_operand_change = 0;
511 /* Small utility function to set all regs in hard reg set TO which are
512 allocated to pseudos in regset FROM. */
515 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
518 reg_set_iterator rsi;
520 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
522 int r = reg_renumber[regno];
526 /* reload_combine uses the information from DF_LIVE_IN,
527 which might still contain registers that have not
528 actually been allocated since they have an
530 gcc_assert (ira_conflicts_p || reload_completed);
533 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
537 /* Replace all pseudos found in LOC with their corresponding
541 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
554 unsigned int regno = REGNO (x);
556 if (regno < FIRST_PSEUDO_REGISTER)
559 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
563 replace_pseudos_in (loc, mem_mode, usage);
567 if (reg_equiv_constant (regno))
568 *loc = reg_equiv_constant (regno);
569 else if (reg_equiv_invariant (regno))
570 *loc = reg_equiv_invariant (regno);
571 else if (reg_equiv_mem (regno))
572 *loc = reg_equiv_mem (regno);
573 else if (reg_equiv_address (regno))
574 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
577 gcc_assert (!REG_P (regno_reg_rtx[regno])
578 || REGNO (regno_reg_rtx[regno]) != regno);
579 *loc = regno_reg_rtx[regno];
584 else if (code == MEM)
586 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
590 /* Process each of our operands recursively. */
591 fmt = GET_RTX_FORMAT (code);
592 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
594 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
595 else if (*fmt == 'E')
596 for (j = 0; j < XVECLEN (x, i); j++)
597 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
600 /* Determine if the current function has an exception receiver block
601 that reaches the exit block via non-exceptional edges */
604 has_nonexceptional_receiver (void)
608 basic_block *tos, *worklist, bb;
610 /* If we're not optimizing, then just err on the safe side. */
614 /* First determine which blocks can reach exit via normal paths. */
615 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
618 bb->flags &= ~BB_REACHABLE;
620 /* Place the exit block on our worklist. */
621 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
622 *tos++ = EXIT_BLOCK_PTR;
624 /* Iterate: find everything reachable from what we've already seen. */
625 while (tos != worklist)
629 FOR_EACH_EDGE (e, ei, bb->preds)
630 if (!(e->flags & EDGE_ABNORMAL))
632 basic_block src = e->src;
634 if (!(src->flags & BB_REACHABLE))
636 src->flags |= BB_REACHABLE;
643 /* Now see if there's a reachable block with an exceptional incoming
646 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
649 /* No exceptional block reached exit unexceptionally. */
653 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
654 zero elements) to MAX_REG_NUM elements.
656 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
658 grow_reg_equivs (void)
660 int old_size = VEC_length (reg_equivs_t, reg_equivs);
661 int max_regno = max_reg_num ();
664 VEC_reserve (reg_equivs_t, gc, reg_equivs, max_regno);
665 for (i = old_size; i < max_regno; i++)
667 VEC_quick_insert (reg_equivs_t, reg_equivs, i, 0);
668 memset (VEC_index (reg_equivs_t, reg_equivs, i), 0, sizeof (reg_equivs_t));
674 /* Global variables used by reload and its subroutines. */
676 /* The current basic block while in calculate_elim_costs_all_insns. */
677 static basic_block elim_bb;
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed;
683 /* Set by alter_regs if we spilled a register to the stack. */
684 static bool something_was_spilled;
686 /* Nonzero means we couldn't get enough spill regs. */
689 /* Temporary array of pseudo-register number. */
690 static int *temp_pseudo_reg_arr;
692 /* Main entry point for the reload pass.
694 FIRST is the first insn of the function being compiled.
696 GLOBAL nonzero means we were called from global_alloc
697 and should attempt to reallocate any pseudoregs that we
698 displace from hard regs we will use for reloads.
699 If GLOBAL is zero, we do not have enough information to do that,
700 so any pseudo reg that is spilled must go to the stack.
702 Return value is TRUE if reload likely left dead insns in the
703 stream and a DCE pass should be run to elimiante them. Else the
704 return value is FALSE. */
707 reload (rtx first, int global)
711 struct elim_table *ep;
715 /* Make sure even insns with volatile mem refs are recognizable. */
720 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
722 /* Make sure that the last insn in the chain
723 is not something that needs reloading. */
724 emit_note (NOTE_INSN_DELETED);
726 /* Enable find_equiv_reg to distinguish insns made by reload. */
727 reload_first_uid = get_max_uid ();
729 #ifdef SECONDARY_MEMORY_NEEDED
730 /* Initialize the secondary memory table. */
731 clear_secondary_mem ();
734 /* We don't have a stack slot for any spill reg yet. */
735 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
736 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
738 /* Initialize the save area information for caller-save, in case some
742 /* Compute which hard registers are now in use
743 as homes for pseudo registers.
744 This is done here rather than (eg) in global_alloc
745 because this point is reached even if not optimizing. */
746 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
749 /* A function that has a nonlocal label that can reach the exit
750 block via non-exceptional paths must save all call-saved
752 if (cfun->has_nonlocal_label
753 && has_nonexceptional_receiver ())
754 crtl->saves_all_registers = 1;
756 if (crtl->saves_all_registers)
757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
758 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
759 df_set_regs_ever_live (i, true);
761 /* Find all the pseudo registers that didn't get hard regs
762 but do have known equivalent constants or memory slots.
763 These include parameters (known equivalent to parameter slots)
764 and cse'd or loop-moved constant memory addresses.
766 Record constant equivalents in reg_equiv_constant
767 so they will be substituted by find_reloads.
768 Record memory equivalents in reg_mem_equiv so they can
769 be substituted eventually by altering the REG-rtx's. */
772 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
773 reg_old_renumber = XCNEWVEC (short, max_regno);
774 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
775 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
776 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
778 CLEAR_HARD_REG_SET (bad_spill_regs_global);
780 init_eliminable_invariants (first, true);
783 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
784 stack slots to the pseudos that lack hard regs or equivalents.
785 Do not touch virtual registers. */
787 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
788 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
789 temp_pseudo_reg_arr[n++] = i;
792 /* Ask IRA to order pseudo-registers for better stack slot
794 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
796 for (i = 0; i < n; i++)
797 alter_reg (temp_pseudo_reg_arr[i], -1, false);
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
807 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
809 maybe_fix_stack_asms ();
811 insns_need_reload = 0;
812 something_needs_elimination = 0;
814 /* Initialize to -1, which means take the first spill register. */
817 /* Spill any hard regs that we know we can't eliminate. */
818 CLEAR_HARD_REG_SET (used_spill_regs);
819 /* There can be multiple ways to eliminate a register;
820 they should be listed adjacently.
821 Elimination for any register fails only if all possible ways fail. */
822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
825 int can_eliminate = 0;
828 can_eliminate |= ep->can_eliminate;
831 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
833 spill_hard_reg (from, 1);
836 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
837 if (frame_pointer_needed)
838 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
840 finish_spills (global);
842 /* From now on, we may need to generate moves differently. We may also
843 allow modifications of insns which cause them to not be recognized.
844 Any such modifications will be cleaned up during reload itself. */
845 reload_in_progress = 1;
847 /* This loop scans the entire function each go-round
848 and repeats until one repetition spills no additional hard regs. */
851 int something_changed;
853 HOST_WIDE_INT starting_frame_size;
855 starting_frame_size = get_frame_size ();
856 something_was_spilled = false;
858 set_initial_elim_offsets ();
859 set_initial_label_offsets ();
861 /* For each pseudo register that has an equivalent location defined,
862 try to eliminate any eliminable registers (such as the frame pointer)
863 assuming initial offsets for the replacement register, which
866 If the resulting location is directly addressable, substitute
867 the MEM we just got directly for the old REG.
869 If it is not addressable but is a constant or the sum of a hard reg
870 and constant, it is probably not addressable because the constant is
871 out of range, in that case record the address; we will generate
872 hairy code to compute the address in a register each time it is
873 needed. Similarly if it is a hard register, but one that is not
874 valid as an address register.
876 If the location is not addressable, but does not have one of the
877 above forms, assign a stack slot. We have to do this to avoid the
878 potential of producing lots of reloads if, e.g., a location involves
879 a pseudo that didn't get a hard register and has an equivalent memory
880 location that also involves a pseudo that didn't get a hard register.
882 Perhaps at some point we will improve reload_when_needed handling
883 so this problem goes away. But that's very hairy. */
885 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
886 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
888 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
891 if (strict_memory_address_addr_space_p
892 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
894 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
895 else if (CONSTANT_P (XEXP (x, 0))
896 || (REG_P (XEXP (x, 0))
897 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
898 || (GET_CODE (XEXP (x, 0)) == PLUS
899 && REG_P (XEXP (XEXP (x, 0), 0))
900 && (REGNO (XEXP (XEXP (x, 0), 0))
901 < FIRST_PSEUDO_REGISTER)
902 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
903 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
906 /* Make a new stack slot. Then indicate that something
907 changed so we go back and recompute offsets for
908 eliminable registers because the allocation of memory
909 below might change some offset. reg_equiv_{mem,address}
910 will be set up for this pseudo on the next pass around
912 reg_equiv_memory_loc (i) = 0;
913 reg_equiv_init (i) = 0;
914 alter_reg (i, -1, true);
918 if (caller_save_needed)
921 /* If we allocated another stack slot, redo elimination bookkeeping. */
922 if (something_was_spilled || starting_frame_size != get_frame_size ())
924 if (starting_frame_size && crtl->stack_alignment_needed)
926 /* If we have a stack frame, we must align it now. The
927 stack size may be a part of the offset computation for
928 register elimination. So if this changes the stack size,
929 then repeat the elimination bookkeeping. We don't
930 realign when there is no stack, as that will cause a
931 stack frame when none is needed should
932 STARTING_FRAME_OFFSET not be already aligned to
934 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
935 if (starting_frame_size != get_frame_size ())
939 if (caller_save_needed)
941 save_call_clobbered_regs ();
942 /* That might have allocated new insn_chain structures. */
943 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
946 calculate_needs_all_insns (global);
948 if (! ira_conflicts_p)
949 /* Don't do it for IRA. We need this info because we don't
950 change live_throughout and dead_or_set for chains when IRA
952 CLEAR_REG_SET (&spilled_pseudos);
956 something_changed = 0;
958 /* If we allocated any new memory locations, make another pass
959 since it might have changed elimination offsets. */
960 if (something_was_spilled || starting_frame_size != get_frame_size ())
961 something_changed = 1;
963 /* Even if the frame size remained the same, we might still have
964 changed elimination offsets, e.g. if find_reloads called
965 force_const_mem requiring the back end to allocate a constant
966 pool base register that needs to be saved on the stack. */
967 else if (!verify_initial_elim_offsets ())
968 something_changed = 1;
971 HARD_REG_SET to_spill;
972 CLEAR_HARD_REG_SET (to_spill);
973 update_eliminables (&to_spill);
974 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
977 if (TEST_HARD_REG_BIT (to_spill, i))
979 spill_hard_reg (i, 1);
982 /* Regardless of the state of spills, if we previously had
983 a register that we thought we could eliminate, but now can
984 not eliminate, we must run another pass.
986 Consider pseudos which have an entry in reg_equiv_* which
987 reference an eliminable register. We must make another pass
988 to update reg_equiv_* so that we do not substitute in the
989 old value from when we thought the elimination could be
991 something_changed = 1;
995 select_reload_regs ();
999 if (insns_need_reload != 0 || did_spill)
1000 something_changed |= finish_spills (global);
1002 if (! something_changed)
1005 if (caller_save_needed)
1006 delete_caller_save_insns ();
1008 obstack_free (&reload_obstack, reload_firstobj);
1011 /* If global-alloc was run, notify it of any register eliminations we have
1014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1015 if (ep->can_eliminate)
1016 mark_elimination (ep->from, ep->to);
1018 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1019 If that insn didn't set the register (i.e., it copied the register to
1020 memory), just delete that insn instead of the equivalencing insn plus
1021 anything now dead. If we call delete_dead_insn on that insn, we may
1022 delete the insn that actually sets the register if the register dies
1023 there and that is incorrect. */
1025 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1027 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1030 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1032 rtx equiv_insn = XEXP (list, 0);
1034 /* If we already deleted the insn or if it may trap, we can't
1035 delete it. The latter case shouldn't happen, but can
1036 if an insn has a variable address, gets a REG_EH_REGION
1037 note added to it, and then gets converted into a load
1038 from a constant address. */
1039 if (NOTE_P (equiv_insn)
1040 || can_throw_internal (equiv_insn))
1042 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1043 delete_dead_insn (equiv_insn);
1045 SET_INSN_DELETED (equiv_insn);
1050 /* Use the reload registers where necessary
1051 by generating move instructions to move the must-be-register
1052 values into or out of the reload registers. */
1054 if (insns_need_reload != 0 || something_needs_elimination
1055 || something_needs_operands_changed)
1057 HOST_WIDE_INT old_frame_size = get_frame_size ();
1059 reload_as_needed (global);
1061 gcc_assert (old_frame_size == get_frame_size ());
1063 gcc_assert (verify_initial_elim_offsets ());
1066 /* If we were able to eliminate the frame pointer, show that it is no
1067 longer live at the start of any basic block. If it ls live by
1068 virtue of being in a pseudo, that pseudo will be marked live
1069 and hence the frame pointer will be known to be live via that
1072 if (! frame_pointer_needed)
1074 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1076 /* Come here (with failure set nonzero) if we can't get enough spill
1080 CLEAR_REG_SET (&changed_allocation_pseudos);
1081 CLEAR_REG_SET (&spilled_pseudos);
1082 reload_in_progress = 0;
1084 /* Now eliminate all pseudo regs by modifying them into
1085 their equivalent memory references.
1086 The REG-rtx's for the pseudos are modified in place,
1087 so all insns that used to refer to them now refer to memory.
1089 For a reg that has a reg_equiv_address, all those insns
1090 were changed by reloading so that no insns refer to it any longer;
1091 but the DECL_RTL of a variable decl may refer to it,
1092 and if so this causes the debugging info to mention the variable. */
1094 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1098 if (reg_equiv_mem (i))
1099 addr = XEXP (reg_equiv_mem (i), 0);
1101 if (reg_equiv_address (i))
1102 addr = reg_equiv_address (i);
1106 if (reg_renumber[i] < 0)
1108 rtx reg = regno_reg_rtx[i];
1110 REG_USERVAR_P (reg) = 0;
1111 PUT_CODE (reg, MEM);
1112 XEXP (reg, 0) = addr;
1113 if (reg_equiv_memory_loc (i))
1114 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1117 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1118 MEM_ATTRS (reg) = 0;
1120 MEM_NOTRAP_P (reg) = 1;
1122 else if (reg_equiv_mem (i))
1123 XEXP (reg_equiv_mem (i), 0) = addr;
1126 /* We don't want complex addressing modes in debug insns
1127 if simpler ones will do, so delegitimize equivalences
1129 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1131 rtx reg = regno_reg_rtx[i];
1135 if (reg_equiv_constant (i))
1136 equiv = reg_equiv_constant (i);
1137 else if (reg_equiv_invariant (i))
1138 equiv = reg_equiv_invariant (i);
1139 else if (reg && MEM_P (reg))
1140 equiv = targetm.delegitimize_address (reg);
1141 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1147 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1149 insn = DF_REF_INSN (use);
1151 /* Make sure the next ref is for a different instruction,
1152 so that we're not affected by the rescan. */
1153 next = DF_REF_NEXT_REG (use);
1154 while (next && DF_REF_INSN (next) == insn)
1155 next = DF_REF_NEXT_REG (next);
1157 if (DEBUG_INSN_P (insn))
1161 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1162 df_insn_rescan_debug_internal (insn);
1165 INSN_VAR_LOCATION_LOC (insn)
1166 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1173 /* We must set reload_completed now since the cleanup_subreg_operands call
1174 below will re-recognize each insn and reload may have generated insns
1175 which are only valid during and after reload. */
1176 reload_completed = 1;
1178 /* Make a pass over all the insns and delete all USEs which we inserted
1179 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1180 notes. Delete all CLOBBER insns, except those that refer to the return
1181 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1182 from misarranging variable-array code, and simplify (subreg (reg))
1183 operands. Strip and regenerate REG_INC notes that may have been moved
1186 for (insn = first; insn; insn = NEXT_INSN (insn))
1192 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1193 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1195 if ((GET_CODE (PATTERN (insn)) == USE
1196 /* We mark with QImode USEs introduced by reload itself. */
1197 && (GET_MODE (insn) == QImode
1198 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1199 || (GET_CODE (PATTERN (insn)) == CLOBBER
1200 && (!MEM_P (XEXP (PATTERN (insn), 0))
1201 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1202 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1203 && XEXP (XEXP (PATTERN (insn), 0), 0)
1204 != stack_pointer_rtx))
1205 && (!REG_P (XEXP (PATTERN (insn), 0))
1206 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1212 /* Some CLOBBERs may survive until here and still reference unassigned
1213 pseudos with const equivalent, which may in turn cause ICE in later
1214 passes if the reference remains in place. */
1215 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1216 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1217 VOIDmode, PATTERN (insn));
1219 /* Discard obvious no-ops, even without -O. This optimization
1220 is fast and doesn't interfere with debugging. */
1221 if (NONJUMP_INSN_P (insn)
1222 && GET_CODE (PATTERN (insn)) == SET
1223 && REG_P (SET_SRC (PATTERN (insn)))
1224 && REG_P (SET_DEST (PATTERN (insn)))
1225 && (REGNO (SET_SRC (PATTERN (insn)))
1226 == REGNO (SET_DEST (PATTERN (insn)))))
1232 pnote = ®_NOTES (insn);
1235 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1236 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1237 || REG_NOTE_KIND (*pnote) == REG_INC)
1238 *pnote = XEXP (*pnote, 1);
1240 pnote = &XEXP (*pnote, 1);
1244 add_auto_inc_notes (insn, PATTERN (insn));
1247 /* Simplify (subreg (reg)) if it appears as an operand. */
1248 cleanup_subreg_operands (insn);
1250 /* Clean up invalid ASMs so that they don't confuse later passes.
1252 if (asm_noperands (PATTERN (insn)) >= 0)
1254 extract_insn (insn);
1255 if (!constrain_operands (1))
1257 error_for_asm (insn,
1258 "%<asm%> operand has impossible constraints");
1265 /* If we are doing generic stack checking, give a warning if this
1266 function's frame size is larger than we expect. */
1267 if (flag_stack_check == GENERIC_STACK_CHECK)
1269 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1270 static int verbose_warned = 0;
1272 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1273 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1274 size += UNITS_PER_WORD;
1276 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1278 warning (0, "frame size too large for reliable stack checking");
1279 if (! verbose_warned)
1281 warning (0, "try reducing the number of local variables");
1287 free (temp_pseudo_reg_arr);
1289 /* Indicate that we no longer have known memory locations or constants. */
1292 free (reg_max_ref_width);
1293 free (reg_old_renumber);
1294 free (pseudo_previous_regs);
1295 free (pseudo_forbidden_regs);
1297 CLEAR_HARD_REG_SET (used_spill_regs);
1298 for (i = 0; i < n_spills; i++)
1299 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1301 /* Free all the insn_chain structures at once. */
1302 obstack_free (&reload_obstack, reload_startobj);
1303 unused_insn_chains = 0;
1305 inserted = fixup_abnormal_edges ();
1307 /* We've possibly turned single trapping insn into multiple ones. */
1308 if (cfun->can_throw_non_call_exceptions)
1311 blocks = sbitmap_alloc (last_basic_block);
1312 sbitmap_ones (blocks);
1313 find_many_sub_basic_blocks (blocks);
1314 sbitmap_free (blocks);
1318 commit_edge_insertions ();
1320 /* Replacing pseudos with their memory equivalents might have
1321 created shared rtx. Subsequent passes would get confused
1322 by this, so unshare everything here. */
1323 unshare_all_rtl_again (first);
1325 #ifdef STACK_BOUNDARY
1326 /* init_emit has set the alignment of the hard frame pointer
1327 to STACK_BOUNDARY. It is very likely no longer valid if
1328 the hard frame pointer was used for register allocation. */
1329 if (!frame_pointer_needed)
1330 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1333 VEC_free (rtx_p, heap, substitute_stack);
1335 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1337 reload_completed = !failure;
1342 /* Yet another special case. Unfortunately, reg-stack forces people to
1343 write incorrect clobbers in asm statements. These clobbers must not
1344 cause the register to appear in bad_spill_regs, otherwise we'll call
1345 fatal_insn later. We clear the corresponding regnos in the live
1346 register sets to avoid this.
1347 The whole thing is rather sick, I'm afraid. */
1350 maybe_fix_stack_asms (void)
1353 const char *constraints[MAX_RECOG_OPERANDS];
1354 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1355 struct insn_chain *chain;
1357 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1360 HARD_REG_SET clobbered, allowed;
1363 if (! INSN_P (chain->insn)
1364 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1366 pat = PATTERN (chain->insn);
1367 if (GET_CODE (pat) != PARALLEL)
1370 CLEAR_HARD_REG_SET (clobbered);
1371 CLEAR_HARD_REG_SET (allowed);
1373 /* First, make a mask of all stack regs that are clobbered. */
1374 for (i = 0; i < XVECLEN (pat, 0); i++)
1376 rtx t = XVECEXP (pat, 0, i);
1377 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1378 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1381 /* Get the operand values and constraints out of the insn. */
1382 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1383 constraints, operand_mode, NULL);
1385 /* For every operand, see what registers are allowed. */
1386 for (i = 0; i < noperands; i++)
1388 const char *p = constraints[i];
1389 /* For every alternative, we compute the class of registers allowed
1390 for reloading in CLS, and merge its contents into the reg set
1392 int cls = (int) NO_REGS;
1398 if (c == '\0' || c == ',' || c == '#')
1400 /* End of one alternative - mark the regs in the current
1401 class, and reset the class. */
1402 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1408 } while (c != '\0' && c != ',');
1416 case '=': case '+': case '*': case '%': case '?': case '!':
1417 case '0': case '1': case '2': case '3': case '4': case '<':
1418 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1419 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1420 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1421 case TARGET_MEM_CONSTRAINT:
1425 cls = (int) reg_class_subunion[cls]
1426 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1431 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1435 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1436 cls = (int) reg_class_subunion[cls]
1437 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1439 cls = (int) reg_class_subunion[cls]
1440 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1442 p += CONSTRAINT_LEN (c, p);
1445 /* Those of the registers which are clobbered, but allowed by the
1446 constraints, must be usable as reload registers. So clear them
1447 out of the life information. */
1448 AND_HARD_REG_SET (allowed, clobbered);
1449 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1450 if (TEST_HARD_REG_BIT (allowed, i))
1452 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1453 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1460 /* Copy the global variables n_reloads and rld into the corresponding elts
1463 copy_reloads (struct insn_chain *chain)
1465 chain->n_reloads = n_reloads;
1466 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1467 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1468 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1471 /* Walk the chain of insns, and determine for each whether it needs reloads
1472 and/or eliminations. Build the corresponding insns_need_reload list, and
1473 set something_needs_elimination as appropriate. */
1475 calculate_needs_all_insns (int global)
1477 struct insn_chain **pprev_reload = &insns_need_reload;
1478 struct insn_chain *chain, *next = 0;
1480 something_needs_elimination = 0;
1482 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1483 for (chain = reload_insn_chain; chain != 0; chain = next)
1485 rtx insn = chain->insn;
1489 /* Clear out the shortcuts. */
1490 chain->n_reloads = 0;
1491 chain->need_elim = 0;
1492 chain->need_reload = 0;
1493 chain->need_operand_change = 0;
1495 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1496 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1497 what effects this has on the known offsets at labels. */
1499 if (LABEL_P (insn) || JUMP_P (insn)
1500 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1501 set_label_offsets (insn, insn, 0);
1505 rtx old_body = PATTERN (insn);
1506 int old_code = INSN_CODE (insn);
1507 rtx old_notes = REG_NOTES (insn);
1508 int did_elimination = 0;
1509 int operands_changed = 0;
1510 rtx set = single_set (insn);
1512 /* Skip insns that only set an equivalence. */
1513 if (set && REG_P (SET_DEST (set))
1514 && reg_renumber[REGNO (SET_DEST (set))] < 0
1515 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1516 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1517 && reg_equiv_init (REGNO (SET_DEST (set))))
1520 /* If needed, eliminate any eliminable registers. */
1521 if (num_eliminable || num_eliminable_invariants)
1522 did_elimination = eliminate_regs_in_insn (insn, 0);
1524 /* Analyze the instruction. */
1525 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1526 global, spill_reg_order);
1528 /* If a no-op set needs more than one reload, this is likely
1529 to be something that needs input address reloads. We
1530 can't get rid of this cleanly later, and it is of no use
1531 anyway, so discard it now.
1532 We only do this when expensive_optimizations is enabled,
1533 since this complements reload inheritance / output
1534 reload deletion, and it can make debugging harder. */
1535 if (flag_expensive_optimizations && n_reloads > 1)
1537 rtx set = single_set (insn);
1540 ((SET_SRC (set) == SET_DEST (set)
1541 && REG_P (SET_SRC (set))
1542 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1543 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1544 && reg_renumber[REGNO (SET_SRC (set))] < 0
1545 && reg_renumber[REGNO (SET_DEST (set))] < 0
1546 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1547 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1548 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1549 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1551 if (ira_conflicts_p)
1552 /* Inform IRA about the insn deletion. */
1553 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1554 REGNO (SET_SRC (set)));
1556 /* Delete it from the reload chain. */
1558 chain->prev->next = next;
1560 reload_insn_chain = next;
1562 next->prev = chain->prev;
1563 chain->next = unused_insn_chains;
1564 unused_insn_chains = chain;
1569 update_eliminable_offsets ();
1571 /* Remember for later shortcuts which insns had any reloads or
1572 register eliminations. */
1573 chain->need_elim = did_elimination;
1574 chain->need_reload = n_reloads > 0;
1575 chain->need_operand_change = operands_changed;
1577 /* Discard any register replacements done. */
1578 if (did_elimination)
1580 obstack_free (&reload_obstack, reload_insn_firstobj);
1581 PATTERN (insn) = old_body;
1582 INSN_CODE (insn) = old_code;
1583 REG_NOTES (insn) = old_notes;
1584 something_needs_elimination = 1;
1587 something_needs_operands_changed |= operands_changed;
1591 copy_reloads (chain);
1592 *pprev_reload = chain;
1593 pprev_reload = &chain->next_need_reload;
1600 /* This function is called from the register allocator to set up estimates
1601 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1602 an invariant. The structure is similar to calculate_needs_all_insns. */
1605 calculate_elim_costs_all_insns (void)
1607 int *reg_equiv_init_cost;
1611 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1613 init_eliminable_invariants (get_insns (), false);
1615 set_initial_elim_offsets ();
1616 set_initial_label_offsets ();
1623 FOR_BB_INSNS (bb, insn)
1625 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1626 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1627 what effects this has on the known offsets at labels. */
1629 if (LABEL_P (insn) || JUMP_P (insn)
1630 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1631 set_label_offsets (insn, insn, 0);
1635 rtx set = single_set (insn);
1637 /* Skip insns that only set an equivalence. */
1638 if (set && REG_P (SET_DEST (set))
1639 && reg_renumber[REGNO (SET_DEST (set))] < 0
1640 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1641 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1643 unsigned regno = REGNO (SET_DEST (set));
1644 rtx init = reg_equiv_init (regno);
1647 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1649 int cost = rtx_cost (t, SET,
1650 optimize_bb_for_speed_p (bb));
1651 int freq = REG_FREQ_FROM_BB (bb);
1653 reg_equiv_init_cost[regno] = cost * freq;
1657 /* If needed, eliminate any eliminable registers. */
1658 if (num_eliminable || num_eliminable_invariants)
1659 elimination_costs_in_insn (insn);
1662 update_eliminable_offsets ();
1666 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1668 if (reg_equiv_invariant (i))
1670 if (reg_equiv_init (i))
1672 int cost = reg_equiv_init_cost[i];
1675 "Reg %d has equivalence, initial gains %d\n", i, cost);
1677 ira_adjust_equiv_reg_cost (i, cost);
1683 "Reg %d had equivalence, but can't be eliminated\n",
1685 ira_adjust_equiv_reg_cost (i, 0);
1690 free (reg_equiv_init_cost);
1693 /* Comparison function for qsort to decide which of two reloads
1694 should be handled first. *P1 and *P2 are the reload numbers. */
1697 reload_reg_class_lower (const void *r1p, const void *r2p)
1699 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1702 /* Consider required reloads before optional ones. */
1703 t = rld[r1].optional - rld[r2].optional;
1707 /* Count all solitary classes before non-solitary ones. */
1708 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1709 - (reg_class_size[(int) rld[r1].rclass] == 1));
1713 /* Aside from solitaires, consider all multi-reg groups first. */
1714 t = rld[r2].nregs - rld[r1].nregs;
1718 /* Consider reloads in order of increasing reg-class number. */
1719 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1723 /* If reloads are equally urgent, sort by reload number,
1724 so that the results of qsort leave nothing to chance. */
1728 /* The cost of spilling each hard reg. */
1729 static int spill_cost[FIRST_PSEUDO_REGISTER];
1731 /* When spilling multiple hard registers, we use SPILL_COST for the first
1732 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1733 only the first hard reg for a multi-reg pseudo. */
1734 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1736 /* Map of hard regno to pseudo regno currently occupying the hard
1738 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1740 /* Update the spill cost arrays, considering that pseudo REG is live. */
1743 count_pseudo (int reg)
1745 int freq = REG_FREQ (reg);
1746 int r = reg_renumber[reg];
1749 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1750 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1751 /* Ignore spilled pseudo-registers which can be here only if IRA
1753 || (ira_conflicts_p && r < 0))
1756 SET_REGNO_REG_SET (&pseudos_counted, reg);
1758 gcc_assert (r >= 0);
1760 spill_add_cost[r] += freq;
1761 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1764 hard_regno_to_pseudo_regno[r + nregs] = reg;
1765 spill_cost[r + nregs] += freq;
1769 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1770 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1773 order_regs_for_reload (struct insn_chain *chain)
1776 HARD_REG_SET used_by_pseudos;
1777 HARD_REG_SET used_by_pseudos2;
1778 reg_set_iterator rsi;
1780 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1782 memset (spill_cost, 0, sizeof spill_cost);
1783 memset (spill_add_cost, 0, sizeof spill_add_cost);
1784 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1785 hard_regno_to_pseudo_regno[i] = -1;
1787 /* Count number of uses of each hard reg by pseudo regs allocated to it
1788 and then order them by decreasing use. First exclude hard registers
1789 that are live in or across this insn. */
1791 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1792 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1793 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1794 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1796 /* Now find out which pseudos are allocated to it, and update
1798 CLEAR_REG_SET (&pseudos_counted);
1800 EXECUTE_IF_SET_IN_REG_SET
1801 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1805 EXECUTE_IF_SET_IN_REG_SET
1806 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1810 CLEAR_REG_SET (&pseudos_counted);
1813 /* Vector of reload-numbers showing the order in which the reloads should
1815 static short reload_order[MAX_RELOADS];
1817 /* This is used to keep track of the spill regs used in one insn. */
1818 static HARD_REG_SET used_spill_regs_local;
1820 /* We decided to spill hard register SPILLED, which has a size of
1821 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1822 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1823 update SPILL_COST/SPILL_ADD_COST. */
1826 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1828 int freq = REG_FREQ (reg);
1829 int r = reg_renumber[reg];
1830 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1832 /* Ignore spilled pseudo-registers which can be here only if IRA is
1834 if ((ira_conflicts_p && r < 0)
1835 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1836 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1839 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1841 spill_add_cost[r] -= freq;
1844 hard_regno_to_pseudo_regno[r + nregs] = -1;
1845 spill_cost[r + nregs] -= freq;
1849 /* Find reload register to use for reload number ORDER. */
1852 find_reg (struct insn_chain *chain, int order)
1854 int rnum = reload_order[order];
1855 struct reload *rl = rld + rnum;
1856 int best_cost = INT_MAX;
1858 unsigned int i, j, n;
1860 HARD_REG_SET not_usable;
1861 HARD_REG_SET used_by_other_reload;
1862 reg_set_iterator rsi;
1863 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1864 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1866 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1867 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1868 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1870 CLEAR_HARD_REG_SET (used_by_other_reload);
1871 for (k = 0; k < order; k++)
1873 int other = reload_order[k];
1875 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1876 for (j = 0; j < rld[other].nregs; j++)
1877 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1880 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1882 #ifdef REG_ALLOC_ORDER
1883 unsigned int regno = reg_alloc_order[i];
1885 unsigned int regno = i;
1888 if (! TEST_HARD_REG_BIT (not_usable, regno)
1889 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1890 && HARD_REGNO_MODE_OK (regno, rl->mode))
1892 int this_cost = spill_cost[regno];
1894 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1896 for (j = 1; j < this_nregs; j++)
1898 this_cost += spill_add_cost[regno + j];
1899 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1900 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1906 if (ira_conflicts_p)
1908 /* Ask IRA to find a better pseudo-register for
1910 for (n = j = 0; j < this_nregs; j++)
1912 int r = hard_regno_to_pseudo_regno[regno + j];
1916 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1917 regno_pseudo_regs[n++] = r;
1919 regno_pseudo_regs[n++] = -1;
1921 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1922 best_regno_pseudo_regs,
1929 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1930 if (regno_pseudo_regs[j] < 0)
1937 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1939 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1941 if (this_cost < best_cost
1942 /* Among registers with equal cost, prefer caller-saved ones, or
1943 use REG_ALLOC_ORDER if it is defined. */
1944 || (this_cost == best_cost
1945 #ifdef REG_ALLOC_ORDER
1946 && (inv_reg_alloc_order[regno]
1947 < inv_reg_alloc_order[best_reg])
1949 && call_used_regs[regno]
1950 && ! call_used_regs[best_reg]
1955 best_cost = this_cost;
1963 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1965 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1966 rl->regno = best_reg;
1968 EXECUTE_IF_SET_IN_REG_SET
1969 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1971 count_spilled_pseudo (best_reg, rl->nregs, j);
1974 EXECUTE_IF_SET_IN_REG_SET
1975 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1977 count_spilled_pseudo (best_reg, rl->nregs, j);
1980 for (i = 0; i < rl->nregs; i++)
1982 gcc_assert (spill_cost[best_reg + i] == 0);
1983 gcc_assert (spill_add_cost[best_reg + i] == 0);
1984 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1985 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1990 /* Find more reload regs to satisfy the remaining need of an insn, which
1992 Do it by ascending class number, since otherwise a reg
1993 might be spilled for a big class and might fail to count
1994 for a smaller class even though it belongs to that class. */
1997 find_reload_regs (struct insn_chain *chain)
2001 /* In order to be certain of getting the registers we need,
2002 we must sort the reloads into order of increasing register class.
2003 Then our grabbing of reload registers will parallel the process
2004 that provided the reload registers. */
2005 for (i = 0; i < chain->n_reloads; i++)
2007 /* Show whether this reload already has a hard reg. */
2008 if (chain->rld[i].reg_rtx)
2010 int regno = REGNO (chain->rld[i].reg_rtx);
2011 chain->rld[i].regno = regno;
2013 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2016 chain->rld[i].regno = -1;
2017 reload_order[i] = i;
2020 n_reloads = chain->n_reloads;
2021 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2023 CLEAR_HARD_REG_SET (used_spill_regs_local);
2026 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2028 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2030 /* Compute the order of preference for hard registers to spill. */
2032 order_regs_for_reload (chain);
2034 for (i = 0; i < n_reloads; i++)
2036 int r = reload_order[i];
2038 /* Ignore reloads that got marked inoperative. */
2039 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2040 && ! rld[r].optional
2041 && rld[r].regno == -1)
2042 if (! find_reg (chain, i))
2045 fprintf (dump_file, "reload failure for reload %d\n", r);
2046 spill_failure (chain->insn, rld[r].rclass);
2052 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2053 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2055 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2059 select_reload_regs (void)
2061 struct insn_chain *chain;
2063 /* Try to satisfy the needs for each insn. */
2064 for (chain = insns_need_reload; chain != 0;
2065 chain = chain->next_need_reload)
2066 find_reload_regs (chain);
2069 /* Delete all insns that were inserted by emit_caller_save_insns during
2072 delete_caller_save_insns (void)
2074 struct insn_chain *c = reload_insn_chain;
2078 while (c != 0 && c->is_caller_save_insn)
2080 struct insn_chain *next = c->next;
2083 if (c == reload_insn_chain)
2084 reload_insn_chain = next;
2088 next->prev = c->prev;
2090 c->prev->next = next;
2091 c->next = unused_insn_chains;
2092 unused_insn_chains = c;
2100 /* Handle the failure to find a register to spill.
2101 INSN should be one of the insns which needed this particular spill reg. */
2104 spill_failure (rtx insn, enum reg_class rclass)
2106 if (asm_noperands (PATTERN (insn)) >= 0)
2107 error_for_asm (insn, "can%'t find a register in class %qs while "
2108 "reloading %<asm%>",
2109 reg_class_names[rclass]);
2112 error ("unable to find a register to spill in class %qs",
2113 reg_class_names[rclass]);
2117 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2118 debug_reload_to_stream (dump_file);
2120 fatal_insn ("this is the insn:", insn);
2124 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2125 data that is dead in INSN. */
2128 delete_dead_insn (rtx insn)
2130 rtx prev = prev_active_insn (insn);
2133 /* If the previous insn sets a register that dies in our insn make
2134 a note that we want to run DCE immediately after reload.
2136 We used to delete the previous insn & recurse, but that's wrong for
2137 block local equivalences. Instead of trying to figure out the exact
2138 circumstances where we can delete the potentially dead insns, just
2139 let DCE do the job. */
2140 if (prev && GET_CODE (PATTERN (prev)) == SET
2141 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2142 && reg_mentioned_p (prev_dest, PATTERN (insn))
2143 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2144 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2147 SET_INSN_DELETED (insn);
2150 /* Modify the home of pseudo-reg I.
2151 The new home is present in reg_renumber[I].
2153 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2154 or it may be -1, meaning there is none or it is not relevant.
2155 This is used so that all pseudos spilled from a given hard reg
2156 can share one stack slot. */
2159 alter_reg (int i, int from_reg, bool dont_share_p)
2161 /* When outputting an inline function, this can happen
2162 for a reg that isn't actually used. */
2163 if (regno_reg_rtx[i] == 0)
2166 /* If the reg got changed to a MEM at rtl-generation time,
2168 if (!REG_P (regno_reg_rtx[i]))
2171 /* Modify the reg-rtx to contain the new hard reg
2172 number or else to contain its pseudo reg number. */
2173 SET_REGNO (regno_reg_rtx[i],
2174 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2176 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2177 allocate a stack slot for it. */
2179 if (reg_renumber[i] < 0
2180 && REG_N_REFS (i) > 0
2181 && reg_equiv_constant (i) == 0
2182 && (reg_equiv_invariant (i) == 0
2183 || reg_equiv_init (i) == 0)
2184 && reg_equiv_memory_loc (i) == 0)
2187 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2188 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2189 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2190 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2191 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2194 something_was_spilled = true;
2196 if (ira_conflicts_p)
2198 /* Mark the spill for IRA. */
2199 SET_REGNO_REG_SET (&spilled_pseudos, i);
2201 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2207 /* Each pseudo reg has an inherent size which comes from its own mode,
2208 and a total size which provides room for paradoxical subregs
2209 which refer to the pseudo reg in wider modes.
2211 We can use a slot already allocated if it provides both
2212 enough inherent space and enough total space.
2213 Otherwise, we allocate a new slot, making sure that it has no less
2214 inherent space, and no less total space, then the previous slot. */
2215 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2219 /* No known place to spill from => no slot to reuse. */
2220 x = assign_stack_local (mode, total_size,
2221 min_align > inherent_align
2222 || total_size > inherent_size ? -1 : 0);
2226 /* Cancel the big-endian correction done in assign_stack_local.
2227 Get the address of the beginning of the slot. This is so we
2228 can do a big-endian correction unconditionally below. */
2229 if (BYTES_BIG_ENDIAN)
2231 adjust = inherent_size - total_size;
2234 = adjust_address_nv (x, mode_for_size (total_size
2240 if (! dont_share_p && ira_conflicts_p)
2241 /* Inform IRA about allocation a new stack slot. */
2242 ira_mark_new_stack_slot (stack_slot, i, total_size);
2245 /* Reuse a stack slot if possible. */
2246 else if (spill_stack_slot[from_reg] != 0
2247 && spill_stack_slot_width[from_reg] >= total_size
2248 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2250 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2251 x = spill_stack_slot[from_reg];
2253 /* Allocate a bigger slot. */
2256 /* Compute maximum size needed, both for inherent size
2257 and for total size. */
2260 if (spill_stack_slot[from_reg])
2262 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2264 mode = GET_MODE (spill_stack_slot[from_reg]);
2265 if (spill_stack_slot_width[from_reg] > total_size)
2266 total_size = spill_stack_slot_width[from_reg];
2267 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2268 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2271 /* Make a slot with that size. */
2272 x = assign_stack_local (mode, total_size,
2273 min_align > inherent_align
2274 || total_size > inherent_size ? -1 : 0);
2277 /* Cancel the big-endian correction done in assign_stack_local.
2278 Get the address of the beginning of the slot. This is so we
2279 can do a big-endian correction unconditionally below. */
2280 if (BYTES_BIG_ENDIAN)
2282 adjust = GET_MODE_SIZE (mode) - total_size;
2285 = adjust_address_nv (x, mode_for_size (total_size
2291 spill_stack_slot[from_reg] = stack_slot;
2292 spill_stack_slot_width[from_reg] = total_size;
2295 /* On a big endian machine, the "address" of the slot
2296 is the address of the low part that fits its inherent mode. */
2297 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2298 adjust += (total_size - inherent_size);
2300 /* If we have any adjustment to make, or if the stack slot is the
2301 wrong mode, make a new stack slot. */
2302 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2304 /* Set all of the memory attributes as appropriate for a spill. */
2305 set_mem_attrs_for_spill (x);
2307 /* Save the stack slot for later. */
2308 reg_equiv_memory_loc (i) = x;
2312 /* Mark the slots in regs_ever_live for the hard regs used by
2313 pseudo-reg number REGNO, accessed in MODE. */
2316 mark_home_live_1 (int regno, enum machine_mode mode)
2320 i = reg_renumber[regno];
2323 lim = end_hard_regno (mode, i);
2325 df_set_regs_ever_live(i++, true);
2328 /* Mark the slots in regs_ever_live for the hard regs
2329 used by pseudo-reg number REGNO. */
2332 mark_home_live (int regno)
2334 if (reg_renumber[regno] >= 0)
2335 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2338 /* This function handles the tracking of elimination offsets around branches.
2340 X is a piece of RTL being scanned.
2342 INSN is the insn that it came from, if any.
2344 INITIAL_P is nonzero if we are to set the offset to be the initial
2345 offset and zero if we are setting the offset of the label to be the
2349 set_label_offsets (rtx x, rtx insn, int initial_p)
2351 enum rtx_code code = GET_CODE (x);
2354 struct elim_table *p;
2359 if (LABEL_REF_NONLOCAL_P (x))
2364 /* ... fall through ... */
2367 /* If we know nothing about this label, set the desired offsets. Note
2368 that this sets the offset at a label to be the offset before a label
2369 if we don't know anything about the label. This is not correct for
2370 the label after a BARRIER, but is the best guess we can make. If
2371 we guessed wrong, we will suppress an elimination that might have
2372 been possible had we been able to guess correctly. */
2374 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2376 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2377 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2378 = (initial_p ? reg_eliminate[i].initial_offset
2379 : reg_eliminate[i].offset);
2380 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2383 /* Otherwise, if this is the definition of a label and it is
2384 preceded by a BARRIER, set our offsets to the known offset of
2388 && (tem = prev_nonnote_insn (insn)) != 0
2390 set_offsets_for_label (insn);
2392 /* If neither of the above cases is true, compare each offset
2393 with those previously recorded and suppress any eliminations
2394 where the offsets disagree. */
2396 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2397 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2398 != (initial_p ? reg_eliminate[i].initial_offset
2399 : reg_eliminate[i].offset))
2400 reg_eliminate[i].can_eliminate = 0;
2405 set_label_offsets (PATTERN (insn), insn, initial_p);
2407 /* ... fall through ... */
2411 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2412 to indirectly and hence must have all eliminations at their
2414 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2415 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2416 set_label_offsets (XEXP (tem, 0), insn, 1);
2422 /* Each of the labels in the parallel or address vector must be
2423 at their initial offsets. We want the first field for PARALLEL
2424 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2426 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2427 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2432 /* We only care about setting PC. If the source is not RETURN,
2433 IF_THEN_ELSE, or a label, disable any eliminations not at
2434 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2435 isn't one of those possibilities. For branches to a label,
2436 call ourselves recursively.
2438 Note that this can disable elimination unnecessarily when we have
2439 a non-local goto since it will look like a non-constant jump to
2440 someplace in the current function. This isn't a significant
2441 problem since such jumps will normally be when all elimination
2442 pairs are back to their initial offsets. */
2444 if (SET_DEST (x) != pc_rtx)
2447 switch (GET_CODE (SET_SRC (x)))
2454 set_label_offsets (SET_SRC (x), insn, initial_p);
2458 tem = XEXP (SET_SRC (x), 1);
2459 if (GET_CODE (tem) == LABEL_REF)
2460 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2461 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2464 tem = XEXP (SET_SRC (x), 2);
2465 if (GET_CODE (tem) == LABEL_REF)
2466 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2467 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2475 /* If we reach here, all eliminations must be at their initial
2476 offset because we are doing a jump to a variable address. */
2477 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2478 if (p->offset != p->initial_offset)
2479 p->can_eliminate = 0;
2487 /* Called through for_each_rtx, this function examines every reg that occurs
2488 in PX and adjusts the costs for its elimination which are gathered by IRA.
2489 DATA is the insn in which PX occurs. We do not recurse into MEM
2493 note_reg_elim_costly (rtx *px, void *data)
2495 rtx insn = (rtx)data;
2502 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2503 && reg_equiv_init (REGNO (x))
2504 && reg_equiv_invariant (REGNO (x)))
2506 rtx t = reg_equiv_invariant (REGNO (x));
2507 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2508 int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
2509 int freq = REG_FREQ_FROM_BB (elim_bb);
2512 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2517 /* Scan X and replace any eliminable registers (such as fp) with a
2518 replacement (such as sp), plus an offset.
2520 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2521 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2522 MEM, we are allowed to replace a sum of a register and the constant zero
2523 with the register, which we cannot do outside a MEM. In addition, we need
2524 to record the fact that a register is referenced outside a MEM.
2526 If INSN is an insn, it is the insn containing X. If we replace a REG
2527 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2528 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2529 the REG is being modified.
2531 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2532 That's used when we eliminate in expressions stored in notes.
2533 This means, do not set ref_outside_mem even if the reference
2536 If FOR_COSTS is true, we are being called before reload in order to
2537 estimate the costs of keeping registers with an equivalence unallocated.
2539 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2540 replacements done assuming all offsets are at their initial values. If
2541 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2542 encounter, return the actual location so that find_reloads will do
2543 the proper thing. */
2546 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2547 bool may_use_invariant, bool for_costs)
2549 enum rtx_code code = GET_CODE (x);
2550 struct elim_table *ep;
2557 if (! current_function_decl)
2580 /* First handle the case where we encounter a bare register that
2581 is eliminable. Replace it with a PLUS. */
2582 if (regno < FIRST_PSEUDO_REGISTER)
2584 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2586 if (ep->from_rtx == x && ep->can_eliminate)
2587 return plus_constant (ep->to_rtx, ep->previous_offset);
2590 else if (reg_renumber && reg_renumber[regno] < 0
2592 && reg_equiv_invariant (regno))
2594 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2595 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2596 mem_mode, insn, true, for_costs);
2597 /* There exists at least one use of REGNO that cannot be
2598 eliminated. Prevent the defining insn from being deleted. */
2599 reg_equiv_init (regno) = NULL_RTX;
2601 alter_reg (regno, -1, true);
2605 /* You might think handling MINUS in a manner similar to PLUS is a
2606 good idea. It is not. It has been tried multiple times and every
2607 time the change has had to have been reverted.
2609 Other parts of reload know a PLUS is special (gen_reload for example)
2610 and require special code to handle code a reloaded PLUS operand.
2612 Also consider backends where the flags register is clobbered by a
2613 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2614 lea instruction comes to mind). If we try to reload a MINUS, we
2615 may kill the flags register that was holding a useful value.
2617 So, please before trying to handle MINUS, consider reload as a
2618 whole instead of this little section as well as the backend issues. */
2620 /* If this is the sum of an eliminable register and a constant, rework
2622 if (REG_P (XEXP (x, 0))
2623 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2624 && CONSTANT_P (XEXP (x, 1)))
2626 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2628 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2630 /* The only time we want to replace a PLUS with a REG (this
2631 occurs when the constant operand of the PLUS is the negative
2632 of the offset) is when we are inside a MEM. We won't want
2633 to do so at other times because that would change the
2634 structure of the insn in a way that reload can't handle.
2635 We special-case the commonest situation in
2636 eliminate_regs_in_insn, so just replace a PLUS with a
2637 PLUS here, unless inside a MEM. */
2638 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2639 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2642 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2643 plus_constant (XEXP (x, 1),
2644 ep->previous_offset));
2647 /* If the register is not eliminable, we are done since the other
2648 operand is a constant. */
2652 /* If this is part of an address, we want to bring any constant to the
2653 outermost PLUS. We will do this by doing register replacement in
2654 our operands and seeing if a constant shows up in one of them.
2656 Note that there is no risk of modifying the structure of the insn,
2657 since we only get called for its operands, thus we are either
2658 modifying the address inside a MEM, or something like an address
2659 operand of a load-address insn. */
2662 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2664 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2667 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2669 /* If one side is a PLUS and the other side is a pseudo that
2670 didn't get a hard register but has a reg_equiv_constant,
2671 we must replace the constant here since it may no longer
2672 be in the position of any operand. */
2673 if (GET_CODE (new0) == PLUS && REG_P (new1)
2674 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2675 && reg_renumber[REGNO (new1)] < 0
2677 && reg_equiv_constant (REGNO (new1)) != 0)
2678 new1 = reg_equiv_constant (REGNO (new1));
2679 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2680 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2681 && reg_renumber[REGNO (new0)] < 0
2682 && reg_equiv_constant (REGNO (new0)) != 0)
2683 new0 = reg_equiv_constant (REGNO (new0));
2685 new_rtx = form_sum (GET_MODE (x), new0, new1);
2687 /* As above, if we are not inside a MEM we do not want to
2688 turn a PLUS into something else. We might try to do so here
2689 for an addition of 0 if we aren't optimizing. */
2690 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2691 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2699 /* If this is the product of an eliminable register and a
2700 constant, apply the distribute law and move the constant out
2701 so that we have (plus (mult ..) ..). This is needed in order
2702 to keep load-address insns valid. This case is pathological.
2703 We ignore the possibility of overflow here. */
2704 if (REG_P (XEXP (x, 0))
2705 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2706 && CONST_INT_P (XEXP (x, 1)))
2707 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2709 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2712 /* Refs inside notes or in DEBUG_INSNs don't count for
2714 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2715 || GET_CODE (insn) == INSN_LIST
2716 || DEBUG_INSN_P (insn))))
2717 ep->ref_outside_mem = 1;
2720 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2721 ep->previous_offset * INTVAL (XEXP (x, 1)));
2724 /* ... fall through ... */
2728 /* See comments before PLUS about handling MINUS. */
2730 case DIV: case UDIV:
2731 case MOD: case UMOD:
2732 case AND: case IOR: case XOR:
2733 case ROTATERT: case ROTATE:
2734 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2736 case GE: case GT: case GEU: case GTU:
2737 case LE: case LT: case LEU: case LTU:
2739 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2741 rtx new1 = XEXP (x, 1)
2742 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2745 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2746 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2751 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2754 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2756 if (new_rtx != XEXP (x, 0))
2758 /* If this is a REG_DEAD note, it is not valid anymore.
2759 Using the eliminated version could result in creating a
2760 REG_DEAD note for the stack or frame pointer. */
2761 if (REG_NOTE_KIND (x) == REG_DEAD)
2763 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2767 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2771 /* ... fall through ... */
2774 /* Now do eliminations in the rest of the chain. If this was
2775 an EXPR_LIST, this might result in allocating more memory than is
2776 strictly needed, but it simplifies the code. */
2779 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2781 if (new_rtx != XEXP (x, 1))
2783 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2791 /* We do not support elimination of a register that is modified.
2792 elimination_effects has already make sure that this does not
2798 /* We do not support elimination of a register that is modified.
2799 elimination_effects has already make sure that this does not
2800 happen. The only remaining case we need to consider here is
2801 that the increment value may be an eliminable register. */
2802 if (GET_CODE (XEXP (x, 1)) == PLUS
2803 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2805 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2806 insn, true, for_costs);
2808 if (new_rtx != XEXP (XEXP (x, 1), 1))
2809 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2810 gen_rtx_PLUS (GET_MODE (x),
2811 XEXP (x, 0), new_rtx));
2815 case STRICT_LOW_PART:
2817 case SIGN_EXTEND: case ZERO_EXTEND:
2818 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2819 case FLOAT: case FIX:
2820 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2829 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2831 if (new_rtx != XEXP (x, 0))
2832 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2836 /* Similar to above processing, but preserve SUBREG_BYTE.
2837 Convert (subreg (mem)) to (mem) if not paradoxical.
2838 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2839 pseudo didn't get a hard reg, we must replace this with the
2840 eliminated version of the memory location because push_reload
2841 may do the replacement in certain circumstances. */
2842 if (REG_P (SUBREG_REG (x))
2843 && !paradoxical_subreg_p (x)
2845 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2847 new_rtx = SUBREG_REG (x);
2850 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2852 if (new_rtx != SUBREG_REG (x))
2854 int x_size = GET_MODE_SIZE (GET_MODE (x));
2855 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2858 && ((x_size < new_size
2859 #ifdef WORD_REGISTER_OPERATIONS
2860 /* On these machines, combine can create rtl of the form
2861 (set (subreg:m1 (reg:m2 R) 0) ...)
2862 where m1 < m2, and expects something interesting to
2863 happen to the entire word. Moreover, it will use the
2864 (reg:m2 R) later, expecting all bits to be preserved.
2865 So if the number of words is the same, preserve the
2866 subreg so that push_reload can see it. */
2867 && ! ((x_size - 1) / UNITS_PER_WORD
2868 == (new_size -1 ) / UNITS_PER_WORD)
2871 || x_size == new_size)
2873 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2875 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2881 /* Our only special processing is to pass the mode of the MEM to our
2882 recursive call and copy the flags. While we are here, handle this
2883 case more efficiently. */
2885 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2888 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2889 && !memory_address_p (GET_MODE (x), new_rtx))
2890 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2892 return replace_equiv_address_nv (x, new_rtx);
2895 /* Handle insn_list USE that a call to a pure function may generate. */
2896 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2898 if (new_rtx != XEXP (x, 0))
2899 return gen_rtx_USE (GET_MODE (x), new_rtx);
2904 gcc_assert (insn && DEBUG_INSN_P (insn));
2914 /* Process each of our operands recursively. If any have changed, make a
2916 fmt = GET_RTX_FORMAT (code);
2917 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2921 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2923 if (new_rtx != XEXP (x, i) && ! copied)
2925 x = shallow_copy_rtx (x);
2928 XEXP (x, i) = new_rtx;
2930 else if (*fmt == 'E')
2933 for (j = 0; j < XVECLEN (x, i); j++)
2935 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2937 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2939 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2943 x = shallow_copy_rtx (x);
2946 XVEC (x, i) = new_v;
2949 XVECEXP (x, i, j) = new_rtx;
2958 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2960 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2963 /* Scan rtx X for modifications of elimination target registers. Update
2964 the table of eliminables to reflect the changed state. MEM_MODE is
2965 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2968 elimination_effects (rtx x, enum machine_mode mem_mode)
2970 enum rtx_code code = GET_CODE (x);
2971 struct elim_table *ep;
2996 /* First handle the case where we encounter a bare register that
2997 is eliminable. Replace it with a PLUS. */
2998 if (regno < FIRST_PSEUDO_REGISTER)
3000 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3002 if (ep->from_rtx == x && ep->can_eliminate)
3005 ep->ref_outside_mem = 1;
3010 else if (reg_renumber[regno] < 0
3012 && reg_equiv_constant (regno)
3013 && ! function_invariant_p (reg_equiv_constant (regno)))
3014 elimination_effects (reg_equiv_constant (regno), mem_mode);
3023 /* If we modify the source of an elimination rule, disable it. */
3024 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3025 if (ep->from_rtx == XEXP (x, 0))
3026 ep->can_eliminate = 0;
3028 /* If we modify the target of an elimination rule by adding a constant,
3029 update its offset. If we modify the target in any other way, we'll
3030 have to disable the rule as well. */
3031 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3032 if (ep->to_rtx == XEXP (x, 0))
3034 int size = GET_MODE_SIZE (mem_mode);
3036 /* If more bytes than MEM_MODE are pushed, account for them. */
3037 #ifdef PUSH_ROUNDING
3038 if (ep->to_rtx == stack_pointer_rtx)
3039 size = PUSH_ROUNDING (size);
3041 if (code == PRE_DEC || code == POST_DEC)
3043 else if (code == PRE_INC || code == POST_INC)
3045 else if (code == PRE_MODIFY || code == POST_MODIFY)
3047 if (GET_CODE (XEXP (x, 1)) == PLUS
3048 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3049 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3050 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3052 ep->can_eliminate = 0;
3056 /* These two aren't unary operators. */
3057 if (code == POST_MODIFY || code == PRE_MODIFY)
3060 /* Fall through to generic unary operation case. */
3061 case STRICT_LOW_PART:
3063 case SIGN_EXTEND: case ZERO_EXTEND:
3064 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3065 case FLOAT: case FIX:
3066 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3075 elimination_effects (XEXP (x, 0), mem_mode);
3079 if (REG_P (SUBREG_REG (x))
3080 && (GET_MODE_SIZE (GET_MODE (x))
3081 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3083 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3086 elimination_effects (SUBREG_REG (x), mem_mode);
3090 /* If using a register that is the source of an eliminate we still
3091 think can be performed, note it cannot be performed since we don't
3092 know how this register is used. */
3093 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3094 if (ep->from_rtx == XEXP (x, 0))
3095 ep->can_eliminate = 0;
3097 elimination_effects (XEXP (x, 0), mem_mode);
3101 /* If clobbering a register that is the replacement register for an
3102 elimination we still think can be performed, note that it cannot
3103 be performed. Otherwise, we need not be concerned about it. */
3104 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3105 if (ep->to_rtx == XEXP (x, 0))
3106 ep->can_eliminate = 0;
3108 elimination_effects (XEXP (x, 0), mem_mode);
3112 /* Check for setting a register that we know about. */
3113 if (REG_P (SET_DEST (x)))
3115 /* See if this is setting the replacement register for an
3118 If DEST is the hard frame pointer, we do nothing because we
3119 assume that all assignments to the frame pointer are for
3120 non-local gotos and are being done at a time when they are valid
3121 and do not disturb anything else. Some machines want to
3122 eliminate a fake argument pointer (or even a fake frame pointer)
3123 with either the real frame or the stack pointer. Assignments to
3124 the hard frame pointer must not prevent this elimination. */
3126 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3128 if (ep->to_rtx == SET_DEST (x)
3129 && SET_DEST (x) != hard_frame_pointer_rtx)
3131 /* If it is being incremented, adjust the offset. Otherwise,
3132 this elimination can't be done. */
3133 rtx src = SET_SRC (x);
3135 if (GET_CODE (src) == PLUS
3136 && XEXP (src, 0) == SET_DEST (x)
3137 && CONST_INT_P (XEXP (src, 1)))
3138 ep->offset -= INTVAL (XEXP (src, 1));
3140 ep->can_eliminate = 0;
3144 elimination_effects (SET_DEST (x), VOIDmode);
3145 elimination_effects (SET_SRC (x), VOIDmode);
3149 /* Our only special processing is to pass the mode of the MEM to our
3151 elimination_effects (XEXP (x, 0), GET_MODE (x));
3158 fmt = GET_RTX_FORMAT (code);
3159 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3162 elimination_effects (XEXP (x, i), mem_mode);
3163 else if (*fmt == 'E')
3164 for (j = 0; j < XVECLEN (x, i); j++)
3165 elimination_effects (XVECEXP (x, i, j), mem_mode);
3169 /* Descend through rtx X and verify that no references to eliminable registers
3170 remain. If any do remain, mark the involved register as not
3174 check_eliminable_occurrences (rtx x)
3183 code = GET_CODE (x);
3185 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3187 struct elim_table *ep;
3189 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3190 if (ep->from_rtx == x)
3191 ep->can_eliminate = 0;
3195 fmt = GET_RTX_FORMAT (code);
3196 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3199 check_eliminable_occurrences (XEXP (x, i));
3200 else if (*fmt == 'E')
3203 for (j = 0; j < XVECLEN (x, i); j++)
3204 check_eliminable_occurrences (XVECEXP (x, i, j));
3209 /* Scan INSN and eliminate all eliminable registers in it.
3211 If REPLACE is nonzero, do the replacement destructively. Also
3212 delete the insn as dead it if it is setting an eliminable register.
3214 If REPLACE is zero, do all our allocations in reload_obstack.
3216 If no eliminations were done and this insn doesn't require any elimination
3217 processing (these are not identical conditions: it might be updating sp,
3218 but not referencing fp; this needs to be seen during reload_as_needed so
3219 that the offset between fp and sp can be taken into consideration), zero
3220 is returned. Otherwise, 1 is returned. */
3223 eliminate_regs_in_insn (rtx insn, int replace)
3225 int icode = recog_memoized (insn);
3226 rtx old_body = PATTERN (insn);
3227 int insn_is_asm = asm_noperands (old_body) >= 0;
3228 rtx old_set = single_set (insn);
3232 rtx substed_operand[MAX_RECOG_OPERANDS];
3233 rtx orig_operand[MAX_RECOG_OPERANDS];
3234 struct elim_table *ep;
3235 rtx plus_src, plus_cst_src;
3237 if (! insn_is_asm && icode < 0)
3239 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3240 || GET_CODE (PATTERN (insn)) == CLOBBER
3241 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3242 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3243 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3244 || DEBUG_INSN_P (insn));
3245 if (DEBUG_INSN_P (insn))
3246 INSN_VAR_LOCATION_LOC (insn)
3247 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3251 if (old_set != 0 && REG_P (SET_DEST (old_set))
3252 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3254 /* Check for setting an eliminable register. */
3255 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3256 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3258 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3259 /* If this is setting the frame pointer register to the
3260 hardware frame pointer register and this is an elimination
3261 that will be done (tested above), this insn is really
3262 adjusting the frame pointer downward to compensate for
3263 the adjustment done before a nonlocal goto. */
3264 if (ep->from == FRAME_POINTER_REGNUM
3265 && ep->to == HARD_FRAME_POINTER_REGNUM)
3267 rtx base = SET_SRC (old_set);
3268 rtx base_insn = insn;
3269 HOST_WIDE_INT offset = 0;
3271 while (base != ep->to_rtx)
3273 rtx prev_insn, prev_set;
3275 if (GET_CODE (base) == PLUS
3276 && CONST_INT_P (XEXP (base, 1)))
3278 offset += INTVAL (XEXP (base, 1));
3279 base = XEXP (base, 0);
3281 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3282 && (prev_set = single_set (prev_insn)) != 0
3283 && rtx_equal_p (SET_DEST (prev_set), base))
3285 base = SET_SRC (prev_set);
3286 base_insn = prev_insn;
3292 if (base == ep->to_rtx)
3295 = plus_constant (ep->to_rtx, offset - ep->offset);
3297 new_body = old_body;
3300 new_body = copy_insn (old_body);
3301 if (REG_NOTES (insn))
3302 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3304 PATTERN (insn) = new_body;
3305 old_set = single_set (insn);
3307 /* First see if this insn remains valid when we
3308 make the change. If not, keep the INSN_CODE
3309 the same and let reload fit it up. */
3310 validate_change (insn, &SET_SRC (old_set), src, 1);
3311 validate_change (insn, &SET_DEST (old_set),
3313 if (! apply_change_group ())
3315 SET_SRC (old_set) = src;
3316 SET_DEST (old_set) = ep->to_rtx;
3325 /* In this case this insn isn't serving a useful purpose. We
3326 will delete it in reload_as_needed once we know that this
3327 elimination is, in fact, being done.
3329 If REPLACE isn't set, we can't delete this insn, but needn't
3330 process it since it won't be used unless something changes. */
3333 delete_dead_insn (insn);
3341 /* We allow one special case which happens to work on all machines we
3342 currently support: a single set with the source or a REG_EQUAL
3343 note being a PLUS of an eliminable register and a constant. */
3344 plus_src = plus_cst_src = 0;
3345 if (old_set && REG_P (SET_DEST (old_set)))
3347 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3348 plus_src = SET_SRC (old_set);
3349 /* First see if the source is of the form (plus (...) CST). */
3351 && CONST_INT_P (XEXP (plus_src, 1)))
3352 plus_cst_src = plus_src;
3353 else if (REG_P (SET_SRC (old_set))
3356 /* Otherwise, see if we have a REG_EQUAL note of the form
3357 (plus (...) CST). */
3359 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3361 if ((REG_NOTE_KIND (links) == REG_EQUAL
3362 || REG_NOTE_KIND (links) == REG_EQUIV)
3363 && GET_CODE (XEXP (links, 0)) == PLUS
3364 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3366 plus_cst_src = XEXP (links, 0);
3372 /* Check that the first operand of the PLUS is a hard reg or
3373 the lowpart subreg of one. */
3376 rtx reg = XEXP (plus_cst_src, 0);
3377 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3378 reg = SUBREG_REG (reg);
3380 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3386 rtx reg = XEXP (plus_cst_src, 0);
3387 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3389 if (GET_CODE (reg) == SUBREG)
3390 reg = SUBREG_REG (reg);
3392 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3393 if (ep->from_rtx == reg && ep->can_eliminate)
3395 rtx to_rtx = ep->to_rtx;
3396 offset += ep->offset;
3397 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3399 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3400 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3402 /* If we have a nonzero offset, and the source is already
3403 a simple REG, the following transformation would
3404 increase the cost of the insn by replacing a simple REG
3405 with (plus (reg sp) CST). So try only when we already
3406 had a PLUS before. */
3407 if (offset == 0 || plus_src)
3409 rtx new_src = plus_constant (to_rtx, offset);
3411 new_body = old_body;
3414 new_body = copy_insn (old_body);
3415 if (REG_NOTES (insn))
3416 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3418 PATTERN (insn) = new_body;
3419 old_set = single_set (insn);
3421 /* First see if this insn remains valid when we make the
3422 change. If not, try to replace the whole pattern with
3423 a simple set (this may help if the original insn was a
3424 PARALLEL that was only recognized as single_set due to
3425 REG_UNUSED notes). If this isn't valid either, keep
3426 the INSN_CODE the same and let reload fix it up. */
3427 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3429 rtx new_pat = gen_rtx_SET (VOIDmode,
3430 SET_DEST (old_set), new_src);
3432 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3433 SET_SRC (old_set) = new_src;
3440 /* This can't have an effect on elimination offsets, so skip right
3446 /* Determine the effects of this insn on elimination offsets. */
3447 elimination_effects (old_body, VOIDmode);
3449 /* Eliminate all eliminable registers occurring in operands that
3450 can be handled by reload. */
3451 extract_insn (insn);
3452 for (i = 0; i < recog_data.n_operands; i++)
3454 orig_operand[i] = recog_data.operand[i];
3455 substed_operand[i] = recog_data.operand[i];
3457 /* For an asm statement, every operand is eliminable. */
3458 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3460 bool is_set_src, in_plus;
3462 /* Check for setting a register that we know about. */
3463 if (recog_data.operand_type[i] != OP_IN
3464 && REG_P (orig_operand[i]))
3466 /* If we are assigning to a register that can be eliminated, it
3467 must be as part of a PARALLEL, since the code above handles
3468 single SETs. We must indicate that we can no longer
3469 eliminate this reg. */
3470 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3472 if (ep->from_rtx == orig_operand[i])
3473 ep->can_eliminate = 0;
3476 /* Companion to the above plus substitution, we can allow
3477 invariants as the source of a plain move. */
3480 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3484 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3485 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3489 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3490 replace ? insn : NULL_RTX,
3491 is_set_src || in_plus, false);
3492 if (substed_operand[i] != orig_operand[i])
3494 /* Terminate the search in check_eliminable_occurrences at
3496 *recog_data.operand_loc[i] = 0;
3498 /* If an output operand changed from a REG to a MEM and INSN is an
3499 insn, write a CLOBBER insn. */
3500 if (recog_data.operand_type[i] != OP_IN
3501 && REG_P (orig_operand[i])
3502 && MEM_P (substed_operand[i])
3504 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3508 for (i = 0; i < recog_data.n_dups; i++)
3509 *recog_data.dup_loc[i]
3510 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3512 /* If any eliminable remain, they aren't eliminable anymore. */
3513 check_eliminable_occurrences (old_body);
3515 /* Substitute the operands; the new values are in the substed_operand
3517 for (i = 0; i < recog_data.n_operands; i++)
3518 *recog_data.operand_loc[i] = substed_operand[i];
3519 for (i = 0; i < recog_data.n_dups; i++)
3520 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3522 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3523 re-recognize the insn. We do this in case we had a simple addition
3524 but now can do this as a load-address. This saves an insn in this
3526 If re-recognition fails, the old insn code number will still be used,
3527 and some register operands may have changed into PLUS expressions.
3528 These will be handled by find_reloads by loading them into a register
3533 /* If we aren't replacing things permanently and we changed something,
3534 make another copy to ensure that all the RTL is new. Otherwise
3535 things can go wrong if find_reload swaps commutative operands
3536 and one is inside RTL that has been copied while the other is not. */
3537 new_body = old_body;
3540 new_body = copy_insn (old_body);
3541 if (REG_NOTES (insn))
3542 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3544 PATTERN (insn) = new_body;
3546 /* If we had a move insn but now we don't, rerecognize it. This will
3547 cause spurious re-recognition if the old move had a PARALLEL since
3548 the new one still will, but we can't call single_set without
3549 having put NEW_BODY into the insn and the re-recognition won't
3550 hurt in this rare case. */
3551 /* ??? Why this huge if statement - why don't we just rerecognize the
3555 && ((REG_P (SET_SRC (old_set))
3556 && (GET_CODE (new_body) != SET
3557 || !REG_P (SET_SRC (new_body))))
3558 /* If this was a load from or store to memory, compare
3559 the MEM in recog_data.operand to the one in the insn.
3560 If they are not equal, then rerecognize the insn. */
3562 && ((MEM_P (SET_SRC (old_set))
3563 && SET_SRC (old_set) != recog_data.operand[1])
3564 || (MEM_P (SET_DEST (old_set))
3565 && SET_DEST (old_set) != recog_data.operand[0])))
3566 /* If this was an add insn before, rerecognize. */
3567 || GET_CODE (SET_SRC (old_set)) == PLUS))
3569 int new_icode = recog (PATTERN (insn), insn, 0);
3571 INSN_CODE (insn) = new_icode;
3575 /* Restore the old body. If there were any changes to it, we made a copy
3576 of it while the changes were still in place, so we'll correctly return
3577 a modified insn below. */
3580 /* Restore the old body. */
3581 for (i = 0; i < recog_data.n_operands; i++)
3582 /* Restoring a top-level match_parallel would clobber the new_body
3583 we installed in the insn. */
3584 if (recog_data.operand_loc[i] != &PATTERN (insn))
3585 *recog_data.operand_loc[i] = orig_operand[i];
3586 for (i = 0; i < recog_data.n_dups; i++)
3587 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3590 /* Update all elimination pairs to reflect the status after the current
3591 insn. The changes we make were determined by the earlier call to
3592 elimination_effects.
3594 We also detect cases where register elimination cannot be done,
3595 namely, if a register would be both changed and referenced outside a MEM
3596 in the resulting insn since such an insn is often undefined and, even if
3597 not, we cannot know what meaning will be given to it. Note that it is
3598 valid to have a register used in an address in an insn that changes it
3599 (presumably with a pre- or post-increment or decrement).
3601 If anything changes, return nonzero. */
3603 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3605 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3606 ep->can_eliminate = 0;
3608 ep->ref_outside_mem = 0;
3610 if (ep->previous_offset != ep->offset)
3615 /* If we changed something, perform elimination in REG_NOTES. This is
3616 needed even when REPLACE is zero because a REG_DEAD note might refer
3617 to a register that we eliminate and could cause a different number
3618 of spill registers to be needed in the final reload pass than in
3620 if (val && REG_NOTES (insn) != 0)
3622 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3628 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3629 register allocator. INSN is the instruction we need to examine, we perform
3630 eliminations in its operands and record cases where eliminating a reg with
3631 an invariant equivalence would add extra cost. */
3634 elimination_costs_in_insn (rtx insn)
3636 int icode = recog_memoized (insn);
3637 rtx old_body = PATTERN (insn);
3638 int insn_is_asm = asm_noperands (old_body) >= 0;
3639 rtx old_set = single_set (insn);
3641 rtx orig_operand[MAX_RECOG_OPERANDS];
3642 rtx orig_dup[MAX_RECOG_OPERANDS];
3643 struct elim_table *ep;
3644 rtx plus_src, plus_cst_src;
3647 if (! insn_is_asm && icode < 0)
3649 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3650 || GET_CODE (PATTERN (insn)) == CLOBBER
3651 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3652 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3653 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3654 || DEBUG_INSN_P (insn));
3658 if (old_set != 0 && REG_P (SET_DEST (old_set))
3659 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3661 /* Check for setting an eliminable register. */
3662 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3663 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3667 /* We allow one special case which happens to work on all machines we
3668 currently support: a single set with the source or a REG_EQUAL
3669 note being a PLUS of an eliminable register and a constant. */
3670 plus_src = plus_cst_src = 0;
3672 if (old_set && REG_P (SET_DEST (old_set)))
3675 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3676 plus_src = SET_SRC (old_set);
3677 /* First see if the source is of the form (plus (...) CST). */
3679 && CONST_INT_P (XEXP (plus_src, 1)))
3680 plus_cst_src = plus_src;
3681 else if (REG_P (SET_SRC (old_set))
3684 /* Otherwise, see if we have a REG_EQUAL note of the form
3685 (plus (...) CST). */
3687 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3689 if ((REG_NOTE_KIND (links) == REG_EQUAL
3690 || REG_NOTE_KIND (links) == REG_EQUIV)
3691 && GET_CODE (XEXP (links, 0)) == PLUS
3692 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3694 plus_cst_src = XEXP (links, 0);
3701 /* Determine the effects of this insn on elimination offsets. */
3702 elimination_effects (old_body, VOIDmode);
3704 /* Eliminate all eliminable registers occurring in operands that
3705 can be handled by reload. */
3706 extract_insn (insn);
3707 for (i = 0; i < recog_data.n_dups; i++)
3708 orig_dup[i] = *recog_data.dup_loc[i];
3710 for (i = 0; i < recog_data.n_operands; i++)
3712 orig_operand[i] = recog_data.operand[i];
3714 /* For an asm statement, every operand is eliminable. */
3715 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3717 bool is_set_src, in_plus;
3719 /* Check for setting a register that we know about. */
3720 if (recog_data.operand_type[i] != OP_IN
3721 && REG_P (orig_operand[i]))
3723 /* If we are assigning to a register that can be eliminated, it
3724 must be as part of a PARALLEL, since the code above handles
3725 single SETs. We must indicate that we can no longer
3726 eliminate this reg. */
3727 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3729 if (ep->from_rtx == orig_operand[i])
3730 ep->can_eliminate = 0;
3733 /* Companion to the above plus substitution, we can allow
3734 invariants as the source of a plain move. */
3736 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3738 if (is_set_src && !sets_reg_p)
3739 note_reg_elim_costly (&SET_SRC (old_set), insn);
3741 if (plus_src && sets_reg_p
3742 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3743 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3746 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3748 is_set_src || in_plus, true);
3749 /* Terminate the search in check_eliminable_occurrences at
3751 *recog_data.operand_loc[i] = 0;
3755 for (i = 0; i < recog_data.n_dups; i++)
3756 *recog_data.dup_loc[i]
3757 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3759 /* If any eliminable remain, they aren't eliminable anymore. */
3760 check_eliminable_occurrences (old_body);
3762 /* Restore the old body. */
3763 for (i = 0; i < recog_data.n_operands; i++)
3764 *recog_data.operand_loc[i] = orig_operand[i];
3765 for (i = 0; i < recog_data.n_dups; i++)
3766 *recog_data.dup_loc[i] = orig_dup[i];
3768 /* Update all elimination pairs to reflect the status after the current
3769 insn. The changes we make were determined by the earlier call to
3770 elimination_effects. */
3772 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3774 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3775 ep->can_eliminate = 0;
3777 ep->ref_outside_mem = 0;
3783 /* Loop through all elimination pairs.
3784 Recalculate the number not at initial offset.
3786 Compute the maximum offset (minimum offset if the stack does not
3787 grow downward) for each elimination pair. */
3790 update_eliminable_offsets (void)
3792 struct elim_table *ep;
3794 num_not_at_initial_offset = 0;
3795 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3797 ep->previous_offset = ep->offset;
3798 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3799 num_not_at_initial_offset++;
3803 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3804 replacement we currently believe is valid, mark it as not eliminable if X
3805 modifies DEST in any way other than by adding a constant integer to it.
3807 If DEST is the frame pointer, we do nothing because we assume that
3808 all assignments to the hard frame pointer are nonlocal gotos and are being
3809 done at a time when they are valid and do not disturb anything else.
3810 Some machines want to eliminate a fake argument pointer with either the
3811 frame or stack pointer. Assignments to the hard frame pointer must not
3812 prevent this elimination.
3814 Called via note_stores from reload before starting its passes to scan
3815 the insns of the function. */
3818 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3822 /* A SUBREG of a hard register here is just changing its mode. We should
3823 not see a SUBREG of an eliminable hard register, but check just in
3825 if (GET_CODE (dest) == SUBREG)
3826 dest = SUBREG_REG (dest);
3828 if (dest == hard_frame_pointer_rtx)
3831 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3832 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3833 && (GET_CODE (x) != SET
3834 || GET_CODE (SET_SRC (x)) != PLUS
3835 || XEXP (SET_SRC (x), 0) != dest
3836 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3838 reg_eliminate[i].can_eliminate_previous
3839 = reg_eliminate[i].can_eliminate = 0;
3844 /* Verify that the initial elimination offsets did not change since the
3845 last call to set_initial_elim_offsets. This is used to catch cases
3846 where something illegal happened during reload_as_needed that could
3847 cause incorrect code to be generated if we did not check for it. */
3850 verify_initial_elim_offsets (void)
3854 if (!num_eliminable)
3857 #ifdef ELIMINABLE_REGS
3859 struct elim_table *ep;
3861 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3863 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3864 if (t != ep->initial_offset)
3869 INITIAL_FRAME_POINTER_OFFSET (t);
3870 if (t != reg_eliminate[0].initial_offset)
3877 /* Reset all offsets on eliminable registers to their initial values. */
3880 set_initial_elim_offsets (void)
3882 struct elim_table *ep = reg_eliminate;
3884 #ifdef ELIMINABLE_REGS
3885 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3887 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3888 ep->previous_offset = ep->offset = ep->initial_offset;
3891 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3892 ep->previous_offset = ep->offset = ep->initial_offset;
3895 num_not_at_initial_offset = 0;
3898 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3901 set_initial_eh_label_offset (rtx label)
3903 set_label_offsets (label, NULL_RTX, 1);
3906 /* Initialize the known label offsets.
3907 Set a known offset for each forced label to be at the initial offset
3908 of each elimination. We do this because we assume that all
3909 computed jumps occur from a location where each elimination is
3910 at its initial offset.
3911 For all other labels, show that we don't know the offsets. */
3914 set_initial_label_offsets (void)
3917 memset (offsets_known_at, 0, num_labels);
3919 for (x = forced_labels; x; x = XEXP (x, 1))
3921 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3923 for_each_eh_label (set_initial_eh_label_offset);
3926 /* Set all elimination offsets to the known values for the code label given
3930 set_offsets_for_label (rtx insn)
3933 int label_nr = CODE_LABEL_NUMBER (insn);
3934 struct elim_table *ep;
3936 num_not_at_initial_offset = 0;
3937 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3939 ep->offset = ep->previous_offset
3940 = offsets_at[label_nr - first_label_num][i];
3941 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3942 num_not_at_initial_offset++;
3946 /* See if anything that happened changes which eliminations are valid.
3947 For example, on the SPARC, whether or not the frame pointer can
3948 be eliminated can depend on what registers have been used. We need
3949 not check some conditions again (such as flag_omit_frame_pointer)
3950 since they can't have changed. */
3953 update_eliminables (HARD_REG_SET *pset)
3955 int previous_frame_pointer_needed = frame_pointer_needed;
3956 struct elim_table *ep;
3958 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3959 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3960 && targetm.frame_pointer_required ())
3961 #ifdef ELIMINABLE_REGS
3962 || ! targetm.can_eliminate (ep->from, ep->to)
3965 ep->can_eliminate = 0;
3967 /* Look for the case where we have discovered that we can't replace
3968 register A with register B and that means that we will now be
3969 trying to replace register A with register C. This means we can
3970 no longer replace register C with register B and we need to disable
3971 such an elimination, if it exists. This occurs often with A == ap,
3972 B == sp, and C == fp. */
3974 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3976 struct elim_table *op;
3979 if (! ep->can_eliminate && ep->can_eliminate_previous)
3981 /* Find the current elimination for ep->from, if there is a
3983 for (op = reg_eliminate;
3984 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3985 if (op->from == ep->from && op->can_eliminate)
3991 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3993 for (op = reg_eliminate;
3994 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3995 if (op->from == new_to && op->to == ep->to)
3996 op->can_eliminate = 0;
4000 /* See if any registers that we thought we could eliminate the previous
4001 time are no longer eliminable. If so, something has changed and we
4002 must spill the register. Also, recompute the number of eliminable
4003 registers and see if the frame pointer is needed; it is if there is
4004 no elimination of the frame pointer that we can perform. */
4006 frame_pointer_needed = 1;
4007 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4009 if (ep->can_eliminate
4010 && ep->from == FRAME_POINTER_REGNUM
4011 && ep->to != HARD_FRAME_POINTER_REGNUM
4012 && (! SUPPORTS_STACK_ALIGNMENT
4013 || ! crtl->stack_realign_needed))
4014 frame_pointer_needed = 0;
4016 if (! ep->can_eliminate && ep->can_eliminate_previous)
4018 ep->can_eliminate_previous = 0;
4019 SET_HARD_REG_BIT (*pset, ep->from);
4024 /* If we didn't need a frame pointer last time, but we do now, spill
4025 the hard frame pointer. */
4026 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4027 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4030 /* Return true if X is used as the target register of an elimination. */
4033 elimination_target_reg_p (rtx x)
4035 struct elim_table *ep;
4037 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4038 if (ep->to_rtx == x && ep->can_eliminate)
4044 /* Initialize the table of registers to eliminate.
4045 Pre-condition: global flag frame_pointer_needed has been set before
4046 calling this function. */
4049 init_elim_table (void)
4051 struct elim_table *ep;
4052 #ifdef ELIMINABLE_REGS
4053 const struct elim_table_1 *ep1;
4057 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4061 #ifdef ELIMINABLE_REGS
4062 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4063 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4065 ep->from = ep1->from;
4067 ep->can_eliminate = ep->can_eliminate_previous
4068 = (targetm.can_eliminate (ep->from, ep->to)
4069 && ! (ep->to == STACK_POINTER_REGNUM
4070 && frame_pointer_needed
4071 && (! SUPPORTS_STACK_ALIGNMENT
4072 || ! stack_realign_fp)));
4075 reg_eliminate[0].from = reg_eliminate_1[0].from;
4076 reg_eliminate[0].to = reg_eliminate_1[0].to;
4077 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4078 = ! frame_pointer_needed;
4081 /* Count the number of eliminable registers and build the FROM and TO
4082 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4083 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4084 We depend on this. */
4085 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4087 num_eliminable += ep->can_eliminate;
4088 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4089 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4093 /* Find all the pseudo registers that didn't get hard regs
4094 but do have known equivalent constants or memory slots.
4095 These include parameters (known equivalent to parameter slots)
4096 and cse'd or loop-moved constant memory addresses.
4098 Record constant equivalents in reg_equiv_constant
4099 so they will be substituted by find_reloads.
4100 Record memory equivalents in reg_mem_equiv so they can
4101 be substituted eventually by altering the REG-rtx's. */
4104 init_eliminable_invariants (rtx first, bool do_subregs)
4111 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4113 reg_max_ref_width = NULL;
4115 num_eliminable_invariants = 0;
4117 first_label_num = get_first_label_num ();
4118 num_labels = max_label_num () - first_label_num;
4120 /* Allocate the tables used to store offset information at labels. */
4121 offsets_known_at = XNEWVEC (char, num_labels);
4122 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4124 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4125 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4126 find largest such for each pseudo. FIRST is the head of the insn
4129 for (insn = first; insn; insn = NEXT_INSN (insn))
4131 rtx set = single_set (insn);
4133 /* We may introduce USEs that we want to remove at the end, so
4134 we'll mark them with QImode. Make sure there are no
4135 previously-marked insns left by say regmove. */
4136 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4137 && GET_MODE (insn) != VOIDmode)
4138 PUT_MODE (insn, VOIDmode);
4140 if (do_subregs && NONDEBUG_INSN_P (insn))
4141 scan_paradoxical_subregs (PATTERN (insn));
4143 if (set != 0 && REG_P (SET_DEST (set)))
4145 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4151 i = REGNO (SET_DEST (set));
4154 if (i <= LAST_VIRTUAL_REGISTER)
4157 /* If flag_pic and we have constant, verify it's legitimate. */
4159 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4161 /* It can happen that a REG_EQUIV note contains a MEM
4162 that is not a legitimate memory operand. As later
4163 stages of reload assume that all addresses found
4164 in the reg_equiv_* arrays were originally legitimate,
4165 we ignore such REG_EQUIV notes. */
4166 if (memory_operand (x, VOIDmode))
4168 /* Always unshare the equivalence, so we can
4169 substitute into this insn without touching the
4171 reg_equiv_memory_loc (i) = copy_rtx (x);
4173 else if (function_invariant_p (x))
4175 enum machine_mode mode;
4177 mode = GET_MODE (SET_DEST (set));
4178 if (GET_CODE (x) == PLUS)
4180 /* This is PLUS of frame pointer and a constant,
4181 and might be shared. Unshare it. */
4182 reg_equiv_invariant (i) = copy_rtx (x);
4183 num_eliminable_invariants++;
4185 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4187 reg_equiv_invariant (i) = x;
4188 num_eliminable_invariants++;
4190 else if (targetm.legitimate_constant_p (mode, x))
4191 reg_equiv_constant (i) = x;
4194 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4195 if (! reg_equiv_memory_loc (i))
4196 reg_equiv_init (i) = NULL_RTX;
4201 reg_equiv_init (i) = NULL_RTX;
4206 reg_equiv_init (i) = NULL_RTX;
4211 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4212 if (reg_equiv_init (i))
4214 fprintf (dump_file, "init_insns for %u: ", i);
4215 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4216 fprintf (dump_file, "\n");
4220 /* Indicate that we no longer have known memory locations or constants.
4221 Free all data involved in tracking these. */
4224 free_reg_equiv (void)
4229 free (offsets_known_at);
4232 offsets_known_at = 0;
4234 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4235 if (reg_equiv_alt_mem_list (i))
4236 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4237 VEC_free (reg_equivs_t, gc, reg_equivs);
4242 /* Kick all pseudos out of hard register REGNO.
4244 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4245 because we found we can't eliminate some register. In the case, no pseudos
4246 are allowed to be in the register, even if they are only in a block that
4247 doesn't require spill registers, unlike the case when we are spilling this
4248 hard reg to produce another spill register.
4250 Return nonzero if any pseudos needed to be kicked out. */
4253 spill_hard_reg (unsigned int regno, int cant_eliminate)
4259 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4260 df_set_regs_ever_live (regno, true);
4263 /* Spill every pseudo reg that was allocated to this reg
4264 or to something that overlaps this reg. */
4266 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4267 if (reg_renumber[i] >= 0
4268 && (unsigned int) reg_renumber[i] <= regno
4269 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4270 SET_REGNO_REG_SET (&spilled_pseudos, i);
4273 /* After find_reload_regs has been run for all insn that need reloads,
4274 and/or spill_hard_regs was called, this function is used to actually
4275 spill pseudo registers and try to reallocate them. It also sets up the
4276 spill_regs array for use by choose_reload_regs. */
4279 finish_spills (int global)
4281 struct insn_chain *chain;
4282 int something_changed = 0;
4284 reg_set_iterator rsi;
4286 /* Build the spill_regs array for the function. */
4287 /* If there are some registers still to eliminate and one of the spill regs
4288 wasn't ever used before, additional stack space may have to be
4289 allocated to store this register. Thus, we may have changed the offset
4290 between the stack and frame pointers, so mark that something has changed.
4292 One might think that we need only set VAL to 1 if this is a call-used
4293 register. However, the set of registers that must be saved by the
4294 prologue is not identical to the call-used set. For example, the
4295 register used by the call insn for the return PC is a call-used register,
4296 but must be saved by the prologue. */
4299 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4300 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4302 spill_reg_order[i] = n_spills;
4303 spill_regs[n_spills++] = i;
4304 if (num_eliminable && ! df_regs_ever_live_p (i))
4305 something_changed = 1;
4306 df_set_regs_ever_live (i, true);
4309 spill_reg_order[i] = -1;
4311 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4312 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4314 /* Record the current hard register the pseudo is allocated to
4315 in pseudo_previous_regs so we avoid reallocating it to the
4316 same hard reg in a later pass. */
4317 gcc_assert (reg_renumber[i] >= 0);
4319 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4320 /* Mark it as no longer having a hard register home. */
4321 reg_renumber[i] = -1;
4322 if (ira_conflicts_p)
4323 /* Inform IRA about the change. */
4324 ira_mark_allocation_change (i);
4325 /* We will need to scan everything again. */
4326 something_changed = 1;
4329 /* Retry global register allocation if possible. */
4330 if (global && ira_conflicts_p)
4334 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4335 /* For every insn that needs reloads, set the registers used as spill
4336 regs in pseudo_forbidden_regs for every pseudo live across the
4338 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4340 EXECUTE_IF_SET_IN_REG_SET
4341 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4343 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4344 chain->used_spill_regs);
4346 EXECUTE_IF_SET_IN_REG_SET
4347 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4349 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4350 chain->used_spill_regs);
4354 /* Retry allocating the pseudos spilled in IRA and the
4355 reload. For each reg, merge the various reg sets that
4356 indicate which hard regs can't be used, and call
4357 ira_reassign_pseudos. */
4358 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4359 if (reg_old_renumber[i] != reg_renumber[i])
4361 if (reg_renumber[i] < 0)
4362 temp_pseudo_reg_arr[n++] = i;
4364 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4366 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4367 bad_spill_regs_global,
4368 pseudo_forbidden_regs, pseudo_previous_regs,
4370 something_changed = 1;
4372 /* Fix up the register information in the insn chain.
4373 This involves deleting those of the spilled pseudos which did not get
4374 a new hard register home from the live_{before,after} sets. */
4375 for (chain = reload_insn_chain; chain; chain = chain->next)
4377 HARD_REG_SET used_by_pseudos;
4378 HARD_REG_SET used_by_pseudos2;
4380 if (! ira_conflicts_p)
4382 /* Don't do it for IRA because IRA and the reload still can
4383 assign hard registers to the spilled pseudos on next
4384 reload iterations. */
4385 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4386 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4388 /* Mark any unallocated hard regs as available for spills. That
4389 makes inheritance work somewhat better. */
4390 if (chain->need_reload)
4392 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4393 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4394 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4396 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4397 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4398 /* Value of chain->used_spill_regs from previous iteration
4399 may be not included in the value calculated here because
4400 of possible removing caller-saves insns (see function
4401 delete_caller_save_insns. */
4402 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4403 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4407 CLEAR_REG_SET (&changed_allocation_pseudos);
4408 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4409 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4411 int regno = reg_renumber[i];
4412 if (reg_old_renumber[i] == regno)
4415 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4417 alter_reg (i, reg_old_renumber[i], false);
4418 reg_old_renumber[i] = regno;
4422 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4424 fprintf (dump_file, " Register %d now in %d.\n\n",
4425 i, reg_renumber[i]);
4429 return something_changed;
4432 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4435 scan_paradoxical_subregs (rtx x)
4439 enum rtx_code code = GET_CODE (x);
4450 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4458 if (REG_P (SUBREG_REG (x))
4459 && (GET_MODE_SIZE (GET_MODE (x))
4460 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4462 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4463 = GET_MODE_SIZE (GET_MODE (x));
4464 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4472 fmt = GET_RTX_FORMAT (code);
4473 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4476 scan_paradoxical_subregs (XEXP (x, i));
4477 else if (fmt[i] == 'E')
4480 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4481 scan_paradoxical_subregs (XVECEXP (x, i, j));
4486 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4487 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4488 and apply the corresponding narrowing subreg to *OTHER_PTR.
4489 Return true if the operands were changed, false otherwise. */
4492 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4494 rtx op, inner, other, tem;
4497 if (!paradoxical_subreg_p (op))
4499 inner = SUBREG_REG (op);
4502 tem = gen_lowpart_common (GET_MODE (inner), other);
4506 /* If the lowpart operation turned a hard register into a subreg,
4507 rather than simplifying it to another hard register, then the
4508 mode change cannot be properly represented. For example, OTHER
4509 might be valid in its current mode, but not in the new one. */
4510 if (GET_CODE (tem) == SUBREG
4512 && HARD_REGISTER_P (other))
4520 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4521 examine all of the reload insns between PREV and NEXT exclusive, and
4522 annotate all that may trap. */
4525 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4527 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4530 if (!insn_could_throw_p (insn))
4531 remove_note (insn, note);
4532 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4535 /* Reload pseudo-registers into hard regs around each insn as needed.
4536 Additional register load insns are output before the insn that needs it
4537 and perhaps store insns after insns that modify the reloaded pseudo reg.
4539 reg_last_reload_reg and reg_reloaded_contents keep track of
4540 which registers are already available in reload registers.
4541 We update these for the reloads that we perform,
4542 as the insns are scanned. */
4545 reload_as_needed (int live_known)
4547 struct insn_chain *chain;
4548 #if defined (AUTO_INC_DEC)
4553 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4554 memset (spill_reg_store, 0, sizeof spill_reg_store);
4555 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4556 INIT_REG_SET (®_has_output_reload);
4557 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4558 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4560 set_initial_elim_offsets ();
4562 for (chain = reload_insn_chain; chain; chain = chain->next)
4565 rtx insn = chain->insn;
4566 rtx old_next = NEXT_INSN (insn);
4568 rtx old_prev = PREV_INSN (insn);
4571 /* If we pass a label, copy the offsets from the label information
4572 into the current offsets of each elimination. */
4574 set_offsets_for_label (insn);
4576 else if (INSN_P (insn))
4578 regset_head regs_to_forget;
4579 INIT_REG_SET (®s_to_forget);
4580 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4582 /* If this is a USE and CLOBBER of a MEM, ensure that any
4583 references to eliminable registers have been removed. */
4585 if ((GET_CODE (PATTERN (insn)) == USE
4586 || GET_CODE (PATTERN (insn)) == CLOBBER)
4587 && MEM_P (XEXP (PATTERN (insn), 0)))
4588 XEXP (XEXP (PATTERN (insn), 0), 0)
4589 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4590 GET_MODE (XEXP (PATTERN (insn), 0)),
4593 /* If we need to do register elimination processing, do so.
4594 This might delete the insn, in which case we are done. */
4595 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4597 eliminate_regs_in_insn (insn, 1);
4600 update_eliminable_offsets ();
4601 CLEAR_REG_SET (®s_to_forget);
4606 /* If need_elim is nonzero but need_reload is zero, one might think
4607 that we could simply set n_reloads to 0. However, find_reloads
4608 could have done some manipulation of the insn (such as swapping
4609 commutative operands), and these manipulations are lost during
4610 the first pass for every insn that needs register elimination.
4611 So the actions of find_reloads must be redone here. */
4613 if (! chain->need_elim && ! chain->need_reload
4614 && ! chain->need_operand_change)
4616 /* First find the pseudo regs that must be reloaded for this insn.
4617 This info is returned in the tables reload_... (see reload.h).
4618 Also modify the body of INSN by substituting RELOAD
4619 rtx's for those pseudo regs. */
4622 CLEAR_REG_SET (®_has_output_reload);
4623 CLEAR_HARD_REG_SET (reg_is_output_reload);
4625 find_reloads (insn, 1, spill_indirect_levels, live_known,
4631 rtx next = NEXT_INSN (insn);
4634 prev = PREV_INSN (insn);
4636 /* Now compute which reload regs to reload them into. Perhaps
4637 reusing reload regs from previous insns, or else output
4638 load insns to reload them. Maybe output store insns too.
4639 Record the choices of reload reg in reload_reg_rtx. */
4640 choose_reload_regs (chain);
4642 /* Generate the insns to reload operands into or out of
4643 their reload regs. */
4644 emit_reload_insns (chain);
4646 /* Substitute the chosen reload regs from reload_reg_rtx
4647 into the insn's body (or perhaps into the bodies of other
4648 load and store insn that we just made for reloading
4649 and that we moved the structure into). */
4650 subst_reloads (insn);
4652 /* Adjust the exception region notes for loads and stores. */
4653 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4654 fixup_eh_region_note (insn, prev, next);
4656 /* If this was an ASM, make sure that all the reload insns
4657 we have generated are valid. If not, give an error
4659 if (asm_noperands (PATTERN (insn)) >= 0)
4660 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4661 if (p != insn && INSN_P (p)
4662 && GET_CODE (PATTERN (p)) != USE
4663 && (recog_memoized (p) < 0
4664 || (extract_insn (p), ! constrain_operands (1))))
4666 error_for_asm (insn,
4667 "%<asm%> operand requires "
4668 "impossible reload");
4673 if (num_eliminable && chain->need_elim)
4674 update_eliminable_offsets ();
4676 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4677 is no longer validly lying around to save a future reload.
4678 Note that this does not detect pseudos that were reloaded
4679 for this insn in order to be stored in
4680 (obeying register constraints). That is correct; such reload
4681 registers ARE still valid. */
4682 forget_marked_reloads (®s_to_forget);
4683 CLEAR_REG_SET (®s_to_forget);
4685 /* There may have been CLOBBER insns placed after INSN. So scan
4686 between INSN and NEXT and use them to forget old reloads. */
4687 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4688 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4689 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4692 /* Likewise for regs altered by auto-increment in this insn.
4693 REG_INC notes have been changed by reloading:
4694 find_reloads_address_1 records substitutions for them,
4695 which have been performed by subst_reloads above. */
4696 for (i = n_reloads - 1; i >= 0; i--)
4698 rtx in_reg = rld[i].in_reg;
4701 enum rtx_code code = GET_CODE (in_reg);
4702 /* PRE_INC / PRE_DEC will have the reload register ending up
4703 with the same value as the stack slot, but that doesn't
4704 hold true for POST_INC / POST_DEC. Either we have to
4705 convert the memory access to a true POST_INC / POST_DEC,
4706 or we can't use the reload register for inheritance. */
4707 if ((code == POST_INC || code == POST_DEC)
4708 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4709 REGNO (rld[i].reg_rtx))
4710 /* Make sure it is the inc/dec pseudo, and not
4711 some other (e.g. output operand) pseudo. */
4712 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4713 == REGNO (XEXP (in_reg, 0))))
4716 rtx reload_reg = rld[i].reg_rtx;
4717 enum machine_mode mode = GET_MODE (reload_reg);
4721 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4723 /* We really want to ignore REG_INC notes here, so
4724 use PATTERN (p) as argument to reg_set_p . */
4725 if (reg_set_p (reload_reg, PATTERN (p)))
4727 n = count_occurrences (PATTERN (p), reload_reg, 0);
4733 = gen_rtx_fmt_e (code, mode, reload_reg);
4735 validate_replace_rtx_group (reload_reg,
4737 n = verify_changes (0);
4739 /* We must also verify that the constraints
4740 are met after the replacement. Make sure
4741 extract_insn is only called for an insn
4742 where the replacements were found to be
4747 n = constrain_operands (1);
4750 /* If the constraints were not met, then
4751 undo the replacement, else confirm it. */
4755 confirm_change_group ();
4761 add_reg_note (p, REG_INC, reload_reg);
4762 /* Mark this as having an output reload so that the
4763 REG_INC processing code below won't invalidate
4764 the reload for inheritance. */
4765 SET_HARD_REG_BIT (reg_is_output_reload,
4766 REGNO (reload_reg));
4767 SET_REGNO_REG_SET (®_has_output_reload,
4768 REGNO (XEXP (in_reg, 0)));
4771 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4774 else if ((code == PRE_INC || code == PRE_DEC)
4775 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4776 REGNO (rld[i].reg_rtx))
4777 /* Make sure it is the inc/dec pseudo, and not
4778 some other (e.g. output operand) pseudo. */
4779 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4780 == REGNO (XEXP (in_reg, 0))))
4782 SET_HARD_REG_BIT (reg_is_output_reload,
4783 REGNO (rld[i].reg_rtx));
4784 SET_REGNO_REG_SET (®_has_output_reload,
4785 REGNO (XEXP (in_reg, 0)));
4787 else if (code == PRE_INC || code == PRE_DEC
4788 || code == POST_INC || code == POST_DEC)
4790 int in_regno = REGNO (XEXP (in_reg, 0));
4792 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4795 bool forget_p = true;
4797 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4798 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4801 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4804 if (x == reg_reloaded_insn[in_hard_regno])
4810 /* If for some reasons, we didn't set up
4811 reg_last_reload_reg in this insn,
4812 invalidate inheritance from previous
4813 insns for the incremented/decremented
4814 register. Such registers will be not in
4815 reg_has_output_reload. Invalidate it
4816 also if the corresponding element in
4817 reg_reloaded_insn is also
4820 forget_old_reloads_1 (XEXP (in_reg, 0),
4826 /* If a pseudo that got a hard register is auto-incremented,
4827 we must purge records of copying it into pseudos without
4829 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4830 if (REG_NOTE_KIND (x) == REG_INC)
4832 /* See if this pseudo reg was reloaded in this insn.
4833 If so, its last-reload info is still valid
4834 because it is based on this insn's reload. */
4835 for (i = 0; i < n_reloads; i++)
4836 if (rld[i].out == XEXP (x, 0))
4840 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4844 /* A reload reg's contents are unknown after a label. */
4846 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4848 /* Don't assume a reload reg is still good after a call insn
4849 if it is a call-used reg, or if it contains a value that will
4850 be partially clobbered by the call. */
4851 else if (CALL_P (insn))
4853 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4854 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4856 /* If this is a call to a setjmp-type function, we must not
4857 reuse any reload reg contents across the call; that will
4858 just be clobbered by other uses of the register in later
4859 code, before the longjmp. */
4860 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4861 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4866 free (reg_last_reload_reg);
4867 CLEAR_REG_SET (®_has_output_reload);
4870 /* Discard all record of any value reloaded from X,
4871 or reloaded in X from someplace else;
4872 unless X is an output reload reg of the current insn.
4874 X may be a hard reg (the reload reg)
4875 or it may be a pseudo reg that was reloaded from.
4877 When DATA is non-NULL just mark the registers in regset
4878 to be forgotten later. */
4881 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4886 regset regs = (regset) data;
4888 /* note_stores does give us subregs of hard regs,
4889 subreg_regno_offset requires a hard reg. */
4890 while (GET_CODE (x) == SUBREG)
4892 /* We ignore the subreg offset when calculating the regno,
4893 because we are using the entire underlying hard register
4903 if (regno >= FIRST_PSEUDO_REGISTER)
4909 nr = hard_regno_nregs[regno][GET_MODE (x)];
4910 /* Storing into a spilled-reg invalidates its contents.
4911 This can happen if a block-local pseudo is allocated to that reg
4912 and it wasn't spilled because this block's total need is 0.
4913 Then some insn might have an optional reload and use this reg. */
4915 for (i = 0; i < nr; i++)
4916 /* But don't do this if the reg actually serves as an output
4917 reload reg in the current instruction. */
4919 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4921 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4922 spill_reg_store[regno + i] = 0;
4928 SET_REGNO_REG_SET (regs, regno + nr);
4931 /* Since value of X has changed,
4932 forget any value previously copied from it. */
4935 /* But don't forget a copy if this is the output reload
4936 that establishes the copy's validity. */
4938 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4939 reg_last_reload_reg[regno + nr] = 0;
4943 /* Forget the reloads marked in regset by previous function. */
4945 forget_marked_reloads (regset regs)
4948 reg_set_iterator rsi;
4949 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4951 if (reg < FIRST_PSEUDO_REGISTER
4952 /* But don't do this if the reg actually serves as an output
4953 reload reg in the current instruction. */
4955 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4957 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4958 spill_reg_store[reg] = 0;
4961 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4962 reg_last_reload_reg[reg] = 0;
4966 /* The following HARD_REG_SETs indicate when each hard register is
4967 used for a reload of various parts of the current insn. */
4969 /* If reg is unavailable for all reloads. */
4970 static HARD_REG_SET reload_reg_unavailable;
4971 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4972 static HARD_REG_SET reload_reg_used;
4973 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4974 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4975 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4976 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4977 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4978 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4979 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4980 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4981 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4982 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4983 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4984 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4985 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4986 static HARD_REG_SET reload_reg_used_in_op_addr;
4987 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4988 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4989 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4990 static HARD_REG_SET reload_reg_used_in_insn;
4991 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4992 static HARD_REG_SET reload_reg_used_in_other_addr;
4994 /* If reg is in use as a reload reg for any sort of reload. */
4995 static HARD_REG_SET reload_reg_used_at_all;
4997 /* If reg is use as an inherited reload. We just mark the first register
4999 static HARD_REG_SET reload_reg_used_for_inherit;
5001 /* Records which hard regs are used in any way, either as explicit use or
5002 by being allocated to a pseudo during any point of the current insn. */
5003 static HARD_REG_SET reg_used_in_insn;
5005 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5006 TYPE. MODE is used to indicate how many consecutive regs are
5010 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5011 enum machine_mode mode)
5016 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5019 case RELOAD_FOR_INPUT_ADDRESS:
5020 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5023 case RELOAD_FOR_INPADDR_ADDRESS:
5024 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5027 case RELOAD_FOR_OUTPUT_ADDRESS:
5028 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5031 case RELOAD_FOR_OUTADDR_ADDRESS:
5032 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5035 case RELOAD_FOR_OPERAND_ADDRESS:
5036 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5039 case RELOAD_FOR_OPADDR_ADDR:
5040 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5043 case RELOAD_FOR_OTHER_ADDRESS:
5044 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5047 case RELOAD_FOR_INPUT:
5048 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5051 case RELOAD_FOR_OUTPUT:
5052 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5055 case RELOAD_FOR_INSN:
5056 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5060 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5063 /* Similarly, but show REGNO is no longer in use for a reload. */
5066 clear_reload_reg_in_use (unsigned int regno, int opnum,
5067 enum reload_type type, enum machine_mode mode)
5069 unsigned int nregs = hard_regno_nregs[regno][mode];
5070 unsigned int start_regno, end_regno, r;
5072 /* A complication is that for some reload types, inheritance might
5073 allow multiple reloads of the same types to share a reload register.
5074 We set check_opnum if we have to check only reloads with the same
5075 operand number, and check_any if we have to check all reloads. */
5076 int check_opnum = 0;
5078 HARD_REG_SET *used_in_set;
5083 used_in_set = &reload_reg_used;
5086 case RELOAD_FOR_INPUT_ADDRESS:
5087 used_in_set = &reload_reg_used_in_input_addr[opnum];
5090 case RELOAD_FOR_INPADDR_ADDRESS:
5092 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5095 case RELOAD_FOR_OUTPUT_ADDRESS:
5096 used_in_set = &reload_reg_used_in_output_addr[opnum];
5099 case RELOAD_FOR_OUTADDR_ADDRESS:
5101 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5104 case RELOAD_FOR_OPERAND_ADDRESS:
5105 used_in_set = &reload_reg_used_in_op_addr;
5108 case RELOAD_FOR_OPADDR_ADDR:
5110 used_in_set = &reload_reg_used_in_op_addr_reload;
5113 case RELOAD_FOR_OTHER_ADDRESS:
5114 used_in_set = &reload_reg_used_in_other_addr;
5118 case RELOAD_FOR_INPUT:
5119 used_in_set = &reload_reg_used_in_input[opnum];
5122 case RELOAD_FOR_OUTPUT:
5123 used_in_set = &reload_reg_used_in_output[opnum];
5126 case RELOAD_FOR_INSN:
5127 used_in_set = &reload_reg_used_in_insn;
5132 /* We resolve conflicts with remaining reloads of the same type by
5133 excluding the intervals of reload registers by them from the
5134 interval of freed reload registers. Since we only keep track of
5135 one set of interval bounds, we might have to exclude somewhat
5136 more than what would be necessary if we used a HARD_REG_SET here.
5137 But this should only happen very infrequently, so there should
5138 be no reason to worry about it. */
5140 start_regno = regno;
5141 end_regno = regno + nregs;
5142 if (check_opnum || check_any)
5144 for (i = n_reloads - 1; i >= 0; i--)
5146 if (rld[i].when_needed == type
5147 && (check_any || rld[i].opnum == opnum)
5150 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5151 unsigned int conflict_end
5152 = end_hard_regno (rld[i].mode, conflict_start);
5154 /* If there is an overlap with the first to-be-freed register,
5155 adjust the interval start. */
5156 if (conflict_start <= start_regno && conflict_end > start_regno)
5157 start_regno = conflict_end;
5158 /* Otherwise, if there is a conflict with one of the other
5159 to-be-freed registers, adjust the interval end. */
5160 if (conflict_start > start_regno && conflict_start < end_regno)
5161 end_regno = conflict_start;
5166 for (r = start_regno; r < end_regno; r++)
5167 CLEAR_HARD_REG_BIT (*used_in_set, r);
5170 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5171 specified by OPNUM and TYPE. */
5174 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5178 /* In use for a RELOAD_OTHER means it's not available for anything. */
5179 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5180 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5186 /* In use for anything means we can't use it for RELOAD_OTHER. */
5187 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5188 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5189 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5190 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5193 for (i = 0; i < reload_n_operands; i++)
5194 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5195 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5196 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5197 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5198 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5199 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5204 case RELOAD_FOR_INPUT:
5205 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5206 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5209 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5212 /* If it is used for some other input, can't use it. */
5213 for (i = 0; i < reload_n_operands; i++)
5214 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5217 /* If it is used in a later operand's address, can't use it. */
5218 for (i = opnum + 1; i < reload_n_operands; i++)
5219 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5220 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5225 case RELOAD_FOR_INPUT_ADDRESS:
5226 /* Can't use a register if it is used for an input address for this
5227 operand or used as an input in an earlier one. */
5228 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5229 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5232 for (i = 0; i < opnum; i++)
5233 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5238 case RELOAD_FOR_INPADDR_ADDRESS:
5239 /* Can't use a register if it is used for an input address
5240 for this operand or used as an input in an earlier
5242 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5245 for (i = 0; i < opnum; i++)
5246 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5251 case RELOAD_FOR_OUTPUT_ADDRESS:
5252 /* Can't use a register if it is used for an output address for this
5253 operand or used as an output in this or a later operand. Note
5254 that multiple output operands are emitted in reverse order, so
5255 the conflicting ones are those with lower indices. */
5256 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5259 for (i = 0; i <= opnum; i++)
5260 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5265 case RELOAD_FOR_OUTADDR_ADDRESS:
5266 /* Can't use a register if it is used for an output address
5267 for this operand or used as an output in this or a
5268 later operand. Note that multiple output operands are
5269 emitted in reverse order, so the conflicting ones are
5270 those with lower indices. */
5271 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5274 for (i = 0; i <= opnum; i++)
5275 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5280 case RELOAD_FOR_OPERAND_ADDRESS:
5281 for (i = 0; i < reload_n_operands; i++)
5282 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5285 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5286 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5288 case RELOAD_FOR_OPADDR_ADDR:
5289 for (i = 0; i < reload_n_operands; i++)
5290 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5293 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5295 case RELOAD_FOR_OUTPUT:
5296 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5297 outputs, or an operand address for this or an earlier output.
5298 Note that multiple output operands are emitted in reverse order,
5299 so the conflicting ones are those with higher indices. */
5300 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5303 for (i = 0; i < reload_n_operands; i++)
5304 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5307 for (i = opnum; i < reload_n_operands; i++)
5308 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5309 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5314 case RELOAD_FOR_INSN:
5315 for (i = 0; i < reload_n_operands; i++)
5316 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5317 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5320 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5321 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5323 case RELOAD_FOR_OTHER_ADDRESS:
5324 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5331 /* Return 1 if the value in reload reg REGNO, as used by a reload
5332 needed for the part of the insn specified by OPNUM and TYPE,
5333 is still available in REGNO at the end of the insn.
5335 We can assume that the reload reg was already tested for availability
5336 at the time it is needed, and we should not check this again,
5337 in case the reg has already been marked in use. */
5340 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
5347 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5348 its value must reach the end. */
5351 /* If this use is for part of the insn,
5352 its value reaches if no subsequent part uses the same register.
5353 Just like the above function, don't try to do this with lots
5356 case RELOAD_FOR_OTHER_ADDRESS:
5357 /* Here we check for everything else, since these don't conflict
5358 with anything else and everything comes later. */
5360 for (i = 0; i < reload_n_operands; i++)
5361 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5362 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5363 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5364 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5365 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5366 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5369 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5370 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5371 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5372 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5374 case RELOAD_FOR_INPUT_ADDRESS:
5375 case RELOAD_FOR_INPADDR_ADDRESS:
5376 /* Similar, except that we check only for this and subsequent inputs
5377 and the address of only subsequent inputs and we do not need
5378 to check for RELOAD_OTHER objects since they are known not to
5381 for (i = opnum; i < reload_n_operands; i++)
5382 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5385 for (i = opnum + 1; i < reload_n_operands; i++)
5386 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5387 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5390 for (i = 0; i < reload_n_operands; i++)
5391 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5392 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5393 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5396 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5399 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5400 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5401 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5403 case RELOAD_FOR_INPUT:
5404 /* Similar to input address, except we start at the next operand for
5405 both input and input address and we do not check for
5406 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5409 for (i = opnum + 1; i < reload_n_operands; i++)
5410 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5411 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5412 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5415 /* ... fall through ... */
5417 case RELOAD_FOR_OPERAND_ADDRESS:
5418 /* Check outputs and their addresses. */
5420 for (i = 0; i < reload_n_operands; i++)
5421 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5422 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5423 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5426 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5428 case RELOAD_FOR_OPADDR_ADDR:
5429 for (i = 0; i < reload_n_operands; i++)
5430 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5431 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5432 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5435 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5436 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5437 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5439 case RELOAD_FOR_INSN:
5440 /* These conflict with other outputs with RELOAD_OTHER. So
5441 we need only check for output addresses. */
5443 opnum = reload_n_operands;
5445 /* ... fall through ... */
5447 case RELOAD_FOR_OUTPUT:
5448 case RELOAD_FOR_OUTPUT_ADDRESS:
5449 case RELOAD_FOR_OUTADDR_ADDRESS:
5450 /* We already know these can't conflict with a later output. So the
5451 only thing to check are later output addresses.
5452 Note that multiple output operands are emitted in reverse order,
5453 so the conflicting ones are those with lower indices. */
5454 for (i = 0; i < opnum; i++)
5455 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5456 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5466 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5467 every register in the range [REGNO, REGNO + NREGS). */
5470 reload_regs_reach_end_p (unsigned int regno, int nregs,
5471 int opnum, enum reload_type type)
5475 for (i = 0; i < nregs; i++)
5476 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5482 /* Returns whether R1 and R2 are uniquely chained: the value of one
5483 is used by the other, and that value is not used by any other
5484 reload for this insn. This is used to partially undo the decision
5485 made in find_reloads when in the case of multiple
5486 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5487 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5488 reloads. This code tries to avoid the conflict created by that
5489 change. It might be cleaner to explicitly keep track of which
5490 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5491 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5492 this after the fact. */
5494 reloads_unique_chain_p (int r1, int r2)
5498 /* We only check input reloads. */
5499 if (! rld[r1].in || ! rld[r2].in)
5502 /* Avoid anything with output reloads. */
5503 if (rld[r1].out || rld[r2].out)
5506 /* "chained" means one reload is a component of the other reload,
5507 not the same as the other reload. */
5508 if (rld[r1].opnum != rld[r2].opnum
5509 || rtx_equal_p (rld[r1].in, rld[r2].in)
5510 || rld[r1].optional || rld[r2].optional
5511 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5512 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5515 for (i = 0; i < n_reloads; i ++)
5516 /* Look for input reloads that aren't our two */
5517 if (i != r1 && i != r2 && rld[i].in)
5519 /* If our reload is mentioned at all, it isn't a simple chain. */
5520 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5526 /* The recursive function change all occurrences of WHAT in *WHERE
5529 substitute (rtx *where, const_rtx what, rtx repl)
5538 if (*where == what || rtx_equal_p (*where, what))
5540 /* Record the location of the changed rtx. */
5541 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5546 code = GET_CODE (*where);
5547 fmt = GET_RTX_FORMAT (code);
5548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5554 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5555 substitute (&XVECEXP (*where, i, j), what, repl);
5557 else if (fmt[i] == 'e')
5558 substitute (&XEXP (*where, i), what, repl);
5562 /* The function returns TRUE if chain of reload R1 and R2 (in any
5563 order) can be evaluated without usage of intermediate register for
5564 the reload containing another reload. It is important to see
5565 gen_reload to understand what the function is trying to do. As an
5566 example, let us have reload chain
5569 r1: <something> + const
5571 and reload R2 got reload reg HR. The function returns true if
5572 there is a correct insn HR = HR + <something>. Otherwise,
5573 gen_reload will use intermediate register (and this is the reload
5574 reg for R1) to reload <something>.
5576 We need this function to find a conflict for chain reloads. In our
5577 example, if HR = HR + <something> is incorrect insn, then we cannot
5578 use HR as a reload register for R2. If we do use it then we get a
5587 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5589 /* Assume other cases in gen_reload are not possible for
5590 chain reloads or do need an intermediate hard registers. */
5594 rtx last = get_last_insn ();
5596 /* Make r2 a component of r1. */
5597 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5603 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5604 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5605 gcc_assert (regno >= 0);
5606 out = gen_rtx_REG (rld[r1].mode, regno);
5608 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5610 /* If IN is a paradoxical SUBREG, remove it and try to put the
5611 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5612 strip_paradoxical_subreg (&in, &out);
5614 if (GET_CODE (in) == PLUS
5615 && (REG_P (XEXP (in, 0))
5616 || GET_CODE (XEXP (in, 0)) == SUBREG
5617 || MEM_P (XEXP (in, 0)))
5618 && (REG_P (XEXP (in, 1))
5619 || GET_CODE (XEXP (in, 1)) == SUBREG
5620 || CONSTANT_P (XEXP (in, 1))
5621 || MEM_P (XEXP (in, 1))))
5623 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5624 code = recog_memoized (insn);
5629 extract_insn (insn);
5630 /* We want constrain operands to treat this insn strictly in
5631 its validity determination, i.e., the way it would after
5632 reload has completed. */
5633 result = constrain_operands (1);
5636 delete_insns_since (last);
5639 /* Restore the original value at each changed address within R1. */
5640 while (!VEC_empty (rtx_p, substitute_stack))
5642 rtx *where = VEC_pop (rtx_p, substitute_stack);
5643 *where = rld[r2].in;
5649 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5652 This function uses the same algorithm as reload_reg_free_p above. */
5655 reloads_conflict (int r1, int r2)
5657 enum reload_type r1_type = rld[r1].when_needed;
5658 enum reload_type r2_type = rld[r2].when_needed;
5659 int r1_opnum = rld[r1].opnum;
5660 int r2_opnum = rld[r2].opnum;
5662 /* RELOAD_OTHER conflicts with everything. */
5663 if (r2_type == RELOAD_OTHER)
5666 /* Otherwise, check conflicts differently for each type. */
5670 case RELOAD_FOR_INPUT:
5671 return (r2_type == RELOAD_FOR_INSN
5672 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5673 || r2_type == RELOAD_FOR_OPADDR_ADDR
5674 || r2_type == RELOAD_FOR_INPUT
5675 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5676 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5677 && r2_opnum > r1_opnum));
5679 case RELOAD_FOR_INPUT_ADDRESS:
5680 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5681 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5683 case RELOAD_FOR_INPADDR_ADDRESS:
5684 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5685 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5687 case RELOAD_FOR_OUTPUT_ADDRESS:
5688 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5689 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5691 case RELOAD_FOR_OUTADDR_ADDRESS:
5692 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5693 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5695 case RELOAD_FOR_OPERAND_ADDRESS:
5696 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5697 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5698 && (!reloads_unique_chain_p (r1, r2)
5699 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5701 case RELOAD_FOR_OPADDR_ADDR:
5702 return (r2_type == RELOAD_FOR_INPUT
5703 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5705 case RELOAD_FOR_OUTPUT:
5706 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5707 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5708 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5709 && r2_opnum >= r1_opnum));
5711 case RELOAD_FOR_INSN:
5712 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5713 || r2_type == RELOAD_FOR_INSN
5714 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5716 case RELOAD_FOR_OTHER_ADDRESS:
5717 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5727 /* Indexed by reload number, 1 if incoming value
5728 inherited from previous insns. */
5729 static char reload_inherited[MAX_RELOADS];
5731 /* For an inherited reload, this is the insn the reload was inherited from,
5732 if we know it. Otherwise, this is 0. */
5733 static rtx reload_inheritance_insn[MAX_RELOADS];
5735 /* If nonzero, this is a place to get the value of the reload,
5736 rather than using reload_in. */
5737 static rtx reload_override_in[MAX_RELOADS];
5739 /* For each reload, the hard register number of the register used,
5740 or -1 if we did not need a register for this reload. */
5741 static int reload_spill_index[MAX_RELOADS];
5743 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5744 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5746 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5747 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5749 /* Subroutine of free_for_value_p, used to check a single register.
5750 START_REGNO is the starting regno of the full reload register
5751 (possibly comprising multiple hard registers) that we are considering. */
5754 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5755 enum reload_type type, rtx value, rtx out,
5756 int reloadnum, int ignore_address_reloads)
5759 /* Set if we see an input reload that must not share its reload register
5760 with any new earlyclobber, but might otherwise share the reload
5761 register with an output or input-output reload. */
5762 int check_earlyclobber = 0;
5766 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5769 if (out == const0_rtx)
5775 /* We use some pseudo 'time' value to check if the lifetimes of the
5776 new register use would overlap with the one of a previous reload
5777 that is not read-only or uses a different value.
5778 The 'time' used doesn't have to be linear in any shape or form, just
5780 Some reload types use different 'buckets' for each operand.
5781 So there are MAX_RECOG_OPERANDS different time values for each
5783 We compute TIME1 as the time when the register for the prospective
5784 new reload ceases to be live, and TIME2 for each existing
5785 reload as the time when that the reload register of that reload
5787 Where there is little to be gained by exact lifetime calculations,
5788 we just make conservative assumptions, i.e. a longer lifetime;
5789 this is done in the 'default:' cases. */
5792 case RELOAD_FOR_OTHER_ADDRESS:
5793 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5794 time1 = copy ? 0 : 1;
5797 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5799 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5800 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5801 respectively, to the time values for these, we get distinct time
5802 values. To get distinct time values for each operand, we have to
5803 multiply opnum by at least three. We round that up to four because
5804 multiply by four is often cheaper. */
5805 case RELOAD_FOR_INPADDR_ADDRESS:
5806 time1 = opnum * 4 + 2;
5808 case RELOAD_FOR_INPUT_ADDRESS:
5809 time1 = opnum * 4 + 3;
5811 case RELOAD_FOR_INPUT:
5812 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5813 executes (inclusive). */
5814 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5816 case RELOAD_FOR_OPADDR_ADDR:
5818 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5819 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5821 case RELOAD_FOR_OPERAND_ADDRESS:
5822 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5824 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5826 case RELOAD_FOR_OUTADDR_ADDRESS:
5827 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5829 case RELOAD_FOR_OUTPUT_ADDRESS:
5830 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5833 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5836 for (i = 0; i < n_reloads; i++)
5838 rtx reg = rld[i].reg_rtx;
5839 if (reg && REG_P (reg)
5840 && ((unsigned) regno - true_regnum (reg)
5841 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5844 rtx other_input = rld[i].in;
5846 /* If the other reload loads the same input value, that
5847 will not cause a conflict only if it's loading it into
5848 the same register. */
5849 if (true_regnum (reg) != start_regno)
5850 other_input = NULL_RTX;
5851 if (! other_input || ! rtx_equal_p (other_input, value)
5852 || rld[i].out || out)
5855 switch (rld[i].when_needed)
5857 case RELOAD_FOR_OTHER_ADDRESS:
5860 case RELOAD_FOR_INPADDR_ADDRESS:
5861 /* find_reloads makes sure that a
5862 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5863 by at most one - the first -
5864 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5865 address reload is inherited, the address address reload
5866 goes away, so we can ignore this conflict. */
5867 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5868 && ignore_address_reloads
5869 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5870 Then the address address is still needed to store
5871 back the new address. */
5872 && ! rld[reloadnum].out)
5874 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5875 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5877 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5878 && ignore_address_reloads
5879 /* Unless we are reloading an auto_inc expression. */
5880 && ! rld[reloadnum].out)
5882 time2 = rld[i].opnum * 4 + 2;
5884 case RELOAD_FOR_INPUT_ADDRESS:
5885 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5886 && ignore_address_reloads
5887 && ! rld[reloadnum].out)
5889 time2 = rld[i].opnum * 4 + 3;
5891 case RELOAD_FOR_INPUT:
5892 time2 = rld[i].opnum * 4 + 4;
5893 check_earlyclobber = 1;
5895 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5896 == MAX_RECOG_OPERAND * 4 */
5897 case RELOAD_FOR_OPADDR_ADDR:
5898 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5899 && ignore_address_reloads
5900 && ! rld[reloadnum].out)
5902 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5904 case RELOAD_FOR_OPERAND_ADDRESS:
5905 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5906 check_earlyclobber = 1;
5908 case RELOAD_FOR_INSN:
5909 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5911 case RELOAD_FOR_OUTPUT:
5912 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5913 instruction is executed. */
5914 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5916 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5917 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5919 case RELOAD_FOR_OUTADDR_ADDRESS:
5920 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5921 && ignore_address_reloads
5922 && ! rld[reloadnum].out)
5924 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5926 case RELOAD_FOR_OUTPUT_ADDRESS:
5927 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5930 /* If there is no conflict in the input part, handle this
5931 like an output reload. */
5932 if (! rld[i].in || rtx_equal_p (other_input, value))
5934 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5935 /* Earlyclobbered outputs must conflict with inputs. */
5936 if (earlyclobber_operand_p (rld[i].out))
5937 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5942 /* RELOAD_OTHER might be live beyond instruction execution,
5943 but this is not obvious when we set time2 = 1. So check
5944 here if there might be a problem with the new reload
5945 clobbering the register used by the RELOAD_OTHER. */
5953 && (! rld[i].in || rld[i].out
5954 || ! rtx_equal_p (other_input, value)))
5955 || (out && rld[reloadnum].out_reg
5956 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5962 /* Earlyclobbered outputs must conflict with inputs. */
5963 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5969 /* Return 1 if the value in reload reg REGNO, as used by a reload
5970 needed for the part of the insn specified by OPNUM and TYPE,
5971 may be used to load VALUE into it.
5973 MODE is the mode in which the register is used, this is needed to
5974 determine how many hard regs to test.
5976 Other read-only reloads with the same value do not conflict
5977 unless OUT is nonzero and these other reloads have to live while
5978 output reloads live.
5979 If OUT is CONST0_RTX, this is a special case: it means that the
5980 test should not be for using register REGNO as reload register, but
5981 for copying from register REGNO into the reload register.
5983 RELOADNUM is the number of the reload we want to load this value for;
5984 a reload does not conflict with itself.
5986 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5987 reloads that load an address for the very reload we are considering.
5989 The caller has to make sure that there is no conflict with the return
5993 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5994 enum reload_type type, rtx value, rtx out, int reloadnum,
5995 int ignore_address_reloads)
5997 int nregs = hard_regno_nregs[regno][mode];
5999 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6000 value, out, reloadnum,
6001 ignore_address_reloads))
6006 /* Return nonzero if the rtx X is invariant over the current function. */
6007 /* ??? Actually, the places where we use this expect exactly what is
6008 tested here, and not everything that is function invariant. In
6009 particular, the frame pointer and arg pointer are special cased;
6010 pic_offset_table_rtx is not, and we must not spill these things to
6014 function_invariant_p (const_rtx x)
6018 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6020 if (GET_CODE (x) == PLUS
6021 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6022 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6027 /* Determine whether the reload reg X overlaps any rtx'es used for
6028 overriding inheritance. Return nonzero if so. */
6031 conflicts_with_override (rtx x)
6034 for (i = 0; i < n_reloads; i++)
6035 if (reload_override_in[i]
6036 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6041 /* Give an error message saying we failed to find a reload for INSN,
6042 and clear out reload R. */
6044 failed_reload (rtx insn, int r)
6046 if (asm_noperands (PATTERN (insn)) < 0)
6047 /* It's the compiler's fault. */
6048 fatal_insn ("could not find a spill register", insn);
6050 /* It's the user's fault; the operand's mode and constraint
6051 don't match. Disable this reload so we don't crash in final. */
6052 error_for_asm (insn,
6053 "%<asm%> operand constraint incompatible with operand size");
6057 rld[r].optional = 1;
6058 rld[r].secondary_p = 1;
6061 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6062 for reload R. If it's valid, get an rtx for it. Return nonzero if
6065 set_reload_reg (int i, int r)
6067 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6069 int regno ATTRIBUTE_UNUSED;
6070 rtx reg = spill_reg_rtx[i];
6072 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6073 spill_reg_rtx[i] = reg
6074 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6076 regno = true_regnum (reg);
6078 /* Detect when the reload reg can't hold the reload mode.
6079 This used to be one `if', but Sequent compiler can't handle that. */
6080 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6082 enum machine_mode test_mode = VOIDmode;
6084 test_mode = GET_MODE (rld[r].in);
6085 /* If rld[r].in has VOIDmode, it means we will load it
6086 in whatever mode the reload reg has: to wit, rld[r].mode.
6087 We have already tested that for validity. */
6088 /* Aside from that, we need to test that the expressions
6089 to reload from or into have modes which are valid for this
6090 reload register. Otherwise the reload insns would be invalid. */
6091 if (! (rld[r].in != 0 && test_mode != VOIDmode
6092 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6093 if (! (rld[r].out != 0
6094 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6096 /* The reg is OK. */
6099 /* Mark as in use for this insn the reload regs we use
6101 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6102 rld[r].when_needed, rld[r].mode);
6104 rld[r].reg_rtx = reg;
6105 reload_spill_index[r] = spill_regs[i];
6112 /* Find a spill register to use as a reload register for reload R.
6113 LAST_RELOAD is nonzero if this is the last reload for the insn being
6116 Set rld[R].reg_rtx to the register allocated.
6118 We return 1 if successful, or 0 if we couldn't find a spill reg and
6119 we didn't change anything. */
6122 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6127 /* If we put this reload ahead, thinking it is a group,
6128 then insist on finding a group. Otherwise we can grab a
6129 reg that some other reload needs.
6130 (That can happen when we have a 68000 DATA_OR_FP_REG
6131 which is a group of data regs or one fp reg.)
6132 We need not be so restrictive if there are no more reloads
6135 ??? Really it would be nicer to have smarter handling
6136 for that kind of reg class, where a problem like this is normal.
6137 Perhaps those classes should be avoided for reloading
6138 by use of more alternatives. */
6140 int force_group = rld[r].nregs > 1 && ! last_reload;
6142 /* If we want a single register and haven't yet found one,
6143 take any reg in the right class and not in use.
6144 If we want a consecutive group, here is where we look for it.
6146 We use three passes so we can first look for reload regs to
6147 reuse, which are already in use for other reloads in this insn,
6148 and only then use additional registers which are not "bad", then
6149 finally any register.
6151 I think that maximizing reuse is needed to make sure we don't
6152 run out of reload regs. Suppose we have three reloads, and
6153 reloads A and B can share regs. These need two regs.
6154 Suppose A and B are given different regs.
6155 That leaves none for C. */
6156 for (pass = 0; pass < 3; pass++)
6158 /* I is the index in spill_regs.
6159 We advance it round-robin between insns to use all spill regs
6160 equally, so that inherited reloads have a chance
6161 of leapfrogging each other. */
6165 for (count = 0; count < n_spills; count++)
6167 int rclass = (int) rld[r].rclass;
6173 regnum = spill_regs[i];
6175 if ((reload_reg_free_p (regnum, rld[r].opnum,
6178 /* We check reload_reg_used to make sure we
6179 don't clobber the return register. */
6180 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6181 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6182 rld[r].when_needed, rld[r].in,
6184 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6185 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6186 /* Look first for regs to share, then for unshared. But
6187 don't share regs used for inherited reloads; they are
6188 the ones we want to preserve. */
6190 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6192 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6195 int nr = hard_regno_nregs[regnum][rld[r].mode];
6197 /* During the second pass we want to avoid reload registers
6198 which are "bad" for this reload. */
6200 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6203 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6204 (on 68000) got us two FP regs. If NR is 1,
6205 we would reject both of them. */
6208 /* If we need only one reg, we have already won. */
6211 /* But reject a single reg if we demand a group. */
6216 /* Otherwise check that as many consecutive regs as we need
6217 are available here. */
6220 int regno = regnum + nr - 1;
6221 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6222 && spill_reg_order[regno] >= 0
6223 && reload_reg_free_p (regno, rld[r].opnum,
6224 rld[r].when_needed)))
6233 /* If we found something on the current pass, omit later passes. */
6234 if (count < n_spills)
6238 /* We should have found a spill register by now. */
6239 if (count >= n_spills)
6242 /* I is the index in SPILL_REG_RTX of the reload register we are to
6243 allocate. Get an rtx for it and find its register number. */
6245 return set_reload_reg (i, r);
6248 /* Initialize all the tables needed to allocate reload registers.
6249 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6250 is the array we use to restore the reg_rtx field for every reload. */
6253 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6257 for (i = 0; i < n_reloads; i++)
6258 rld[i].reg_rtx = save_reload_reg_rtx[i];
6260 memset (reload_inherited, 0, MAX_RELOADS);
6261 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6262 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6264 CLEAR_HARD_REG_SET (reload_reg_used);
6265 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6266 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6267 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6268 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6269 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6271 CLEAR_HARD_REG_SET (reg_used_in_insn);
6274 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6275 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6276 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6277 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6278 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6279 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6282 for (i = 0; i < reload_n_operands; i++)
6284 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6285 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6286 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6287 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6288 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6289 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6292 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6294 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6296 for (i = 0; i < n_reloads; i++)
6297 /* If we have already decided to use a certain register,
6298 don't use it in another way. */
6300 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6301 rld[i].when_needed, rld[i].mode);
6304 /* Assign hard reg targets for the pseudo-registers we must reload
6305 into hard regs for this insn.
6306 Also output the instructions to copy them in and out of the hard regs.
6308 For machines with register classes, we are responsible for
6309 finding a reload reg in the proper class. */
6312 choose_reload_regs (struct insn_chain *chain)
6314 rtx insn = chain->insn;
6316 unsigned int max_group_size = 1;
6317 enum reg_class group_class = NO_REGS;
6318 int pass, win, inheritance;
6320 rtx save_reload_reg_rtx[MAX_RELOADS];
6322 /* In order to be certain of getting the registers we need,
6323 we must sort the reloads into order of increasing register class.
6324 Then our grabbing of reload registers will parallel the process
6325 that provided the reload registers.
6327 Also note whether any of the reloads wants a consecutive group of regs.
6328 If so, record the maximum size of the group desired and what
6329 register class contains all the groups needed by this insn. */
6331 for (j = 0; j < n_reloads; j++)
6333 reload_order[j] = j;
6334 if (rld[j].reg_rtx != NULL_RTX)
6336 gcc_assert (REG_P (rld[j].reg_rtx)
6337 && HARD_REGISTER_P (rld[j].reg_rtx));
6338 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6341 reload_spill_index[j] = -1;
6343 if (rld[j].nregs > 1)
6345 max_group_size = MAX (rld[j].nregs, max_group_size);
6347 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6350 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6354 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6356 /* If -O, try first with inheritance, then turning it off.
6357 If not -O, don't do inheritance.
6358 Using inheritance when not optimizing leads to paradoxes
6359 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6360 because one side of the comparison might be inherited. */
6362 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6364 choose_reload_regs_init (chain, save_reload_reg_rtx);
6366 /* Process the reloads in order of preference just found.
6367 Beyond this point, subregs can be found in reload_reg_rtx.
6369 This used to look for an existing reloaded home for all of the
6370 reloads, and only then perform any new reloads. But that could lose
6371 if the reloads were done out of reg-class order because a later
6372 reload with a looser constraint might have an old home in a register
6373 needed by an earlier reload with a tighter constraint.
6375 To solve this, we make two passes over the reloads, in the order
6376 described above. In the first pass we try to inherit a reload
6377 from a previous insn. If there is a later reload that needs a
6378 class that is a proper subset of the class being processed, we must
6379 also allocate a spill register during the first pass.
6381 Then make a second pass over the reloads to allocate any reloads
6382 that haven't been given registers yet. */
6384 for (j = 0; j < n_reloads; j++)
6386 int r = reload_order[j];
6387 rtx search_equiv = NULL_RTX;
6389 /* Ignore reloads that got marked inoperative. */
6390 if (rld[r].out == 0 && rld[r].in == 0
6391 && ! rld[r].secondary_p)
6394 /* If find_reloads chose to use reload_in or reload_out as a reload
6395 register, we don't need to chose one. Otherwise, try even if it
6396 found one since we might save an insn if we find the value lying
6398 Try also when reload_in is a pseudo without a hard reg. */
6399 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6400 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6401 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6402 && !MEM_P (rld[r].in)
6403 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6406 #if 0 /* No longer needed for correct operation.
6407 It might give better code, or might not; worth an experiment? */
6408 /* If this is an optional reload, we can't inherit from earlier insns
6409 until we are sure that any non-optional reloads have been allocated.
6410 The following code takes advantage of the fact that optional reloads
6411 are at the end of reload_order. */
6412 if (rld[r].optional != 0)
6413 for (i = 0; i < j; i++)
6414 if ((rld[reload_order[i]].out != 0
6415 || rld[reload_order[i]].in != 0
6416 || rld[reload_order[i]].secondary_p)
6417 && ! rld[reload_order[i]].optional
6418 && rld[reload_order[i]].reg_rtx == 0)
6419 allocate_reload_reg (chain, reload_order[i], 0);
6422 /* First see if this pseudo is already available as reloaded
6423 for a previous insn. We cannot try to inherit for reloads
6424 that are smaller than the maximum number of registers needed
6425 for groups unless the register we would allocate cannot be used
6428 We could check here to see if this is a secondary reload for
6429 an object that is already in a register of the desired class.
6430 This would avoid the need for the secondary reload register.
6431 But this is complex because we can't easily determine what
6432 objects might want to be loaded via this reload. So let a
6433 register be allocated here. In `emit_reload_insns' we suppress
6434 one of the loads in the case described above. */
6440 enum machine_mode mode = VOIDmode;
6444 else if (REG_P (rld[r].in))
6446 regno = REGNO (rld[r].in);
6447 mode = GET_MODE (rld[r].in);
6449 else if (REG_P (rld[r].in_reg))
6451 regno = REGNO (rld[r].in_reg);
6452 mode = GET_MODE (rld[r].in_reg);
6454 else if (GET_CODE (rld[r].in_reg) == SUBREG
6455 && REG_P (SUBREG_REG (rld[r].in_reg)))
6457 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6458 if (regno < FIRST_PSEUDO_REGISTER)
6459 regno = subreg_regno (rld[r].in_reg);
6461 byte = SUBREG_BYTE (rld[r].in_reg);
6462 mode = GET_MODE (rld[r].in_reg);
6465 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6466 && REG_P (XEXP (rld[r].in_reg, 0)))
6468 regno = REGNO (XEXP (rld[r].in_reg, 0));
6469 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6470 rld[r].out = rld[r].in;
6474 /* This won't work, since REGNO can be a pseudo reg number.
6475 Also, it takes much more hair to keep track of all the things
6476 that can invalidate an inherited reload of part of a pseudoreg. */
6477 else if (GET_CODE (rld[r].in) == SUBREG
6478 && REG_P (SUBREG_REG (rld[r].in)))
6479 regno = subreg_regno (rld[r].in);
6483 && reg_last_reload_reg[regno] != 0
6484 #ifdef CANNOT_CHANGE_MODE_CLASS
6485 /* Verify that the register it's in can be used in
6487 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6488 GET_MODE (reg_last_reload_reg[regno]),
6493 enum reg_class rclass = rld[r].rclass, last_class;
6494 rtx last_reg = reg_last_reload_reg[regno];
6495 enum machine_mode need_mode;
6497 i = REGNO (last_reg);
6498 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6499 last_class = REGNO_REG_CLASS (i);
6505 = smallest_mode_for_size
6506 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6507 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6508 ? MODE_INT : GET_MODE_CLASS (mode));
6510 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6511 >= GET_MODE_SIZE (need_mode))
6512 && reg_reloaded_contents[i] == regno
6513 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6514 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6515 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6516 /* Even if we can't use this register as a reload
6517 register, we might use it for reload_override_in,
6518 if copying it to the desired class is cheap
6520 || ((register_move_cost (mode, last_class, rclass)
6521 < memory_move_cost (mode, rclass, true))
6522 && (secondary_reload_class (1, rclass, mode,
6525 #ifdef SECONDARY_MEMORY_NEEDED
6526 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6531 && (rld[r].nregs == max_group_size
6532 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6534 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6535 rld[r].when_needed, rld[r].in,
6538 /* If a group is needed, verify that all the subsequent
6539 registers still have their values intact. */
6540 int nr = hard_regno_nregs[i][rld[r].mode];
6543 for (k = 1; k < nr; k++)
6544 if (reg_reloaded_contents[i + k] != regno
6545 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6553 last_reg = (GET_MODE (last_reg) == mode
6554 ? last_reg : gen_rtx_REG (mode, i));
6557 for (k = 0; k < nr; k++)
6558 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6561 /* We found a register that contains the
6562 value we need. If this register is the
6563 same as an `earlyclobber' operand of the
6564 current insn, just mark it as a place to
6565 reload from since we can't use it as the
6566 reload register itself. */
6568 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6569 if (reg_overlap_mentioned_for_reload_p
6570 (reg_last_reload_reg[regno],
6571 reload_earlyclobbers[i1]))
6574 if (i1 != n_earlyclobbers
6575 || ! (free_for_value_p (i, rld[r].mode,
6577 rld[r].when_needed, rld[r].in,
6579 /* Don't use it if we'd clobber a pseudo reg. */
6580 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6582 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6583 /* Don't clobber the frame pointer. */
6584 || (i == HARD_FRAME_POINTER_REGNUM
6585 && frame_pointer_needed
6587 /* Don't really use the inherited spill reg
6588 if we need it wider than we've got it. */
6589 || (GET_MODE_SIZE (rld[r].mode)
6590 > GET_MODE_SIZE (mode))
6593 /* If find_reloads chose reload_out as reload
6594 register, stay with it - that leaves the
6595 inherited register for subsequent reloads. */
6596 || (rld[r].out && rld[r].reg_rtx
6597 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6599 if (! rld[r].optional)
6601 reload_override_in[r] = last_reg;
6602 reload_inheritance_insn[r]
6603 = reg_reloaded_insn[i];
6609 /* We can use this as a reload reg. */
6610 /* Mark the register as in use for this part of
6612 mark_reload_reg_in_use (i,
6616 rld[r].reg_rtx = last_reg;
6617 reload_inherited[r] = 1;
6618 reload_inheritance_insn[r]
6619 = reg_reloaded_insn[i];
6620 reload_spill_index[r] = i;
6621 for (k = 0; k < nr; k++)
6622 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6630 /* Here's another way to see if the value is already lying around. */
6633 && ! reload_inherited[r]
6635 && (CONSTANT_P (rld[r].in)
6636 || GET_CODE (rld[r].in) == PLUS
6637 || REG_P (rld[r].in)
6638 || MEM_P (rld[r].in))
6639 && (rld[r].nregs == max_group_size
6640 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6641 search_equiv = rld[r].in;
6646 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6647 -1, NULL, 0, rld[r].mode);
6653 regno = REGNO (equiv);
6656 /* This must be a SUBREG of a hard register.
6657 Make a new REG since this might be used in an
6658 address and not all machines support SUBREGs
6660 gcc_assert (GET_CODE (equiv) == SUBREG);
6661 regno = subreg_regno (equiv);
6662 equiv = gen_rtx_REG (rld[r].mode, regno);
6663 /* If we choose EQUIV as the reload register, but the
6664 loop below decides to cancel the inheritance, we'll
6665 end up reloading EQUIV in rld[r].mode, not the mode
6666 it had originally. That isn't safe when EQUIV isn't
6667 available as a spill register since its value might
6668 still be live at this point. */
6669 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6670 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6675 /* If we found a spill reg, reject it unless it is free
6676 and of the desired class. */
6680 int bad_for_class = 0;
6681 int max_regno = regno + rld[r].nregs;
6683 for (i = regno; i < max_regno; i++)
6685 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6687 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6692 && ! free_for_value_p (regno, rld[r].mode,
6693 rld[r].opnum, rld[r].when_needed,
6694 rld[r].in, rld[r].out, r, 1))
6699 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6702 /* We found a register that contains the value we need.
6703 If this register is the same as an `earlyclobber' operand
6704 of the current insn, just mark it as a place to reload from
6705 since we can't use it as the reload register itself. */
6708 for (i = 0; i < n_earlyclobbers; i++)
6709 if (reg_overlap_mentioned_for_reload_p (equiv,
6710 reload_earlyclobbers[i]))
6712 if (! rld[r].optional)
6713 reload_override_in[r] = equiv;
6718 /* If the equiv register we have found is explicitly clobbered
6719 in the current insn, it depends on the reload type if we
6720 can use it, use it for reload_override_in, or not at all.
6721 In particular, we then can't use EQUIV for a
6722 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6726 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6727 switch (rld[r].when_needed)
6729 case RELOAD_FOR_OTHER_ADDRESS:
6730 case RELOAD_FOR_INPADDR_ADDRESS:
6731 case RELOAD_FOR_INPUT_ADDRESS:
6732 case RELOAD_FOR_OPADDR_ADDR:
6735 case RELOAD_FOR_INPUT:
6736 case RELOAD_FOR_OPERAND_ADDRESS:
6737 if (! rld[r].optional)
6738 reload_override_in[r] = equiv;
6744 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6745 switch (rld[r].when_needed)
6747 case RELOAD_FOR_OTHER_ADDRESS:
6748 case RELOAD_FOR_INPADDR_ADDRESS:
6749 case RELOAD_FOR_INPUT_ADDRESS:
6750 case RELOAD_FOR_OPADDR_ADDR:
6751 case RELOAD_FOR_OPERAND_ADDRESS:
6752 case RELOAD_FOR_INPUT:
6755 if (! rld[r].optional)
6756 reload_override_in[r] = equiv;
6764 /* If we found an equivalent reg, say no code need be generated
6765 to load it, and use it as our reload reg. */
6767 && (regno != HARD_FRAME_POINTER_REGNUM
6768 || !frame_pointer_needed))
6770 int nr = hard_regno_nregs[regno][rld[r].mode];
6772 rld[r].reg_rtx = equiv;
6773 reload_spill_index[r] = regno;
6774 reload_inherited[r] = 1;
6776 /* If reg_reloaded_valid is not set for this register,
6777 there might be a stale spill_reg_store lying around.
6778 We must clear it, since otherwise emit_reload_insns
6779 might delete the store. */
6780 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6781 spill_reg_store[regno] = NULL_RTX;
6782 /* If any of the hard registers in EQUIV are spill
6783 registers, mark them as in use for this insn. */
6784 for (k = 0; k < nr; k++)
6786 i = spill_reg_order[regno + k];
6789 mark_reload_reg_in_use (regno, rld[r].opnum,
6792 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6799 /* If we found a register to use already, or if this is an optional
6800 reload, we are done. */
6801 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6805 /* No longer needed for correct operation. Might or might
6806 not give better code on the average. Want to experiment? */
6808 /* See if there is a later reload that has a class different from our
6809 class that intersects our class or that requires less register
6810 than our reload. If so, we must allocate a register to this
6811 reload now, since that reload might inherit a previous reload
6812 and take the only available register in our class. Don't do this
6813 for optional reloads since they will force all previous reloads
6814 to be allocated. Also don't do this for reloads that have been
6817 for (i = j + 1; i < n_reloads; i++)
6819 int s = reload_order[i];
6821 if ((rld[s].in == 0 && rld[s].out == 0
6822 && ! rld[s].secondary_p)
6826 if ((rld[s].rclass != rld[r].rclass
6827 && reg_classes_intersect_p (rld[r].rclass,
6829 || rld[s].nregs < rld[r].nregs)
6836 allocate_reload_reg (chain, r, j == n_reloads - 1);
6840 /* Now allocate reload registers for anything non-optional that
6841 didn't get one yet. */
6842 for (j = 0; j < n_reloads; j++)
6844 int r = reload_order[j];
6846 /* Ignore reloads that got marked inoperative. */
6847 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6850 /* Skip reloads that already have a register allocated or are
6852 if (rld[r].reg_rtx != 0 || rld[r].optional)
6855 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6859 /* If that loop got all the way, we have won. */
6866 /* Loop around and try without any inheritance. */
6871 /* First undo everything done by the failed attempt
6872 to allocate with inheritance. */
6873 choose_reload_regs_init (chain, save_reload_reg_rtx);
6875 /* Some sanity tests to verify that the reloads found in the first
6876 pass are identical to the ones we have now. */
6877 gcc_assert (chain->n_reloads == n_reloads);
6879 for (i = 0; i < n_reloads; i++)
6881 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6883 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6884 for (j = 0; j < n_spills; j++)
6885 if (spill_regs[j] == chain->rld[i].regno)
6886 if (! set_reload_reg (j, i))
6887 failed_reload (chain->insn, i);
6891 /* If we thought we could inherit a reload, because it seemed that
6892 nothing else wanted the same reload register earlier in the insn,
6893 verify that assumption, now that all reloads have been assigned.
6894 Likewise for reloads where reload_override_in has been set. */
6896 /* If doing expensive optimizations, do one preliminary pass that doesn't
6897 cancel any inheritance, but removes reloads that have been needed only
6898 for reloads that we know can be inherited. */
6899 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6901 for (j = 0; j < n_reloads; j++)
6903 int r = reload_order[j];
6905 if (reload_inherited[r] && rld[r].reg_rtx)
6906 check_reg = rld[r].reg_rtx;
6907 else if (reload_override_in[r]
6908 && (REG_P (reload_override_in[r])
6909 || GET_CODE (reload_override_in[r]) == SUBREG))
6910 check_reg = reload_override_in[r];
6913 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6914 rld[r].opnum, rld[r].when_needed, rld[r].in,
6915 (reload_inherited[r]
6916 ? rld[r].out : const0_rtx),
6921 reload_inherited[r] = 0;
6922 reload_override_in[r] = 0;
6924 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6925 reload_override_in, then we do not need its related
6926 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6927 likewise for other reload types.
6928 We handle this by removing a reload when its only replacement
6929 is mentioned in reload_in of the reload we are going to inherit.
6930 A special case are auto_inc expressions; even if the input is
6931 inherited, we still need the address for the output. We can
6932 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6933 If we succeeded removing some reload and we are doing a preliminary
6934 pass just to remove such reloads, make another pass, since the
6935 removal of one reload might allow us to inherit another one. */
6937 && rld[r].out != rld[r].in
6938 && remove_address_replacements (rld[r].in) && pass)
6943 /* Now that reload_override_in is known valid,
6944 actually override reload_in. */
6945 for (j = 0; j < n_reloads; j++)
6946 if (reload_override_in[j])
6947 rld[j].in = reload_override_in[j];
6949 /* If this reload won't be done because it has been canceled or is
6950 optional and not inherited, clear reload_reg_rtx so other
6951 routines (such as subst_reloads) don't get confused. */
6952 for (j = 0; j < n_reloads; j++)
6953 if (rld[j].reg_rtx != 0
6954 && ((rld[j].optional && ! reload_inherited[j])
6955 || (rld[j].in == 0 && rld[j].out == 0
6956 && ! rld[j].secondary_p)))
6958 int regno = true_regnum (rld[j].reg_rtx);
6960 if (spill_reg_order[regno] >= 0)
6961 clear_reload_reg_in_use (regno, rld[j].opnum,
6962 rld[j].when_needed, rld[j].mode);
6964 reload_spill_index[j] = -1;
6967 /* Record which pseudos and which spill regs have output reloads. */
6968 for (j = 0; j < n_reloads; j++)
6970 int r = reload_order[j];
6972 i = reload_spill_index[r];
6974 /* I is nonneg if this reload uses a register.
6975 If rld[r].reg_rtx is 0, this is an optional reload
6976 that we opted to ignore. */
6977 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6978 && rld[r].reg_rtx != 0)
6980 int nregno = REGNO (rld[r].out_reg);
6983 if (nregno < FIRST_PSEUDO_REGISTER)
6984 nr = hard_regno_nregs[nregno][rld[r].mode];
6987 SET_REGNO_REG_SET (®_has_output_reload,
6991 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
6993 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6994 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6995 || rld[r].when_needed == RELOAD_FOR_INSN);
7000 /* Deallocate the reload register for reload R. This is called from
7001 remove_address_replacements. */
7004 deallocate_reload_reg (int r)
7008 if (! rld[r].reg_rtx)
7010 regno = true_regnum (rld[r].reg_rtx);
7012 if (spill_reg_order[regno] >= 0)
7013 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7015 reload_spill_index[r] = -1;
7018 /* These arrays are filled by emit_reload_insns and its subroutines. */
7019 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7020 static rtx other_input_address_reload_insns = 0;
7021 static rtx other_input_reload_insns = 0;
7022 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7023 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7024 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7025 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7026 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7027 static rtx operand_reload_insns = 0;
7028 static rtx other_operand_reload_insns = 0;
7029 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7031 /* Values to be put in spill_reg_store are put here first. */
7032 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7033 static HARD_REG_SET reg_reloaded_died;
7035 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7036 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7037 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7038 adjusted register, and return true. Otherwise, return false. */
7040 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7041 enum reg_class new_class,
7042 enum machine_mode new_mode)
7047 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7049 unsigned regno = REGNO (reg);
7051 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7053 if (GET_MODE (reg) != new_mode)
7055 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7057 if (hard_regno_nregs[regno][new_mode]
7058 > hard_regno_nregs[regno][GET_MODE (reg)])
7060 reg = reload_adjust_reg_for_mode (reg, new_mode);
7068 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7069 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7070 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7071 adjusted register, and return true. Otherwise, return false. */
7073 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7074 enum insn_code icode)
7077 enum reg_class new_class = scratch_reload_class (icode);
7078 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7080 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7081 new_class, new_mode);
7084 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7085 has the number J. OLD contains the value to be used as input. */
7088 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7091 rtx insn = chain->insn;
7093 rtx oldequiv_reg = 0;
7096 enum machine_mode mode;
7099 /* delete_output_reload is only invoked properly if old contains
7100 the original pseudo register. Since this is replaced with a
7101 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7102 find the pseudo in RELOAD_IN_REG. */
7103 if (reload_override_in[j]
7104 && REG_P (rl->in_reg))
7111 else if (REG_P (oldequiv))
7112 oldequiv_reg = oldequiv;
7113 else if (GET_CODE (oldequiv) == SUBREG)
7114 oldequiv_reg = SUBREG_REG (oldequiv);
7116 reloadreg = reload_reg_rtx_for_input[j];
7117 mode = GET_MODE (reloadreg);
7119 /* If we are reloading from a register that was recently stored in
7120 with an output-reload, see if we can prove there was
7121 actually no need to store the old value in it. */
7123 if (optimize && REG_P (oldequiv)
7124 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7125 && spill_reg_store[REGNO (oldequiv)]
7127 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7128 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7130 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7132 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7135 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7136 oldequiv = SUBREG_REG (oldequiv);
7137 if (GET_MODE (oldequiv) != VOIDmode
7138 && mode != GET_MODE (oldequiv))
7139 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7141 /* Switch to the right place to emit the reload insns. */
7142 switch (rl->when_needed)
7145 where = &other_input_reload_insns;
7147 case RELOAD_FOR_INPUT:
7148 where = &input_reload_insns[rl->opnum];
7150 case RELOAD_FOR_INPUT_ADDRESS:
7151 where = &input_address_reload_insns[rl->opnum];
7153 case RELOAD_FOR_INPADDR_ADDRESS:
7154 where = &inpaddr_address_reload_insns[rl->opnum];
7156 case RELOAD_FOR_OUTPUT_ADDRESS:
7157 where = &output_address_reload_insns[rl->opnum];
7159 case RELOAD_FOR_OUTADDR_ADDRESS:
7160 where = &outaddr_address_reload_insns[rl->opnum];
7162 case RELOAD_FOR_OPERAND_ADDRESS:
7163 where = &operand_reload_insns;
7165 case RELOAD_FOR_OPADDR_ADDR:
7166 where = &other_operand_reload_insns;
7168 case RELOAD_FOR_OTHER_ADDRESS:
7169 where = &other_input_address_reload_insns;
7175 push_to_sequence (*where);
7177 /* Auto-increment addresses must be reloaded in a special way. */
7178 if (rl->out && ! rl->out_reg)
7180 /* We are not going to bother supporting the case where a
7181 incremented register can't be copied directly from
7182 OLDEQUIV since this seems highly unlikely. */
7183 gcc_assert (rl->secondary_in_reload < 0);
7185 if (reload_inherited[j])
7186 oldequiv = reloadreg;
7188 old = XEXP (rl->in_reg, 0);
7190 /* Prevent normal processing of this reload. */
7192 /* Output a special code sequence for this case, and forget about
7193 spill reg information. */
7194 new_spill_reg_store[REGNO (reloadreg)] = NULL;
7195 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7198 /* If we are reloading a pseudo-register that was set by the previous
7199 insn, see if we can get rid of that pseudo-register entirely
7200 by redirecting the previous insn into our reload register. */
7202 else if (optimize && REG_P (old)
7203 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7204 && dead_or_set_p (insn, old)
7205 /* This is unsafe if some other reload
7206 uses the same reg first. */
7207 && ! conflicts_with_override (reloadreg)
7208 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7209 rl->when_needed, old, rl->out, j, 0))
7211 rtx temp = PREV_INSN (insn);
7212 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7213 temp = PREV_INSN (temp);
7215 && NONJUMP_INSN_P (temp)
7216 && GET_CODE (PATTERN (temp)) == SET
7217 && SET_DEST (PATTERN (temp)) == old
7218 /* Make sure we can access insn_operand_constraint. */
7219 && asm_noperands (PATTERN (temp)) < 0
7220 /* This is unsafe if operand occurs more than once in current
7221 insn. Perhaps some occurrences aren't reloaded. */
7222 && count_occurrences (PATTERN (insn), old, 0) == 1)
7224 rtx old = SET_DEST (PATTERN (temp));
7225 /* Store into the reload register instead of the pseudo. */
7226 SET_DEST (PATTERN (temp)) = reloadreg;
7228 /* Verify that resulting insn is valid. */
7229 extract_insn (temp);
7230 if (constrain_operands (1))
7232 /* If the previous insn is an output reload, the source is
7233 a reload register, and its spill_reg_store entry will
7234 contain the previous destination. This is now
7236 if (REG_P (SET_SRC (PATTERN (temp)))
7237 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7239 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7240 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7243 /* If these are the only uses of the pseudo reg,
7244 pretend for GDB it lives in the reload reg we used. */
7245 if (REG_N_DEATHS (REGNO (old)) == 1
7246 && REG_N_SETS (REGNO (old)) == 1)
7248 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7249 if (ira_conflicts_p)
7250 /* Inform IRA about the change. */
7251 ira_mark_allocation_change (REGNO (old));
7252 alter_reg (REGNO (old), -1, false);
7256 /* Adjust any debug insns between temp and insn. */
7257 while ((temp = NEXT_INSN (temp)) != insn)
7258 if (DEBUG_INSN_P (temp))
7259 replace_rtx (PATTERN (temp), old, reloadreg);
7261 gcc_assert (NOTE_P (temp));
7265 SET_DEST (PATTERN (temp)) = old;
7270 /* We can't do that, so output an insn to load RELOADREG. */
7272 /* If we have a secondary reload, pick up the secondary register
7273 and icode, if any. If OLDEQUIV and OLD are different or
7274 if this is an in-out reload, recompute whether or not we
7275 still need a secondary register and what the icode should
7276 be. If we still need a secondary register and the class or
7277 icode is different, go back to reloading from OLD if using
7278 OLDEQUIV means that we got the wrong type of register. We
7279 cannot have different class or icode due to an in-out reload
7280 because we don't make such reloads when both the input and
7281 output need secondary reload registers. */
7283 if (! special && rl->secondary_in_reload >= 0)
7285 rtx second_reload_reg = 0;
7286 rtx third_reload_reg = 0;
7287 int secondary_reload = rl->secondary_in_reload;
7288 rtx real_oldequiv = oldequiv;
7291 enum insn_code icode;
7292 enum insn_code tertiary_icode = CODE_FOR_nothing;
7294 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7295 and similarly for OLD.
7296 See comments in get_secondary_reload in reload.c. */
7297 /* If it is a pseudo that cannot be replaced with its
7298 equivalent MEM, we must fall back to reload_in, which
7299 will have all the necessary substitutions registered.
7300 Likewise for a pseudo that can't be replaced with its
7301 equivalent constant.
7303 Take extra care for subregs of such pseudos. Note that
7304 we cannot use reg_equiv_mem in this case because it is
7305 not in the right mode. */
7308 if (GET_CODE (tmp) == SUBREG)
7309 tmp = SUBREG_REG (tmp);
7311 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7312 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7313 || reg_equiv_constant (REGNO (tmp)) != 0))
7315 if (! reg_equiv_mem (REGNO (tmp))
7316 || num_not_at_initial_offset
7317 || GET_CODE (oldequiv) == SUBREG)
7318 real_oldequiv = rl->in;
7320 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7324 if (GET_CODE (tmp) == SUBREG)
7325 tmp = SUBREG_REG (tmp);
7327 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7328 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7329 || reg_equiv_constant (REGNO (tmp)) != 0))
7331 if (! reg_equiv_mem (REGNO (tmp))
7332 || num_not_at_initial_offset
7333 || GET_CODE (old) == SUBREG)
7336 real_old = reg_equiv_mem (REGNO (tmp));
7339 second_reload_reg = rld[secondary_reload].reg_rtx;
7340 if (rld[secondary_reload].secondary_in_reload >= 0)
7342 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7344 third_reload_reg = rld[tertiary_reload].reg_rtx;
7345 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7346 /* We'd have to add more code for quartary reloads. */
7347 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7349 icode = rl->secondary_in_icode;
7351 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7352 || (rl->in != 0 && rl->out != 0))
7354 secondary_reload_info sri, sri2;
7355 enum reg_class new_class, new_t_class;
7357 sri.icode = CODE_FOR_nothing;
7358 sri.prev_sri = NULL;
7360 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7364 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7365 second_reload_reg = 0;
7366 else if (new_class == NO_REGS)
7368 if (reload_adjust_reg_for_icode (&second_reload_reg,
7370 (enum insn_code) sri.icode))
7372 icode = (enum insn_code) sri.icode;
7373 third_reload_reg = 0;
7378 real_oldequiv = real_old;
7381 else if (sri.icode != CODE_FOR_nothing)
7382 /* We currently lack a way to express this in reloads. */
7386 sri2.icode = CODE_FOR_nothing;
7387 sri2.prev_sri = &sri;
7389 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7392 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7394 if (reload_adjust_reg_for_temp (&second_reload_reg,
7398 third_reload_reg = 0;
7399 tertiary_icode = (enum insn_code) sri2.icode;
7404 real_oldequiv = real_old;
7407 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7409 rtx intermediate = second_reload_reg;
7411 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7413 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7417 second_reload_reg = intermediate;
7418 tertiary_icode = (enum insn_code) sri2.icode;
7423 real_oldequiv = real_old;
7426 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7428 rtx intermediate = second_reload_reg;
7430 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7432 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7435 second_reload_reg = intermediate;
7436 tertiary_icode = (enum insn_code) sri2.icode;
7441 real_oldequiv = real_old;
7446 /* This could be handled more intelligently too. */
7448 real_oldequiv = real_old;
7453 /* If we still need a secondary reload register, check
7454 to see if it is being used as a scratch or intermediate
7455 register and generate code appropriately. If we need
7456 a scratch register, use REAL_OLDEQUIV since the form of
7457 the insn may depend on the actual address if it is
7460 if (second_reload_reg)
7462 if (icode != CODE_FOR_nothing)
7464 /* We'd have to add extra code to handle this case. */
7465 gcc_assert (!third_reload_reg);
7467 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7468 second_reload_reg));
7473 /* See if we need a scratch register to load the
7474 intermediate register (a tertiary reload). */
7475 if (tertiary_icode != CODE_FOR_nothing)
7477 emit_insn ((GEN_FCN (tertiary_icode)
7478 (second_reload_reg, real_oldequiv,
7479 third_reload_reg)));
7481 else if (third_reload_reg)
7483 gen_reload (third_reload_reg, real_oldequiv,
7486 gen_reload (second_reload_reg, third_reload_reg,
7491 gen_reload (second_reload_reg, real_oldequiv,
7495 oldequiv = second_reload_reg;
7500 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7502 rtx real_oldequiv = oldequiv;
7504 if ((REG_P (oldequiv)
7505 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7506 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7507 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7508 || (GET_CODE (oldequiv) == SUBREG
7509 && REG_P (SUBREG_REG (oldequiv))
7510 && (REGNO (SUBREG_REG (oldequiv))
7511 >= FIRST_PSEUDO_REGISTER)
7512 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7513 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7514 || (CONSTANT_P (oldequiv)
7515 && (targetm.preferred_reload_class (oldequiv,
7516 REGNO_REG_CLASS (REGNO (reloadreg)))
7518 real_oldequiv = rl->in;
7519 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7523 if (cfun->can_throw_non_call_exceptions)
7524 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7526 /* End this sequence. */
7527 *where = get_insns ();
7530 /* Update reload_override_in so that delete_address_reloads_1
7531 can see the actual register usage. */
7533 reload_override_in[j] = oldequiv;
7536 /* Generate insns to for the output reload RL, which is for the insn described
7537 by CHAIN and has the number J. */
7539 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7543 rtx insn = chain->insn;
7546 enum machine_mode mode;
7550 if (rl->when_needed == RELOAD_OTHER)
7553 push_to_sequence (output_reload_insns[rl->opnum]);
7555 rl_reg_rtx = reload_reg_rtx_for_output[j];
7556 mode = GET_MODE (rl_reg_rtx);
7558 reloadreg = rl_reg_rtx;
7560 /* If we need two reload regs, set RELOADREG to the intermediate
7561 one, since it will be stored into OLD. We might need a secondary
7562 register only for an input reload, so check again here. */
7564 if (rl->secondary_out_reload >= 0)
7567 int secondary_reload = rl->secondary_out_reload;
7568 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7570 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7571 && reg_equiv_mem (REGNO (old)) != 0)
7572 real_old = reg_equiv_mem (REGNO (old));
7574 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7576 rtx second_reloadreg = reloadreg;
7577 reloadreg = rld[secondary_reload].reg_rtx;
7579 /* See if RELOADREG is to be used as a scratch register
7580 or as an intermediate register. */
7581 if (rl->secondary_out_icode != CODE_FOR_nothing)
7583 /* We'd have to add extra code to handle this case. */
7584 gcc_assert (tertiary_reload < 0);
7586 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7587 (real_old, second_reloadreg, reloadreg)));
7592 /* See if we need both a scratch and intermediate reload
7595 enum insn_code tertiary_icode
7596 = rld[secondary_reload].secondary_out_icode;
7598 /* We'd have to add more code for quartary reloads. */
7599 gcc_assert (tertiary_reload < 0
7600 || rld[tertiary_reload].secondary_out_reload < 0);
7602 if (GET_MODE (reloadreg) != mode)
7603 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7605 if (tertiary_icode != CODE_FOR_nothing)
7607 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7609 /* Copy primary reload reg to secondary reload reg.
7610 (Note that these have been swapped above, then
7611 secondary reload reg to OLD using our insn.) */
7613 /* If REAL_OLD is a paradoxical SUBREG, remove it
7614 and try to put the opposite SUBREG on
7616 strip_paradoxical_subreg (&real_old, &reloadreg);
7618 gen_reload (reloadreg, second_reloadreg,
7619 rl->opnum, rl->when_needed);
7620 emit_insn ((GEN_FCN (tertiary_icode)
7621 (real_old, reloadreg, third_reloadreg)));
7627 /* Copy between the reload regs here and then to
7630 gen_reload (reloadreg, second_reloadreg,
7631 rl->opnum, rl->when_needed);
7632 if (tertiary_reload >= 0)
7634 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7636 gen_reload (third_reloadreg, reloadreg,
7637 rl->opnum, rl->when_needed);
7638 reloadreg = third_reloadreg;
7645 /* Output the last reload insn. */
7650 /* Don't output the last reload if OLD is not the dest of
7651 INSN and is in the src and is clobbered by INSN. */
7652 if (! flag_expensive_optimizations
7654 || !(set = single_set (insn))
7655 || rtx_equal_p (old, SET_DEST (set))
7656 || !reg_mentioned_p (old, SET_SRC (set))
7657 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7658 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7659 gen_reload (old, reloadreg, rl->opnum,
7663 /* Look at all insns we emitted, just to be safe. */
7664 for (p = get_insns (); p; p = NEXT_INSN (p))
7667 rtx pat = PATTERN (p);
7669 /* If this output reload doesn't come from a spill reg,
7670 clear any memory of reloaded copies of the pseudo reg.
7671 If this output reload comes from a spill reg,
7672 reg_has_output_reload will make this do nothing. */
7673 note_stores (pat, forget_old_reloads_1, NULL);
7675 if (reg_mentioned_p (rl_reg_rtx, pat))
7677 rtx set = single_set (insn);
7678 if (reload_spill_index[j] < 0
7680 && SET_SRC (set) == rl_reg_rtx)
7682 int src = REGNO (SET_SRC (set));
7684 reload_spill_index[j] = src;
7685 SET_HARD_REG_BIT (reg_is_output_reload, src);
7686 if (find_regno_note (insn, REG_DEAD, src))
7687 SET_HARD_REG_BIT (reg_reloaded_died, src);
7689 if (HARD_REGISTER_P (rl_reg_rtx))
7691 int s = rl->secondary_out_reload;
7692 set = single_set (p);
7693 /* If this reload copies only to the secondary reload
7694 register, the secondary reload does the actual
7696 if (s >= 0 && set == NULL_RTX)
7697 /* We can't tell what function the secondary reload
7698 has and where the actual store to the pseudo is
7699 made; leave new_spill_reg_store alone. */
7702 && SET_SRC (set) == rl_reg_rtx
7703 && SET_DEST (set) == rld[s].reg_rtx)
7705 /* Usually the next instruction will be the
7706 secondary reload insn; if we can confirm
7707 that it is, setting new_spill_reg_store to
7708 that insn will allow an extra optimization. */
7709 rtx s_reg = rld[s].reg_rtx;
7710 rtx next = NEXT_INSN (p);
7711 rld[s].out = rl->out;
7712 rld[s].out_reg = rl->out_reg;
7713 set = single_set (next);
7714 if (set && SET_SRC (set) == s_reg
7715 && ! new_spill_reg_store[REGNO (s_reg)])
7717 SET_HARD_REG_BIT (reg_is_output_reload,
7719 new_spill_reg_store[REGNO (s_reg)] = next;
7723 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7728 if (rl->when_needed == RELOAD_OTHER)
7730 emit_insn (other_output_reload_insns[rl->opnum]);
7731 other_output_reload_insns[rl->opnum] = get_insns ();
7734 output_reload_insns[rl->opnum] = get_insns ();
7736 if (cfun->can_throw_non_call_exceptions)
7737 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7742 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7743 and has the number J. */
7745 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7747 rtx insn = chain->insn;
7748 rtx old = (rl->in && MEM_P (rl->in)
7749 ? rl->in_reg : rl->in);
7750 rtx reg_rtx = rl->reg_rtx;
7754 enum machine_mode mode;
7756 /* Determine the mode to reload in.
7757 This is very tricky because we have three to choose from.
7758 There is the mode the insn operand wants (rl->inmode).
7759 There is the mode of the reload register RELOADREG.
7760 There is the intrinsic mode of the operand, which we could find
7761 by stripping some SUBREGs.
7762 It turns out that RELOADREG's mode is irrelevant:
7763 we can change that arbitrarily.
7765 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7766 then the reload reg may not support QImode moves, so use SImode.
7767 If foo is in memory due to spilling a pseudo reg, this is safe,
7768 because the QImode value is in the least significant part of a
7769 slot big enough for a SImode. If foo is some other sort of
7770 memory reference, then it is impossible to reload this case,
7771 so previous passes had better make sure this never happens.
7773 Then consider a one-word union which has SImode and one of its
7774 members is a float, being fetched as (SUBREG:SF union:SI).
7775 We must fetch that as SFmode because we could be loading into
7776 a float-only register. In this case OLD's mode is correct.
7778 Consider an immediate integer: it has VOIDmode. Here we need
7779 to get a mode from something else.
7781 In some cases, there is a fourth mode, the operand's
7782 containing mode. If the insn specifies a containing mode for
7783 this operand, it overrides all others.
7785 I am not sure whether the algorithm here is always right,
7786 but it does the right things in those cases. */
7788 mode = GET_MODE (old);
7789 if (mode == VOIDmode)
7792 /* We cannot use gen_lowpart_common since it can do the wrong thing
7793 when REG_RTX has a multi-word mode. Note that REG_RTX must
7794 always be a REG here. */
7795 if (GET_MODE (reg_rtx) != mode)
7796 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7798 reload_reg_rtx_for_input[j] = reg_rtx;
7801 /* AUTO_INC reloads need to be handled even if inherited. We got an
7802 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7803 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7804 && ! rtx_equal_p (reg_rtx, old)
7806 emit_input_reload_insns (chain, rld + j, old, j);
7808 /* When inheriting a wider reload, we have a MEM in rl->in,
7809 e.g. inheriting a SImode output reload for
7810 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7811 if (optimize && reload_inherited[j] && rl->in
7813 && MEM_P (rl->in_reg)
7814 && reload_spill_index[j] >= 0
7815 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7816 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7818 /* If we are reloading a register that was recently stored in with an
7819 output-reload, see if we can prove there was
7820 actually no need to store the old value in it. */
7823 && (reload_inherited[j] || reload_override_in[j])
7826 && spill_reg_store[REGNO (reg_rtx)] != 0
7828 /* There doesn't seem to be any reason to restrict this to pseudos
7829 and doing so loses in the case where we are copying from a
7830 register of the wrong class. */
7831 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7833 /* The insn might have already some references to stackslots
7834 replaced by MEMs, while reload_out_reg still names the
7836 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7837 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7838 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7841 /* Do output reloading for reload RL, which is for the insn described by
7842 CHAIN and has the number J.
7843 ??? At some point we need to support handling output reloads of
7844 JUMP_INSNs or insns that set cc0. */
7846 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7849 rtx insn = chain->insn;
7850 /* If this is an output reload that stores something that is
7851 not loaded in this same reload, see if we can eliminate a previous
7853 rtx pseudo = rl->out_reg;
7854 rtx reg_rtx = rl->reg_rtx;
7856 if (rl->out && reg_rtx)
7858 enum machine_mode mode;
7860 /* Determine the mode to reload in.
7861 See comments above (for input reloading). */
7862 mode = GET_MODE (rl->out);
7863 if (mode == VOIDmode)
7865 /* VOIDmode should never happen for an output. */
7866 if (asm_noperands (PATTERN (insn)) < 0)
7867 /* It's the compiler's fault. */
7868 fatal_insn ("VOIDmode on an output", insn);
7869 error_for_asm (insn, "output operand is constant in %<asm%>");
7870 /* Prevent crash--use something we know is valid. */
7872 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7874 if (GET_MODE (reg_rtx) != mode)
7875 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7877 reload_reg_rtx_for_output[j] = reg_rtx;
7882 && ! rtx_equal_p (rl->in_reg, pseudo)
7883 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7884 && reg_last_reload_reg[REGNO (pseudo)])
7886 int pseudo_no = REGNO (pseudo);
7887 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7889 /* We don't need to test full validity of last_regno for
7890 inherit here; we only want to know if the store actually
7891 matches the pseudo. */
7892 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7893 && reg_reloaded_contents[last_regno] == pseudo_no
7894 && spill_reg_store[last_regno]
7895 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7896 delete_output_reload (insn, j, last_regno, reg_rtx);
7902 || rtx_equal_p (old, reg_rtx))
7905 /* An output operand that dies right away does need a reload,
7906 but need not be copied from it. Show the new location in the
7908 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7909 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7911 XEXP (note, 0) = reg_rtx;
7914 /* Likewise for a SUBREG of an operand that dies. */
7915 else if (GET_CODE (old) == SUBREG
7916 && REG_P (SUBREG_REG (old))
7917 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7920 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7923 else if (GET_CODE (old) == SCRATCH)
7924 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7925 but we don't want to make an output reload. */
7928 /* If is a JUMP_INSN, we can't support output reloads yet. */
7929 gcc_assert (NONJUMP_INSN_P (insn));
7931 emit_output_reload_insns (chain, rld + j, j);
7934 /* A reload copies values of MODE from register SRC to register DEST.
7935 Return true if it can be treated for inheritance purposes like a
7936 group of reloads, each one reloading a single hard register. The
7937 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7938 occupy the same number of hard registers. */
7941 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7942 int src ATTRIBUTE_UNUSED,
7943 enum machine_mode mode ATTRIBUTE_UNUSED)
7945 #ifdef CANNOT_CHANGE_MODE_CLASS
7946 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7947 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7953 /* Output insns to reload values in and out of the chosen reload regs. */
7956 emit_reload_insns (struct insn_chain *chain)
7958 rtx insn = chain->insn;
7962 CLEAR_HARD_REG_SET (reg_reloaded_died);
7964 for (j = 0; j < reload_n_operands; j++)
7965 input_reload_insns[j] = input_address_reload_insns[j]
7966 = inpaddr_address_reload_insns[j]
7967 = output_reload_insns[j] = output_address_reload_insns[j]
7968 = outaddr_address_reload_insns[j]
7969 = other_output_reload_insns[j] = 0;
7970 other_input_address_reload_insns = 0;
7971 other_input_reload_insns = 0;
7972 operand_reload_insns = 0;
7973 other_operand_reload_insns = 0;
7975 /* Dump reloads into the dump file. */
7978 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7979 debug_reload_to_stream (dump_file);
7982 /* Now output the instructions to copy the data into and out of the
7983 reload registers. Do these in the order that the reloads were reported,
7984 since reloads of base and index registers precede reloads of operands
7985 and the operands may need the base and index registers reloaded. */
7987 for (j = 0; j < n_reloads; j++)
7989 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7993 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7994 new_spill_reg_store[i] = 0;
7997 do_input_reload (chain, rld + j, j);
7998 do_output_reload (chain, rld + j, j);
8001 /* Now write all the insns we made for reloads in the order expected by
8002 the allocation functions. Prior to the insn being reloaded, we write
8003 the following reloads:
8005 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8007 RELOAD_OTHER reloads.
8009 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8010 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8011 RELOAD_FOR_INPUT reload for the operand.
8013 RELOAD_FOR_OPADDR_ADDRS reloads.
8015 RELOAD_FOR_OPERAND_ADDRESS reloads.
8017 After the insn being reloaded, we write the following:
8019 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8020 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8021 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8022 reloads for the operand. The RELOAD_OTHER output reloads are
8023 output in descending order by reload number. */
8025 emit_insn_before (other_input_address_reload_insns, insn);
8026 emit_insn_before (other_input_reload_insns, insn);
8028 for (j = 0; j < reload_n_operands; j++)
8030 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8031 emit_insn_before (input_address_reload_insns[j], insn);
8032 emit_insn_before (input_reload_insns[j], insn);
8035 emit_insn_before (other_operand_reload_insns, insn);
8036 emit_insn_before (operand_reload_insns, insn);
8038 for (j = 0; j < reload_n_operands; j++)
8040 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8041 x = emit_insn_after (output_address_reload_insns[j], x);
8042 x = emit_insn_after (output_reload_insns[j], x);
8043 emit_insn_after (other_output_reload_insns[j], x);
8046 /* For all the spill regs newly reloaded in this instruction,
8047 record what they were reloaded from, so subsequent instructions
8048 can inherit the reloads.
8050 Update spill_reg_store for the reloads of this insn.
8051 Copy the elements that were updated in the loop above. */
8053 for (j = 0; j < n_reloads; j++)
8055 int r = reload_order[j];
8056 int i = reload_spill_index[r];
8058 /* If this is a non-inherited input reload from a pseudo, we must
8059 clear any memory of a previous store to the same pseudo. Only do
8060 something if there will not be an output reload for the pseudo
8062 if (rld[r].in_reg != 0
8063 && ! (reload_inherited[r] || reload_override_in[r]))
8065 rtx reg = rld[r].in_reg;
8067 if (GET_CODE (reg) == SUBREG)
8068 reg = SUBREG_REG (reg);
8071 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8072 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8074 int nregno = REGNO (reg);
8076 if (reg_last_reload_reg[nregno])
8078 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8080 if (reg_reloaded_contents[last_regno] == nregno)
8081 spill_reg_store[last_regno] = 0;
8086 /* I is nonneg if this reload used a register.
8087 If rld[r].reg_rtx is 0, this is an optional reload
8088 that we opted to ignore. */
8090 if (i >= 0 && rld[r].reg_rtx != 0)
8092 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8095 /* For a multi register reload, we need to check if all or part
8096 of the value lives to the end. */
8097 for (k = 0; k < nr; k++)
8098 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
8099 rld[r].when_needed))
8100 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8102 /* Maybe the spill reg contains a copy of reload_out. */
8104 && (REG_P (rld[r].out)
8106 ? REG_P (rld[r].out_reg)
8107 /* The reload value is an auto-modification of
8108 some kind. For PRE_INC, POST_INC, PRE_DEC
8109 and POST_DEC, we record an equivalence
8110 between the reload register and the operand
8111 on the optimistic assumption that we can make
8112 the equivalence hold. reload_as_needed must
8113 then either make it hold or invalidate the
8116 PRE_MODIFY and POST_MODIFY addresses are reloaded
8117 somewhat differently, and allowing them here leads
8119 : (GET_CODE (rld[r].out) != POST_MODIFY
8120 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8123 enum machine_mode mode;
8126 reg = reload_reg_rtx_for_output[r];
8127 mode = GET_MODE (reg);
8128 regno = REGNO (reg);
8129 nregs = hard_regno_nregs[regno][mode];
8130 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8131 rld[r].when_needed))
8133 rtx out = (REG_P (rld[r].out)
8137 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8138 int out_regno = REGNO (out);
8139 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8140 : hard_regno_nregs[out_regno][mode]);
8143 spill_reg_store[regno] = new_spill_reg_store[regno];
8144 spill_reg_stored_to[regno] = out;
8145 reg_last_reload_reg[out_regno] = reg;
8147 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8148 && nregs == out_nregs
8149 && inherit_piecemeal_p (out_regno, regno, mode));
8151 /* If OUT_REGNO is a hard register, it may occupy more than
8152 one register. If it does, say what is in the
8153 rest of the registers assuming that both registers
8154 agree on how many words the object takes. If not,
8155 invalidate the subsequent registers. */
8157 if (HARD_REGISTER_NUM_P (out_regno))
8158 for (k = 1; k < out_nregs; k++)
8159 reg_last_reload_reg[out_regno + k]
8160 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8162 /* Now do the inverse operation. */
8163 for (k = 0; k < nregs; k++)
8165 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8166 reg_reloaded_contents[regno + k]
8167 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8170 reg_reloaded_insn[regno + k] = insn;
8171 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8172 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8173 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8176 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8181 /* Maybe the spill reg contains a copy of reload_in. Only do
8182 something if there will not be an output reload for
8183 the register being reloaded. */
8184 else if (rld[r].out_reg == 0
8186 && ((REG_P (rld[r].in)
8187 && !HARD_REGISTER_P (rld[r].in)
8188 && !REGNO_REG_SET_P (®_has_output_reload,
8190 || (REG_P (rld[r].in_reg)
8191 && !REGNO_REG_SET_P (®_has_output_reload,
8192 REGNO (rld[r].in_reg))))
8193 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8196 enum machine_mode mode;
8199 reg = reload_reg_rtx_for_input[r];
8200 mode = GET_MODE (reg);
8201 regno = REGNO (reg);
8202 nregs = hard_regno_nregs[regno][mode];
8203 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8204 rld[r].when_needed))
8211 if (REG_P (rld[r].in)
8212 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8214 else if (REG_P (rld[r].in_reg))
8217 in = XEXP (rld[r].in_reg, 0);
8218 in_regno = REGNO (in);
8220 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8221 : hard_regno_nregs[in_regno][mode]);
8223 reg_last_reload_reg[in_regno] = reg;
8225 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8226 && nregs == in_nregs
8227 && inherit_piecemeal_p (regno, in_regno, mode));
8229 if (HARD_REGISTER_NUM_P (in_regno))
8230 for (k = 1; k < in_nregs; k++)
8231 reg_last_reload_reg[in_regno + k]
8232 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8234 /* Unless we inherited this reload, show we haven't
8235 recently done a store.
8236 Previous stores of inherited auto_inc expressions
8237 also have to be discarded. */
8238 if (! reload_inherited[r]
8239 || (rld[r].out && ! rld[r].out_reg))
8240 spill_reg_store[regno] = 0;
8242 for (k = 0; k < nregs; k++)
8244 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8245 reg_reloaded_contents[regno + k]
8246 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8249 reg_reloaded_insn[regno + k] = insn;
8250 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8251 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8252 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8255 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8262 /* The following if-statement was #if 0'd in 1.34 (or before...).
8263 It's reenabled in 1.35 because supposedly nothing else
8264 deals with this problem. */
8266 /* If a register gets output-reloaded from a non-spill register,
8267 that invalidates any previous reloaded copy of it.
8268 But forget_old_reloads_1 won't get to see it, because
8269 it thinks only about the original insn. So invalidate it here.
8270 Also do the same thing for RELOAD_OTHER constraints where the
8271 output is discarded. */
8273 && ((rld[r].out != 0
8274 && (REG_P (rld[r].out)
8275 || (MEM_P (rld[r].out)
8276 && REG_P (rld[r].out_reg))))
8277 || (rld[r].out == 0 && rld[r].out_reg
8278 && REG_P (rld[r].out_reg))))
8280 rtx out = ((rld[r].out && REG_P (rld[r].out))
8281 ? rld[r].out : rld[r].out_reg);
8282 int out_regno = REGNO (out);
8283 enum machine_mode mode = GET_MODE (out);
8285 /* REG_RTX is now set or clobbered by the main instruction.
8286 As the comment above explains, forget_old_reloads_1 only
8287 sees the original instruction, and there is no guarantee
8288 that the original instruction also clobbered REG_RTX.
8289 For example, if find_reloads sees that the input side of
8290 a matched operand pair dies in this instruction, it may
8291 use the input register as the reload register.
8293 Calling forget_old_reloads_1 is a waste of effort if
8294 REG_RTX is also the output register.
8296 If we know that REG_RTX holds the value of a pseudo
8297 register, the code after the call will record that fact. */
8298 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8299 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8301 if (!HARD_REGISTER_NUM_P (out_regno))
8303 rtx src_reg, store_insn = NULL_RTX;
8305 reg_last_reload_reg[out_regno] = 0;
8307 /* If we can find a hard register that is stored, record
8308 the storing insn so that we may delete this insn with
8309 delete_output_reload. */
8310 src_reg = reload_reg_rtx_for_output[r];
8312 /* If this is an optional reload, try to find the source reg
8313 from an input reload. */
8316 rtx set = single_set (insn);
8317 if (set && SET_DEST (set) == rld[r].out)
8321 src_reg = SET_SRC (set);
8323 for (k = 0; k < n_reloads; k++)
8325 if (rld[k].in == src_reg)
8327 src_reg = reload_reg_rtx_for_input[k];
8334 store_insn = new_spill_reg_store[REGNO (src_reg)];
8335 if (src_reg && REG_P (src_reg)
8336 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8338 int src_regno, src_nregs, k;
8341 gcc_assert (GET_MODE (src_reg) == mode);
8342 src_regno = REGNO (src_reg);
8343 src_nregs = hard_regno_nregs[src_regno][mode];
8344 /* The place where to find a death note varies with
8345 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8346 necessarily checked exactly in the code that moves
8347 notes, so just check both locations. */
8348 note = find_regno_note (insn, REG_DEAD, src_regno);
8349 if (! note && store_insn)
8350 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8351 for (k = 0; k < src_nregs; k++)
8353 spill_reg_store[src_regno + k] = store_insn;
8354 spill_reg_stored_to[src_regno + k] = out;
8355 reg_reloaded_contents[src_regno + k] = out_regno;
8356 reg_reloaded_insn[src_regno + k] = store_insn;
8357 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8358 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8359 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8361 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8364 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8366 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8368 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8370 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8372 reg_last_reload_reg[out_regno] = src_reg;
8373 /* We have to set reg_has_output_reload here, or else
8374 forget_old_reloads_1 will clear reg_last_reload_reg
8376 SET_REGNO_REG_SET (®_has_output_reload,
8382 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8384 for (k = 0; k < out_nregs; k++)
8385 reg_last_reload_reg[out_regno + k] = 0;
8389 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8392 /* Go through the motions to emit INSN and test if it is strictly valid.
8393 Return the emitted insn if valid, else return NULL. */
8396 emit_insn_if_valid_for_reload (rtx insn)
8398 rtx last = get_last_insn ();
8401 insn = emit_insn (insn);
8402 code = recog_memoized (insn);
8406 extract_insn (insn);
8407 /* We want constrain operands to treat this insn strictly in its
8408 validity determination, i.e., the way it would after reload has
8410 if (constrain_operands (1))
8414 delete_insns_since (last);
8418 /* Emit code to perform a reload from IN (which may be a reload register) to
8419 OUT (which may also be a reload register). IN or OUT is from operand
8420 OPNUM with reload type TYPE.
8422 Returns first insn emitted. */
8425 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8427 rtx last = get_last_insn ();
8430 /* If IN is a paradoxical SUBREG, remove it and try to put the
8431 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8432 if (!strip_paradoxical_subreg (&in, &out))
8433 strip_paradoxical_subreg (&out, &in);
8435 /* How to do this reload can get quite tricky. Normally, we are being
8436 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8437 register that didn't get a hard register. In that case we can just
8438 call emit_move_insn.
8440 We can also be asked to reload a PLUS that adds a register or a MEM to
8441 another register, constant or MEM. This can occur during frame pointer
8442 elimination and while reloading addresses. This case is handled by
8443 trying to emit a single insn to perform the add. If it is not valid,
8444 we use a two insn sequence.
8446 Or we can be asked to reload an unary operand that was a fragment of
8447 an addressing mode, into a register. If it isn't recognized as-is,
8448 we try making the unop operand and the reload-register the same:
8449 (set reg:X (unop:X expr:Y))
8450 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8452 Finally, we could be called to handle an 'o' constraint by putting
8453 an address into a register. In that case, we first try to do this
8454 with a named pattern of "reload_load_address". If no such pattern
8455 exists, we just emit a SET insn and hope for the best (it will normally
8456 be valid on machines that use 'o').
8458 This entire process is made complex because reload will never
8459 process the insns we generate here and so we must ensure that
8460 they will fit their constraints and also by the fact that parts of
8461 IN might be being reloaded separately and replaced with spill registers.
8462 Because of this, we are, in some sense, just guessing the right approach
8463 here. The one listed above seems to work.
8465 ??? At some point, this whole thing needs to be rethought. */
8467 if (GET_CODE (in) == PLUS
8468 && (REG_P (XEXP (in, 0))
8469 || GET_CODE (XEXP (in, 0)) == SUBREG
8470 || MEM_P (XEXP (in, 0)))
8471 && (REG_P (XEXP (in, 1))
8472 || GET_CODE (XEXP (in, 1)) == SUBREG
8473 || CONSTANT_P (XEXP (in, 1))
8474 || MEM_P (XEXP (in, 1))))
8476 /* We need to compute the sum of a register or a MEM and another
8477 register, constant, or MEM, and put it into the reload
8478 register. The best possible way of doing this is if the machine
8479 has a three-operand ADD insn that accepts the required operands.
8481 The simplest approach is to try to generate such an insn and see if it
8482 is recognized and matches its constraints. If so, it can be used.
8484 It might be better not to actually emit the insn unless it is valid,
8485 but we need to pass the insn as an operand to `recog' and
8486 `extract_insn' and it is simpler to emit and then delete the insn if
8487 not valid than to dummy things up. */
8489 rtx op0, op1, tem, insn;
8490 enum insn_code code;
8492 op0 = find_replacement (&XEXP (in, 0));
8493 op1 = find_replacement (&XEXP (in, 1));
8495 /* Since constraint checking is strict, commutativity won't be
8496 checked, so we need to do that here to avoid spurious failure
8497 if the add instruction is two-address and the second operand
8498 of the add is the same as the reload reg, which is frequently
8499 the case. If the insn would be A = B + A, rearrange it so
8500 it will be A = A + B as constrain_operands expects. */
8502 if (REG_P (XEXP (in, 1))
8503 && REGNO (out) == REGNO (XEXP (in, 1)))
8504 tem = op0, op0 = op1, op1 = tem;
8506 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8507 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8509 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8513 /* If that failed, we must use a conservative two-insn sequence.
8515 Use a move to copy one operand into the reload register. Prefer
8516 to reload a constant, MEM or pseudo since the move patterns can
8517 handle an arbitrary operand. If OP1 is not a constant, MEM or
8518 pseudo and OP1 is not a valid operand for an add instruction, then
8521 After reloading one of the operands into the reload register, add
8522 the reload register to the output register.
8524 If there is another way to do this for a specific machine, a
8525 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8528 code = optab_handler (add_optab, GET_MODE (out));
8530 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8532 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8533 || (code != CODE_FOR_nothing
8534 && !insn_operand_matches (code, 2, op1)))
8535 tem = op0, op0 = op1, op1 = tem;
8537 gen_reload (out, op0, opnum, type);
8539 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8540 This fixes a problem on the 32K where the stack pointer cannot
8541 be used as an operand of an add insn. */
8543 if (rtx_equal_p (op0, op1))
8546 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8549 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8550 set_unique_reg_note (insn, REG_EQUIV, in);
8554 /* If that failed, copy the address register to the reload register.
8555 Then add the constant to the reload register. */
8557 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8558 gen_reload (out, op1, opnum, type);
8559 insn = emit_insn (gen_add2_insn (out, op0));
8560 set_unique_reg_note (insn, REG_EQUIV, in);
8563 #ifdef SECONDARY_MEMORY_NEEDED
8564 /* If we need a memory location to do the move, do it that way. */
8565 else if ((REG_P (in)
8566 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8567 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8569 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8570 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8571 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8572 REGNO_REG_CLASS (reg_or_subregno (out)),
8575 /* Get the memory to use and rewrite both registers to its mode. */
8576 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8578 if (GET_MODE (loc) != GET_MODE (out))
8579 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8581 if (GET_MODE (loc) != GET_MODE (in))
8582 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8584 gen_reload (loc, in, opnum, type);
8585 gen_reload (out, loc, opnum, type);
8588 else if (REG_P (out) && UNARY_P (in))
8595 op1 = find_replacement (&XEXP (in, 0));
8596 if (op1 != XEXP (in, 0))
8597 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8599 /* First, try a plain SET. */
8600 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8604 /* If that failed, move the inner operand to the reload
8605 register, and try the same unop with the inner expression
8606 replaced with the reload register. */
8608 if (GET_MODE (op1) != GET_MODE (out))
8609 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8613 gen_reload (out_moded, op1, opnum, type);
8616 = gen_rtx_SET (VOIDmode, out,
8617 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8619 insn = emit_insn_if_valid_for_reload (insn);
8622 set_unique_reg_note (insn, REG_EQUIV, in);
8626 fatal_insn ("failure trying to reload:", set);
8628 /* If IN is a simple operand, use gen_move_insn. */
8629 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8631 tem = emit_insn (gen_move_insn (out, in));
8632 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8633 mark_jump_label (in, tem, 0);
8636 #ifdef HAVE_reload_load_address
8637 else if (HAVE_reload_load_address)
8638 emit_insn (gen_reload_load_address (out, in));
8641 /* Otherwise, just write (set OUT IN) and hope for the best. */
8643 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8645 /* Return the first insn emitted.
8646 We can not just return get_last_insn, because there may have
8647 been multiple instructions emitted. Also note that gen_move_insn may
8648 emit more than one insn itself, so we can not assume that there is one
8649 insn emitted per emit_insn_before call. */
8651 return last ? NEXT_INSN (last) : get_insns ();
8654 /* Delete a previously made output-reload whose result we now believe
8655 is not needed. First we double-check.
8657 INSN is the insn now being processed.
8658 LAST_RELOAD_REG is the hard register number for which we want to delete
8659 the last output reload.
8660 J is the reload-number that originally used REG. The caller has made
8661 certain that reload J doesn't use REG any longer for input.
8662 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8665 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8667 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8668 rtx reg = spill_reg_stored_to[last_reload_reg];
8671 int n_inherited = 0;
8677 /* It is possible that this reload has been only used to set another reload
8678 we eliminated earlier and thus deleted this instruction too. */
8679 if (INSN_DELETED_P (output_reload_insn))
8682 /* Get the raw pseudo-register referred to. */
8684 while (GET_CODE (reg) == SUBREG)
8685 reg = SUBREG_REG (reg);
8686 substed = reg_equiv_memory_loc (REGNO (reg));
8688 /* This is unsafe if the operand occurs more often in the current
8689 insn than it is inherited. */
8690 for (k = n_reloads - 1; k >= 0; k--)
8692 rtx reg2 = rld[k].in;
8695 if (MEM_P (reg2) || reload_override_in[k])
8696 reg2 = rld[k].in_reg;
8698 if (rld[k].out && ! rld[k].out_reg)
8699 reg2 = XEXP (rld[k].in_reg, 0);
8701 while (GET_CODE (reg2) == SUBREG)
8702 reg2 = SUBREG_REG (reg2);
8703 if (rtx_equal_p (reg2, reg))
8705 if (reload_inherited[k] || reload_override_in[k] || k == j)
8711 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8712 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8713 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8716 n_occurrences += count_occurrences (PATTERN (insn),
8717 eliminate_regs (substed, VOIDmode,
8719 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8721 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8722 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8724 if (n_occurrences > n_inherited)
8727 regno = REGNO (reg);
8728 if (regno >= FIRST_PSEUDO_REGISTER)
8731 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8733 /* If the pseudo-reg we are reloading is no longer referenced
8734 anywhere between the store into it and here,
8735 and we're within the same basic block, then the value can only
8736 pass through the reload reg and end up here.
8737 Otherwise, give up--return. */
8738 for (i1 = NEXT_INSN (output_reload_insn);
8739 i1 != insn; i1 = NEXT_INSN (i1))
8741 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8743 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8744 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8746 /* If this is USE in front of INSN, we only have to check that
8747 there are no more references than accounted for by inheritance. */
8748 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8750 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8751 i1 = NEXT_INSN (i1);
8753 if (n_occurrences <= n_inherited && i1 == insn)
8759 /* We will be deleting the insn. Remove the spill reg information. */
8760 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8762 spill_reg_store[last_reload_reg + k] = 0;
8763 spill_reg_stored_to[last_reload_reg + k] = 0;
8766 /* The caller has already checked that REG dies or is set in INSN.
8767 It has also checked that we are optimizing, and thus some
8768 inaccuracies in the debugging information are acceptable.
8769 So we could just delete output_reload_insn. But in some cases
8770 we can improve the debugging information without sacrificing
8771 optimization - maybe even improving the code: See if the pseudo
8772 reg has been completely replaced with reload regs. If so, delete
8773 the store insn and forget we had a stack slot for the pseudo. */
8774 if (rld[j].out != rld[j].in
8775 && REG_N_DEATHS (REGNO (reg)) == 1
8776 && REG_N_SETS (REGNO (reg)) == 1
8777 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8778 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8782 /* We know that it was used only between here and the beginning of
8783 the current basic block. (We also know that the last use before
8784 INSN was the output reload we are thinking of deleting, but never
8785 mind that.) Search that range; see if any ref remains. */
8786 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8788 rtx set = single_set (i2);
8790 /* Uses which just store in the pseudo don't count,
8791 since if they are the only uses, they are dead. */
8792 if (set != 0 && SET_DEST (set) == reg)
8797 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8798 && reg_mentioned_p (reg, PATTERN (i2)))
8800 /* Some other ref remains; just delete the output reload we
8802 delete_address_reloads (output_reload_insn, insn);
8803 delete_insn (output_reload_insn);
8808 /* Delete the now-dead stores into this pseudo. Note that this
8809 loop also takes care of deleting output_reload_insn. */
8810 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8812 rtx set = single_set (i2);
8814 if (set != 0 && SET_DEST (set) == reg)
8816 delete_address_reloads (i2, insn);
8824 /* For the debugging info, say the pseudo lives in this reload reg. */
8825 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8826 if (ira_conflicts_p)
8827 /* Inform IRA about the change. */
8828 ira_mark_allocation_change (REGNO (reg));
8829 alter_reg (REGNO (reg), -1, false);
8833 delete_address_reloads (output_reload_insn, insn);
8834 delete_insn (output_reload_insn);
8838 /* We are going to delete DEAD_INSN. Recursively delete loads of
8839 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8840 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8842 delete_address_reloads (rtx dead_insn, rtx current_insn)
8844 rtx set = single_set (dead_insn);
8845 rtx set2, dst, prev, next;
8848 rtx dst = SET_DEST (set);
8850 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8852 /* If we deleted the store from a reloaded post_{in,de}c expression,
8853 we can delete the matching adds. */
8854 prev = PREV_INSN (dead_insn);
8855 next = NEXT_INSN (dead_insn);
8856 if (! prev || ! next)
8858 set = single_set (next);
8859 set2 = single_set (prev);
8861 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8862 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8863 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8865 dst = SET_DEST (set);
8866 if (! rtx_equal_p (dst, SET_DEST (set2))
8867 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8868 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8869 || (INTVAL (XEXP (SET_SRC (set), 1))
8870 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8872 delete_related_insns (prev);
8873 delete_related_insns (next);
8876 /* Subfunction of delete_address_reloads: process registers found in X. */
8878 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8880 rtx prev, set, dst, i2;
8882 enum rtx_code code = GET_CODE (x);
8886 const char *fmt = GET_RTX_FORMAT (code);
8887 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8890 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8891 else if (fmt[i] == 'E')
8893 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8894 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8901 if (spill_reg_order[REGNO (x)] < 0)
8904 /* Scan backwards for the insn that sets x. This might be a way back due
8906 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8908 code = GET_CODE (prev);
8909 if (code == CODE_LABEL || code == JUMP_INSN)
8913 if (reg_set_p (x, PATTERN (prev)))
8915 if (reg_referenced_p (x, PATTERN (prev)))
8918 if (! prev || INSN_UID (prev) < reload_first_uid)
8920 /* Check that PREV only sets the reload register. */
8921 set = single_set (prev);
8924 dst = SET_DEST (set);
8926 || ! rtx_equal_p (dst, x))
8928 if (! reg_set_p (dst, PATTERN (dead_insn)))
8930 /* Check if DST was used in a later insn -
8931 it might have been inherited. */
8932 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8938 if (reg_referenced_p (dst, PATTERN (i2)))
8940 /* If there is a reference to the register in the current insn,
8941 it might be loaded in a non-inherited reload. If no other
8942 reload uses it, that means the register is set before
8944 if (i2 == current_insn)
8946 for (j = n_reloads - 1; j >= 0; j--)
8947 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8948 || reload_override_in[j] == dst)
8950 for (j = n_reloads - 1; j >= 0; j--)
8951 if (rld[j].in && rld[j].reg_rtx == dst)
8960 /* If DST is still live at CURRENT_INSN, check if it is used for
8961 any reload. Note that even if CURRENT_INSN sets DST, we still
8962 have to check the reloads. */
8963 if (i2 == current_insn)
8965 for (j = n_reloads - 1; j >= 0; j--)
8966 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8967 || reload_override_in[j] == dst)
8969 /* ??? We can't finish the loop here, because dst might be
8970 allocated to a pseudo in this block if no reload in this
8971 block needs any of the classes containing DST - see
8972 spill_hard_reg. There is no easy way to tell this, so we
8973 have to scan till the end of the basic block. */
8975 if (reg_set_p (dst, PATTERN (i2)))
8979 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8980 reg_reloaded_contents[REGNO (dst)] = -1;
8984 /* Output reload-insns to reload VALUE into RELOADREG.
8985 VALUE is an autoincrement or autodecrement RTX whose operand
8986 is a register or memory location;
8987 so reloading involves incrementing that location.
8988 IN is either identical to VALUE, or some cheaper place to reload from.
8990 INC_AMOUNT is the number to increment or decrement by (always positive).
8991 This cannot be deduced from VALUE. */
8994 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8996 /* REG or MEM to be copied and incremented. */
8997 rtx incloc = find_replacement (&XEXP (value, 0));
8998 /* Nonzero if increment after copying. */
8999 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9000 || GET_CODE (value) == POST_MODIFY);
9005 rtx real_in = in == value ? incloc : in;
9007 /* No hard register is equivalent to this register after
9008 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9009 we could inc/dec that register as well (maybe even using it for
9010 the source), but I'm not sure it's worth worrying about. */
9012 reg_last_reload_reg[REGNO (incloc)] = 0;
9014 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9016 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9017 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9021 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9022 inc_amount = -inc_amount;
9024 inc = GEN_INT (inc_amount);
9027 /* If this is post-increment, first copy the location to the reload reg. */
9028 if (post && real_in != reloadreg)
9029 emit_insn (gen_move_insn (reloadreg, real_in));
9033 /* See if we can directly increment INCLOC. Use a method similar to
9034 that in gen_reload. */
9036 last = get_last_insn ();
9037 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9038 gen_rtx_PLUS (GET_MODE (incloc),
9041 code = recog_memoized (add_insn);
9044 extract_insn (add_insn);
9045 if (constrain_operands (1))
9047 /* If this is a pre-increment and we have incremented the value
9048 where it lives, copy the incremented value to RELOADREG to
9049 be used as an address. */
9052 emit_insn (gen_move_insn (reloadreg, incloc));
9056 delete_insns_since (last);
9059 /* If couldn't do the increment directly, must increment in RELOADREG.
9060 The way we do this depends on whether this is pre- or post-increment.
9061 For pre-increment, copy INCLOC to the reload register, increment it
9062 there, then save back. */
9066 if (in != reloadreg)
9067 emit_insn (gen_move_insn (reloadreg, real_in));
9068 emit_insn (gen_add2_insn (reloadreg, inc));
9069 emit_insn (gen_move_insn (incloc, reloadreg));
9074 Because this might be a jump insn or a compare, and because RELOADREG
9075 may not be available after the insn in an input reload, we must do
9076 the incrementation before the insn being reloaded for.
9078 We have already copied IN to RELOADREG. Increment the copy in
9079 RELOADREG, save that back, then decrement RELOADREG so it has
9080 the original value. */
9082 emit_insn (gen_add2_insn (reloadreg, inc));
9083 emit_insn (gen_move_insn (incloc, reloadreg));
9084 if (CONST_INT_P (inc))
9085 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9087 emit_insn (gen_sub2_insn (reloadreg, inc));
9093 add_auto_inc_notes (rtx insn, rtx x)
9095 enum rtx_code code = GET_CODE (x);
9099 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9101 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9105 /* Scan all the operand sub-expressions. */
9106 fmt = GET_RTX_FORMAT (code);
9107 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9110 add_auto_inc_notes (insn, XEXP (x, i));
9111 else if (fmt[i] == 'E')
9112 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9113 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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