1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-flags.h"
33 #include "insn-codes.h"
38 #include "basic-block.h"
46 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
47 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
85 #ifndef REGISTER_MOVE_COST
86 #define REGISTER_MOVE_COST(x, y) 2
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx *reg_equiv_constant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx *reg_equiv_address;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static unsigned int *reg_max_ref_width;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx *reg_equiv_init;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs[FIRST_PSEUDO_REGISTER];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET *pseudo_previous_regs;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET *pseudo_forbidden_regs;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
239 /* Width allocated so far for that stack slot. */
240 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
265 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
292 extern tree current_function_decl;
294 extern union tree_node *current_function_decl;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 int initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset; /* Current offset between the two regs. */
314 int previous_offset; /* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table * reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at;
365 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
367 /* Number of labels in the current function. */
369 static int num_labels;
371 static void maybe_fix_stack_asms PARAMS ((void));
372 static void copy_reloads PARAMS ((struct insn_chain *));
373 static void calculate_needs_all_insns PARAMS ((int));
374 static int find_reg PARAMS ((struct insn_chain *, int,
376 static void find_reload_regs PARAMS ((struct insn_chain *, FILE *));
377 static void select_reload_regs PARAMS ((FILE *));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, FILE *, int));
397 static int finish_spills PARAMS ((int, FILE *));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
414 rtx, rtx, int, int));
415 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
417 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
419 static void failed_reload PARAMS ((rtx, int));
420 static int set_reload_reg PARAMS ((int, int));
421 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
422 static void choose_reload_regs PARAMS ((struct insn_chain *));
423 static void merge_assigned_reloads PARAMS ((rtx));
424 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
425 struct reload *, rtx, int));
426 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
427 struct reload *, int));
428 static void do_input_reload PARAMS ((struct insn_chain *,
429 struct reload *, int));
430 static void do_output_reload PARAMS ((struct insn_chain *,
431 struct reload *, int));
432 static void emit_reload_insns PARAMS ((struct insn_chain *));
433 static void delete_output_reload PARAMS ((rtx, int, int));
434 static void delete_address_reloads PARAMS ((rtx, rtx));
435 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
436 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
437 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
438 static void reload_cse_regs_1 PARAMS ((rtx));
439 static int reload_cse_noop_set_p PARAMS ((rtx));
440 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
441 static int reload_cse_simplify_operands PARAMS ((rtx));
442 static void reload_combine PARAMS ((void));
443 static void reload_combine_note_use PARAMS ((rtx *, rtx));
444 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
445 static void reload_cse_move2add PARAMS ((rtx));
446 static void move2add_note_store PARAMS ((rtx, rtx, void *));
448 static void add_auto_inc_notes PARAMS ((rtx, rtx));
450 static rtx gen_mode_int PARAMS ((enum machine_mode,
452 static void failed_reload PARAMS ((rtx, int));
453 static int set_reload_reg PARAMS ((int, int));
454 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
455 static void reload_cse_simplify PARAMS ((rtx));
456 extern void dump_needs PARAMS ((struct insn_chain *, FILE *));
458 /* Initialize the reload pass once per compilation. */
465 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
466 Set spill_indirect_levels to the number of levels such addressing is
467 permitted, zero if it is not permitted at all. */
470 = gen_rtx_MEM (Pmode,
473 LAST_VIRTUAL_REGISTER + 1),
475 spill_indirect_levels = 0;
477 while (memory_address_p (QImode, tem))
479 spill_indirect_levels++;
480 tem = gen_rtx_MEM (Pmode, tem);
483 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
485 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
486 indirect_symref_ok = memory_address_p (QImode, tem);
488 /* See if reg+reg is a valid (and offsettable) address. */
490 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
492 tem = gen_rtx_PLUS (Pmode,
493 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
494 gen_rtx_REG (Pmode, i));
496 /* This way, we make sure that reg+reg is an offsettable address. */
497 tem = plus_constant (tem, 4);
499 if (memory_address_p (QImode, tem))
501 double_reg_address_ok = 1;
506 /* Initialize obstack for our rtl allocation. */
507 gcc_obstack_init (&reload_obstack);
508 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
510 INIT_REG_SET (&spilled_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = (struct insn_chain *)
526 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
527 INIT_REG_SET (&c->live_throughout);
528 INIT_REG_SET (&c->dead_or_set);
532 c = unused_insn_chains;
533 unused_insn_chains = c->next;
535 c->is_caller_save_insn = 0;
536 c->need_operand_change = 0;
542 /* Small utility function to set all regs in hard reg set TO which are
543 allocated to pseudos in regset FROM. */
546 compute_use_by_pseudos (to, from)
552 EXECUTE_IF_SET_IN_REG_SET
553 (from, FIRST_PSEUDO_REGISTER, regno,
555 int r = reg_renumber[regno];
560 /* reload_combine uses the information from
561 BASIC_BLOCK->global_live_at_start, which might still
562 contain registers that have not actually been allocated
563 since they have an equivalence. */
564 if (! reload_completed)
569 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
571 SET_HARD_REG_BIT (*to, r + nregs);
576 /* Global variables used by reload and its subroutines. */
578 /* Set during calculate_needs if an insn needs register elimination. */
579 static int something_needs_elimination;
580 /* Set during calculate_needs if an insn needs an operand changed. */
581 int something_needs_operands_changed;
583 /* Nonzero means we couldn't get enough spill regs. */
586 /* Main entry point for the reload pass.
588 FIRST is the first insn of the function being compiled.
590 GLOBAL nonzero means we were called from global_alloc
591 and should attempt to reallocate any pseudoregs that we
592 displace from hard regs we will use for reloads.
593 If GLOBAL is zero, we do not have enough information to do that,
594 so any pseudo reg that is spilled must go to the stack.
596 DUMPFILE is the global-reg debugging dump file stream, or 0.
597 If it is nonzero, messages are written to it to describe
598 which registers are seized as reload regs, which pseudo regs
599 are spilled from them, and where the pseudo regs are reallocated to.
601 Return value is nonzero if reload failed
602 and we must not do any more for this function. */
605 reload (first, global, dumpfile)
612 register struct elim_table *ep;
614 /* The two pointers used to track the true location of the memory used
615 for label offsets. */
616 char *real_known_ptr = NULL_PTR;
617 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
619 /* Make sure even insns with volatile mem refs are recognizable. */
624 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
626 /* Make sure that the last insn in the chain
627 is not something that needs reloading. */
628 emit_note (NULL_PTR, NOTE_INSN_DELETED);
630 /* Enable find_equiv_reg to distinguish insns made by reload. */
631 reload_first_uid = get_max_uid ();
633 #ifdef SECONDARY_MEMORY_NEEDED
634 /* Initialize the secondary memory table. */
635 clear_secondary_mem ();
638 /* We don't have a stack slot for any spill reg yet. */
639 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
640 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
642 /* Initialize the save area information for caller-save, in case some
646 /* Compute which hard registers are now in use
647 as homes for pseudo registers.
648 This is done here rather than (eg) in global_alloc
649 because this point is reached even if not optimizing. */
650 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
653 /* A function that receives a nonlocal goto must save all call-saved
655 if (current_function_has_nonlocal_label)
656 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
658 if (! call_used_regs[i] && ! fixed_regs[i])
659 regs_ever_live[i] = 1;
662 /* Find all the pseudo registers that didn't get hard regs
663 but do have known equivalent constants or memory slots.
664 These include parameters (known equivalent to parameter slots)
665 and cse'd or loop-moved constant memory addresses.
667 Record constant equivalents in reg_equiv_constant
668 so they will be substituted by find_reloads.
669 Record memory equivalents in reg_mem_equiv so they can
670 be substituted eventually by altering the REG-rtx's. */
672 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
673 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
674 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
675 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
676 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
677 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
678 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
679 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
680 pseudo_forbidden_regs
681 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
683 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
685 CLEAR_HARD_REG_SET (bad_spill_regs_global);
687 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
688 Also find all paradoxical subregs and find largest such for each pseudo.
689 On machines with small register classes, record hard registers that
690 are used for user variables. These can never be used for spills.
691 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
692 caller-saved registers must be marked live. */
694 num_eliminable_invariants = 0;
695 for (insn = first; insn; insn = NEXT_INSN (insn))
697 rtx set = single_set (insn);
699 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
700 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
701 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
702 if (! call_used_regs[i])
703 regs_ever_live[i] = 1;
705 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
707 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
709 #ifdef LEGITIMATE_PIC_OPERAND_P
710 && (! function_invariant_p (XEXP (note, 0))
712 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
716 rtx x = XEXP (note, 0);
717 i = REGNO (SET_DEST (set));
718 if (i > LAST_VIRTUAL_REGISTER)
720 if (GET_CODE (x) == MEM)
722 /* If the operand is a PLUS, the MEM may be shared,
723 so make sure we have an unshared copy here. */
724 if (GET_CODE (XEXP (x, 0)) == PLUS)
727 reg_equiv_memory_loc[i] = x;
729 else if (function_invariant_p (x))
731 if (GET_CODE (x) == PLUS)
733 /* This is PLUS of frame pointer and a constant,
734 and might be shared. Unshare it. */
735 reg_equiv_constant[i] = copy_rtx (x);
736 num_eliminable_invariants++;
738 else if (x == frame_pointer_rtx
739 || x == arg_pointer_rtx)
741 reg_equiv_constant[i] = x;
742 num_eliminable_invariants++;
744 else if (LEGITIMATE_CONSTANT_P (x))
745 reg_equiv_constant[i] = x;
747 reg_equiv_memory_loc[i]
748 = force_const_mem (GET_MODE (SET_DEST (set)), x);
753 /* If this register is being made equivalent to a MEM
754 and the MEM is not SET_SRC, the equivalencing insn
755 is one with the MEM as a SET_DEST and it occurs later.
756 So don't mark this insn now. */
757 if (GET_CODE (x) != MEM
758 || rtx_equal_p (SET_SRC (set), x))
760 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
765 /* If this insn is setting a MEM from a register equivalent to it,
766 this is the equivalencing insn. */
767 else if (set && GET_CODE (SET_DEST (set)) == MEM
768 && GET_CODE (SET_SRC (set)) == REG
769 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
770 && rtx_equal_p (SET_DEST (set),
771 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
772 reg_equiv_init[REGNO (SET_SRC (set))]
773 = gen_rtx_INSN_LIST (VOIDmode, insn,
774 reg_equiv_init[REGNO (SET_SRC (set))]);
776 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
777 scan_paradoxical_subregs (PATTERN (insn));
782 num_labels = max_label_num () - get_first_label_num ();
784 /* Allocate the tables used to store offset information at labels. */
785 /* We used to use alloca here, but the size of what it would try to
786 allocate would occasionally cause it to exceed the stack limit and
787 cause a core dump. */
788 real_known_ptr = xmalloc (num_labels);
790 = (int (*)[NUM_ELIMINABLE_REGS])
791 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
793 offsets_known_at = real_known_ptr - get_first_label_num ();
795 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
797 /* Alter each pseudo-reg rtx to contain its hard reg number.
798 Assign stack slots to the pseudos that lack hard regs or equivalents.
799 Do not touch virtual registers. */
801 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
804 /* If we have some registers we think can be eliminated, scan all insns to
805 see if there is an insn that sets one of these registers to something
806 other than itself plus a constant. If so, the register cannot be
807 eliminated. Doing this scan here eliminates an extra pass through the
808 main reload loop in the most common case where register elimination
810 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
811 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
812 || GET_CODE (insn) == CALL_INSN)
813 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
815 maybe_fix_stack_asms ();
817 insns_need_reload = 0;
818 something_needs_elimination = 0;
820 /* Initialize to -1, which means take the first spill register. */
823 /* Spill any hard regs that we know we can't eliminate. */
824 CLEAR_HARD_REG_SET (used_spill_regs);
825 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
826 if (! ep->can_eliminate)
827 spill_hard_reg (ep->from, dumpfile, 1);
829 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
830 if (frame_pointer_needed)
831 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
833 finish_spills (global, dumpfile);
835 /* From now on, we may need to generate moves differently. We may also
836 allow modifications of insns which cause them to not be recognized.
837 Any such modifications will be cleaned up during reload itself. */
838 reload_in_progress = 1;
840 /* This loop scans the entire function each go-round
841 and repeats until one repetition spills no additional hard regs. */
844 int something_changed;
847 HOST_WIDE_INT starting_frame_size;
849 /* Round size of stack frame to stack_alignment_needed. This must be done
850 here because the stack size may be a part of the offset computation
851 for register elimination, and there might have been new stack slots
852 created in the last iteration of this loop. */
853 if (cfun->stack_alignment_needed)
854 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
856 starting_frame_size = get_frame_size ();
858 set_initial_elim_offsets ();
859 set_initial_label_offsets ();
861 /* For each pseudo register that has an equivalent location defined,
862 try to eliminate any eliminable registers (such as the frame pointer)
863 assuming initial offsets for the replacement register, which
866 If the resulting location is directly addressable, substitute
867 the MEM we just got directly for the old REG.
869 If it is not addressable but is a constant or the sum of a hard reg
870 and constant, it is probably not addressable because the constant is
871 out of range, in that case record the address; we will generate
872 hairy code to compute the address in a register each time it is
873 needed. Similarly if it is a hard register, but one that is not
874 valid as an address register.
876 If the location is not addressable, but does not have one of the
877 above forms, assign a stack slot. We have to do this to avoid the
878 potential of producing lots of reloads if, e.g., a location involves
879 a pseudo that didn't get a hard register and has an equivalent memory
880 location that also involves a pseudo that didn't get a hard register.
882 Perhaps at some point we will improve reload_when_needed handling
883 so this problem goes away. But that's very hairy. */
885 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
886 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
888 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
890 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
892 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
893 else if (CONSTANT_P (XEXP (x, 0))
894 || (GET_CODE (XEXP (x, 0)) == REG
895 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
896 || (GET_CODE (XEXP (x, 0)) == PLUS
897 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
898 && (REGNO (XEXP (XEXP (x, 0), 0))
899 < FIRST_PSEUDO_REGISTER)
900 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
901 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
904 /* Make a new stack slot. Then indicate that something
905 changed so we go back and recompute offsets for
906 eliminable registers because the allocation of memory
907 below might change some offset. reg_equiv_{mem,address}
908 will be set up for this pseudo on the next pass around
910 reg_equiv_memory_loc[i] = 0;
911 reg_equiv_init[i] = 0;
916 if (caller_save_needed)
919 /* If we allocated another stack slot, redo elimination bookkeeping. */
920 if (starting_frame_size != get_frame_size ())
923 if (caller_save_needed)
925 save_call_clobbered_regs ();
926 /* That might have allocated new insn_chain structures. */
927 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
930 calculate_needs_all_insns (global);
932 CLEAR_REG_SET (&spilled_pseudos);
935 something_changed = 0;
937 /* If we allocated any new memory locations, make another pass
938 since it might have changed elimination offsets. */
939 if (starting_frame_size != get_frame_size ())
940 something_changed = 1;
943 HARD_REG_SET to_spill;
944 CLEAR_HARD_REG_SET (to_spill);
945 update_eliminables (&to_spill);
946 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
947 if (TEST_HARD_REG_BIT (to_spill, i))
949 spill_hard_reg (i, dumpfile, 1);
952 /* Regardless of the state of spills, if we previously had
953 a register that we thought we could eliminate, but no can
954 not eliminate, we must run another pass.
956 Consider pseudos which have an entry in reg_equiv_* which
957 reference an eliminable register. We must make another pass
958 to update reg_equiv_* so that we do not substitute in the
959 old value from when we thought the elimination could be
961 something_changed = 1;
965 select_reload_regs (dumpfile);
969 if (insns_need_reload != 0 || did_spill)
970 something_changed |= finish_spills (global, dumpfile);
972 if (! something_changed)
975 if (caller_save_needed)
976 delete_caller_save_insns ();
978 obstack_free (&reload_obstack, reload_firstobj);
981 /* If global-alloc was run, notify it of any register eliminations we have
984 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
985 if (ep->can_eliminate)
986 mark_elimination (ep->from, ep->to);
988 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
989 If that insn didn't set the register (i.e., it copied the register to
990 memory), just delete that insn instead of the equivalencing insn plus
991 anything now dead. If we call delete_dead_insn on that insn, we may
992 delete the insn that actually sets the register if the register dies
993 there and that is incorrect. */
995 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
997 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1000 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1002 rtx equiv_insn = XEXP (list, 0);
1003 if (GET_CODE (equiv_insn) == NOTE)
1005 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1006 delete_dead_insn (equiv_insn);
1009 PUT_CODE (equiv_insn, NOTE);
1010 NOTE_SOURCE_FILE (equiv_insn) = 0;
1011 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1017 /* Use the reload registers where necessary
1018 by generating move instructions to move the must-be-register
1019 values into or out of the reload registers. */
1021 if (insns_need_reload != 0 || something_needs_elimination
1022 || something_needs_operands_changed)
1024 int old_frame_size = get_frame_size ();
1026 reload_as_needed (global);
1028 if (old_frame_size != get_frame_size ())
1032 verify_initial_elim_offsets ();
1035 /* If we were able to eliminate the frame pointer, show that it is no
1036 longer live at the start of any basic block. If it ls live by
1037 virtue of being in a pseudo, that pseudo will be marked live
1038 and hence the frame pointer will be known to be live via that
1041 if (! frame_pointer_needed)
1042 for (i = 0; i < n_basic_blocks; i++)
1043 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1044 HARD_FRAME_POINTER_REGNUM);
1046 /* Come here (with failure set nonzero) if we can't get enough spill regs
1047 and we decide not to abort about it. */
1050 CLEAR_REG_SET (&spilled_pseudos);
1051 reload_in_progress = 0;
1053 /* Now eliminate all pseudo regs by modifying them into
1054 their equivalent memory references.
1055 The REG-rtx's for the pseudos are modified in place,
1056 so all insns that used to refer to them now refer to memory.
1058 For a reg that has a reg_equiv_address, all those insns
1059 were changed by reloading so that no insns refer to it any longer;
1060 but the DECL_RTL of a variable decl may refer to it,
1061 and if so this causes the debugging info to mention the variable. */
1063 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1068 int is_readonly = 0;
1070 if (reg_equiv_memory_loc[i])
1072 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1073 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1074 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1077 if (reg_equiv_mem[i])
1078 addr = XEXP (reg_equiv_mem[i], 0);
1080 if (reg_equiv_address[i])
1081 addr = reg_equiv_address[i];
1085 if (reg_renumber[i] < 0)
1087 rtx reg = regno_reg_rtx[i];
1088 PUT_CODE (reg, MEM);
1089 XEXP (reg, 0) = addr;
1090 REG_USERVAR_P (reg) = 0;
1091 RTX_UNCHANGING_P (reg) = is_readonly;
1092 MEM_IN_STRUCT_P (reg) = in_struct;
1093 MEM_SCALAR_P (reg) = is_scalar;
1094 /* We have no alias information about this newly created
1096 MEM_ALIAS_SET (reg) = 0;
1098 else if (reg_equiv_mem[i])
1099 XEXP (reg_equiv_mem[i], 0) = addr;
1103 /* We must set reload_completed now since the cleanup_subreg_operands call
1104 below will re-recognize each insn and reload may have generated insns
1105 which are only valid during and after reload. */
1106 reload_completed = 1;
1108 /* Make a pass over all the insns and delete all USEs which we inserted
1109 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1110 notes. Delete all CLOBBER insns that don't refer to the return value
1111 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1112 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1113 and regenerate REG_INC notes that may have been moved around. */
1115 for (insn = first; insn; insn = NEXT_INSN (insn))
1116 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1120 if ((GET_CODE (PATTERN (insn)) == USE
1121 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1122 || (GET_CODE (PATTERN (insn)) == CLOBBER
1123 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1124 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1126 PUT_CODE (insn, NOTE);
1127 NOTE_SOURCE_FILE (insn) = 0;
1128 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1132 pnote = ®_NOTES (insn);
1135 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1136 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1137 || REG_NOTE_KIND (*pnote) == REG_INC
1138 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1139 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1140 *pnote = XEXP (*pnote, 1);
1142 pnote = &XEXP (*pnote, 1);
1146 add_auto_inc_notes (insn, PATTERN (insn));
1149 /* And simplify (subreg (reg)) if it appears as an operand. */
1150 cleanup_subreg_operands (insn);
1153 /* If we are doing stack checking, give a warning if this function's
1154 frame size is larger than we expect. */
1155 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1157 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1158 static int verbose_warned = 0;
1160 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1161 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1162 size += UNITS_PER_WORD;
1164 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1166 warning ("frame size too large for reliable stack checking");
1167 if (! verbose_warned)
1169 warning ("try reducing the number of local variables");
1175 /* Indicate that we no longer have known memory locations or constants. */
1176 if (reg_equiv_constant)
1177 free (reg_equiv_constant);
1178 reg_equiv_constant = 0;
1179 if (reg_equiv_memory_loc)
1180 free (reg_equiv_memory_loc);
1181 reg_equiv_memory_loc = 0;
1184 free (real_known_ptr);
1188 free (reg_equiv_mem);
1189 free (reg_equiv_init);
1190 free (reg_equiv_address);
1191 free (reg_max_ref_width);
1192 free (reg_old_renumber);
1193 free (pseudo_previous_regs);
1194 free (pseudo_forbidden_regs);
1196 CLEAR_HARD_REG_SET (used_spill_regs);
1197 for (i = 0; i < n_spills; i++)
1198 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1200 /* Free all the insn_chain structures at once. */
1201 obstack_free (&reload_obstack, reload_startobj);
1202 unused_insn_chains = 0;
1207 /* Yet another special case. Unfortunately, reg-stack forces people to
1208 write incorrect clobbers in asm statements. These clobbers must not
1209 cause the register to appear in bad_spill_regs, otherwise we'll call
1210 fatal_insn later. We clear the corresponding regnos in the live
1211 register sets to avoid this.
1212 The whole thing is rather sick, I'm afraid. */
1215 maybe_fix_stack_asms ()
1218 const char *constraints[MAX_RECOG_OPERANDS];
1219 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1220 struct insn_chain *chain;
1222 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1225 HARD_REG_SET clobbered, allowed;
1228 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1229 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1231 pat = PATTERN (chain->insn);
1232 if (GET_CODE (pat) != PARALLEL)
1235 CLEAR_HARD_REG_SET (clobbered);
1236 CLEAR_HARD_REG_SET (allowed);
1238 /* First, make a mask of all stack regs that are clobbered. */
1239 for (i = 0; i < XVECLEN (pat, 0); i++)
1241 rtx t = XVECEXP (pat, 0, i);
1242 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1243 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1246 /* Get the operand values and constraints out of the insn. */
1247 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1248 constraints, operand_mode);
1250 /* For every operand, see what registers are allowed. */
1251 for (i = 0; i < noperands; i++)
1253 const char *p = constraints[i];
1254 /* For every alternative, we compute the class of registers allowed
1255 for reloading in CLS, and merge its contents into the reg set
1257 int cls = (int) NO_REGS;
1263 if (c == '\0' || c == ',' || c == '#')
1265 /* End of one alternative - mark the regs in the current
1266 class, and reset the class. */
1267 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1272 } while (c != '\0' && c != ',');
1280 case '=': case '+': case '*': case '%': case '?': case '!':
1281 case '0': case '1': case '2': case '3': case '4': case 'm':
1282 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1283 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1284 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1286 #ifdef EXTRA_CONSTRAINT
1287 case 'Q': case 'R': case 'S': case 'T': case 'U':
1292 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1297 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1301 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1306 /* Those of the registers which are clobbered, but allowed by the
1307 constraints, must be usable as reload registers. So clear them
1308 out of the life information. */
1309 AND_HARD_REG_SET (allowed, clobbered);
1310 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1311 if (TEST_HARD_REG_BIT (allowed, i))
1313 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1314 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1321 /* Copy the global variables n_reloads and rld into the corresponding elts
1324 copy_reloads (chain)
1325 struct insn_chain *chain;
1327 chain->n_reloads = n_reloads;
1329 = (struct reload *) obstack_alloc (&reload_obstack,
1330 n_reloads * sizeof (struct reload));
1331 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1332 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1335 /* Walk the chain of insns, and determine for each whether it needs reloads
1336 and/or eliminations. Build the corresponding insns_need_reload list, and
1337 set something_needs_elimination as appropriate. */
1339 calculate_needs_all_insns (global)
1342 struct insn_chain **pprev_reload = &insns_need_reload;
1343 struct insn_chain *chain;
1345 something_needs_elimination = 0;
1347 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1348 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1350 rtx insn = chain->insn;
1352 /* Clear out the shortcuts. */
1353 chain->n_reloads = 0;
1354 chain->need_elim = 0;
1355 chain->need_reload = 0;
1356 chain->need_operand_change = 0;
1358 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1359 include REG_LABEL), we need to see what effects this has on the
1360 known offsets at labels. */
1362 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1363 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1364 && REG_NOTES (insn) != 0))
1365 set_label_offsets (insn, insn, 0);
1367 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1369 rtx old_body = PATTERN (insn);
1370 int old_code = INSN_CODE (insn);
1371 rtx old_notes = REG_NOTES (insn);
1372 int did_elimination = 0;
1373 int operands_changed = 0;
1374 rtx set = single_set (insn);
1376 /* Skip insns that only set an equivalence. */
1377 if (set && GET_CODE (SET_DEST (set)) == REG
1378 && reg_renumber[REGNO (SET_DEST (set))] < 0
1379 && reg_equiv_constant[REGNO (SET_DEST (set))])
1382 /* If needed, eliminate any eliminable registers. */
1383 if (num_eliminable || num_eliminable_invariants)
1384 did_elimination = eliminate_regs_in_insn (insn, 0);
1386 /* Analyze the instruction. */
1387 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1388 global, spill_reg_order);
1390 /* If a no-op set needs more than one reload, this is likely
1391 to be something that needs input address reloads. We
1392 can't get rid of this cleanly later, and it is of no use
1393 anyway, so discard it now.
1394 We only do this when expensive_optimizations is enabled,
1395 since this complements reload inheritance / output
1396 reload deletion, and it can make debugging harder. */
1397 if (flag_expensive_optimizations && n_reloads > 1)
1399 rtx set = single_set (insn);
1401 && SET_SRC (set) == SET_DEST (set)
1402 && GET_CODE (SET_SRC (set)) == REG
1403 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1405 PUT_CODE (insn, NOTE);
1406 NOTE_SOURCE_FILE (insn) = 0;
1407 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1412 update_eliminable_offsets ();
1414 /* Remember for later shortcuts which insns had any reloads or
1415 register eliminations. */
1416 chain->need_elim = did_elimination;
1417 chain->need_reload = n_reloads > 0;
1418 chain->need_operand_change = operands_changed;
1420 /* Discard any register replacements done. */
1421 if (did_elimination)
1423 obstack_free (&reload_obstack, reload_insn_firstobj);
1424 PATTERN (insn) = old_body;
1425 INSN_CODE (insn) = old_code;
1426 REG_NOTES (insn) = old_notes;
1427 something_needs_elimination = 1;
1430 something_needs_operands_changed |= operands_changed;
1434 copy_reloads (chain);
1435 *pprev_reload = chain;
1436 pprev_reload = &chain->next_need_reload;
1443 /* Comparison function for qsort to decide which of two reloads
1444 should be handled first. *P1 and *P2 are the reload numbers. */
1447 reload_reg_class_lower (r1p, r2p)
1451 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
1454 /* Consider required reloads before optional ones. */
1455 t = rld[r1].optional - rld[r2].optional;
1459 /* Count all solitary classes before non-solitary ones. */
1460 t = ((reg_class_size[(int) rld[r2].class] == 1)
1461 - (reg_class_size[(int) rld[r1].class] == 1));
1465 /* Aside from solitaires, consider all multi-reg groups first. */
1466 t = rld[r2].nregs - rld[r1].nregs;
1470 /* Consider reloads in order of increasing reg-class number. */
1471 t = (int) rld[r1].class - (int) rld[r2].class;
1475 /* If reloads are equally urgent, sort by reload number,
1476 so that the results of qsort leave nothing to chance. */
1480 /* The cost of spilling each hard reg. */
1481 static int spill_cost[FIRST_PSEUDO_REGISTER];
1483 /* When spilling multiple hard registers, we use SPILL_COST for the first
1484 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1485 only the first hard reg for a multi-reg pseudo. */
1486 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1488 /* Update the spill cost arrays, considering that pseudo REG is live. */
1494 int n_refs = REG_N_REFS (reg);
1495 int r = reg_renumber[reg];
1498 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1499 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1502 SET_REGNO_REG_SET (&pseudos_counted, reg);
1507 spill_add_cost[r] += n_refs;
1509 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1511 spill_cost[r + nregs] += n_refs;
1514 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1515 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1518 order_regs_for_reload (chain)
1519 struct insn_chain *chain;
1522 HARD_REG_SET used_by_pseudos;
1523 HARD_REG_SET used_by_pseudos2;
1525 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1527 memset (spill_cost, 0, sizeof spill_cost);
1528 memset (spill_add_cost, 0, sizeof spill_add_cost);
1530 /* Count number of uses of each hard reg by pseudo regs allocated to it
1531 and then order them by decreasing use. First exclude hard registers
1532 that are live in or across this insn. */
1534 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1535 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1536 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1537 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1539 /* Now find out which pseudos are allocated to it, and update
1541 CLEAR_REG_SET (&pseudos_counted);
1543 EXECUTE_IF_SET_IN_REG_SET
1544 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1548 EXECUTE_IF_SET_IN_REG_SET
1549 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1553 CLEAR_REG_SET (&pseudos_counted);
1556 /* Vector of reload-numbers showing the order in which the reloads should
1558 static short reload_order[MAX_RELOADS];
1560 /* This is used to keep track of the spill regs used in one insn. */
1561 static HARD_REG_SET used_spill_regs_local;
1563 /* We decided to spill hard register SPILLED, which has a size of
1564 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1565 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1566 update SPILL_COST/SPILL_ADD_COST. */
1569 count_spilled_pseudo (spilled, spilled_nregs, reg)
1570 int spilled, spilled_nregs, reg;
1572 int r = reg_renumber[reg];
1573 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1575 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1576 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1579 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1581 spill_add_cost[r] -= REG_N_REFS (reg);
1583 spill_cost[r + nregs] -= REG_N_REFS (reg);
1586 /* Find reload register to use for reload number ORDER. */
1589 find_reg (chain, order, dumpfile)
1590 struct insn_chain *chain;
1594 int rnum = reload_order[order];
1595 struct reload *rl = rld + rnum;
1596 int best_cost = INT_MAX;
1600 HARD_REG_SET not_usable;
1601 HARD_REG_SET used_by_other_reload;
1603 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1604 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1605 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1607 CLEAR_HARD_REG_SET (used_by_other_reload);
1608 for (k = 0; k < order; k++)
1610 int other = reload_order[k];
1612 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1613 for (j = 0; j < rld[other].nregs; j++)
1614 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1617 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1619 unsigned int regno = i;
1621 if (! TEST_HARD_REG_BIT (not_usable, regno)
1622 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1623 && HARD_REGNO_MODE_OK (regno, rl->mode))
1625 int this_cost = spill_cost[regno];
1627 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1629 for (j = 1; j < this_nregs; j++)
1631 this_cost += spill_add_cost[regno + j];
1632 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1633 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1638 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1640 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1642 if (this_cost < best_cost
1643 /* Among registers with equal cost, prefer caller-saved ones, or
1644 use REG_ALLOC_ORDER if it is defined. */
1645 || (this_cost == best_cost
1646 #ifdef REG_ALLOC_ORDER
1647 && (inv_reg_alloc_order[regno]
1648 < inv_reg_alloc_order[best_reg])
1650 && call_used_regs[regno]
1651 && ! call_used_regs[best_reg]
1656 best_cost = this_cost;
1664 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1666 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1667 rl->regno = best_reg;
1669 EXECUTE_IF_SET_IN_REG_SET
1670 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1672 count_spilled_pseudo (best_reg, rl->nregs, j);
1675 EXECUTE_IF_SET_IN_REG_SET
1676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1678 count_spilled_pseudo (best_reg, rl->nregs, j);
1681 for (i = 0; i < rl->nregs; i++)
1683 if (spill_cost[best_reg + i] != 0
1684 || spill_add_cost[best_reg + i] != 0)
1686 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1691 /* Find more reload regs to satisfy the remaining need of an insn, which
1693 Do it by ascending class number, since otherwise a reg
1694 might be spilled for a big class and might fail to count
1695 for a smaller class even though it belongs to that class. */
1698 find_reload_regs (chain, dumpfile)
1699 struct insn_chain *chain;
1704 /* In order to be certain of getting the registers we need,
1705 we must sort the reloads into order of increasing register class.
1706 Then our grabbing of reload registers will parallel the process
1707 that provided the reload registers. */
1708 for (i = 0; i < chain->n_reloads; i++)
1710 /* Show whether this reload already has a hard reg. */
1711 if (chain->rld[i].reg_rtx)
1713 int regno = REGNO (chain->rld[i].reg_rtx);
1714 chain->rld[i].regno = regno;
1716 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1719 chain->rld[i].regno = -1;
1720 reload_order[i] = i;
1723 n_reloads = chain->n_reloads;
1724 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1726 CLEAR_HARD_REG_SET (used_spill_regs_local);
1729 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1731 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1733 /* Compute the order of preference for hard registers to spill. */
1735 order_regs_for_reload (chain);
1737 for (i = 0; i < n_reloads; i++)
1739 int r = reload_order[i];
1741 /* Ignore reloads that got marked inoperative. */
1742 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1743 && ! rld[r].optional
1744 && rld[r].regno == -1)
1745 if (! find_reg (chain, i, dumpfile))
1747 spill_failure (chain->insn, rld[r].class);
1753 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1754 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1756 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1760 select_reload_regs (dumpfile)
1763 struct insn_chain *chain;
1765 /* Try to satisfy the needs for each insn. */
1766 for (chain = insns_need_reload; chain != 0;
1767 chain = chain->next_need_reload)
1768 find_reload_regs (chain, dumpfile);
1771 /* Delete all insns that were inserted by emit_caller_save_insns during
1774 delete_caller_save_insns ()
1776 struct insn_chain *c = reload_insn_chain;
1780 while (c != 0 && c->is_caller_save_insn)
1782 struct insn_chain *next = c->next;
1785 if (insn == BLOCK_HEAD (c->block))
1786 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1787 if (insn == BLOCK_END (c->block))
1788 BLOCK_END (c->block) = PREV_INSN (insn);
1789 if (c == reload_insn_chain)
1790 reload_insn_chain = next;
1792 if (NEXT_INSN (insn) != 0)
1793 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1794 if (PREV_INSN (insn) != 0)
1795 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1798 next->prev = c->prev;
1800 c->prev->next = next;
1801 c->next = unused_insn_chains;
1802 unused_insn_chains = c;
1810 /* Handle the failure to find a register to spill.
1811 INSN should be one of the insns which needed this particular spill reg. */
1814 spill_failure (insn, class)
1816 enum reg_class class;
1818 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1819 if (asm_noperands (PATTERN (insn)) >= 0)
1820 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1821 reg_class_names[class]);
1824 error ("Unable to find a register to spill in class `%s'.",
1825 reg_class_names[class]);
1826 fatal_insn ("This is the insn:", insn);
1830 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1831 data that is dead in INSN. */
1834 delete_dead_insn (insn)
1837 rtx prev = prev_real_insn (insn);
1840 /* If the previous insn sets a register that dies in our insn, delete it
1842 if (prev && GET_CODE (PATTERN (prev)) == SET
1843 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1844 && reg_mentioned_p (prev_dest, PATTERN (insn))
1845 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1846 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1847 delete_dead_insn (prev);
1849 PUT_CODE (insn, NOTE);
1850 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1851 NOTE_SOURCE_FILE (insn) = 0;
1854 /* Modify the home of pseudo-reg I.
1855 The new home is present in reg_renumber[I].
1857 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1858 or it may be -1, meaning there is none or it is not relevant.
1859 This is used so that all pseudos spilled from a given hard reg
1860 can share one stack slot. */
1863 alter_reg (i, from_reg)
1867 /* When outputting an inline function, this can happen
1868 for a reg that isn't actually used. */
1869 if (regno_reg_rtx[i] == 0)
1872 /* If the reg got changed to a MEM at rtl-generation time,
1874 if (GET_CODE (regno_reg_rtx[i]) != REG)
1877 /* Modify the reg-rtx to contain the new hard reg
1878 number or else to contain its pseudo reg number. */
1879 REGNO (regno_reg_rtx[i])
1880 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1882 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1883 allocate a stack slot for it. */
1885 if (reg_renumber[i] < 0
1886 && REG_N_REFS (i) > 0
1887 && reg_equiv_constant[i] == 0
1888 && reg_equiv_memory_loc[i] == 0)
1891 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1892 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1895 /* Each pseudo reg has an inherent size which comes from its own mode,
1896 and a total size which provides room for paradoxical subregs
1897 which refer to the pseudo reg in wider modes.
1899 We can use a slot already allocated if it provides both
1900 enough inherent space and enough total space.
1901 Otherwise, we allocate a new slot, making sure that it has no less
1902 inherent space, and no less total space, then the previous slot. */
1905 /* No known place to spill from => no slot to reuse. */
1906 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1907 inherent_size == total_size ? 0 : -1);
1908 if (BYTES_BIG_ENDIAN)
1909 /* Cancel the big-endian correction done in assign_stack_local.
1910 Get the address of the beginning of the slot.
1911 This is so we can do a big-endian correction unconditionally
1913 adjust = inherent_size - total_size;
1915 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1917 /* Reuse a stack slot if possible. */
1918 else if (spill_stack_slot[from_reg] != 0
1919 && spill_stack_slot_width[from_reg] >= total_size
1920 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1922 x = spill_stack_slot[from_reg];
1923 /* Allocate a bigger slot. */
1926 /* Compute maximum size needed, both for inherent size
1927 and for total size. */
1928 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1930 if (spill_stack_slot[from_reg])
1932 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1934 mode = GET_MODE (spill_stack_slot[from_reg]);
1935 if (spill_stack_slot_width[from_reg] > total_size)
1936 total_size = spill_stack_slot_width[from_reg];
1938 /* Make a slot with that size. */
1939 x = assign_stack_local (mode, total_size,
1940 inherent_size == total_size ? 0 : -1);
1942 if (BYTES_BIG_ENDIAN)
1944 /* Cancel the big-endian correction done in assign_stack_local.
1945 Get the address of the beginning of the slot.
1946 This is so we can do a big-endian correction unconditionally
1948 adjust = GET_MODE_SIZE (mode) - total_size;
1950 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1953 plus_constant (XEXP (x, 0), adjust));
1955 spill_stack_slot[from_reg] = stack_slot;
1956 spill_stack_slot_width[from_reg] = total_size;
1959 /* On a big endian machine, the "address" of the slot
1960 is the address of the low part that fits its inherent mode. */
1961 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1962 adjust += (total_size - inherent_size);
1964 /* If we have any adjustment to make, or if the stack slot is the
1965 wrong mode, make a new stack slot. */
1966 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1968 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1969 plus_constant (XEXP (x, 0), adjust));
1971 /* If this was shared among registers, must ensure we never
1972 set it readonly since that can cause scheduling
1973 problems. Note we would only have in this adjustment
1974 case in any event, since the code above doesn't set it. */
1977 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1980 /* Save the stack slot for later. */
1981 reg_equiv_memory_loc[i] = x;
1985 /* Mark the slots in regs_ever_live for the hard regs
1986 used by pseudo-reg number REGNO. */
1989 mark_home_live (regno)
1992 register int i, lim;
1994 i = reg_renumber[regno];
1997 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1999 regs_ever_live[i++] = 1;
2002 /* This function handles the tracking of elimination offsets around branches.
2004 X is a piece of RTL being scanned.
2006 INSN is the insn that it came from, if any.
2008 INITIAL_P is non-zero if we are to set the offset to be the initial
2009 offset and zero if we are setting the offset of the label to be the
2013 set_label_offsets (x, insn, initial_p)
2018 enum rtx_code code = GET_CODE (x);
2021 struct elim_table *p;
2026 if (LABEL_REF_NONLOCAL_P (x))
2031 /* ... fall through ... */
2034 /* If we know nothing about this label, set the desired offsets. Note
2035 that this sets the offset at a label to be the offset before a label
2036 if we don't know anything about the label. This is not correct for
2037 the label after a BARRIER, but is the best guess we can make. If
2038 we guessed wrong, we will suppress an elimination that might have
2039 been possible had we been able to guess correctly. */
2041 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2043 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2044 offsets_at[CODE_LABEL_NUMBER (x)][i]
2045 = (initial_p ? reg_eliminate[i].initial_offset
2046 : reg_eliminate[i].offset);
2047 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2050 /* Otherwise, if this is the definition of a label and it is
2051 preceded by a BARRIER, set our offsets to the known offset of
2055 && (tem = prev_nonnote_insn (insn)) != 0
2056 && GET_CODE (tem) == BARRIER)
2057 set_offsets_for_label (insn);
2059 /* If neither of the above cases is true, compare each offset
2060 with those previously recorded and suppress any eliminations
2061 where the offsets disagree. */
2063 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2064 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2065 != (initial_p ? reg_eliminate[i].initial_offset
2066 : reg_eliminate[i].offset))
2067 reg_eliminate[i].can_eliminate = 0;
2072 set_label_offsets (PATTERN (insn), insn, initial_p);
2074 /* ... fall through ... */
2078 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2079 and hence must have all eliminations at their initial offsets. */
2080 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2081 if (REG_NOTE_KIND (tem) == REG_LABEL)
2082 set_label_offsets (XEXP (tem, 0), insn, 1);
2087 /* Each of the labels in the address vector must be at their initial
2088 offsets. We want the first field for ADDR_VEC and the second
2089 field for ADDR_DIFF_VEC. */
2091 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2092 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2097 /* We only care about setting PC. If the source is not RETURN,
2098 IF_THEN_ELSE, or a label, disable any eliminations not at
2099 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2100 isn't one of those possibilities. For branches to a label,
2101 call ourselves recursively.
2103 Note that this can disable elimination unnecessarily when we have
2104 a non-local goto since it will look like a non-constant jump to
2105 someplace in the current function. This isn't a significant
2106 problem since such jumps will normally be when all elimination
2107 pairs are back to their initial offsets. */
2109 if (SET_DEST (x) != pc_rtx)
2112 switch (GET_CODE (SET_SRC (x)))
2119 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2123 tem = XEXP (SET_SRC (x), 1);
2124 if (GET_CODE (tem) == LABEL_REF)
2125 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2126 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2129 tem = XEXP (SET_SRC (x), 2);
2130 if (GET_CODE (tem) == LABEL_REF)
2131 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2132 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2140 /* If we reach here, all eliminations must be at their initial
2141 offset because we are doing a jump to a variable address. */
2142 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2143 if (p->offset != p->initial_offset)
2144 p->can_eliminate = 0;
2152 /* Scan X and replace any eliminable registers (such as fp) with a
2153 replacement (such as sp), plus an offset.
2155 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2156 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2157 MEM, we are allowed to replace a sum of a register and the constant zero
2158 with the register, which we cannot do outside a MEM. In addition, we need
2159 to record the fact that a register is referenced outside a MEM.
2161 If INSN is an insn, it is the insn containing X. If we replace a REG
2162 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2163 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2164 the REG is being modified.
2166 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2167 That's used when we eliminate in expressions stored in notes.
2168 This means, do not set ref_outside_mem even if the reference
2171 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2172 replacements done assuming all offsets are at their initial values. If
2173 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2174 encounter, return the actual location so that find_reloads will do
2175 the proper thing. */
2178 eliminate_regs (x, mem_mode, insn)
2180 enum machine_mode mem_mode;
2183 enum rtx_code code = GET_CODE (x);
2184 struct elim_table *ep;
2191 if (! current_function_decl)
2210 /* This is only for the benefit of the debugging backends, which call
2211 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2212 removed after CSE. */
2213 new = eliminate_regs (XEXP (x, 0), 0, insn);
2214 if (GET_CODE (new) == MEM)
2215 return XEXP (new, 0);
2221 /* First handle the case where we encounter a bare register that
2222 is eliminable. Replace it with a PLUS. */
2223 if (regno < FIRST_PSEUDO_REGISTER)
2225 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2227 if (ep->from_rtx == x && ep->can_eliminate)
2228 return plus_constant (ep->to_rtx, ep->previous_offset);
2231 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2232 && reg_equiv_constant[regno]
2233 && ! CONSTANT_P (reg_equiv_constant[regno]))
2234 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2238 /* You might think handling MINUS in a manner similar to PLUS is a
2239 good idea. It is not. It has been tried multiple times and every
2240 time the change has had to have been reverted.
2242 Other parts of reload know a PLUS is special (gen_reload for example)
2243 and require special code to handle code a reloaded PLUS operand.
2245 Also consider backends where the flags register is clobbered by a
2246 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2247 lea instruction comes to mind). If we try to reload a MINUS, we
2248 may kill the flags register that was holding a useful value.
2250 So, please before trying to handle MINUS, consider reload as a
2251 whole instead of this little section as well as the backend issues. */
2253 /* If this is the sum of an eliminable register and a constant, rework
2255 if (GET_CODE (XEXP (x, 0)) == REG
2256 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2257 && CONSTANT_P (XEXP (x, 1)))
2259 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2261 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2263 /* The only time we want to replace a PLUS with a REG (this
2264 occurs when the constant operand of the PLUS is the negative
2265 of the offset) is when we are inside a MEM. We won't want
2266 to do so at other times because that would change the
2267 structure of the insn in a way that reload can't handle.
2268 We special-case the commonest situation in
2269 eliminate_regs_in_insn, so just replace a PLUS with a
2270 PLUS here, unless inside a MEM. */
2271 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2272 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2275 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2276 plus_constant (XEXP (x, 1),
2277 ep->previous_offset));
2280 /* If the register is not eliminable, we are done since the other
2281 operand is a constant. */
2285 /* If this is part of an address, we want to bring any constant to the
2286 outermost PLUS. We will do this by doing register replacement in
2287 our operands and seeing if a constant shows up in one of them.
2289 Note that there is no risk of modifying the structure of the insn,
2290 since we only get called for its operands, thus we are either
2291 modifying the address inside a MEM, or something like an address
2292 operand of a load-address insn. */
2295 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2296 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2298 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2300 /* If one side is a PLUS and the other side is a pseudo that
2301 didn't get a hard register but has a reg_equiv_constant,
2302 we must replace the constant here since it may no longer
2303 be in the position of any operand. */
2304 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2305 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2306 && reg_renumber[REGNO (new1)] < 0
2307 && reg_equiv_constant != 0
2308 && reg_equiv_constant[REGNO (new1)] != 0)
2309 new1 = reg_equiv_constant[REGNO (new1)];
2310 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2311 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2312 && reg_renumber[REGNO (new0)] < 0
2313 && reg_equiv_constant[REGNO (new0)] != 0)
2314 new0 = reg_equiv_constant[REGNO (new0)];
2316 new = form_sum (new0, new1);
2318 /* As above, if we are not inside a MEM we do not want to
2319 turn a PLUS into something else. We might try to do so here
2320 for an addition of 0 if we aren't optimizing. */
2321 if (! mem_mode && GET_CODE (new) != PLUS)
2322 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2330 /* If this is the product of an eliminable register and a
2331 constant, apply the distribute law and move the constant out
2332 so that we have (plus (mult ..) ..). This is needed in order
2333 to keep load-address insns valid. This case is pathological.
2334 We ignore the possibility of overflow here. */
2335 if (GET_CODE (XEXP (x, 0)) == REG
2336 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2337 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2338 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2340 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2343 /* Refs inside notes don't count for this purpose. */
2344 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2345 || GET_CODE (insn) == INSN_LIST)))
2346 ep->ref_outside_mem = 1;
2349 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2350 ep->previous_offset * INTVAL (XEXP (x, 1)));
2353 /* ... fall through ... */
2357 /* See comments before PLUS about handling MINUS. */
2359 case DIV: case UDIV:
2360 case MOD: case UMOD:
2361 case AND: case IOR: case XOR:
2362 case ROTATERT: case ROTATE:
2363 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2365 case GE: case GT: case GEU: case GTU:
2366 case LE: case LT: case LEU: case LTU:
2368 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2370 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2372 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2373 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2378 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2381 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2382 if (new != XEXP (x, 0))
2384 /* If this is a REG_DEAD note, it is not valid anymore.
2385 Using the eliminated version could result in creating a
2386 REG_DEAD note for the stack or frame pointer. */
2387 if (GET_MODE (x) == REG_DEAD)
2389 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2392 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2396 /* ... fall through ... */
2399 /* Now do eliminations in the rest of the chain. If this was
2400 an EXPR_LIST, this might result in allocating more memory than is
2401 strictly needed, but it simplifies the code. */
2404 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2405 if (new != XEXP (x, 1))
2406 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2414 case STRICT_LOW_PART:
2416 case SIGN_EXTEND: case ZERO_EXTEND:
2417 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2418 case FLOAT: case FIX:
2419 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2423 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2424 if (new != XEXP (x, 0))
2425 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2429 /* Similar to above processing, but preserve SUBREG_WORD.
2430 Convert (subreg (mem)) to (mem) if not paradoxical.
2431 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2432 pseudo didn't get a hard reg, we must replace this with the
2433 eliminated version of the memory location because push_reloads
2434 may do the replacement in certain circumstances. */
2435 if (GET_CODE (SUBREG_REG (x)) == REG
2436 && (GET_MODE_SIZE (GET_MODE (x))
2437 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2438 && reg_equiv_memory_loc != 0
2439 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2441 new = SUBREG_REG (x);
2444 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2446 if (new != XEXP (x, 0))
2448 int x_size = GET_MODE_SIZE (GET_MODE (x));
2449 int new_size = GET_MODE_SIZE (GET_MODE (new));
2451 if (GET_CODE (new) == MEM
2452 && ((x_size < new_size
2453 #ifdef WORD_REGISTER_OPERATIONS
2454 /* On these machines, combine can create rtl of the form
2455 (set (subreg:m1 (reg:m2 R) 0) ...)
2456 where m1 < m2, and expects something interesting to
2457 happen to the entire word. Moreover, it will use the
2458 (reg:m2 R) later, expecting all bits to be preserved.
2459 So if the number of words is the same, preserve the
2460 subreg so that push_reloads can see it. */
2461 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2464 || (x_size == new_size))
2467 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2468 enum machine_mode mode = GET_MODE (x);
2470 if (BYTES_BIG_ENDIAN)
2471 offset += (MIN (UNITS_PER_WORD,
2472 GET_MODE_SIZE (GET_MODE (new)))
2473 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2475 PUT_MODE (new, mode);
2476 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2480 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2486 /* This is only for the benefit of the debugging backends, which call
2487 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2488 removed after CSE. */
2489 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2490 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2492 /* Our only special processing is to pass the mode of the MEM to our
2493 recursive call and copy the flags. While we are here, handle this
2494 case more efficiently. */
2495 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2496 if (new != XEXP (x, 0))
2498 new = gen_rtx_MEM (GET_MODE (x), new);
2499 new->volatil = x->volatil;
2500 new->unchanging = x->unchanging;
2501 new->in_struct = x->in_struct;
2517 /* Process each of our operands recursively. If any have changed, make a
2519 fmt = GET_RTX_FORMAT (code);
2520 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2524 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2525 if (new != XEXP (x, i) && ! copied)
2527 rtx new_x = rtx_alloc (code);
2528 bcopy ((char *) x, (char *) new_x,
2529 (sizeof (*new_x) - sizeof (new_x->fld)
2530 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2536 else if (*fmt == 'E')
2539 for (j = 0; j < XVECLEN (x, i); j++)
2541 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2542 if (new != XVECEXP (x, i, j) && ! copied_vec)
2544 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2548 rtx new_x = rtx_alloc (code);
2549 bcopy ((char *) x, (char *) new_x,
2550 (sizeof (*new_x) - sizeof (new_x->fld)
2551 + (sizeof (new_x->fld[0])
2552 * GET_RTX_LENGTH (code))));
2556 XVEC (x, i) = new_v;
2559 XVECEXP (x, i, j) = new;
2567 /* Scan rtx X for modifications of elimination target registers. Update
2568 the table of eliminables to reflect the changed state. MEM_MODE is
2569 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2572 elimination_effects (x, mem_mode)
2574 enum machine_mode mem_mode;
2577 enum rtx_code code = GET_CODE (x);
2578 struct elim_table *ep;
2604 /* First handle the case where we encounter a bare register that
2605 is eliminable. Replace it with a PLUS. */
2606 if (regno < FIRST_PSEUDO_REGISTER)
2608 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2610 if (ep->from_rtx == x && ep->can_eliminate)
2613 ep->ref_outside_mem = 1;
2618 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2619 && reg_equiv_constant[regno]
2620 && ! CONSTANT_P (reg_equiv_constant[regno]))
2621 elimination_effects (reg_equiv_constant[regno], mem_mode);
2628 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2629 if (ep->to_rtx == XEXP (x, 0))
2631 int size = GET_MODE_SIZE (mem_mode);
2633 /* If more bytes than MEM_MODE are pushed, account for them. */
2634 #ifdef PUSH_ROUNDING
2635 if (ep->to_rtx == stack_pointer_rtx)
2636 size = PUSH_ROUNDING (size);
2638 if (code == PRE_DEC || code == POST_DEC)
2644 /* Fall through to generic unary operation case. */
2645 case STRICT_LOW_PART:
2647 case SIGN_EXTEND: case ZERO_EXTEND:
2648 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2649 case FLOAT: case FIX:
2650 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2654 elimination_effects (XEXP (x, 0), mem_mode);
2658 if (GET_CODE (SUBREG_REG (x)) == REG
2659 && (GET_MODE_SIZE (GET_MODE (x))
2660 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2661 && reg_equiv_memory_loc != 0
2662 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2665 elimination_effects (SUBREG_REG (x), mem_mode);
2669 /* If using a register that is the source of an eliminate we still
2670 think can be performed, note it cannot be performed since we don't
2671 know how this register is used. */
2672 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2673 if (ep->from_rtx == XEXP (x, 0))
2674 ep->can_eliminate = 0;
2676 elimination_effects (XEXP (x, 0), mem_mode);
2680 /* If clobbering a register that is the replacement register for an
2681 elimination we still think can be performed, note that it cannot
2682 be performed. Otherwise, we need not be concerned about it. */
2683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2684 if (ep->to_rtx == XEXP (x, 0))
2685 ep->can_eliminate = 0;
2687 elimination_effects (XEXP (x, 0), mem_mode);
2691 /* Check for setting a register that we know about. */
2692 if (GET_CODE (SET_DEST (x)) == REG)
2694 /* See if this is setting the replacement register for an
2697 If DEST is the hard frame pointer, we do nothing because we
2698 assume that all assignments to the frame pointer are for
2699 non-local gotos and are being done at a time when they are valid
2700 and do not disturb anything else. Some machines want to
2701 eliminate a fake argument pointer (or even a fake frame pointer)
2702 with either the real frame or the stack pointer. Assignments to
2703 the hard frame pointer must not prevent this elimination. */
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2707 if (ep->to_rtx == SET_DEST (x)
2708 && SET_DEST (x) != hard_frame_pointer_rtx)
2710 /* If it is being incremented, adjust the offset. Otherwise,
2711 this elimination can't be done. */
2712 rtx src = SET_SRC (x);
2714 if (GET_CODE (src) == PLUS
2715 && XEXP (src, 0) == SET_DEST (x)
2716 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2717 ep->offset -= INTVAL (XEXP (src, 1));
2719 ep->can_eliminate = 0;
2723 elimination_effects (SET_DEST (x), 0);
2724 elimination_effects (SET_SRC (x), 0);
2728 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2731 /* Our only special processing is to pass the mode of the MEM to our
2733 elimination_effects (XEXP (x, 0), GET_MODE (x));
2740 fmt = GET_RTX_FORMAT (code);
2741 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2744 elimination_effects (XEXP (x, i), mem_mode);
2745 else if (*fmt == 'E')
2746 for (j = 0; j < XVECLEN (x, i); j++)
2747 elimination_effects (XVECEXP (x, i, j), mem_mode);
2751 /* Descend through rtx X and verify that no references to eliminable registers
2752 remain. If any do remain, mark the involved register as not
2756 check_eliminable_occurrences (x)
2766 code = GET_CODE (x);
2768 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2770 struct elim_table *ep;
2772 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2773 if (ep->from_rtx == x && ep->can_eliminate)
2774 ep->can_eliminate = 0;
2778 fmt = GET_RTX_FORMAT (code);
2779 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2782 check_eliminable_occurrences (XEXP (x, i));
2783 else if (*fmt == 'E')
2786 for (j = 0; j < XVECLEN (x, i); j++)
2787 check_eliminable_occurrences (XVECEXP (x, i, j));
2792 /* Scan INSN and eliminate all eliminable registers in it.
2794 If REPLACE is nonzero, do the replacement destructively. Also
2795 delete the insn as dead it if it is setting an eliminable register.
2797 If REPLACE is zero, do all our allocations in reload_obstack.
2799 If no eliminations were done and this insn doesn't require any elimination
2800 processing (these are not identical conditions: it might be updating sp,
2801 but not referencing fp; this needs to be seen during reload_as_needed so
2802 that the offset between fp and sp can be taken into consideration), zero
2803 is returned. Otherwise, 1 is returned. */
2806 eliminate_regs_in_insn (insn, replace)
2810 int icode = recog_memoized (insn);
2811 rtx old_body = PATTERN (insn);
2812 int insn_is_asm = asm_noperands (old_body) >= 0;
2813 rtx old_set = single_set (insn);
2817 rtx substed_operand[MAX_RECOG_OPERANDS];
2818 rtx orig_operand[MAX_RECOG_OPERANDS];
2819 struct elim_table *ep;
2821 if (! insn_is_asm && icode < 0)
2823 if (GET_CODE (PATTERN (insn)) == USE
2824 || GET_CODE (PATTERN (insn)) == CLOBBER
2825 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2826 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2827 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2833 push_obstacks (&reload_obstack, &reload_obstack);
2835 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2836 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2838 /* Check for setting an eliminable register. */
2839 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2840 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2842 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2843 /* If this is setting the frame pointer register to the
2844 hardware frame pointer register and this is an elimination
2845 that will be done (tested above), this insn is really
2846 adjusting the frame pointer downward to compensate for
2847 the adjustment done before a nonlocal goto. */
2848 if (ep->from == FRAME_POINTER_REGNUM
2849 && ep->to == HARD_FRAME_POINTER_REGNUM)
2851 rtx src = SET_SRC (old_set);
2852 int offset = 0, ok = 0;
2853 rtx prev_insn, prev_set;
2855 if (src == ep->to_rtx)
2857 else if (GET_CODE (src) == PLUS
2858 && GET_CODE (XEXP (src, 0)) == CONST_INT
2859 && XEXP (src, 1) == ep->to_rtx)
2860 offset = INTVAL (XEXP (src, 0)), ok = 1;
2861 else if (GET_CODE (src) == PLUS
2862 && GET_CODE (XEXP (src, 1)) == CONST_INT
2863 && XEXP (src, 0) == ep->to_rtx)
2864 offset = INTVAL (XEXP (src, 1)), ok = 1;
2865 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2866 && (prev_set = single_set (prev_insn)) != 0
2867 && rtx_equal_p (SET_DEST (prev_set), src))
2869 src = SET_SRC (prev_set);
2870 if (src == ep->to_rtx)
2872 else if (GET_CODE (src) == PLUS
2873 && GET_CODE (XEXP (src, 0)) == CONST_INT
2874 && XEXP (src, 1) == ep->to_rtx)
2875 offset = INTVAL (XEXP (src, 0)), ok = 1;
2876 else if (GET_CODE (src) == PLUS
2877 && GET_CODE (XEXP (src, 1)) == CONST_INT
2878 && XEXP (src, 0) == ep->to_rtx)
2879 offset = INTVAL (XEXP (src, 1)), ok = 1;
2887 = plus_constant (ep->to_rtx, offset - ep->offset);
2889 /* First see if this insn remains valid when we
2890 make the change. If not, keep the INSN_CODE
2891 the same and let reload fit it up. */
2892 validate_change (insn, &SET_SRC (old_set), src, 1);
2893 validate_change (insn, &SET_DEST (old_set),
2895 if (! apply_change_group ())
2897 SET_SRC (old_set) = src;
2898 SET_DEST (old_set) = ep->to_rtx;
2908 /* In this case this insn isn't serving a useful purpose. We
2909 will delete it in reload_as_needed once we know that this
2910 elimination is, in fact, being done.
2912 If REPLACE isn't set, we can't delete this insn, but needn't
2913 process it since it won't be used unless something changes. */
2916 delete_dead_insn (insn);
2924 /* We allow one special case which happens to work on all machines we
2925 currently support: a single set with the source being a PLUS of an
2926 eliminable register and a constant. */
2928 && GET_CODE (SET_SRC (old_set)) == PLUS
2929 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2930 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2931 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2933 rtx reg = XEXP (SET_SRC (old_set), 0);
2934 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2936 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2937 if (ep->from_rtx == reg && ep->can_eliminate)
2939 offset += ep->offset;
2943 /* We assume here that we don't need a PARALLEL of
2944 any CLOBBERs for this assignment. There's not
2945 much we can do if we do need it. */
2946 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2949 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
2950 if (INSN_CODE (insn) < 0)
2955 new_body = old_body;
2958 new_body = copy_insn (old_body);
2959 if (REG_NOTES (insn))
2960 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2962 PATTERN (insn) = new_body;
2963 old_set = single_set (insn);
2965 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2966 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2969 /* This can't have an effect on elimination offsets, so skip right
2975 /* Determine the effects of this insn on elimination offsets. */
2976 elimination_effects (old_body, 0);
2978 /* Eliminate all eliminable registers occurring in operands that
2979 can be handled by reload. */
2980 extract_insn (insn);
2982 for (i = 0; i < recog_data.n_operands; i++)
2984 orig_operand[i] = recog_data.operand[i];
2985 substed_operand[i] = recog_data.operand[i];
2987 /* For an asm statement, every operand is eliminable. */
2988 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2990 /* Check for setting a register that we know about. */
2991 if (recog_data.operand_type[i] != OP_IN
2992 && GET_CODE (orig_operand[i]) == REG)
2994 /* If we are assigning to a register that can be eliminated, it
2995 must be as part of a PARALLEL, since the code above handles
2996 single SETs. We must indicate that we can no longer
2997 eliminate this reg. */
2998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3000 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3001 ep->can_eliminate = 0;
3004 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3005 replace ? insn : NULL_RTX);
3006 if (substed_operand[i] != orig_operand[i])
3007 val = any_changes = 1;
3008 /* Terminate the search in check_eliminable_occurrences at
3010 *recog_data.operand_loc[i] = 0;
3012 /* If an output operand changed from a REG to a MEM and INSN is an
3013 insn, write a CLOBBER insn. */
3014 if (recog_data.operand_type[i] != OP_IN
3015 && GET_CODE (orig_operand[i]) == REG
3016 && GET_CODE (substed_operand[i]) == MEM
3018 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3023 for (i = 0; i < recog_data.n_dups; i++)
3024 *recog_data.dup_loc[i]
3025 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
3027 /* If any eliminable remain, they aren't eliminable anymore. */
3028 check_eliminable_occurrences (old_body);
3030 /* Substitute the operands; the new values are in the substed_operand
3032 for (i = 0; i < recog_data.n_operands; i++)
3033 *recog_data.operand_loc[i] = substed_operand[i];
3034 for (i = 0; i < recog_data.n_dups; i++)
3035 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3037 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3038 re-recognize the insn. We do this in case we had a simple addition
3039 but now can do this as a load-address. This saves an insn in this
3041 If re-recognition fails, the old insn code number will still be used,
3042 and some register operands may have changed into PLUS expressions.
3043 These will be handled by find_reloads by loading them into a register
3048 /* If we aren't replacing things permanently and we changed something,
3049 make another copy to ensure that all the RTL is new. Otherwise
3050 things can go wrong if find_reload swaps commutative operands
3051 and one is inside RTL that has been copied while the other is not. */
3052 new_body = old_body;
3055 new_body = copy_insn (old_body);
3056 if (REG_NOTES (insn))
3057 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3059 PATTERN (insn) = new_body;
3061 /* If we had a move insn but now we don't, rerecognize it. This will
3062 cause spurious re-recognition if the old move had a PARALLEL since
3063 the new one still will, but we can't call single_set without
3064 having put NEW_BODY into the insn and the re-recognition won't
3065 hurt in this rare case. */
3066 /* ??? Why this huge if statement - why don't we just rerecognize the
3070 && ((GET_CODE (SET_SRC (old_set)) == REG
3071 && (GET_CODE (new_body) != SET
3072 || GET_CODE (SET_SRC (new_body)) != REG))
3073 /* If this was a load from or store to memory, compare
3074 the MEM in recog_data.operand to the one in the insn.
3075 If they are not equal, then rerecognize the insn. */
3077 && ((GET_CODE (SET_SRC (old_set)) == MEM
3078 && SET_SRC (old_set) != recog_data.operand[1])
3079 || (GET_CODE (SET_DEST (old_set)) == MEM
3080 && SET_DEST (old_set) != recog_data.operand[0])))
3081 /* If this was an add insn before, rerecognize. */
3082 || GET_CODE (SET_SRC (old_set)) == PLUS))
3084 int new_icode = recog (PATTERN (insn), insn, 0);
3086 INSN_CODE (insn) = icode;
3090 /* Restore the old body. If there were any changes to it, we made a copy
3091 of it while the changes were still in place, so we'll correctly return
3092 a modified insn below. */
3095 /* Restore the old body. */
3096 for (i = 0; i < recog_data.n_operands; i++)
3097 *recog_data.operand_loc[i] = orig_operand[i];
3098 for (i = 0; i < recog_data.n_dups; i++)
3099 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3102 /* Update all elimination pairs to reflect the status after the current
3103 insn. The changes we make were determined by the earlier call to
3104 elimination_effects.
3106 We also detect a cases where register elimination cannot be done,
3107 namely, if a register would be both changed and referenced outside a MEM
3108 in the resulting insn since such an insn is often undefined and, even if
3109 not, we cannot know what meaning will be given to it. Note that it is
3110 valid to have a register used in an address in an insn that changes it
3111 (presumably with a pre- or post-increment or decrement).
3113 If anything changes, return nonzero. */
3115 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3117 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3118 ep->can_eliminate = 0;
3120 ep->ref_outside_mem = 0;
3122 if (ep->previous_offset != ep->offset)
3127 /* If we changed something, perform elimination in REG_NOTES. This is
3128 needed even when REPLACE is zero because a REG_DEAD note might refer
3129 to a register that we eliminate and could cause a different number
3130 of spill registers to be needed in the final reload pass than in
3132 if (val && REG_NOTES (insn) != 0)
3133 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3141 /* Loop through all elimination pairs.
3142 Recalculate the number not at initial offset.
3144 Compute the maximum offset (minimum offset if the stack does not
3145 grow downward) for each elimination pair. */
3148 update_eliminable_offsets ()
3150 struct elim_table *ep;
3152 num_not_at_initial_offset = 0;
3153 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3155 ep->previous_offset = ep->offset;
3156 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3157 num_not_at_initial_offset++;
3161 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3162 replacement we currently believe is valid, mark it as not eliminable if X
3163 modifies DEST in any way other than by adding a constant integer to it.
3165 If DEST is the frame pointer, we do nothing because we assume that
3166 all assignments to the hard frame pointer are nonlocal gotos and are being
3167 done at a time when they are valid and do not disturb anything else.
3168 Some machines want to eliminate a fake argument pointer with either the
3169 frame or stack pointer. Assignments to the hard frame pointer must not
3170 prevent this elimination.
3172 Called via note_stores from reload before starting its passes to scan
3173 the insns of the function. */
3176 mark_not_eliminable (dest, x, data)
3179 void *data ATTRIBUTE_UNUSED;
3181 register unsigned int i;
3183 /* A SUBREG of a hard register here is just changing its mode. We should
3184 not see a SUBREG of an eliminable hard register, but check just in
3186 if (GET_CODE (dest) == SUBREG)
3187 dest = SUBREG_REG (dest);
3189 if (dest == hard_frame_pointer_rtx)
3192 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3193 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3194 && (GET_CODE (x) != SET
3195 || GET_CODE (SET_SRC (x)) != PLUS
3196 || XEXP (SET_SRC (x), 0) != dest
3197 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3199 reg_eliminate[i].can_eliminate_previous
3200 = reg_eliminate[i].can_eliminate = 0;
3205 /* Verify that the initial elimination offsets did not change since the
3206 last call to set_initial_elim_offsets. This is used to catch cases
3207 where something illegal happened during reload_as_needed that could
3208 cause incorrect code to be generated if we did not check for it. */
3211 verify_initial_elim_offsets ()
3215 #ifdef ELIMINABLE_REGS
3216 struct elim_table *ep;
3218 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3220 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3221 if (t != ep->initial_offset)
3225 INITIAL_FRAME_POINTER_OFFSET (t);
3226 if (t != reg_eliminate[0].initial_offset)
3231 /* Reset all offsets on eliminable registers to their initial values. */
3234 set_initial_elim_offsets ()
3236 struct elim_table *ep = reg_eliminate;
3238 #ifdef ELIMINABLE_REGS
3239 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3241 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3242 ep->previous_offset = ep->offset = ep->initial_offset;
3245 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3246 ep->previous_offset = ep->offset = ep->initial_offset;
3249 num_not_at_initial_offset = 0;
3252 /* Initialize the known label offsets.
3253 Set a known offset for each forced label to be at the initial offset
3254 of each elimination. We do this because we assume that all
3255 computed jumps occur from a location where each elimination is
3256 at its initial offset.
3257 For all other labels, show that we don't know the offsets. */
3260 set_initial_label_offsets ()
3263 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3265 for (x = forced_labels; x; x = XEXP (x, 1))
3267 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3270 /* Set all elimination offsets to the known values for the code label given
3274 set_offsets_for_label (insn)
3278 int label_nr = CODE_LABEL_NUMBER (insn);
3279 struct elim_table *ep;
3281 num_not_at_initial_offset = 0;
3282 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3284 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3285 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3286 num_not_at_initial_offset++;
3290 /* See if anything that happened changes which eliminations are valid.
3291 For example, on the Sparc, whether or not the frame pointer can
3292 be eliminated can depend on what registers have been used. We need
3293 not check some conditions again (such as flag_omit_frame_pointer)
3294 since they can't have changed. */
3297 update_eliminables (pset)
3300 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3301 int previous_frame_pointer_needed = frame_pointer_needed;
3303 struct elim_table *ep;
3305 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3306 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3307 #ifdef ELIMINABLE_REGS
3308 || ! CAN_ELIMINATE (ep->from, ep->to)
3311 ep->can_eliminate = 0;
3313 /* Look for the case where we have discovered that we can't replace
3314 register A with register B and that means that we will now be
3315 trying to replace register A with register C. This means we can
3316 no longer replace register C with register B and we need to disable
3317 such an elimination, if it exists. This occurs often with A == ap,
3318 B == sp, and C == fp. */
3320 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3322 struct elim_table *op;
3323 register int new_to = -1;
3325 if (! ep->can_eliminate && ep->can_eliminate_previous)
3327 /* Find the current elimination for ep->from, if there is a
3329 for (op = reg_eliminate;
3330 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3331 if (op->from == ep->from && op->can_eliminate)
3337 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3339 for (op = reg_eliminate;
3340 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3341 if (op->from == new_to && op->to == ep->to)
3342 op->can_eliminate = 0;
3346 /* See if any registers that we thought we could eliminate the previous
3347 time are no longer eliminable. If so, something has changed and we
3348 must spill the register. Also, recompute the number of eliminable
3349 registers and see if the frame pointer is needed; it is if there is
3350 no elimination of the frame pointer that we can perform. */
3352 frame_pointer_needed = 1;
3353 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3355 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3356 && ep->to != HARD_FRAME_POINTER_REGNUM)
3357 frame_pointer_needed = 0;
3359 if (! ep->can_eliminate && ep->can_eliminate_previous)
3361 ep->can_eliminate_previous = 0;
3362 SET_HARD_REG_BIT (*pset, ep->from);
3367 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3368 /* If we didn't need a frame pointer last time, but we do now, spill
3369 the hard frame pointer. */
3370 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3371 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3375 /* Initialize the table of registers to eliminate. */
3380 struct elim_table *ep;
3381 #ifdef ELIMINABLE_REGS
3382 struct elim_table_1 *ep1;
3386 reg_eliminate = (struct elim_table *)
3387 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3389 /* Does this function require a frame pointer? */
3391 frame_pointer_needed = (! flag_omit_frame_pointer
3392 #ifdef EXIT_IGNORE_STACK
3393 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3394 and restore sp for alloca. So we can't eliminate
3395 the frame pointer in that case. At some point,
3396 we should improve this by emitting the
3397 sp-adjusting insns for this case. */
3398 || (current_function_calls_alloca
3399 && EXIT_IGNORE_STACK)
3401 || FRAME_POINTER_REQUIRED);
3405 #ifdef ELIMINABLE_REGS
3406 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3407 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3409 ep->from = ep1->from;
3411 ep->can_eliminate = ep->can_eliminate_previous
3412 = (CAN_ELIMINATE (ep->from, ep->to)
3413 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3416 reg_eliminate[0].from = reg_eliminate_1[0].from;
3417 reg_eliminate[0].to = reg_eliminate_1[0].to;
3418 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3419 = ! frame_pointer_needed;
3422 /* Count the number of eliminable registers and build the FROM and TO
3423 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3424 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3425 We depend on this. */
3426 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3428 num_eliminable += ep->can_eliminate;
3429 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3430 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3434 /* Kick all pseudos out of hard register REGNO.
3435 If DUMPFILE is nonzero, log actions taken on that file.
3437 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3438 because we found we can't eliminate some register. In the case, no pseudos
3439 are allowed to be in the register, even if they are only in a block that
3440 doesn't require spill registers, unlike the case when we are spilling this
3441 hard reg to produce another spill register.
3443 Return nonzero if any pseudos needed to be kicked out. */
3446 spill_hard_reg (regno, dumpfile, cant_eliminate)
3448 FILE *dumpfile ATTRIBUTE_UNUSED;
3455 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3456 regs_ever_live[regno] = 1;
3459 /* Spill every pseudo reg that was allocated to this reg
3460 or to something that overlaps this reg. */
3462 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3463 if (reg_renumber[i] >= 0
3464 && (unsigned int) reg_renumber[i] <= regno
3465 && ((unsigned int) reg_renumber[i]
3466 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3467 PSEUDO_REGNO_MODE (i))
3469 SET_REGNO_REG_SET (&spilled_pseudos, i);
3472 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3473 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3476 ior_hard_reg_set (set1, set2)
3477 HARD_REG_SET *set1, *set2;
3479 IOR_HARD_REG_SET (*set1, *set2);
3482 /* After find_reload_regs has been run for all insn that need reloads,
3483 and/or spill_hard_regs was called, this function is used to actually
3484 spill pseudo registers and try to reallocate them. It also sets up the
3485 spill_regs array for use by choose_reload_regs. */
3488 finish_spills (global, dumpfile)
3492 struct insn_chain *chain;
3493 int something_changed = 0;
3496 /* Build the spill_regs array for the function. */
3497 /* If there are some registers still to eliminate and one of the spill regs
3498 wasn't ever used before, additional stack space may have to be
3499 allocated to store this register. Thus, we may have changed the offset
3500 between the stack and frame pointers, so mark that something has changed.
3502 One might think that we need only set VAL to 1 if this is a call-used
3503 register. However, the set of registers that must be saved by the
3504 prologue is not identical to the call-used set. For example, the
3505 register used by the call insn for the return PC is a call-used register,
3506 but must be saved by the prologue. */
3509 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3510 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3512 spill_reg_order[i] = n_spills;
3513 spill_regs[n_spills++] = i;
3514 if (num_eliminable && ! regs_ever_live[i])
3515 something_changed = 1;
3516 regs_ever_live[i] = 1;
3519 spill_reg_order[i] = -1;
3521 EXECUTE_IF_SET_IN_REG_SET
3522 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3524 /* Record the current hard register the pseudo is allocated to in
3525 pseudo_previous_regs so we avoid reallocating it to the same
3526 hard reg in a later pass. */
3527 if (reg_renumber[i] < 0)
3530 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3531 /* Mark it as no longer having a hard register home. */
3532 reg_renumber[i] = -1;
3533 /* We will need to scan everything again. */
3534 something_changed = 1;
3537 /* Retry global register allocation if possible. */
3540 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3541 /* For every insn that needs reloads, set the registers used as spill
3542 regs in pseudo_forbidden_regs for every pseudo live across the
3544 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3546 EXECUTE_IF_SET_IN_REG_SET
3547 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3549 ior_hard_reg_set (pseudo_forbidden_regs + i,
3550 &chain->used_spill_regs);
3552 EXECUTE_IF_SET_IN_REG_SET
3553 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3555 ior_hard_reg_set (pseudo_forbidden_regs + i,
3556 &chain->used_spill_regs);
3560 /* Retry allocating the spilled pseudos. For each reg, merge the
3561 various reg sets that indicate which hard regs can't be used,
3562 and call retry_global_alloc.
3563 We change spill_pseudos here to only contain pseudos that did not
3564 get a new hard register. */
3565 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3566 if (reg_old_renumber[i] != reg_renumber[i])
3568 HARD_REG_SET forbidden;
3569 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3570 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3571 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3572 retry_global_alloc (i, forbidden);
3573 if (reg_renumber[i] >= 0)
3574 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3578 /* Fix up the register information in the insn chain.
3579 This involves deleting those of the spilled pseudos which did not get
3580 a new hard register home from the live_{before,after} sets. */
3581 for (chain = reload_insn_chain; chain; chain = chain->next)
3583 HARD_REG_SET used_by_pseudos;
3584 HARD_REG_SET used_by_pseudos2;
3586 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3587 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3589 /* Mark any unallocated hard regs as available for spills. That
3590 makes inheritance work somewhat better. */
3591 if (chain->need_reload)
3593 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3594 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3595 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3597 /* Save the old value for the sanity test below. */
3598 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3600 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3601 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3602 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3603 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3605 /* Make sure we only enlarge the set. */
3606 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3612 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3613 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3615 int regno = reg_renumber[i];
3616 if (reg_old_renumber[i] == regno)
3619 alter_reg (i, reg_old_renumber[i]);
3620 reg_old_renumber[i] = regno;
3624 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3626 fprintf (dumpfile, " Register %d now in %d.\n\n",
3627 i, reg_renumber[i]);
3631 return something_changed;
3634 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3635 Also mark any hard registers used to store user variables as
3636 forbidden from being used for spill registers. */
3639 scan_paradoxical_subregs (x)
3643 register const char *fmt;
3644 register enum rtx_code code = GET_CODE (x);
3650 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3651 && REG_USERVAR_P (x))
3652 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3668 if (GET_CODE (SUBREG_REG (x)) == REG
3669 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3670 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3671 = GET_MODE_SIZE (GET_MODE (x));
3678 fmt = GET_RTX_FORMAT (code);
3679 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3682 scan_paradoxical_subregs (XEXP (x, i));
3683 else if (fmt[i] == 'E')
3686 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3687 scan_paradoxical_subregs (XVECEXP (x, i, j));
3692 /* Reload pseudo-registers into hard regs around each insn as needed.
3693 Additional register load insns are output before the insn that needs it
3694 and perhaps store insns after insns that modify the reloaded pseudo reg.
3696 reg_last_reload_reg and reg_reloaded_contents keep track of
3697 which registers are already available in reload registers.
3698 We update these for the reloads that we perform,
3699 as the insns are scanned. */
3702 reload_as_needed (live_known)
3705 struct insn_chain *chain;
3706 #if defined (AUTO_INC_DEC)
3711 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3712 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3713 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3714 reg_has_output_reload = (char *) xmalloc (max_regno);
3715 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3717 set_initial_elim_offsets ();
3719 for (chain = reload_insn_chain; chain; chain = chain->next)
3722 rtx insn = chain->insn;
3723 rtx old_next = NEXT_INSN (insn);
3725 /* If we pass a label, copy the offsets from the label information
3726 into the current offsets of each elimination. */
3727 if (GET_CODE (insn) == CODE_LABEL)
3728 set_offsets_for_label (insn);
3730 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3732 rtx oldpat = PATTERN (insn);
3734 /* If this is a USE and CLOBBER of a MEM, ensure that any
3735 references to eliminable registers have been removed. */
3737 if ((GET_CODE (PATTERN (insn)) == USE
3738 || GET_CODE (PATTERN (insn)) == CLOBBER)
3739 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3740 XEXP (XEXP (PATTERN (insn), 0), 0)
3741 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3742 GET_MODE (XEXP (PATTERN (insn), 0)),
3745 /* If we need to do register elimination processing, do so.
3746 This might delete the insn, in which case we are done. */
3747 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3749 eliminate_regs_in_insn (insn, 1);
3750 if (GET_CODE (insn) == NOTE)
3752 update_eliminable_offsets ();
3757 /* If need_elim is nonzero but need_reload is zero, one might think
3758 that we could simply set n_reloads to 0. However, find_reloads
3759 could have done some manipulation of the insn (such as swapping
3760 commutative operands), and these manipulations are lost during
3761 the first pass for every insn that needs register elimination.
3762 So the actions of find_reloads must be redone here. */
3764 if (! chain->need_elim && ! chain->need_reload
3765 && ! chain->need_operand_change)
3767 /* First find the pseudo regs that must be reloaded for this insn.
3768 This info is returned in the tables reload_... (see reload.h).
3769 Also modify the body of INSN by substituting RELOAD
3770 rtx's for those pseudo regs. */
3773 bzero (reg_has_output_reload, max_regno);
3774 CLEAR_HARD_REG_SET (reg_is_output_reload);
3776 find_reloads (insn, 1, spill_indirect_levels, live_known,
3780 if (num_eliminable && chain->need_elim)
3781 update_eliminable_offsets ();
3785 rtx next = NEXT_INSN (insn);
3788 prev = PREV_INSN (insn);
3790 /* Now compute which reload regs to reload them into. Perhaps
3791 reusing reload regs from previous insns, or else output
3792 load insns to reload them. Maybe output store insns too.
3793 Record the choices of reload reg in reload_reg_rtx. */
3794 choose_reload_regs (chain);
3796 /* Merge any reloads that we didn't combine for fear of
3797 increasing the number of spill registers needed but now
3798 discover can be safely merged. */
3799 if (SMALL_REGISTER_CLASSES)
3800 merge_assigned_reloads (insn);
3802 /* Generate the insns to reload operands into or out of
3803 their reload regs. */
3804 emit_reload_insns (chain);
3806 /* Substitute the chosen reload regs from reload_reg_rtx
3807 into the insn's body (or perhaps into the bodies of other
3808 load and store insn that we just made for reloading
3809 and that we moved the structure into). */
3812 /* If this was an ASM, make sure that all the reload insns
3813 we have generated are valid. If not, give an error
3816 if (asm_noperands (PATTERN (insn)) >= 0)
3817 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3818 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3819 && (recog_memoized (p) < 0
3820 || (extract_insn (p), ! constrain_operands (1))))
3822 error_for_asm (insn,
3823 "`asm' operand requires impossible reload");
3825 NOTE_SOURCE_FILE (p) = 0;
3826 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3829 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3830 is no longer validly lying around to save a future reload.
3831 Note that this does not detect pseudos that were reloaded
3832 for this insn in order to be stored in
3833 (obeying register constraints). That is correct; such reload
3834 registers ARE still valid. */
3835 note_stores (oldpat, forget_old_reloads_1, NULL);
3837 /* There may have been CLOBBER insns placed after INSN. So scan
3838 between INSN and NEXT and use them to forget old reloads. */
3839 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3840 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3841 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3844 /* Likewise for regs altered by auto-increment in this insn.
3845 REG_INC notes have been changed by reloading:
3846 find_reloads_address_1 records substitutions for them,
3847 which have been performed by subst_reloads above. */
3848 for (i = n_reloads - 1; i >= 0; i--)
3850 rtx in_reg = rld[i].in_reg;
3853 enum rtx_code code = GET_CODE (in_reg);
3854 /* PRE_INC / PRE_DEC will have the reload register ending up
3855 with the same value as the stack slot, but that doesn't
3856 hold true for POST_INC / POST_DEC. Either we have to
3857 convert the memory access to a true POST_INC / POST_DEC,
3858 or we can't use the reload register for inheritance. */
3859 if ((code == POST_INC || code == POST_DEC)
3860 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3861 REGNO (rld[i].reg_rtx))
3862 /* Make sure it is the inc/dec pseudo, and not
3863 some other (e.g. output operand) pseudo. */
3864 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3865 == REGNO (XEXP (in_reg, 0))))
3868 rtx reload_reg = rld[i].reg_rtx;
3869 enum machine_mode mode = GET_MODE (reload_reg);
3873 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3875 /* We really want to ignore REG_INC notes here, so
3876 use PATTERN (p) as argument to reg_set_p . */
3877 if (reg_set_p (reload_reg, PATTERN (p)))
3879 n = count_occurrences (PATTERN (p), reload_reg);
3884 n = validate_replace_rtx (reload_reg,
3885 gen_rtx (code, mode,
3889 /* We must also verify that the constraints
3890 are met after the replacement. */
3893 n = constrain_operands (1);
3897 /* If the constraints were not met, then
3898 undo the replacement. */
3901 validate_replace_rtx (gen_rtx (code, mode,
3913 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3915 /* Mark this as having an output reload so that the
3916 REG_INC processing code below won't invalidate
3917 the reload for inheritance. */
3918 SET_HARD_REG_BIT (reg_is_output_reload,
3919 REGNO (reload_reg));
3920 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3923 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3926 else if ((code == PRE_INC || code == PRE_DEC)
3927 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3928 REGNO (rld[i].reg_rtx))
3929 /* Make sure it is the inc/dec pseudo, and not
3930 some other (e.g. output operand) pseudo. */
3931 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3932 == REGNO (XEXP (in_reg, 0))))
3934 SET_HARD_REG_BIT (reg_is_output_reload,
3935 REGNO (rld[i].reg_rtx));
3936 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3940 /* If a pseudo that got a hard register is auto-incremented,
3941 we must purge records of copying it into pseudos without
3943 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3944 if (REG_NOTE_KIND (x) == REG_INC)
3946 /* See if this pseudo reg was reloaded in this insn.
3947 If so, its last-reload info is still valid
3948 because it is based on this insn's reload. */
3949 for (i = 0; i < n_reloads; i++)
3950 if (rld[i].out == XEXP (x, 0))
3954 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3958 /* A reload reg's contents are unknown after a label. */
3959 if (GET_CODE (insn) == CODE_LABEL)
3960 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3962 /* Don't assume a reload reg is still good after a call insn
3963 if it is a call-used reg. */
3964 else if (GET_CODE (insn) == CALL_INSN)
3965 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3969 free (reg_last_reload_reg);
3970 free (reg_has_output_reload);
3973 /* Discard all record of any value reloaded from X,
3974 or reloaded in X from someplace else;
3975 unless X is an output reload reg of the current insn.
3977 X may be a hard reg (the reload reg)
3978 or it may be a pseudo reg that was reloaded from. */
3981 forget_old_reloads_1 (x, ignored, data)
3983 rtx ignored ATTRIBUTE_UNUSED;
3984 void *data ATTRIBUTE_UNUSED;
3990 /* note_stores does give us subregs of hard regs. */
3991 while (GET_CODE (x) == SUBREG)
3993 offset += SUBREG_WORD (x);
3997 if (GET_CODE (x) != REG)
4000 regno = REGNO (x) + offset;
4002 if (regno >= FIRST_PSEUDO_REGISTER)
4008 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4009 /* Storing into a spilled-reg invalidates its contents.
4010 This can happen if a block-local pseudo is allocated to that reg
4011 and it wasn't spilled because this block's total need is 0.
4012 Then some insn might have an optional reload and use this reg. */
4013 for (i = 0; i < nr; i++)
4014 /* But don't do this if the reg actually serves as an output
4015 reload reg in the current instruction. */
4017 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4018 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4021 /* Since value of X has changed,
4022 forget any value previously copied from it. */
4025 /* But don't forget a copy if this is the output reload
4026 that establishes the copy's validity. */
4027 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4028 reg_last_reload_reg[regno + nr] = 0;
4031 /* The following HARD_REG_SETs indicate when each hard register is
4032 used for a reload of various parts of the current insn. */
4034 /* If reg is unavailable for all reloads. */
4035 static HARD_REG_SET reload_reg_unavailable;
4036 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4037 static HARD_REG_SET reload_reg_used;
4038 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4039 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4040 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4041 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4042 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4043 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4044 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4045 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4046 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4047 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4048 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4049 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4050 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4051 static HARD_REG_SET reload_reg_used_in_op_addr;
4052 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4053 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4054 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4055 static HARD_REG_SET reload_reg_used_in_insn;
4056 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4057 static HARD_REG_SET reload_reg_used_in_other_addr;
4059 /* If reg is in use as a reload reg for any sort of reload. */
4060 static HARD_REG_SET reload_reg_used_at_all;
4062 /* If reg is use as an inherited reload. We just mark the first register
4064 static HARD_REG_SET reload_reg_used_for_inherit;
4066 /* Records which hard regs are used in any way, either as explicit use or
4067 by being allocated to a pseudo during any point of the current insn. */
4068 static HARD_REG_SET reg_used_in_insn;
4070 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4071 TYPE. MODE is used to indicate how many consecutive regs are
4075 mark_reload_reg_in_use (regno, opnum, type, mode)
4078 enum reload_type type;
4079 enum machine_mode mode;
4081 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4084 for (i = regno; i < nregs + regno; i++)
4089 SET_HARD_REG_BIT (reload_reg_used, i);
4092 case RELOAD_FOR_INPUT_ADDRESS:
4093 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4096 case RELOAD_FOR_INPADDR_ADDRESS:
4097 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4100 case RELOAD_FOR_OUTPUT_ADDRESS:
4101 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4104 case RELOAD_FOR_OUTADDR_ADDRESS:
4105 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4108 case RELOAD_FOR_OPERAND_ADDRESS:
4109 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4112 case RELOAD_FOR_OPADDR_ADDR:
4113 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4116 case RELOAD_FOR_OTHER_ADDRESS:
4117 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4120 case RELOAD_FOR_INPUT:
4121 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4124 case RELOAD_FOR_OUTPUT:
4125 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4128 case RELOAD_FOR_INSN:
4129 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4133 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4137 /* Similarly, but show REGNO is no longer in use for a reload. */
4140 clear_reload_reg_in_use (regno, opnum, type, mode)
4143 enum reload_type type;
4144 enum machine_mode mode;
4146 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4147 unsigned int start_regno, end_regno, r;
4149 /* A complication is that for some reload types, inheritance might
4150 allow multiple reloads of the same types to share a reload register.
4151 We set check_opnum if we have to check only reloads with the same
4152 operand number, and check_any if we have to check all reloads. */
4153 int check_opnum = 0;
4155 HARD_REG_SET *used_in_set;
4160 used_in_set = &reload_reg_used;
4163 case RELOAD_FOR_INPUT_ADDRESS:
4164 used_in_set = &reload_reg_used_in_input_addr[opnum];
4167 case RELOAD_FOR_INPADDR_ADDRESS:
4169 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4172 case RELOAD_FOR_OUTPUT_ADDRESS:
4173 used_in_set = &reload_reg_used_in_output_addr[opnum];
4176 case RELOAD_FOR_OUTADDR_ADDRESS:
4178 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4181 case RELOAD_FOR_OPERAND_ADDRESS:
4182 used_in_set = &reload_reg_used_in_op_addr;
4185 case RELOAD_FOR_OPADDR_ADDR:
4187 used_in_set = &reload_reg_used_in_op_addr_reload;
4190 case RELOAD_FOR_OTHER_ADDRESS:
4191 used_in_set = &reload_reg_used_in_other_addr;
4195 case RELOAD_FOR_INPUT:
4196 used_in_set = &reload_reg_used_in_input[opnum];
4199 case RELOAD_FOR_OUTPUT:
4200 used_in_set = &reload_reg_used_in_output[opnum];
4203 case RELOAD_FOR_INSN:
4204 used_in_set = &reload_reg_used_in_insn;
4209 /* We resolve conflicts with remaining reloads of the same type by
4210 excluding the intervals of of reload registers by them from the
4211 interval of freed reload registers. Since we only keep track of
4212 one set of interval bounds, we might have to exclude somewhat
4213 more then what would be necessary if we used a HARD_REG_SET here.
4214 But this should only happen very infrequently, so there should
4215 be no reason to worry about it. */
4217 start_regno = regno;
4218 end_regno = regno + nregs;
4219 if (check_opnum || check_any)
4221 for (i = n_reloads - 1; i >= 0; i--)
4223 if (rld[i].when_needed == type
4224 && (check_any || rld[i].opnum == opnum)
4227 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4228 unsigned int conflict_end
4230 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4232 /* If there is an overlap with the first to-be-freed register,
4233 adjust the interval start. */
4234 if (conflict_start <= start_regno && conflict_end > start_regno)
4235 start_regno = conflict_end;
4236 /* Otherwise, if there is a conflict with one of the other
4237 to-be-freed registers, adjust the interval end. */
4238 if (conflict_start > start_regno && conflict_start < end_regno)
4239 end_regno = conflict_start;
4244 for (r = start_regno; r < end_regno; r++)
4245 CLEAR_HARD_REG_BIT (*used_in_set, r);
4248 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4249 specified by OPNUM and TYPE. */
4252 reload_reg_free_p (regno, opnum, type)
4255 enum reload_type type;
4259 /* In use for a RELOAD_OTHER means it's not available for anything. */
4260 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4261 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4267 /* In use for anything means we can't use it for RELOAD_OTHER. */
4268 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4269 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4270 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4273 for (i = 0; i < reload_n_operands; i++)
4274 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4275 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4276 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4277 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4278 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4279 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4284 case RELOAD_FOR_INPUT:
4285 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4286 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4289 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4292 /* If it is used for some other input, can't use it. */
4293 for (i = 0; i < reload_n_operands; i++)
4294 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4297 /* If it is used in a later operand's address, can't use it. */
4298 for (i = opnum + 1; i < reload_n_operands; i++)
4299 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4300 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4305 case RELOAD_FOR_INPUT_ADDRESS:
4306 /* Can't use a register if it is used for an input address for this
4307 operand or used as an input in an earlier one. */
4308 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4309 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4312 for (i = 0; i < opnum; i++)
4313 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4318 case RELOAD_FOR_INPADDR_ADDRESS:
4319 /* Can't use a register if it is used for an input address
4320 for this operand or used as an input in an earlier
4322 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4325 for (i = 0; i < opnum; i++)
4326 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4331 case RELOAD_FOR_OUTPUT_ADDRESS:
4332 /* Can't use a register if it is used for an output address for this
4333 operand or used as an output in this or a later operand. */
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4337 for (i = opnum; i < reload_n_operands; i++)
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4343 case RELOAD_FOR_OUTADDR_ADDRESS:
4344 /* Can't use a register if it is used for an output address
4345 for this operand or used as an output in this or a
4347 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4350 for (i = opnum; i < reload_n_operands; i++)
4351 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4356 case RELOAD_FOR_OPERAND_ADDRESS:
4357 for (i = 0; i < reload_n_operands; i++)
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4361 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4362 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4364 case RELOAD_FOR_OPADDR_ADDR:
4365 for (i = 0; i < reload_n_operands; i++)
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4369 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4371 case RELOAD_FOR_OUTPUT:
4372 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4373 outputs, or an operand address for this or an earlier output. */
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4377 for (i = 0; i < reload_n_operands; i++)
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4381 for (i = 0; i <= opnum; i++)
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4388 case RELOAD_FOR_INSN:
4389 for (i = 0; i < reload_n_operands; i++)
4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4391 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4394 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4395 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4397 case RELOAD_FOR_OTHER_ADDRESS:
4398 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4403 /* Return 1 if the value in reload reg REGNO, as used by a reload
4404 needed for the part of the insn specified by OPNUM and TYPE,
4405 is still available in REGNO at the end of the insn.
4407 We can assume that the reload reg was already tested for availability
4408 at the time it is needed, and we should not check this again,
4409 in case the reg has already been marked in use. */
4412 reload_reg_reaches_end_p (regno, opnum, type)
4415 enum reload_type type;
4422 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4423 its value must reach the end. */
4426 /* If this use is for part of the insn,
4427 its value reaches if no subsequent part uses the same register.
4428 Just like the above function, don't try to do this with lots
4431 case RELOAD_FOR_OTHER_ADDRESS:
4432 /* Here we check for everything else, since these don't conflict
4433 with anything else and everything comes later. */
4435 for (i = 0; i < reload_n_operands; i++)
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4438 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4439 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4440 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4444 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4445 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4446 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4448 case RELOAD_FOR_INPUT_ADDRESS:
4449 case RELOAD_FOR_INPADDR_ADDRESS:
4450 /* Similar, except that we check only for this and subsequent inputs
4451 and the address of only subsequent inputs and we do not need
4452 to check for RELOAD_OTHER objects since they are known not to
4455 for (i = opnum; i < reload_n_operands; i++)
4456 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4459 for (i = opnum + 1; i < reload_n_operands; i++)
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4464 for (i = 0; i < reload_n_operands; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4467 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4473 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4474 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4476 case RELOAD_FOR_INPUT:
4477 /* Similar to input address, except we start at the next operand for
4478 both input and input address and we do not check for
4479 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4482 for (i = opnum + 1; i < reload_n_operands; i++)
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4484 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4485 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4488 /* ... fall through ... */
4490 case RELOAD_FOR_OPERAND_ADDRESS:
4491 /* Check outputs and their addresses. */
4493 for (i = 0; i < reload_n_operands; i++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4496 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4501 case RELOAD_FOR_OPADDR_ADDR:
4502 for (i = 0; i < reload_n_operands; i++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4505 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4508 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4509 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4511 case RELOAD_FOR_INSN:
4512 /* These conflict with other outputs with RELOAD_OTHER. So
4513 we need only check for output addresses. */
4517 /* ... fall through ... */
4519 case RELOAD_FOR_OUTPUT:
4520 case RELOAD_FOR_OUTPUT_ADDRESS:
4521 case RELOAD_FOR_OUTADDR_ADDRESS:
4522 /* We already know these can't conflict with a later output. So the
4523 only thing to check are later output addresses. */
4524 for (i = opnum + 1; i < reload_n_operands; i++)
4525 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4535 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4538 This function uses the same algorithm as reload_reg_free_p above. */
4541 reloads_conflict (r1, r2)
4544 enum reload_type r1_type = rld[r1].when_needed;
4545 enum reload_type r2_type = rld[r2].when_needed;
4546 int r1_opnum = rld[r1].opnum;
4547 int r2_opnum = rld[r2].opnum;
4549 /* RELOAD_OTHER conflicts with everything. */
4550 if (r2_type == RELOAD_OTHER)
4553 /* Otherwise, check conflicts differently for each type. */
4557 case RELOAD_FOR_INPUT:
4558 return (r2_type == RELOAD_FOR_INSN
4559 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4560 || r2_type == RELOAD_FOR_OPADDR_ADDR
4561 || r2_type == RELOAD_FOR_INPUT
4562 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4563 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4564 && r2_opnum > r1_opnum));
4566 case RELOAD_FOR_INPUT_ADDRESS:
4567 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4568 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4570 case RELOAD_FOR_INPADDR_ADDRESS:
4571 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4572 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4574 case RELOAD_FOR_OUTPUT_ADDRESS:
4575 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4576 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4578 case RELOAD_FOR_OUTADDR_ADDRESS:
4579 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4580 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4582 case RELOAD_FOR_OPERAND_ADDRESS:
4583 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4584 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4586 case RELOAD_FOR_OPADDR_ADDR:
4587 return (r2_type == RELOAD_FOR_INPUT
4588 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4590 case RELOAD_FOR_OUTPUT:
4591 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4592 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4593 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4594 && r2_opnum <= r1_opnum));
4596 case RELOAD_FOR_INSN:
4597 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4598 || r2_type == RELOAD_FOR_INSN
4599 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4601 case RELOAD_FOR_OTHER_ADDRESS:
4602 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4612 /* Indexed by reload number, 1 if incoming value
4613 inherited from previous insns. */
4614 char reload_inherited[MAX_RELOADS];
4616 /* For an inherited reload, this is the insn the reload was inherited from,
4617 if we know it. Otherwise, this is 0. */
4618 rtx reload_inheritance_insn[MAX_RELOADS];
4620 /* If non-zero, this is a place to get the value of the reload,
4621 rather than using reload_in. */
4622 rtx reload_override_in[MAX_RELOADS];
4624 /* For each reload, the hard register number of the register used,
4625 or -1 if we did not need a register for this reload. */
4626 int reload_spill_index[MAX_RELOADS];
4628 /* Return 1 if the value in reload reg REGNO, as used by a reload
4629 needed for the part of the insn specified by OPNUM and TYPE,
4630 may be used to load VALUE into it.
4632 Other read-only reloads with the same value do not conflict
4633 unless OUT is non-zero and these other reloads have to live while
4634 output reloads live.
4635 If OUT is CONST0_RTX, this is a special case: it means that the
4636 test should not be for using register REGNO as reload register, but
4637 for copying from register REGNO into the reload register.
4639 RELOADNUM is the number of the reload we want to load this value for;
4640 a reload does not conflict with itself.
4642 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4643 reloads that load an address for the very reload we are considering.
4645 The caller has to make sure that there is no conflict with the return
4648 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4649 ignore_address_reloads)
4652 enum reload_type type;
4655 int ignore_address_reloads;
4658 /* Set if we see an input reload that must not share its reload register
4659 with any new earlyclobber, but might otherwise share the reload
4660 register with an output or input-output reload. */
4661 int check_earlyclobber = 0;
4665 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4668 if (out == const0_rtx)
4674 /* We use some pseudo 'time' value to check if the lifetimes of the
4675 new register use would overlap with the one of a previous reload
4676 that is not read-only or uses a different value.
4677 The 'time' used doesn't have to be linear in any shape or form, just
4679 Some reload types use different 'buckets' for each operand.
4680 So there are MAX_RECOG_OPERANDS different time values for each
4682 We compute TIME1 as the time when the register for the prospective
4683 new reload ceases to be live, and TIME2 for each existing
4684 reload as the time when that the reload register of that reload
4686 Where there is little to be gained by exact lifetime calculations,
4687 we just make conservative assumptions, i.e. a longer lifetime;
4688 this is done in the 'default:' cases. */
4691 case RELOAD_FOR_OTHER_ADDRESS:
4692 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4693 time1 = copy ? 0 : 1;
4696 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4698 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4699 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4700 respectively, to the time values for these, we get distinct time
4701 values. To get distinct time values for each operand, we have to
4702 multiply opnum by at least three. We round that up to four because
4703 multiply by four is often cheaper. */
4704 case RELOAD_FOR_INPADDR_ADDRESS:
4705 time1 = opnum * 4 + 2;
4707 case RELOAD_FOR_INPUT_ADDRESS:
4708 time1 = opnum * 4 + 3;
4710 case RELOAD_FOR_INPUT:
4711 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4712 executes (inclusive). */
4713 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4715 case RELOAD_FOR_OPADDR_ADDR:
4717 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4718 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4720 case RELOAD_FOR_OPERAND_ADDRESS:
4721 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4723 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4725 case RELOAD_FOR_OUTADDR_ADDRESS:
4726 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4728 case RELOAD_FOR_OUTPUT_ADDRESS:
4729 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4732 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4735 for (i = 0; i < n_reloads; i++)
4737 rtx reg = rld[i].reg_rtx;
4738 if (reg && GET_CODE (reg) == REG
4739 && ((unsigned) regno - true_regnum (reg)
4740 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4743 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4744 || rld[i].out || out)
4747 switch (rld[i].when_needed)
4749 case RELOAD_FOR_OTHER_ADDRESS:
4752 case RELOAD_FOR_INPADDR_ADDRESS:
4753 /* find_reloads makes sure that a
4754 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4755 by at most one - the first -
4756 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4757 address reload is inherited, the address address reload
4758 goes away, so we can ignore this conflict. */
4759 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4760 && ignore_address_reloads
4761 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4762 Then the address address is still needed to store
4763 back the new address. */
4764 && ! rld[reloadnum].out)
4766 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4767 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4769 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4770 && ignore_address_reloads
4771 /* Unless we are reloading an auto_inc expression. */
4772 && ! rld[reloadnum].out)
4774 time2 = rld[i].opnum * 4 + 2;
4776 case RELOAD_FOR_INPUT_ADDRESS:
4777 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4778 && ignore_address_reloads
4779 && ! rld[reloadnum].out)
4781 time2 = rld[i].opnum * 4 + 3;
4783 case RELOAD_FOR_INPUT:
4784 time2 = rld[i].opnum * 4 + 4;
4785 check_earlyclobber = 1;
4787 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4788 == MAX_RECOG_OPERAND * 4 */
4789 case RELOAD_FOR_OPADDR_ADDR:
4790 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4791 && ignore_address_reloads
4792 && ! rld[reloadnum].out)
4794 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4796 case RELOAD_FOR_OPERAND_ADDRESS:
4797 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4798 check_earlyclobber = 1;
4800 case RELOAD_FOR_INSN:
4801 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4803 case RELOAD_FOR_OUTPUT:
4804 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4805 instruction is executed. */
4806 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4808 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4809 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4811 case RELOAD_FOR_OUTADDR_ADDRESS:
4812 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4813 && ignore_address_reloads
4814 && ! rld[reloadnum].out)
4816 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4818 case RELOAD_FOR_OUTPUT_ADDRESS:
4819 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4822 /* If there is no conflict in the input part, handle this
4823 like an output reload. */
4824 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4826 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4827 /* Earlyclobbered outputs must conflict with inputs. */
4828 if (earlyclobber_operand_p (rld[i].out))
4829 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4834 /* RELOAD_OTHER might be live beyond instruction execution,
4835 but this is not obvious when we set time2 = 1. So check
4836 here if there might be a problem with the new reload
4837 clobbering the register used by the RELOAD_OTHER. */
4845 && (! rld[i].in || rld[i].out
4846 || ! rtx_equal_p (rld[i].in, value)))
4847 || (out && rld[reloadnum].out_reg
4848 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4854 /* Earlyclobbered outputs must conflict with inputs. */
4855 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4861 /* Give an error message saying we failed to find a reload for INSN,
4862 and clear out reload R. */
4864 failed_reload (insn, r)
4868 if (asm_noperands (PATTERN (insn)) < 0)
4869 /* It's the compiler's fault. */
4870 fatal_insn ("Could not find a spill register", insn);
4872 /* It's the user's fault; the operand's mode and constraint
4873 don't match. Disable this reload so we don't crash in final. */
4874 error_for_asm (insn,
4875 "`asm' operand constraint incompatible with operand size");
4879 rld[r].optional = 1;
4880 rld[r].secondary_p = 1;
4883 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4884 for reload R. If it's valid, get an rtx for it. Return nonzero if
4887 set_reload_reg (i, r)
4891 rtx reg = spill_reg_rtx[i];
4893 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4894 spill_reg_rtx[i] = reg
4895 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4897 regno = true_regnum (reg);
4899 /* Detect when the reload reg can't hold the reload mode.
4900 This used to be one `if', but Sequent compiler can't handle that. */
4901 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4903 enum machine_mode test_mode = VOIDmode;
4905 test_mode = GET_MODE (rld[r].in);
4906 /* If rld[r].in has VOIDmode, it means we will load it
4907 in whatever mode the reload reg has: to wit, rld[r].mode.
4908 We have already tested that for validity. */
4909 /* Aside from that, we need to test that the expressions
4910 to reload from or into have modes which are valid for this
4911 reload register. Otherwise the reload insns would be invalid. */
4912 if (! (rld[r].in != 0 && test_mode != VOIDmode
4913 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4914 if (! (rld[r].out != 0
4915 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4917 /* The reg is OK. */
4920 /* Mark as in use for this insn the reload regs we use
4922 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4923 rld[r].when_needed, rld[r].mode);
4925 rld[r].reg_rtx = reg;
4926 reload_spill_index[r] = spill_regs[i];
4933 /* Find a spill register to use as a reload register for reload R.
4934 LAST_RELOAD is non-zero if this is the last reload for the insn being
4937 Set rld[R].reg_rtx to the register allocated.
4939 We return 1 if successful, or 0 if we couldn't find a spill reg and
4940 we didn't change anything. */
4943 allocate_reload_reg (chain, r, last_reload)
4944 struct insn_chain *chain ATTRIBUTE_UNUSED;
4950 /* If we put this reload ahead, thinking it is a group,
4951 then insist on finding a group. Otherwise we can grab a
4952 reg that some other reload needs.
4953 (That can happen when we have a 68000 DATA_OR_FP_REG
4954 which is a group of data regs or one fp reg.)
4955 We need not be so restrictive if there are no more reloads
4958 ??? Really it would be nicer to have smarter handling
4959 for that kind of reg class, where a problem like this is normal.
4960 Perhaps those classes should be avoided for reloading
4961 by use of more alternatives. */
4963 int force_group = rld[r].nregs > 1 && ! last_reload;
4965 /* If we want a single register and haven't yet found one,
4966 take any reg in the right class and not in use.
4967 If we want a consecutive group, here is where we look for it.
4969 We use two passes so we can first look for reload regs to
4970 reuse, which are already in use for other reloads in this insn,
4971 and only then use additional registers.
4972 I think that maximizing reuse is needed to make sure we don't
4973 run out of reload regs. Suppose we have three reloads, and
4974 reloads A and B can share regs. These need two regs.
4975 Suppose A and B are given different regs.
4976 That leaves none for C. */
4977 for (pass = 0; pass < 2; pass++)
4979 /* I is the index in spill_regs.
4980 We advance it round-robin between insns to use all spill regs
4981 equally, so that inherited reloads have a chance
4982 of leapfrogging each other. */
4986 for (count = 0; count < n_spills; count++)
4988 int class = (int) rld[r].class;
4994 regnum = spill_regs[i];
4996 if ((reload_reg_free_p (regnum, rld[r].opnum,
4999 /* We check reload_reg_used to make sure we
5000 don't clobber the return register. */
5001 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5002 && reload_reg_free_for_value_p (regnum,
5007 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5008 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5009 /* Look first for regs to share, then for unshared. But
5010 don't share regs used for inherited reloads; they are
5011 the ones we want to preserve. */
5013 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5015 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5018 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5019 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5020 (on 68000) got us two FP regs. If NR is 1,
5021 we would reject both of them. */
5024 /* If we need only one reg, we have already won. */
5027 /* But reject a single reg if we demand a group. */
5032 /* Otherwise check that as many consecutive regs as we need
5033 are available here. */
5036 int regno = regnum + nr - 1;
5037 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5038 && spill_reg_order[regno] >= 0
5039 && reload_reg_free_p (regno, rld[r].opnum,
5040 rld[r].when_needed)))
5049 /* If we found something on pass 1, omit pass 2. */
5050 if (count < n_spills)
5054 /* We should have found a spill register by now. */
5055 if (count >= n_spills)
5058 /* I is the index in SPILL_REG_RTX of the reload register we are to
5059 allocate. Get an rtx for it and find its register number. */
5061 return set_reload_reg (i, r);
5064 /* Initialize all the tables needed to allocate reload registers.
5065 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5066 is the array we use to restore the reg_rtx field for every reload. */
5069 choose_reload_regs_init (chain, save_reload_reg_rtx)
5070 struct insn_chain *chain;
5071 rtx *save_reload_reg_rtx;
5075 for (i = 0; i < n_reloads; i++)
5076 rld[i].reg_rtx = save_reload_reg_rtx[i];
5078 bzero (reload_inherited, MAX_RELOADS);
5079 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5080 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5082 CLEAR_HARD_REG_SET (reload_reg_used);
5083 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5084 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5085 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5086 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5087 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5089 CLEAR_HARD_REG_SET (reg_used_in_insn);
5092 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5093 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5094 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5095 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5096 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5097 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5100 for (i = 0; i < reload_n_operands; i++)
5102 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5103 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5104 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5105 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5106 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5107 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5110 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5112 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5114 for (i = 0; i < n_reloads; i++)
5115 /* If we have already decided to use a certain register,
5116 don't use it in another way. */
5118 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5119 rld[i].when_needed, rld[i].mode);
5122 /* Assign hard reg targets for the pseudo-registers we must reload
5123 into hard regs for this insn.
5124 Also output the instructions to copy them in and out of the hard regs.
5126 For machines with register classes, we are responsible for
5127 finding a reload reg in the proper class. */
5130 choose_reload_regs (chain)
5131 struct insn_chain *chain;
5133 rtx insn = chain->insn;
5135 unsigned int max_group_size = 1;
5136 enum reg_class group_class = NO_REGS;
5137 int pass, win, inheritance;
5139 rtx save_reload_reg_rtx[MAX_RELOADS];
5141 /* In order to be certain of getting the registers we need,
5142 we must sort the reloads into order of increasing register class.
5143 Then our grabbing of reload registers will parallel the process
5144 that provided the reload registers.
5146 Also note whether any of the reloads wants a consecutive group of regs.
5147 If so, record the maximum size of the group desired and what
5148 register class contains all the groups needed by this insn. */
5150 for (j = 0; j < n_reloads; j++)
5152 reload_order[j] = j;
5153 reload_spill_index[j] = -1;
5155 if (rld[j].nregs > 1)
5157 max_group_size = MAX (rld[j].nregs, max_group_size);
5159 = reg_class_superunion[(int)rld[j].class][(int)group_class];
5162 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5166 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5168 /* If -O, try first with inheritance, then turning it off.
5169 If not -O, don't do inheritance.
5170 Using inheritance when not optimizing leads to paradoxes
5171 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5172 because one side of the comparison might be inherited. */
5174 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5176 choose_reload_regs_init (chain, save_reload_reg_rtx);
5178 /* Process the reloads in order of preference just found.
5179 Beyond this point, subregs can be found in reload_reg_rtx.
5181 This used to look for an existing reloaded home for all of the
5182 reloads, and only then perform any new reloads. But that could lose
5183 if the reloads were done out of reg-class order because a later
5184 reload with a looser constraint might have an old home in a register
5185 needed by an earlier reload with a tighter constraint.
5187 To solve this, we make two passes over the reloads, in the order
5188 described above. In the first pass we try to inherit a reload
5189 from a previous insn. If there is a later reload that needs a
5190 class that is a proper subset of the class being processed, we must
5191 also allocate a spill register during the first pass.
5193 Then make a second pass over the reloads to allocate any reloads
5194 that haven't been given registers yet. */
5196 for (j = 0; j < n_reloads; j++)
5198 register int r = reload_order[j];
5199 rtx search_equiv = NULL_RTX;
5201 /* Ignore reloads that got marked inoperative. */
5202 if (rld[r].out == 0 && rld[r].in == 0
5203 && ! rld[r].secondary_p)
5206 /* If find_reloads chose to use reload_in or reload_out as a reload
5207 register, we don't need to chose one. Otherwise, try even if it
5208 found one since we might save an insn if we find the value lying
5210 Try also when reload_in is a pseudo without a hard reg. */
5211 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5212 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5213 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5214 && GET_CODE (rld[r].in) != MEM
5215 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5218 #if 0 /* No longer needed for correct operation.
5219 It might give better code, or might not; worth an experiment? */
5220 /* If this is an optional reload, we can't inherit from earlier insns
5221 until we are sure that any non-optional reloads have been allocated.
5222 The following code takes advantage of the fact that optional reloads
5223 are at the end of reload_order. */
5224 if (rld[r].optional != 0)
5225 for (i = 0; i < j; i++)
5226 if ((rld[reload_order[i]].out != 0
5227 || rld[reload_order[i]].in != 0
5228 || rld[reload_order[i]].secondary_p)
5229 && ! rld[reload_order[i]].optional
5230 && rld[reload_order[i]].reg_rtx == 0)
5231 allocate_reload_reg (chain, reload_order[i], 0);
5234 /* First see if this pseudo is already available as reloaded
5235 for a previous insn. We cannot try to inherit for reloads
5236 that are smaller than the maximum number of registers needed
5237 for groups unless the register we would allocate cannot be used
5240 We could check here to see if this is a secondary reload for
5241 an object that is already in a register of the desired class.
5242 This would avoid the need for the secondary reload register.
5243 But this is complex because we can't easily determine what
5244 objects might want to be loaded via this reload. So let a
5245 register be allocated here. In `emit_reload_insns' we suppress
5246 one of the loads in the case described above. */
5251 register int regno = -1;
5252 enum machine_mode mode = VOIDmode;
5256 else if (GET_CODE (rld[r].in) == REG)
5258 regno = REGNO (rld[r].in);
5259 mode = GET_MODE (rld[r].in);
5261 else if (GET_CODE (rld[r].in_reg) == REG)
5263 regno = REGNO (rld[r].in_reg);
5264 mode = GET_MODE (rld[r].in_reg);
5266 else if (GET_CODE (rld[r].in_reg) == SUBREG
5267 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5269 word = SUBREG_WORD (rld[r].in_reg);
5270 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5271 if (regno < FIRST_PSEUDO_REGISTER)
5273 mode = GET_MODE (rld[r].in_reg);
5276 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5277 || GET_CODE (rld[r].in_reg) == PRE_DEC
5278 || GET_CODE (rld[r].in_reg) == POST_INC
5279 || GET_CODE (rld[r].in_reg) == POST_DEC)
5280 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5282 regno = REGNO (XEXP (rld[r].in_reg, 0));
5283 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5284 rld[r].out = rld[r].in;
5288 /* This won't work, since REGNO can be a pseudo reg number.
5289 Also, it takes much more hair to keep track of all the things
5290 that can invalidate an inherited reload of part of a pseudoreg. */
5291 else if (GET_CODE (rld[r].in) == SUBREG
5292 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5293 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5296 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5298 enum reg_class class = rld[r].class, last_class;
5299 rtx last_reg = reg_last_reload_reg[regno];
5301 i = REGNO (last_reg) + word;
5302 last_class = REGNO_REG_CLASS (i);
5303 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5304 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5305 && reg_reloaded_contents[i] == regno
5306 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5307 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5308 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5309 /* Even if we can't use this register as a reload
5310 register, we might use it for reload_override_in,
5311 if copying it to the desired class is cheap
5313 || ((REGISTER_MOVE_COST (last_class, class)
5314 < MEMORY_MOVE_COST (mode, class, 1))
5315 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5316 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5320 #ifdef SECONDARY_MEMORY_NEEDED
5321 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5326 && (rld[r].nregs == max_group_size
5327 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5329 && reload_reg_free_for_value_p (i, rld[r].opnum,
5334 /* If a group is needed, verify that all the subsequent
5335 registers still have their values intact. */
5337 = HARD_REGNO_NREGS (i, rld[r].mode);
5340 for (k = 1; k < nr; k++)
5341 if (reg_reloaded_contents[i + k] != regno
5342 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5349 last_reg = (GET_MODE (last_reg) == mode
5350 ? last_reg : gen_rtx_REG (mode, i));
5352 /* We found a register that contains the
5353 value we need. If this register is the
5354 same as an `earlyclobber' operand of the
5355 current insn, just mark it as a place to
5356 reload from since we can't use it as the
5357 reload register itself. */
5359 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5360 if (reg_overlap_mentioned_for_reload_p
5361 (reg_last_reload_reg[regno],
5362 reload_earlyclobbers[i1]))
5365 if (i1 != n_earlyclobbers
5366 || ! (reload_reg_free_for_value_p
5367 (i, rld[r].opnum, rld[r].when_needed,
5368 rld[r].in, rld[r].out, r, 1))
5369 /* Don't use it if we'd clobber a pseudo reg. */
5370 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5372 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5373 /* Don't clobber the frame pointer. */
5374 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5375 /* Don't really use the inherited spill reg
5376 if we need it wider than we've got it. */
5377 || (GET_MODE_SIZE (rld[r].mode)
5378 > GET_MODE_SIZE (mode))
5379 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5382 /* If find_reloads chose reload_out as reload
5383 register, stay with it - that leaves the
5384 inherited register for subsequent reloads. */
5385 || (rld[r].out && rld[r].reg_rtx
5386 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5388 reload_override_in[r] = last_reg;
5389 reload_inheritance_insn[r]
5390 = reg_reloaded_insn[i];
5395 /* We can use this as a reload reg. */
5396 /* Mark the register as in use for this part of
5398 mark_reload_reg_in_use (i,
5402 rld[r].reg_rtx = last_reg;
5403 reload_inherited[r] = 1;
5404 reload_inheritance_insn[r]
5405 = reg_reloaded_insn[i];
5406 reload_spill_index[r] = i;
5407 for (k = 0; k < nr; k++)
5408 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5416 /* Here's another way to see if the value is already lying around. */
5419 && ! reload_inherited[r]
5421 && (CONSTANT_P (rld[r].in)
5422 || GET_CODE (rld[r].in) == PLUS
5423 || GET_CODE (rld[r].in) == REG
5424 || GET_CODE (rld[r].in) == MEM)
5425 && (rld[r].nregs == max_group_size
5426 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5427 search_equiv = rld[r].in;
5428 /* If this is an output reload from a simple move insn, look
5429 if an equivalence for the input is available. */
5430 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5432 rtx set = single_set (insn);
5435 && rtx_equal_p (rld[r].out, SET_DEST (set))
5436 && CONSTANT_P (SET_SRC (set)))
5437 search_equiv = SET_SRC (set);
5443 = find_equiv_reg (search_equiv, insn, rld[r].class,
5444 -1, NULL_PTR, 0, rld[r].mode);
5449 if (GET_CODE (equiv) == REG)
5450 regno = REGNO (equiv);
5451 else if (GET_CODE (equiv) == SUBREG)
5453 /* This must be a SUBREG of a hard register.
5454 Make a new REG since this might be used in an
5455 address and not all machines support SUBREGs
5457 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5458 equiv = gen_rtx_REG (rld[r].mode, regno);
5464 /* If we found a spill reg, reject it unless it is free
5465 and of the desired class. */
5467 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5468 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5472 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5476 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5479 /* We found a register that contains the value we need.
5480 If this register is the same as an `earlyclobber' operand
5481 of the current insn, just mark it as a place to reload from
5482 since we can't use it as the reload register itself. */
5485 for (i = 0; i < n_earlyclobbers; i++)
5486 if (reg_overlap_mentioned_for_reload_p (equiv,
5487 reload_earlyclobbers[i]))
5489 reload_override_in[r] = equiv;
5494 /* If the equiv register we have found is explicitly clobbered
5495 in the current insn, it depends on the reload type if we
5496 can use it, use it for reload_override_in, or not at all.
5497 In particular, we then can't use EQUIV for a
5498 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5500 if (equiv != 0 && regno_clobbered_p (regno, insn))
5502 switch (rld[r].when_needed)
5504 case RELOAD_FOR_OTHER_ADDRESS:
5505 case RELOAD_FOR_INPADDR_ADDRESS:
5506 case RELOAD_FOR_INPUT_ADDRESS:
5507 case RELOAD_FOR_OPADDR_ADDR:
5510 case RELOAD_FOR_INPUT:
5511 case RELOAD_FOR_OPERAND_ADDRESS:
5512 reload_override_in[r] = equiv;
5520 /* If we found an equivalent reg, say no code need be generated
5521 to load it, and use it as our reload reg. */
5522 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5524 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5526 rld[r].reg_rtx = equiv;
5527 reload_inherited[r] = 1;
5529 /* If reg_reloaded_valid is not set for this register,
5530 there might be a stale spill_reg_store lying around.
5531 We must clear it, since otherwise emit_reload_insns
5532 might delete the store. */
5533 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5534 spill_reg_store[regno] = NULL_RTX;
5535 /* If any of the hard registers in EQUIV are spill
5536 registers, mark them as in use for this insn. */
5537 for (k = 0; k < nr; k++)
5539 i = spill_reg_order[regno + k];
5542 mark_reload_reg_in_use (regno, rld[r].opnum,
5545 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5552 /* If we found a register to use already, or if this is an optional
5553 reload, we are done. */
5554 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5557 #if 0 /* No longer needed for correct operation. Might or might not
5558 give better code on the average. Want to experiment? */
5560 /* See if there is a later reload that has a class different from our
5561 class that intersects our class or that requires less register
5562 than our reload. If so, we must allocate a register to this
5563 reload now, since that reload might inherit a previous reload
5564 and take the only available register in our class. Don't do this
5565 for optional reloads since they will force all previous reloads
5566 to be allocated. Also don't do this for reloads that have been
5569 for (i = j + 1; i < n_reloads; i++)
5571 int s = reload_order[i];
5573 if ((rld[s].in == 0 && rld[s].out == 0
5574 && ! rld[s].secondary_p)
5578 if ((rld[s].class != rld[r].class
5579 && reg_classes_intersect_p (rld[r].class,
5581 || rld[s].nregs < rld[r].nregs)
5588 allocate_reload_reg (chain, r, j == n_reloads - 1);
5592 /* Now allocate reload registers for anything non-optional that
5593 didn't get one yet. */
5594 for (j = 0; j < n_reloads; j++)
5596 register int r = reload_order[j];
5598 /* Ignore reloads that got marked inoperative. */
5599 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5602 /* Skip reloads that already have a register allocated or are
5604 if (rld[r].reg_rtx != 0 || rld[r].optional)
5607 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5611 /* If that loop got all the way, we have won. */
5618 /* Loop around and try without any inheritance. */
5623 /* First undo everything done by the failed attempt
5624 to allocate with inheritance. */
5625 choose_reload_regs_init (chain, save_reload_reg_rtx);
5627 /* Some sanity tests to verify that the reloads found in the first
5628 pass are identical to the ones we have now. */
5629 if (chain->n_reloads != n_reloads)
5632 for (i = 0; i < n_reloads; i++)
5634 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5636 if (chain->rld[i].when_needed != rld[i].when_needed)
5638 for (j = 0; j < n_spills; j++)
5639 if (spill_regs[j] == chain->rld[i].regno)
5640 if (! set_reload_reg (j, i))
5641 failed_reload (chain->insn, i);
5645 /* If we thought we could inherit a reload, because it seemed that
5646 nothing else wanted the same reload register earlier in the insn,
5647 verify that assumption, now that all reloads have been assigned.
5648 Likewise for reloads where reload_override_in has been set. */
5650 /* If doing expensive optimizations, do one preliminary pass that doesn't
5651 cancel any inheritance, but removes reloads that have been needed only
5652 for reloads that we know can be inherited. */
5653 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5655 for (j = 0; j < n_reloads; j++)
5657 register int r = reload_order[j];
5659 if (reload_inherited[r] && rld[r].reg_rtx)
5660 check_reg = rld[r].reg_rtx;
5661 else if (reload_override_in[r]
5662 && (GET_CODE (reload_override_in[r]) == REG
5663 || GET_CODE (reload_override_in[r]) == SUBREG))
5664 check_reg = reload_override_in[r];
5667 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5671 (reload_inherited[r]
5672 ? rld[r].out : const0_rtx),
5677 reload_inherited[r] = 0;
5678 reload_override_in[r] = 0;
5680 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5681 reload_override_in, then we do not need its related
5682 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5683 likewise for other reload types.
5684 We handle this by removing a reload when its only replacement
5685 is mentioned in reload_in of the reload we are going to inherit.
5686 A special case are auto_inc expressions; even if the input is
5687 inherited, we still need the address for the output. We can
5688 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5689 If we suceeded removing some reload and we are doing a preliminary
5690 pass just to remove such reloads, make another pass, since the
5691 removal of one reload might allow us to inherit another one. */
5693 && rld[r].out != rld[r].in
5694 && remove_address_replacements (rld[r].in) && pass)
5699 /* Now that reload_override_in is known valid,
5700 actually override reload_in. */
5701 for (j = 0; j < n_reloads; j++)
5702 if (reload_override_in[j])
5703 rld[j].in = reload_override_in[j];
5705 /* If this reload won't be done because it has been cancelled or is
5706 optional and not inherited, clear reload_reg_rtx so other
5707 routines (such as subst_reloads) don't get confused. */
5708 for (j = 0; j < n_reloads; j++)
5709 if (rld[j].reg_rtx != 0
5710 && ((rld[j].optional && ! reload_inherited[j])
5711 || (rld[j].in == 0 && rld[j].out == 0
5712 && ! rld[j].secondary_p)))
5714 int regno = true_regnum (rld[j].reg_rtx);
5716 if (spill_reg_order[regno] >= 0)
5717 clear_reload_reg_in_use (regno, rld[j].opnum,
5718 rld[j].when_needed, rld[j].mode);
5720 reload_spill_index[j] = -1;
5723 /* Record which pseudos and which spill regs have output reloads. */
5724 for (j = 0; j < n_reloads; j++)
5726 register int r = reload_order[j];
5728 i = reload_spill_index[r];
5730 /* I is nonneg if this reload uses a register.
5731 If rld[r].reg_rtx is 0, this is an optional reload
5732 that we opted to ignore. */
5733 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5734 && rld[r].reg_rtx != 0)
5736 register int nregno = REGNO (rld[r].out_reg);
5739 if (nregno < FIRST_PSEUDO_REGISTER)
5740 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5743 reg_has_output_reload[nregno + nr] = 1;
5747 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5749 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5752 if (rld[r].when_needed != RELOAD_OTHER
5753 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5754 && rld[r].when_needed != RELOAD_FOR_INSN)
5760 /* Deallocate the reload register for reload R. This is called from
5761 remove_address_replacements. */
5764 deallocate_reload_reg (r)
5769 if (! rld[r].reg_rtx)
5771 regno = true_regnum (rld[r].reg_rtx);
5773 if (spill_reg_order[regno] >= 0)
5774 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5776 reload_spill_index[r] = -1;
5779 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5780 reloads of the same item for fear that we might not have enough reload
5781 registers. However, normally they will get the same reload register
5782 and hence actually need not be loaded twice.
5784 Here we check for the most common case of this phenomenon: when we have
5785 a number of reloads for the same object, each of which were allocated
5786 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5787 reload, and is not modified in the insn itself. If we find such,
5788 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5789 This will not increase the number of spill registers needed and will
5790 prevent redundant code. */
5793 merge_assigned_reloads (insn)
5798 /* Scan all the reloads looking for ones that only load values and
5799 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5800 assigned and not modified by INSN. */
5802 for (i = 0; i < n_reloads; i++)
5804 int conflicting_input = 0;
5805 int max_input_address_opnum = -1;
5806 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5808 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5809 || rld[i].out != 0 || rld[i].reg_rtx == 0
5810 || reg_set_p (rld[i].reg_rtx, insn))
5813 /* Look at all other reloads. Ensure that the only use of this
5814 reload_reg_rtx is in a reload that just loads the same value
5815 as we do. Note that any secondary reloads must be of the identical
5816 class since the values, modes, and result registers are the
5817 same, so we need not do anything with any secondary reloads. */
5819 for (j = 0; j < n_reloads; j++)
5821 if (i == j || rld[j].reg_rtx == 0
5822 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5826 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5827 && rld[j].opnum > max_input_address_opnum)
5828 max_input_address_opnum = rld[j].opnum;
5830 /* If the reload regs aren't exactly the same (e.g, different modes)
5831 or if the values are different, we can't merge this reload.
5832 But if it is an input reload, we might still merge
5833 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5835 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5836 || rld[j].out != 0 || rld[j].in == 0
5837 || ! rtx_equal_p (rld[i].in, rld[j].in))
5839 if (rld[j].when_needed != RELOAD_FOR_INPUT
5840 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5841 || rld[i].opnum > rld[j].opnum)
5842 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5844 conflicting_input = 1;
5845 if (min_conflicting_input_opnum > rld[j].opnum)
5846 min_conflicting_input_opnum = rld[j].opnum;
5850 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5851 we, in fact, found any matching reloads. */
5854 && max_input_address_opnum <= min_conflicting_input_opnum)
5856 for (j = 0; j < n_reloads; j++)
5857 if (i != j && rld[j].reg_rtx != 0
5858 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5859 && (! conflicting_input
5860 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5861 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5863 rld[i].when_needed = RELOAD_OTHER;
5865 reload_spill_index[j] = -1;
5866 transfer_replacements (i, j);
5869 /* If this is now RELOAD_OTHER, look for any reloads that load
5870 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5871 if they were for inputs, RELOAD_OTHER for outputs. Note that
5872 this test is equivalent to looking for reloads for this operand
5875 if (rld[i].when_needed == RELOAD_OTHER)
5876 for (j = 0; j < n_reloads; j++)
5878 && rld[i].when_needed != RELOAD_OTHER
5879 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5882 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5883 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5884 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5890 /* These arrays are filled by emit_reload_insns and its subroutines. */
5891 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5892 static rtx other_input_address_reload_insns = 0;
5893 static rtx other_input_reload_insns = 0;
5894 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5895 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5896 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5897 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5898 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5899 static rtx operand_reload_insns = 0;
5900 static rtx other_operand_reload_insns = 0;
5901 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5903 /* Values to be put in spill_reg_store are put here first. */
5904 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5905 static HARD_REG_SET reg_reloaded_died;
5907 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5908 has the number J. OLD contains the value to be used as input. */
5911 emit_input_reload_insns (chain, rl, old, j)
5912 struct insn_chain *chain;
5917 rtx insn = chain->insn;
5918 register rtx reloadreg = rl->reg_rtx;
5919 rtx oldequiv_reg = 0;
5922 enum machine_mode mode;
5925 /* Determine the mode to reload in.
5926 This is very tricky because we have three to choose from.
5927 There is the mode the insn operand wants (rl->inmode).
5928 There is the mode of the reload register RELOADREG.
5929 There is the intrinsic mode of the operand, which we could find
5930 by stripping some SUBREGs.
5931 It turns out that RELOADREG's mode is irrelevant:
5932 we can change that arbitrarily.
5934 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5935 then the reload reg may not support QImode moves, so use SImode.
5936 If foo is in memory due to spilling a pseudo reg, this is safe,
5937 because the QImode value is in the least significant part of a
5938 slot big enough for a SImode. If foo is some other sort of
5939 memory reference, then it is impossible to reload this case,
5940 so previous passes had better make sure this never happens.
5942 Then consider a one-word union which has SImode and one of its
5943 members is a float, being fetched as (SUBREG:SF union:SI).
5944 We must fetch that as SFmode because we could be loading into
5945 a float-only register. In this case OLD's mode is correct.
5947 Consider an immediate integer: it has VOIDmode. Here we need
5948 to get a mode from something else.
5950 In some cases, there is a fourth mode, the operand's
5951 containing mode. If the insn specifies a containing mode for
5952 this operand, it overrides all others.
5954 I am not sure whether the algorithm here is always right,
5955 but it does the right things in those cases. */
5957 mode = GET_MODE (old);
5958 if (mode == VOIDmode)
5961 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5962 /* If we need a secondary register for this operation, see if
5963 the value is already in a register in that class. Don't
5964 do this if the secondary register will be used as a scratch
5967 if (rl->secondary_in_reload >= 0
5968 && rl->secondary_in_icode == CODE_FOR_nothing
5971 = find_equiv_reg (old, insn,
5972 rld[rl->secondary_in_reload].class,
5973 -1, NULL_PTR, 0, mode);
5976 /* If reloading from memory, see if there is a register
5977 that already holds the same value. If so, reload from there.
5978 We can pass 0 as the reload_reg_p argument because
5979 any other reload has either already been emitted,
5980 in which case find_equiv_reg will see the reload-insn,
5981 or has yet to be emitted, in which case it doesn't matter
5982 because we will use this equiv reg right away. */
5984 if (oldequiv == 0 && optimize
5985 && (GET_CODE (old) == MEM
5986 || (GET_CODE (old) == REG
5987 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5988 && reg_renumber[REGNO (old)] < 0)))
5989 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5990 -1, NULL_PTR, 0, mode);
5994 unsigned int regno = true_regnum (oldequiv);
5996 /* Don't use OLDEQUIV if any other reload changes it at an
5997 earlier stage of this insn or at this stage. */
5998 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6000 rl->in, const0_rtx, j,
6004 /* If it is no cheaper to copy from OLDEQUIV into the
6005 reload register than it would be to move from memory,
6006 don't use it. Likewise, if we need a secondary register
6010 && ((REGNO_REG_CLASS (regno) != rl->class
6011 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6013 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6014 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6015 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6019 #ifdef SECONDARY_MEMORY_NEEDED
6020 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6028 /* delete_output_reload is only invoked properly if old contains
6029 the original pseudo register. Since this is replaced with a
6030 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6031 find the pseudo in RELOAD_IN_REG. */
6033 && reload_override_in[j]
6034 && GET_CODE (rl->in_reg) == REG)
6041 else if (GET_CODE (oldequiv) == REG)
6042 oldequiv_reg = oldequiv;
6043 else if (GET_CODE (oldequiv) == SUBREG)
6044 oldequiv_reg = SUBREG_REG (oldequiv);
6046 /* If we are reloading from a register that was recently stored in
6047 with an output-reload, see if we can prove there was
6048 actually no need to store the old value in it. */
6050 if (optimize && GET_CODE (oldequiv) == REG
6051 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6052 && spill_reg_store[REGNO (oldequiv)]
6053 && GET_CODE (old) == REG
6054 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6055 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6057 delete_output_reload (insn, j, REGNO (oldequiv));
6059 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6060 then load RELOADREG from OLDEQUIV. Note that we cannot use
6061 gen_lowpart_common since it can do the wrong thing when
6062 RELOADREG has a multi-word mode. Note that RELOADREG
6063 must always be a REG here. */
6065 if (GET_MODE (reloadreg) != mode)
6066 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6067 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6068 oldequiv = SUBREG_REG (oldequiv);
6069 if (GET_MODE (oldequiv) != VOIDmode
6070 && mode != GET_MODE (oldequiv))
6071 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6073 /* Switch to the right place to emit the reload insns. */
6074 switch (rl->when_needed)
6077 where = &other_input_reload_insns;
6079 case RELOAD_FOR_INPUT:
6080 where = &input_reload_insns[rl->opnum];
6082 case RELOAD_FOR_INPUT_ADDRESS:
6083 where = &input_address_reload_insns[rl->opnum];
6085 case RELOAD_FOR_INPADDR_ADDRESS:
6086 where = &inpaddr_address_reload_insns[rl->opnum];
6088 case RELOAD_FOR_OUTPUT_ADDRESS:
6089 where = &output_address_reload_insns[rl->opnum];
6091 case RELOAD_FOR_OUTADDR_ADDRESS:
6092 where = &outaddr_address_reload_insns[rl->opnum];
6094 case RELOAD_FOR_OPERAND_ADDRESS:
6095 where = &operand_reload_insns;
6097 case RELOAD_FOR_OPADDR_ADDR:
6098 where = &other_operand_reload_insns;
6100 case RELOAD_FOR_OTHER_ADDRESS:
6101 where = &other_input_address_reload_insns;
6107 push_to_sequence (*where);
6109 /* Auto-increment addresses must be reloaded in a special way. */
6110 if (rl->out && ! rl->out_reg)
6112 /* We are not going to bother supporting the case where a
6113 incremented register can't be copied directly from
6114 OLDEQUIV since this seems highly unlikely. */
6115 if (rl->secondary_in_reload >= 0)
6118 if (reload_inherited[j])
6119 oldequiv = reloadreg;
6121 old = XEXP (rl->in_reg, 0);
6123 if (optimize && GET_CODE (oldequiv) == REG
6124 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6125 && spill_reg_store[REGNO (oldequiv)]
6126 && GET_CODE (old) == REG
6127 && (dead_or_set_p (insn,
6128 spill_reg_stored_to[REGNO (oldequiv)])
6129 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6131 delete_output_reload (insn, j, REGNO (oldequiv));
6133 /* Prevent normal processing of this reload. */
6135 /* Output a special code sequence for this case. */
6136 new_spill_reg_store[REGNO (reloadreg)]
6137 = inc_for_reload (reloadreg, oldequiv, rl->out,
6141 /* If we are reloading a pseudo-register that was set by the previous
6142 insn, see if we can get rid of that pseudo-register entirely
6143 by redirecting the previous insn into our reload register. */
6145 else if (optimize && GET_CODE (old) == REG
6146 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6147 && dead_or_set_p (insn, old)
6148 /* This is unsafe if some other reload
6149 uses the same reg first. */
6150 && reload_reg_free_for_value_p (REGNO (reloadreg),
6156 rtx temp = PREV_INSN (insn);
6157 while (temp && GET_CODE (temp) == NOTE)
6158 temp = PREV_INSN (temp);
6160 && GET_CODE (temp) == INSN
6161 && GET_CODE (PATTERN (temp)) == SET
6162 && SET_DEST (PATTERN (temp)) == old
6163 /* Make sure we can access insn_operand_constraint. */
6164 && asm_noperands (PATTERN (temp)) < 0
6165 /* This is unsafe if prev insn rejects our reload reg. */
6166 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6168 /* This is unsafe if operand occurs more than once in current
6169 insn. Perhaps some occurrences aren't reloaded. */
6170 && count_occurrences (PATTERN (insn), old) == 1
6171 /* Don't risk splitting a matching pair of operands. */
6172 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6174 /* Store into the reload register instead of the pseudo. */
6175 SET_DEST (PATTERN (temp)) = reloadreg;
6177 /* If the previous insn is an output reload, the source is
6178 a reload register, and its spill_reg_store entry will
6179 contain the previous destination. This is now
6181 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6182 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6184 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6185 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6188 /* If these are the only uses of the pseudo reg,
6189 pretend for GDB it lives in the reload reg we used. */
6190 if (REG_N_DEATHS (REGNO (old)) == 1
6191 && REG_N_SETS (REGNO (old)) == 1)
6193 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6194 alter_reg (REGNO (old), -1);
6200 /* We can't do that, so output an insn to load RELOADREG. */
6202 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6203 /* If we have a secondary reload, pick up the secondary register
6204 and icode, if any. If OLDEQUIV and OLD are different or
6205 if this is an in-out reload, recompute whether or not we
6206 still need a secondary register and what the icode should
6207 be. If we still need a secondary register and the class or
6208 icode is different, go back to reloading from OLD if using
6209 OLDEQUIV means that we got the wrong type of register. We
6210 cannot have different class or icode due to an in-out reload
6211 because we don't make such reloads when both the input and
6212 output need secondary reload registers. */
6214 if (! special && rl->secondary_in_reload >= 0)
6216 rtx second_reload_reg = 0;
6217 int secondary_reload = rl->secondary_in_reload;
6218 rtx real_oldequiv = oldequiv;
6221 enum insn_code icode;
6223 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6224 and similarly for OLD.
6225 See comments in get_secondary_reload in reload.c. */
6226 /* If it is a pseudo that cannot be replaced with its
6227 equivalent MEM, we must fall back to reload_in, which
6228 will have all the necessary substitutions registered.
6229 Likewise for a pseudo that can't be replaced with its
6230 equivalent constant.
6232 Take extra care for subregs of such pseudos. Note that
6233 we cannot use reg_equiv_mem in this case because it is
6234 not in the right mode. */
6237 if (GET_CODE (tmp) == SUBREG)
6238 tmp = SUBREG_REG (tmp);
6239 if (GET_CODE (tmp) == REG
6240 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6241 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6242 || reg_equiv_constant[REGNO (tmp)] != 0))
6244 if (! reg_equiv_mem[REGNO (tmp)]
6245 || num_not_at_initial_offset
6246 || GET_CODE (oldequiv) == SUBREG)
6247 real_oldequiv = rl->in;
6249 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6253 if (GET_CODE (tmp) == SUBREG)
6254 tmp = SUBREG_REG (tmp);
6255 if (GET_CODE (tmp) == REG
6256 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6257 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6258 || reg_equiv_constant[REGNO (tmp)] != 0))
6260 if (! reg_equiv_mem[REGNO (tmp)]
6261 || num_not_at_initial_offset
6262 || GET_CODE (old) == SUBREG)
6265 real_old = reg_equiv_mem[REGNO (tmp)];
6268 second_reload_reg = rld[secondary_reload].reg_rtx;
6269 icode = rl->secondary_in_icode;
6271 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6272 || (rl->in != 0 && rl->out != 0))
6274 enum reg_class new_class
6275 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6276 mode, real_oldequiv);
6278 if (new_class == NO_REGS)
6279 second_reload_reg = 0;
6282 enum insn_code new_icode;
6283 enum machine_mode new_mode;
6285 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6286 REGNO (second_reload_reg)))
6287 oldequiv = old, real_oldequiv = real_old;
6290 new_icode = reload_in_optab[(int) mode];
6291 if (new_icode != CODE_FOR_nothing
6292 && ((insn_data[(int) new_icode].operand[0].predicate
6293 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6295 || (insn_data[(int) new_icode].operand[1].predicate
6296 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6297 (real_oldequiv, mode)))))
6298 new_icode = CODE_FOR_nothing;
6300 if (new_icode == CODE_FOR_nothing)
6303 new_mode = insn_data[(int) new_icode].operand[2].mode;
6305 if (GET_MODE (second_reload_reg) != new_mode)
6307 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6309 oldequiv = old, real_oldequiv = real_old;
6312 = gen_rtx_REG (new_mode,
6313 REGNO (second_reload_reg));
6319 /* If we still need a secondary reload register, check
6320 to see if it is being used as a scratch or intermediate
6321 register and generate code appropriately. If we need
6322 a scratch register, use REAL_OLDEQUIV since the form of
6323 the insn may depend on the actual address if it is
6326 if (second_reload_reg)
6328 if (icode != CODE_FOR_nothing)
6330 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6331 second_reload_reg));
6336 /* See if we need a scratch register to load the
6337 intermediate register (a tertiary reload). */
6338 enum insn_code tertiary_icode
6339 = rld[secondary_reload].secondary_in_icode;
6341 if (tertiary_icode != CODE_FOR_nothing)
6343 rtx third_reload_reg
6344 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6346 emit_insn ((GEN_FCN (tertiary_icode)
6347 (second_reload_reg, real_oldequiv,
6348 third_reload_reg)));
6351 gen_reload (second_reload_reg, real_oldequiv,
6355 oldequiv = second_reload_reg;
6361 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6363 rtx real_oldequiv = oldequiv;
6365 if ((GET_CODE (oldequiv) == REG
6366 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6367 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6368 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6369 || (GET_CODE (oldequiv) == SUBREG
6370 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6371 && (REGNO (SUBREG_REG (oldequiv))
6372 >= FIRST_PSEUDO_REGISTER)
6373 && ((reg_equiv_memory_loc
6374 [REGNO (SUBREG_REG (oldequiv))] != 0)
6375 || (reg_equiv_constant
6376 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6377 real_oldequiv = rl->in;
6378 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6382 /* End this sequence. */
6383 *where = get_insns ();
6386 /* Update reload_override_in so that delete_address_reloads_1
6387 can see the actual register usage. */
6389 reload_override_in[j] = oldequiv;
6392 /* Generate insns to for the output reload RL, which is for the insn described
6393 by CHAIN and has the number J. */
6395 emit_output_reload_insns (chain, rl, j)
6396 struct insn_chain *chain;
6400 rtx reloadreg = rl->reg_rtx;
6401 rtx insn = chain->insn;
6404 enum machine_mode mode = GET_MODE (old);
6407 if (rl->when_needed == RELOAD_OTHER)
6410 push_to_sequence (output_reload_insns[rl->opnum]);
6412 /* Determine the mode to reload in.
6413 See comments above (for input reloading). */
6415 if (mode == VOIDmode)
6417 /* VOIDmode should never happen for an output. */
6418 if (asm_noperands (PATTERN (insn)) < 0)
6419 /* It's the compiler's fault. */
6420 fatal_insn ("VOIDmode on an output", insn);
6421 error_for_asm (insn, "output operand is constant in `asm'");
6422 /* Prevent crash--use something we know is valid. */
6424 old = gen_rtx_REG (mode, REGNO (reloadreg));
6427 if (GET_MODE (reloadreg) != mode)
6428 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6430 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6432 /* If we need two reload regs, set RELOADREG to the intermediate
6433 one, since it will be stored into OLD. We might need a secondary
6434 register only for an input reload, so check again here. */
6436 if (rl->secondary_out_reload >= 0)
6440 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6441 && reg_equiv_mem[REGNO (old)] != 0)
6442 real_old = reg_equiv_mem[REGNO (old)];
6444 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6448 rtx second_reloadreg = reloadreg;
6449 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6451 /* See if RELOADREG is to be used as a scratch register
6452 or as an intermediate register. */
6453 if (rl->secondary_out_icode != CODE_FOR_nothing)
6455 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6456 (real_old, second_reloadreg, reloadreg)));
6461 /* See if we need both a scratch and intermediate reload
6464 int secondary_reload = rl->secondary_out_reload;
6465 enum insn_code tertiary_icode
6466 = rld[secondary_reload].secondary_out_icode;
6468 if (GET_MODE (reloadreg) != mode)
6469 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6471 if (tertiary_icode != CODE_FOR_nothing)
6474 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6477 /* Copy primary reload reg to secondary reload reg.
6478 (Note that these have been swapped above, then
6479 secondary reload reg to OLD using our insn. */
6481 /* If REAL_OLD is a paradoxical SUBREG, remove it
6482 and try to put the opposite SUBREG on
6484 if (GET_CODE (real_old) == SUBREG
6485 && (GET_MODE_SIZE (GET_MODE (real_old))
6486 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6487 && 0 != (tem = gen_lowpart_common
6488 (GET_MODE (SUBREG_REG (real_old)),
6490 real_old = SUBREG_REG (real_old), reloadreg = tem;
6492 gen_reload (reloadreg, second_reloadreg,
6493 rl->opnum, rl->when_needed);
6494 emit_insn ((GEN_FCN (tertiary_icode)
6495 (real_old, reloadreg, third_reloadreg)));
6500 /* Copy between the reload regs here and then to
6503 gen_reload (reloadreg, second_reloadreg,
6504 rl->opnum, rl->when_needed);
6510 /* Output the last reload insn. */
6515 /* Don't output the last reload if OLD is not the dest of
6516 INSN and is in the src and is clobbered by INSN. */
6517 if (! flag_expensive_optimizations
6518 || GET_CODE (old) != REG
6519 || !(set = single_set (insn))
6520 || rtx_equal_p (old, SET_DEST (set))
6521 || !reg_mentioned_p (old, SET_SRC (set))
6522 || !regno_clobbered_p (REGNO (old), insn))
6523 gen_reload (old, reloadreg, rl->opnum,
6527 /* Look at all insns we emitted, just to be safe. */
6528 for (p = get_insns (); p; p = NEXT_INSN (p))
6529 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6531 rtx pat = PATTERN (p);
6533 /* If this output reload doesn't come from a spill reg,
6534 clear any memory of reloaded copies of the pseudo reg.
6535 If this output reload comes from a spill reg,
6536 reg_has_output_reload will make this do nothing. */
6537 note_stores (pat, forget_old_reloads_1, NULL);
6539 if (reg_mentioned_p (rl->reg_rtx, pat))
6541 rtx set = single_set (insn);
6542 if (reload_spill_index[j] < 0
6544 && SET_SRC (set) == rl->reg_rtx)
6546 int src = REGNO (SET_SRC (set));
6548 reload_spill_index[j] = src;
6549 SET_HARD_REG_BIT (reg_is_output_reload, src);
6550 if (find_regno_note (insn, REG_DEAD, src))
6551 SET_HARD_REG_BIT (reg_reloaded_died, src);
6553 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6555 int s = rl->secondary_out_reload;
6556 set = single_set (p);
6557 /* If this reload copies only to the secondary reload
6558 register, the secondary reload does the actual
6560 if (s >= 0 && set == NULL_RTX)
6561 ; /* We can't tell what function the secondary reload
6562 has and where the actual store to the pseudo is
6563 made; leave new_spill_reg_store alone. */
6565 && SET_SRC (set) == rl->reg_rtx
6566 && SET_DEST (set) == rld[s].reg_rtx)
6568 /* Usually the next instruction will be the
6569 secondary reload insn; if we can confirm
6570 that it is, setting new_spill_reg_store to
6571 that insn will allow an extra optimization. */
6572 rtx s_reg = rld[s].reg_rtx;
6573 rtx next = NEXT_INSN (p);
6574 rld[s].out = rl->out;
6575 rld[s].out_reg = rl->out_reg;
6576 set = single_set (next);
6577 if (set && SET_SRC (set) == s_reg
6578 && ! new_spill_reg_store[REGNO (s_reg)])
6580 SET_HARD_REG_BIT (reg_is_output_reload,
6582 new_spill_reg_store[REGNO (s_reg)] = next;
6586 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6591 if (rl->when_needed == RELOAD_OTHER)
6593 emit_insns (other_output_reload_insns[rl->opnum]);
6594 other_output_reload_insns[rl->opnum] = get_insns ();
6597 output_reload_insns[rl->opnum] = get_insns ();
6602 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6603 and has the number J. */
6605 do_input_reload (chain, rl, j)
6606 struct insn_chain *chain;
6610 int expect_occurrences = 1;
6611 rtx insn = chain->insn;
6612 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6613 ? rl->in_reg : rl->in);
6616 /* AUTO_INC reloads need to be handled even if inherited. We got an
6617 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6618 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6619 && ! rtx_equal_p (rl->reg_rtx, old)
6620 && rl->reg_rtx != 0)
6621 emit_input_reload_insns (chain, rld + j, old, j);
6623 /* When inheriting a wider reload, we have a MEM in rl->in,
6624 e.g. inheriting a SImode output reload for
6625 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6626 if (optimize && reload_inherited[j] && rl->in
6627 && GET_CODE (rl->in) == MEM
6628 && GET_CODE (rl->in_reg) == MEM
6629 && reload_spill_index[j] >= 0
6630 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6633 = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1;
6635 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6638 /* If we are reloading a register that was recently stored in with an
6639 output-reload, see if we can prove there was
6640 actually no need to store the old value in it. */
6643 && (reload_inherited[j] || reload_override_in[j])
6645 && GET_CODE (rl->reg_rtx) == REG
6646 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6648 /* There doesn't seem to be any reason to restrict this to pseudos
6649 and doing so loses in the case where we are copying from a
6650 register of the wrong class. */
6651 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6652 >= FIRST_PSEUDO_REGISTER)
6654 /* The insn might have already some references to stackslots
6655 replaced by MEMs, while reload_out_reg still names the
6657 && (dead_or_set_p (insn,
6658 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6659 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6661 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6664 /* Do output reloading for reload RL, which is for the insn described by
6665 CHAIN and has the number J.
6666 ??? At some point we need to support handling output reloads of
6667 JUMP_INSNs or insns that set cc0. */
6669 do_output_reload (chain, rl, j)
6670 struct insn_chain *chain;
6675 rtx insn = chain->insn;
6676 /* If this is an output reload that stores something that is
6677 not loaded in this same reload, see if we can eliminate a previous
6679 rtx pseudo = rl->out_reg;
6682 && GET_CODE (pseudo) == REG
6683 && ! rtx_equal_p (rl->in_reg, pseudo)
6684 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6685 && reg_last_reload_reg[REGNO (pseudo)])
6687 int pseudo_no = REGNO (pseudo);
6688 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6690 /* We don't need to test full validity of last_regno for
6691 inherit here; we only want to know if the store actually
6692 matches the pseudo. */
6693 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6694 && reg_reloaded_contents[last_regno] == pseudo_no
6695 && spill_reg_store[last_regno]
6696 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6697 delete_output_reload (insn, j, last_regno);
6702 || rl->reg_rtx == old
6703 || rl->reg_rtx == 0)
6706 /* An output operand that dies right away does need a reload,
6707 but need not be copied from it. Show the new location in the
6709 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6710 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6712 XEXP (note, 0) = rl->reg_rtx;
6715 /* Likewise for a SUBREG of an operand that dies. */
6716 else if (GET_CODE (old) == SUBREG
6717 && GET_CODE (SUBREG_REG (old)) == REG
6718 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6721 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6725 else if (GET_CODE (old) == SCRATCH)
6726 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6727 but we don't want to make an output reload. */
6730 /* If is a JUMP_INSN, we can't support output reloads yet. */
6731 if (GET_CODE (insn) == JUMP_INSN)
6734 emit_output_reload_insns (chain, rld + j, j);
6737 /* Output insns to reload values in and out of the chosen reload regs. */
6740 emit_reload_insns (chain)
6741 struct insn_chain *chain;
6743 rtx insn = chain->insn;
6746 rtx following_insn = NEXT_INSN (insn);
6747 rtx before_insn = PREV_INSN (insn);
6749 CLEAR_HARD_REG_SET (reg_reloaded_died);
6751 for (j = 0; j < reload_n_operands; j++)
6752 input_reload_insns[j] = input_address_reload_insns[j]
6753 = inpaddr_address_reload_insns[j]
6754 = output_reload_insns[j] = output_address_reload_insns[j]
6755 = outaddr_address_reload_insns[j]
6756 = other_output_reload_insns[j] = 0;
6757 other_input_address_reload_insns = 0;
6758 other_input_reload_insns = 0;
6759 operand_reload_insns = 0;
6760 other_operand_reload_insns = 0;
6762 /* Now output the instructions to copy the data into and out of the
6763 reload registers. Do these in the order that the reloads were reported,
6764 since reloads of base and index registers precede reloads of operands
6765 and the operands may need the base and index registers reloaded. */
6767 for (j = 0; j < n_reloads; j++)
6770 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6771 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6773 do_input_reload (chain, rld + j, j);
6774 do_output_reload (chain, rld + j, j);
6777 /* Now write all the insns we made for reloads in the order expected by
6778 the allocation functions. Prior to the insn being reloaded, we write
6779 the following reloads:
6781 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6783 RELOAD_OTHER reloads.
6785 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6786 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6787 RELOAD_FOR_INPUT reload for the operand.
6789 RELOAD_FOR_OPADDR_ADDRS reloads.
6791 RELOAD_FOR_OPERAND_ADDRESS reloads.
6793 After the insn being reloaded, we write the following:
6795 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6796 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6797 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6798 reloads for the operand. The RELOAD_OTHER output reloads are
6799 output in descending order by reload number. */
6801 emit_insns_before (other_input_address_reload_insns, insn);
6802 emit_insns_before (other_input_reload_insns, insn);
6804 for (j = 0; j < reload_n_operands; j++)
6806 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6807 emit_insns_before (input_address_reload_insns[j], insn);
6808 emit_insns_before (input_reload_insns[j], insn);
6811 emit_insns_before (other_operand_reload_insns, insn);
6812 emit_insns_before (operand_reload_insns, insn);
6814 for (j = 0; j < reload_n_operands; j++)
6816 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6817 emit_insns_before (output_address_reload_insns[j], following_insn);
6818 emit_insns_before (output_reload_insns[j], following_insn);
6819 emit_insns_before (other_output_reload_insns[j], following_insn);
6822 /* Keep basic block info up to date. */
6825 if (BLOCK_HEAD (chain->block) == insn)
6826 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6827 if (BLOCK_END (chain->block) == insn)
6828 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6831 /* For all the spill regs newly reloaded in this instruction,
6832 record what they were reloaded from, so subsequent instructions
6833 can inherit the reloads.
6835 Update spill_reg_store for the reloads of this insn.
6836 Copy the elements that were updated in the loop above. */
6838 for (j = 0; j < n_reloads; j++)
6840 register int r = reload_order[j];
6841 register int i = reload_spill_index[r];
6843 /* If this is a non-inherited input reload from a pseudo, we must
6844 clear any memory of a previous store to the same pseudo. Only do
6845 something if there will not be an output reload for the pseudo
6847 if (rld[r].in_reg != 0
6848 && ! (reload_inherited[r] || reload_override_in[r]))
6850 rtx reg = rld[r].in_reg;
6852 if (GET_CODE (reg) == SUBREG)
6853 reg = SUBREG_REG (reg);
6855 if (GET_CODE (reg) == REG
6856 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6857 && ! reg_has_output_reload[REGNO (reg)])
6859 int nregno = REGNO (reg);
6861 if (reg_last_reload_reg[nregno])
6863 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6865 if (reg_reloaded_contents[last_regno] == nregno)
6866 spill_reg_store[last_regno] = 0;
6871 /* I is nonneg if this reload used a register.
6872 If rld[r].reg_rtx is 0, this is an optional reload
6873 that we opted to ignore. */
6875 if (i >= 0 && rld[r].reg_rtx != 0)
6878 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6880 int part_reaches_end = 0;
6881 int all_reaches_end = 1;
6883 /* For a multi register reload, we need to check if all or part
6884 of the value lives to the end. */
6885 for (k = 0; k < nr; k++)
6887 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6888 rld[r].when_needed))
6889 part_reaches_end = 1;
6891 all_reaches_end = 0;
6894 /* Ignore reloads that don't reach the end of the insn in
6896 if (all_reaches_end)
6898 /* First, clear out memory of what used to be in this spill reg.
6899 If consecutive registers are used, clear them all. */
6901 for (k = 0; k < nr; k++)
6902 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6904 /* Maybe the spill reg contains a copy of reload_out. */
6906 && (GET_CODE (rld[r].out) == REG
6910 || GET_CODE (rld[r].out_reg) == REG))
6912 rtx out = (GET_CODE (rld[r].out) == REG
6916 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6917 register int nregno = REGNO (out);
6918 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6919 : HARD_REGNO_NREGS (nregno,
6920 GET_MODE (rld[r].reg_rtx)));
6922 spill_reg_store[i] = new_spill_reg_store[i];
6923 spill_reg_stored_to[i] = out;
6924 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6926 /* If NREGNO is a hard register, it may occupy more than
6927 one register. If it does, say what is in the
6928 rest of the registers assuming that both registers
6929 agree on how many words the object takes. If not,
6930 invalidate the subsequent registers. */
6932 if (nregno < FIRST_PSEUDO_REGISTER)
6933 for (k = 1; k < nnr; k++)
6934 reg_last_reload_reg[nregno + k]
6936 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6937 REGNO (rld[r].reg_rtx) + k)
6940 /* Now do the inverse operation. */
6941 for (k = 0; k < nr; k++)
6943 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6944 reg_reloaded_contents[i + k]
6945 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6948 reg_reloaded_insn[i + k] = insn;
6949 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6953 /* Maybe the spill reg contains a copy of reload_in. Only do
6954 something if there will not be an output reload for
6955 the register being reloaded. */
6956 else if (rld[r].out_reg == 0
6958 && ((GET_CODE (rld[r].in) == REG
6959 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6960 && ! reg_has_output_reload[REGNO (rld[r].in)])
6961 || (GET_CODE (rld[r].in_reg) == REG
6962 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6963 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6965 register int nregno;
6968 if (GET_CODE (rld[r].in) == REG
6969 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6970 nregno = REGNO (rld[r].in);
6971 else if (GET_CODE (rld[r].in_reg) == REG)
6972 nregno = REGNO (rld[r].in_reg);
6974 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6976 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6977 : HARD_REGNO_NREGS (nregno,
6978 GET_MODE (rld[r].reg_rtx)));
6980 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6982 if (nregno < FIRST_PSEUDO_REGISTER)
6983 for (k = 1; k < nnr; k++)
6984 reg_last_reload_reg[nregno + k]
6986 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6987 REGNO (rld[r].reg_rtx) + k)
6990 /* Unless we inherited this reload, show we haven't
6991 recently done a store.
6992 Previous stores of inherited auto_inc expressions
6993 also have to be discarded. */
6994 if (! reload_inherited[r]
6995 || (rld[r].out && ! rld[r].out_reg))
6996 spill_reg_store[i] = 0;
6998 for (k = 0; k < nr; k++)
7000 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7001 reg_reloaded_contents[i + k]
7002 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7005 reg_reloaded_insn[i + k] = insn;
7006 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7011 /* However, if part of the reload reaches the end, then we must
7012 invalidate the old info for the part that survives to the end. */
7013 else if (part_reaches_end)
7015 for (k = 0; k < nr; k++)
7016 if (reload_reg_reaches_end_p (i + k,
7018 rld[r].when_needed))
7019 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7023 /* The following if-statement was #if 0'd in 1.34 (or before...).
7024 It's reenabled in 1.35 because supposedly nothing else
7025 deals with this problem. */
7027 /* If a register gets output-reloaded from a non-spill register,
7028 that invalidates any previous reloaded copy of it.
7029 But forget_old_reloads_1 won't get to see it, because
7030 it thinks only about the original insn. So invalidate it here. */
7031 if (i < 0 && rld[r].out != 0
7032 && (GET_CODE (rld[r].out) == REG
7033 || (GET_CODE (rld[r].out) == MEM
7034 && GET_CODE (rld[r].out_reg) == REG)))
7036 rtx out = (GET_CODE (rld[r].out) == REG
7037 ? rld[r].out : rld[r].out_reg);
7038 register int nregno = REGNO (out);
7039 if (nregno >= FIRST_PSEUDO_REGISTER)
7041 rtx src_reg, store_insn = NULL_RTX;
7043 reg_last_reload_reg[nregno] = 0;
7045 /* If we can find a hard register that is stored, record
7046 the storing insn so that we may delete this insn with
7047 delete_output_reload. */
7048 src_reg = rld[r].reg_rtx;
7050 /* If this is an optional reload, try to find the source reg
7051 from an input reload. */
7054 rtx set = single_set (insn);
7055 if (set && SET_DEST (set) == rld[r].out)
7059 src_reg = SET_SRC (set);
7061 for (k = 0; k < n_reloads; k++)
7063 if (rld[k].in == src_reg)
7065 src_reg = rld[k].reg_rtx;
7072 store_insn = new_spill_reg_store[REGNO (src_reg)];
7073 if (src_reg && GET_CODE (src_reg) == REG
7074 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7076 int src_regno = REGNO (src_reg);
7077 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7078 /* The place where to find a death note varies with
7079 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7080 necessarily checked exactly in the code that moves
7081 notes, so just check both locations. */
7082 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7084 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7087 spill_reg_store[src_regno + nr] = store_insn;
7088 spill_reg_stored_to[src_regno + nr] = out;
7089 reg_reloaded_contents[src_regno + nr] = nregno;
7090 reg_reloaded_insn[src_regno + nr] = store_insn;
7091 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7092 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7093 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7095 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7097 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7099 reg_last_reload_reg[nregno] = src_reg;
7104 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7106 while (num_regs-- > 0)
7107 reg_last_reload_reg[nregno + num_regs] = 0;
7111 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7114 /* Emit code to perform a reload from IN (which may be a reload register) to
7115 OUT (which may also be a reload register). IN or OUT is from operand
7116 OPNUM with reload type TYPE.
7118 Returns first insn emitted. */
7121 gen_reload (out, in, opnum, type)
7125 enum reload_type type;
7127 rtx last = get_last_insn ();
7130 /* If IN is a paradoxical SUBREG, remove it and try to put the
7131 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7132 if (GET_CODE (in) == SUBREG
7133 && (GET_MODE_SIZE (GET_MODE (in))
7134 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7135 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7136 in = SUBREG_REG (in), out = tem;
7137 else if (GET_CODE (out) == SUBREG
7138 && (GET_MODE_SIZE (GET_MODE (out))
7139 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7140 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7141 out = SUBREG_REG (out), in = tem;
7143 /* How to do this reload can get quite tricky. Normally, we are being
7144 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7145 register that didn't get a hard register. In that case we can just
7146 call emit_move_insn.
7148 We can also be asked to reload a PLUS that adds a register or a MEM to
7149 another register, constant or MEM. This can occur during frame pointer
7150 elimination and while reloading addresses. This case is handled by
7151 trying to emit a single insn to perform the add. If it is not valid,
7152 we use a two insn sequence.
7154 Finally, we could be called to handle an 'o' constraint by putting
7155 an address into a register. In that case, we first try to do this
7156 with a named pattern of "reload_load_address". If no such pattern
7157 exists, we just emit a SET insn and hope for the best (it will normally
7158 be valid on machines that use 'o').
7160 This entire process is made complex because reload will never
7161 process the insns we generate here and so we must ensure that
7162 they will fit their constraints and also by the fact that parts of
7163 IN might be being reloaded separately and replaced with spill registers.
7164 Because of this, we are, in some sense, just guessing the right approach
7165 here. The one listed above seems to work.
7167 ??? At some point, this whole thing needs to be rethought. */
7169 if (GET_CODE (in) == PLUS
7170 && (GET_CODE (XEXP (in, 0)) == REG
7171 || GET_CODE (XEXP (in, 0)) == SUBREG
7172 || GET_CODE (XEXP (in, 0)) == MEM)
7173 && (GET_CODE (XEXP (in, 1)) == REG
7174 || GET_CODE (XEXP (in, 1)) == SUBREG
7175 || CONSTANT_P (XEXP (in, 1))
7176 || GET_CODE (XEXP (in, 1)) == MEM))
7178 /* We need to compute the sum of a register or a MEM and another
7179 register, constant, or MEM, and put it into the reload
7180 register. The best possible way of doing this is if the machine
7181 has a three-operand ADD insn that accepts the required operands.
7183 The simplest approach is to try to generate such an insn and see if it
7184 is recognized and matches its constraints. If so, it can be used.
7186 It might be better not to actually emit the insn unless it is valid,
7187 but we need to pass the insn as an operand to `recog' and
7188 `extract_insn' and it is simpler to emit and then delete the insn if
7189 not valid than to dummy things up. */
7191 rtx op0, op1, tem, insn;
7194 op0 = find_replacement (&XEXP (in, 0));
7195 op1 = find_replacement (&XEXP (in, 1));
7197 /* Since constraint checking is strict, commutativity won't be
7198 checked, so we need to do that here to avoid spurious failure
7199 if the add instruction is two-address and the second operand
7200 of the add is the same as the reload reg, which is frequently
7201 the case. If the insn would be A = B + A, rearrange it so
7202 it will be A = A + B as constrain_operands expects. */
7204 if (GET_CODE (XEXP (in, 1)) == REG
7205 && REGNO (out) == REGNO (XEXP (in, 1)))
7206 tem = op0, op0 = op1, op1 = tem;
7208 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7209 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7211 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7212 code = recog_memoized (insn);
7216 extract_insn (insn);
7217 /* We want constrain operands to treat this insn strictly in
7218 its validity determination, i.e., the way it would after reload
7220 if (constrain_operands (1))
7224 delete_insns_since (last);
7226 /* If that failed, we must use a conservative two-insn sequence.
7228 Use a move to copy one operand into the reload register. Prefer
7229 to reload a constant, MEM or pseudo since the move patterns can
7230 handle an arbitrary operand. If OP1 is not a constant, MEM or
7231 pseudo and OP1 is not a valid operand for an add instruction, then
7234 After reloading one of the operands into the reload register, add
7235 the reload register to the output register.
7237 If there is another way to do this for a specific machine, a
7238 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7241 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7243 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7244 || (GET_CODE (op1) == REG
7245 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7246 || (code != CODE_FOR_nothing
7247 && ! ((*insn_data[code].operand[2].predicate)
7248 (op1, insn_data[code].operand[2].mode))))
7249 tem = op0, op0 = op1, op1 = tem;
7251 gen_reload (out, op0, opnum, type);
7253 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7254 This fixes a problem on the 32K where the stack pointer cannot
7255 be used as an operand of an add insn. */
7257 if (rtx_equal_p (op0, op1))
7260 insn = emit_insn (gen_add2_insn (out, op1));
7262 /* If that failed, copy the address register to the reload register.
7263 Then add the constant to the reload register. */
7265 code = recog_memoized (insn);
7269 extract_insn (insn);
7270 /* We want constrain operands to treat this insn strictly in
7271 its validity determination, i.e., the way it would after reload
7273 if (constrain_operands (1))
7275 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7277 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7282 delete_insns_since (last);
7284 gen_reload (out, op1, opnum, type);
7285 insn = emit_insn (gen_add2_insn (out, op0));
7286 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7289 #ifdef SECONDARY_MEMORY_NEEDED
7290 /* If we need a memory location to do the move, do it that way. */
7291 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7292 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7293 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7294 REGNO_REG_CLASS (REGNO (out)),
7297 /* Get the memory to use and rewrite both registers to its mode. */
7298 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7300 if (GET_MODE (loc) != GET_MODE (out))
7301 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7303 if (GET_MODE (loc) != GET_MODE (in))
7304 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7306 gen_reload (loc, in, opnum, type);
7307 gen_reload (out, loc, opnum, type);
7311 /* If IN is a simple operand, use gen_move_insn. */
7312 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7313 emit_insn (gen_move_insn (out, in));
7315 #ifdef HAVE_reload_load_address
7316 else if (HAVE_reload_load_address)
7317 emit_insn (gen_reload_load_address (out, in));
7320 /* Otherwise, just write (set OUT IN) and hope for the best. */
7322 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7324 /* Return the first insn emitted.
7325 We can not just return get_last_insn, because there may have
7326 been multiple instructions emitted. Also note that gen_move_insn may
7327 emit more than one insn itself, so we can not assume that there is one
7328 insn emitted per emit_insn_before call. */
7330 return last ? NEXT_INSN (last) : get_insns ();
7333 /* Delete a previously made output-reload
7334 whose result we now believe is not needed.
7335 First we double-check.
7337 INSN is the insn now being processed.
7338 LAST_RELOAD_REG is the hard register number for which we want to delete
7339 the last output reload.
7340 J is the reload-number that originally used REG. The caller has made
7341 certain that reload J doesn't use REG any longer for input. */
7344 delete_output_reload (insn, j, last_reload_reg)
7347 int last_reload_reg;
7349 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7350 rtx reg = spill_reg_stored_to[last_reload_reg];
7353 int n_inherited = 0;
7357 /* Get the raw pseudo-register referred to. */
7359 while (GET_CODE (reg) == SUBREG)
7360 reg = SUBREG_REG (reg);
7361 substed = reg_equiv_memory_loc[REGNO (reg)];
7363 /* This is unsafe if the operand occurs more often in the current
7364 insn than it is inherited. */
7365 for (k = n_reloads - 1; k >= 0; k--)
7367 rtx reg2 = rld[k].in;
7370 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7371 reg2 = rld[k].in_reg;
7373 if (rld[k].out && ! rld[k].out_reg)
7374 reg2 = XEXP (rld[k].in_reg, 0);
7376 while (GET_CODE (reg2) == SUBREG)
7377 reg2 = SUBREG_REG (reg2);
7378 if (rtx_equal_p (reg2, reg))
7380 if (reload_inherited[k] || reload_override_in[k] || k == j)
7383 reg2 = rld[k].out_reg;
7386 while (GET_CODE (reg2) == SUBREG)
7387 reg2 = XEXP (reg2, 0);
7388 if (rtx_equal_p (reg2, reg))
7395 n_occurrences = count_occurrences (PATTERN (insn), reg);
7397 n_occurrences += count_occurrences (PATTERN (insn), substed);
7398 if (n_occurrences > n_inherited)
7401 /* If the pseudo-reg we are reloading is no longer referenced
7402 anywhere between the store into it and here,
7403 and no jumps or labels intervene, then the value can get
7404 here through the reload reg alone.
7405 Otherwise, give up--return. */
7406 for (i1 = NEXT_INSN (output_reload_insn);
7407 i1 != insn; i1 = NEXT_INSN (i1))
7409 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7411 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7412 && reg_mentioned_p (reg, PATTERN (i1)))
7414 /* If this is USE in front of INSN, we only have to check that
7415 there are no more references than accounted for by inheritance. */
7416 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7418 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7419 i1 = NEXT_INSN (i1);
7421 if (n_occurrences <= n_inherited && i1 == insn)
7427 /* The caller has already checked that REG dies or is set in INSN.
7428 It has also checked that we are optimizing, and thus some inaccurancies
7429 in the debugging information are acceptable.
7430 So we could just delete output_reload_insn.
7431 But in some cases we can improve the debugging information without
7432 sacrificing optimization - maybe even improving the code:
7433 See if the pseudo reg has been completely replaced
7434 with reload regs. If so, delete the store insn
7435 and forget we had a stack slot for the pseudo. */
7436 if (rld[j].out != rld[j].in
7437 && REG_N_DEATHS (REGNO (reg)) == 1
7438 && REG_N_SETS (REGNO (reg)) == 1
7439 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7440 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7444 /* We know that it was used only between here
7445 and the beginning of the current basic block.
7446 (We also know that the last use before INSN was
7447 the output reload we are thinking of deleting, but never mind that.)
7448 Search that range; see if any ref remains. */
7449 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7451 rtx set = single_set (i2);
7453 /* Uses which just store in the pseudo don't count,
7454 since if they are the only uses, they are dead. */
7455 if (set != 0 && SET_DEST (set) == reg)
7457 if (GET_CODE (i2) == CODE_LABEL
7458 || GET_CODE (i2) == JUMP_INSN)
7460 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7461 && reg_mentioned_p (reg, PATTERN (i2)))
7463 /* Some other ref remains; just delete the output reload we
7465 delete_address_reloads (output_reload_insn, insn);
7466 PUT_CODE (output_reload_insn, NOTE);
7467 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7468 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7473 /* Delete the now-dead stores into this pseudo. */
7474 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7476 rtx set = single_set (i2);
7478 if (set != 0 && SET_DEST (set) == reg)
7480 delete_address_reloads (i2, insn);
7481 /* This might be a basic block head,
7482 thus don't use delete_insn. */
7483 PUT_CODE (i2, NOTE);
7484 NOTE_SOURCE_FILE (i2) = 0;
7485 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7487 if (GET_CODE (i2) == CODE_LABEL
7488 || GET_CODE (i2) == JUMP_INSN)
7492 /* For the debugging info,
7493 say the pseudo lives in this reload reg. */
7494 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7495 alter_reg (REGNO (reg), -1);
7497 delete_address_reloads (output_reload_insn, insn);
7498 PUT_CODE (output_reload_insn, NOTE);
7499 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7500 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7504 /* We are going to delete DEAD_INSN. Recursively delete loads of
7505 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7506 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7508 delete_address_reloads (dead_insn, current_insn)
7509 rtx dead_insn, current_insn;
7511 rtx set = single_set (dead_insn);
7512 rtx set2, dst, prev, next;
7515 rtx dst = SET_DEST (set);
7516 if (GET_CODE (dst) == MEM)
7517 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7519 /* If we deleted the store from a reloaded post_{in,de}c expression,
7520 we can delete the matching adds. */
7521 prev = PREV_INSN (dead_insn);
7522 next = NEXT_INSN (dead_insn);
7523 if (! prev || ! next)
7525 set = single_set (next);
7526 set2 = single_set (prev);
7528 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7529 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7530 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7532 dst = SET_DEST (set);
7533 if (! rtx_equal_p (dst, SET_DEST (set2))
7534 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7535 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7536 || (INTVAL (XEXP (SET_SRC (set), 1))
7537 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7543 /* Subfunction of delete_address_reloads: process registers found in X. */
7545 delete_address_reloads_1 (dead_insn, x, current_insn)
7546 rtx dead_insn, x, current_insn;
7548 rtx prev, set, dst, i2;
7550 enum rtx_code code = GET_CODE (x);
7554 const char *fmt= GET_RTX_FORMAT (code);
7555 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7558 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7559 else if (fmt[i] == 'E')
7561 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7562 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7569 if (spill_reg_order[REGNO (x)] < 0)
7572 /* Scan backwards for the insn that sets x. This might be a way back due
7574 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7576 code = GET_CODE (prev);
7577 if (code == CODE_LABEL || code == JUMP_INSN)
7579 if (GET_RTX_CLASS (code) != 'i')
7581 if (reg_set_p (x, PATTERN (prev)))
7583 if (reg_referenced_p (x, PATTERN (prev)))
7586 if (! prev || INSN_UID (prev) < reload_first_uid)
7588 /* Check that PREV only sets the reload register. */
7589 set = single_set (prev);
7592 dst = SET_DEST (set);
7593 if (GET_CODE (dst) != REG
7594 || ! rtx_equal_p (dst, x))
7596 if (! reg_set_p (dst, PATTERN (dead_insn)))
7598 /* Check if DST was used in a later insn -
7599 it might have been inherited. */
7600 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7602 if (GET_CODE (i2) == CODE_LABEL)
7604 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7606 if (reg_referenced_p (dst, PATTERN (i2)))
7608 /* If there is a reference to the register in the current insn,
7609 it might be loaded in a non-inherited reload. If no other
7610 reload uses it, that means the register is set before
7612 if (i2 == current_insn)
7614 for (j = n_reloads - 1; j >= 0; j--)
7615 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7616 || reload_override_in[j] == dst)
7618 for (j = n_reloads - 1; j >= 0; j--)
7619 if (rld[j].in && rld[j].reg_rtx == dst)
7626 if (GET_CODE (i2) == JUMP_INSN)
7628 /* If DST is still live at CURRENT_INSN, check if it is used for
7629 any reload. Note that even if CURRENT_INSN sets DST, we still
7630 have to check the reloads. */
7631 if (i2 == current_insn)
7633 for (j = n_reloads - 1; j >= 0; j--)
7634 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7635 || reload_override_in[j] == dst)
7637 /* ??? We can't finish the loop here, because dst might be
7638 allocated to a pseudo in this block if no reload in this
7639 block needs any of the clsses containing DST - see
7640 spill_hard_reg. There is no easy way to tell this, so we
7641 have to scan till the end of the basic block. */
7643 if (reg_set_p (dst, PATTERN (i2)))
7647 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7648 reg_reloaded_contents[REGNO (dst)] = -1;
7649 /* Can't use delete_insn here because PREV might be a basic block head. */
7650 PUT_CODE (prev, NOTE);
7651 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7652 NOTE_SOURCE_FILE (prev) = 0;
7655 /* Output reload-insns to reload VALUE into RELOADREG.
7656 VALUE is an autoincrement or autodecrement RTX whose operand
7657 is a register or memory location;
7658 so reloading involves incrementing that location.
7659 IN is either identical to VALUE, or some cheaper place to reload from.
7661 INC_AMOUNT is the number to increment or decrement by (always positive).
7662 This cannot be deduced from VALUE.
7664 Return the instruction that stores into RELOADREG. */
7667 inc_for_reload (reloadreg, in, value, inc_amount)
7672 /* REG or MEM to be copied and incremented. */
7673 rtx incloc = XEXP (value, 0);
7674 /* Nonzero if increment after copying. */
7675 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7681 rtx real_in = in == value ? XEXP (in, 0) : in;
7683 /* No hard register is equivalent to this register after
7684 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7685 we could inc/dec that register as well (maybe even using it for
7686 the source), but I'm not sure it's worth worrying about. */
7687 if (GET_CODE (incloc) == REG)
7688 reg_last_reload_reg[REGNO (incloc)] = 0;
7690 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7691 inc_amount = - inc_amount;
7693 inc = GEN_INT (inc_amount);
7695 /* If this is post-increment, first copy the location to the reload reg. */
7696 if (post && real_in != reloadreg)
7697 emit_insn (gen_move_insn (reloadreg, real_in));
7701 /* See if we can directly increment INCLOC. Use a method similar to
7702 that in gen_reload. */
7704 last = get_last_insn ();
7705 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7706 gen_rtx_PLUS (GET_MODE (incloc),
7709 code = recog_memoized (add_insn);
7712 extract_insn (add_insn);
7713 if (constrain_operands (1))
7715 /* If this is a pre-increment and we have incremented the value
7716 where it lives, copy the incremented value to RELOADREG to
7717 be used as an address. */
7720 emit_insn (gen_move_insn (reloadreg, incloc));
7725 delete_insns_since (last);
7728 /* If couldn't do the increment directly, must increment in RELOADREG.
7729 The way we do this depends on whether this is pre- or post-increment.
7730 For pre-increment, copy INCLOC to the reload register, increment it
7731 there, then save back. */
7735 if (in != reloadreg)
7736 emit_insn (gen_move_insn (reloadreg, real_in));
7737 emit_insn (gen_add2_insn (reloadreg, inc));
7738 store = emit_insn (gen_move_insn (incloc, reloadreg));
7743 Because this might be a jump insn or a compare, and because RELOADREG
7744 may not be available after the insn in an input reload, we must do
7745 the incrementation before the insn being reloaded for.
7747 We have already copied IN to RELOADREG. Increment the copy in
7748 RELOADREG, save that back, then decrement RELOADREG so it has
7749 the original value. */
7751 emit_insn (gen_add2_insn (reloadreg, inc));
7752 store = emit_insn (gen_move_insn (incloc, reloadreg));
7753 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7759 /* Return 1 if we are certain that the constraint-string STRING allows
7760 the hard register REG. Return 0 if we can't be sure of this. */
7763 constraint_accepts_reg_p (string, reg)
7768 int regno = true_regnum (reg);
7771 /* Initialize for first alternative. */
7773 /* Check that each alternative contains `g' or `r'. */
7775 switch (c = *string++)
7778 /* If an alternative lacks `g' or `r', we lose. */
7781 /* If an alternative lacks `g' or `r', we lose. */
7784 /* Initialize for next alternative. */
7789 /* Any general reg wins for this alternative. */
7790 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7794 /* Any reg in specified class wins for this alternative. */
7796 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7798 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7804 /* Return the number of places FIND appears within X, but don't count
7805 an occurrence if some SET_DEST is FIND. */
7808 count_occurrences (x, find)
7809 register rtx x, find;
7812 register enum rtx_code code;
7813 register const char *format_ptr;
7821 code = GET_CODE (x);
7836 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
7840 if (SET_DEST (x) == find)
7841 return count_occurrences (SET_SRC (x), find);
7848 format_ptr = GET_RTX_FORMAT (code);
7851 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7853 switch (*format_ptr++)
7856 count += count_occurrences (XEXP (x, i), find);
7860 if (XVEC (x, i) != NULL)
7862 for (j = 0; j < XVECLEN (x, i); j++)
7863 count += count_occurrences (XVECEXP (x, i, j), find);
7871 /* INSN is a no-op; delete it.
7872 If this sets the return value of the function, we must keep a USE around,
7873 in case this is in a different basic block than the final USE. Otherwise,
7874 we could loose important register lifeness information on
7875 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7876 spills: subsequent passes assume that spill registers are dead at the end
7878 VALUE must be the return value in such a case, NULL otherwise. */
7880 reload_cse_delete_noop_set (insn, value)
7885 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7886 INSN_CODE (insn) = -1;
7887 REG_NOTES (insn) = NULL_RTX;
7891 PUT_CODE (insn, NOTE);
7892 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7893 NOTE_SOURCE_FILE (insn) = 0;
7897 /* See whether a single set SET is a noop. */
7899 reload_cse_noop_set_p (set)
7902 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7905 /* Try to simplify INSN. */
7907 reload_cse_simplify (insn)
7910 rtx body = PATTERN (insn);
7912 if (GET_CODE (body) == SET)
7915 if (reload_cse_noop_set_p (body))
7917 rtx value = SET_DEST (body);
7918 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7920 reload_cse_delete_noop_set (insn, value);
7924 /* It's not a no-op, but we can try to simplify it. */
7925 count += reload_cse_simplify_set (body, insn);
7928 apply_change_group ();
7930 reload_cse_simplify_operands (insn);
7932 else if (GET_CODE (body) == PARALLEL)
7936 rtx value = NULL_RTX;
7938 /* If every action in a PARALLEL is a noop, we can delete
7939 the entire PARALLEL. */
7940 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7942 rtx part = XVECEXP (body, 0, i);
7943 if (GET_CODE (part) == SET)
7945 if (! reload_cse_noop_set_p (part))
7947 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7951 value = SET_DEST (part);
7954 else if (GET_CODE (part) != CLOBBER)
7960 reload_cse_delete_noop_set (insn, value);
7961 /* We're done with this insn. */
7965 /* It's not a no-op, but we can try to simplify it. */
7966 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7967 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7968 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7971 apply_change_group ();
7973 reload_cse_simplify_operands (insn);
7977 /* Do a very simple CSE pass over the hard registers.
7979 This function detects no-op moves where we happened to assign two
7980 different pseudo-registers to the same hard register, and then
7981 copied one to the other. Reload will generate a useless
7982 instruction copying a register to itself.
7984 This function also detects cases where we load a value from memory
7985 into two different registers, and (if memory is more expensive than
7986 registers) changes it to simply copy the first register into the
7989 Another optimization is performed that scans the operands of each
7990 instruction to see whether the value is already available in a
7991 hard register. It then replaces the operand with the hard register
7992 if possible, much like an optional reload would. */
7995 reload_cse_regs_1 (first)
8001 init_alias_analysis ();
8003 for (insn = first; insn; insn = NEXT_INSN (insn))
8005 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
8006 reload_cse_simplify (insn);
8008 cselib_process_insn (insn);
8012 end_alias_analysis ();
8016 /* Call cse / combine like post-reload optimization phases.
8017 FIRST is the first instruction. */
8019 reload_cse_regs (first)
8022 reload_cse_regs_1 (first);
8024 reload_cse_move2add (first);
8025 if (flag_expensive_optimizations)
8026 reload_cse_regs_1 (first);
8029 /* Try to simplify a single SET instruction. SET is the set pattern.
8030 INSN is the instruction it came from.
8031 This function only handles one case: if we set a register to a value
8032 which is not a register, we try to find that value in some other register
8033 and change the set into a register copy. */
8036 reload_cse_simplify_set (set, insn)
8043 enum reg_class dclass;
8046 struct elt_loc_list *l;
8048 dreg = true_regnum (SET_DEST (set));
8052 src = SET_SRC (set);
8053 if (side_effects_p (src) || true_regnum (src) >= 0)
8056 dclass = REGNO_REG_CLASS (dreg);
8058 /* If memory loads are cheaper than register copies, don't change them. */
8059 if (GET_CODE (src) == MEM)
8060 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8061 else if (CONSTANT_P (src))
8062 old_cost = rtx_cost (src, SET);
8063 else if (GET_CODE (src) == REG)
8064 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8067 old_cost = rtx_cost (src, SET);
8069 val = cselib_lookup (src, VOIDmode, 0);
8072 for (l = val->locs; l; l = l->next)
8075 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8076 this_cost = rtx_cost (l->loc, SET);
8077 else if (GET_CODE (l->loc) == REG)
8078 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8082 /* If equal costs, prefer registers over anything else. That tends to
8083 lead to smaller instructions on some machines. */
8084 if ((this_cost < old_cost
8085 || (this_cost == old_cost
8086 && GET_CODE (l->loc) == REG
8087 && GET_CODE (SET_SRC (set)) != REG))
8088 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8089 old_cost = this_cost, did_change = 1;
8095 /* Try to replace operands in INSN with equivalent values that are already
8096 in registers. This can be viewed as optional reloading.
8098 For each non-register operand in the insn, see if any hard regs are
8099 known to be equivalent to that operand. Record the alternatives which
8100 can accept these hard registers. Among all alternatives, select the
8101 ones which are better or equal to the one currently matching, where
8102 "better" is in terms of '?' and '!' constraints. Among the remaining
8103 alternatives, select the one which replaces most operands with
8107 reload_cse_simplify_operands (insn)
8112 /* For each operand, all registers that are equivalent to it. */
8113 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8115 const char *constraints[MAX_RECOG_OPERANDS];
8117 /* Vector recording how bad an alternative is. */
8118 int *alternative_reject;
8119 /* Vector recording how many registers can be introduced by choosing
8120 this alternative. */
8121 int *alternative_nregs;
8122 /* Array of vectors recording, for each operand and each alternative,
8123 which hard register to substitute, or -1 if the operand should be
8125 int *op_alt_regno[MAX_RECOG_OPERANDS];
8126 /* Array of alternatives, sorted in order of decreasing desirability. */
8127 int *alternative_order;
8128 rtx reg = gen_rtx_REG (VOIDmode, -1);
8130 extract_insn (insn);
8132 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8135 /* Figure out which alternative currently matches. */
8136 if (! constrain_operands (1))
8137 fatal_insn_not_found (insn);
8139 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8140 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8141 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8142 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8143 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8145 /* For each operand, find out which regs are equivalent. */
8146 for (i = 0; i < recog_data.n_operands; i++)
8149 struct elt_loc_list *l;
8151 CLEAR_HARD_REG_SET (equiv_regs[i]);
8153 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8154 right, so avoid the problem here. */
8155 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8158 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8162 for (l = v->locs; l; l = l->next)
8163 if (GET_CODE (l->loc) == REG)
8164 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8167 for (i = 0; i < recog_data.n_operands; i++)
8169 enum machine_mode mode;
8173 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8174 for (j = 0; j < recog_data.n_alternatives; j++)
8175 op_alt_regno[i][j] = -1;
8177 p = constraints[i] = recog_data.constraints[i];
8178 mode = recog_data.operand_mode[i];
8180 /* Add the reject values for each alternative given by the constraints
8181 for this operand. */
8189 alternative_reject[j] += 3;
8191 alternative_reject[j] += 300;
8194 /* We won't change operands which are already registers. We
8195 also don't want to modify output operands. */
8196 regno = true_regnum (recog_data.operand[i]);
8198 || constraints[i][0] == '='
8199 || constraints[i][0] == '+')
8202 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8204 int class = (int) NO_REGS;
8206 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8209 REGNO (reg) = regno;
8210 PUT_MODE (reg, mode);
8212 /* We found a register equal to this operand. Now look for all
8213 alternatives that can accept this register and have not been
8214 assigned a register they can use yet. */
8223 case '=': case '+': case '?':
8224 case '#': case '&': case '!':
8226 case '0': case '1': case '2': case '3': case '4':
8227 case '5': case '6': case '7': case '8': case '9':
8228 case 'm': case '<': case '>': case 'V': case 'o':
8229 case 'E': case 'F': case 'G': case 'H':
8230 case 's': case 'i': case 'n':
8231 case 'I': case 'J': case 'K': case 'L':
8232 case 'M': case 'N': case 'O': case 'P':
8233 #ifdef EXTRA_CONSTRAINT
8234 case 'Q': case 'R': case 'S': case 'T': case 'U':
8237 /* These don't say anything we care about. */
8241 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8246 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8249 case ',': case '\0':
8250 /* See if REGNO fits this alternative, and set it up as the
8251 replacement register if we don't have one for this
8252 alternative yet and the operand being replaced is not
8253 a cheap CONST_INT. */
8254 if (op_alt_regno[i][j] == -1
8255 && reg_fits_class_p (reg, class, 0, mode)
8256 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8257 || (rtx_cost (recog_data.operand[i], SET)
8258 > rtx_cost (reg, SET))))
8260 alternative_nregs[j]++;
8261 op_alt_regno[i][j] = regno;
8273 /* Record all alternatives which are better or equal to the currently
8274 matching one in the alternative_order array. */
8275 for (i = j = 0; i < recog_data.n_alternatives; i++)
8276 if (alternative_reject[i] <= alternative_reject[which_alternative])
8277 alternative_order[j++] = i;
8278 recog_data.n_alternatives = j;
8280 /* Sort it. Given a small number of alternatives, a dumb algorithm
8281 won't hurt too much. */
8282 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8285 int best_reject = alternative_reject[alternative_order[i]];
8286 int best_nregs = alternative_nregs[alternative_order[i]];
8289 for (j = i + 1; j < recog_data.n_alternatives; j++)
8291 int this_reject = alternative_reject[alternative_order[j]];
8292 int this_nregs = alternative_nregs[alternative_order[j]];
8294 if (this_reject < best_reject
8295 || (this_reject == best_reject && this_nregs < best_nregs))
8298 best_reject = this_reject;
8299 best_nregs = this_nregs;
8303 tmp = alternative_order[best];
8304 alternative_order[best] = alternative_order[i];
8305 alternative_order[i] = tmp;
8308 /* Substitute the operands as determined by op_alt_regno for the best
8310 j = alternative_order[0];
8312 for (i = 0; i < recog_data.n_operands; i++)
8314 enum machine_mode mode = recog_data.operand_mode[i];
8315 if (op_alt_regno[i][j] == -1)
8318 validate_change (insn, recog_data.operand_loc[i],
8319 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8322 for (i = recog_data.n_dups - 1; i >= 0; i--)
8324 int op = recog_data.dup_num[i];
8325 enum machine_mode mode = recog_data.operand_mode[op];
8327 if (op_alt_regno[op][j] == -1)
8330 validate_change (insn, recog_data.dup_loc[i],
8331 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8334 return apply_change_group ();
8337 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8339 This code might also be useful when reload gave up on reg+reg addresssing
8340 because of clashes between the return register and INDEX_REG_CLASS. */
8342 /* The maximum number of uses of a register we can keep track of to
8343 replace them with reg+reg addressing. */
8344 #define RELOAD_COMBINE_MAX_USES 6
8346 /* INSN is the insn where a register has ben used, and USEP points to the
8347 location of the register within the rtl. */
8348 struct reg_use { rtx insn, *usep; };
8350 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8351 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8352 indicates where it becomes live again.
8353 Otherwise, USE_INDEX is the index of the last encountered use of the
8354 register (which is first among these we have seen since we scan backwards),
8355 OFFSET contains the constant offset that is added to the register in
8356 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8357 last, of these uses.
8358 STORE_RUID is always meaningful if we only want to use a value in a
8359 register in a different place: it denotes the next insn in the insn
8360 stream (i.e. the last ecountered) that sets or clobbers the register. */
8363 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8368 } reg_state[FIRST_PSEUDO_REGISTER];
8370 /* Reverse linear uid. This is increased in reload_combine while scanning
8371 the instructions from last to first. It is used to set last_label_ruid
8372 and the store_ruid / use_ruid fields in reg_state. */
8373 static int reload_combine_ruid;
8375 #define LABEL_LIVE(LABEL) \
8376 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8382 int first_index_reg = 1, last_index_reg = 0;
8385 int last_label_ruid;
8386 int min_labelno, n_labels;
8387 HARD_REG_SET ever_live_at_start, *label_live;
8389 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8390 reload has already used it where appropriate, so there is no use in
8391 trying to generate it now. */
8392 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8395 /* To avoid wasting too much time later searching for an index register,
8396 determine the minimum and maximum index register numbers. */
8397 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8398 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8400 if (! first_index_reg)
8401 first_index_reg = r;
8406 /* If no index register is available, we can quit now. */
8407 if (first_index_reg > last_index_reg)
8410 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8411 information is a bit fuzzy immediately after reload, but it's
8412 still good enough to determine which registers are live at a jump
8414 min_labelno = get_first_label_num ();
8415 n_labels = max_label_num () - min_labelno;
8416 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8417 CLEAR_HARD_REG_SET (ever_live_at_start);
8419 for (i = n_basic_blocks - 1; i >= 0; i--)
8421 insn = BLOCK_HEAD (i);
8422 if (GET_CODE (insn) == CODE_LABEL)
8426 REG_SET_TO_HARD_REG_SET (live,
8427 BASIC_BLOCK (i)->global_live_at_start);
8428 compute_use_by_pseudos (&live,
8429 BASIC_BLOCK (i)->global_live_at_start);
8430 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8431 IOR_HARD_REG_SET (ever_live_at_start, live);
8435 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8436 last_label_ruid = reload_combine_ruid = 0;
8437 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8439 reg_state[r].store_ruid = reload_combine_ruid;
8441 reg_state[r].use_index = -1;
8443 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8446 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8450 /* We cannot do our optimization across labels. Invalidating all the use
8451 information we have would be costly, so we just note where the label
8452 is and then later disable any optimization that would cross it. */
8453 if (GET_CODE (insn) == CODE_LABEL)
8454 last_label_ruid = reload_combine_ruid;
8455 else if (GET_CODE (insn) == BARRIER)
8456 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8457 if (! fixed_regs[r])
8458 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8460 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8463 reload_combine_ruid++;
8465 /* Look for (set (REGX) (CONST_INT))
8466 (set (REGX) (PLUS (REGX) (REGY)))
8468 ... (MEM (REGX)) ...
8470 (set (REGZ) (CONST_INT))
8472 ... (MEM (PLUS (REGZ) (REGY)))... .
8474 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8475 and that we know all uses of REGX before it dies. */
8476 set = single_set (insn);
8478 && GET_CODE (SET_DEST (set)) == REG
8479 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8480 GET_MODE (SET_DEST (set)))
8482 && GET_CODE (SET_SRC (set)) == PLUS
8483 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8484 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8485 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8487 rtx reg = SET_DEST (set);
8488 rtx plus = SET_SRC (set);
8489 rtx base = XEXP (plus, 1);
8490 rtx prev = prev_nonnote_insn (insn);
8491 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8492 unsigned int regno = REGNO (reg);
8493 rtx const_reg = NULL_RTX;
8494 rtx reg_sum = NULL_RTX;
8496 /* Now, we need an index register.
8497 We'll set index_reg to this index register, const_reg to the
8498 register that is to be loaded with the constant
8499 (denoted as REGZ in the substitution illustration above),
8500 and reg_sum to the register-register that we want to use to
8501 substitute uses of REG (typically in MEMs) with.
8502 First check REG and BASE for being index registers;
8503 we can use them even if they are not dead. */
8504 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8505 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8513 /* Otherwise, look for a free index register. Since we have
8514 checked above that neiter REG nor BASE are index registers,
8515 if we find anything at all, it will be different from these
8517 for (i = first_index_reg; i <= last_index_reg; i++)
8519 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8521 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8522 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8523 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8525 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8527 const_reg = index_reg;
8528 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8534 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8535 (REGY), i.e. BASE, is not clobbered before the last use we'll
8538 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8539 && rtx_equal_p (SET_DEST (prev_set), reg)
8540 && reg_state[regno].use_index >= 0
8541 && (reg_state[REGNO (base)].store_ruid
8542 <= reg_state[regno].use_ruid)
8547 /* Change destination register and, if necessary, the
8548 constant value in PREV, the constant loading instruction. */
8549 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8550 if (reg_state[regno].offset != const0_rtx)
8551 validate_change (prev,
8552 &SET_SRC (prev_set),
8553 GEN_INT (INTVAL (SET_SRC (prev_set))
8554 + INTVAL (reg_state[regno].offset)),
8557 /* Now for every use of REG that we have recorded, replace REG
8559 for (i = reg_state[regno].use_index;
8560 i < RELOAD_COMBINE_MAX_USES; i++)
8561 validate_change (reg_state[regno].reg_use[i].insn,
8562 reg_state[regno].reg_use[i].usep,
8565 if (apply_change_group ())
8569 /* Delete the reg-reg addition. */
8570 PUT_CODE (insn, NOTE);
8571 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8572 NOTE_SOURCE_FILE (insn) = 0;
8574 if (reg_state[regno].offset != const0_rtx)
8575 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8577 for (np = ®_NOTES (prev); *np; )
8579 if (REG_NOTE_KIND (*np) == REG_EQUAL
8580 || REG_NOTE_KIND (*np) == REG_EQUIV)
8581 *np = XEXP (*np, 1);
8583 np = &XEXP (*np, 1);
8586 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8587 reg_state[REGNO (const_reg)].store_ruid
8588 = reload_combine_ruid;
8594 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8596 if (GET_CODE (insn) == CALL_INSN)
8600 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8601 if (call_used_regs[r])
8603 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8604 reg_state[r].store_ruid = reload_combine_ruid;
8607 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8608 link = XEXP (link, 1))
8609 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8611 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8613 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8615 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8616 reg_state[regno].store_ruid = reload_combine_ruid;
8619 reg_state[regno].use_index = -1;
8623 else if (GET_CODE (insn) == JUMP_INSN
8624 && GET_CODE (PATTERN (insn)) != RETURN)
8626 /* Non-spill registers might be used at the call destination in
8627 some unknown fashion, so we have to mark the unknown use. */
8630 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8631 && JUMP_LABEL (insn))
8632 live = &LABEL_LIVE (JUMP_LABEL (insn));
8634 live = &ever_live_at_start;
8636 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8637 if (TEST_HARD_REG_BIT (*live, i))
8638 reg_state[i].use_index = -1;
8641 reload_combine_note_use (&PATTERN (insn), insn);
8642 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8644 if (REG_NOTE_KIND (note) == REG_INC
8645 && GET_CODE (XEXP (note, 0)) == REG)
8647 int regno = REGNO (XEXP (note, 0));
8649 reg_state[regno].store_ruid = reload_combine_ruid;
8650 reg_state[regno].use_index = -1;
8658 /* Check if DST is a register or a subreg of a register; if it is,
8659 update reg_state[regno].store_ruid and reg_state[regno].use_index
8660 accordingly. Called via note_stores from reload_combine. */
8663 reload_combine_note_store (dst, set, data)
8665 void *data ATTRIBUTE_UNUSED;
8669 enum machine_mode mode = GET_MODE (dst);
8671 if (GET_CODE (dst) == SUBREG)
8673 regno = SUBREG_WORD (dst);
8674 dst = SUBREG_REG (dst);
8676 if (GET_CODE (dst) != REG)
8678 regno += REGNO (dst);
8680 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8681 careful with registers / register parts that are not full words.
8683 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8684 if (GET_CODE (set) != SET
8685 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8686 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8687 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8689 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8691 reg_state[i].use_index = -1;
8692 reg_state[i].store_ruid = reload_combine_ruid;
8697 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8699 reg_state[i].store_ruid = reload_combine_ruid;
8700 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8705 /* XP points to a piece of rtl that has to be checked for any uses of
8707 *XP is the pattern of INSN, or a part of it.
8708 Called from reload_combine, and recursively by itself. */
8710 reload_combine_note_use (xp, insn)
8714 enum rtx_code code = x->code;
8717 rtx offset = const0_rtx; /* For the REG case below. */
8722 if (GET_CODE (SET_DEST (x)) == REG)
8724 reload_combine_note_use (&SET_SRC (x), insn);
8730 /* If this is the USE of a return value, we can't change it. */
8731 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8733 /* Mark the return register as used in an unknown fashion. */
8734 rtx reg = XEXP (x, 0);
8735 int regno = REGNO (reg);
8736 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8738 while (--nregs >= 0)
8739 reg_state[regno + nregs].use_index = -1;
8745 if (GET_CODE (SET_DEST (x)) == REG)
8750 /* We are interested in (plus (reg) (const_int)) . */
8751 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
8753 offset = XEXP (x, 1);
8758 int regno = REGNO (x);
8762 /* Some spurious USEs of pseudo registers might remain.
8763 Just ignore them. */
8764 if (regno >= FIRST_PSEUDO_REGISTER)
8767 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8769 /* We can't substitute into multi-hard-reg uses. */
8772 while (--nregs >= 0)
8773 reg_state[regno + nregs].use_index = -1;
8777 /* If this register is already used in some unknown fashion, we
8779 If we decrement the index from zero to -1, we can't store more
8780 uses, so this register becomes used in an unknown fashion. */
8781 use_index = --reg_state[regno].use_index;
8785 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8787 /* We have found another use for a register that is already
8788 used later. Check if the offsets match; if not, mark the
8789 register as used in an unknown fashion. */
8790 if (! rtx_equal_p (offset, reg_state[regno].offset))
8792 reg_state[regno].use_index = -1;
8798 /* This is the first use of this register we have seen since we
8799 marked it as dead. */
8800 reg_state[regno].offset = offset;
8801 reg_state[regno].use_ruid = reload_combine_ruid;
8803 reg_state[regno].reg_use[use_index].insn = insn;
8804 reg_state[regno].reg_use[use_index].usep = xp;
8812 /* Recursively process the components of X. */
8813 fmt = GET_RTX_FORMAT (code);
8814 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8817 reload_combine_note_use (&XEXP (x, i), insn);
8818 else if (fmt[i] == 'E')
8820 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8821 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8826 /* See if we can reduce the cost of a constant by replacing a move with
8828 /* We cannot do our optimization across labels. Invalidating all the
8829 information about register contents we have would be costly, so we
8830 use last_label_luid (local variable of reload_cse_move2add) to note
8831 where the label is and then later disable any optimization that would
8833 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8834 reg_set_luid[n] is larger than last_label_luid[n] . */
8835 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8837 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8838 reg_mode[n] to be valid.
8839 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8840 has been set to reg_offset[n] in mode reg_mode[n] .
8841 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8842 register n has been set to the sum of reg_offset[n] and register
8843 reg_base_reg[n], calculated in mode reg_mode[n] . */
8844 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8845 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8846 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8848 /* move2add_luid is linearily increased while scanning the instructions
8849 from first to last. It is used to set reg_set_luid in
8850 reload_cse_move2add and move2add_note_store. */
8851 static int move2add_luid;
8853 /* Generate a CONST_INT and force it in the range of MODE. */
8856 gen_mode_int (mode, value)
8857 enum machine_mode mode;
8858 HOST_WIDE_INT value;
8860 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8861 int width = GET_MODE_BITSIZE (mode);
8863 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8865 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8866 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8867 cval |= (HOST_WIDE_INT) -1 << width;
8869 return GEN_INT (cval);
8873 reload_cse_move2add (first)
8878 int last_label_luid;
8880 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
8881 reg_set_luid[i] = 0;
8883 last_label_luid = 0;
8885 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8889 if (GET_CODE (insn) == CODE_LABEL)
8890 last_label_luid = move2add_luid;
8891 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8893 pat = PATTERN (insn);
8894 /* For simplicity, we only perform this optimization on
8895 straightforward SETs. */
8896 if (GET_CODE (pat) == SET
8897 && GET_CODE (SET_DEST (pat)) == REG)
8899 rtx reg = SET_DEST (pat);
8900 int regno = REGNO (reg);
8901 rtx src = SET_SRC (pat);
8903 /* Check if we have valid information on the contents of this
8904 register in the mode of REG. */
8905 /* ??? We don't know how zero / sign extension is handled, hence
8906 we can't go from a narrower to a wider mode. */
8907 if (reg_set_luid[regno] > last_label_luid
8908 && ((GET_MODE_SIZE (GET_MODE (reg))
8909 == GET_MODE_SIZE (reg_mode[regno]))
8910 || ((GET_MODE_SIZE (GET_MODE (reg))
8911 <= GET_MODE_SIZE (reg_mode[regno]))
8912 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8913 GET_MODE_BITSIZE (reg_mode[regno]))))
8914 && GET_CODE (reg_offset[regno]) == CONST_INT)
8916 /* Try to transform (set (REGX) (CONST_INT A))
8918 (set (REGX) (CONST_INT B))
8920 (set (REGX) (CONST_INT A))
8922 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8924 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8928 = gen_mode_int (GET_MODE (reg),
8929 INTVAL (src) - INTVAL (reg_offset[regno]));
8930 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8931 use (set (reg) (reg)) instead.
8932 We don't delete this insn, nor do we convert it into a
8933 note, to avoid losing register notes or the return
8934 value flag. jump2 already knowns how to get rid of
8936 if (new_src == const0_rtx)
8937 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8938 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8939 && have_add2_insn (GET_MODE (reg)))
8940 success = validate_change (insn, &PATTERN (insn),
8941 gen_add2_insn (reg, new_src), 0);
8942 reg_set_luid[regno] = move2add_luid;
8943 reg_mode[regno] = GET_MODE (reg);
8944 reg_offset[regno] = src;
8948 /* Try to transform (set (REGX) (REGY))
8949 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8952 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8955 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8957 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8958 else if (GET_CODE (src) == REG
8959 && reg_base_reg[regno] == (int) REGNO (src)
8960 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8962 rtx next = next_nonnote_insn (insn);
8965 set = single_set (next);
8968 && SET_DEST (set) == reg
8969 && GET_CODE (SET_SRC (set)) == PLUS
8970 && XEXP (SET_SRC (set), 0) == reg
8971 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8973 rtx src3 = XEXP (SET_SRC (set), 1);
8975 = gen_mode_int (GET_MODE (reg),
8977 - INTVAL (reg_offset[regno]));
8980 if (new_src == const0_rtx)
8981 /* See above why we create (set (reg) (reg)) here. */
8983 = validate_change (next, &SET_SRC (set), reg, 0);
8984 else if ((rtx_cost (new_src, PLUS)
8985 < 2 + rtx_cost (src3, SET))
8986 && have_add2_insn (GET_MODE (reg)))
8988 = validate_change (next, &PATTERN (next),
8989 gen_add2_insn (reg, new_src), 0);
8992 /* INSN might be the first insn in a basic block
8993 if the preceding insn is a conditional jump
8994 or a possible-throwing call. */
8995 PUT_CODE (insn, NOTE);
8996 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8997 NOTE_SOURCE_FILE (insn) = 0;
9000 reg_set_luid[regno] = move2add_luid;
9001 reg_mode[regno] = GET_MODE (reg);
9002 reg_offset[regno] = src3;
9009 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9011 if (REG_NOTE_KIND (note) == REG_INC
9012 && GET_CODE (XEXP (note, 0)) == REG)
9014 /* Indicate that this register has been recently written to,
9015 but the exact contents are not available. */
9016 int regno = REGNO (XEXP (note, 0));
9017 if (regno < FIRST_PSEUDO_REGISTER)
9019 reg_set_luid[regno] = move2add_luid;
9020 reg_offset[regno] = note;
9024 note_stores (PATTERN (insn), move2add_note_store, NULL);
9025 /* If this is a CALL_INSN, all call used registers are stored with
9027 if (GET_CODE (insn) == CALL_INSN)
9029 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9031 if (call_used_regs[i])
9033 reg_set_luid[i] = move2add_luid;
9034 reg_offset[i] = insn; /* Invalidate contents. */
9041 /* SET is a SET or CLOBBER that sets DST.
9042 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9043 Called from reload_cse_move2add via note_stores. */
9046 move2add_note_store (dst, set, data)
9048 void *data ATTRIBUTE_UNUSED;
9050 unsigned int regno = 0;
9052 enum machine_mode mode = GET_MODE (dst);
9054 if (GET_CODE (dst) == SUBREG)
9056 regno = SUBREG_WORD (dst);
9057 dst = SUBREG_REG (dst);
9060 if (GET_CODE (dst) != REG)
9063 regno += REGNO (dst);
9065 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9066 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9067 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9068 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9070 rtx src = SET_SRC (set);
9072 reg_mode[regno] = mode;
9073 switch (GET_CODE (src))
9077 rtx src0 = XEXP (src, 0);
9079 if (GET_CODE (src0) == REG)
9081 if (REGNO (src0) != regno
9082 || reg_offset[regno] != const0_rtx)
9084 reg_base_reg[regno] = REGNO (src0);
9085 reg_set_luid[regno] = move2add_luid;
9088 reg_offset[regno] = XEXP (src, 1);
9092 reg_set_luid[regno] = move2add_luid;
9093 reg_offset[regno] = set; /* Invalidate contents. */
9098 reg_base_reg[regno] = REGNO (SET_SRC (set));
9099 reg_offset[regno] = const0_rtx;
9100 reg_set_luid[regno] = move2add_luid;
9104 reg_base_reg[regno] = -1;
9105 reg_offset[regno] = SET_SRC (set);
9106 reg_set_luid[regno] = move2add_luid;
9112 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9114 for (i = regno; i < endregno; i++)
9116 /* Indicate that this register has been recently written to,
9117 but the exact contents are not available. */
9118 reg_set_luid[i] = move2add_luid;
9119 reg_offset[i] = dst;
9126 add_auto_inc_notes (insn, x)
9130 enum rtx_code code = GET_CODE (x);
9134 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9137 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9141 /* Scan all the operand sub-expressions. */
9142 fmt = GET_RTX_FORMAT (code);
9143 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9146 add_auto_inc_notes (insn, XEXP (x, i));
9147 else if (fmt[i] == 'E')
9148 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9149 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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