1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
71 #ifndef REGISTER_MOVE_COST
72 #define REGISTER_MOVE_COST(x, y) 2
75 #ifndef MEMORY_MOVE_COST
76 #define MEMORY_MOVE_COST(x) 4
79 /* During reload_as_needed, element N contains a REG rtx for the hard reg
80 into which reg N has been reloaded (perhaps for a previous insn). */
81 static rtx *reg_last_reload_reg;
83 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
84 for an output reload that stores into reg N. */
85 static char *reg_has_output_reload;
87 /* Indicates which hard regs are reload-registers for an output reload
88 in the current insn. */
89 static HARD_REG_SET reg_is_output_reload;
91 /* Element N is the constant value to which pseudo reg N is equivalent,
92 or zero if pseudo reg N is not equivalent to a constant.
93 find_reloads looks at this in order to replace pseudo reg N
94 with the constant it stands for. */
95 rtx *reg_equiv_constant;
97 /* Element N is a memory location to which pseudo reg N is equivalent,
98 prior to any register elimination (such as frame pointer to stack
99 pointer). Depending on whether or not it is a valid address, this value
100 is transferred to either reg_equiv_address or reg_equiv_mem. */
101 rtx *reg_equiv_memory_loc;
103 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
104 This is used when the address is not valid as a memory address
105 (because its displacement is too big for the machine.) */
106 rtx *reg_equiv_address;
108 /* Element N is the memory slot to which pseudo reg N is equivalent,
109 or zero if pseudo reg N is not equivalent to a memory slot. */
112 /* Widest width in which each pseudo reg is referred to (via subreg). */
113 static int *reg_max_ref_width;
115 /* Element N is the insn that initialized reg N from its equivalent
116 constant or memory slot. */
117 static rtx *reg_equiv_init;
119 /* During reload_as_needed, element N contains the last pseudo regno
120 reloaded into the Nth reload register. This vector is in parallel
121 with spill_regs. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 the Nth reload register was last used. This vector is in parallel
128 with spill_regs, and its contents are significant only when
129 reg_reloaded_contents is significant. */
130 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
132 /* Number of spill-regs so far; number of valid elements of spill_regs. */
135 /* In parallel with spill_regs, contains REG rtx's for those regs.
136 Holds the last rtx used for any given reg, or 0 if it has never
137 been used for spilling yet. This rtx is reused, provided it has
139 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
141 /* In parallel with spill_regs, contains nonzero for a spill reg
142 that was stored after the last time it was used.
143 The precise value is the insn generated to do the store. */
144 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs. */
150 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
152 /* This reg set indicates registers that may not be used for retrying global
153 allocation. The registers that may not be used include all spill registers
154 and the frame pointer (if we are using one). */
155 HARD_REG_SET forbidden_regs;
157 /* This reg set indicates registers that are not good for spill registers.
158 They will not be used to complete groups of spill registers. This includes
159 all fixed registers, registers that may be eliminated, and, if
160 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
162 (spill_reg_order prevents these registers from being used to start a
164 static HARD_REG_SET bad_spill_regs;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `spills' is the number of
168 elements that are actually valid; new ones are added at the end. */
169 static short spill_regs[FIRST_PSEUDO_REGISTER];
171 /* Describes order of preference for putting regs into spill_regs.
172 Contains the numbers of all the hard regs, in order most preferred first.
173 This order is different for each function.
174 It is set up by order_regs_for_reload.
175 Empty elements at the end contain -1. */
176 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
178 /* 1 for a hard register that appears explicitly in the rtl
179 (for example, function value registers, special registers
180 used by insns, structure value pointer registers). */
181 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
183 /* Indicates if a register was counted against the need for
184 groups. 0 means it can count against max_nongroup instead. */
185 static HARD_REG_SET counted_for_groups;
187 /* Indicates if a register was counted against the need for
188 non-groups. 0 means it can become part of a new group.
189 During choose_reload_regs, 1 here means don't use this reg
190 as part of a group, even if it seems to be otherwise ok. */
191 static HARD_REG_SET counted_for_nongroups;
193 /* Indexed by pseudo reg number N,
194 says may not delete stores into the real (memory) home of pseudo N.
195 This is set if we already substituted a memory equivalent in some uses,
196 which happens when we have to eliminate the fp from it. */
197 static char *cannot_omit_stores;
199 /* Nonzero if indirect addressing is supported on the machine; this means
200 that spilling (REG n) does not require reloading it into a register in
201 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
202 value indicates the level of indirect addressing supported, e.g., two
203 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
206 static char spill_indirect_levels;
208 /* Nonzero if indirect addressing is supported when the innermost MEM is
209 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
210 which these are valid is the same as spill_indirect_levels, above. */
212 char indirect_symref_ok;
214 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
216 char double_reg_address_ok;
218 /* Record the stack slot for each spilled hard register. */
220 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
222 /* Width allocated so far for that stack slot. */
224 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
226 /* Indexed by register class and basic block number, nonzero if there is
227 any need for a spill register of that class in that basic block.
228 The pointer is 0 if we did stupid allocation and don't know
229 the structure of basic blocks. */
231 char *basic_block_needs[N_REG_CLASSES];
233 /* First uid used by insns created by reload in this function.
234 Used in find_equiv_reg. */
235 int reload_first_uid;
237 /* Flag set by local-alloc or global-alloc if anything is live in
238 a call-clobbered reg across calls. */
240 int caller_save_needed;
242 /* Set to 1 while reload_as_needed is operating.
243 Required by some machines to handle any generated moves differently. */
245 int reload_in_progress = 0;
247 /* These arrays record the insn_code of insns that may be needed to
248 perform input and output reloads of special objects. They provide a
249 place to pass a scratch register. */
251 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
252 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
254 /* This obstack is used for allocation of rtl during register elimination.
255 The allocated storage can be freed once find_reloads has processed the
258 struct obstack reload_obstack;
259 char *reload_firstobj;
261 #define obstack_chunk_alloc xmalloc
262 #define obstack_chunk_free free
264 /* List of labels that must never be deleted. */
265 extern rtx forced_labels;
267 /* This structure is used to record information about register eliminations.
268 Each array entry describes one possible way of eliminating a register
269 in favor of another. If there is more than one way of eliminating a
270 particular register, the most preferred should be specified first. */
272 static struct elim_table
274 int from; /* Register number to be eliminated. */
275 int to; /* Register number used as replacement. */
276 int initial_offset; /* Initial difference between values. */
277 int can_eliminate; /* Non-zero if this elimination can be done. */
278 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
279 insns made by reload. */
280 int offset; /* Current offset between the two regs. */
281 int max_offset; /* Maximum offset between the two regs. */
282 int previous_offset; /* Offset at end of previous insn. */
283 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
284 rtx from_rtx; /* REG rtx for the register to be eliminated.
285 We cannot simply compare the number since
286 we might then spuriously replace a hard
287 register corresponding to a pseudo
288 assigned to the reg to be eliminated. */
289 rtx to_rtx; /* REG rtx for the replacement. */
292 /* If a set of eliminable registers was specified, define the table from it.
293 Otherwise, default to the normal case of the frame pointer being
294 replaced by the stack pointer. */
296 #ifdef ELIMINABLE_REGS
299 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
302 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
304 /* Record the number of pending eliminations that have an offset not equal
305 to their initial offset. If non-zero, we use a new copy of each
306 replacement result in any insns encountered. */
307 static int num_not_at_initial_offset;
309 /* Count the number of registers that we may be able to eliminate. */
310 static int num_eliminable;
312 /* For each label, we record the offset of each elimination. If we reach
313 a label by more than one path and an offset differs, we cannot do the
314 elimination. This information is indexed by the number of the label.
315 The first table is an array of flags that records whether we have yet
316 encountered a label and the second table is an array of arrays, one
317 entry in the latter array for each elimination. */
319 static char *offsets_known_at;
320 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
322 /* Number of labels in the current function. */
324 static int num_labels;
326 struct hard_reg_n_uses { int regno; int uses; };
328 static int possible_group_p PROTO((int, int *));
329 static void count_possible_groups PROTO((int *, enum machine_mode *,
331 static int modes_equiv_for_class_p PROTO((enum machine_mode,
334 static void spill_failure PROTO((rtx));
335 static int new_spill_reg PROTO((int, int, int *, int *, int,
337 static void delete_dead_insn PROTO((rtx));
338 static void alter_reg PROTO((int, int));
339 static void set_label_offsets PROTO((rtx, rtx, int));
340 static int eliminate_regs_in_insn PROTO((rtx, int));
341 static void mark_not_eliminable PROTO((rtx, rtx));
342 static int spill_hard_reg PROTO((int, int, FILE *, int));
343 static void scan_paradoxical_subregs PROTO((rtx));
344 static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *,
345 struct hard_reg_n_uses *));
346 static void order_regs_for_reload PROTO((void));
347 static void reload_as_needed PROTO((rtx, int));
348 static void forget_old_reloads_1 PROTO((rtx, rtx));
349 static int reload_reg_class_lower PROTO((short *, short *));
350 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
352 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
354 static int reload_reg_free_p PROTO((int, int, enum reload_type));
355 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
356 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
357 static int allocate_reload_reg PROTO((int, rtx, int, int));
358 static void choose_reload_regs PROTO((rtx, rtx));
359 static void merge_assigned_reloads PROTO((rtx));
360 static void emit_reload_insns PROTO((rtx));
361 static void delete_output_reload PROTO((rtx, int, rtx));
362 static void inc_for_reload PROTO((rtx, rtx, int));
363 static int constraint_accepts_reg_p PROTO((char *, rtx));
364 static int count_occurrences PROTO((rtx, rtx));
366 /* Initialize the reload pass once per compilation. */
373 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
374 Set spill_indirect_levels to the number of levels such addressing is
375 permitted, zero if it is not permitted at all. */
378 = gen_rtx (MEM, Pmode,
379 gen_rtx (PLUS, Pmode,
380 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
382 spill_indirect_levels = 0;
384 while (memory_address_p (QImode, tem))
386 spill_indirect_levels++;
387 tem = gen_rtx (MEM, Pmode, tem);
390 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
392 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
393 indirect_symref_ok = memory_address_p (QImode, tem);
395 /* See if reg+reg is a valid (and offsettable) address. */
397 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
399 tem = gen_rtx (PLUS, Pmode,
400 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
401 gen_rtx (REG, Pmode, i));
402 /* This way, we make sure that reg+reg is an offsettable address. */
403 tem = plus_constant (tem, 4);
405 if (memory_address_p (QImode, tem))
407 double_reg_address_ok = 1;
412 /* Initialize obstack for our rtl allocation. */
413 gcc_obstack_init (&reload_obstack);
414 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
417 /* Main entry point for the reload pass.
419 FIRST is the first insn of the function being compiled.
421 GLOBAL nonzero means we were called from global_alloc
422 and should attempt to reallocate any pseudoregs that we
423 displace from hard regs we will use for reloads.
424 If GLOBAL is zero, we do not have enough information to do that,
425 so any pseudo reg that is spilled must go to the stack.
427 DUMPFILE is the global-reg debugging dump file stream, or 0.
428 If it is nonzero, messages are written to it to describe
429 which registers are seized as reload regs, which pseudo regs
430 are spilled from them, and where the pseudo regs are reallocated to.
432 Return value is nonzero if reload failed
433 and we must not do any more for this function. */
436 reload (first, global, dumpfile)
444 register struct elim_table *ep;
446 int something_changed;
447 int something_needs_reloads;
448 int something_needs_elimination;
449 int new_basic_block_needs;
450 enum reg_class caller_save_spill_class = NO_REGS;
451 int caller_save_group_size = 1;
453 /* Nonzero means we couldn't get enough spill regs. */
456 /* The basic block number currently being processed for INSN. */
459 /* Make sure even insns with volatile mem refs are recognizable. */
462 /* Enable find_equiv_reg to distinguish insns made by reload. */
463 reload_first_uid = get_max_uid ();
465 for (i = 0; i < N_REG_CLASSES; i++)
466 basic_block_needs[i] = 0;
468 #ifdef SECONDARY_MEMORY_NEEDED
469 /* Initialize the secondary memory table. */
470 clear_secondary_mem ();
473 /* Remember which hard regs appear explicitly
474 before we merge into `regs_ever_live' the ones in which
475 pseudo regs have been allocated. */
476 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
478 /* We don't have a stack slot for any spill reg yet. */
479 bzero (spill_stack_slot, sizeof spill_stack_slot);
480 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
482 /* Initialize the save area information for caller-save, in case some
486 /* Compute which hard registers are now in use
487 as homes for pseudo registers.
488 This is done here rather than (eg) in global_alloc
489 because this point is reached even if not optimizing. */
491 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
494 /* Make sure that the last insn in the chain
495 is not something that needs reloading. */
496 emit_note (NULL_PTR, NOTE_INSN_DELETED);
498 /* Find all the pseudo registers that didn't get hard regs
499 but do have known equivalent constants or memory slots.
500 These include parameters (known equivalent to parameter slots)
501 and cse'd or loop-moved constant memory addresses.
503 Record constant equivalents in reg_equiv_constant
504 so they will be substituted by find_reloads.
505 Record memory equivalents in reg_mem_equiv so they can
506 be substituted eventually by altering the REG-rtx's. */
508 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
509 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
510 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
511 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
512 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
513 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
514 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
515 bzero (reg_equiv_init, max_regno * sizeof (rtx));
516 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
517 bzero (reg_equiv_address, max_regno * sizeof (rtx));
518 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
519 bzero (reg_max_ref_width, max_regno * sizeof (int));
520 cannot_omit_stores = (char *) alloca (max_regno);
521 bzero (cannot_omit_stores, max_regno);
523 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
524 Also find all paradoxical subregs
525 and find largest such for each pseudo. */
527 for (insn = first; insn; insn = NEXT_INSN (insn))
529 rtx set = single_set (insn);
531 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
533 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
535 #ifdef LEGITIMATE_PIC_OPERAND_P
536 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
537 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
541 rtx x = XEXP (note, 0);
542 i = REGNO (SET_DEST (set));
543 if (i > LAST_VIRTUAL_REGISTER)
545 if (GET_CODE (x) == MEM)
546 reg_equiv_memory_loc[i] = x;
547 else if (CONSTANT_P (x))
549 if (LEGITIMATE_CONSTANT_P (x))
550 reg_equiv_constant[i] = x;
552 reg_equiv_memory_loc[i]
553 = force_const_mem (GET_MODE (SET_DEST (set)), x);
558 /* If this register is being made equivalent to a MEM
559 and the MEM is not SET_SRC, the equivalencing insn
560 is one with the MEM as a SET_DEST and it occurs later.
561 So don't mark this insn now. */
562 if (GET_CODE (x) != MEM
563 || rtx_equal_p (SET_SRC (set), x))
564 reg_equiv_init[i] = insn;
569 /* If this insn is setting a MEM from a register equivalent to it,
570 this is the equivalencing insn. */
571 else if (set && GET_CODE (SET_DEST (set)) == MEM
572 && GET_CODE (SET_SRC (set)) == REG
573 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
574 && rtx_equal_p (SET_DEST (set),
575 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
576 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
578 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
579 scan_paradoxical_subregs (PATTERN (insn));
582 /* Does this function require a frame pointer? */
584 frame_pointer_needed = (! flag_omit_frame_pointer
585 #ifdef EXIT_IGNORE_STACK
586 /* ?? If EXIT_IGNORE_STACK is set, we will not save
587 and restore sp for alloca. So we can't eliminate
588 the frame pointer in that case. At some point,
589 we should improve this by emitting the
590 sp-adjusting insns for this case. */
591 || (current_function_calls_alloca
592 && EXIT_IGNORE_STACK)
594 || FRAME_POINTER_REQUIRED);
598 /* Initialize the table of registers to eliminate. The way we do this
599 depends on how the eliminable registers were defined. */
600 #ifdef ELIMINABLE_REGS
601 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
603 ep->can_eliminate = ep->can_eliminate_previous
604 = (CAN_ELIMINATE (ep->from, ep->to)
605 && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
608 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
609 = ! frame_pointer_needed;
612 /* Count the number of eliminable registers and build the FROM and TO
613 REG rtx's. Note that code in gen_rtx will cause, e.g.,
614 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
615 We depend on this. */
616 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
618 num_eliminable += ep->can_eliminate;
619 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
620 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
623 num_labels = max_label_num () - get_first_label_num ();
625 /* Allocate the tables used to store offset information at labels. */
626 offsets_known_at = (char *) alloca (num_labels);
628 = (int (*)[NUM_ELIMINABLE_REGS])
629 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
631 offsets_known_at -= get_first_label_num ();
632 offsets_at -= get_first_label_num ();
634 /* Alter each pseudo-reg rtx to contain its hard reg number.
635 Assign stack slots to the pseudos that lack hard regs or equivalents.
636 Do not touch virtual registers. */
638 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
641 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
642 because the stack size may be a part of the offset computation for
643 register elimination. */
644 assign_stack_local (BLKmode, 0, 0);
646 /* If we have some registers we think can be eliminated, scan all insns to
647 see if there is an insn that sets one of these registers to something
648 other than itself plus a constant. If so, the register cannot be
649 eliminated. Doing this scan here eliminates an extra pass through the
650 main reload loop in the most common case where register elimination
652 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
653 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
654 || GET_CODE (insn) == CALL_INSN)
655 note_stores (PATTERN (insn), mark_not_eliminable);
657 #ifndef REGISTER_CONSTRAINTS
658 /* If all the pseudo regs have hard regs,
659 except for those that are never referenced,
660 we know that no reloads are needed. */
661 /* But that is not true if there are register constraints, since
662 in that case some pseudos might be in the wrong kind of hard reg. */
664 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
665 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
668 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
672 /* Compute the order of preference for hard registers to spill.
673 Store them by decreasing preference in potential_reload_regs. */
675 order_regs_for_reload ();
677 /* So far, no hard regs have been spilled. */
679 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
680 spill_reg_order[i] = -1;
682 /* On most machines, we can't use any register explicitly used in the
683 rtl as a spill register. But on some, we have to. Those will have
684 taken care to keep the life of hard regs as short as possible. */
686 #ifdef SMALL_REGISTER_CLASSES
687 CLEAR_HARD_REG_SET (forbidden_regs);
689 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
692 /* Spill any hard regs that we know we can't eliminate. */
693 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
694 if (! ep->can_eliminate)
696 spill_hard_reg (ep->from, global, dumpfile, 1);
697 regs_ever_live[ep->from] = 1;
701 for (i = 0; i < N_REG_CLASSES; i++)
703 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
704 bzero (basic_block_needs[i], n_basic_blocks);
707 /* From now on, we need to emit any moves without making new pseudos. */
708 reload_in_progress = 1;
710 /* This loop scans the entire function each go-round
711 and repeats until one repetition spills no additional hard regs. */
713 /* This flag is set when a pseudo reg is spilled,
714 to require another pass. Note that getting an additional reload
715 reg does not necessarily imply any pseudo reg was spilled;
716 sometimes we find a reload reg that no pseudo reg was allocated in. */
717 something_changed = 1;
718 /* This flag is set if there are any insns that require reloading. */
719 something_needs_reloads = 0;
720 /* This flag is set if there are any insns that require register
722 something_needs_elimination = 0;
723 while (something_changed)
727 /* For each class, number of reload regs needed in that class.
728 This is the maximum over all insns of the needs in that class
729 of the individual insn. */
730 int max_needs[N_REG_CLASSES];
731 /* For each class, size of group of consecutive regs
732 that is needed for the reloads of this class. */
733 int group_size[N_REG_CLASSES];
734 /* For each class, max number of consecutive groups needed.
735 (Each group contains group_size[CLASS] consecutive registers.) */
736 int max_groups[N_REG_CLASSES];
737 /* For each class, max number needed of regs that don't belong
738 to any of the groups. */
739 int max_nongroups[N_REG_CLASSES];
740 /* For each class, the machine mode which requires consecutive
741 groups of regs of that class.
742 If two different modes ever require groups of one class,
743 they must be the same size and equally restrictive for that class,
744 otherwise we can't handle the complexity. */
745 enum machine_mode group_mode[N_REG_CLASSES];
746 /* Record the insn where each maximum need is first found. */
747 rtx max_needs_insn[N_REG_CLASSES];
748 rtx max_groups_insn[N_REG_CLASSES];
749 rtx max_nongroups_insn[N_REG_CLASSES];
751 int starting_frame_size = get_frame_size ();
752 static char *reg_class_names[] = REG_CLASS_NAMES;
754 something_changed = 0;
755 bzero (max_needs, sizeof max_needs);
756 bzero (max_groups, sizeof max_groups);
757 bzero (max_nongroups, sizeof max_nongroups);
758 bzero (max_needs_insn, sizeof max_needs_insn);
759 bzero (max_groups_insn, sizeof max_groups_insn);
760 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
761 bzero (group_size, sizeof group_size);
762 for (i = 0; i < N_REG_CLASSES; i++)
763 group_mode[i] = VOIDmode;
765 /* Keep track of which basic blocks are needing the reloads. */
768 /* Remember whether any element of basic_block_needs
769 changes from 0 to 1 in this pass. */
770 new_basic_block_needs = 0;
772 /* Reset all offsets on eliminable registers to their initial values. */
773 #ifdef ELIMINABLE_REGS
774 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
776 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
777 ep->previous_offset = ep->offset
778 = ep->max_offset = ep->initial_offset;
781 #ifdef INITIAL_FRAME_POINTER_OFFSET
782 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
784 if (!FRAME_POINTER_REQUIRED)
786 reg_eliminate[0].initial_offset = 0;
788 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
789 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
792 num_not_at_initial_offset = 0;
794 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
796 /* Set a known offset for each forced label to be at the initial offset
797 of each elimination. We do this because we assume that all
798 computed jumps occur from a location where each elimination is
799 at its initial offset. */
801 for (x = forced_labels; x; x = XEXP (x, 1))
803 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
805 /* For each pseudo register that has an equivalent location defined,
806 try to eliminate any eliminable registers (such as the frame pointer)
807 assuming initial offsets for the replacement register, which
810 If the resulting location is directly addressable, substitute
811 the MEM we just got directly for the old REG.
813 If it is not addressable but is a constant or the sum of a hard reg
814 and constant, it is probably not addressable because the constant is
815 out of range, in that case record the address; we will generate
816 hairy code to compute the address in a register each time it is
819 If the location is not addressable, but does not have one of the
820 above forms, assign a stack slot. We have to do this to avoid the
821 potential of producing lots of reloads if, e.g., a location involves
822 a pseudo that didn't get a hard register and has an equivalent memory
823 location that also involves a pseudo that didn't get a hard register.
825 Perhaps at some point we will improve reload_when_needed handling
826 so this problem goes away. But that's very hairy. */
828 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
829 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
831 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
833 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
835 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
836 else if (CONSTANT_P (XEXP (x, 0))
837 || (GET_CODE (XEXP (x, 0)) == PLUS
838 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
839 && (REGNO (XEXP (XEXP (x, 0), 0))
840 < FIRST_PSEUDO_REGISTER)
841 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
842 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
845 /* Make a new stack slot. Then indicate that something
846 changed so we go back and recompute offsets for
847 eliminable registers because the allocation of memory
848 below might change some offset. reg_equiv_{mem,address}
849 will be set up for this pseudo on the next pass around
851 reg_equiv_memory_loc[i] = 0;
852 reg_equiv_init[i] = 0;
854 something_changed = 1;
858 /* If we allocated another pseudo to the stack, redo elimination
860 if (something_changed)
863 /* If caller-saves needs a group, initialize the group to include
864 the size and mode required for caller-saves. */
866 if (caller_save_group_size > 1)
868 group_mode[(int) caller_save_spill_class] = Pmode;
869 group_size[(int) caller_save_spill_class] = caller_save_group_size;
872 /* Compute the most additional registers needed by any instruction.
873 Collect information separately for each class of regs. */
875 for (insn = first; insn; insn = NEXT_INSN (insn))
877 if (global && this_block + 1 < n_basic_blocks
878 && insn == basic_block_head[this_block+1])
881 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
882 might include REG_LABEL), we need to see what effects this
883 has on the known offsets at labels. */
885 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
886 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
887 && REG_NOTES (insn) != 0))
888 set_label_offsets (insn, insn, 0);
890 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
892 /* Nonzero means don't use a reload reg that overlaps
893 the place where a function value can be returned. */
894 rtx avoid_return_reg = 0;
896 rtx old_body = PATTERN (insn);
897 int old_code = INSN_CODE (insn);
898 rtx old_notes = REG_NOTES (insn);
899 int did_elimination = 0;
900 int max_total_input_groups = 0, max_total_output_groups = 0;
902 /* To compute the number of reload registers of each class
903 needed for an insn, we must similate what choose_reload_regs
904 can do. We do this by splitting an insn into an "input" and
905 an "output" part. RELOAD_OTHER reloads are used in both.
906 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
907 which must be live over the entire input section of reloads,
908 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
909 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
912 The registers needed for output are RELOAD_OTHER and
913 RELOAD_FOR_OUTPUT, which are live for the entire output
914 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
915 reloads for each operand.
917 The total number of registers needed is the maximum of the
918 inputs and outputs. */
920 /* These just count RELOAD_OTHER. */
921 int insn_needs[N_REG_CLASSES];
922 int insn_groups[N_REG_CLASSES];
923 int insn_total_groups = 0;
925 /* Count RELOAD_FOR_INPUT reloads. */
926 int insn_needs_for_inputs[N_REG_CLASSES];
927 int insn_groups_for_inputs[N_REG_CLASSES];
928 int insn_total_groups_for_inputs = 0;
930 /* Count RELOAD_FOR_OUTPUT reloads. */
931 int insn_needs_for_outputs[N_REG_CLASSES];
932 int insn_groups_for_outputs[N_REG_CLASSES];
933 int insn_total_groups_for_outputs = 0;
935 /* Count RELOAD_FOR_INSN reloads. */
936 int insn_needs_for_insn[N_REG_CLASSES];
937 int insn_groups_for_insn[N_REG_CLASSES];
938 int insn_total_groups_for_insn = 0;
940 /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */
941 int insn_needs_for_other_addr[N_REG_CLASSES];
942 int insn_groups_for_other_addr[N_REG_CLASSES];
943 int insn_total_groups_for_other_addr = 0;
945 /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */
946 int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
947 int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
948 int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS];
950 /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */
951 int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
952 int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
953 int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS];
955 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
956 int insn_needs_for_op_addr[N_REG_CLASSES];
957 int insn_groups_for_op_addr[N_REG_CLASSES];
958 int insn_total_groups_for_op_addr = 0;
960 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
961 looks for non-strict memory addresses. */
962 /* Optimization: a bit-field instruction whose field
963 happens to be a byte or halfword in memory
964 can be changed to a move instruction. */
966 if (GET_CODE (PATTERN (insn)) == SET)
968 rtx dest = SET_DEST (PATTERN (insn));
969 rtx src = SET_SRC (PATTERN (insn));
971 if (GET_CODE (dest) == ZERO_EXTRACT
972 || GET_CODE (dest) == SIGN_EXTRACT)
973 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
974 if (GET_CODE (src) == ZERO_EXTRACT
975 || GET_CODE (src) == SIGN_EXTRACT)
976 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
980 /* If needed, eliminate any eliminable registers. */
982 did_elimination = eliminate_regs_in_insn (insn, 0);
984 #ifdef SMALL_REGISTER_CLASSES
985 /* Set avoid_return_reg if this is an insn
986 that might use the value of a function call. */
987 if (GET_CODE (insn) == CALL_INSN)
989 if (GET_CODE (PATTERN (insn)) == SET)
990 after_call = SET_DEST (PATTERN (insn));
991 else if (GET_CODE (PATTERN (insn)) == PARALLEL
992 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
993 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
997 else if (after_call != 0
998 && !(GET_CODE (PATTERN (insn)) == SET
999 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1001 if (reg_mentioned_p (after_call, PATTERN (insn)))
1002 avoid_return_reg = after_call;
1005 #endif /* SMALL_REGISTER_CLASSES */
1007 /* Analyze the instruction. */
1008 find_reloads (insn, 0, spill_indirect_levels, global,
1011 /* Remember for later shortcuts which insns had any reloads or
1012 register eliminations.
1014 One might think that it would be worthwhile to mark insns
1015 that need register replacements but not reloads, but this is
1016 not safe because find_reloads may do some manipulation of
1017 the insn (such as swapping commutative operands), which would
1018 be lost when we restore the old pattern after register
1019 replacement. So the actions of find_reloads must be redone in
1020 subsequent passes or in reload_as_needed.
1022 However, it is safe to mark insns that need reloads
1023 but not register replacement. */
1025 PUT_MODE (insn, (did_elimination ? QImode
1026 : n_reloads ? HImode
1027 : GET_MODE (insn) == DImode ? DImode
1030 /* Discard any register replacements done. */
1031 if (did_elimination)
1033 obstack_free (&reload_obstack, reload_firstobj);
1034 PATTERN (insn) = old_body;
1035 INSN_CODE (insn) = old_code;
1036 REG_NOTES (insn) = old_notes;
1037 something_needs_elimination = 1;
1040 /* If this insn has no reloads, we need not do anything except
1041 in the case of a CALL_INSN when we have caller-saves and
1042 caller-save needs reloads. */
1045 && ! (GET_CODE (insn) == CALL_INSN
1046 && caller_save_spill_class != NO_REGS))
1049 something_needs_reloads = 1;
1051 for (i = 0; i < N_REG_CLASSES; i++)
1053 insn_needs[i] = 0, insn_groups[i] = 0;
1054 insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1055 insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1056 insn_needs_for_insn[i] = 0, insn_groups_for_insn[i] = 0;
1057 insn_needs_for_op_addr[i] = 0, insn_groups_for_op_addr[i] = 0;
1058 insn_needs_for_other_addr[i] = 0;
1059 insn_groups_for_other_addr[i] = 0;
1062 for (i = 0; i < reload_n_operands; i++)
1064 insn_total_groups_for_in_addr[i] = 0;
1065 insn_total_groups_for_out_addr[i] = 0;
1067 for (j = 0; j < N_REG_CLASSES; j++)
1069 insn_needs_for_in_addr[i][j] = 0;
1070 insn_needs_for_out_addr[i][j] = 0;
1071 insn_groups_for_in_addr[i][j] = 0;
1072 insn_groups_for_out_addr[i][j] = 0;
1076 /* Count each reload once in every class
1077 containing the reload's own class. */
1079 for (i = 0; i < n_reloads; i++)
1081 register enum reg_class *p;
1082 enum reg_class class = reload_reg_class[i];
1084 enum machine_mode mode;
1087 int *this_total_groups;
1089 /* Don't count the dummy reloads, for which one of the
1090 regs mentioned in the insn can be used for reloading.
1091 Don't count optional reloads.
1092 Don't count reloads that got combined with others. */
1093 if (reload_reg_rtx[i] != 0
1094 || reload_optional[i] != 0
1095 || (reload_out[i] == 0 && reload_in[i] == 0
1096 && ! reload_secondary_p[i]))
1099 /* Show that a reload register of this class is needed
1100 in this basic block. We do not use insn_needs and
1101 insn_groups because they are overly conservative for
1103 if (global && ! basic_block_needs[(int) class][this_block])
1105 basic_block_needs[(int) class][this_block] = 1;
1106 new_basic_block_needs = 1;
1109 /* Decide which time-of-use to count this reload for. */
1110 switch (reload_when_needed[i])
1113 this_needs = insn_needs;
1114 this_groups = insn_groups;
1115 this_total_groups = &insn_total_groups;
1118 case RELOAD_FOR_INPUT:
1119 this_needs = insn_needs_for_inputs;
1120 this_groups = insn_groups_for_inputs;
1121 this_total_groups = &insn_total_groups_for_inputs;
1124 case RELOAD_FOR_OUTPUT:
1125 this_needs = insn_needs_for_outputs;
1126 this_groups = insn_groups_for_outputs;
1127 this_total_groups = &insn_total_groups_for_outputs;
1130 case RELOAD_FOR_INSN:
1131 this_needs = insn_needs_for_insn;
1132 this_groups = insn_groups_for_outputs;
1133 this_total_groups = &insn_total_groups_for_insn;
1136 case RELOAD_FOR_OTHER_ADDRESS:
1137 this_needs = insn_needs_for_other_addr;
1138 this_groups = insn_groups_for_other_addr;
1139 this_total_groups = &insn_total_groups_for_other_addr;
1142 case RELOAD_FOR_INPUT_ADDRESS:
1143 this_needs = insn_needs_for_in_addr[reload_opnum[i]];
1144 this_groups = insn_groups_for_in_addr[reload_opnum[i]];
1146 = &insn_total_groups_for_in_addr[reload_opnum[i]];
1149 case RELOAD_FOR_OUTPUT_ADDRESS:
1150 this_needs = insn_needs_for_out_addr[reload_opnum[i]];
1151 this_groups = insn_groups_for_out_addr[reload_opnum[i]];
1153 = &insn_total_groups_for_out_addr[reload_opnum[i]];
1156 case RELOAD_FOR_OPERAND_ADDRESS:
1157 this_needs = insn_needs_for_op_addr;
1158 this_groups = insn_groups_for_op_addr;
1159 this_total_groups = &insn_total_groups_for_op_addr;
1163 mode = reload_inmode[i];
1164 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1165 mode = reload_outmode[i];
1166 size = CLASS_MAX_NREGS (class, mode);
1169 enum machine_mode other_mode, allocate_mode;
1171 /* Count number of groups needed separately from
1172 number of individual regs needed. */
1173 this_groups[(int) class]++;
1174 p = reg_class_superclasses[(int) class];
1175 while (*p != LIM_REG_CLASSES)
1176 this_groups[(int) *p++]++;
1177 (*this_total_groups)++;
1179 /* Record size and mode of a group of this class. */
1180 /* If more than one size group is needed,
1181 make all groups the largest needed size. */
1182 if (group_size[(int) class] < size)
1184 other_mode = group_mode[(int) class];
1185 allocate_mode = mode;
1187 group_size[(int) class] = size;
1188 group_mode[(int) class] = mode;
1193 allocate_mode = group_mode[(int) class];
1196 /* Crash if two dissimilar machine modes both need
1197 groups of consecutive regs of the same class. */
1199 if (other_mode != VOIDmode
1200 && other_mode != allocate_mode
1201 && ! modes_equiv_for_class_p (allocate_mode,
1208 this_needs[(int) class] += 1;
1209 p = reg_class_superclasses[(int) class];
1210 while (*p != LIM_REG_CLASSES)
1211 this_needs[(int) *p++] += 1;
1217 /* All reloads have been counted for this insn;
1218 now merge the various times of use.
1219 This sets insn_needs, etc., to the maximum total number
1220 of registers needed at any point in this insn. */
1222 for (i = 0; i < N_REG_CLASSES; i++)
1224 int in_max, out_max;
1226 for (in_max = 0, out_max = 0, j = 0;
1227 j < reload_n_operands; j++)
1229 in_max = MAX (in_max, insn_needs_for_in_addr[j][i]);
1230 out_max = MAX (out_max, insn_needs_for_out_addr[j][i]);
1233 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1234 and operand addresses but not things used to reload them.
1235 Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't
1236 conflict with things needed to reload inputs or
1239 in_max = MAX (in_max, insn_needs_for_op_addr[i]);
1240 out_max = MAX (out_max, insn_needs_for_insn[i]);
1242 insn_needs_for_inputs[i]
1243 = MAX (insn_needs_for_inputs[i]
1244 + insn_needs_for_op_addr[i]
1245 + insn_needs_for_insn[i],
1246 in_max + insn_needs_for_inputs[i]);
1248 insn_needs_for_outputs[i] += out_max;
1249 insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i],
1250 insn_needs_for_outputs[i]),
1251 insn_needs_for_other_addr[i]);
1253 for (in_max = 0, out_max = 0, j = 0;
1254 j < reload_n_operands; j++)
1256 in_max = MAX (in_max, insn_groups_for_in_addr[j][i]);
1257 out_max = MAX (out_max, insn_groups_for_out_addr[j][i]);
1260 in_max = MAX (in_max, insn_groups_for_op_addr[i]);
1261 out_max = MAX (out_max, insn_groups_for_insn[i]);
1263 insn_groups_for_inputs[i]
1264 = MAX (insn_groups_for_inputs[i]
1265 + insn_groups_for_op_addr[i]
1266 + insn_groups_for_insn[i],
1267 in_max + insn_groups_for_inputs[i]);
1269 insn_groups_for_outputs[i] += out_max;
1270 insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i],
1271 insn_groups_for_outputs[i]),
1272 insn_groups_for_other_addr[i]);
1275 for (i = 0; i < reload_n_operands; i++)
1277 max_total_input_groups
1278 = MAX (max_total_input_groups,
1279 insn_total_groups_for_in_addr[i]);
1280 max_total_output_groups
1281 = MAX (max_total_output_groups,
1282 insn_total_groups_for_out_addr[i]);
1285 max_total_input_groups = MAX (max_total_input_groups,
1286 insn_total_groups_for_op_addr);
1287 max_total_output_groups = MAX (max_total_output_groups,
1288 insn_total_groups_for_insn);
1290 insn_total_groups_for_inputs
1291 = MAX (max_total_input_groups + insn_total_groups_for_op_addr
1292 + insn_total_groups_for_insn,
1293 max_total_input_groups + insn_total_groups_for_inputs);
1295 insn_total_groups_for_outputs += max_total_output_groups;
1297 insn_total_groups += MAX (MAX (insn_total_groups_for_outputs,
1298 insn_total_groups_for_inputs),
1299 insn_total_groups_for_other_addr);
1301 /* If this is a CALL_INSN and caller-saves will need
1302 a spill register, act as if the spill register is
1303 needed for this insn. However, the spill register
1304 can be used by any reload of this insn, so we only
1305 need do something if no need for that class has
1308 The assumption that every CALL_INSN will trigger a
1309 caller-save is highly conservative, however, the number
1310 of cases where caller-saves will need a spill register but
1311 a block containing a CALL_INSN won't need a spill register
1312 of that class should be quite rare.
1314 If a group is needed, the size and mode of the group will
1315 have been set up at the beginning of this loop. */
1317 if (GET_CODE (insn) == CALL_INSN
1318 && caller_save_spill_class != NO_REGS)
1320 int *caller_save_needs
1321 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1323 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1325 register enum reg_class *p
1326 = reg_class_superclasses[(int) caller_save_spill_class];
1328 caller_save_needs[(int) caller_save_spill_class]++;
1330 while (*p != LIM_REG_CLASSES)
1331 caller_save_needs[(int) *p++] += 1;
1334 if (caller_save_group_size > 1)
1335 insn_total_groups = MAX (insn_total_groups, 1);
1338 /* Show that this basic block will need a register of
1342 && ! (basic_block_needs[(int) caller_save_spill_class]
1345 basic_block_needs[(int) caller_save_spill_class]
1347 new_basic_block_needs = 1;
1351 #ifdef SMALL_REGISTER_CLASSES
1352 /* If this insn stores the value of a function call,
1353 and that value is in a register that has been spilled,
1354 and if the insn needs a reload in a class
1355 that might use that register as the reload register,
1356 then add add an extra need in that class.
1357 This makes sure we have a register available that does
1358 not overlap the return value. */
1359 if (avoid_return_reg)
1361 int regno = REGNO (avoid_return_reg);
1363 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1365 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1367 /* First compute the "basic needs", which counts a
1368 need only in the smallest class in which it
1371 bcopy (insn_needs, basic_needs, sizeof basic_needs);
1372 bcopy (insn_groups, basic_groups, sizeof basic_groups);
1374 for (i = 0; i < N_REG_CLASSES; i++)
1378 if (basic_needs[i] >= 0)
1379 for (p = reg_class_superclasses[i];
1380 *p != LIM_REG_CLASSES; p++)
1381 basic_needs[(int) *p] -= basic_needs[i];
1383 if (basic_groups[i] >= 0)
1384 for (p = reg_class_superclasses[i];
1385 *p != LIM_REG_CLASSES; p++)
1386 basic_groups[(int) *p] -= basic_groups[i];
1389 /* Now count extra regs if there might be a conflict with
1390 the return value register.
1392 ??? This is not quite correct because we don't properly
1393 handle the case of groups, but if we end up doing
1394 something wrong, it either will end up not mattering or
1395 we will abort elsewhere. */
1397 for (r = regno; r < regno + nregs; r++)
1398 if (spill_reg_order[r] >= 0)
1399 for (i = 0; i < N_REG_CLASSES; i++)
1400 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1402 if (basic_needs[i] > 0 || basic_groups[i] > 0)
1407 p = reg_class_superclasses[i];
1408 while (*p != LIM_REG_CLASSES)
1409 insn_needs[(int) *p++]++;
1413 #endif /* SMALL_REGISTER_CLASSES */
1415 /* For each class, collect maximum need of any insn. */
1417 for (i = 0; i < N_REG_CLASSES; i++)
1419 if (max_needs[i] < insn_needs[i])
1421 max_needs[i] = insn_needs[i];
1422 max_needs_insn[i] = insn;
1424 if (max_groups[i] < insn_groups[i])
1426 max_groups[i] = insn_groups[i];
1427 max_groups_insn[i] = insn;
1429 if (insn_total_groups > 0)
1430 if (max_nongroups[i] < insn_needs[i])
1432 max_nongroups[i] = insn_needs[i];
1433 max_nongroups_insn[i] = insn;
1437 /* Note that there is a continue statement above. */
1440 /* If we allocated any new memory locations, make another pass
1441 since it might have changed elimination offsets. */
1442 if (starting_frame_size != get_frame_size ())
1443 something_changed = 1;
1446 for (i = 0; i < N_REG_CLASSES; i++)
1448 if (max_needs[i] > 0)
1450 ";; Need %d reg%s of class %s (for insn %d).\n",
1451 max_needs[i], max_needs[i] == 1 ? "" : "s",
1452 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1453 if (max_nongroups[i] > 0)
1455 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1456 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1457 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1458 if (max_groups[i] > 0)
1460 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1461 max_groups[i], max_groups[i] == 1 ? "" : "s",
1462 mode_name[(int) group_mode[i]],
1463 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1466 /* If we have caller-saves, set up the save areas and see if caller-save
1467 will need a spill register. */
1469 if (caller_save_needed
1470 && ! setup_save_areas (&something_changed)
1471 && caller_save_spill_class == NO_REGS)
1473 /* The class we will need depends on whether the machine
1474 supports the sum of two registers for an address; see
1475 find_address_reloads for details. */
1477 caller_save_spill_class
1478 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1479 caller_save_group_size
1480 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1481 something_changed = 1;
1484 /* See if anything that happened changes which eliminations are valid.
1485 For example, on the Sparc, whether or not the frame pointer can
1486 be eliminated can depend on what registers have been used. We need
1487 not check some conditions again (such as flag_omit_frame_pointer)
1488 since they can't have changed. */
1490 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1491 if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1492 #ifdef ELIMINABLE_REGS
1493 || ! CAN_ELIMINATE (ep->from, ep->to)
1496 ep->can_eliminate = 0;
1498 /* Look for the case where we have discovered that we can't replace
1499 register A with register B and that means that we will now be
1500 trying to replace register A with register C. This means we can
1501 no longer replace register C with register B and we need to disable
1502 such an elimination, if it exists. This occurs often with A == ap,
1503 B == sp, and C == fp. */
1505 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1507 struct elim_table *op;
1508 register int new_to = -1;
1510 if (! ep->can_eliminate && ep->can_eliminate_previous)
1512 /* Find the current elimination for ep->from, if there is a
1514 for (op = reg_eliminate;
1515 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1516 if (op->from == ep->from && op->can_eliminate)
1522 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1524 for (op = reg_eliminate;
1525 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1526 if (op->from == new_to && op->to == ep->to)
1527 op->can_eliminate = 0;
1531 /* See if any registers that we thought we could eliminate the previous
1532 time are no longer eliminable. If so, something has changed and we
1533 must spill the register. Also, recompute the number of eliminable
1534 registers and see if the frame pointer is needed; it is if there is
1535 no elimination of the frame pointer that we can perform. */
1537 frame_pointer_needed = 1;
1538 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1540 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1541 frame_pointer_needed = 0;
1543 if (! ep->can_eliminate && ep->can_eliminate_previous)
1545 ep->can_eliminate_previous = 0;
1546 spill_hard_reg (ep->from, global, dumpfile, 1);
1547 regs_ever_live[ep->from] = 1;
1548 something_changed = 1;
1553 /* If all needs are met, we win. */
1555 for (i = 0; i < N_REG_CLASSES; i++)
1556 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1558 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1561 /* Not all needs are met; must spill some hard regs. */
1563 /* Put all registers spilled so far back in potential_reload_regs, but
1564 put them at the front, since we've already spilled most of the
1565 psuedos in them (we might have left some pseudos unspilled if they
1566 were in a block that didn't need any spill registers of a conflicting
1567 class. We used to try to mark off the need for those registers,
1568 but doing so properly is very complex and reallocating them is the
1569 simpler approach. First, "pack" potential_reload_regs by pushing
1570 any nonnegative entries towards the end. That will leave room
1571 for the registers we already spilled.
1573 Also, undo the marking of the spill registers from the last time
1574 around in FORBIDDEN_REGS since we will be probably be allocating
1577 ??? It is theoretically possible that we might end up not using one
1578 of our previously-spilled registers in this allocation, even though
1579 they are at the head of the list. It's not clear what to do about
1580 this, but it was no better before, when we marked off the needs met
1581 by the previously-spilled registers. With the current code, globals
1582 can be allocated into these registers, but locals cannot. */
1586 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1587 if (potential_reload_regs[i] != -1)
1588 potential_reload_regs[j--] = potential_reload_regs[i];
1590 for (i = 0; i < n_spills; i++)
1592 potential_reload_regs[i] = spill_regs[i];
1593 spill_reg_order[spill_regs[i]] = -1;
1594 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1600 /* Now find more reload regs to satisfy the remaining need
1601 Do it by ascending class number, since otherwise a reg
1602 might be spilled for a big class and might fail to count
1603 for a smaller class even though it belongs to that class.
1605 Count spilled regs in `spills', and add entries to
1606 `spill_regs' and `spill_reg_order'.
1608 ??? Note there is a problem here.
1609 When there is a need for a group in a high-numbered class,
1610 and also need for non-group regs that come from a lower class,
1611 the non-group regs are chosen first. If there aren't many regs,
1612 they might leave no room for a group.
1614 This was happening on the 386. To fix it, we added the code
1615 that calls possible_group_p, so that the lower class won't
1616 break up the last possible group.
1618 Really fixing the problem would require changes above
1619 in counting the regs already spilled, and in choose_reload_regs.
1620 It might be hard to avoid introducing bugs there. */
1622 CLEAR_HARD_REG_SET (counted_for_groups);
1623 CLEAR_HARD_REG_SET (counted_for_nongroups);
1625 for (class = 0; class < N_REG_CLASSES; class++)
1627 /* First get the groups of registers.
1628 If we got single registers first, we might fragment
1630 while (max_groups[class] > 0)
1632 /* If any single spilled regs happen to form groups,
1633 count them now. Maybe we don't really need
1634 to spill another group. */
1635 count_possible_groups (group_size, group_mode, max_groups);
1637 if (max_groups[class] <= 0)
1640 /* Groups of size 2 (the only groups used on most machines)
1641 are treated specially. */
1642 if (group_size[class] == 2)
1644 /* First, look for a register that will complete a group. */
1645 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1649 j = potential_reload_regs[i];
1650 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1652 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1653 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1654 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1655 && HARD_REGNO_MODE_OK (other, group_mode[class])
1656 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1658 /* We don't want one part of another group.
1659 We could get "two groups" that overlap! */
1660 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1662 (j < FIRST_PSEUDO_REGISTER - 1
1663 && (other = j + 1, spill_reg_order[other] >= 0)
1664 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1665 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1666 && HARD_REGNO_MODE_OK (j, group_mode[class])
1667 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1669 && ! TEST_HARD_REG_BIT (counted_for_groups,
1672 register enum reg_class *p;
1674 /* We have found one that will complete a group,
1675 so count off one group as provided. */
1676 max_groups[class]--;
1677 p = reg_class_superclasses[class];
1678 while (*p != LIM_REG_CLASSES)
1679 max_groups[(int) *p++]--;
1681 /* Indicate both these regs are part of a group. */
1682 SET_HARD_REG_BIT (counted_for_groups, j);
1683 SET_HARD_REG_BIT (counted_for_groups, other);
1687 /* We can't complete a group, so start one. */
1688 if (i == FIRST_PSEUDO_REGISTER)
1689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1692 j = potential_reload_regs[i];
1693 /* Verify that J+1 is a potential reload reg. */
1694 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1695 if (potential_reload_regs[k] == j + 1)
1697 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1698 && k < FIRST_PSEUDO_REGISTER
1699 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1700 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1701 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1702 && HARD_REGNO_MODE_OK (j, group_mode[class])
1703 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1705 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1709 /* I should be the index in potential_reload_regs
1710 of the new reload reg we have found. */
1712 if (i >= FIRST_PSEUDO_REGISTER)
1714 /* There are no groups left to spill. */
1715 spill_failure (max_groups_insn[class]);
1721 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1726 /* For groups of more than 2 registers,
1727 look for a sufficient sequence of unspilled registers,
1728 and spill them all at once. */
1729 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1733 j = potential_reload_regs[i];
1735 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1736 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1738 /* Check each reg in the sequence. */
1739 for (k = 0; k < group_size[class]; k++)
1740 if (! (spill_reg_order[j + k] < 0
1741 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1742 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1744 /* We got a full sequence, so spill them all. */
1745 if (k == group_size[class])
1747 register enum reg_class *p;
1748 for (k = 0; k < group_size[class]; k++)
1751 SET_HARD_REG_BIT (counted_for_groups, j + k);
1752 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1753 if (potential_reload_regs[idx] == j + k)
1756 |= new_spill_reg (idx, class,
1757 max_needs, NULL_PTR,
1761 /* We have found one that will complete a group,
1762 so count off one group as provided. */
1763 max_groups[class]--;
1764 p = reg_class_superclasses[class];
1765 while (*p != LIM_REG_CLASSES)
1766 max_groups[(int) *p++]--;
1772 /* We couldn't find any registers for this reload.
1773 Avoid going into an infinite loop. */
1774 if (i >= FIRST_PSEUDO_REGISTER)
1776 /* There are no groups left. */
1777 spill_failure (max_groups_insn[class]);
1784 /* Now similarly satisfy all need for single registers. */
1786 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1788 /* Consider the potential reload regs that aren't
1789 yet in use as reload regs, in order of preference.
1790 Find the most preferred one that's in this class. */
1792 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1793 if (potential_reload_regs[i] >= 0
1794 && TEST_HARD_REG_BIT (reg_class_contents[class],
1795 potential_reload_regs[i])
1796 /* If this reg will not be available for groups,
1797 pick one that does not foreclose possible groups.
1798 This is a kludge, and not very general,
1799 but it should be sufficient to make the 386 work,
1800 and the problem should not occur on machines with
1802 && (max_nongroups[class] == 0
1803 || possible_group_p (potential_reload_regs[i], max_groups)))
1806 /* If we couldn't get a register, try to get one even if we
1807 might foreclose possible groups. This may cause problems
1808 later, but that's better than aborting now, since it is
1809 possible that we will, in fact, be able to form the needed
1810 group even with this allocation. */
1812 if (i >= FIRST_PSEUDO_REGISTER
1813 && (asm_noperands (max_needs[class] > 0
1814 ? max_needs_insn[class]
1815 : max_nongroups_insn[class])
1817 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1818 if (potential_reload_regs[i] >= 0
1819 && TEST_HARD_REG_BIT (reg_class_contents[class],
1820 potential_reload_regs[i]))
1823 /* I should be the index in potential_reload_regs
1824 of the new reload reg we have found. */
1826 if (i >= FIRST_PSEUDO_REGISTER)
1828 /* There are no possible registers left to spill. */
1829 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1830 : max_nongroups_insn[class]);
1836 |= new_spill_reg (i, class, max_needs, max_nongroups,
1842 /* If global-alloc was run, notify it of any register eliminations we have
1845 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1846 if (ep->can_eliminate)
1847 mark_elimination (ep->from, ep->to);
1849 /* Insert code to save and restore call-clobbered hard regs
1850 around calls. Tell if what mode to use so that we will process
1851 those insns in reload_as_needed if we have to. */
1853 if (caller_save_needed)
1854 save_call_clobbered_regs (num_eliminable ? QImode
1855 : caller_save_spill_class != NO_REGS ? HImode
1858 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1859 If that insn didn't set the register (i.e., it copied the register to
1860 memory), just delete that insn instead of the equivalencing insn plus
1861 anything now dead. If we call delete_dead_insn on that insn, we may
1862 delete the insn that actually sets the register if the register die
1863 there and that is incorrect. */
1865 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1866 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1867 && GET_CODE (reg_equiv_init[i]) != NOTE)
1869 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1870 delete_dead_insn (reg_equiv_init[i]);
1873 PUT_CODE (reg_equiv_init[i], NOTE);
1874 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1875 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1879 /* Use the reload registers where necessary
1880 by generating move instructions to move the must-be-register
1881 values into or out of the reload registers. */
1883 if (something_needs_reloads || something_needs_elimination
1884 || (caller_save_needed && num_eliminable)
1885 || caller_save_spill_class != NO_REGS)
1886 reload_as_needed (first, global);
1888 /* If we were able to eliminate the frame pointer, show that it is no
1889 longer live at the start of any basic block. If it ls live by
1890 virtue of being in a pseudo, that pseudo will be marked live
1891 and hence the frame pointer will be known to be live via that
1894 if (! frame_pointer_needed)
1895 for (i = 0; i < n_basic_blocks; i++)
1896 basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1897 &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS));
1899 /* Come here (with failure set nonzero) if we can't get enough spill regs
1900 and we decide not to abort about it. */
1903 reload_in_progress = 0;
1905 /* Now eliminate all pseudo regs by modifying them into
1906 their equivalent memory references.
1907 The REG-rtx's for the pseudos are modified in place,
1908 so all insns that used to refer to them now refer to memory.
1910 For a reg that has a reg_equiv_address, all those insns
1911 were changed by reloading so that no insns refer to it any longer;
1912 but the DECL_RTL of a variable decl may refer to it,
1913 and if so this causes the debugging info to mention the variable. */
1915 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1919 if (reg_equiv_mem[i])
1921 addr = XEXP (reg_equiv_mem[i], 0);
1922 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1924 if (reg_equiv_address[i])
1925 addr = reg_equiv_address[i];
1928 if (reg_renumber[i] < 0)
1930 rtx reg = regno_reg_rtx[i];
1931 XEXP (reg, 0) = addr;
1932 REG_USERVAR_P (reg) = 0;
1933 MEM_IN_STRUCT_P (reg) = in_struct;
1934 PUT_CODE (reg, MEM);
1936 else if (reg_equiv_mem[i])
1937 XEXP (reg_equiv_mem[i], 0) = addr;
1941 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1942 /* Make a pass over all the insns and remove death notes for things that
1943 are no longer registers or no longer die in the insn (e.g., an input
1944 and output pseudo being tied). */
1946 for (insn = first; insn; insn = NEXT_INSN (insn))
1947 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1951 for (note = REG_NOTES (insn); note; note = next)
1953 next = XEXP (note, 1);
1954 if (REG_NOTE_KIND (note) == REG_DEAD
1955 && (GET_CODE (XEXP (note, 0)) != REG
1956 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1957 remove_note (insn, note);
1962 /* Indicate that we no longer have known memory locations or constants. */
1963 reg_equiv_constant = 0;
1964 reg_equiv_memory_loc = 0;
1969 /* Nonzero if, after spilling reg REGNO for non-groups,
1970 it will still be possible to find a group if we still need one. */
1973 possible_group_p (regno, max_groups)
1978 int class = (int) NO_REGS;
1980 for (i = 0; i < (int) N_REG_CLASSES; i++)
1981 if (max_groups[i] > 0)
1987 if (class == (int) NO_REGS)
1990 /* Consider each pair of consecutive registers. */
1991 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1993 /* Ignore pairs that include reg REGNO. */
1994 if (i == regno || i + 1 == regno)
1997 /* Ignore pairs that are outside the class that needs the group.
1998 ??? Here we fail to handle the case where two different classes
1999 independently need groups. But this never happens with our
2000 current machine descriptions. */
2001 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2002 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2005 /* A pair of consecutive regs we can still spill does the trick. */
2006 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2007 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2008 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2011 /* A pair of one already spilled and one we can spill does it
2012 provided the one already spilled is not otherwise reserved. */
2013 if (spill_reg_order[i] < 0
2014 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2015 && spill_reg_order[i + 1] >= 0
2016 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2017 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2019 if (spill_reg_order[i + 1] < 0
2020 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2021 && spill_reg_order[i] >= 0
2022 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2023 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2030 /* Count any groups that can be formed from the registers recently spilled.
2031 This is done class by class, in order of ascending class number. */
2034 count_possible_groups (group_size, group_mode, max_groups)
2036 enum machine_mode *group_mode;
2040 /* Now find all consecutive groups of spilled registers
2041 and mark each group off against the need for such groups.
2042 But don't count them against ordinary need, yet. */
2044 for (i = 0; i < N_REG_CLASSES; i++)
2045 if (group_size[i] > 1)
2050 CLEAR_HARD_REG_SET (new);
2052 /* Make a mask of all the regs that are spill regs in class I. */
2053 for (j = 0; j < n_spills; j++)
2054 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
2055 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
2056 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
2058 SET_HARD_REG_BIT (new, spill_regs[j]);
2060 /* Find each consecutive group of them. */
2061 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
2062 if (TEST_HARD_REG_BIT (new, j)
2063 && j + group_size[i] <= FIRST_PSEUDO_REGISTER
2064 /* Next line in case group-mode for this class
2065 demands an even-odd pair. */
2066 && HARD_REGNO_MODE_OK (j, group_mode[i]))
2069 for (k = 1; k < group_size[i]; k++)
2070 if (! TEST_HARD_REG_BIT (new, j + k))
2072 if (k == group_size[i])
2074 /* We found a group. Mark it off against this class's
2075 need for groups, and against each superclass too. */
2076 register enum reg_class *p;
2078 p = reg_class_superclasses[i];
2079 while (*p != LIM_REG_CLASSES)
2080 max_groups[(int) *p++]--;
2081 /* Don't count these registers again. */
2082 for (k = 0; k < group_size[i]; k++)
2083 SET_HARD_REG_BIT (counted_for_groups, j + k);
2085 /* Skip to the last reg in this group. When j is incremented
2086 above, it will then point to the first reg of the next
2094 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2095 another mode that needs to be reloaded for the same register class CLASS.
2096 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2097 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2099 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2100 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2101 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2102 causes unnecessary failures on machines requiring alignment of register
2103 groups when the two modes are different sizes, because the larger mode has
2104 more strict alignment rules than the smaller mode. */
2107 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2108 enum machine_mode allocate_mode, other_mode;
2109 enum reg_class class;
2112 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2114 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2115 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2116 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2122 /* Handle the failure to find a register to spill.
2123 INSN should be one of the insns which needed this particular spill reg. */
2126 spill_failure (insn)
2129 if (asm_noperands (PATTERN (insn)) >= 0)
2130 error_for_asm (insn, "`asm' needs too many reloads");
2135 /* Add a new register to the tables of available spill-registers
2136 (as well as spilling all pseudos allocated to the register).
2137 I is the index of this register in potential_reload_regs.
2138 CLASS is the regclass whose need is being satisfied.
2139 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2140 so that this register can count off against them.
2141 MAX_NONGROUPS is 0 if this register is part of a group.
2142 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2145 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2153 register enum reg_class *p;
2155 int regno = potential_reload_regs[i];
2157 if (i >= FIRST_PSEUDO_REGISTER)
2158 abort (); /* Caller failed to find any register. */
2160 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2161 fatal ("fixed or forbidden register was spilled.\n\
2162 This may be due to a compiler bug or to impossible asm statements.");
2164 /* Make reg REGNO an additional reload reg. */
2166 potential_reload_regs[i] = -1;
2167 spill_regs[n_spills] = regno;
2168 spill_reg_order[regno] = n_spills;
2170 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2172 /* Clear off the needs we just satisfied. */
2175 p = reg_class_superclasses[class];
2176 while (*p != LIM_REG_CLASSES)
2177 max_needs[(int) *p++]--;
2179 if (max_nongroups && max_nongroups[class] > 0)
2181 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2182 max_nongroups[class]--;
2183 p = reg_class_superclasses[class];
2184 while (*p != LIM_REG_CLASSES)
2185 max_nongroups[(int) *p++]--;
2188 /* Spill every pseudo reg that was allocated to this reg
2189 or to something that overlaps this reg. */
2191 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2193 /* If there are some registers still to eliminate and this register
2194 wasn't ever used before, additional stack space may have to be
2195 allocated to store this register. Thus, we may have changed the offset
2196 between the stack and frame pointers, so mark that something has changed.
2197 (If new pseudos were spilled, thus requiring more space, VAL would have
2198 been set non-zero by the call to spill_hard_reg above since additional
2199 reloads may be needed in that case.
2201 One might think that we need only set VAL to 1 if this is a call-used
2202 register. However, the set of registers that must be saved by the
2203 prologue is not identical to the call-used set. For example, the
2204 register used by the call insn for the return PC is a call-used register,
2205 but must be saved by the prologue. */
2206 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2209 regs_ever_live[spill_regs[n_spills]] = 1;
2215 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2216 data that is dead in INSN. */
2219 delete_dead_insn (insn)
2222 rtx prev = prev_real_insn (insn);
2225 /* If the previous insn sets a register that dies in our insn, delete it
2227 if (prev && GET_CODE (PATTERN (prev)) == SET
2228 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2229 && reg_mentioned_p (prev_dest, PATTERN (insn))
2230 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2231 delete_dead_insn (prev);
2233 PUT_CODE (insn, NOTE);
2234 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2235 NOTE_SOURCE_FILE (insn) = 0;
2238 /* Modify the home of pseudo-reg I.
2239 The new home is present in reg_renumber[I].
2241 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2242 or it may be -1, meaning there is none or it is not relevant.
2243 This is used so that all pseudos spilled from a given hard reg
2244 can share one stack slot. */
2247 alter_reg (i, from_reg)
2251 /* When outputting an inline function, this can happen
2252 for a reg that isn't actually used. */
2253 if (regno_reg_rtx[i] == 0)
2256 /* If the reg got changed to a MEM at rtl-generation time,
2258 if (GET_CODE (regno_reg_rtx[i]) != REG)
2261 /* Modify the reg-rtx to contain the new hard reg
2262 number or else to contain its pseudo reg number. */
2263 REGNO (regno_reg_rtx[i])
2264 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2266 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2267 allocate a stack slot for it. */
2269 if (reg_renumber[i] < 0
2270 && reg_n_refs[i] > 0
2271 && reg_equiv_constant[i] == 0
2272 && reg_equiv_memory_loc[i] == 0)
2275 int inherent_size = PSEUDO_REGNO_BYTES (i);
2276 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2279 /* Each pseudo reg has an inherent size which comes from its own mode,
2280 and a total size which provides room for paradoxical subregs
2281 which refer to the pseudo reg in wider modes.
2283 We can use a slot already allocated if it provides both
2284 enough inherent space and enough total space.
2285 Otherwise, we allocate a new slot, making sure that it has no less
2286 inherent space, and no less total space, then the previous slot. */
2289 /* No known place to spill from => no slot to reuse. */
2290 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2291 #if BYTES_BIG_ENDIAN
2292 /* Cancel the big-endian correction done in assign_stack_local.
2293 Get the address of the beginning of the slot.
2294 This is so we can do a big-endian correction unconditionally
2296 adjust = inherent_size - total_size;
2299 /* Reuse a stack slot if possible. */
2300 else if (spill_stack_slot[from_reg] != 0
2301 && spill_stack_slot_width[from_reg] >= total_size
2302 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2304 x = spill_stack_slot[from_reg];
2305 /* Allocate a bigger slot. */
2308 /* Compute maximum size needed, both for inherent size
2309 and for total size. */
2310 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2311 if (spill_stack_slot[from_reg])
2313 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2315 mode = GET_MODE (spill_stack_slot[from_reg]);
2316 if (spill_stack_slot_width[from_reg] > total_size)
2317 total_size = spill_stack_slot_width[from_reg];
2319 /* Make a slot with that size. */
2320 x = assign_stack_local (mode, total_size, -1);
2321 #if BYTES_BIG_ENDIAN
2322 /* Cancel the big-endian correction done in assign_stack_local.
2323 Get the address of the beginning of the slot.
2324 This is so we can do a big-endian correction unconditionally
2326 adjust = GET_MODE_SIZE (mode) - total_size;
2328 spill_stack_slot[from_reg] = x;
2329 spill_stack_slot_width[from_reg] = total_size;
2332 #if BYTES_BIG_ENDIAN
2333 /* On a big endian machine, the "address" of the slot
2334 is the address of the low part that fits its inherent mode. */
2335 if (inherent_size < total_size)
2336 adjust += (total_size - inherent_size);
2337 #endif /* BYTES_BIG_ENDIAN */
2339 /* If we have any adjustment to make, or if the stack slot is the
2340 wrong mode, make a new stack slot. */
2341 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2343 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2344 plus_constant (XEXP (x, 0), adjust));
2345 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2348 /* Save the stack slot for later. */
2349 reg_equiv_memory_loc[i] = x;
2353 /* Mark the slots in regs_ever_live for the hard regs
2354 used by pseudo-reg number REGNO. */
2357 mark_home_live (regno)
2360 register int i, lim;
2361 i = reg_renumber[regno];
2364 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2366 regs_ever_live[i++] = 1;
2369 /* This function handles the tracking of elimination offsets around branches.
2371 X is a piece of RTL being scanned.
2373 INSN is the insn that it came from, if any.
2375 INITIAL_P is non-zero if we are to set the offset to be the initial
2376 offset and zero if we are setting the offset of the label to be the
2380 set_label_offsets (x, insn, initial_p)
2385 enum rtx_code code = GET_CODE (x);
2388 struct elim_table *p;
2393 if (LABEL_REF_NONLOCAL_P (x))
2398 /* ... fall through ... */
2401 /* If we know nothing about this label, set the desired offsets. Note
2402 that this sets the offset at a label to be the offset before a label
2403 if we don't know anything about the label. This is not correct for
2404 the label after a BARRIER, but is the best guess we can make. If
2405 we guessed wrong, we will suppress an elimination that might have
2406 been possible had we been able to guess correctly. */
2408 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2410 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2411 offsets_at[CODE_LABEL_NUMBER (x)][i]
2412 = (initial_p ? reg_eliminate[i].initial_offset
2413 : reg_eliminate[i].offset);
2414 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2417 /* Otherwise, if this is the definition of a label and it is
2418 preceded by a BARRIER, set our offsets to the known offset of
2422 && (tem = prev_nonnote_insn (insn)) != 0
2423 && GET_CODE (tem) == BARRIER)
2425 num_not_at_initial_offset = 0;
2426 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2428 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2429 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2430 if (reg_eliminate[i].can_eliminate
2431 && (reg_eliminate[i].offset
2432 != reg_eliminate[i].initial_offset))
2433 num_not_at_initial_offset++;
2438 /* If neither of the above cases is true, compare each offset
2439 with those previously recorded and suppress any eliminations
2440 where the offsets disagree. */
2442 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2443 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2444 != (initial_p ? reg_eliminate[i].initial_offset
2445 : reg_eliminate[i].offset))
2446 reg_eliminate[i].can_eliminate = 0;
2451 set_label_offsets (PATTERN (insn), insn, initial_p);
2453 /* ... fall through ... */
2457 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2458 and hence must have all eliminations at their initial offsets. */
2459 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2460 if (REG_NOTE_KIND (tem) == REG_LABEL)
2461 set_label_offsets (XEXP (tem, 0), insn, 1);
2466 /* Each of the labels in the address vector must be at their initial
2467 offsets. We want the first first for ADDR_VEC and the second
2468 field for ADDR_DIFF_VEC. */
2470 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2471 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2476 /* We only care about setting PC. If the source is not RETURN,
2477 IF_THEN_ELSE, or a label, disable any eliminations not at
2478 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2479 isn't one of those possibilities. For branches to a label,
2480 call ourselves recursively.
2482 Note that this can disable elimination unnecessarily when we have
2483 a non-local goto since it will look like a non-constant jump to
2484 someplace in the current function. This isn't a significant
2485 problem since such jumps will normally be when all elimination
2486 pairs are back to their initial offsets. */
2488 if (SET_DEST (x) != pc_rtx)
2491 switch (GET_CODE (SET_SRC (x)))
2498 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2502 tem = XEXP (SET_SRC (x), 1);
2503 if (GET_CODE (tem) == LABEL_REF)
2504 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2505 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2508 tem = XEXP (SET_SRC (x), 2);
2509 if (GET_CODE (tem) == LABEL_REF)
2510 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2511 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2516 /* If we reach here, all eliminations must be at their initial
2517 offset because we are doing a jump to a variable address. */
2518 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2519 if (p->offset != p->initial_offset)
2520 p->can_eliminate = 0;
2524 /* Used for communication between the next two function to properly share
2525 the vector for an ASM_OPERANDS. */
2527 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2529 /* Scan X and replace any eliminable registers (such as fp) with a
2530 replacement (such as sp), plus an offset.
2532 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2533 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2534 MEM, we are allowed to replace a sum of a register and the constant zero
2535 with the register, which we cannot do outside a MEM. In addition, we need
2536 to record the fact that a register is referenced outside a MEM.
2538 If INSN is nonzero, it is the insn containing X. If we replace a REG
2539 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2540 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2541 that the REG is being modified.
2543 If we see a modification to a register we know about, take the
2544 appropriate action (see case SET, below).
2546 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2547 replacements done assuming all offsets are at their initial values. If
2548 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2549 encounter, return the actual location so that find_reloads will do
2550 the proper thing. */
2553 eliminate_regs (x, mem_mode, insn)
2555 enum machine_mode mem_mode;
2558 enum rtx_code code = GET_CODE (x);
2559 struct elim_table *ep;
2584 /* First handle the case where we encounter a bare register that
2585 is eliminable. Replace it with a PLUS. */
2586 if (regno < FIRST_PSEUDO_REGISTER)
2588 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2590 if (ep->from_rtx == x && ep->can_eliminate)
2593 ep->ref_outside_mem = 1;
2594 return plus_constant (ep->to_rtx, ep->previous_offset);
2598 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2599 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2601 /* In this case, find_reloads would attempt to either use an
2602 incorrect address (if something is not at its initial offset)
2603 or substitute an replaced address into an insn (which loses
2604 if the offset is changed by some later action). So we simply
2605 return the replaced stack slot (assuming it is changed by
2606 elimination) and ignore the fact that this is actually a
2607 reference to the pseudo. Ensure we make a copy of the
2608 address in case it is shared. */
2609 new = eliminate_regs (reg_equiv_memory_loc[regno],
2610 mem_mode, NULL_RTX);
2611 if (new != reg_equiv_memory_loc[regno])
2613 cannot_omit_stores[regno] = 1;
2614 return copy_rtx (new);
2620 /* If this is the sum of an eliminable register and a constant, rework
2622 if (GET_CODE (XEXP (x, 0)) == REG
2623 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2624 && CONSTANT_P (XEXP (x, 1)))
2626 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2628 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2631 ep->ref_outside_mem = 1;
2633 /* The only time we want to replace a PLUS with a REG (this
2634 occurs when the constant operand of the PLUS is the negative
2635 of the offset) is when we are inside a MEM. We won't want
2636 to do so at other times because that would change the
2637 structure of the insn in a way that reload can't handle.
2638 We special-case the commonest situation in
2639 eliminate_regs_in_insn, so just replace a PLUS with a
2640 PLUS here, unless inside a MEM. */
2641 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2642 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2645 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2646 plus_constant (XEXP (x, 1),
2647 ep->previous_offset));
2650 /* If the register is not eliminable, we are done since the other
2651 operand is a constant. */
2655 /* If this is part of an address, we want to bring any constant to the
2656 outermost PLUS. We will do this by doing register replacement in
2657 our operands and seeing if a constant shows up in one of them.
2659 We assume here this is part of an address (or a "load address" insn)
2660 since an eliminable register is not likely to appear in any other
2663 If we have (plus (eliminable) (reg)), we want to produce
2664 (plus (plus (replacement) (reg) (const))). If this was part of a
2665 normal add insn, (plus (replacement) (reg)) will be pushed as a
2666 reload. This is the desired action. */
2669 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2670 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2672 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2674 /* If one side is a PLUS and the other side is a pseudo that
2675 didn't get a hard register but has a reg_equiv_constant,
2676 we must replace the constant here since it may no longer
2677 be in the position of any operand. */
2678 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2679 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2680 && reg_renumber[REGNO (new1)] < 0
2681 && reg_equiv_constant != 0
2682 && reg_equiv_constant[REGNO (new1)] != 0)
2683 new1 = reg_equiv_constant[REGNO (new1)];
2684 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2685 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2686 && reg_renumber[REGNO (new0)] < 0
2687 && reg_equiv_constant[REGNO (new0)] != 0)
2688 new0 = reg_equiv_constant[REGNO (new0)];
2690 new = form_sum (new0, new1);
2692 /* As above, if we are not inside a MEM we do not want to
2693 turn a PLUS into something else. We might try to do so here
2694 for an addition of 0 if we aren't optimizing. */
2695 if (! mem_mode && GET_CODE (new) != PLUS)
2696 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2704 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2707 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2708 if (new != XEXP (x, 0))
2709 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2712 /* ... fall through ... */
2715 /* Now do eliminations in the rest of the chain. If this was
2716 an EXPR_LIST, this might result in allocating more memory than is
2717 strictly needed, but it simplifies the code. */
2720 new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2721 if (new != XEXP (x, 1))
2722 return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2730 case DIV: case UDIV:
2731 case MOD: case UMOD:
2732 case AND: case IOR: case XOR:
2733 case LSHIFT: case ASHIFT: case ROTATE:
2734 case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2736 case GE: case GT: case GEU: case GTU:
2737 case LE: case LT: case LEU: case LTU:
2739 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2741 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0;
2743 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2744 return gen_rtx (code, GET_MODE (x), new0, new1);
2752 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2753 if (ep->to_rtx == XEXP (x, 0))
2755 int size = GET_MODE_SIZE (mem_mode);
2757 /* If more bytes than MEM_MODE are pushed, account for them. */
2758 #ifdef PUSH_ROUNDING
2759 if (ep->to_rtx == stack_pointer_rtx)
2760 size = PUSH_ROUNDING (size);
2762 if (code == PRE_DEC || code == POST_DEC)
2768 /* Fall through to generic unary operation case. */
2770 case STRICT_LOW_PART:
2772 case SIGN_EXTEND: case ZERO_EXTEND:
2773 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2774 case FLOAT: case FIX:
2775 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2779 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2780 if (new != XEXP (x, 0))
2781 return gen_rtx (code, GET_MODE (x), new);
2785 /* Similar to above processing, but preserve SUBREG_WORD.
2786 Convert (subreg (mem)) to (mem) if not paradoxical.
2787 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2788 pseudo didn't get a hard reg, we must replace this with the
2789 eliminated version of the memory location because push_reloads
2790 may do the replacement in certain circumstances. */
2791 if (GET_CODE (SUBREG_REG (x)) == REG
2792 && (GET_MODE_SIZE (GET_MODE (x))
2793 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2794 && reg_equiv_memory_loc != 0
2795 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2797 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2798 mem_mode, NULL_RTX);
2800 /* If we didn't change anything, we must retain the pseudo. */
2801 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2804 /* Otherwise, ensure NEW isn't shared in case we have to reload
2806 new = copy_rtx (new);
2809 new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX);
2811 if (new != XEXP (x, 0))
2813 if (GET_CODE (new) == MEM
2814 && (GET_MODE_SIZE (GET_MODE (x))
2815 <= GET_MODE_SIZE (GET_MODE (new)))
2816 #if defined(BYTES_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
2817 /* On these machines we will be reloading what is
2818 inside the SUBREG if it originally was a pseudo and
2819 the inner and outer modes are both a word or
2820 smaller. So leave the SUBREG then. */
2821 && ! (GET_CODE (SUBREG_REG (x)) == REG
2822 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
2823 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD)
2827 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2828 enum machine_mode mode = GET_MODE (x);
2830 #if BYTES_BIG_ENDIAN
2831 offset += (MIN (UNITS_PER_WORD,
2832 GET_MODE_SIZE (GET_MODE (new)))
2833 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2836 PUT_MODE (new, mode);
2837 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2841 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2847 /* If clobbering a register that is the replacement register for an
2848 elimination we still think can be performed, note that it cannot
2849 be performed. Otherwise, we need not be concerned about it. */
2850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2851 if (ep->to_rtx == XEXP (x, 0))
2852 ep->can_eliminate = 0;
2854 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2855 if (new != XEXP (x, 0))
2856 return gen_rtx (code, GET_MODE (x), new);
2862 /* Properly handle sharing input and constraint vectors. */
2863 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2865 /* When we come to a new vector not seen before,
2866 scan all its elements; keep the old vector if none
2867 of them changes; otherwise, make a copy. */
2868 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2869 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2870 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2871 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2872 mem_mode, NULL_RTX);
2874 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2875 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2878 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2879 new_asm_operands_vec = old_asm_operands_vec;
2881 new_asm_operands_vec
2882 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2885 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2886 if (new_asm_operands_vec == old_asm_operands_vec)
2889 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2890 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2891 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2892 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2893 ASM_OPERANDS_SOURCE_FILE (x),
2894 ASM_OPERANDS_SOURCE_LINE (x));
2895 new->volatil = x->volatil;
2900 /* Check for setting a register that we know about. */
2901 if (GET_CODE (SET_DEST (x)) == REG)
2903 /* See if this is setting the replacement register for an
2906 If DEST is the frame pointer, we do nothing because we assume that
2907 all assignments to the frame pointer are for non-local gotos and
2908 are being done at a time when they are valid and do not disturb
2909 anything else. Some machines want to eliminate a fake argument
2910 pointer with either the frame or stack pointer. Assignments to
2911 the frame pointer must not prevent this elimination. */
2913 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2915 if (ep->to_rtx == SET_DEST (x)
2916 && SET_DEST (x) != frame_pointer_rtx)
2918 /* If it is being incremented, adjust the offset. Otherwise,
2919 this elimination can't be done. */
2920 rtx src = SET_SRC (x);
2922 if (GET_CODE (src) == PLUS
2923 && XEXP (src, 0) == SET_DEST (x)
2924 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2925 ep->offset -= INTVAL (XEXP (src, 1));
2927 ep->can_eliminate = 0;
2930 /* Now check to see we are assigning to a register that can be
2931 eliminated. If so, it must be as part of a PARALLEL, since we
2932 will not have been called if this is a single SET. So indicate
2933 that we can no longer eliminate this reg. */
2934 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2936 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2937 ep->can_eliminate = 0;
2940 /* Now avoid the loop below in this common case. */
2942 rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX);
2943 rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX);
2945 /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2946 write a CLOBBER insn. */
2947 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2949 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2951 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2952 return gen_rtx (SET, VOIDmode, new0, new1);
2958 /* Our only special processing is to pass the mode of the MEM to our
2959 recursive call and copy the flags. While we are here, handle this
2960 case more efficiently. */
2961 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX);
2962 if (new != XEXP (x, 0))
2964 new = gen_rtx (MEM, GET_MODE (x), new);
2965 new->volatil = x->volatil;
2966 new->unchanging = x->unchanging;
2967 new->in_struct = x->in_struct;
2974 /* Process each of our operands recursively. If any have changed, make a
2976 fmt = GET_RTX_FORMAT (code);
2977 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2981 new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX);
2982 if (new != XEXP (x, i) && ! copied)
2984 rtx new_x = rtx_alloc (code);
2985 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2986 + (sizeof (new_x->fld[0])
2987 * GET_RTX_LENGTH (code))));
2993 else if (*fmt == 'E')
2996 for (j = 0; j < XVECLEN (x, i); j++)
2998 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2999 if (new != XVECEXP (x, i, j) && ! copied_vec)
3001 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3002 &XVECEXP (x, i, 0));
3005 rtx new_x = rtx_alloc (code);
3006 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
3007 + (sizeof (new_x->fld[0])
3008 * GET_RTX_LENGTH (code))));
3012 XVEC (x, i) = new_v;
3015 XVECEXP (x, i, j) = new;
3023 /* Scan INSN and eliminate all eliminable registers in it.
3025 If REPLACE is nonzero, do the replacement destructively. Also
3026 delete the insn as dead it if it is setting an eliminable register.
3028 If REPLACE is zero, do all our allocations in reload_obstack.
3030 If no eliminations were done and this insn doesn't require any elimination
3031 processing (these are not identical conditions: it might be updating sp,
3032 but not referencing fp; this needs to be seen during reload_as_needed so
3033 that the offset between fp and sp can be taken into consideration), zero
3034 is returned. Otherwise, 1 is returned. */
3037 eliminate_regs_in_insn (insn, replace)
3041 rtx old_body = PATTERN (insn);
3044 struct elim_table *ep;
3047 push_obstacks (&reload_obstack, &reload_obstack);
3049 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
3050 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
3052 /* Check for setting an eliminable register. */
3053 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3054 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
3056 /* In this case this insn isn't serving a useful purpose. We
3057 will delete it in reload_as_needed once we know that this
3058 elimination is, in fact, being done.
3060 If REPLACE isn't set, we can't delete this insn, but neededn't
3061 process it since it won't be used unless something changes. */
3063 delete_dead_insn (insn);
3068 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3069 in the insn is the negative of the offset in FROM. Substitute
3070 (set (reg) (reg to)) for the insn and change its code.
3072 We have to do this here, rather than in eliminate_regs, do that we can
3073 change the insn code. */
3075 if (GET_CODE (SET_SRC (old_body)) == PLUS
3076 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
3077 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
3078 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3080 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
3081 && ep->can_eliminate
3082 && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
3084 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3085 SET_DEST (old_body), ep->to_rtx);
3086 INSN_CODE (insn) = -1;
3092 old_asm_operands_vec = 0;
3094 /* Replace the body of this insn with a substituted form. If we changed
3095 something, return non-zero. If this is the final call for this
3096 insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
3098 If we are replacing a body that was a (set X (plus Y Z)), try to
3099 re-recognize the insn. We do this in case we had a simple addition
3100 but now can do this as a load-address. This saves an insn in this
3103 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3104 if (new_body != old_body)
3106 /* If we aren't replacing things permanently and we changed something,
3107 make another copy to ensure that all the RTL is new. Otherwise
3108 things can go wrong if find_reload swaps commutative operands
3109 and one is inside RTL that has been copied while the other is not. */
3111 /* Don't copy an asm_operands because (1) there's no need and (2)
3112 copy_rtx can't do it properly when there are multiple outputs. */
3113 if (! replace && asm_noperands (old_body) < 0)
3114 new_body = copy_rtx (new_body);
3116 /* If we had a move insn but now we don't, rerecognize it. */
3117 if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG
3118 && (GET_CODE (new_body) != SET
3119 || GET_CODE (SET_SRC (new_body)) != REG))
3120 /* If this was an add insn before, rerecognize. */
3122 (GET_CODE (old_body) == SET
3123 && GET_CODE (SET_SRC (old_body)) == PLUS))
3125 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3126 /* If recognition fails, store the new body anyway.
3127 It's normal to have recognition failures here
3128 due to bizarre memory addresses; reloading will fix them. */
3129 PATTERN (insn) = new_body;
3132 PATTERN (insn) = new_body;
3134 if (replace && REG_NOTES (insn))
3135 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX);
3139 /* Loop through all elimination pairs. See if any have changed and
3140 recalculate the number not at initial offset.
3142 Compute the maximum offset (minimum offset if the stack does not
3143 grow downward) for each elimination pair.
3145 We also detect a cases where register elimination cannot be done,
3146 namely, if a register would be both changed and referenced outside a MEM
3147 in the resulting insn since such an insn is often undefined and, even if
3148 not, we cannot know what meaning will be given to it. Note that it is
3149 valid to have a register used in an address in an insn that changes it
3150 (presumably with a pre- or post-increment or decrement).
3152 If anything changes, return nonzero. */
3154 num_not_at_initial_offset = 0;
3155 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3157 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3158 ep->can_eliminate = 0;
3160 ep->ref_outside_mem = 0;
3162 if (ep->previous_offset != ep->offset)
3165 ep->previous_offset = ep->offset;
3166 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3167 num_not_at_initial_offset++;
3169 #ifdef STACK_GROWS_DOWNWARD
3170 ep->max_offset = MAX (ep->max_offset, ep->offset);
3172 ep->max_offset = MIN (ep->max_offset, ep->offset);
3183 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3184 replacement we currently believe is valid, mark it as not eliminable if X
3185 modifies DEST in any way other than by adding a constant integer to it.
3187 If DEST is the frame pointer, we do nothing because we assume that
3188 all assignments to the frame pointer are nonlocal gotos and are being done
3189 at a time when they are valid and do not disturb anything else.
3190 Some machines want to eliminate a fake argument pointer with either the
3191 frame or stack pointer. Assignments to the frame pointer must not prevent
3194 Called via note_stores from reload before starting its passes to scan
3195 the insns of the function. */
3198 mark_not_eliminable (dest, x)
3204 /* A SUBREG of a hard register here is just changing its mode. We should
3205 not see a SUBREG of an eliminable hard register, but check just in
3207 if (GET_CODE (dest) == SUBREG)
3208 dest = SUBREG_REG (dest);
3210 if (dest == frame_pointer_rtx)
3213 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3214 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3215 && (GET_CODE (x) != SET
3216 || GET_CODE (SET_SRC (x)) != PLUS
3217 || XEXP (SET_SRC (x), 0) != dest
3218 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3220 reg_eliminate[i].can_eliminate_previous
3221 = reg_eliminate[i].can_eliminate = 0;
3226 /* Kick all pseudos out of hard register REGNO.
3227 If GLOBAL is nonzero, try to find someplace else to put them.
3228 If DUMPFILE is nonzero, log actions taken on that file.
3230 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3231 because we found we can't eliminate some register. In the case, no pseudos
3232 are allowed to be in the register, even if they are only in a block that
3233 doesn't require spill registers, unlike the case when we are spilling this
3234 hard reg to produce another spill register.
3236 Return nonzero if any pseudos needed to be kicked out. */
3239 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3245 int something_changed = 0;
3248 SET_HARD_REG_BIT (forbidden_regs, regno);
3250 /* Spill every pseudo reg that was allocated to this reg
3251 or to something that overlaps this reg. */
3253 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3254 if (reg_renumber[i] >= 0
3255 && reg_renumber[i] <= regno
3257 + HARD_REGNO_NREGS (reg_renumber[i],
3258 PSEUDO_REGNO_MODE (i))
3261 enum reg_class class = REGNO_REG_CLASS (regno);
3263 /* If this register belongs solely to a basic block which needed no
3264 spilling of any class that this register is contained in,
3265 leave it be, unless we are spilling this register because
3266 it was a hard register that can't be eliminated. */
3268 if (! cant_eliminate
3269 && basic_block_needs[0]
3270 && reg_basic_block[i] >= 0
3271 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3275 for (p = reg_class_superclasses[(int) class];
3276 *p != LIM_REG_CLASSES; p++)
3277 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3280 if (*p == LIM_REG_CLASSES)
3284 /* Mark it as no longer having a hard register home. */
3285 reg_renumber[i] = -1;
3286 /* We will need to scan everything again. */
3287 something_changed = 1;
3289 retry_global_alloc (i, forbidden_regs);
3291 alter_reg (i, regno);
3294 if (reg_renumber[i] == -1)
3295 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3297 fprintf (dumpfile, " Register %d now in %d.\n\n",
3298 i, reg_renumber[i]);
3302 return something_changed;
3305 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3308 scan_paradoxical_subregs (x)
3313 register enum rtx_code code = GET_CODE (x);
3330 if (GET_CODE (SUBREG_REG (x)) == REG
3331 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3332 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3333 = GET_MODE_SIZE (GET_MODE (x));
3337 fmt = GET_RTX_FORMAT (code);
3338 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3341 scan_paradoxical_subregs (XEXP (x, i));
3342 else if (fmt[i] == 'E')
3345 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3346 scan_paradoxical_subregs (XVECEXP (x, i, j));
3352 hard_reg_use_compare (p1, p2)
3353 struct hard_reg_n_uses *p1, *p2;
3355 int tem = p1->uses - p2->uses;
3356 if (tem != 0) return tem;
3357 /* If regs are equally good, sort by regno,
3358 so that the results of qsort leave nothing to chance. */
3359 return p1->regno - p2->regno;
3362 /* Choose the order to consider regs for use as reload registers
3363 based on how much trouble would be caused by spilling one.
3364 Store them in order of decreasing preference in potential_reload_regs. */
3367 order_regs_for_reload ()
3373 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3375 CLEAR_HARD_REG_SET (bad_spill_regs);
3377 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3378 potential_reload_regs[i] = -1;
3380 /* Count number of uses of each hard reg by pseudo regs allocated to it
3381 and then order them by decreasing use. */
3383 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3385 hard_reg_n_uses[i].uses = 0;
3386 hard_reg_n_uses[i].regno = i;
3389 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3391 int regno = reg_renumber[i];
3394 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3396 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3398 large += reg_n_refs[i];
3401 /* Now fixed registers (which cannot safely be used for reloading)
3402 get a very high use count so they will be considered least desirable.
3403 Registers used explicitly in the rtl code are almost as bad. */
3405 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3409 hard_reg_n_uses[i].uses += 2 * large + 2;
3410 SET_HARD_REG_BIT (bad_spill_regs, i);
3412 else if (regs_explicitly_used[i])
3414 hard_reg_n_uses[i].uses += large + 1;
3415 #ifndef SMALL_REGISTER_CLASSES
3416 /* ??? We are doing this here because of the potential that
3417 bad code may be generated if a register explicitly used in
3418 an insn was used as a spill register for that insn. But
3419 not using these are spill registers may lose on some machine.
3420 We'll have to see how this works out. */
3421 SET_HARD_REG_BIT (bad_spill_regs, i);
3425 hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3426 SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3428 #ifdef ELIMINABLE_REGS
3429 /* If registers other than the frame pointer are eliminable, mark them as
3431 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3433 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3434 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3438 /* Prefer registers not so far used, for use in temporary loading.
3439 Among them, if REG_ALLOC_ORDER is defined, use that order.
3440 Otherwise, prefer registers not preserved by calls. */
3442 #ifdef REG_ALLOC_ORDER
3443 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3445 int regno = reg_alloc_order[i];
3447 if (hard_reg_n_uses[regno].uses == 0)
3448 potential_reload_regs[o++] = regno;
3451 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3453 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3454 potential_reload_regs[o++] = i;
3456 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3458 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3459 potential_reload_regs[o++] = i;
3463 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3464 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3466 /* Now add the regs that are already used,
3467 preferring those used less often. The fixed and otherwise forbidden
3468 registers will be at the end of this list. */
3470 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3471 if (hard_reg_n_uses[i].uses != 0)
3472 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3475 /* Reload pseudo-registers into hard regs around each insn as needed.
3476 Additional register load insns are output before the insn that needs it
3477 and perhaps store insns after insns that modify the reloaded pseudo reg.
3479 reg_last_reload_reg and reg_reloaded_contents keep track of
3480 which registers are already available in reload registers.
3481 We update these for the reloads that we perform,
3482 as the insns are scanned. */
3485 reload_as_needed (first, live_known)
3495 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3496 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3497 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3498 reg_has_output_reload = (char *) alloca (max_regno);
3499 for (i = 0; i < n_spills; i++)
3501 reg_reloaded_contents[i] = -1;
3502 reg_reloaded_insn[i] = 0;
3505 /* Reset all offsets on eliminable registers to their initial values. */
3506 #ifdef ELIMINABLE_REGS
3507 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3509 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3510 reg_eliminate[i].initial_offset);
3511 reg_eliminate[i].previous_offset
3512 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3515 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3516 reg_eliminate[0].previous_offset
3517 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3520 num_not_at_initial_offset = 0;
3522 for (insn = first; insn;)
3524 register rtx next = NEXT_INSN (insn);
3526 /* Notice when we move to a new basic block. */
3527 if (live_known && this_block + 1 < n_basic_blocks
3528 && insn == basic_block_head[this_block+1])
3531 /* If we pass a label, copy the offsets from the label information
3532 into the current offsets of each elimination. */
3533 if (GET_CODE (insn) == CODE_LABEL)
3535 num_not_at_initial_offset = 0;
3536 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3538 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3539 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3540 if (reg_eliminate[i].can_eliminate
3541 && (reg_eliminate[i].offset
3542 != reg_eliminate[i].initial_offset))
3543 num_not_at_initial_offset++;
3547 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3549 rtx avoid_return_reg = 0;
3551 #ifdef SMALL_REGISTER_CLASSES
3552 /* Set avoid_return_reg if this is an insn
3553 that might use the value of a function call. */
3554 if (GET_CODE (insn) == CALL_INSN)
3556 if (GET_CODE (PATTERN (insn)) == SET)
3557 after_call = SET_DEST (PATTERN (insn));
3558 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3559 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3560 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3564 else if (after_call != 0
3565 && !(GET_CODE (PATTERN (insn)) == SET
3566 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3568 if (reg_mentioned_p (after_call, PATTERN (insn)))
3569 avoid_return_reg = after_call;
3572 #endif /* SMALL_REGISTER_CLASSES */
3574 /* If this is a USE and CLOBBER of a MEM, ensure that any
3575 references to eliminable registers have been removed. */
3577 if ((GET_CODE (PATTERN (insn)) == USE
3578 || GET_CODE (PATTERN (insn)) == CLOBBER)
3579 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3580 XEXP (XEXP (PATTERN (insn), 0), 0)
3581 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3582 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3584 /* If we need to do register elimination processing, do so.
3585 This might delete the insn, in which case we are done. */
3586 if (num_eliminable && GET_MODE (insn) == QImode)
3588 eliminate_regs_in_insn (insn, 1);
3589 if (GET_CODE (insn) == NOTE)
3596 if (GET_MODE (insn) == VOIDmode)
3598 /* First find the pseudo regs that must be reloaded for this insn.
3599 This info is returned in the tables reload_... (see reload.h).
3600 Also modify the body of INSN by substituting RELOAD
3601 rtx's for those pseudo regs. */
3604 bzero (reg_has_output_reload, max_regno);
3605 CLEAR_HARD_REG_SET (reg_is_output_reload);
3607 find_reloads (insn, 1, spill_indirect_levels, live_known,
3613 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3617 /* If this block has not had spilling done for a
3618 particular clas and we have any non-optionals that need a
3619 spill reg in that class, abort. */
3621 for (class = 0; class < N_REG_CLASSES; class++)
3622 if (basic_block_needs[class] != 0
3623 && basic_block_needs[class][this_block] == 0)
3624 for (i = 0; i < n_reloads; i++)
3625 if (class == (int) reload_reg_class[i]
3626 && reload_reg_rtx[i] == 0
3627 && ! reload_optional[i]
3628 && (reload_in[i] != 0 || reload_out[i] != 0
3629 || reload_secondary_p[i] != 0))
3632 /* Now compute which reload regs to reload them into. Perhaps
3633 reusing reload regs from previous insns, or else output
3634 load insns to reload them. Maybe output store insns too.
3635 Record the choices of reload reg in reload_reg_rtx. */
3636 choose_reload_regs (insn, avoid_return_reg);
3638 #ifdef SMALL_REGISTER_CLASSES
3639 /* Merge any reloads that we didn't combine for fear of
3640 increasing the number of spill registers needed but now
3641 discover can be safely merged. */
3642 merge_assigned_reloads (insn);
3645 /* Generate the insns to reload operands into or out of
3646 their reload regs. */
3647 emit_reload_insns (insn);
3649 /* Substitute the chosen reload regs from reload_reg_rtx
3650 into the insn's body (or perhaps into the bodies of other
3651 load and store insn that we just made for reloading
3652 and that we moved the structure into). */
3655 /* If this was an ASM, make sure that all the reload insns
3656 we have generated are valid. If not, give an error
3659 if (asm_noperands (PATTERN (insn)) >= 0)
3660 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3661 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3662 && (recog_memoized (p) < 0
3663 || (insn_extract (p),
3664 ! constrain_operands (INSN_CODE (p), 1))))
3666 error_for_asm (insn,
3667 "`asm' operand requires impossible reload");
3669 NOTE_SOURCE_FILE (p) = 0;
3670 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3673 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3674 is no longer validly lying around to save a future reload.
3675 Note that this does not detect pseudos that were reloaded
3676 for this insn in order to be stored in
3677 (obeying register constraints). That is correct; such reload
3678 registers ARE still valid. */
3679 note_stores (PATTERN (insn), forget_old_reloads_1);
3681 /* There may have been CLOBBER insns placed after INSN. So scan
3682 between INSN and NEXT and use them to forget old reloads. */
3683 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3684 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3685 note_stores (PATTERN (x), forget_old_reloads_1);
3688 /* Likewise for regs altered by auto-increment in this insn.
3689 But note that the reg-notes are not changed by reloading:
3690 they still contain the pseudo-regs, not the spill regs. */
3691 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3692 if (REG_NOTE_KIND (x) == REG_INC)
3694 /* See if this pseudo reg was reloaded in this insn.
3695 If so, its last-reload info is still valid
3696 because it is based on this insn's reload. */
3697 for (i = 0; i < n_reloads; i++)
3698 if (reload_out[i] == XEXP (x, 0))
3702 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
3706 /* A reload reg's contents are unknown after a label. */
3707 if (GET_CODE (insn) == CODE_LABEL)
3708 for (i = 0; i < n_spills; i++)
3710 reg_reloaded_contents[i] = -1;
3711 reg_reloaded_insn[i] = 0;
3714 /* Don't assume a reload reg is still good after a call insn
3715 if it is a call-used reg. */
3716 else if (GET_CODE (insn) == CALL_INSN)
3717 for (i = 0; i < n_spills; i++)
3718 if (call_used_regs[spill_regs[i]])
3720 reg_reloaded_contents[i] = -1;
3721 reg_reloaded_insn[i] = 0;
3724 /* In case registers overlap, allow certain insns to invalidate
3725 particular hard registers. */
3727 #ifdef INSN_CLOBBERS_REGNO_P
3728 for (i = 0 ; i < n_spills ; i++)
3729 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3731 reg_reloaded_contents[i] = -1;
3732 reg_reloaded_insn[i] = 0;
3744 /* Discard all record of any value reloaded from X,
3745 or reloaded in X from someplace else;
3746 unless X is an output reload reg of the current insn.
3748 X may be a hard reg (the reload reg)
3749 or it may be a pseudo reg that was reloaded from. */
3752 forget_old_reloads_1 (x, ignored)
3760 /* note_stores does give us subregs of hard regs. */
3761 while (GET_CODE (x) == SUBREG)
3763 offset += SUBREG_WORD (x);
3767 if (GET_CODE (x) != REG)
3770 regno = REGNO (x) + offset;
3772 if (regno >= FIRST_PSEUDO_REGISTER)
3777 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3778 /* Storing into a spilled-reg invalidates its contents.
3779 This can happen if a block-local pseudo is allocated to that reg
3780 and it wasn't spilled because this block's total need is 0.
3781 Then some insn might have an optional reload and use this reg. */
3782 for (i = 0; i < nr; i++)
3783 if (spill_reg_order[regno + i] >= 0
3784 /* But don't do this if the reg actually serves as an output
3785 reload reg in the current instruction. */
3787 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3789 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3790 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3794 /* Since value of X has changed,
3795 forget any value previously copied from it. */
3798 /* But don't forget a copy if this is the output reload
3799 that establishes the copy's validity. */
3800 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3801 reg_last_reload_reg[regno + nr] = 0;
3804 /* For each reload, the mode of the reload register. */
3805 static enum machine_mode reload_mode[MAX_RELOADS];
3807 /* For each reload, the largest number of registers it will require. */
3808 static int reload_nregs[MAX_RELOADS];
3810 /* Comparison function for qsort to decide which of two reloads
3811 should be handled first. *P1 and *P2 are the reload numbers. */
3814 reload_reg_class_lower (p1, p2)
3817 register int r1 = *p1, r2 = *p2;
3820 /* Consider required reloads before optional ones. */
3821 t = reload_optional[r1] - reload_optional[r2];
3825 /* Count all solitary classes before non-solitary ones. */
3826 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3827 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3831 /* Aside from solitaires, consider all multi-reg groups first. */
3832 t = reload_nregs[r2] - reload_nregs[r1];
3836 /* Consider reloads in order of increasing reg-class number. */
3837 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3841 /* If reloads are equally urgent, sort by reload number,
3842 so that the results of qsort leave nothing to chance. */
3846 /* The following HARD_REG_SETs indicate when each hard register is
3847 used for a reload of various parts of the current insn. */
3849 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3850 static HARD_REG_SET reload_reg_used;
3851 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
3852 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
3853 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
3854 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
3855 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
3856 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
3857 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
3858 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
3859 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3860 static HARD_REG_SET reload_reg_used_in_op_addr;
3861 /* If reg is in use for a RELOAD_FOR_INSN reload. */
3862 static HARD_REG_SET reload_reg_used_in_insn;
3863 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
3864 static HARD_REG_SET reload_reg_used_in_other_addr;
3866 /* If reg is in use as a reload reg for any sort of reload. */
3867 static HARD_REG_SET reload_reg_used_at_all;
3869 /* If reg is use as an inherited reload. We just mark the first register
3871 static HARD_REG_SET reload_reg_used_for_inherit;
3873 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
3874 TYPE. MODE is used to indicate how many consecutive regs are
3878 mark_reload_reg_in_use (regno, opnum, type, mode)
3881 enum reload_type type;
3882 enum machine_mode mode;
3884 int nregs = HARD_REGNO_NREGS (regno, mode);
3887 for (i = regno; i < nregs + regno; i++)
3892 SET_HARD_REG_BIT (reload_reg_used, i);
3895 case RELOAD_FOR_INPUT_ADDRESS:
3896 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
3899 case RELOAD_FOR_OUTPUT_ADDRESS:
3900 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
3903 case RELOAD_FOR_OPERAND_ADDRESS:
3904 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3907 case RELOAD_FOR_OTHER_ADDRESS:
3908 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
3911 case RELOAD_FOR_INPUT:
3912 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
3915 case RELOAD_FOR_OUTPUT:
3916 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
3919 case RELOAD_FOR_INSN:
3920 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
3924 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3928 /* Similarly, but show REGNO is no longer in use for a reload. */
3931 clear_reload_reg_in_use (regno, opnum, type, mode)
3934 enum reload_type type;
3935 enum machine_mode mode;
3937 int nregs = HARD_REGNO_NREGS (regno, mode);
3940 for (i = regno; i < nregs + regno; i++)
3945 CLEAR_HARD_REG_BIT (reload_reg_used, i);
3948 case RELOAD_FOR_INPUT_ADDRESS:
3949 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
3952 case RELOAD_FOR_OUTPUT_ADDRESS:
3953 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
3956 case RELOAD_FOR_OPERAND_ADDRESS:
3957 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3960 case RELOAD_FOR_OTHER_ADDRESS:
3961 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
3964 case RELOAD_FOR_INPUT:
3965 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
3968 case RELOAD_FOR_OUTPUT:
3969 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
3972 case RELOAD_FOR_INSN:
3973 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
3979 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3980 specified by OPNUM and TYPE. */
3983 reload_reg_free_p (regno, opnum, type)
3986 enum reload_type type;
3990 /* In use for a RELOAD_OTHER means it's not available for anything except
3991 RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
3992 to be used only for inputs. */
3994 if (type != RELOAD_FOR_OTHER_ADDRESS
3995 && TEST_HARD_REG_BIT (reload_reg_used, regno))
4001 /* In use for anything means not available for a RELOAD_OTHER. */
4002 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
4004 /* The other kinds of use can sometimes share a register. */
4005 case RELOAD_FOR_INPUT:
4006 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4007 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4010 /* If it is used for some other input, can't use it. */
4011 for (i = 0; i < reload_n_operands; i++)
4012 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4015 /* If it is used in a later operand's address, can't use it. */
4016 for (i = opnum + 1; i < reload_n_operands; i++)
4017 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4022 case RELOAD_FOR_INPUT_ADDRESS:
4023 /* Can't use a register if it is used for an input address for this
4024 operand or used as an input in an earlier one. */
4025 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
4028 for (i = 0; i < opnum; i++)
4029 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4034 case RELOAD_FOR_OUTPUT_ADDRESS:
4035 /* Can't use a register if it is used for an output address for this
4036 operand or used as an output in this or a later operand. */
4037 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4040 for (i = opnum; i < reload_n_operands; i++)
4041 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4046 case RELOAD_FOR_OPERAND_ADDRESS:
4047 for (i = 0; i < reload_n_operands; i++)
4048 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4051 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4052 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4054 case RELOAD_FOR_OUTPUT:
4055 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4056 outputs, or an operand address for this or an earlier output. */
4057 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4060 for (i = 0; i < reload_n_operands; i++)
4061 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4064 for (i = 0; i <= opnum; i++)
4065 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4070 case RELOAD_FOR_INSN:
4071 for (i = 0; i < reload_n_operands; i++)
4072 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4073 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4076 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4077 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4079 case RELOAD_FOR_OTHER_ADDRESS:
4080 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4085 /* Return 1 if the value in reload reg REGNO, as used by a reload
4086 needed for the part of the insn specified by OPNUM and TYPE,
4087 is not in use for a reload in any prior part of the insn.
4089 We can assume that the reload reg was already tested for availability
4090 at the time it is needed, and we should not check this again,
4091 in case the reg has already been marked in use. */
4094 reload_reg_free_before_p (regno, opnum, type)
4097 enum reload_type type;
4103 case RELOAD_FOR_OTHER_ADDRESS:
4104 /* These always come first. */
4108 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4110 /* If this use is for part of the insn,
4111 check the reg is not in use for any prior part. It is tempting
4112 to try to do this by falling through from objecs that occur
4113 later in the insn to ones that occur earlier, but that will not
4114 correctly take into account the fact that here we MUST ignore
4115 things that would prevent the register from being allocated in
4116 the first place, since we know that it was allocated. */
4118 case RELOAD_FOR_OUTPUT_ADDRESS:
4119 /* Earlier reloads are for earlier outputs or their addresses,
4120 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4121 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4123 for (i = 0; i < opnum; i++)
4124 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4125 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4128 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4131 for (i = 0; i < reload_n_operands; i++)
4132 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4133 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4136 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4137 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4138 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4140 case RELOAD_FOR_OUTPUT:
4141 /* This can't be used in the output address for this operand and
4142 anything that can't be used for it, except that we've already
4143 tested for RELOAD_FOR_INSN objects. */
4145 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4148 for (i = 0; i < opnum; i++)
4149 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4150 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4153 for (i = 0; i < reload_n_operands; i++)
4154 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4155 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4156 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4159 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4161 case RELOAD_FOR_OPERAND_ADDRESS:
4162 case RELOAD_FOR_INSN:
4163 /* These can't conflict with inputs, or each other, so all we have to
4164 test is input addresses and the addresses of OTHER items. */
4166 for (i = 0; i < reload_n_operands; i++)
4167 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4170 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4172 case RELOAD_FOR_INPUT:
4173 /* The only things earlier are the address for this and
4174 earlier inputs, other inputs (which we know we don't conflict
4175 with), and addresses of RELOAD_OTHER objects. */
4177 for (i = 0; i <= opnum; i++)
4178 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4181 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4183 case RELOAD_FOR_INPUT_ADDRESS:
4184 /* Similarly, all we have to check is for use in earlier inputs'
4186 for (i = 0; i < opnum; i++)
4187 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4190 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4195 /* Return 1 if the value in reload reg REGNO, as used by a reload
4196 needed for the part of the insn specified by OPNUM and TYPE,
4197 is still available in REGNO at the end of the insn.
4199 We can assume that the reload reg was already tested for availability
4200 at the time it is needed, and we should not check this again,
4201 in case the reg has already been marked in use. */
4204 reload_reg_reaches_end_p (regno, opnum, type)
4207 enum reload_type type;
4214 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4215 its value must reach the end. */
4218 /* If this use is for part of the insn,
4219 its value reaches if no subsequent part uses the same register.
4220 Just like the above function, don't try to do this with lots
4223 case RELOAD_FOR_OTHER_ADDRESS:
4224 /* Here we check for everything else, since these don't conflict
4225 with anything else and everything comes later. */
4227 for (i = 0; i < reload_n_operands; i++)
4228 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4229 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4230 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4231 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4234 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4235 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4236 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4238 case RELOAD_FOR_INPUT_ADDRESS:
4239 /* Similar, except that we check only for this and subsequent inputs
4240 and the address of only subsequent inputs and we do not need
4241 to check for RELOAD_OTHER objects since they are known not to
4244 for (i = opnum; i < reload_n_operands; i++)
4245 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4248 for (i = opnum + 1; i < reload_n_operands; i++)
4249 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4252 for (i = 0; i < reload_n_operands; i++)
4253 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4254 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4257 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4258 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4260 case RELOAD_FOR_INPUT:
4261 /* Similar to input address, except we start at the next operand for
4262 both input and input address and we do not check for
4263 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4266 for (i = opnum + 1; i < reload_n_operands; i++)
4267 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4268 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4271 /* ... fall through ... */
4273 case RELOAD_FOR_OPERAND_ADDRESS:
4274 /* Check outputs and their addresses. */
4276 for (i = 0; i < reload_n_operands; i++)
4277 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4278 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4283 case RELOAD_FOR_INSN:
4284 /* These conflict with other outputs with with RELOAD_OTHER. So
4285 we need only check for output addresses. */
4289 /* ... fall through ... */
4291 case RELOAD_FOR_OUTPUT:
4292 case RELOAD_FOR_OUTPUT_ADDRESS:
4293 /* We already know these can't conflict with a later output. So the
4294 only thing to check are later output addresses. */
4295 for (i = opnum + 1; i < reload_n_operands; i++)
4296 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4305 /* Vector of reload-numbers showing the order in which the reloads should
4307 short reload_order[MAX_RELOADS];
4309 /* Indexed by reload number, 1 if incoming value
4310 inherited from previous insns. */
4311 char reload_inherited[MAX_RELOADS];
4313 /* For an inherited reload, this is the insn the reload was inherited from,
4314 if we know it. Otherwise, this is 0. */
4315 rtx reload_inheritance_insn[MAX_RELOADS];
4317 /* If non-zero, this is a place to get the value of the reload,
4318 rather than using reload_in. */
4319 rtx reload_override_in[MAX_RELOADS];
4321 /* For each reload, the index in spill_regs of the spill register used,
4322 or -1 if we did not need one of the spill registers for this reload. */
4323 int reload_spill_index[MAX_RELOADS];
4325 /* Index of last register assigned as a spill register. We allocate in
4326 a round-robin fashio. */
4328 static int last_spill_reg = 0;
4330 /* Find a spill register to use as a reload register for reload R.
4331 LAST_RELOAD is non-zero if this is the last reload for the insn being
4334 Set reload_reg_rtx[R] to the register allocated.
4336 If NOERROR is nonzero, we return 1 if successful,
4337 or 0 if we couldn't find a spill reg and we didn't change anything. */
4340 allocate_reload_reg (r, insn, last_reload, noerror)
4352 /* If we put this reload ahead, thinking it is a group,
4353 then insist on finding a group. Otherwise we can grab a
4354 reg that some other reload needs.
4355 (That can happen when we have a 68000 DATA_OR_FP_REG
4356 which is a group of data regs or one fp reg.)
4357 We need not be so restrictive if there are no more reloads
4360 ??? Really it would be nicer to have smarter handling
4361 for that kind of reg class, where a problem like this is normal.
4362 Perhaps those classes should be avoided for reloading
4363 by use of more alternatives. */
4365 int force_group = reload_nregs[r] > 1 && ! last_reload;
4367 /* If we want a single register and haven't yet found one,
4368 take any reg in the right class and not in use.
4369 If we want a consecutive group, here is where we look for it.
4371 We use two passes so we can first look for reload regs to
4372 reuse, which are already in use for other reloads in this insn,
4373 and only then use additional registers.
4374 I think that maximizing reuse is needed to make sure we don't
4375 run out of reload regs. Suppose we have three reloads, and
4376 reloads A and B can share regs. These need two regs.
4377 Suppose A and B are given different regs.
4378 That leaves none for C. */
4379 for (pass = 0; pass < 2; pass++)
4381 /* I is the index in spill_regs.
4382 We advance it round-robin between insns to use all spill regs
4383 equally, so that inherited reloads have a chance
4384 of leapfrogging each other. */
4386 for (count = 0, i = last_spill_reg; count < n_spills; count++)
4388 int class = (int) reload_reg_class[r];
4390 i = (i + 1) % n_spills;
4392 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4393 reload_when_needed[r])
4394 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4395 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4396 /* Look first for regs to share, then for unshared. But
4397 don't share regs used for inherited reloads; they are
4398 the ones we want to preserve. */
4400 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4402 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4405 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4406 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4407 (on 68000) got us two FP regs. If NR is 1,
4408 we would reject both of them. */
4410 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4411 /* If we need only one reg, we have already won. */
4414 /* But reject a single reg if we demand a group. */
4419 /* Otherwise check that as many consecutive regs as we need
4421 Also, don't use for a group registers that are
4422 needed for nongroups. */
4423 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4426 regno = spill_regs[i] + nr - 1;
4427 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4428 && spill_reg_order[regno] >= 0
4429 && reload_reg_free_p (regno, reload_opnum[r],
4430 reload_when_needed[r])
4431 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4441 /* If we found something on pass 1, omit pass 2. */
4442 if (count < n_spills)
4446 /* We should have found a spill register by now. */
4447 if (count == n_spills)
4454 /* I is the index in SPILL_REG_RTX of the reload register we are to
4455 allocate. Get an rtx for it and find its register number. */
4457 new = spill_reg_rtx[i];
4459 if (new == 0 || GET_MODE (new) != reload_mode[r])
4460 spill_reg_rtx[i] = new
4461 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4463 regno = true_regnum (new);
4465 /* Detect when the reload reg can't hold the reload mode.
4466 This used to be one `if', but Sequent compiler can't handle that. */
4467 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4469 enum machine_mode test_mode = VOIDmode;
4471 test_mode = GET_MODE (reload_in[r]);
4472 /* If reload_in[r] has VOIDmode, it means we will load it
4473 in whatever mode the reload reg has: to wit, reload_mode[r].
4474 We have already tested that for validity. */
4475 /* Aside from that, we need to test that the expressions
4476 to reload from or into have modes which are valid for this
4477 reload register. Otherwise the reload insns would be invalid. */
4478 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4479 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4480 if (! (reload_out[r] != 0
4481 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4483 /* The reg is OK. */
4486 /* Mark as in use for this insn the reload regs we use
4488 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4489 reload_when_needed[r], reload_mode[r]);
4491 reload_reg_rtx[r] = new;
4492 reload_spill_index[r] = i;
4497 /* The reg is not OK. */
4502 if (asm_noperands (PATTERN (insn)) < 0)
4503 /* It's the compiler's fault. */
4506 /* It's the user's fault; the operand's mode and constraint
4507 don't match. Disable this reload so we don't crash in final. */
4508 error_for_asm (insn,
4509 "`asm' operand constraint incompatible with operand size");
4512 reload_reg_rtx[r] = 0;
4513 reload_optional[r] = 1;
4514 reload_secondary_p[r] = 1;
4519 /* Assign hard reg targets for the pseudo-registers we must reload
4520 into hard regs for this insn.
4521 Also output the instructions to copy them in and out of the hard regs.
4523 For machines with register classes, we are responsible for
4524 finding a reload reg in the proper class. */
4527 choose_reload_regs (insn, avoid_return_reg)
4529 rtx avoid_return_reg;
4532 int max_group_size = 1;
4533 enum reg_class group_class = NO_REGS;
4536 rtx save_reload_reg_rtx[MAX_RELOADS];
4537 char save_reload_inherited[MAX_RELOADS];
4538 rtx save_reload_inheritance_insn[MAX_RELOADS];
4539 rtx save_reload_override_in[MAX_RELOADS];
4540 int save_reload_spill_index[MAX_RELOADS];
4541 HARD_REG_SET save_reload_reg_used;
4542 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4543 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4544 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4545 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4546 HARD_REG_SET save_reload_reg_used_in_op_addr;
4547 HARD_REG_SET save_reload_reg_used_in_insn;
4548 HARD_REG_SET save_reload_reg_used_in_other_addr;
4549 HARD_REG_SET save_reload_reg_used_at_all;
4551 bzero (reload_inherited, MAX_RELOADS);
4552 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4553 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4555 CLEAR_HARD_REG_SET (reload_reg_used);
4556 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4557 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4558 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4559 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4561 for (i = 0; i < reload_n_operands; i++)
4563 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4564 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4565 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4566 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4569 #ifdef SMALL_REGISTER_CLASSES
4570 /* Don't bother with avoiding the return reg
4571 if we have no mandatory reload that could use it. */
4572 if (avoid_return_reg)
4575 int regno = REGNO (avoid_return_reg);
4577 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4580 for (r = regno; r < regno + nregs; r++)
4581 if (spill_reg_order[r] >= 0)
4582 for (j = 0; j < n_reloads; j++)
4583 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4584 && (reload_in[j] != 0 || reload_out[j] != 0
4585 || reload_secondary_p[j])
4587 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4590 avoid_return_reg = 0;
4592 #endif /* SMALL_REGISTER_CLASSES */
4594 #if 0 /* Not needed, now that we can always retry without inheritance. */
4595 /* See if we have more mandatory reloads than spill regs.
4596 If so, then we cannot risk optimizations that could prevent
4597 reloads from sharing one spill register.
4599 Since we will try finding a better register than reload_reg_rtx
4600 unless it is equal to reload_in or reload_out, count such reloads. */
4604 #ifdef SMALL_REGISTER_CLASSES
4605 int tem = (avoid_return_reg != 0);
4607 for (j = 0; j < n_reloads; j++)
4608 if (! reload_optional[j]
4609 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4610 && (reload_reg_rtx[j] == 0
4611 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4612 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4619 #ifdef SMALL_REGISTER_CLASSES
4620 /* Don't use the subroutine call return reg for a reload
4621 if we are supposed to avoid it. */
4622 if (avoid_return_reg)
4624 int regno = REGNO (avoid_return_reg);
4626 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4629 for (r = regno; r < regno + nregs; r++)
4630 if (spill_reg_order[r] >= 0)
4631 SET_HARD_REG_BIT (reload_reg_used, r);
4633 #endif /* SMALL_REGISTER_CLASSES */
4635 /* In order to be certain of getting the registers we need,
4636 we must sort the reloads into order of increasing register class.
4637 Then our grabbing of reload registers will parallel the process
4638 that provided the reload registers.
4640 Also note whether any of the reloads wants a consecutive group of regs.
4641 If so, record the maximum size of the group desired and what
4642 register class contains all the groups needed by this insn. */
4644 for (j = 0; j < n_reloads; j++)
4646 reload_order[j] = j;
4647 reload_spill_index[j] = -1;
4650 = (reload_inmode[j] == VOIDmode
4651 || (GET_MODE_SIZE (reload_outmode[j])
4652 > GET_MODE_SIZE (reload_inmode[j])))
4653 ? reload_outmode[j] : reload_inmode[j];
4655 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4657 if (reload_nregs[j] > 1)
4659 max_group_size = MAX (reload_nregs[j], max_group_size);
4660 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4663 /* If we have already decided to use a certain register,
4664 don't use it in another way. */
4665 if (reload_reg_rtx[j])
4666 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
4667 reload_when_needed[j], reload_mode[j]);
4671 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4673 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4674 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4675 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4676 sizeof reload_inheritance_insn);
4677 bcopy (reload_override_in, save_reload_override_in,
4678 sizeof reload_override_in);
4679 bcopy (reload_spill_index, save_reload_spill_index,
4680 sizeof reload_spill_index);
4681 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4682 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4683 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4684 reload_reg_used_in_op_addr);
4685 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
4686 reload_reg_used_in_insn);
4687 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
4688 reload_reg_used_in_other_addr);
4690 for (i = 0; i < reload_n_operands; i++)
4692 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
4693 reload_reg_used_in_output[i]);
4694 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
4695 reload_reg_used_in_input[i]);
4696 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
4697 reload_reg_used_in_input_addr[i]);
4698 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
4699 reload_reg_used_in_output_addr[i]);
4702 /* If -O, try first with inheritance, then turning it off.
4703 If not -O, don't do inheritance.
4704 Using inheritance when not optimizing leads to paradoxes
4705 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
4706 because one side of the comparison might be inherited. */
4708 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
4710 /* Process the reloads in order of preference just found.
4711 Beyond this point, subregs can be found in reload_reg_rtx.
4713 This used to look for an existing reloaded home for all
4714 of the reloads, and only then perform any new reloads.
4715 But that could lose if the reloads were done out of reg-class order
4716 because a later reload with a looser constraint might have an old
4717 home in a register needed by an earlier reload with a tighter constraint.
4719 To solve this, we make two passes over the reloads, in the order
4720 described above. In the first pass we try to inherit a reload
4721 from a previous insn. If there is a later reload that needs a
4722 class that is a proper subset of the class being processed, we must
4723 also allocate a spill register during the first pass.
4725 Then make a second pass over the reloads to allocate any reloads
4726 that haven't been given registers yet. */
4728 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
4730 for (j = 0; j < n_reloads; j++)
4732 register int r = reload_order[j];
4734 /* Ignore reloads that got marked inoperative. */
4735 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4738 /* If find_reloads chose a to use reload_in or reload_out as a reload
4739 register, we don't need to chose one. Otherwise, try even if it found
4740 one since we might save an insn if we find the value lying around. */
4741 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4742 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4743 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4746 #if 0 /* No longer needed for correct operation.
4747 It might give better code, or might not; worth an experiment? */
4748 /* If this is an optional reload, we can't inherit from earlier insns
4749 until we are sure that any non-optional reloads have been allocated.
4750 The following code takes advantage of the fact that optional reloads
4751 are at the end of reload_order. */
4752 if (reload_optional[r] != 0)
4753 for (i = 0; i < j; i++)
4754 if ((reload_out[reload_order[i]] != 0
4755 || reload_in[reload_order[i]] != 0
4756 || reload_secondary_p[reload_order[i]])
4757 && ! reload_optional[reload_order[i]]
4758 && reload_reg_rtx[reload_order[i]] == 0)
4759 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4762 /* First see if this pseudo is already available as reloaded
4763 for a previous insn. We cannot try to inherit for reloads
4764 that are smaller than the maximum number of registers needed
4765 for groups unless the register we would allocate cannot be used
4768 We could check here to see if this is a secondary reload for
4769 an object that is already in a register of the desired class.
4770 This would avoid the need for the secondary reload register.
4771 But this is complex because we can't easily determine what
4772 objects might want to be loaded via this reload. So let a register
4773 be allocated here. In `emit_reload_insns' we suppress one of the
4774 loads in the case described above. */
4778 register int regno = -1;
4779 enum machine_mode mode;
4781 if (reload_in[r] == 0)
4783 else if (GET_CODE (reload_in[r]) == REG)
4785 regno = REGNO (reload_in[r]);
4786 mode = GET_MODE (reload_in[r]);
4788 else if (GET_CODE (reload_in_reg[r]) == REG)
4790 regno = REGNO (reload_in_reg[r]);
4791 mode = GET_MODE (reload_in_reg[r]);
4794 /* This won't work, since REGNO can be a pseudo reg number.
4795 Also, it takes much more hair to keep track of all the things
4796 that can invalidate an inherited reload of part of a pseudoreg. */
4797 else if (GET_CODE (reload_in[r]) == SUBREG
4798 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4799 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4802 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4804 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4806 if (reg_reloaded_contents[i] == regno
4807 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
4808 >= GET_MODE_SIZE (mode))
4809 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4810 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4812 && (reload_nregs[r] == max_group_size
4813 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4815 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
4816 reload_when_needed[r])
4817 && reload_reg_free_before_p (spill_regs[i],
4819 reload_when_needed[r]))
4821 /* If a group is needed, verify that all the subsequent
4822 registers still have their values intact. */
4824 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4827 for (k = 1; k < nr; k++)
4828 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4836 /* We found a register that contains the
4837 value we need. If this register is the
4838 same as an `earlyclobber' operand of the
4839 current insn, just mark it as a place to
4840 reload from since we can't use it as the
4841 reload register itself. */
4843 for (i1 = 0; i1 < n_earlyclobbers; i1++)
4844 if (reg_overlap_mentioned_for_reload_p
4845 (reg_last_reload_reg[regno],
4846 reload_earlyclobbers[i1]))
4849 if (i1 != n_earlyclobbers
4850 /* Don't really use the inherited spill reg
4851 if we need it wider than we've got it. */
4852 || (GET_MODE_SIZE (reload_mode[r])
4853 > GET_MODE_SIZE (mode)))
4854 reload_override_in[r] = reg_last_reload_reg[regno];
4857 /* We can use this as a reload reg. */
4858 /* Mark the register as in use for this part of
4860 mark_reload_reg_in_use (spill_regs[i],
4862 reload_when_needed[r],
4864 reload_reg_rtx[r] = reg_last_reload_reg[regno];
4865 reload_inherited[r] = 1;
4866 reload_inheritance_insn[r]
4867 = reg_reloaded_insn[i];
4868 reload_spill_index[r] = i;
4869 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
4877 /* Here's another way to see if the value is already lying around. */
4879 && reload_in[r] != 0
4880 && ! reload_inherited[r]
4881 && reload_out[r] == 0
4882 && (CONSTANT_P (reload_in[r])
4883 || GET_CODE (reload_in[r]) == PLUS
4884 || GET_CODE (reload_in[r]) == REG
4885 || GET_CODE (reload_in[r]) == MEM)
4886 && (reload_nregs[r] == max_group_size
4887 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4890 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4891 -1, NULL_PTR, 0, reload_mode[r]);
4896 if (GET_CODE (equiv) == REG)
4897 regno = REGNO (equiv);
4898 else if (GET_CODE (equiv) == SUBREG)
4900 regno = REGNO (SUBREG_REG (equiv));
4901 if (regno < FIRST_PSEUDO_REGISTER)
4902 regno += SUBREG_WORD (equiv);
4908 /* If we found a spill reg, reject it unless it is free
4909 and of the desired class. */
4911 && ((spill_reg_order[regno] >= 0
4912 && ! reload_reg_free_before_p (regno, reload_opnum[r],
4913 reload_when_needed[r]))
4914 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4918 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4921 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4924 /* We found a register that contains the value we need.
4925 If this register is the same as an `earlyclobber' operand
4926 of the current insn, just mark it as a place to reload from
4927 since we can't use it as the reload register itself. */
4930 for (i = 0; i < n_earlyclobbers; i++)
4931 if (reg_overlap_mentioned_for_reload_p (equiv,
4932 reload_earlyclobbers[i]))
4934 reload_override_in[r] = equiv;
4939 /* JRV: If the equiv register we have found is explicitly
4940 clobbered in the current insn, mark but don't use, as above. */
4942 if (equiv != 0 && regno_clobbered_p (regno, insn))
4944 reload_override_in[r] = equiv;
4948 /* If we found an equivalent reg, say no code need be generated
4949 to load it, and use it as our reload reg. */
4950 if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4952 reload_reg_rtx[r] = equiv;
4953 reload_inherited[r] = 1;
4954 /* If it is a spill reg,
4955 mark the spill reg as in use for this insn. */
4956 i = spill_reg_order[regno];
4959 mark_reload_reg_in_use (regno, reload_opnum[r],
4960 reload_when_needed[r],
4962 SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno);
4967 /* If we found a register to use already, or if this is an optional
4968 reload, we are done. */
4969 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4972 #if 0 /* No longer needed for correct operation. Might or might not
4973 give better code on the average. Want to experiment? */
4975 /* See if there is a later reload that has a class different from our
4976 class that intersects our class or that requires less register
4977 than our reload. If so, we must allocate a register to this
4978 reload now, since that reload might inherit a previous reload
4979 and take the only available register in our class. Don't do this
4980 for optional reloads since they will force all previous reloads
4981 to be allocated. Also don't do this for reloads that have been
4984 for (i = j + 1; i < n_reloads; i++)
4986 int s = reload_order[i];
4988 if ((reload_in[s] == 0 && reload_out[s] == 0
4989 && ! reload_secondary_p[s])
4990 || reload_optional[s])
4993 if ((reload_reg_class[s] != reload_reg_class[r]
4994 && reg_classes_intersect_p (reload_reg_class[r],
4995 reload_reg_class[s]))
4996 || reload_nregs[s] < reload_nregs[r])
5003 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5007 /* Now allocate reload registers for anything non-optional that
5008 didn't get one yet. */
5009 for (j = 0; j < n_reloads; j++)
5011 register int r = reload_order[j];
5013 /* Ignore reloads that got marked inoperative. */
5014 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5017 /* Skip reloads that already have a register allocated or are
5019 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5022 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5026 /* If that loop got all the way, we have won. */
5031 /* Loop around and try without any inheritance. */
5032 /* First undo everything done by the failed attempt
5033 to allocate with inheritance. */
5034 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
5035 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
5036 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
5037 sizeof reload_inheritance_insn);
5038 bcopy (save_reload_override_in, reload_override_in,
5039 sizeof reload_override_in);
5040 bcopy (save_reload_spill_index, reload_spill_index,
5041 sizeof reload_spill_index);
5042 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5043 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5044 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5045 save_reload_reg_used_in_op_addr);
5046 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5047 save_reload_reg_used_in_insn);
5048 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5049 save_reload_reg_used_in_other_addr);
5051 for (i = 0; i < reload_n_operands; i++)
5053 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5054 save_reload_reg_used_in_input[i]);
5055 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5056 save_reload_reg_used_in_output[i]);
5057 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5058 save_reload_reg_used_in_input_addr[i]);
5059 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5060 save_reload_reg_used_in_output_addr[i]);
5064 /* If we thought we could inherit a reload, because it seemed that
5065 nothing else wanted the same reload register earlier in the insn,
5066 verify that assumption, now that all reloads have been assigned. */
5068 for (j = 0; j < n_reloads; j++)
5070 register int r = reload_order[j];
5072 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5073 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5075 reload_when_needed[r]))
5076 reload_inherited[r] = 0;
5078 /* If we found a better place to reload from,
5079 validate it in the same fashion, if it is a reload reg. */
5080 if (reload_override_in[r]
5081 && (GET_CODE (reload_override_in[r]) == REG
5082 || GET_CODE (reload_override_in[r]) == SUBREG))
5084 int regno = true_regnum (reload_override_in[r]);
5085 if (spill_reg_order[regno] >= 0
5086 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5087 reload_when_needed[r]))
5088 reload_override_in[r] = 0;
5092 /* Now that reload_override_in is known valid,
5093 actually override reload_in. */
5094 for (j = 0; j < n_reloads; j++)
5095 if (reload_override_in[j])
5096 reload_in[j] = reload_override_in[j];
5098 /* If this reload won't be done because it has been cancelled or is
5099 optional and not inherited, clear reload_reg_rtx so other
5100 routines (such as subst_reloads) don't get confused. */
5101 for (j = 0; j < n_reloads; j++)
5102 if (reload_reg_rtx[j] != 0
5103 && ((reload_optional[j] && ! reload_inherited[j])
5104 || (reload_in[j] == 0 && reload_out[j] == 0
5105 && ! reload_secondary_p[j])))
5107 int regno = true_regnum (reload_reg_rtx[j]);
5109 if (spill_reg_order[regno] >= 0)
5110 clear_reload_reg_in_use (regno, reload_opnum[j],
5111 reload_when_needed[j], reload_mode[j]);
5112 reload_reg_rtx[j] = 0;
5115 /* Record which pseudos and which spill regs have output reloads. */
5116 for (j = 0; j < n_reloads; j++)
5118 register int r = reload_order[j];
5120 i = reload_spill_index[r];
5122 /* I is nonneg if this reload used one of the spill regs.
5123 If reload_reg_rtx[r] is 0, this is an optional reload
5124 that we opted to ignore. */
5125 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5126 && reload_reg_rtx[r] != 0)
5128 register int nregno = REGNO (reload_out[r]);
5131 if (nregno < FIRST_PSEUDO_REGISTER)
5132 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5135 reg_has_output_reload[nregno + nr] = 1;
5139 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5141 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5144 if (reload_when_needed[r] != RELOAD_OTHER
5145 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5146 && reload_when_needed[r] != RELOAD_FOR_INSN)
5152 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5153 reloads of the same item for fear that we might not have enough reload
5154 registers. However, normally they will get the same reload register
5155 and hence actually need not be loaded twice.
5157 Here we check for the most common case of this phenomenon: when we have
5158 a number of reloads for the same object, each of which were allocated
5159 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5160 reload, and is not modified in the insn itself. If we find such,
5161 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5162 This will not increase the number of spill registers needed and will
5163 prevent redundant code. */
5165 #ifdef SMALL_REGISTER_CLASSES
5168 merge_assigned_reloads (insn)
5173 /* Scan all the reloads looking for ones that only load values and
5174 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5175 assigned and not modified by INSN. */
5177 for (i = 0; i < n_reloads; i++)
5179 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5180 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5181 || reg_set_p (reload_reg_rtx[i], insn))
5184 /* Look at all other reloads. Ensure that the only use of this
5185 reload_reg_rtx is in a reload that just loads the same value
5186 as we do. Note that any secondary reloads must be of the identical
5187 class since the values, modes, and result registers are the
5188 same, so we need not do anything with any secondary reloads. */
5190 for (j = 0; j < n_reloads; j++)
5192 if (i == j || reload_reg_rtx[j] == 0
5193 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5197 /* If the reload regs aren't exactly the same (e.g, different modes)
5198 or if the values are different, we can't merge anything with this
5201 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5202 || reload_out[j] != 0 || reload_in[j] == 0
5203 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5207 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5208 we, in fact, found any matching reloads. */
5212 for (j = 0; j < n_reloads; j++)
5213 if (i != j && reload_reg_rtx[j] != 0
5214 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5216 reload_when_needed[i] = RELOAD_OTHER;
5218 transfer_replacements (i, j);
5221 /* If this is now RELOAD_OTHER, look for any reloads that load
5222 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5223 if they were for inputs, RELOAD_OTHER for outputs. Note that
5224 this test is equivalent to looking for reloads for this operand
5227 if (reload_when_needed[i] == RELOAD_OTHER)
5228 for (j = 0; j < n_reloads; j++)
5229 if (reload_in[j] != 0
5230 && reload_when_needed[i] != RELOAD_OTHER
5231 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5233 reload_when_needed[j]
5234 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5235 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5239 #endif /* SMALL_RELOAD_CLASSES */
5241 /* Output insns to reload values in and out of the chosen reload regs. */
5244 emit_reload_insns (insn)
5248 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5249 rtx other_input_address_reload_insns = 0;
5250 rtx other_input_reload_insns = 0;
5251 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5252 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5253 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5254 rtx operand_reload_insns = 0;
5255 rtx following_insn = NEXT_INSN (insn);
5256 rtx before_insn = insn;
5258 /* Values to be put in spill_reg_store are put here first. */
5259 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5261 for (j = 0; j < reload_n_operands; j++)
5262 input_reload_insns[j] = input_address_reload_insns[j]
5263 = output_reload_insns[j] = output_address_reload_insns[j] = 0;
5265 /* If this is a CALL_INSN preceded by USE insns, any reload insns
5266 must go in front of the first USE insn, not in front of INSN. */
5268 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
5269 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
5270 while (GET_CODE (PREV_INSN (before_insn)) == INSN
5271 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
5272 before_insn = PREV_INSN (before_insn);
5274 /* If INSN is followed by any CLOBBER insns made by find_reloads,
5275 put our reloads after them since they may otherwise be
5278 while (GET_CODE (following_insn) == INSN
5279 && GET_MODE (following_insn) == DImode
5280 && GET_CODE (PATTERN (following_insn)) == CLOBBER
5281 && NEXT_INSN (following_insn) != 0)
5282 following_insn = NEXT_INSN (following_insn);
5284 /* Now output the instructions to copy the data into and out of the
5285 reload registers. Do these in the order that the reloads were reported,
5286 since reloads of base and index registers precede reloads of operands
5287 and the operands may need the base and index registers reloaded. */
5289 for (j = 0; j < n_reloads; j++)
5292 rtx oldequiv_reg = 0;
5296 if (old != 0 && ! reload_inherited[j]
5297 && ! rtx_equal_p (reload_reg_rtx[j], old)
5298 && reload_reg_rtx[j] != 0)
5300 register rtx reloadreg = reload_reg_rtx[j];
5302 enum machine_mode mode;
5305 /* Determine the mode to reload in.
5306 This is very tricky because we have three to choose from.
5307 There is the mode the insn operand wants (reload_inmode[J]).
5308 There is the mode of the reload register RELOADREG.
5309 There is the intrinsic mode of the operand, which we could find
5310 by stripping some SUBREGs.
5311 It turns out that RELOADREG's mode is irrelevant:
5312 we can change that arbitrarily.
5314 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5315 then the reload reg may not support QImode moves, so use SImode.
5316 If foo is in memory due to spilling a pseudo reg, this is safe,
5317 because the QImode value is in the least significant part of a
5318 slot big enough for a SImode. If foo is some other sort of
5319 memory reference, then it is impossible to reload this case,
5320 so previous passes had better make sure this never happens.
5322 Then consider a one-word union which has SImode and one of its
5323 members is a float, being fetched as (SUBREG:SF union:SI).
5324 We must fetch that as SFmode because we could be loading into
5325 a float-only register. In this case OLD's mode is correct.
5327 Consider an immediate integer: it has VOIDmode. Here we need
5328 to get a mode from something else.
5330 In some cases, there is a fourth mode, the operand's
5331 containing mode. If the insn specifies a containing mode for
5332 this operand, it overrides all others.
5334 I am not sure whether the algorithm here is always right,
5335 but it does the right things in those cases. */
5337 mode = GET_MODE (old);
5338 if (mode == VOIDmode)
5339 mode = reload_inmode[j];
5341 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5342 /* If we need a secondary register for this operation, see if
5343 the value is already in a register in that class. Don't
5344 do this if the secondary register will be used as a scratch
5347 if (reload_secondary_reload[j] >= 0
5348 && reload_secondary_icode[j] == CODE_FOR_nothing
5351 = find_equiv_reg (old, insn,
5352 reload_reg_class[reload_secondary_reload[j]],
5353 -1, NULL_PTR, 0, mode);
5356 /* If reloading from memory, see if there is a register
5357 that already holds the same value. If so, reload from there.
5358 We can pass 0 as the reload_reg_p argument because
5359 any other reload has either already been emitted,
5360 in which case find_equiv_reg will see the reload-insn,
5361 or has yet to be emitted, in which case it doesn't matter
5362 because we will use this equiv reg right away. */
5364 if (oldequiv == 0 && optimize
5365 && (GET_CODE (old) == MEM
5366 || (GET_CODE (old) == REG
5367 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5368 && reg_renumber[REGNO (old)] < 0)))
5369 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5370 -1, NULL_PTR, 0, mode);
5374 int regno = true_regnum (oldequiv);
5376 /* If OLDEQUIV is a spill register, don't use it for this
5377 if any other reload needs it at an earlier stage of this insn
5378 or at this stage. */
5379 if (spill_reg_order[regno] >= 0
5380 && (! reload_reg_free_p (regno, reload_opnum[j],
5381 reload_when_needed[j])
5382 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5383 reload_when_needed[j])))
5386 /* If OLDEQUIV is not a spill register,
5387 don't use it if any other reload wants it. */
5388 if (spill_reg_order[regno] < 0)
5391 for (k = 0; k < n_reloads; k++)
5392 if (reload_reg_rtx[k] != 0 && k != j
5393 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5401 /* If it is no cheaper to copy from OLDEQUIV into the
5402 reload register than it would be to move from memory,
5403 don't use it. Likewise, if we need a secondary register
5407 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5408 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5409 reload_reg_class[j])
5410 >= MEMORY_MOVE_COST (mode)))
5411 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5412 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5416 #ifdef SECONDARY_MEMORY_NEEDED
5417 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5418 REGNO_REG_CLASS (regno),
5427 else if (GET_CODE (oldequiv) == REG)
5428 oldequiv_reg = oldequiv;
5429 else if (GET_CODE (oldequiv) == SUBREG)
5430 oldequiv_reg = SUBREG_REG (oldequiv);
5432 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5433 then load RELOADREG from OLDEQUIV. */
5435 if (GET_MODE (reloadreg) != mode)
5436 reloadreg = gen_lowpart_common (mode, reloadreg);
5437 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5438 oldequiv = SUBREG_REG (oldequiv);
5439 if (GET_MODE (oldequiv) != VOIDmode
5440 && mode != GET_MODE (oldequiv))
5441 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5443 /* Switch to the right place to emit the reload insns. */
5444 switch (reload_when_needed[j])
5447 where = &other_input_reload_insns;
5449 case RELOAD_FOR_INPUT:
5450 where = &input_reload_insns[reload_opnum[j]];
5452 case RELOAD_FOR_INPUT_ADDRESS:
5453 where = &input_address_reload_insns[reload_opnum[j]];
5455 case RELOAD_FOR_OUTPUT_ADDRESS:
5456 where = &output_address_reload_insns[reload_opnum[j]];
5458 case RELOAD_FOR_OPERAND_ADDRESS:
5459 where = &operand_reload_insns;
5461 case RELOAD_FOR_OTHER_ADDRESS:
5462 where = &other_input_address_reload_insns;
5468 push_to_sequence (*where);
5471 /* Auto-increment addresses must be reloaded in a special way. */
5472 if (GET_CODE (oldequiv) == POST_INC
5473 || GET_CODE (oldequiv) == POST_DEC
5474 || GET_CODE (oldequiv) == PRE_INC
5475 || GET_CODE (oldequiv) == PRE_DEC)
5477 /* We are not going to bother supporting the case where a
5478 incremented register can't be copied directly from
5479 OLDEQUIV since this seems highly unlikely. */
5480 if (reload_secondary_reload[j] >= 0)
5482 /* Prevent normal processing of this reload. */
5484 /* Output a special code sequence for this case. */
5485 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5488 /* If we are reloading a pseudo-register that was set by the previous
5489 insn, see if we can get rid of that pseudo-register entirely
5490 by redirecting the previous insn into our reload register. */
5492 else if (optimize && GET_CODE (old) == REG
5493 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5494 && dead_or_set_p (insn, old)
5495 /* This is unsafe if some other reload
5496 uses the same reg first. */
5497 && reload_reg_free_before_p (REGNO (reloadreg),
5499 reload_when_needed[j]))
5501 rtx temp = PREV_INSN (insn);
5502 while (temp && GET_CODE (temp) == NOTE)
5503 temp = PREV_INSN (temp);
5505 && GET_CODE (temp) == INSN
5506 && GET_CODE (PATTERN (temp)) == SET
5507 && SET_DEST (PATTERN (temp)) == old
5508 /* Make sure we can access insn_operand_constraint. */
5509 && asm_noperands (PATTERN (temp)) < 0
5510 /* This is unsafe if prev insn rejects our reload reg. */
5511 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5513 /* This is unsafe if operand occurs more than once in current
5514 insn. Perhaps some occurrences aren't reloaded. */
5515 && count_occurrences (PATTERN (insn), old) == 1
5516 /* Don't risk splitting a matching pair of operands. */
5517 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5519 /* Store into the reload register instead of the pseudo. */
5520 SET_DEST (PATTERN (temp)) = reloadreg;
5521 /* If these are the only uses of the pseudo reg,
5522 pretend for GDB it lives in the reload reg we used. */
5523 if (reg_n_deaths[REGNO (old)] == 1
5524 && reg_n_sets[REGNO (old)] == 1)
5526 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5527 alter_reg (REGNO (old), -1);
5533 /* We can't do that, so output an insn to load RELOADREG. */
5537 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5538 rtx second_reload_reg = 0;
5539 enum insn_code icode;
5541 /* If we have a secondary reload, pick up the secondary register
5542 and icode, if any. If OLDEQUIV and OLD are different or
5543 if this is an in-out reload, recompute whether or not we
5544 still need a secondary register and what the icode should
5545 be. If we still need a secondary register and the class or
5546 icode is different, go back to reloading from OLD if using
5547 OLDEQUIV means that we got the wrong type of register. We
5548 cannot have different class or icode due to an in-out reload
5549 because we don't make such reloads when both the input and
5550 output need secondary reload registers. */
5552 if (reload_secondary_reload[j] >= 0)
5554 int secondary_reload = reload_secondary_reload[j];
5555 rtx real_oldequiv = oldequiv;
5558 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5559 and similarly for OLD.
5560 See comments in find_secondary_reload in reload.c. */
5561 if (GET_CODE (oldequiv) == REG
5562 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5563 && reg_equiv_mem[REGNO (oldequiv)] != 0)
5564 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5566 if (GET_CODE (old) == REG
5567 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5568 && reg_equiv_mem[REGNO (old)] != 0)
5569 real_old = reg_equiv_mem[REGNO (old)];
5571 second_reload_reg = reload_reg_rtx[secondary_reload];
5572 icode = reload_secondary_icode[j];
5574 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5575 || (reload_in[j] != 0 && reload_out[j] != 0))
5577 enum reg_class new_class
5578 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5579 mode, real_oldequiv);
5581 if (new_class == NO_REGS)
5582 second_reload_reg = 0;
5585 enum insn_code new_icode;
5586 enum machine_mode new_mode;
5588 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5589 REGNO (second_reload_reg)))
5590 oldequiv = old, real_oldequiv = real_old;
5593 new_icode = reload_in_optab[(int) mode];
5594 if (new_icode != CODE_FOR_nothing
5595 && ((insn_operand_predicate[(int) new_icode][0]
5596 && ! ((*insn_operand_predicate[(int) new_icode][0])
5598 || (insn_operand_predicate[(int) new_icode][1]
5599 && ! ((*insn_operand_predicate[(int) new_icode][1])
5600 (real_oldequiv, mode)))))
5601 new_icode = CODE_FOR_nothing;
5603 if (new_icode == CODE_FOR_nothing)
5606 new_mode = insn_operand_mode[(int) new_icode][2];
5608 if (GET_MODE (second_reload_reg) != new_mode)
5610 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
5612 oldequiv = old, real_oldequiv = real_old;
5615 = gen_rtx (REG, new_mode,
5616 REGNO (second_reload_reg));
5622 /* If we still need a secondary reload register, check
5623 to see if it is being used as a scratch or intermediate
5624 register and generate code appropriately. If we need
5625 a scratch register, use REAL_OLDEQUIV since the form of
5626 the insn may depend on the actual address if it is
5629 if (second_reload_reg)
5631 if (icode != CODE_FOR_nothing)
5633 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
5634 second_reload_reg));
5639 /* See if we need a scratch register to load the
5640 intermediate register (a tertiary reload). */
5641 enum insn_code tertiary_icode
5642 = reload_secondary_icode[secondary_reload];
5644 if (tertiary_icode != CODE_FOR_nothing)
5646 rtx third_reload_reg
5647 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5649 emit_insn ((GEN_FCN (tertiary_icode)
5650 (second_reload_reg, real_oldequiv,
5651 third_reload_reg)));
5654 gen_input_reload (second_reload_reg, oldequiv,
5656 reload_when_needed[j]);
5658 oldequiv = second_reload_reg;
5665 gen_input_reload (reloadreg, oldequiv, reload_opnum[j],
5666 reload_when_needed[j]);
5668 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5669 /* We may have to make a REG_DEAD note for the secondary reload
5670 register in the insns we just made. Find the last insn that
5671 mentioned the register. */
5672 if (! special && second_reload_reg
5673 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
5677 for (prev = get_last_insn (); prev;
5678 prev = PREV_INSN (prev))
5679 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5680 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5683 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5692 /* End this sequence. */
5693 *where = get_insns ();
5697 /* Add a note saying the input reload reg
5698 dies in this insn, if anyone cares. */
5699 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5701 && reload_reg_rtx[j] != old
5702 && reload_reg_rtx[j] != 0
5703 && reload_out[j] == 0
5704 && ! reload_inherited[j]
5705 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5707 register rtx reloadreg = reload_reg_rtx[j];
5710 /* We can't abort here because we need to support this for sched.c.
5711 It's not terrible to miss a REG_DEAD note, but we should try
5712 to figure out how to do this correctly. */
5713 /* The code below is incorrect for address-only reloads. */
5714 if (reload_when_needed[j] != RELOAD_OTHER
5715 && reload_when_needed[j] != RELOAD_FOR_INPUT)
5719 /* Add a death note to this insn, for an input reload. */
5721 if ((reload_when_needed[j] == RELOAD_OTHER
5722 || reload_when_needed[j] == RELOAD_FOR_INPUT)
5723 && ! dead_or_set_p (insn, reloadreg))
5725 = gen_rtx (EXPR_LIST, REG_DEAD,
5726 reloadreg, REG_NOTES (insn));
5729 /* When we inherit a reload, the last marked death of the reload reg
5730 may no longer really be a death. */
5731 if (reload_reg_rtx[j] != 0
5732 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5733 && reload_inherited[j])
5735 /* Handle inheriting an output reload.
5736 Remove the death note from the output reload insn. */
5737 if (reload_spill_index[j] >= 0
5738 && GET_CODE (reload_in[j]) == REG
5739 && spill_reg_store[reload_spill_index[j]] != 0
5740 && find_regno_note (spill_reg_store[reload_spill_index[j]],
5741 REG_DEAD, REGNO (reload_reg_rtx[j])))
5742 remove_death (REGNO (reload_reg_rtx[j]),
5743 spill_reg_store[reload_spill_index[j]]);
5744 /* Likewise for input reloads that were inherited. */
5745 else if (reload_spill_index[j] >= 0
5746 && GET_CODE (reload_in[j]) == REG
5747 && spill_reg_store[reload_spill_index[j]] == 0
5748 && reload_inheritance_insn[j] != 0
5749 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5750 REGNO (reload_reg_rtx[j])))
5751 remove_death (REGNO (reload_reg_rtx[j]),
5752 reload_inheritance_insn[j]);
5757 /* We got this register from find_equiv_reg.
5758 Search back for its last death note and get rid of it.
5759 But don't search back too far.
5760 Don't go past a place where this reg is set,
5761 since a death note before that remains valid. */
5762 for (prev = PREV_INSN (insn);
5763 prev && GET_CODE (prev) != CODE_LABEL;
5764 prev = PREV_INSN (prev))
5765 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5766 && dead_or_set_p (prev, reload_reg_rtx[j]))
5768 if (find_regno_note (prev, REG_DEAD,
5769 REGNO (reload_reg_rtx[j])))
5770 remove_death (REGNO (reload_reg_rtx[j]), prev);
5776 /* We might have used find_equiv_reg above to choose an alternate
5777 place from which to reload. If so, and it died, we need to remove
5778 that death and move it to one of the insns we just made. */
5780 if (oldequiv_reg != 0
5781 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5785 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5786 prev = PREV_INSN (prev))
5787 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5788 && dead_or_set_p (prev, oldequiv_reg))
5790 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5792 for (prev1 = this_reload_insn;
5793 prev1; prev1 = PREV_INSN (prev1))
5794 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5795 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5798 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5803 remove_death (REGNO (oldequiv_reg), prev);
5810 /* If we are reloading a register that was recently stored in with an
5811 output-reload, see if we can prove there was
5812 actually no need to store the old value in it. */
5814 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5815 && reload_in[j] != 0
5816 && GET_CODE (reload_in[j]) == REG
5818 /* There doesn't seem to be any reason to restrict this to pseudos
5819 and doing so loses in the case where we are copying from a
5820 register of the wrong class. */
5821 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5823 && spill_reg_store[reload_spill_index[j]] != 0
5824 /* This is unsafe if some other reload uses the same reg first. */
5825 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
5826 reload_opnum[j], reload_when_needed[j])
5827 && dead_or_set_p (insn, reload_in[j])
5828 /* This is unsafe if operand occurs more than once in current
5829 insn. Perhaps some occurrences weren't reloaded. */
5830 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5831 delete_output_reload (insn, j,
5832 spill_reg_store[reload_spill_index[j]]);
5834 /* Input-reloading is done. Now do output-reloading,
5835 storing the value from the reload-register after the main insn
5836 if reload_out[j] is nonzero.
5838 ??? At some point we need to support handling output reloads of
5839 JUMP_INSNs or insns that set cc0. */
5840 old = reload_out[j];
5842 && reload_reg_rtx[j] != old
5843 && reload_reg_rtx[j] != 0)
5845 register rtx reloadreg = reload_reg_rtx[j];
5846 register rtx second_reloadreg = 0;
5848 enum machine_mode mode;
5851 /* An output operand that dies right away does need a reload,
5852 but need not be copied from it. Show the new location in the
5854 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5855 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5857 XEXP (note, 0) = reload_reg_rtx[j];
5860 else if (GET_CODE (old) == SCRATCH)
5861 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5862 but we don't want to make an output reload. */
5866 /* Strip off of OLD any size-increasing SUBREGs such as
5867 (SUBREG:SI foo:QI 0). */
5869 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5870 && (GET_MODE_SIZE (GET_MODE (old))
5871 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5872 old = SUBREG_REG (old);
5875 /* If is a JUMP_INSN, we can't support output reloads yet. */
5876 if (GET_CODE (insn) == JUMP_INSN)
5879 push_to_sequence (output_reload_insns[reload_opnum[j]]);
5881 /* Determine the mode to reload in.
5882 See comments above (for input reloading). */
5884 mode = GET_MODE (old);
5885 if (mode == VOIDmode)
5887 /* VOIDmode should never happen for an output. */
5888 if (asm_noperands (PATTERN (insn)) < 0)
5889 /* It's the compiler's fault. */
5891 error_for_asm (insn, "output operand is constant in `asm'");
5892 /* Prevent crash--use something we know is valid. */
5894 old = gen_rtx (REG, mode, REGNO (reloadreg));
5897 if (GET_MODE (reloadreg) != mode)
5898 reloadreg = gen_lowpart_common (mode, reloadreg);
5900 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5902 /* If we need two reload regs, set RELOADREG to the intermediate
5903 one, since it will be stored into OUT. We might need a secondary
5904 register only for an input reload, so check again here. */
5906 if (reload_secondary_reload[j] >= 0)
5910 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5911 && reg_equiv_mem[REGNO (old)] != 0)
5912 real_old = reg_equiv_mem[REGNO (old)];
5914 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
5918 second_reloadreg = reloadreg;
5919 reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
5921 /* See if RELOADREG is to be used as a scratch register
5922 or as an intermediate register. */
5923 if (reload_secondary_icode[j] != CODE_FOR_nothing)
5925 emit_insn ((GEN_FCN (reload_secondary_icode[j])
5926 (real_old, second_reloadreg, reloadreg)));
5931 /* See if we need both a scratch and intermediate reload
5933 int secondary_reload = reload_secondary_reload[j];
5934 enum insn_code tertiary_icode
5935 = reload_secondary_icode[secondary_reload];
5938 if (GET_MODE (reloadreg) != mode)
5939 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5941 if (tertiary_icode != CODE_FOR_nothing)
5944 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5945 pat = (GEN_FCN (tertiary_icode)
5946 (reloadreg, second_reloadreg, third_reloadreg));
5948 #ifdef SECONDARY_MEMORY_NEEDED
5949 /* If we need a memory location to do the move, do it that way. */
5950 else if (GET_CODE (reloadreg) == REG
5951 && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER
5952 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)),
5953 REGNO_REG_CLASS (REGNO (second_reloadreg)),
5954 GET_MODE (second_reloadreg)))
5956 /* Get the memory to use and rewrite both registers
5959 = get_secondary_mem (reloadreg,
5960 GET_MODE (second_reloadreg),
5962 reload_when_needed[j]);
5965 if (GET_MODE (loc) != GET_MODE (second_reloadreg))
5966 second_reloadreg = gen_rtx (REG, GET_MODE (loc),
5967 REGNO (second_reloadreg));
5969 if (GET_MODE (loc) != GET_MODE (reloadreg))
5970 tmp_reloadreg = gen_rtx (REG, GET_MODE (loc),
5973 tmp_reloadreg = reloadreg;
5975 emit_move_insn (loc, second_reloadreg);
5976 pat = gen_move_insn (tmp_reloadreg, loc);
5980 pat = gen_move_insn (reloadreg, second_reloadreg);
5988 /* Output the last reload insn. */
5991 #ifdef SECONDARY_MEMORY_NEEDED
5992 /* If we need a memory location to do the move, do it that way. */
5993 if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
5994 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
5995 REGNO_REG_CLASS (REGNO (reloadreg)),
5996 GET_MODE (reloadreg)))
5998 /* Get the memory to use and rewrite both registers to
6000 rtx loc = get_secondary_mem (old, GET_MODE (reloadreg),
6002 reload_when_needed[j]);
6004 if (GET_MODE (loc) != GET_MODE (reloadreg))
6005 reloadreg = gen_rtx (REG, GET_MODE (loc),
6008 if (GET_MODE (loc) != GET_MODE (old))
6009 old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
6011 emit_insn (gen_move_insn (loc, reloadreg));
6012 emit_insn (gen_move_insn (old, loc));
6016 emit_insn (gen_move_insn (old, reloadreg));
6019 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6020 /* If final will look at death notes for this reg,
6021 put one on the last output-reload insn to use it. Similarly
6022 for any secondary register. */
6023 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6024 for (p = get_last_insn (); p; p = PREV_INSN (p))
6025 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6026 && reg_overlap_mentioned_for_reload_p (reloadreg,
6028 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6029 reloadreg, REG_NOTES (p));
6031 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6033 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6034 for (p = get_last_insn (); p; p = PREV_INSN (p))
6035 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6036 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6038 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6039 second_reloadreg, REG_NOTES (p));
6042 /* Look at all insns we emitted, just to be safe. */
6043 for (p = get_insns (); p; p = NEXT_INSN (p))
6044 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6046 /* If this output reload doesn't come from a spill reg,
6047 clear any memory of reloaded copies of the pseudo reg.
6048 If this output reload comes from a spill reg,
6049 reg_has_output_reload will make this do nothing. */
6050 note_stores (PATTERN (p), forget_old_reloads_1);
6052 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
6056 output_reload_insns[reload_opnum[j]] = get_insns ();
6061 if (reload_spill_index[j] >= 0)
6062 new_spill_reg_store[reload_spill_index[j]] = store_insn;
6065 /* Now write all the insns we made for reloads in the order expected by
6066 the allocation functions. Prior to the insn being reloaded, we write
6067 the following reloads:
6069 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6071 RELOAD_OTHER reloads.
6073 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6074 the RELOAD_FOR_INPUT reload for the operand.
6076 RELOAD_FOR_OPERAND_ADDRESS reloads.
6078 After the insn being reloaded, we write the following:
6080 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6081 the RELOAD_FOR_OUTPUT reload for that operand. */
6083 emit_insns_before (other_input_address_reload_insns, before_insn);
6084 emit_insns_before (other_input_reload_insns, before_insn);
6086 for (j = 0; j < reload_n_operands; j++)
6088 emit_insns_before (input_address_reload_insns[j], before_insn);
6089 emit_insns_before (input_reload_insns[j], before_insn);
6092 emit_insns_before (operand_reload_insns, before_insn);
6094 for (j = 0; j < reload_n_operands; j++)
6096 emit_insns_before (output_address_reload_insns[j], following_insn);
6097 emit_insns_before (output_reload_insns[j], following_insn);
6100 /* Move death notes from INSN
6101 to output-operand-address and output reload insns. */
6102 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6105 /* Loop over those insns, last ones first. */
6106 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6107 insn1 = PREV_INSN (insn1))
6108 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6110 rtx source = SET_SRC (PATTERN (insn1));
6111 rtx dest = SET_DEST (PATTERN (insn1));
6113 /* The note we will examine next. */
6114 rtx reg_notes = REG_NOTES (insn);
6115 /* The place that pointed to this note. */
6116 rtx *prev_reg_note = ®_NOTES (insn);
6118 /* If the note is for something used in the source of this
6119 reload insn, or in the output address, move the note. */
6122 rtx next_reg_notes = XEXP (reg_notes, 1);
6123 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6124 && GET_CODE (XEXP (reg_notes, 0)) == REG
6125 && ((GET_CODE (dest) != REG
6126 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6128 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6131 *prev_reg_note = next_reg_notes;
6132 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6133 REG_NOTES (insn1) = reg_notes;
6136 prev_reg_note = &XEXP (reg_notes, 1);
6138 reg_notes = next_reg_notes;
6144 /* For all the spill regs newly reloaded in this instruction,
6145 record what they were reloaded from, so subsequent instructions
6146 can inherit the reloads.
6148 Update spill_reg_store for the reloads of this insn.
6149 Copy the elements that were updated in the loop above. */
6151 for (j = 0; j < n_reloads; j++)
6153 register int r = reload_order[j];
6154 register int i = reload_spill_index[r];
6156 /* I is nonneg if this reload used one of the spill regs.
6157 If reload_reg_rtx[r] is 0, this is an optional reload
6158 that we opted to ignore.
6160 Also ignore reloads that don't reach the end of the insn,
6161 since we will eventually see the one that does. */
6163 if (i >= 0 && reload_reg_rtx[r] != 0
6164 && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r],
6165 reload_when_needed[r]))
6167 /* First, clear out memory of what used to be in this spill reg.
6168 If consecutive registers are used, clear them all. */
6170 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6173 for (k = 0; k < nr; k++)
6175 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6176 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6179 /* Maybe the spill reg contains a copy of reload_out. */
6180 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6182 register int nregno = REGNO (reload_out[r]);
6183 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6184 : HARD_REGNO_NREGS (nregno,
6185 GET_MODE (reload_reg_rtx[r])));
6187 spill_reg_store[i] = new_spill_reg_store[i];
6188 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6190 /* If NREGNO is a hard register, it may occupy more than
6191 one register. If it does, say what is in the
6192 rest of the registers assuming that both registers
6193 agree on how many words the object takes. If not,
6194 invalidate the subsequent registers. */
6196 if (nregno < FIRST_PSEUDO_REGISTER)
6197 for (k = 1; k < nnr; k++)
6198 reg_last_reload_reg[nregno + k]
6199 = (nr == nnr ? gen_rtx (REG, word_mode,
6200 REGNO (reload_reg_rtx[r]) + k)
6203 /* Now do the inverse operation. */
6204 for (k = 0; k < nr; k++)
6206 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6207 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6209 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6213 /* Maybe the spill reg contains a copy of reload_in. Only do
6214 something if there will not be an output reload for
6215 the register being reloaded. */
6216 else if (reload_out[r] == 0
6217 && reload_in[r] != 0
6218 && ((GET_CODE (reload_in[r]) == REG
6219 && ! reg_has_output_reload[REGNO (reload_in[r])]
6220 || (GET_CODE (reload_in_reg[r]) == REG
6221 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))))
6223 register int nregno;
6226 if (GET_CODE (reload_in[r]) == REG)
6227 nregno = REGNO (reload_in[r]);
6229 nregno = REGNO (reload_in_reg[r]);
6231 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6232 : HARD_REGNO_NREGS (nregno,
6233 GET_MODE (reload_reg_rtx[r])));
6235 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6237 if (nregno < FIRST_PSEUDO_REGISTER)
6238 for (k = 1; k < nnr; k++)
6239 reg_last_reload_reg[nregno + k]
6240 = (nr == nnr ? gen_rtx (REG, word_mode,
6241 REGNO (reload_reg_rtx[r]) + k)
6244 /* Unless we inherited this reload, show we haven't
6245 recently done a store. */
6246 if (! reload_inherited[r])
6247 spill_reg_store[i] = 0;
6249 for (k = 0; k < nr; k++)
6251 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6252 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6254 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6260 /* The following if-statement was #if 0'd in 1.34 (or before...).
6261 It's reenabled in 1.35 because supposedly nothing else
6262 deals with this problem. */
6264 /* If a register gets output-reloaded from a non-spill register,
6265 that invalidates any previous reloaded copy of it.
6266 But forget_old_reloads_1 won't get to see it, because
6267 it thinks only about the original insn. So invalidate it here. */
6268 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6270 register int nregno = REGNO (reload_out[r]);
6271 reg_last_reload_reg[nregno] = 0;
6276 /* Emit code to perform an input reload of IN to RELOADREG. IN is from
6277 operand OPNUM with reload type TYPE.
6279 Returns first insn emitted. */
6282 gen_input_reload (reloadreg, in, opnum, type)
6286 enum reload_type type;
6288 rtx last = get_last_insn ();
6290 /* How to do this reload can get quite tricky. Normally, we are being
6291 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6292 register that didn't get a hard register. In that case we can just
6293 call emit_move_insn.
6295 We can also be asked to reload a PLUS that adds either two registers, or
6296 a register and a constant or MEM, or a MEM and a constant. This can
6297 occur during frame pointer elimination and while reloading addresses.
6298 This case is handled by trying to emit a single insn
6299 to perform the add. If it is not valid, we use a two insn sequence.
6301 Finally, we could be called to handle an 'o' constraint by putting
6302 an address into a register. In that case, we first try to do this
6303 with a named pattern of "reload_load_address". If no such pattern
6304 exists, we just emit a SET insn and hope for the best (it will normally
6305 be valid on machines that use 'o').
6307 This entire process is made complex because reload will never
6308 process the insns we generate here and so we must ensure that
6309 they will fit their constraints and also by the fact that parts of
6310 IN might be being reloaded separately and replaced with spill registers.
6311 Because of this, we are, in some sense, just guessing the right approach
6312 here. The one listed above seems to work.
6314 ??? At some point, this whole thing needs to be rethought. */
6316 if (GET_CODE (in) == PLUS
6317 && ((GET_CODE (XEXP (in, 0)) == REG
6318 && (GET_CODE (XEXP (in, 1)) == REG
6319 || CONSTANT_P (XEXP (in, 1))
6320 || GET_CODE (XEXP (in, 1)) == MEM))
6321 || (GET_CODE (XEXP (in, 0)) == MEM
6322 && CONSTANT_P (XEXP (in, 1)))))
6324 /* We need to compute the sum of what is either a register and a
6325 constant, a register and memory, a hard register and a pseudo
6326 register, or memory and a constant and put it into the reload
6327 register. The best possible way of doing this is if the machine
6328 has a three-operand ADD insn that accepts the required operands.
6330 The simplest approach is to try to generate such an insn and see if it
6331 is recognized and matches its constraints. If so, it can be used.
6333 It might be better not to actually emit the insn unless it is valid,
6334 but we need to pass the insn as an operand to `recog' and
6335 `insn_extract' and it is simpler to emit and then delete the insn if
6336 not valid than to dummy things up. */
6338 rtx op0, op1, tem, insn;
6341 op0 = find_replacement (&XEXP (in, 0));
6342 op1 = find_replacement (&XEXP (in, 1));
6344 /* Since constraint checking is strict, commutativity won't be
6345 checked, so we need to do that here to avoid spurious failure
6346 if the add instruction is two-address and the second operand
6347 of the add is the same as the reload reg, which is frequently
6348 the case. If the insn would be A = B + A, rearrange it so
6349 it will be A = A + B as constrain_operands expects. */
6351 if (GET_CODE (XEXP (in, 1)) == REG
6352 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
6353 tem = op0, op0 = op1, op1 = tem;
6355 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6356 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6358 insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6359 code = recog_memoized (insn);
6363 insn_extract (insn);
6364 /* We want constrain operands to treat this insn strictly in
6365 its validity determination, i.e., the way it would after reload
6367 if (constrain_operands (code, 1))
6371 delete_insns_since (last);
6373 /* If that failed, we must use a conservative two-insn sequence.
6374 use move to copy constant, MEM, or pseudo register to the reload
6375 register since "move" will be able to handle an arbitrary operand,
6376 unlike add which can't, in general. Then add the registers.
6378 If there is another way to do this for a specific machine, a
6379 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6382 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
6383 || (GET_CODE (op1) == REG
6384 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6385 tem = op0, op0 = op1, op1 = tem;
6387 emit_insn (gen_move_insn (reloadreg, op0));
6389 /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
6390 This fixes a problem on the 32K where the stack pointer cannot
6391 be used as an operand of an add insn. */
6393 if (rtx_equal_p (op0, op1))
6396 emit_insn (gen_add2_insn (reloadreg, op1));
6399 #ifdef SECONDARY_MEMORY_NEEDED
6400 /* If we need a memory location to do the move, do it that way. */
6401 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6402 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6403 REGNO_REG_CLASS (REGNO (reloadreg)),
6404 GET_MODE (reloadreg)))
6406 /* Get the memory to use and rewrite both registers to its mode. */
6407 rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type);
6409 if (GET_MODE (loc) != GET_MODE (reloadreg))
6410 reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
6412 if (GET_MODE (loc) != GET_MODE (in))
6413 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6415 emit_insn (gen_move_insn (loc, in));
6416 emit_insn (gen_move_insn (reloadreg, loc));
6420 /* If IN is a simple operand, use gen_move_insn. */
6421 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6422 emit_insn (gen_move_insn (reloadreg, in));
6424 #ifdef HAVE_reload_load_address
6425 else if (HAVE_reload_load_address)
6426 emit_insn (gen_reload_load_address (reloadreg, in));
6429 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
6431 emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6433 /* Return the first insn emitted.
6434 We can not just return get_last_insn, because there may have
6435 been multiple instructions emitted. Also note that gen_move_insn may
6436 emit more than one insn itself, so we can not assume that there is one
6437 insn emitted per emit_insn_before call. */
6439 return last ? NEXT_INSN (last) : get_insns ();
6442 /* Delete a previously made output-reload
6443 whose result we now believe is not needed.
6444 First we double-check.
6446 INSN is the insn now being processed.
6447 OUTPUT_RELOAD_INSN is the insn of the output reload.
6448 J is the reload-number for this insn. */
6451 delete_output_reload (insn, j, output_reload_insn)
6454 rtx output_reload_insn;
6458 /* Get the raw pseudo-register referred to. */
6460 rtx reg = reload_in[j];
6461 while (GET_CODE (reg) == SUBREG)
6462 reg = SUBREG_REG (reg);
6464 /* If the pseudo-reg we are reloading is no longer referenced
6465 anywhere between the store into it and here,
6466 and no jumps or labels intervene, then the value can get
6467 here through the reload reg alone.
6468 Otherwise, give up--return. */
6469 for (i1 = NEXT_INSN (output_reload_insn);
6470 i1 != insn; i1 = NEXT_INSN (i1))
6472 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6474 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6475 && reg_mentioned_p (reg, PATTERN (i1)))
6479 if (cannot_omit_stores[REGNO (reg)])
6482 /* If this insn will store in the pseudo again,
6483 the previous store can be removed. */
6484 if (reload_out[j] == reload_in[j])
6485 delete_insn (output_reload_insn);
6487 /* See if the pseudo reg has been completely replaced
6488 with reload regs. If so, delete the store insn
6489 and forget we had a stack slot for the pseudo. */
6490 else if (reg_n_deaths[REGNO (reg)] == 1
6491 && reg_basic_block[REGNO (reg)] >= 0
6492 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
6496 /* We know that it was used only between here
6497 and the beginning of the current basic block.
6498 (We also know that the last use before INSN was
6499 the output reload we are thinking of deleting, but never mind that.)
6500 Search that range; see if any ref remains. */
6501 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6503 rtx set = single_set (i2);
6505 /* Uses which just store in the pseudo don't count,
6506 since if they are the only uses, they are dead. */
6507 if (set != 0 && SET_DEST (set) == reg)
6509 if (GET_CODE (i2) == CODE_LABEL
6510 || GET_CODE (i2) == JUMP_INSN)
6512 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
6513 && reg_mentioned_p (reg, PATTERN (i2)))
6514 /* Some other ref remains;
6515 we can't do anything. */
6519 /* Delete the now-dead stores into this pseudo. */
6520 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6522 rtx set = single_set (i2);
6524 if (set != 0 && SET_DEST (set) == reg)
6526 if (GET_CODE (i2) == CODE_LABEL
6527 || GET_CODE (i2) == JUMP_INSN)
6531 /* For the debugging info,
6532 say the pseudo lives in this reload reg. */
6533 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
6534 alter_reg (REGNO (reg), -1);
6538 /* Output reload-insns to reload VALUE into RELOADREG.
6539 VALUE is an autoincrement or autodecrement RTX whose operand
6540 is a register or memory location;
6541 so reloading involves incrementing that location.
6543 INC_AMOUNT is the number to increment or decrement by (always positive).
6544 This cannot be deduced from VALUE. */
6547 inc_for_reload (reloadreg, value, inc_amount)
6552 /* REG or MEM to be copied and incremented. */
6553 rtx incloc = XEXP (value, 0);
6554 /* Nonzero if increment after copying. */
6555 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
6561 /* No hard register is equivalent to this register after
6562 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6563 we could inc/dec that register as well (maybe even using it for
6564 the source), but I'm not sure it's worth worrying about. */
6565 if (GET_CODE (incloc) == REG)
6566 reg_last_reload_reg[REGNO (incloc)] = 0;
6568 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
6569 inc_amount = - inc_amount;
6571 inc = GEN_INT (inc_amount);
6573 /* If this is post-increment, first copy the location to the reload reg. */
6575 emit_insn (gen_move_insn (reloadreg, incloc));
6577 /* See if we can directly increment INCLOC. Use a method similar to that
6578 in gen_input_reload. */
6580 last = get_last_insn ();
6581 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
6582 gen_rtx (PLUS, GET_MODE (incloc),
6585 code = recog_memoized (add_insn);
6588 insn_extract (add_insn);
6589 if (constrain_operands (code, 1))
6591 /* If this is a pre-increment and we have incremented the value
6592 where it lives, copy the incremented value to RELOADREG to
6593 be used as an address. */
6596 emit_insn (gen_move_insn (reloadreg, incloc));
6602 delete_insns_since (last);
6604 /* If couldn't do the increment directly, must increment in RELOADREG.
6605 The way we do this depends on whether this is pre- or post-increment.
6606 For pre-increment, copy INCLOC to the reload register, increment it
6607 there, then save back. */
6611 emit_insn (gen_move_insn (reloadreg, incloc));
6612 emit_insn (gen_add2_insn (reloadreg, inc));
6613 emit_insn (gen_move_insn (incloc, reloadreg));
6618 Because this might be a jump insn or a compare, and because RELOADREG
6619 may not be available after the insn in an input reload, we must do
6620 the incrementation before the insn being reloaded for.
6622 We have already copied INCLOC to RELOADREG. Increment the copy in
6623 RELOADREG, save that back, then decrement RELOADREG so it has
6624 the original value. */
6626 emit_insn (gen_add2_insn (reloadreg, inc));
6627 emit_insn (gen_move_insn (incloc, reloadreg));
6628 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
6634 /* Return 1 if we are certain that the constraint-string STRING allows
6635 the hard register REG. Return 0 if we can't be sure of this. */
6638 constraint_accepts_reg_p (string, reg)
6643 int regno = true_regnum (reg);
6646 /* Initialize for first alternative. */
6648 /* Check that each alternative contains `g' or `r'. */
6650 switch (c = *string++)
6653 /* If an alternative lacks `g' or `r', we lose. */
6656 /* If an alternative lacks `g' or `r', we lose. */
6659 /* Initialize for next alternative. */
6664 /* Any general reg wins for this alternative. */
6665 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
6669 /* Any reg in specified class wins for this alternative. */
6671 enum reg_class class = REG_CLASS_FROM_LETTER (c);
6673 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
6679 /* Return the number of places FIND appears within X, but don't count
6680 an occurrence if some SET_DEST is FIND. */
6683 count_occurrences (x, find)
6684 register rtx x, find;
6687 register enum rtx_code code;
6688 register char *format_ptr;
6696 code = GET_CODE (x);
6711 if (SET_DEST (x) == find)
6712 return count_occurrences (SET_SRC (x), find);
6716 format_ptr = GET_RTX_FORMAT (code);
6719 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6721 switch (*format_ptr++)
6724 count += count_occurrences (XEXP (x, i), find);
6728 if (XVEC (x, i) != NULL)
6730 for (j = 0; j < XVECLEN (x, i); j++)
6731 count += count_occurrences (XVECEXP (x, i, j), find);
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